Moved passes to new package

1 files changed, 3 insertions, 22 deletions

diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala
index 18bec9dc..8facc27d 100644
--- a/src/main/scala/firrtl/Compiler.scala
+++ b/src/main/scala/firrtl/Compiler.scala
@@ -22,38 +22,19 @@ object VerilogCompiler extends Compiler {
   // Copied from Stanza implementation
   val passes = Seq(
     CheckHighForm,          
+    Resolve,
     ToWorkingIR,            
     ResolveKinds,
     InferTypes,
-    CheckTypes,
     ResolveGenders,
-    CheckGenders,
-    InferWidths,
-    CheckWidths,
     PullMuxes,
     ExpandConnects,
     RemoveAccesses,
     ExpandWhens,
     CheckInitialization,   
     ConstProp,
-    ResolveKinds,
-    InferTypes,
-    CheckTypes,
-    ResolveGenders,
-    CheckGenders,
-    InferWidths,
-    CheckWidths,
-    LowerTypes,
-    ResolveKinds,
-    InferTypes,
-    CheckTypes,
-    ResolveGenders,
-    CheckGenders,
-    InferWidths,
-    CheckWidths,
-    VerilogWrap,
-    SplitExp,
-    VerilogRename
+    Resolve,
+    LowerTypes
   )
   def run(c: Circuit, w: Writer)
   {