Working on generating SimTop, need to figure out how to split the top-level IO between the sim modules.

1 files changed, 0 insertions, 19 deletions

diff --git a/src/main/scala/Example.scala b/src/main/scala/Example.scala
deleted file mode 100644
index 210a50fb..00000000
--- a/src/main/scala/Example.scala
+++ /dev/null
@@ -1,19 +0,0 @@
-import java.io._
-import firrtl._
-import firrtl.Utils._
-
-object Example
-{
-  // Example use of Scala FIRRTL parser and serialization
-  def main(args: Array[String])
-  {
-    val inputFile = args(0)
-
-    // Parse file
-    val ast = firrtl.Parser.parse(inputFile)
-
-    val writer = new PrintWriter(new File(args(1)))
-    writer.write(ast.serialize) // serialize returns String
-    writer.close()
-  }
-}