diff options
| author | Jack | 2016-02-23 00:57:09 -0800 |
|---|---|---|
| committer | Jack | 2016-02-23 00:57:09 -0800 |
| commit | c48c691e94afe4919c20fa588a9897316c572447 (patch) | |
| tree | 4e2e09a72a7134c4e7cda7830af837342488fa39 /regress/rocket.fir | |
| parent | 6ec6edea9a60f8aab80ee287547160ffaf73aaf7 (diff) | |
Add rocket regression, just runs rocket.fir through Verilog compiler and compares to expected Verilog. Uses ScalaTest. Should be eventually replaced with actual simulation of rocket-chip
Diffstat (limited to 'regress/rocket.fir')
| -rw-r--r-- | regress/rocket.fir | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/regress/rocket.fir b/regress/rocket.fir index debd6af4..adc4bb4d 100644 --- a/regress/rocket.fir +++ b/regress/rocket.fir @@ -17900,7 +17900,7 @@ circuit Top : T_7824 <= T_7823 node T_7826 = eq(reset, UInt<1>("h00")) when T_7826 : - printf(clk, UInt<1>(1), "C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n ", io.host.id, T_7816, wb_valid, wb_reg_pc, T_7818, rf_wdata, rf_wen, T_7819, T_7821, T_7822, T_7824, wb_reg_inst, wb_reg_inst) + printf(clk, UInt<1>(1), "C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", io.host.id, T_7816, wb_valid, wb_reg_pc, T_7818, rf_wdata, rf_wen, T_7819, T_7821, T_7822, T_7824, wb_reg_inst, wb_reg_inst) skip module BTB : |