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authorjackbackrack2015-05-01 12:13:32 -0700
committerjackbackrack2015-05-01 12:13:32 -0700
commit9eba69c6a6a756d0d9fbd6063c8a2e4d77aae570 (patch)
treee9c3edbc813a862674962e3a69c808b0b8215d8a /TODO
parente3bf1ddc8491557e9cff90a6d85725765e733c35 (diff)
parent0a00a6aaa846b695a7a750cf40079d56a9bb94d6 (diff)
merge
Diffstat (limited to 'TODO')
-rw-r--r--TODO10
1 files changed, 9 insertions, 1 deletions
diff --git a/TODO b/TODO
index f7863055..d651b479 100644
--- a/TODO
+++ b/TODO
@@ -6,6 +6,9 @@
Update spec
<>
Add Unit Tests for each pass
+ Separate passes into discrete chunks
+ Push all tests entirely through
+ Check after each pass
======== Update Core ==========
Add source locaters
@@ -53,6 +56,7 @@ Stephen:
pin stephen on an example
Patrick:
move Infer-Widths to before vec expansion?
+ talk about primops
======== Think About ========
<>
@@ -111,10 +115,14 @@ Schedulable
Scheduler
======== Notes ========
-Only for MUXES can width inference go backwards:
+Only for MUXES, AS, and __ can width inference go backwards:
reg r : UInt<5>
r := MUX(p,UInt<?>(1),UInt<?>(2))
==>
reg r : UInt<5>
r := MUX(p,UInt<5>(1),UInt<5>(2))
+
+Which ones
+Treat everything as just bits - the only operators that should exist are ones that emit different bits
+Go through all primops with Andrew