Added a bunch of tests. In the middle of implementing check kinds and check types. Does not compile

1 files changed, 1 insertions, 0 deletions

diff --git a/TODO b/TODO
index 1b5520c8..e2f8b339 100644
--- a/TODO
+++ b/TODO
@@ -108,6 +108,7 @@ Verilog backend - put stuff in posedge clock, not assign statements, for speedup
 Annotate mems with location stuff
 Coverage tests, such as statespace or specific instances (like asserts, sort of)
    check all predicates of whens
+Generate a ROM, and index with cycle counter, and dynamically check any wire on a given cycle
 
 ======== FIRRTL++ =========
 Variable size FIFOs