Updated spec to remove Register,WritePort,ReadPort,RdWrPort,biaccessors

1 files changed, 1 insertions, 0 deletions

diff --git a/TODO b/TODO
index e036ab26..0d86fd34 100644
--- a/TODO
+++ b/TODO
@@ -3,6 +3,7 @@
 ================================================
 
 ======== Current Tasks ========
+Add what is FIRRTL for, and what it is not for
 Add print, assert
 move width inference earlier
    Required for subword assignment, consistent vec width inference, and supporting the new constructs of tobits/frombits