Instances are now male. Reworked lowering pass to be sane. chisel3/ModuleVec.fir doesn't work because incorrecly generated?

1 files changed, 5 insertions, 1 deletions

diff --git a/TODO b/TODO
index fd5685bd..1c84cc96 100644
--- a/TODO
+++ b/TODO
@@ -5,8 +5,9 @@
 ======== Current Tasks ========
 Make instances always male, flip the bundles on declaration
 dlsh,drsh
-move Infer-Widths to before vec expansion?
 Add Unit Tests for each pass
+<>
+Update spec
    
 ======== Update Core ==========
 Add source locaters
@@ -26,6 +27,8 @@ Well-formed high firrtl
    onreset can only handle a register
    all references are declared
    expression in pad must be a ground type
+   node's value cannot be a bundle with a flip in it
+   mems cannot be a bundle with flips
 After adding dynamic assertions, insert bounds check with accessor expansion
 Well-formed low firrtl
    All things only assigned to once
@@ -53,6 +56,7 @@ Patrick:
    move Infer-Widths to before vec expansion?
 
 ======== Think About ========
+<>
 subword accesses
 verilog style guide
 naming for split nodes