Switched to stricter primop width constraints. Implemented Pad. Added some missing primops

1 files changed, 9 insertions, 0 deletions

diff --git a/TODO b/TODO
index bf847a6f..4a099d94 100644
--- a/TODO
+++ b/TODO
@@ -8,8 +8,10 @@ Parser
    Error if incorrectly assign stuff, like use = instead of :=
    Update parser and update tests
 Change all primops to be strict on data widths
+Add pad!
 Make instances always male, flip the bundles on declaration
 dlsh,drsh
+move Infer-Widths to before vec expansion?
    
 ======== Update Core ==========
 Add source locaters
@@ -25,6 +27,8 @@ Well-formed high firrtl
    Subfields are only on bundles, before type inference 
    Can only connect to a Ref or Subfield or Index
    UInt only has positive ints
+   No combinational loops
+   cannot connect to a pad, or a register. only connct to a reference
 After adding dynamic assertions, insert bounds check with accessor expansion
 Well-formed low firrtl
    All things only assigned to once
@@ -32,6 +36,7 @@ Well-formed low firrtl
 ======== Other Passes ========
 constant folding (partial eval) pass
 common subexpression elimination pass
+Verilog backend
 
 ======== Consultations ========
 Stephen:
@@ -52,6 +57,10 @@ Figure out how widths propogate for all updated primops (Adam)
 Add partial bulk connect (Scott, Stephen)
 Add FIFOs to the IR (Palmer)
 Think about supporting generic primops on bundles and vecs (Adam) (wait until front-end more completed)
+Union Types
+Enums?
+Convert to scala
+Firrtl interpreter (in scala)
 
 ======== Update Spec ========
 Add Not to spec