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authorJack Koenig2023-03-15 12:31:40 -0700
committerGitHub2023-03-15 12:31:40 -0700
commit4575518456d8501c3581b195aa7a9e31af19dc38 (patch)
treeca827607a60dc40aa00e9d131811b177eb667938 /README.md
parent6a999e306c81bb6a3276311022349523a576b552 (diff)
parent7262d5a538bd52850b90dd313757d3facb343b4a (diff)
Merge pull request #2613 from chipsalliance/maintenance-mode
Maintenance mode
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+# This project is in maintenance mode
+
+Pull Requests should only be made for bug fixes against versions 1.6 and below (Chisel 3.6 and below).
+
+Please see [CIRCT](https://github.com/llvm/circt) for the next generation FIRRTL compiler.
+Also see [Chisel](https://github.com/chipsalliance/chisel).
+
+---
+
![FIRRTL](https://raw.githubusercontent.com/freechipsproject/firrtl/master/doc/images/firrtl_logo.svg?sanitize=true)
---