diff options
| author | azidar | 2015-07-16 11:10:03 -0700 |
|---|---|---|
| committer | azidar | 2015-07-16 11:10:03 -0700 |
| commit | 98bb81d9d99150a80c77ed8f22d44748a02df628 (patch) | |
| tree | 1146bb50c693786b93c910b6af564abf1576f2b8 /Makefile | |
| parent | b75047591886a8281ca6cba2b2c7daa877cb3ce1 (diff) | |
| parent | 9b6d8514a3be860562d8d524fa425c87d1537e8a (diff) | |
Merge branch 'new-low-firrtl' of github.com:ucb-bar/firrtl into new-low-firrtl
Conflicts:
src/main/stanza/firrtl-ir.stanza
src/main/stanza/passes.stanza
src/main/stanza/verilog.stanza
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -52,7 +52,7 @@ units = ALUTop Datapath Control Core v = $(addsuffix .fir.v, $(units)) $(units): % : - firrtl -X verilog -i test/chisel3/$*.fir -o test/chisel3/$*.fir.v + firrtl -X verilog -i test/chisel3/$*.fir -o test/chisel3/$*.fir.v -p c scp test/chisel3/$*.fir.v adamiz@a5:/scratch/adamiz/firrtl-all/riscv-mini/generated-src/$*.v done: |
