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authorJack2016-02-23 00:57:09 -0800
committerJack2016-02-23 00:57:09 -0800
commitc48c691e94afe4919c20fa588a9897316c572447 (patch)
tree4e2e09a72a7134c4e7cda7830af837342488fa39
parent6ec6edea9a60f8aab80ee287547160ffaf73aaf7 (diff)
Add rocket regression, just runs rocket.fir through Verilog compiler and compares to expected Verilog. Uses ScalaTest. Should be eventually replaced with actual simulation of rocket-chip
Diffstat
-rw-r--r--regress/rocket-golden.v152338
-rw-r--r--regress/rocket.fir2
l---------src/test/resources/regress1
-rw-r--r--src/test/scala/firrtlTests/Regress.scala23
4 files changed, 152363 insertions, 1 deletions
diff --git a/regress/rocket-golden.v b/regress/rocket-golden.v
new file mode 100644
index 00000000..d754d2f5
--- /dev/null
+++ b/regress/rocket-golden.v
@@ -0,0 +1,152338 @@
+module Htif(
+ input clk,
+ input reset,
+ output io_host_clk,
+ output io_host_clk_edge,
+ output io_host_in_ready,
+ input io_host_in_valid,
+ input [15:0] io_host_in_bits,
+ input io_host_out_ready,
+ output io_host_out_valid,
+ output [15:0] io_host_out_bits,
+ output io_host_debug_stats_csr,
+ output io_cpu_0_reset,
+ output io_cpu_0_id,
+ input io_cpu_0_csr_req_ready,
+ output io_cpu_0_csr_req_valid,
+ output io_cpu_0_csr_req_bits_rw,
+ output [11:0] io_cpu_0_csr_req_bits_addr,
+ output [63:0] io_cpu_0_csr_req_bits_data,
+ output io_cpu_0_csr_resp_ready,
+ input io_cpu_0_csr_resp_valid,
+ input [63:0] io_cpu_0_csr_resp_bits,
+ input io_cpu_0_debug_stats_csr,
+ input io_mem_acquire_ready,
+ output io_mem_acquire_valid,
+ output [25:0] io_mem_acquire_bits_addr_block,
+ output [1:0] io_mem_acquire_bits_client_xact_id,
+ output [1:0] io_mem_acquire_bits_addr_beat,
+ output io_mem_acquire_bits_is_builtin_type,
+ output [2:0] io_mem_acquire_bits_a_type,
+ output [16:0] io_mem_acquire_bits_union,
+ output [127:0] io_mem_acquire_bits_data,
+ output io_mem_grant_ready,
+ input io_mem_grant_valid,
+ input [1:0] io_mem_grant_bits_addr_beat,
+ input [1:0] io_mem_grant_bits_client_xact_id,
+ input [3:0] io_mem_grant_bits_manager_xact_id,
+ input io_mem_grant_bits_is_builtin_type,
+ input [3:0] io_mem_grant_bits_g_type,
+ input [127:0] io_mem_grant_bits_data,
+ input io_scr_req_ready,
+ output io_scr_req_valid,
+ output io_scr_req_bits_rw,
+ output [5:0] io_scr_req_bits_addr,
+ output [63:0] io_scr_req_bits_data,
+ output io_scr_resp_ready,
+ input io_scr_resp_valid,
+ input [63:0] io_scr_resp_bits
+);
+ reg [14:0] rx_count;
+ reg [63:0] rx_shifter;
+ wire [47:0] T_1212;
+ wire [63:0] rx_shifter_in;
+ wire [3:0] next_cmd;
+ reg [3:0] cmd;
+ reg [11:0] size;
+ reg [8:0] pos;
+ reg [7:0] seqno;
+ reg [39:0] addr;
+ wire T_1225;
+ wire [15:0] T_1227;
+ wire [14:0] T_1228;
+ wire T_1230;
+ wire [11:0] T_1231;
+ wire [8:0] T_1232;
+ wire [7:0] T_1233;
+ wire [39:0] T_1234;
+ wire [12:0] rx_word_count;
+ wire [1:0] T_1236;
+ wire [1:0] T_1237;
+ wire T_1239;
+ wire rx_word_done;
+ reg [63:0] packet_ram [0:7];
+ wire [63:0] packet_ram_csr_wdata_data;
+ wire [2:0] packet_ram_csr_wdata_addr;
+ wire packet_ram_csr_wdata_en;
+ wire packet_ram_csr_wdata_clk;
+ wire [63:0] packet_ram_T_1411_data;
+ wire [2:0] packet_ram_T_1411_addr;
+ wire packet_ram_T_1411_en;
+ wire packet_ram_T_1411_clk;
+ wire [63:0] packet_ram_T_1419_data;
+ wire [2:0] packet_ram_T_1419_addr;
+ wire packet_ram_T_1419_en;
+ wire packet_ram_T_1419_clk;
+ wire [63:0] packet_ram_T_1734_data;
+ wire [2:0] packet_ram_T_1734_addr;
+ wire packet_ram_T_1734_en;
+ wire packet_ram_T_1734_clk;
+ wire [63:0] packet_ram_T_1249_data;
+ wire [2:0] packet_ram_T_1249_addr;
+ wire packet_ram_T_1249_mask;
+ wire packet_ram_T_1249_en;
+ wire packet_ram_T_1249_clk;
+ wire [63:0] packet_ram_T_1408_data;
+ wire [2:0] packet_ram_T_1408_addr;
+ wire packet_ram_T_1408_mask;
+ wire packet_ram_T_1408_en;
+ wire packet_ram_T_1408_clk;
+ wire [63:0] packet_ram_T_1416_data;
+ wire [2:0] packet_ram_T_1416_addr;
+ wire packet_ram_T_1416_mask;
+ wire packet_ram_T_1416_en;
+ wire packet_ram_T_1416_clk;
+ wire T_1244;
+ wire [2:0] T_1245;
+ wire [3:0] T_1247;
+ wire [2:0] T_1248;
+ wire [11:0] csr_addr;
+ wire [1:0] csr_coreid;
+ wire [2:0] T_1261;
+ wire T_1263;
+ wire [2:0] T_1264;
+ wire T_1266;
+ wire bad_mem_packet;
+ wire T_1268;
+ wire T_1269;
+ wire T_1270;
+ wire T_1271;
+ wire T_1272;
+ wire T_1273;
+ wire T_1275;
+ wire T_1277;
+ wire nack;
+ reg [14:0] tx_count;
+ wire [1:0] tx_subword_count;
+ wire [12:0] tx_word_count;
+ wire [2:0] T_1283;
+ wire [3:0] T_1285;
+ wire [2:0] packet_ram_raddr;
+ wire T_1287;
+ wire [15:0] T_1289;
+ wire [14:0] T_1290;
+ wire T_1292;
+ wire T_1293;
+ wire T_1294;
+ wire T_1295;
+ wire T_1296;
+ wire [2:0] T_1297;
+ wire T_1299;
+ wire T_1300;
+ wire T_1301;
+ wire rx_done;
+ wire T_1304;
+ wire T_1305;
+ wire T_1306;
+ wire T_1307;
+ wire T_1308;
+ wire T_1309;
+ wire T_1310;
+ wire [11:0] tx_size;
+ wire [1:0] T_1313;
+ wire T_1315;
+ wire T_1316;
+ wire T_1317;
+ wire T_1319;
+ wire [2:0] T_1320;
+ wire T_1322;
+ wire T_1323;
+ wire T_1324;
+ wire tx_done;
+ reg [2:0] state;
+ wire T_1336;
+ wire T_1337;
+ wire T_1338;
+ wire T_1339;
+ wire T_1340;
+ reg [1:0] cnt;
+ wire T_1344;
+ wire T_1346;
+ wire [2:0] T_1349;
+ wire [1:0] T_1350;
+ wire [1:0] T_1351;
+ wire cnt_done;
+ wire T_1354;
+ wire [3:0] rx_cmd;
+ wire T_1356;
+ wire T_1357;
+ wire T_1358;
+ wire T_1359;
+ wire T_1360;
+ wire T_1361;
+ wire T_1362;
+ wire [2:0] T_1363;
+ wire [2:0] T_1364;
+ wire [2:0] T_1365;
+ wire T_1366;
+ wire T_1367;
+ wire T_1368;
+ wire T_1369;
+ wire T_1370;
+ wire T_1372;
+ wire T_1373;
+ wire [2:0] T_1374;
+ wire [9:0] T_1376;
+ wire [8:0] T_1377;
+ wire [40:0] T_1379;
+ wire [39:0] T_1380;
+ wire T_1381;
+ wire T_1382;
+ wire T_1383;
+ wire T_1385;
+ wire T_1386;
+ wire [2:0] T_1387;
+ wire [9:0] T_1389;
+ wire [8:0] T_1390;
+ wire [40:0] T_1392;
+ wire [39:0] T_1393;
+ wire T_1394;
+ wire T_1395;
+ wire T_1396;
+ wire T_1399;
+ wire T_1401;
+ wire T_1402;
+ wire [1:0] T_1403;
+ wire T_1405;
+ wire T_1406;
+ wire [2:0] T_1407;
+ wire [63:0] T_1409;
+ wire [2:0] T_1410;
+ wire T_1413;
+ wire T_1414;
+ wire [2:0] T_1415;
+ wire [63:0] T_1417;
+ wire [2:0] T_1418;
+ wire [127:0] mem_req_data;
+ wire [36:0] init_addr;
+ wire T_1422;
+ wire T_1423;
+ wire T_1424;
+ wire T_1425;
+ wire [15:0] GEN_0;
+ wire [15:0] T_1453;
+ wire [3:0] T_1459;
+ wire [1:0] T_1460;
+ wire [5:0] T_1461;
+ wire [1:0] T_1463;
+ wire [4:0] T_1464;
+ wire [16:0] T_1466;
+ wire [16:0] T_1468;
+ wire [3:0] T_1470;
+ wire [1:0] T_1471;
+ wire [5:0] T_1472;
+ wire [5:0] T_1474;
+ wire [5:0] T_1476;
+ wire T_1477;
+ wire [5:0] T_1478;
+ wire T_1479;
+ wire [5:0] T_1480;
+ wire T_1481;
+ wire [5:0] T_1482;
+ wire T_1483;
+ wire [16:0] T_1484;
+ wire T_1485;
+ wire [16:0] T_1486;
+ wire T_1487;
+ wire [16:0] T_1488;
+ wire T_1489;
+ wire [16:0] T_1490;
+ wire [25:0] T_1522_addr_block;
+ wire [1:0] T_1522_client_xact_id;
+ wire [1:0] T_1522_addr_beat;
+ wire T_1522_is_builtin_type;
+ wire [2:0] T_1522_a_type;
+ wire [16:0] T_1522_union;
+ wire [127:0] T_1522_data;
+ wire [3:0] T_1563;
+ wire [5:0] T_1564;
+ wire [9:0] T_1565;
+ wire [5:0] T_1567;
+ wire [8:0] T_1568;
+ wire [1:0] T_1570;
+ wire [1:0] T_1572;
+ wire [3:0] T_1574;
+ wire [5:0] T_1575;
+ wire [9:0] T_1576;
+ wire [5:0] T_1578;
+ wire [5:0] T_1580;
+ wire T_1581;
+ wire [5:0] T_1582;
+ wire T_1583;
+ wire [5:0] T_1584;
+ wire T_1585;
+ wire [9:0] T_1586;
+ wire T_1587;
+ wire [9:0] T_1588;
+ wire T_1589;
+ wire [9:0] T_1590;
+ wire T_1591;
+ wire [9:0] T_1592;
+ wire T_1593;
+ wire [9:0] T_1594;
+ wire [25:0] T_1626_addr_block;
+ wire [1:0] T_1626_client_xact_id;
+ wire [1:0] T_1626_addr_beat;
+ wire T_1626_is_builtin_type;
+ wire [2:0] T_1626_a_type;
+ wire [16:0] T_1626_union;
+ wire [127:0] T_1626_data;
+ wire [25:0] T_1657_addr_block;
+ wire [1:0] T_1657_client_xact_id;
+ wire [1:0] T_1657_addr_beat;
+ wire T_1657_is_builtin_type;
+ wire [2:0] T_1657_a_type;
+ wire [16:0] T_1657_union;
+ wire [127:0] T_1657_data;
+ reg [63:0] csrReadData;
+ reg T_1692;
+ wire T_1694;
+ wire T_1695;
+ wire T_1696;
+ wire T_1698;
+ wire T_1699;
+ wire T_1700;
+ wire T_1701;
+ wire T_1702;
+ wire T_1703;
+ wire T_1705;
+ wire T_1706;
+ wire T_1707;
+ wire T_1708;
+ wire T_1710;
+ wire T_1711;
+ wire T_1712;
+ wire [1:0] T_1713;
+ wire T_1715;
+ wire T_1716;
+ wire [5:0] T_1717;
+ wire T_1718;
+ wire T_1720;
+ wire T_1721;
+ wire T_1722;
+ wire [2:0] tx_cmd;
+ wire [3:0] tx_cmd_ext;
+ wire [47:0] T_1726;
+ wire [15:0] T_1727;
+ wire [63:0] tx_header;
+ wire T_1730;
+ wire T_1731;
+ wire T_1732;
+ wire T_1733;
+ wire [63:0] T_1735;
+ wire [63:0] tx_data;
+ wire T_1737;
+ wire T_1738;
+ wire [1:0] T_1739;
+ wire [5:0] T_1741;
+ wire [63:0] T_1742;
+ reg GEN_1;
+ reg GEN_2;
+ reg GEN_3;
+ assign io_host_clk = GEN_1;
+ assign io_host_clk_edge = GEN_2;
+ assign io_host_in_ready = T_1737;
+ assign io_host_out_valid = T_1738;
+ assign io_host_out_bits = T_1742;
+ assign io_host_debug_stats_csr = io_cpu_0_debug_stats_csr;
+ assign io_cpu_0_reset = T_1692;
+ assign io_cpu_0_id = GEN_3;
+ assign io_cpu_0_csr_req_valid = T_1699;
+ assign io_cpu_0_csr_req_bits_rw = T_1700;
+ assign io_cpu_0_csr_req_bits_addr = csr_addr;
+ assign io_cpu_0_csr_req_bits_data = packet_ram_csr_wdata_data;
+ assign io_cpu_0_csr_resp_ready = 1'h1;
+ assign io_mem_acquire_valid = T_1424;
+ assign io_mem_acquire_bits_addr_block = T_1657_addr_block;
+ assign io_mem_acquire_bits_client_xact_id = T_1657_client_xact_id;
+ assign io_mem_acquire_bits_addr_beat = T_1657_addr_beat;
+ assign io_mem_acquire_bits_is_builtin_type = T_1657_is_builtin_type;
+ assign io_mem_acquire_bits_a_type = T_1657_a_type;
+ assign io_mem_acquire_bits_union = T_1657_union;
+ assign io_mem_acquire_bits_data = T_1657_data;
+ assign io_mem_grant_ready = 1'h1;
+ assign io_scr_req_valid = T_1716;
+ assign io_scr_req_bits_rw = T_1718;
+ assign io_scr_req_bits_addr = T_1717;
+ assign io_scr_req_bits_data = packet_ram_csr_wdata_data;
+ assign io_scr_resp_ready = 1'h1;
+ assign T_1212 = rx_shifter[63:16];
+ assign rx_shifter_in = {io_host_in_bits,T_1212};
+ assign next_cmd = rx_shifter_in[3:0];
+ assign T_1225 = io_host_in_valid & io_host_in_ready;
+ assign T_1227 = rx_count + 1'h1;
+ assign T_1228 = T_1227[14:0];
+ assign T_1230 = rx_count == 2'h3;
+ assign T_1231 = rx_shifter_in[15:4];
+ assign T_1232 = rx_shifter_in[15:7];
+ assign T_1233 = rx_shifter_in[23:16];
+ assign T_1234 = rx_shifter_in[63:24];
+ assign rx_word_count = rx_count[14:2];
+ assign T_1236 = rx_count[1:0];
+ assign T_1237 = ~ T_1236;
+ assign T_1239 = T_1237 == 1'h0;
+ assign rx_word_done = io_host_in_valid & T_1239;
+ assign packet_ram_csr_wdata_addr = 1'h0;
+ assign packet_ram_csr_wdata_en = 1'h1;
+ assign packet_ram_csr_wdata_clk = clk;
+ assign packet_ram_csr_wdata_data = packet_ram[packet_ram_csr_wdata_addr];
+ assign packet_ram_T_1411_addr = T_1410;
+ assign packet_ram_T_1411_en = 1'h1;
+ assign packet_ram_T_1411_clk = clk;
+ assign packet_ram_T_1411_data = packet_ram[packet_ram_T_1411_addr];
+ assign packet_ram_T_1419_addr = T_1418;
+ assign packet_ram_T_1419_en = 1'h1;
+ assign packet_ram_T_1419_clk = clk;
+ assign packet_ram_T_1419_data = packet_ram[packet_ram_T_1419_addr];
+ assign packet_ram_T_1734_addr = packet_ram_raddr;
+ assign packet_ram_T_1734_en = 1'h1;
+ assign packet_ram_T_1734_clk = clk;
+ assign packet_ram_T_1734_data = packet_ram[packet_ram_T_1734_addr];
+ assign packet_ram_T_1249_data = rx_shifter_in;
+ assign packet_ram_T_1249_addr = T_1248;
+ assign packet_ram_T_1249_mask = T_1244 ? 1'h1 : 1'h0;
+ assign packet_ram_T_1249_en = T_1244 ? 1'h1 : 1'h0;
+ assign packet_ram_T_1249_clk = clk;
+ assign packet_ram_T_1408_data = T_1409;
+ assign packet_ram_T_1408_addr = T_1407;
+ assign packet_ram_T_1408_mask = T_1406 ? 1'h1 : 1'h0;
+ assign packet_ram_T_1408_en = T_1406 ? 1'h1 : 1'h0;
+ assign packet_ram_T_1408_clk = clk;
+ assign packet_ram_T_1416_data = T_1417;
+ assign packet_ram_T_1416_addr = T_1415;
+ assign packet_ram_T_1416_mask = T_1414 ? 1'h1 : 1'h0;
+ assign packet_ram_T_1416_en = T_1414 ? 1'h1 : 1'h0;
+ assign packet_ram_T_1416_clk = clk;
+ assign T_1244 = rx_word_done & io_host_in_ready;
+ assign T_1245 = rx_word_count[2:0];
+ assign T_1247 = T_1245 - 1'h1;
+ assign T_1248 = T_1247[2:0];
+ assign csr_addr = addr[11:0];
+ assign csr_coreid = addr[21:20];
+ assign T_1261 = size[2:0];
+ assign T_1263 = T_1261 != 1'h0;
+ assign T_1264 = addr[2:0];
+ assign T_1266 = T_1264 != 1'h0;
+ assign bad_mem_packet = T_1263 | T_1266;
+ assign T_1268 = cmd == 1'h0;
+ assign T_1269 = cmd == 1'h1;
+ assign T_1270 = T_1268 | T_1269;
+ assign T_1271 = cmd == 2'h2;
+ assign T_1272 = cmd == 2'h3;
+ assign T_1273 = T_1271 | T_1272;
+ assign T_1275 = size != 1'h1;
+ assign T_1277 = T_1273 ? T_1275 : 1'h1;
+ assign nack = T_1270 ? bad_mem_packet : T_1277;
+ assign tx_subword_count = tx_count[1:0];
+ assign tx_word_count = tx_count[14:2];
+ assign T_1283 = tx_word_count[2:0];
+ assign T_1285 = T_1283 - 1'h1;
+ assign packet_ram_raddr = T_1285[2:0];
+ assign T_1287 = io_host_out_valid & io_host_out_ready;
+ assign T_1289 = tx_count + 1'h1;
+ assign T_1290 = T_1289[14:0];
+ assign T_1292 = rx_word_count == 1'h0;
+ assign T_1293 = next_cmd != 1'h1;
+ assign T_1294 = next_cmd != 2'h3;
+ assign T_1295 = T_1293 & T_1294;
+ assign T_1296 = rx_word_count == size;
+ assign T_1297 = rx_word_count[2:0];
+ assign T_1299 = T_1297 == 1'h0;
+ assign T_1300 = T_1296 | T_1299;
+ assign T_1301 = T_1292 ? T_1295 : T_1300;
+ assign rx_done = rx_word_done & T_1301;
+ assign T_1304 = nack == 1'h0;
+ assign T_1305 = cmd == 1'h0;
+ assign T_1306 = cmd == 2'h2;
+ assign T_1307 = T_1305 | T_1306;
+ assign T_1308 = cmd == 2'h3;
+ assign T_1309 = T_1307 | T_1308;
+ assign T_1310 = T_1304 & T_1309;
+ assign tx_size = T_1310 ? size : 1'h0;
+ assign T_1313 = ~ tx_subword_count;
+ assign T_1315 = T_1313 == 1'h0;
+ assign T_1316 = io_host_out_ready & T_1315;
+ assign T_1317 = tx_word_count == tx_size;
+ assign T_1319 = tx_word_count > 1'h0;
+ assign T_1320 = ~ packet_ram_raddr;
+ assign T_1322 = T_1320 == 1'h0;
+ assign T_1323 = T_1319 & T_1322;
+ assign T_1324 = T_1317 | T_1323;
+ assign tx_done = T_1316 & T_1324;
+ assign T_1336 = state == 3'h4;
+ assign T_1337 = T_1336 & io_mem_acquire_ready;
+ assign T_1338 = state == 3'h5;
+ assign T_1339 = T_1338 & io_mem_grant_valid;
+ assign T_1340 = T_1337 | T_1339;
+ assign T_1344 = cnt == 2'h3;
+ assign T_1346 = 1'h0 & T_1344;
+ assign T_1349 = cnt + 1'h1;
+ assign T_1350 = T_1349[1:0];
+ assign T_1351 = T_1346 ? 1'h0 : T_1350;
+ assign cnt_done = T_1340 & T_1344;
+ assign T_1354 = rx_word_count == 1'h0;
+ assign rx_cmd = T_1354 ? next_cmd : cmd;
+ assign T_1356 = state == 1'h0;
+ assign T_1357 = T_1356 & rx_done;
+ assign T_1358 = rx_cmd == 1'h0;
+ assign T_1359 = rx_cmd == 1'h1;
+ assign T_1360 = rx_cmd == 2'h2;
+ assign T_1361 = rx_cmd == 2'h3;
+ assign T_1362 = T_1360 | T_1361;
+ assign T_1363 = T_1362 ? 1'h1 : 3'h7;
+ assign T_1364 = T_1359 ? 3'h4 : T_1363;
+ assign T_1365 = T_1358 ? 2'h3 : T_1364;
+ assign T_1366 = state == 3'h4;
+ assign T_1367 = state == 2'h3;
+ assign T_1368 = state == 3'h6;
+ assign T_1369 = T_1368 & io_mem_grant_valid;
+ assign T_1370 = cmd == 1'h0;
+ assign T_1372 = pos == 1'h1;
+ assign T_1373 = T_1370 | T_1372;
+ assign T_1374 = T_1373 ? 3'h7 : 1'h0;
+ assign T_1376 = pos - 1'h1;
+ assign T_1377 = T_1376[8:0];
+ assign T_1379 = addr + 4'h8;
+ assign T_1380 = T_1379[39:0];
+ assign T_1381 = state == 3'h5;
+ assign T_1382 = T_1381 & cnt_done;
+ assign T_1383 = cmd == 1'h0;
+ assign T_1385 = pos == 1'h1;
+ assign T_1386 = T_1383 | T_1385;
+ assign T_1387 = T_1386 ? 3'h7 : 1'h0;
+ assign T_1389 = pos - 1'h1;
+ assign T_1390 = T_1389[8:0];
+ assign T_1392 = addr + 4'h8;
+ assign T_1393 = T_1392[39:0];
+ assign T_1394 = state == 3'h7;
+ assign T_1395 = T_1394 & tx_done;
+ assign T_1396 = tx_word_count == tx_size;
+ assign T_1399 = cmd == 1'h0;
+ assign T_1401 = pos != 1'h0;
+ assign T_1402 = T_1399 & T_1401;
+ assign T_1403 = T_1402 ? 2'h3 : 1'h0;
+ assign T_1405 = state == 3'h5;
+ assign T_1406 = T_1405 & io_mem_grant_valid;
+ assign T_1407 = {io_mem_grant_bits_addr_beat,1'h0};
+ assign T_1409 = io_mem_grant_bits_data[63:0];
+ assign T_1410 = {cnt,1'h0};
+ assign T_1413 = state == 3'h5;
+ assign T_1414 = T_1413 & io_mem_grant_valid;
+ assign T_1415 = {io_mem_grant_bits_addr_beat,1'h1};
+ assign T_1417 = io_mem_grant_bits_data[127:64];
+ assign T_1418 = {cnt,1'h1};
+ assign mem_req_data = {packet_ram_T_1419_data,packet_ram_T_1411_data};
+ assign init_addr = addr[39:3];
+ assign T_1422 = state == 2'h3;
+ assign T_1423 = state == 3'h4;
+ assign T_1424 = T_1422 | T_1423;
+ assign T_1425 = cmd == 1'h1;
+ assign GEN_0 = $signed(16'hffff);
+ assign T_1453 = $unsigned(GEN_0);
+ assign T_1459 = {1'h0,3'h7};
+ assign T_1460 = {1'h0,1'h1};
+ assign T_1461 = {T_1459,T_1460};
+ assign T_1463 = {1'h0,1'h1};
+ assign T_1464 = {3'h7,T_1463};
+ assign T_1466 = {T_1453,1'h1};
+ assign T_1468 = {T_1453,1'h1};
+ assign T_1470 = {1'h0,3'h7};
+ assign T_1471 = {1'h0,1'h1};
+ assign T_1472 = {T_1470,T_1471};
+ assign T_1474 = {5'h0,1'h1};
+ assign T_1476 = {5'h1,1'h1};
+ assign T_1477 = 3'h6 == 3'h3;
+ assign T_1478 = T_1477 ? T_1476 : 1'h0;
+ assign T_1479 = 3'h5 == 3'h3;
+ assign T_1480 = T_1479 ? T_1474 : T_1478;
+ assign T_1481 = 3'h4 == 3'h3;
+ assign T_1482 = T_1481 ? T_1472 : T_1480;
+ assign T_1483 = 3'h3 == 3'h3;
+ assign T_1484 = T_1483 ? T_1468 : T_1482;
+ assign T_1485 = 3'h2 == 3'h3;
+ assign T_1486 = T_1485 ? T_1466 : T_1484;
+ assign T_1487 = 3'h1 == 3'h3;
+ assign T_1488 = T_1487 ? T_1464 : T_1486;
+ assign T_1489 = 3'h0 == 3'h3;
+ assign T_1490 = T_1489 ? T_1461 : T_1488;
+ assign T_1522_addr_block = init_addr;
+ assign T_1522_client_xact_id = 1'h0;
+ assign T_1522_addr_beat = cnt;
+ assign T_1522_is_builtin_type = 1'h1;
+ assign T_1522_a_type = 3'h3;
+ assign T_1522_union = T_1490;
+ assign T_1522_data = mem_req_data;
+ assign T_1563 = {1'h0,3'h7};
+ assign T_1564 = {5'h0,1'h1};
+ assign T_1565 = {T_1563,T_1564};
+ assign T_1567 = {5'h0,1'h1};
+ assign T_1568 = {3'h7,T_1567};
+ assign T_1570 = {1'h0,1'h1};
+ assign T_1572 = {1'h0,1'h1};
+ assign T_1574 = {1'h0,3'h7};
+ assign T_1575 = {5'h0,1'h1};
+ assign T_1576 = {T_1574,T_1575};
+ assign T_1578 = {5'h0,1'h1};
+ assign T_1580 = {5'h1,1'h1};
+ assign T_1581 = 3'h6 == 3'h1;
+ assign T_1582 = T_1581 ? T_1580 : 1'h0;
+ assign T_1583 = 3'h5 == 3'h1;
+ assign T_1584 = T_1583 ? T_1578 : T_1582;
+ assign T_1585 = 3'h4 == 3'h1;
+ assign T_1586 = T_1585 ? T_1576 : T_1584;
+ assign T_1587 = 3'h3 == 3'h1;
+ assign T_1588 = T_1587 ? T_1572 : T_1586;
+ assign T_1589 = 3'h2 == 3'h1;
+ assign T_1590 = T_1589 ? T_1570 : T_1588;
+ assign T_1591 = 3'h1 == 3'h1;
+ assign T_1592 = T_1591 ? T_1568 : T_1590;
+ assign T_1593 = 3'h0 == 3'h1;
+ assign T_1594 = T_1593 ? T_1565 : T_1592;
+ assign T_1626_addr_block = init_addr;
+ assign T_1626_client_xact_id = 1'h0;
+ assign T_1626_addr_beat = 1'h0;
+ assign T_1626_is_builtin_type = 1'h1;
+ assign T_1626_a_type = 3'h1;
+ assign T_1626_union = T_1594;
+ assign T_1626_data = 1'h0;
+ assign T_1657_addr_block = T_1425 ? T_1522_addr_block : T_1626_addr_block;
+ assign T_1657_client_xact_id = T_1425 ? T_1522_client_xact_id : T_1626_client_xact_id;
+ assign T_1657_addr_beat = T_1425 ? T_1522_addr_beat : T_1626_addr_beat;
+ assign T_1657_is_builtin_type = T_1425 ? T_1522_is_builtin_type : T_1626_is_builtin_type;
+ assign T_1657_a_type = T_1425 ? T_1522_a_type : T_1626_a_type;
+ assign T_1657_union = T_1425 ? T_1522_union : T_1626_union;
+ assign T_1657_data = T_1425 ? T_1522_data : T_1626_data;
+ assign T_1694 = csr_coreid == 1'h0;
+ assign T_1695 = state == 1'h1;
+ assign T_1696 = T_1695 & T_1694;
+ assign T_1698 = csr_addr != 11'h782;
+ assign T_1699 = T_1696 & T_1698;
+ assign T_1700 = cmd == 2'h3;
+ assign T_1701 = io_cpu_0_csr_req_ready & io_cpu_0_csr_req_valid;
+ assign T_1702 = state == 1'h1;
+ assign T_1703 = T_1702 & T_1694;
+ assign T_1705 = csr_addr == 11'h782;
+ assign T_1706 = T_1703 & T_1705;
+ assign T_1707 = cmd == 2'h3;
+ assign T_1708 = packet_ram_csr_wdata_data[0];
+ assign T_1710 = state == 2'h2;
+ assign T_1711 = T_1710 & io_cpu_0_csr_resp_valid;
+ assign T_1712 = state == 1'h1;
+ assign T_1713 = ~ csr_coreid;
+ assign T_1715 = T_1713 == 1'h0;
+ assign T_1716 = T_1712 & T_1715;
+ assign T_1717 = addr[5:0];
+ assign T_1718 = cmd == 2'h3;
+ assign T_1720 = io_scr_req_ready & io_scr_req_valid;
+ assign T_1721 = state == 2'h2;
+ assign T_1722 = T_1721 & io_scr_resp_valid;
+ assign tx_cmd = nack ? 3'h5 : 3'h4;
+ assign tx_cmd_ext = {1'h0,tx_cmd};
+ assign T_1726 = {addr,seqno};
+ assign T_1727 = {tx_size,tx_cmd_ext};
+ assign tx_header = {T_1726,T_1727};
+ assign T_1730 = tx_word_count == 1'h0;
+ assign T_1731 = cmd == 2'h2;
+ assign T_1732 = cmd == 2'h3;
+ assign T_1733 = T_1731 | T_1732;
+ assign T_1735 = T_1733 ? csrReadData : packet_ram_T_1734_data;
+ assign tx_data = T_1730 ? tx_header : T_1735;
+ assign T_1737 = state == 1'h0;
+ assign T_1738 = state == 3'h7;
+ assign T_1739 = tx_count[1:0];
+ assign T_1741 = {T_1739,4'h0};
+ assign T_1742 = tx_data >> T_1741;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ rx_count = {1{$random}};
+ rx_shifter = {2{$random}};
+ cmd = {1{$random}};
+ size = {1{$random}};
+ pos = {1{$random}};
+ seqno = {1{$random}};
+ addr = {2{$random}};
+ for (initvar = 0; initvar < 8; initvar = initvar+1)
+ packet_ram[initvar] = {2{$random}};
+ tx_count = {1{$random}};
+ state = {1{$random}};
+ cnt = {1{$random}};
+ csrReadData = {2{$random}};
+ T_1692 = {1{$random}};
+ GEN_1 = {1{$random}};
+ GEN_2 = {1{$random}};
+ GEN_3 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ rx_count <= 15'h0;
+ end else begin
+ if(T_1395) begin
+ if(T_1396) begin
+ rx_count <= 1'h0;
+ end else begin
+ if(T_1225) begin
+ rx_count <= T_1228;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1225) begin
+ rx_count <= T_1228;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1225) begin
+ rx_shifter <= rx_shifter_in;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1225) begin
+ if(T_1230) begin
+ cmd <= next_cmd;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1225) begin
+ if(T_1230) begin
+ size <= T_1231;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1382) begin
+ pos <= T_1390;
+ end else begin
+ if(T_1369) begin
+ pos <= T_1377;
+ end else begin
+ if(T_1225) begin
+ if(T_1230) begin
+ pos <= T_1232;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1225) begin
+ if(T_1230) begin
+ seqno <= T_1233;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1382) begin
+ addr <= T_1393;
+ end else begin
+ if(T_1369) begin
+ addr <= T_1380;
+ end else begin
+ if(T_1225) begin
+ if(T_1230) begin
+ addr <= T_1234;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ if(reset) begin
+ tx_count <= 15'h0;
+ end else begin
+ if(T_1395) begin
+ if(T_1396) begin
+ tx_count <= 1'h0;
+ end else begin
+ if(T_1287) begin
+ tx_count <= T_1290;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1287) begin
+ tx_count <= T_1290;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1722) begin
+ state <= 3'h7;
+ end else begin
+ if(T_1720) begin
+ state <= 2'h2;
+ end else begin
+ if(T_1711) begin
+ state <= 3'h7;
+ end else begin
+ if(T_1706) begin
+ state <= 3'h7;
+ end else begin
+ if(T_1701) begin
+ state <= 2'h2;
+ end else begin
+ if(T_1395) begin
+ state <= T_1403;
+ end else begin
+ if(T_1382) begin
+ state <= T_1387;
+ end else begin
+ if(T_1369) begin
+ state <= T_1374;
+ end else begin
+ if(T_1367) begin
+ if(io_mem_acquire_ready) begin
+ state <= 3'h5;
+ end else begin
+ if(T_1366) begin
+ if(cnt_done) begin
+ state <= 3'h6;
+ end else begin
+ if(T_1357) begin
+ state <= T_1365;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1357) begin
+ state <= T_1365;
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1366) begin
+ if(cnt_done) begin
+ state <= 3'h6;
+ end else begin
+ if(T_1357) begin
+ state <= T_1365;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1357) begin
+ state <= T_1365;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ if(reset) begin
+ cnt <= 2'h0;
+ end else begin
+ if(T_1340) begin
+ cnt <= T_1351;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1722) begin
+ csrReadData <= io_scr_resp_bits;
+ end else begin
+ if(T_1711) begin
+ csrReadData <= io_cpu_0_csr_resp_bits;
+ end else begin
+ if(T_1706) begin
+ csrReadData <= T_1692;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ if(reset) begin
+ T_1692 <= 1'h1;
+ end else begin
+ if(T_1706) begin
+ if(T_1707) begin
+ T_1692 <= T_1708;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ always @(posedge packet_ram_T_1249_clk) begin
+ if(packet_ram_T_1249_en & packet_ram_T_1249_mask) begin
+ packet_ram[packet_ram_T_1249_addr] <= packet_ram_T_1249_data;
+ end
+ end
+ always @(posedge packet_ram_T_1408_clk) begin
+ if(packet_ram_T_1408_en & packet_ram_T_1408_mask) begin
+ packet_ram[packet_ram_T_1408_addr] <= packet_ram_T_1408_data;
+ end
+ end
+ always @(posedge packet_ram_T_1416_clk) begin
+ if(packet_ram_T_1416_en & packet_ram_T_1416_mask) begin
+ packet_ram[packet_ram_T_1416_addr] <= packet_ram_T_1416_data;
+ end
+ end
+endmodule
+module ClientTileLinkIOWrapper(
+ input clk,
+ input reset,
+ output io_in_acquire_ready,
+ input io_in_acquire_valid,
+ input [25:0] io_in_acquire_bits_addr_block,
+ input [1:0] io_in_acquire_bits_client_xact_id,
+ input [1:0] io_in_acquire_bits_addr_beat,
+ input io_in_acquire_bits_is_builtin_type,
+ input [2:0] io_in_acquire_bits_a_type,
+ input [16:0] io_in_acquire_bits_union,
+ input [127:0] io_in_acquire_bits_data,
+ input io_in_grant_ready,
+ output io_in_grant_valid,
+ output [1:0] io_in_grant_bits_addr_beat,
+ output [1:0] io_in_grant_bits_client_xact_id,
+ output [3:0] io_in_grant_bits_manager_xact_id,
+ output io_in_grant_bits_is_builtin_type,
+ output [3:0] io_in_grant_bits_g_type,
+ output [127:0] io_in_grant_bits_data,
+ input io_out_acquire_ready,
+ output io_out_acquire_valid,
+ output [25:0] io_out_acquire_bits_addr_block,
+ output [1:0] io_out_acquire_bits_client_xact_id,
+ output [1:0] io_out_acquire_bits_addr_beat,
+ output io_out_acquire_bits_is_builtin_type,
+ output [2:0] io_out_acquire_bits_a_type,
+ output [16:0] io_out_acquire_bits_union,
+ output [127:0] io_out_acquire_bits_data,
+ output io_out_grant_ready,
+ input io_out_grant_valid,
+ input [1:0] io_out_grant_bits_addr_beat,
+ input [1:0] io_out_grant_bits_client_xact_id,
+ input [3:0] io_out_grant_bits_manager_xact_id,
+ input io_out_grant_bits_is_builtin_type,
+ input [3:0] io_out_grant_bits_g_type,
+ input [127:0] io_out_grant_bits_data,
+ output io_out_probe_ready,
+ input io_out_probe_valid,
+ input [25:0] io_out_probe_bits_addr_block,
+ input [1:0] io_out_probe_bits_p_type,
+ input io_out_release_ready,
+ output io_out_release_valid,
+ output [1:0] io_out_release_bits_addr_beat,
+ output [25:0] io_out_release_bits_addr_block,
+ output [1:0] io_out_release_bits_client_xact_id,
+ output io_out_release_bits_voluntary,
+ output [2:0] io_out_release_bits_r_type,
+ output [127:0] io_out_release_bits_data
+);
+ reg [1:0] GEN_0;
+ reg [25:0] GEN_1;
+ reg [1:0] GEN_2;
+ reg GEN_3;
+ reg [2:0] GEN_4;
+ reg [127:0] GEN_5;
+ assign io_in_acquire_ready = io_out_acquire_ready;
+ assign io_in_grant_valid = io_out_grant_valid;
+ assign io_in_grant_bits_addr_beat = io_out_grant_bits_addr_beat;
+ assign io_in_grant_bits_client_xact_id = io_out_grant_bits_client_xact_id;
+ assign io_in_grant_bits_manager_xact_id = io_out_grant_bits_manager_xact_id;
+ assign io_in_grant_bits_is_builtin_type = io_out_grant_bits_is_builtin_type;
+ assign io_in_grant_bits_g_type = io_out_grant_bits_g_type;
+ assign io_in_grant_bits_data = io_out_grant_bits_data;
+ assign io_out_acquire_valid = io_in_acquire_valid;
+ assign io_out_acquire_bits_addr_block = io_in_acquire_bits_addr_block;
+ assign io_out_acquire_bits_client_xact_id = io_in_acquire_bits_client_xact_id;
+ assign io_out_acquire_bits_addr_beat = io_in_acquire_bits_addr_beat;
+ assign io_out_acquire_bits_is_builtin_type = io_in_acquire_bits_is_builtin_type;
+ assign io_out_acquire_bits_a_type = io_in_acquire_bits_a_type;
+ assign io_out_acquire_bits_union = io_in_acquire_bits_union;
+ assign io_out_acquire_bits_data = io_in_acquire_bits_data;
+ assign io_out_grant_ready = io_in_grant_ready;
+ assign io_out_probe_ready = 1'h1;
+ assign io_out_release_valid = 1'h0;
+ assign io_out_release_bits_addr_beat = GEN_0;
+ assign io_out_release_bits_addr_block = GEN_1;
+ assign io_out_release_bits_client_xact_id = GEN_2;
+ assign io_out_release_bits_voluntary = GEN_3;
+ assign io_out_release_bits_r_type = GEN_4;
+ assign io_out_release_bits_data = GEN_5;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ GEN_0 = {1{$random}};
+ GEN_1 = {1{$random}};
+ GEN_2 = {1{$random}};
+ GEN_3 = {1{$random}};
+ GEN_4 = {1{$random}};
+ GEN_5 = {4{$random}};
+ end
+`endif
+endmodule
+module FinishQueue(
+ input clk,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [3:0] io_enq_bits_fin_manager_xact_id,
+ input [1:0] io_enq_bits_dst,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [3:0] io_deq_bits_fin_manager_xact_id,
+ output [1:0] io_deq_bits_dst,
+ output [1:0] io_count
+);
+ reg [3:0] T_877_fin_manager_xact_id [0:1];
+ wire [3:0] T_877_fin_manager_xact_id_T_1025_data;
+ wire T_877_fin_manager_xact_id_T_1025_addr;
+ wire T_877_fin_manager_xact_id_T_1025_en;
+ wire T_877_fin_manager_xact_id_T_1025_clk;
+ wire [3:0] T_877_fin_manager_xact_id_T_900_data;
+ wire T_877_fin_manager_xact_id_T_900_addr;
+ wire T_877_fin_manager_xact_id_T_900_mask;
+ wire T_877_fin_manager_xact_id_T_900_en;
+ wire T_877_fin_manager_xact_id_T_900_clk;
+ reg [1:0] T_877_dst [0:1];
+ wire [1:0] T_877_dst_T_1025_data;
+ wire T_877_dst_T_1025_addr;
+ wire T_877_dst_T_1025_en;
+ wire T_877_dst_T_1025_clk;
+ wire [1:0] T_877_dst_T_900_data;
+ wire T_877_dst_T_900_addr;
+ wire T_877_dst_T_900_mask;
+ wire T_877_dst_T_900_en;
+ wire T_877_dst_T_900_clk;
+ reg T_879;
+ reg T_881;
+ reg T_883;
+ wire T_884;
+ wire T_886;
+ wire T_887;
+ wire T_888;
+ wire T_890;
+ wire T_891;
+ wire T_892;
+ wire T_894;
+ wire T_895;
+ wire T_896;
+ wire T_898;
+ wire T_899;
+ wire T_997;
+ wire T_999;
+ wire [1:0] T_1002;
+ wire T_1003;
+ wire T_1004;
+ wire T_1006;
+ wire T_1008;
+ wire [1:0] T_1011;
+ wire T_1012;
+ wire T_1013;
+ wire T_1014;
+ wire T_1016;
+ wire T_1018;
+ wire T_1019;
+ wire T_1021;
+ wire T_1023;
+ wire T_1024;
+ wire [3:0] T_1121_fin_manager_xact_id;
+ wire [1:0] T_1121_dst;
+ wire [1:0] T_1217;
+ wire T_1218;
+ wire T_1219;
+ wire [1:0] T_1220;
+ assign io_enq_ready = T_1024;
+ assign io_deq_valid = T_1019;
+ assign io_deq_bits_fin_manager_xact_id = T_1121_fin_manager_xact_id;
+ assign io_deq_bits_dst = T_1121_dst;
+ assign io_count = T_1220;
+ assign T_877_fin_manager_xact_id_T_1025_addr = T_881;
+ assign T_877_fin_manager_xact_id_T_1025_en = 1'h1;
+ assign T_877_fin_manager_xact_id_T_1025_clk = clk;
+ assign T_877_fin_manager_xact_id_T_1025_data = T_877_fin_manager_xact_id[T_877_fin_manager_xact_id_T_1025_addr];
+ assign T_877_fin_manager_xact_id_T_900_data = io_enq_bits_fin_manager_xact_id;
+ assign T_877_fin_manager_xact_id_T_900_addr = T_879;
+ assign T_877_fin_manager_xact_id_T_900_mask = T_895 ? 1'h1 : 1'h0;
+ assign T_877_fin_manager_xact_id_T_900_en = T_895 ? 1'h1 : 1'h0;
+ assign T_877_fin_manager_xact_id_T_900_clk = clk;
+ assign T_877_dst_T_1025_addr = T_881;
+ assign T_877_dst_T_1025_en = 1'h1;
+ assign T_877_dst_T_1025_clk = clk;
+ assign T_877_dst_T_1025_data = T_877_dst[T_877_dst_T_1025_addr];
+ assign T_877_dst_T_900_data = io_enq_bits_dst;
+ assign T_877_dst_T_900_addr = T_879;
+ assign T_877_dst_T_900_mask = T_895 ? 1'h1 : 1'h0;
+ assign T_877_dst_T_900_en = T_895 ? 1'h1 : 1'h0;
+ assign T_877_dst_T_900_clk = clk;
+ assign T_884 = T_879 == T_881;
+ assign T_886 = T_883 == 1'h0;
+ assign T_887 = T_884 & T_886;
+ assign T_888 = T_884 & T_883;
+ assign T_890 = 1'h0 & T_887;
+ assign T_891 = T_890 & io_deq_ready;
+ assign T_892 = io_enq_ready & io_enq_valid;
+ assign T_894 = T_891 == 1'h0;
+ assign T_895 = T_892 & T_894;
+ assign T_896 = io_deq_ready & io_deq_valid;
+ assign T_898 = T_891 == 1'h0;
+ assign T_899 = T_896 & T_898;
+ assign T_997 = T_879 == 1'h1;
+ assign T_999 = 1'h0 & T_997;
+ assign T_1002 = T_879 + 1'h1;
+ assign T_1003 = T_1002[0:0];
+ assign T_1004 = T_999 ? 1'h0 : T_1003;
+ assign T_1006 = T_881 == 1'h1;
+ assign T_1008 = 1'h0 & T_1006;
+ assign T_1011 = T_881 + 1'h1;
+ assign T_1012 = T_1011[0:0];
+ assign T_1013 = T_1008 ? 1'h0 : T_1012;
+ assign T_1014 = T_895 != T_899;
+ assign T_1016 = T_887 == 1'h0;
+ assign T_1018 = 1'h0 & io_enq_valid;
+ assign T_1019 = T_1016 | T_1018;
+ assign T_1021 = T_888 == 1'h0;
+ assign T_1023 = 1'h0 & io_deq_ready;
+ assign T_1024 = T_1021 | T_1023;
+ assign T_1121_fin_manager_xact_id = T_890 ? io_enq_bits_fin_manager_xact_id : T_877_fin_manager_xact_id_T_1025_data;
+ assign T_1121_dst = T_890 ? io_enq_bits_dst : T_877_dst_T_1025_data;
+ assign T_1217 = T_879 - T_881;
+ assign T_1218 = T_1217[0:0];
+ assign T_1219 = T_883 & T_884;
+ assign T_1220 = {T_1219,T_1218};
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ T_877_fin_manager_xact_id[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ T_877_dst[initvar] = {1{$random}};
+ T_879 = {1{$random}};
+ T_881 = {1{$random}};
+ T_883 = {1{$random}};
+ end
+`endif
+ always @(posedge T_877_fin_manager_xact_id_T_900_clk) begin
+ if(T_877_fin_manager_xact_id_T_900_en & T_877_fin_manager_xact_id_T_900_mask) begin
+ T_877_fin_manager_xact_id[T_877_fin_manager_xact_id_T_900_addr] <= T_877_fin_manager_xact_id_T_900_data;
+ end
+ end
+ always @(posedge T_877_dst_T_900_clk) begin
+ if(T_877_dst_T_900_en & T_877_dst_T_900_mask) begin
+ T_877_dst[T_877_dst_T_900_addr] <= T_877_dst_T_900_data;
+ end
+ end
+ always @(posedge clk) begin
+ if(reset) begin
+ T_879 <= 1'h0;
+ end else begin
+ if(T_895) begin
+ T_879 <= T_1004;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_881 <= 1'h0;
+ end else begin
+ if(T_899) begin
+ T_881 <= T_1013;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_883 <= 1'h0;
+ end else begin
+ if(T_1014) begin
+ T_883 <= T_895;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module FinishUnit(
+ input clk,
+ input reset,
+ output io_grant_ready,
+ input io_grant_valid,
+ input [1:0] io_grant_bits_header_src,
+ input [1:0] io_grant_bits_header_dst,
+ input [1:0] io_grant_bits_payload_addr_beat,
+ input [1:0] io_grant_bits_payload_client_xact_id,
+ input [3:0] io_grant_bits_payload_manager_xact_id,
+ input io_grant_bits_payload_is_builtin_type,
+ input [3:0] io_grant_bits_payload_g_type,
+ input [127:0] io_grant_bits_payload_data,
+ input io_refill_ready,
+ output io_refill_valid,
+ output [1:0] io_refill_bits_addr_beat,
+ output [1:0] io_refill_bits_client_xact_id,
+ output [3:0] io_refill_bits_manager_xact_id,
+ output io_refill_bits_is_builtin_type,
+ output [3:0] io_refill_bits_g_type,
+ output [127:0] io_refill_bits_data,
+ input io_finish_ready,
+ output io_finish_valid,
+ output [1:0] io_finish_bits_header_src,
+ output [1:0] io_finish_bits_header_dst,
+ output [3:0] io_finish_bits_payload_manager_xact_id,
+ output io_ready
+);
+ wire T_1178;
+ wire [2:0] T_1183_0;
+ wire T_1186;
+ wire T_1188;
+ wire T_1190_0;
+ wire T_1190_1;
+ wire T_1194;
+ wire T_1195;
+ wire T_1197;
+ wire T_1198;
+ wire T_1199;
+ wire T_1200;
+ wire T_1201;
+ reg [1:0] T_1203;
+ wire T_1205;
+ wire T_1207;
+ wire [2:0] T_1210;
+ wire [1:0] T_1211;
+ wire [1:0] T_1212;
+ wire T_1213;
+ wire [1:0] T_1214;
+ wire T_1215;
+ wire T_1312_clk;
+ wire T_1312_reset;
+ wire T_1312_io_enq_ready;
+ wire T_1312_io_enq_valid;
+ wire [3:0] T_1312_io_enq_bits_fin_manager_xact_id;
+ wire [1:0] T_1312_io_enq_bits_dst;
+ wire T_1312_io_deq_ready;
+ wire T_1312_io_deq_valid;
+ wire [3:0] T_1312_io_deq_bits_fin_manager_xact_id;
+ wire [1:0] T_1312_io_deq_bits_dst;
+ wire [1:0] T_1312_io_count;
+ wire T_1313;
+ wire T_1316;
+ wire T_1318;
+ wire T_1319;
+ wire T_1321;
+ wire T_1322;
+ wire T_1323;
+ wire [2:0] T_1327_0;
+ wire T_1330;
+ wire T_1332;
+ wire T_1334_0;
+ wire T_1334_1;
+ wire T_1338;
+ wire T_1339;
+ wire T_1341;
+ wire T_1342;
+ wire T_1343;
+ wire T_1344;
+ wire T_1346;
+ wire T_1347;
+ wire T_1348;
+ wire [3:0] T_1374_manager_xact_id;
+ wire T_1402;
+ wire T_1404;
+ wire T_1405;
+ wire T_1407;
+ wire T_1408;
+ wire T_1410;
+ wire T_1411;
+ wire T_1412;
+ wire T_1415;
+ wire T_1417;
+ wire T_1418;
+ wire T_1420;
+ wire T_1421;
+ wire T_1423;
+ wire T_1424;
+ wire T_1425;
+ FinishQueue T_1312 (
+ .clk(T_1312_clk),
+ .reset(T_1312_reset),
+ .io_enq_ready(T_1312_io_enq_ready),
+ .io_enq_valid(T_1312_io_enq_valid),
+ .io_enq_bits_fin_manager_xact_id(T_1312_io_enq_bits_fin_manager_xact_id),
+ .io_enq_bits_dst(T_1312_io_enq_bits_dst),
+ .io_deq_ready(T_1312_io_deq_ready),
+ .io_deq_valid(T_1312_io_deq_valid),
+ .io_deq_bits_fin_manager_xact_id(T_1312_io_deq_bits_fin_manager_xact_id),
+ .io_deq_bits_dst(T_1312_io_deq_bits_dst),
+ .io_count(T_1312_io_count)
+ );
+ assign io_grant_ready = T_1425;
+ assign io_refill_valid = T_1412;
+ assign io_refill_bits_addr_beat = io_grant_bits_payload_addr_beat;
+ assign io_refill_bits_client_xact_id = io_grant_bits_payload_client_xact_id;
+ assign io_refill_bits_manager_xact_id = io_grant_bits_payload_manager_xact_id;
+ assign io_refill_bits_is_builtin_type = io_grant_bits_payload_is_builtin_type;
+ assign io_refill_bits_g_type = io_grant_bits_payload_g_type;
+ assign io_refill_bits_data = io_grant_bits_payload_data;
+ assign io_finish_valid = T_1312_io_deq_valid;
+ assign io_finish_bits_header_src = 1'h0;
+ assign io_finish_bits_header_dst = T_1312_io_deq_bits_dst;
+ assign io_finish_bits_payload_manager_xact_id = T_1312_io_deq_bits_fin_manager_xact_id;
+ assign io_ready = T_1312_io_enq_ready;
+ assign T_1178 = io_grant_ready & io_grant_valid;
+ assign T_1183_0 = 3'h5;
+ assign T_1186 = T_1183_0 == io_grant_bits_payload_g_type;
+ assign T_1188 = 1'h0 | T_1186;
+ assign T_1190_0 = 1'h0;
+ assign T_1190_1 = 1'h1;
+ assign T_1194 = T_1190_0 == io_grant_bits_payload_g_type;
+ assign T_1195 = T_1190_1 == io_grant_bits_payload_g_type;
+ assign T_1197 = 1'h0 | T_1194;
+ assign T_1198 = T_1197 | T_1195;
+ assign T_1199 = io_grant_bits_payload_is_builtin_type ? T_1188 : T_1198;
+ assign T_1200 = 1'h1 & T_1199;
+ assign T_1201 = T_1178 & T_1200;
+ assign T_1205 = T_1203 == 2'h3;
+ assign T_1207 = 1'h0 & T_1205;
+ assign T_1210 = T_1203 + 1'h1;
+ assign T_1211 = T_1210[1:0];
+ assign T_1212 = T_1207 ? 1'h0 : T_1211;
+ assign T_1213 = T_1201 & T_1205;
+ assign T_1214 = T_1200 ? T_1203 : 1'h0;
+ assign T_1215 = T_1200 ? T_1213 : T_1178;
+ assign T_1312_clk = clk;
+ assign T_1312_reset = reset;
+ assign T_1312_io_enq_valid = T_1348;
+ assign T_1312_io_enq_bits_fin_manager_xact_id = T_1374_manager_xact_id;
+ assign T_1312_io_enq_bits_dst = io_grant_bits_header_src;
+ assign T_1312_io_deq_ready = io_finish_ready;
+ assign T_1313 = io_grant_ready & io_grant_valid;
+ assign T_1316 = 1'h0 == 1'h0;
+ assign T_1318 = io_grant_bits_payload_g_type == 3'h0;
+ assign T_1319 = io_grant_bits_payload_is_builtin_type & T_1318;
+ assign T_1321 = T_1319 == 1'h0;
+ assign T_1322 = T_1316 & T_1321;
+ assign T_1323 = T_1313 & T_1322;
+ assign T_1327_0 = 3'h5;
+ assign T_1330 = T_1327_0 == io_grant_bits_payload_g_type;
+ assign T_1332 = 1'h0 | T_1330;
+ assign T_1334_0 = 1'h0;
+ assign T_1334_1 = 1'h1;
+ assign T_1338 = T_1334_0 == io_grant_bits_payload_g_type;
+ assign T_1339 = T_1334_1 == io_grant_bits_payload_g_type;
+ assign T_1341 = 1'h0 | T_1338;
+ assign T_1342 = T_1341 | T_1339;
+ assign T_1343 = io_grant_bits_payload_is_builtin_type ? T_1332 : T_1342;
+ assign T_1344 = 1'h1 & T_1343;
+ assign T_1346 = T_1344 == 1'h0;
+ assign T_1347 = T_1346 | T_1215;
+ assign T_1348 = T_1323 & T_1347;
+ assign T_1374_manager_xact_id = io_grant_bits_payload_manager_xact_id;
+ assign T_1402 = 1'h0 == 1'h0;
+ assign T_1404 = io_grant_bits_payload_g_type == 3'h0;
+ assign T_1405 = io_grant_bits_payload_is_builtin_type & T_1404;
+ assign T_1407 = T_1405 == 1'h0;
+ assign T_1408 = T_1402 & T_1407;
+ assign T_1410 = T_1408 == 1'h0;
+ assign T_1411 = T_1312_io_enq_ready | T_1410;
+ assign T_1412 = T_1411 & io_grant_valid;
+ assign T_1415 = 1'h0 == 1'h0;
+ assign T_1417 = io_grant_bits_payload_g_type == 3'h0;
+ assign T_1418 = io_grant_bits_payload_is_builtin_type & T_1417;
+ assign T_1420 = T_1418 == 1'h0;
+ assign T_1421 = T_1415 & T_1420;
+ assign T_1423 = T_1421 == 1'h0;
+ assign T_1424 = T_1312_io_enq_ready | T_1423;
+ assign T_1425 = T_1424 & io_refill_ready;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_1203 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ T_1203 <= 2'h0;
+ end else begin
+ if(T_1201) begin
+ T_1203 <= T_1212;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module ClientTileLinkNetworkPort(
+ input clk,
+ input reset,
+ output io_client_acquire_ready,
+ input io_client_acquire_valid,
+ input [25:0] io_client_acquire_bits_addr_block,
+ input [1:0] io_client_acquire_bits_client_xact_id,
+ input [1:0] io_client_acquire_bits_addr_beat,
+ input io_client_acquire_bits_is_builtin_type,
+ input [2:0] io_client_acquire_bits_a_type,
+ input [16:0] io_client_acquire_bits_union,
+ input [127:0] io_client_acquire_bits_data,
+ input io_client_grant_ready,
+ output io_client_grant_valid,
+ output [1:0] io_client_grant_bits_addr_beat,
+ output [1:0] io_client_grant_bits_client_xact_id,
+ output [3:0] io_client_grant_bits_manager_xact_id,
+ output io_client_grant_bits_is_builtin_type,
+ output [3:0] io_client_grant_bits_g_type,
+ output [127:0] io_client_grant_bits_data,
+ input io_client_probe_ready,
+ output io_client_probe_valid,
+ output [25:0] io_client_probe_bits_addr_block,
+ output [1:0] io_client_probe_bits_p_type,
+ output io_client_release_ready,
+ input io_client_release_valid,
+ input [1:0] io_client_release_bits_addr_beat,
+ input [25:0] io_client_release_bits_addr_block,
+ input [1:0] io_client_release_bits_client_xact_id,
+ input io_client_release_bits_voluntary,
+ input [2:0] io_client_release_bits_r_type,
+ input [127:0] io_client_release_bits_data,
+ input io_network_acquire_ready,
+ output io_network_acquire_valid,
+ output [1:0] io_network_acquire_bits_header_src,
+ output [1:0] io_network_acquire_bits_header_dst,
+ output [25:0] io_network_acquire_bits_payload_addr_block,
+ output [1:0] io_network_acquire_bits_payload_client_xact_id,
+ output [1:0] io_network_acquire_bits_payload_addr_beat,
+ output io_network_acquire_bits_payload_is_builtin_type,
+ output [2:0] io_network_acquire_bits_payload_a_type,
+ output [16:0] io_network_acquire_bits_payload_union,
+ output [127:0] io_network_acquire_bits_payload_data,
+ output io_network_grant_ready,
+ input io_network_grant_valid,
+ input [1:0] io_network_grant_bits_header_src,
+ input [1:0] io_network_grant_bits_header_dst,
+ input [1:0] io_network_grant_bits_payload_addr_beat,
+ input [1:0] io_network_grant_bits_payload_client_xact_id,
+ input [3:0] io_network_grant_bits_payload_manager_xact_id,
+ input io_network_grant_bits_payload_is_builtin_type,
+ input [3:0] io_network_grant_bits_payload_g_type,
+ input [127:0] io_network_grant_bits_payload_data,
+ input io_network_finish_ready,
+ output io_network_finish_valid,
+ output [1:0] io_network_finish_bits_header_src,
+ output [1:0] io_network_finish_bits_header_dst,
+ output [3:0] io_network_finish_bits_payload_manager_xact_id,
+ output io_network_probe_ready,
+ input io_network_probe_valid,
+ input [1:0] io_network_probe_bits_header_src,
+ input [1:0] io_network_probe_bits_header_dst,
+ input [25:0] io_network_probe_bits_payload_addr_block,
+ input [1:0] io_network_probe_bits_payload_p_type,
+ input io_network_release_ready,
+ output io_network_release_valid,
+ output [1:0] io_network_release_bits_header_src,
+ output [1:0] io_network_release_bits_header_dst,
+ output [1:0] io_network_release_bits_payload_addr_beat,
+ output [25:0] io_network_release_bits_payload_addr_block,
+ output [1:0] io_network_release_bits_payload_client_xact_id,
+ output io_network_release_bits_payload_voluntary,
+ output [2:0] io_network_release_bits_payload_r_type,
+ output [127:0] io_network_release_bits_payload_data
+);
+ wire finisher_clk;
+ wire finisher_reset;
+ wire finisher_io_grant_ready;
+ wire finisher_io_grant_valid;
+ wire [1:0] finisher_io_grant_bits_header_src;
+ wire [1:0] finisher_io_grant_bits_header_dst;
+ wire [1:0] finisher_io_grant_bits_payload_addr_beat;
+ wire [1:0] finisher_io_grant_bits_payload_client_xact_id;
+ wire [3:0] finisher_io_grant_bits_payload_manager_xact_id;
+ wire finisher_io_grant_bits_payload_is_builtin_type;
+ wire [3:0] finisher_io_grant_bits_payload_g_type;
+ wire [127:0] finisher_io_grant_bits_payload_data;
+ wire finisher_io_refill_ready;
+ wire finisher_io_refill_valid;
+ wire [1:0] finisher_io_refill_bits_addr_beat;
+ wire [1:0] finisher_io_refill_bits_client_xact_id;
+ wire [3:0] finisher_io_refill_bits_manager_xact_id;
+ wire finisher_io_refill_bits_is_builtin_type;
+ wire [3:0] finisher_io_refill_bits_g_type;
+ wire [127:0] finisher_io_refill_bits_data;
+ wire finisher_io_finish_ready;
+ wire finisher_io_finish_valid;
+ wire [1:0] finisher_io_finish_bits_header_src;
+ wire [1:0] finisher_io_finish_bits_header_dst;
+ wire [3:0] finisher_io_finish_bits_payload_manager_xact_id;
+ wire finisher_io_ready;
+ wire acq_with_header_ready;
+ wire acq_with_header_valid;
+ wire [1:0] acq_with_header_bits_header_src;
+ wire [1:0] acq_with_header_bits_header_dst;
+ wire [25:0] acq_with_header_bits_payload_addr_block;
+ wire [1:0] acq_with_header_bits_payload_client_xact_id;
+ wire [1:0] acq_with_header_bits_payload_addr_beat;
+ wire acq_with_header_bits_payload_is_builtin_type;
+ wire [2:0] acq_with_header_bits_payload_a_type;
+ wire [16:0] acq_with_header_bits_payload_union;
+ wire [127:0] acq_with_header_bits_payload_data;
+ wire rel_with_header_ready;
+ wire rel_with_header_valid;
+ wire [1:0] rel_with_header_bits_header_src;
+ wire [1:0] rel_with_header_bits_header_dst;
+ wire [1:0] rel_with_header_bits_payload_addr_beat;
+ wire [25:0] rel_with_header_bits_payload_addr_block;
+ wire [1:0] rel_with_header_bits_payload_client_xact_id;
+ wire rel_with_header_bits_payload_voluntary;
+ wire [2:0] rel_with_header_bits_payload_r_type;
+ wire [127:0] rel_with_header_bits_payload_data;
+ wire prb_without_header_ready;
+ wire prb_without_header_valid;
+ wire [25:0] prb_without_header_bits_addr_block;
+ wire [1:0] prb_without_header_bits_p_type;
+ wire T_4978;
+ wire T_4979;
+ FinishUnit finisher (
+ .clk(finisher_clk),
+ .reset(finisher_reset),
+ .io_grant_ready(finisher_io_grant_ready),
+ .io_grant_valid(finisher_io_grant_valid),
+ .io_grant_bits_header_src(finisher_io_grant_bits_header_src),
+ .io_grant_bits_header_dst(finisher_io_grant_bits_header_dst),
+ .io_grant_bits_payload_addr_beat(finisher_io_grant_bits_payload_addr_beat),
+ .io_grant_bits_payload_client_xact_id(finisher_io_grant_bits_payload_client_xact_id),
+ .io_grant_bits_payload_manager_xact_id(finisher_io_grant_bits_payload_manager_xact_id),
+ .io_grant_bits_payload_is_builtin_type(finisher_io_grant_bits_payload_is_builtin_type),
+ .io_grant_bits_payload_g_type(finisher_io_grant_bits_payload_g_type),
+ .io_grant_bits_payload_data(finisher_io_grant_bits_payload_data),
+ .io_refill_ready(finisher_io_refill_ready),
+ .io_refill_valid(finisher_io_refill_valid),
+ .io_refill_bits_addr_beat(finisher_io_refill_bits_addr_beat),
+ .io_refill_bits_client_xact_id(finisher_io_refill_bits_client_xact_id),
+ .io_refill_bits_manager_xact_id(finisher_io_refill_bits_manager_xact_id),
+ .io_refill_bits_is_builtin_type(finisher_io_refill_bits_is_builtin_type),
+ .io_refill_bits_g_type(finisher_io_refill_bits_g_type),
+ .io_refill_bits_data(finisher_io_refill_bits_data),
+ .io_finish_ready(finisher_io_finish_ready),
+ .io_finish_valid(finisher_io_finish_valid),
+ .io_finish_bits_header_src(finisher_io_finish_bits_header_src),
+ .io_finish_bits_header_dst(finisher_io_finish_bits_header_dst),
+ .io_finish_bits_payload_manager_xact_id(finisher_io_finish_bits_payload_manager_xact_id),
+ .io_ready(finisher_io_ready)
+ );
+ assign io_client_acquire_ready = acq_with_header_ready;
+ assign io_client_grant_valid = finisher_io_refill_valid;
+ assign io_client_grant_bits_addr_beat = finisher_io_refill_bits_addr_beat;
+ assign io_client_grant_bits_client_xact_id = finisher_io_refill_bits_client_xact_id;
+ assign io_client_grant_bits_manager_xact_id = finisher_io_refill_bits_manager_xact_id;
+ assign io_client_grant_bits_is_builtin_type = finisher_io_refill_bits_is_builtin_type;
+ assign io_client_grant_bits_g_type = finisher_io_refill_bits_g_type;
+ assign io_client_grant_bits_data = finisher_io_refill_bits_data;
+ assign io_client_probe_valid = prb_without_header_valid;
+ assign io_client_probe_bits_addr_block = prb_without_header_bits_addr_block;
+ assign io_client_probe_bits_p_type = prb_without_header_bits_p_type;
+ assign io_client_release_ready = rel_with_header_ready;
+ assign io_network_acquire_valid = T_4978;
+ assign io_network_acquire_bits_header_src = acq_with_header_bits_header_src;
+ assign io_network_acquire_bits_header_dst = acq_with_header_bits_header_dst;
+ assign io_network_acquire_bits_payload_addr_block = acq_with_header_bits_payload_addr_block;
+ assign io_network_acquire_bits_payload_client_xact_id = acq_with_header_bits_payload_client_xact_id;
+ assign io_network_acquire_bits_payload_addr_beat = acq_with_header_bits_payload_addr_beat;
+ assign io_network_acquire_bits_payload_is_builtin_type = acq_with_header_bits_payload_is_builtin_type;
+ assign io_network_acquire_bits_payload_a_type = acq_with_header_bits_payload_a_type;
+ assign io_network_acquire_bits_payload_union = acq_with_header_bits_payload_union;
+ assign io_network_acquire_bits_payload_data = acq_with_header_bits_payload_data;
+ assign io_network_grant_ready = finisher_io_grant_ready;
+ assign io_network_finish_valid = finisher_io_finish_valid;
+ assign io_network_finish_bits_header_src = finisher_io_finish_bits_header_src;
+ assign io_network_finish_bits_header_dst = finisher_io_finish_bits_header_dst;
+ assign io_network_finish_bits_payload_manager_xact_id = finisher_io_finish_bits_payload_manager_xact_id;
+ assign io_network_probe_ready = prb_without_header_ready;
+ assign io_network_release_valid = rel_with_header_valid;
+ assign io_network_release_bits_header_src = rel_with_header_bits_header_src;
+ assign io_network_release_bits_header_dst = rel_with_header_bits_header_dst;
+ assign io_network_release_bits_payload_addr_beat = rel_with_header_bits_payload_addr_beat;
+ assign io_network_release_bits_payload_addr_block = rel_with_header_bits_payload_addr_block;
+ assign io_network_release_bits_payload_client_xact_id = rel_with_header_bits_payload_client_xact_id;
+ assign io_network_release_bits_payload_voluntary = rel_with_header_bits_payload_voluntary;
+ assign io_network_release_bits_payload_r_type = rel_with_header_bits_payload_r_type;
+ assign io_network_release_bits_payload_data = rel_with_header_bits_payload_data;
+ assign finisher_clk = clk;
+ assign finisher_reset = reset;
+ assign finisher_io_grant_valid = io_network_grant_valid;
+ assign finisher_io_grant_bits_header_src = io_network_grant_bits_header_src;
+ assign finisher_io_grant_bits_header_dst = io_network_grant_bits_header_dst;
+ assign finisher_io_grant_bits_payload_addr_beat = io_network_grant_bits_payload_addr_beat;
+ assign finisher_io_grant_bits_payload_client_xact_id = io_network_grant_bits_payload_client_xact_id;
+ assign finisher_io_grant_bits_payload_manager_xact_id = io_network_grant_bits_payload_manager_xact_id;
+ assign finisher_io_grant_bits_payload_is_builtin_type = io_network_grant_bits_payload_is_builtin_type;
+ assign finisher_io_grant_bits_payload_g_type = io_network_grant_bits_payload_g_type;
+ assign finisher_io_grant_bits_payload_data = io_network_grant_bits_payload_data;
+ assign finisher_io_refill_ready = io_client_grant_ready;
+ assign finisher_io_finish_ready = io_network_finish_ready;
+ assign acq_with_header_ready = T_4979;
+ assign acq_with_header_valid = io_client_acquire_valid;
+ assign acq_with_header_bits_header_src = 1'h0;
+ assign acq_with_header_bits_header_dst = 1'h0;
+ assign acq_with_header_bits_payload_addr_block = io_client_acquire_bits_addr_block;
+ assign acq_with_header_bits_payload_client_xact_id = io_client_acquire_bits_client_xact_id;
+ assign acq_with_header_bits_payload_addr_beat = io_client_acquire_bits_addr_beat;
+ assign acq_with_header_bits_payload_is_builtin_type = io_client_acquire_bits_is_builtin_type;
+ assign acq_with_header_bits_payload_a_type = io_client_acquire_bits_a_type;
+ assign acq_with_header_bits_payload_union = io_client_acquire_bits_union;
+ assign acq_with_header_bits_payload_data = io_client_acquire_bits_data;
+ assign rel_with_header_ready = io_network_release_ready;
+ assign rel_with_header_valid = io_client_release_valid;
+ assign rel_with_header_bits_header_src = 1'h0;
+ assign rel_with_header_bits_header_dst = 1'h0;
+ assign rel_with_header_bits_payload_addr_beat = io_client_release_bits_addr_beat;
+ assign rel_with_header_bits_payload_addr_block = io_client_release_bits_addr_block;
+ assign rel_with_header_bits_payload_client_xact_id = io_client_release_bits_client_xact_id;
+ assign rel_with_header_bits_payload_voluntary = io_client_release_bits_voluntary;
+ assign rel_with_header_bits_payload_r_type = io_client_release_bits_r_type;
+ assign rel_with_header_bits_payload_data = io_client_release_bits_data;
+ assign prb_without_header_ready = io_client_probe_ready;
+ assign prb_without_header_valid = io_network_probe_valid;
+ assign prb_without_header_bits_addr_block = io_network_probe_bits_payload_addr_block;
+ assign prb_without_header_bits_p_type = io_network_probe_bits_payload_p_type;
+ assign T_4978 = acq_with_header_valid & finisher_io_ready;
+ assign T_4979 = io_network_acquire_ready & finisher_io_ready;
+endmodule
+module Queue(
+ input clk,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [1:0] io_enq_bits_header_src,
+ input [1:0] io_enq_bits_header_dst,
+ input [25:0] io_enq_bits_payload_addr_block,
+ input [1:0] io_enq_bits_payload_client_xact_id,
+ input [1:0] io_enq_bits_payload_addr_beat,
+ input io_enq_bits_payload_is_builtin_type,
+ input [2:0] io_enq_bits_payload_a_type,
+ input [16:0] io_enq_bits_payload_union,
+ input [127:0] io_enq_bits_payload_data,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [1:0] io_deq_bits_header_src,
+ output [1:0] io_deq_bits_header_dst,
+ output [25:0] io_deq_bits_payload_addr_block,
+ output [1:0] io_deq_bits_payload_client_xact_id,
+ output [1:0] io_deq_bits_payload_addr_beat,
+ output io_deq_bits_payload_is_builtin_type,
+ output [2:0] io_deq_bits_payload_a_type,
+ output [16:0] io_deq_bits_payload_union,
+ output [127:0] io_deq_bits_payload_data,
+ output [1:0] io_count
+);
+ reg [1:0] ram_header_src [0:1];
+ wire [1:0] ram_header_src_T_1337_data;
+ wire ram_header_src_T_1337_addr;
+ wire ram_header_src_T_1337_en;
+ wire ram_header_src_T_1337_clk;
+ wire [1:0] ram_header_src_T_1181_data;
+ wire ram_header_src_T_1181_addr;
+ wire ram_header_src_T_1181_mask;
+ wire ram_header_src_T_1181_en;
+ wire ram_header_src_T_1181_clk;
+ reg [1:0] ram_header_dst [0:1];
+ wire [1:0] ram_header_dst_T_1337_data;
+ wire ram_header_dst_T_1337_addr;
+ wire ram_header_dst_T_1337_en;
+ wire ram_header_dst_T_1337_clk;
+ wire [1:0] ram_header_dst_T_1181_data;
+ wire ram_header_dst_T_1181_addr;
+ wire ram_header_dst_T_1181_mask;
+ wire ram_header_dst_T_1181_en;
+ wire ram_header_dst_T_1181_clk;
+ reg [25:0] ram_payload_addr_block [0:1];
+ wire [25:0] ram_payload_addr_block_T_1337_data;
+ wire ram_payload_addr_block_T_1337_addr;
+ wire ram_payload_addr_block_T_1337_en;
+ wire ram_payload_addr_block_T_1337_clk;
+ wire [25:0] ram_payload_addr_block_T_1181_data;
+ wire ram_payload_addr_block_T_1181_addr;
+ wire ram_payload_addr_block_T_1181_mask;
+ wire ram_payload_addr_block_T_1181_en;
+ wire ram_payload_addr_block_T_1181_clk;
+ reg [1:0] ram_payload_client_xact_id [0:1];
+ wire [1:0] ram_payload_client_xact_id_T_1337_data;
+ wire ram_payload_client_xact_id_T_1337_addr;
+ wire ram_payload_client_xact_id_T_1337_en;
+ wire ram_payload_client_xact_id_T_1337_clk;
+ wire [1:0] ram_payload_client_xact_id_T_1181_data;
+ wire ram_payload_client_xact_id_T_1181_addr;
+ wire ram_payload_client_xact_id_T_1181_mask;
+ wire ram_payload_client_xact_id_T_1181_en;
+ wire ram_payload_client_xact_id_T_1181_clk;
+ reg [1:0] ram_payload_addr_beat [0:1];
+ wire [1:0] ram_payload_addr_beat_T_1337_data;
+ wire ram_payload_addr_beat_T_1337_addr;
+ wire ram_payload_addr_beat_T_1337_en;
+ wire ram_payload_addr_beat_T_1337_clk;
+ wire [1:0] ram_payload_addr_beat_T_1181_data;
+ wire ram_payload_addr_beat_T_1181_addr;
+ wire ram_payload_addr_beat_T_1181_mask;
+ wire ram_payload_addr_beat_T_1181_en;
+ wire ram_payload_addr_beat_T_1181_clk;
+ reg ram_payload_is_builtin_type [0:1];
+ wire ram_payload_is_builtin_type_T_1337_data;
+ wire ram_payload_is_builtin_type_T_1337_addr;
+ wire ram_payload_is_builtin_type_T_1337_en;
+ wire ram_payload_is_builtin_type_T_1337_clk;
+ wire ram_payload_is_builtin_type_T_1181_data;
+ wire ram_payload_is_builtin_type_T_1181_addr;
+ wire ram_payload_is_builtin_type_T_1181_mask;
+ wire ram_payload_is_builtin_type_T_1181_en;
+ wire ram_payload_is_builtin_type_T_1181_clk;
+ reg [2:0] ram_payload_a_type [0:1];
+ wire [2:0] ram_payload_a_type_T_1337_data;
+ wire ram_payload_a_type_T_1337_addr;
+ wire ram_payload_a_type_T_1337_en;
+ wire ram_payload_a_type_T_1337_clk;
+ wire [2:0] ram_payload_a_type_T_1181_data;
+ wire ram_payload_a_type_T_1181_addr;
+ wire ram_payload_a_type_T_1181_mask;
+ wire ram_payload_a_type_T_1181_en;
+ wire ram_payload_a_type_T_1181_clk;
+ reg [16:0] ram_payload_union [0:1];
+ wire [16:0] ram_payload_union_T_1337_data;
+ wire ram_payload_union_T_1337_addr;
+ wire ram_payload_union_T_1337_en;
+ wire ram_payload_union_T_1337_clk;
+ wire [16:0] ram_payload_union_T_1181_data;
+ wire ram_payload_union_T_1181_addr;
+ wire ram_payload_union_T_1181_mask;
+ wire ram_payload_union_T_1181_en;
+ wire ram_payload_union_T_1181_clk;
+ reg [127:0] ram_payload_data [0:1];
+ wire [127:0] ram_payload_data_T_1337_data;
+ wire ram_payload_data_T_1337_addr;
+ wire ram_payload_data_T_1337_en;
+ wire ram_payload_data_T_1337_clk;
+ wire [127:0] ram_payload_data_T_1181_data;
+ wire ram_payload_data_T_1181_addr;
+ wire ram_payload_data_T_1181_mask;
+ wire ram_payload_data_T_1181_en;
+ wire ram_payload_data_T_1181_clk;
+ reg T_1160;
+ reg T_1162;
+ reg maybe_full;
+ wire ptr_match;
+ wire T_1167;
+ wire empty;
+ wire full;
+ wire maybe_flow;
+ wire do_flow;
+ wire T_1173;
+ wire T_1175;
+ wire do_enq;
+ wire T_1177;
+ wire T_1179;
+ wire do_deq;
+ wire T_1309;
+ wire T_1311;
+ wire [1:0] T_1314;
+ wire T_1315;
+ wire T_1316;
+ wire T_1318;
+ wire T_1320;
+ wire [1:0] T_1323;
+ wire T_1324;
+ wire T_1325;
+ wire T_1326;
+ wire T_1328;
+ wire T_1330;
+ wire T_1331;
+ wire T_1333;
+ wire T_1335;
+ wire T_1336;
+ wire [1:0] T_1464_header_src;
+ wire [1:0] T_1464_header_dst;
+ wire [25:0] T_1464_payload_addr_block;
+ wire [1:0] T_1464_payload_client_xact_id;
+ wire [1:0] T_1464_payload_addr_beat;
+ wire T_1464_payload_is_builtin_type;
+ wire [2:0] T_1464_payload_a_type;
+ wire [16:0] T_1464_payload_union;
+ wire [127:0] T_1464_payload_data;
+ wire [1:0] T_1591;
+ wire ptr_diff;
+ wire T_1593;
+ wire [1:0] T_1594;
+ assign io_enq_ready = T_1336;
+ assign io_deq_valid = T_1331;
+ assign io_deq_bits_header_src = T_1464_header_src;
+ assign io_deq_bits_header_dst = T_1464_header_dst;
+ assign io_deq_bits_payload_addr_block = T_1464_payload_addr_block;
+ assign io_deq_bits_payload_client_xact_id = T_1464_payload_client_xact_id;
+ assign io_deq_bits_payload_addr_beat = T_1464_payload_addr_beat;
+ assign io_deq_bits_payload_is_builtin_type = T_1464_payload_is_builtin_type;
+ assign io_deq_bits_payload_a_type = T_1464_payload_a_type;
+ assign io_deq_bits_payload_union = T_1464_payload_union;
+ assign io_deq_bits_payload_data = T_1464_payload_data;
+ assign io_count = T_1594;
+ assign ram_header_src_T_1337_addr = T_1162;
+ assign ram_header_src_T_1337_en = 1'h1;
+ assign ram_header_src_T_1337_clk = clk;
+ assign ram_header_src_T_1337_data = ram_header_src[ram_header_src_T_1337_addr];
+ assign ram_header_src_T_1181_data = io_enq_bits_header_src;
+ assign ram_header_src_T_1181_addr = T_1160;
+ assign ram_header_src_T_1181_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_header_src_T_1181_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_header_src_T_1181_clk = clk;
+ assign ram_header_dst_T_1337_addr = T_1162;
+ assign ram_header_dst_T_1337_en = 1'h1;
+ assign ram_header_dst_T_1337_clk = clk;
+ assign ram_header_dst_T_1337_data = ram_header_dst[ram_header_dst_T_1337_addr];
+ assign ram_header_dst_T_1181_data = io_enq_bits_header_dst;
+ assign ram_header_dst_T_1181_addr = T_1160;
+ assign ram_header_dst_T_1181_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_header_dst_T_1181_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_header_dst_T_1181_clk = clk;
+ assign ram_payload_addr_block_T_1337_addr = T_1162;
+ assign ram_payload_addr_block_T_1337_en = 1'h1;
+ assign ram_payload_addr_block_T_1337_clk = clk;
+ assign ram_payload_addr_block_T_1337_data = ram_payload_addr_block[ram_payload_addr_block_T_1337_addr];
+ assign ram_payload_addr_block_T_1181_data = io_enq_bits_payload_addr_block;
+ assign ram_payload_addr_block_T_1181_addr = T_1160;
+ assign ram_payload_addr_block_T_1181_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_addr_block_T_1181_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_addr_block_T_1181_clk = clk;
+ assign ram_payload_client_xact_id_T_1337_addr = T_1162;
+ assign ram_payload_client_xact_id_T_1337_en = 1'h1;
+ assign ram_payload_client_xact_id_T_1337_clk = clk;
+ assign ram_payload_client_xact_id_T_1337_data = ram_payload_client_xact_id[ram_payload_client_xact_id_T_1337_addr];
+ assign ram_payload_client_xact_id_T_1181_data = io_enq_bits_payload_client_xact_id;
+ assign ram_payload_client_xact_id_T_1181_addr = T_1160;
+ assign ram_payload_client_xact_id_T_1181_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_client_xact_id_T_1181_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_client_xact_id_T_1181_clk = clk;
+ assign ram_payload_addr_beat_T_1337_addr = T_1162;
+ assign ram_payload_addr_beat_T_1337_en = 1'h1;
+ assign ram_payload_addr_beat_T_1337_clk = clk;
+ assign ram_payload_addr_beat_T_1337_data = ram_payload_addr_beat[ram_payload_addr_beat_T_1337_addr];
+ assign ram_payload_addr_beat_T_1181_data = io_enq_bits_payload_addr_beat;
+ assign ram_payload_addr_beat_T_1181_addr = T_1160;
+ assign ram_payload_addr_beat_T_1181_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_addr_beat_T_1181_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_addr_beat_T_1181_clk = clk;
+ assign ram_payload_is_builtin_type_T_1337_addr = T_1162;
+ assign ram_payload_is_builtin_type_T_1337_en = 1'h1;
+ assign ram_payload_is_builtin_type_T_1337_clk = clk;
+ assign ram_payload_is_builtin_type_T_1337_data = ram_payload_is_builtin_type[ram_payload_is_builtin_type_T_1337_addr];
+ assign ram_payload_is_builtin_type_T_1181_data = io_enq_bits_payload_is_builtin_type;
+ assign ram_payload_is_builtin_type_T_1181_addr = T_1160;
+ assign ram_payload_is_builtin_type_T_1181_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_is_builtin_type_T_1181_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_is_builtin_type_T_1181_clk = clk;
+ assign ram_payload_a_type_T_1337_addr = T_1162;
+ assign ram_payload_a_type_T_1337_en = 1'h1;
+ assign ram_payload_a_type_T_1337_clk = clk;
+ assign ram_payload_a_type_T_1337_data = ram_payload_a_type[ram_payload_a_type_T_1337_addr];
+ assign ram_payload_a_type_T_1181_data = io_enq_bits_payload_a_type;
+ assign ram_payload_a_type_T_1181_addr = T_1160;
+ assign ram_payload_a_type_T_1181_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_a_type_T_1181_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_a_type_T_1181_clk = clk;
+ assign ram_payload_union_T_1337_addr = T_1162;
+ assign ram_payload_union_T_1337_en = 1'h1;
+ assign ram_payload_union_T_1337_clk = clk;
+ assign ram_payload_union_T_1337_data = ram_payload_union[ram_payload_union_T_1337_addr];
+ assign ram_payload_union_T_1181_data = io_enq_bits_payload_union;
+ assign ram_payload_union_T_1181_addr = T_1160;
+ assign ram_payload_union_T_1181_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_union_T_1181_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_union_T_1181_clk = clk;
+ assign ram_payload_data_T_1337_addr = T_1162;
+ assign ram_payload_data_T_1337_en = 1'h1;
+ assign ram_payload_data_T_1337_clk = clk;
+ assign ram_payload_data_T_1337_data = ram_payload_data[ram_payload_data_T_1337_addr];
+ assign ram_payload_data_T_1181_data = io_enq_bits_payload_data;
+ assign ram_payload_data_T_1181_addr = T_1160;
+ assign ram_payload_data_T_1181_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_data_T_1181_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_data_T_1181_clk = clk;
+ assign ptr_match = T_1160 == T_1162;
+ assign T_1167 = maybe_full == 1'h0;
+ assign empty = ptr_match & T_1167;
+ assign full = ptr_match & maybe_full;
+ assign maybe_flow = 1'h0 & empty;
+ assign do_flow = maybe_flow & io_deq_ready;
+ assign T_1173 = io_enq_ready & io_enq_valid;
+ assign T_1175 = do_flow == 1'h0;
+ assign do_enq = T_1173 & T_1175;
+ assign T_1177 = io_deq_ready & io_deq_valid;
+ assign T_1179 = do_flow == 1'h0;
+ assign do_deq = T_1177 & T_1179;
+ assign T_1309 = T_1160 == 1'h1;
+ assign T_1311 = 1'h0 & T_1309;
+ assign T_1314 = T_1160 + 1'h1;
+ assign T_1315 = T_1314[0:0];
+ assign T_1316 = T_1311 ? 1'h0 : T_1315;
+ assign T_1318 = T_1162 == 1'h1;
+ assign T_1320 = 1'h0 & T_1318;
+ assign T_1323 = T_1162 + 1'h1;
+ assign T_1324 = T_1323[0:0];
+ assign T_1325 = T_1320 ? 1'h0 : T_1324;
+ assign T_1326 = do_enq != do_deq;
+ assign T_1328 = empty == 1'h0;
+ assign T_1330 = 1'h0 & io_enq_valid;
+ assign T_1331 = T_1328 | T_1330;
+ assign T_1333 = full == 1'h0;
+ assign T_1335 = 1'h0 & io_deq_ready;
+ assign T_1336 = T_1333 | T_1335;
+ assign T_1464_header_src = maybe_flow ? io_enq_bits_header_src : ram_header_src_T_1337_data;
+ assign T_1464_header_dst = maybe_flow ? io_enq_bits_header_dst : ram_header_dst_T_1337_data;
+ assign T_1464_payload_addr_block = maybe_flow ? io_enq_bits_payload_addr_block : ram_payload_addr_block_T_1337_data;
+ assign T_1464_payload_client_xact_id = maybe_flow ? io_enq_bits_payload_client_xact_id : ram_payload_client_xact_id_T_1337_data;
+ assign T_1464_payload_addr_beat = maybe_flow ? io_enq_bits_payload_addr_beat : ram_payload_addr_beat_T_1337_data;
+ assign T_1464_payload_is_builtin_type = maybe_flow ? io_enq_bits_payload_is_builtin_type : ram_payload_is_builtin_type_T_1337_data;
+ assign T_1464_payload_a_type = maybe_flow ? io_enq_bits_payload_a_type : ram_payload_a_type_T_1337_data;
+ assign T_1464_payload_union = maybe_flow ? io_enq_bits_payload_union : ram_payload_union_T_1337_data;
+ assign T_1464_payload_data = maybe_flow ? io_enq_bits_payload_data : ram_payload_data_T_1337_data;
+ assign T_1591 = T_1160 - T_1162;
+ assign ptr_diff = T_1591[0:0];
+ assign T_1593 = maybe_full & ptr_match;
+ assign T_1594 = {T_1593,ptr_diff};
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_header_src[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_header_dst[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_payload_addr_block[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_payload_client_xact_id[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_payload_addr_beat[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_payload_is_builtin_type[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_payload_a_type[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_payload_union[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_payload_data[initvar] = {4{$random}};
+ T_1160 = {1{$random}};
+ T_1162 = {1{$random}};
+ maybe_full = {1{$random}};
+ end
+`endif
+ always @(posedge ram_header_src_T_1181_clk) begin
+ if(ram_header_src_T_1181_en & ram_header_src_T_1181_mask) begin
+ ram_header_src[ram_header_src_T_1181_addr] <= ram_header_src_T_1181_data;
+ end
+ end
+ always @(posedge ram_header_dst_T_1181_clk) begin
+ if(ram_header_dst_T_1181_en & ram_header_dst_T_1181_mask) begin
+ ram_header_dst[ram_header_dst_T_1181_addr] <= ram_header_dst_T_1181_data;
+ end
+ end
+ always @(posedge ram_payload_addr_block_T_1181_clk) begin
+ if(ram_payload_addr_block_T_1181_en & ram_payload_addr_block_T_1181_mask) begin
+ ram_payload_addr_block[ram_payload_addr_block_T_1181_addr] <= ram_payload_addr_block_T_1181_data;
+ end
+ end
+ always @(posedge ram_payload_client_xact_id_T_1181_clk) begin
+ if(ram_payload_client_xact_id_T_1181_en & ram_payload_client_xact_id_T_1181_mask) begin
+ ram_payload_client_xact_id[ram_payload_client_xact_id_T_1181_addr] <= ram_payload_client_xact_id_T_1181_data;
+ end
+ end
+ always @(posedge ram_payload_addr_beat_T_1181_clk) begin
+ if(ram_payload_addr_beat_T_1181_en & ram_payload_addr_beat_T_1181_mask) begin
+ ram_payload_addr_beat[ram_payload_addr_beat_T_1181_addr] <= ram_payload_addr_beat_T_1181_data;
+ end
+ end
+ always @(posedge ram_payload_is_builtin_type_T_1181_clk) begin
+ if(ram_payload_is_builtin_type_T_1181_en & ram_payload_is_builtin_type_T_1181_mask) begin
+ ram_payload_is_builtin_type[ram_payload_is_builtin_type_T_1181_addr] <= ram_payload_is_builtin_type_T_1181_data;
+ end
+ end
+ always @(posedge ram_payload_a_type_T_1181_clk) begin
+ if(ram_payload_a_type_T_1181_en & ram_payload_a_type_T_1181_mask) begin
+ ram_payload_a_type[ram_payload_a_type_T_1181_addr] <= ram_payload_a_type_T_1181_data;
+ end
+ end
+ always @(posedge ram_payload_union_T_1181_clk) begin
+ if(ram_payload_union_T_1181_en & ram_payload_union_T_1181_mask) begin
+ ram_payload_union[ram_payload_union_T_1181_addr] <= ram_payload_union_T_1181_data;
+ end
+ end
+ always @(posedge ram_payload_data_T_1181_clk) begin
+ if(ram_payload_data_T_1181_en & ram_payload_data_T_1181_mask) begin
+ ram_payload_data[ram_payload_data_T_1181_addr] <= ram_payload_data_T_1181_data;
+ end
+ end
+ always @(posedge clk) begin
+ if(reset) begin
+ T_1160 <= 1'h0;
+ end else begin
+ if(do_enq) begin
+ T_1160 <= T_1316;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_1162 <= 1'h0;
+ end else begin
+ if(do_deq) begin
+ T_1162 <= T_1325;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ maybe_full <= 1'h0;
+ end else begin
+ if(T_1326) begin
+ maybe_full <= do_enq;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module Queue_2(
+ input clk,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [1:0] io_enq_bits_header_src,
+ input [1:0] io_enq_bits_header_dst,
+ input [25:0] io_enq_bits_payload_addr_block,
+ input [1:0] io_enq_bits_payload_p_type,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [1:0] io_deq_bits_header_src,
+ output [1:0] io_deq_bits_header_dst,
+ output [25:0] io_deq_bits_payload_addr_block,
+ output [1:0] io_deq_bits_payload_p_type,
+ output [1:0] io_count
+);
+ reg [1:0] ram_header_src [0:1];
+ wire [1:0] ram_header_src_T_1287_data;
+ wire ram_header_src_T_1287_addr;
+ wire ram_header_src_T_1287_en;
+ wire ram_header_src_T_1287_clk;
+ wire [1:0] ram_header_src_T_1136_data;
+ wire ram_header_src_T_1136_addr;
+ wire ram_header_src_T_1136_mask;
+ wire ram_header_src_T_1136_en;
+ wire ram_header_src_T_1136_clk;
+ reg [1:0] ram_header_dst [0:1];
+ wire [1:0] ram_header_dst_T_1287_data;
+ wire ram_header_dst_T_1287_addr;
+ wire ram_header_dst_T_1287_en;
+ wire ram_header_dst_T_1287_clk;
+ wire [1:0] ram_header_dst_T_1136_data;
+ wire ram_header_dst_T_1136_addr;
+ wire ram_header_dst_T_1136_mask;
+ wire ram_header_dst_T_1136_en;
+ wire ram_header_dst_T_1136_clk;
+ reg [25:0] ram_payload_addr_block [0:1];
+ wire [25:0] ram_payload_addr_block_T_1287_data;
+ wire ram_payload_addr_block_T_1287_addr;
+ wire ram_payload_addr_block_T_1287_en;
+ wire ram_payload_addr_block_T_1287_clk;
+ wire [25:0] ram_payload_addr_block_T_1136_data;
+ wire ram_payload_addr_block_T_1136_addr;
+ wire ram_payload_addr_block_T_1136_mask;
+ wire ram_payload_addr_block_T_1136_en;
+ wire ram_payload_addr_block_T_1136_clk;
+ reg [1:0] ram_payload_p_type [0:1];
+ wire [1:0] ram_payload_p_type_T_1287_data;
+ wire ram_payload_p_type_T_1287_addr;
+ wire ram_payload_p_type_T_1287_en;
+ wire ram_payload_p_type_T_1287_clk;
+ wire [1:0] ram_payload_p_type_T_1136_data;
+ wire ram_payload_p_type_T_1136_addr;
+ wire ram_payload_p_type_T_1136_mask;
+ wire ram_payload_p_type_T_1136_en;
+ wire ram_payload_p_type_T_1136_clk;
+ reg T_1115;
+ reg T_1117;
+ reg maybe_full;
+ wire ptr_match;
+ wire T_1122;
+ wire empty;
+ wire full;
+ wire maybe_flow;
+ wire do_flow;
+ wire T_1128;
+ wire T_1130;
+ wire do_enq;
+ wire T_1132;
+ wire T_1134;
+ wire do_deq;
+ wire T_1259;
+ wire T_1261;
+ wire [1:0] T_1264;
+ wire T_1265;
+ wire T_1266;
+ wire T_1268;
+ wire T_1270;
+ wire [1:0] T_1273;
+ wire T_1274;
+ wire T_1275;
+ wire T_1276;
+ wire T_1278;
+ wire T_1280;
+ wire T_1281;
+ wire T_1283;
+ wire T_1285;
+ wire T_1286;
+ wire [1:0] T_1409_header_src;
+ wire [1:0] T_1409_header_dst;
+ wire [25:0] T_1409_payload_addr_block;
+ wire [1:0] T_1409_payload_p_type;
+ wire [1:0] T_1531;
+ wire ptr_diff;
+ wire T_1533;
+ wire [1:0] T_1534;
+ assign io_enq_ready = T_1286;
+ assign io_deq_valid = T_1281;
+ assign io_deq_bits_header_src = T_1409_header_src;
+ assign io_deq_bits_header_dst = T_1409_header_dst;
+ assign io_deq_bits_payload_addr_block = T_1409_payload_addr_block;
+ assign io_deq_bits_payload_p_type = T_1409_payload_p_type;
+ assign io_count = T_1534;
+ assign ram_header_src_T_1287_addr = T_1117;
+ assign ram_header_src_T_1287_en = 1'h1;
+ assign ram_header_src_T_1287_clk = clk;
+ assign ram_header_src_T_1287_data = ram_header_src[ram_header_src_T_1287_addr];
+ assign ram_header_src_T_1136_data = io_enq_bits_header_src;
+ assign ram_header_src_T_1136_addr = T_1115;
+ assign ram_header_src_T_1136_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_header_src_T_1136_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_header_src_T_1136_clk = clk;
+ assign ram_header_dst_T_1287_addr = T_1117;
+ assign ram_header_dst_T_1287_en = 1'h1;
+ assign ram_header_dst_T_1287_clk = clk;
+ assign ram_header_dst_T_1287_data = ram_header_dst[ram_header_dst_T_1287_addr];
+ assign ram_header_dst_T_1136_data = io_enq_bits_header_dst;
+ assign ram_header_dst_T_1136_addr = T_1115;
+ assign ram_header_dst_T_1136_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_header_dst_T_1136_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_header_dst_T_1136_clk = clk;
+ assign ram_payload_addr_block_T_1287_addr = T_1117;
+ assign ram_payload_addr_block_T_1287_en = 1'h1;
+ assign ram_payload_addr_block_T_1287_clk = clk;
+ assign ram_payload_addr_block_T_1287_data = ram_payload_addr_block[ram_payload_addr_block_T_1287_addr];
+ assign ram_payload_addr_block_T_1136_data = io_enq_bits_payload_addr_block;
+ assign ram_payload_addr_block_T_1136_addr = T_1115;
+ assign ram_payload_addr_block_T_1136_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_addr_block_T_1136_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_addr_block_T_1136_clk = clk;
+ assign ram_payload_p_type_T_1287_addr = T_1117;
+ assign ram_payload_p_type_T_1287_en = 1'h1;
+ assign ram_payload_p_type_T_1287_clk = clk;
+ assign ram_payload_p_type_T_1287_data = ram_payload_p_type[ram_payload_p_type_T_1287_addr];
+ assign ram_payload_p_type_T_1136_data = io_enq_bits_payload_p_type;
+ assign ram_payload_p_type_T_1136_addr = T_1115;
+ assign ram_payload_p_type_T_1136_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_p_type_T_1136_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_p_type_T_1136_clk = clk;
+ assign ptr_match = T_1115 == T_1117;
+ assign T_1122 = maybe_full == 1'h0;
+ assign empty = ptr_match & T_1122;
+ assign full = ptr_match & maybe_full;
+ assign maybe_flow = 1'h0 & empty;
+ assign do_flow = maybe_flow & io_deq_ready;
+ assign T_1128 = io_enq_ready & io_enq_valid;
+ assign T_1130 = do_flow == 1'h0;
+ assign do_enq = T_1128 & T_1130;
+ assign T_1132 = io_deq_ready & io_deq_valid;
+ assign T_1134 = do_flow == 1'h0;
+ assign do_deq = T_1132 & T_1134;
+ assign T_1259 = T_1115 == 1'h1;
+ assign T_1261 = 1'h0 & T_1259;
+ assign T_1264 = T_1115 + 1'h1;
+ assign T_1265 = T_1264[0:0];
+ assign T_1266 = T_1261 ? 1'h0 : T_1265;
+ assign T_1268 = T_1117 == 1'h1;
+ assign T_1270 = 1'h0 & T_1268;
+ assign T_1273 = T_1117 + 1'h1;
+ assign T_1274 = T_1273[0:0];
+ assign T_1275 = T_1270 ? 1'h0 : T_1274;
+ assign T_1276 = do_enq != do_deq;
+ assign T_1278 = empty == 1'h0;
+ assign T_1280 = 1'h0 & io_enq_valid;
+ assign T_1281 = T_1278 | T_1280;
+ assign T_1283 = full == 1'h0;
+ assign T_1285 = 1'h0 & io_deq_ready;
+ assign T_1286 = T_1283 | T_1285;
+ assign T_1409_header_src = maybe_flow ? io_enq_bits_header_src : ram_header_src_T_1287_data;
+ assign T_1409_header_dst = maybe_flow ? io_enq_bits_header_dst : ram_header_dst_T_1287_data;
+ assign T_1409_payload_addr_block = maybe_flow ? io_enq_bits_payload_addr_block : ram_payload_addr_block_T_1287_data;
+ assign T_1409_payload_p_type = maybe_flow ? io_enq_bits_payload_p_type : ram_payload_p_type_T_1287_data;
+ assign T_1531 = T_1115 - T_1117;
+ assign ptr_diff = T_1531[0:0];
+ assign T_1533 = maybe_full & ptr_match;
+ assign T_1534 = {T_1533,ptr_diff};
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_header_src[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_header_dst[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_payload_addr_block[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_payload_p_type[initvar] = {1{$random}};
+ T_1115 = {1{$random}};
+ T_1117 = {1{$random}};
+ maybe_full = {1{$random}};
+ end
+`endif
+ always @(posedge ram_header_src_T_1136_clk) begin
+ if(ram_header_src_T_1136_en & ram_header_src_T_1136_mask) begin
+ ram_header_src[ram_header_src_T_1136_addr] <= ram_header_src_T_1136_data;
+ end
+ end
+ always @(posedge ram_header_dst_T_1136_clk) begin
+ if(ram_header_dst_T_1136_en & ram_header_dst_T_1136_mask) begin
+ ram_header_dst[ram_header_dst_T_1136_addr] <= ram_header_dst_T_1136_data;
+ end
+ end
+ always @(posedge ram_payload_addr_block_T_1136_clk) begin
+ if(ram_payload_addr_block_T_1136_en & ram_payload_addr_block_T_1136_mask) begin
+ ram_payload_addr_block[ram_payload_addr_block_T_1136_addr] <= ram_payload_addr_block_T_1136_data;
+ end
+ end
+ always @(posedge ram_payload_p_type_T_1136_clk) begin
+ if(ram_payload_p_type_T_1136_en & ram_payload_p_type_T_1136_mask) begin
+ ram_payload_p_type[ram_payload_p_type_T_1136_addr] <= ram_payload_p_type_T_1136_data;
+ end
+ end
+ always @(posedge clk) begin
+ if(reset) begin
+ T_1115 <= 1'h0;
+ end else begin
+ if(do_enq) begin
+ T_1115 <= T_1266;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_1117 <= 1'h0;
+ end else begin
+ if(do_deq) begin
+ T_1117 <= T_1275;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ maybe_full <= 1'h0;
+ end else begin
+ if(T_1276) begin
+ maybe_full <= do_enq;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module Queue_3(
+ input clk,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [1:0] io_enq_bits_header_src,
+ input [1:0] io_enq_bits_header_dst,
+ input [1:0] io_enq_bits_payload_addr_beat,
+ input [25:0] io_enq_bits_payload_addr_block,
+ input [1:0] io_enq_bits_payload_client_xact_id,
+ input io_enq_bits_payload_voluntary,
+ input [2:0] io_enq_bits_payload_r_type,
+ input [127:0] io_enq_bits_payload_data,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [1:0] io_deq_bits_header_src,
+ output [1:0] io_deq_bits_header_dst,
+ output [1:0] io_deq_bits_payload_addr_beat,
+ output [25:0] io_deq_bits_payload_addr_block,
+ output [1:0] io_deq_bits_payload_client_xact_id,
+ output io_deq_bits_payload_voluntary,
+ output [2:0] io_deq_bits_payload_r_type,
+ output [127:0] io_deq_bits_payload_data,
+ output [1:0] io_count
+);
+ reg [1:0] ram_header_src [0:1];
+ wire [1:0] ram_header_src_T_1327_data;
+ wire ram_header_src_T_1327_addr;
+ wire ram_header_src_T_1327_en;
+ wire ram_header_src_T_1327_clk;
+ wire [1:0] ram_header_src_T_1172_data;
+ wire ram_header_src_T_1172_addr;
+ wire ram_header_src_T_1172_mask;
+ wire ram_header_src_T_1172_en;
+ wire ram_header_src_T_1172_clk;
+ reg [1:0] ram_header_dst [0:1];
+ wire [1:0] ram_header_dst_T_1327_data;
+ wire ram_header_dst_T_1327_addr;
+ wire ram_header_dst_T_1327_en;
+ wire ram_header_dst_T_1327_clk;
+ wire [1:0] ram_header_dst_T_1172_data;
+ wire ram_header_dst_T_1172_addr;
+ wire ram_header_dst_T_1172_mask;
+ wire ram_header_dst_T_1172_en;
+ wire ram_header_dst_T_1172_clk;
+ reg [1:0] ram_payload_addr_beat [0:1];
+ wire [1:0] ram_payload_addr_beat_T_1327_data;
+ wire ram_payload_addr_beat_T_1327_addr;
+ wire ram_payload_addr_beat_T_1327_en;
+ wire ram_payload_addr_beat_T_1327_clk;
+ wire [1:0] ram_payload_addr_beat_T_1172_data;
+ wire ram_payload_addr_beat_T_1172_addr;
+ wire ram_payload_addr_beat_T_1172_mask;
+ wire ram_payload_addr_beat_T_1172_en;
+ wire ram_payload_addr_beat_T_1172_clk;
+ reg [25:0] ram_payload_addr_block [0:1];
+ wire [25:0] ram_payload_addr_block_T_1327_data;
+ wire ram_payload_addr_block_T_1327_addr;
+ wire ram_payload_addr_block_T_1327_en;
+ wire ram_payload_addr_block_T_1327_clk;
+ wire [25:0] ram_payload_addr_block_T_1172_data;
+ wire ram_payload_addr_block_T_1172_addr;
+ wire ram_payload_addr_block_T_1172_mask;
+ wire ram_payload_addr_block_T_1172_en;
+ wire ram_payload_addr_block_T_1172_clk;
+ reg [1:0] ram_payload_client_xact_id [0:1];
+ wire [1:0] ram_payload_client_xact_id_T_1327_data;
+ wire ram_payload_client_xact_id_T_1327_addr;
+ wire ram_payload_client_xact_id_T_1327_en;
+ wire ram_payload_client_xact_id_T_1327_clk;
+ wire [1:0] ram_payload_client_xact_id_T_1172_data;
+ wire ram_payload_client_xact_id_T_1172_addr;
+ wire ram_payload_client_xact_id_T_1172_mask;
+ wire ram_payload_client_xact_id_T_1172_en;
+ wire ram_payload_client_xact_id_T_1172_clk;
+ reg ram_payload_voluntary [0:1];
+ wire ram_payload_voluntary_T_1327_data;
+ wire ram_payload_voluntary_T_1327_addr;
+ wire ram_payload_voluntary_T_1327_en;
+ wire ram_payload_voluntary_T_1327_clk;
+ wire ram_payload_voluntary_T_1172_data;
+ wire ram_payload_voluntary_T_1172_addr;
+ wire ram_payload_voluntary_T_1172_mask;
+ wire ram_payload_voluntary_T_1172_en;
+ wire ram_payload_voluntary_T_1172_clk;
+ reg [2:0] ram_payload_r_type [0:1];
+ wire [2:0] ram_payload_r_type_T_1327_data;
+ wire ram_payload_r_type_T_1327_addr;
+ wire ram_payload_r_type_T_1327_en;
+ wire ram_payload_r_type_T_1327_clk;
+ wire [2:0] ram_payload_r_type_T_1172_data;
+ wire ram_payload_r_type_T_1172_addr;
+ wire ram_payload_r_type_T_1172_mask;
+ wire ram_payload_r_type_T_1172_en;
+ wire ram_payload_r_type_T_1172_clk;
+ reg [127:0] ram_payload_data [0:1];
+ wire [127:0] ram_payload_data_T_1327_data;
+ wire ram_payload_data_T_1327_addr;
+ wire ram_payload_data_T_1327_en;
+ wire ram_payload_data_T_1327_clk;
+ wire [127:0] ram_payload_data_T_1172_data;
+ wire ram_payload_data_T_1172_addr;
+ wire ram_payload_data_T_1172_mask;
+ wire ram_payload_data_T_1172_en;
+ wire ram_payload_data_T_1172_clk;
+ reg T_1151;
+ reg T_1153;
+ reg maybe_full;
+ wire ptr_match;
+ wire T_1158;
+ wire empty;
+ wire full;
+ wire maybe_flow;
+ wire do_flow;
+ wire T_1164;
+ wire T_1166;
+ wire do_enq;
+ wire T_1168;
+ wire T_1170;
+ wire do_deq;
+ wire T_1299;
+ wire T_1301;
+ wire [1:0] T_1304;
+ wire T_1305;
+ wire T_1306;
+ wire T_1308;
+ wire T_1310;
+ wire [1:0] T_1313;
+ wire T_1314;
+ wire T_1315;
+ wire T_1316;
+ wire T_1318;
+ wire T_1320;
+ wire T_1321;
+ wire T_1323;
+ wire T_1325;
+ wire T_1326;
+ wire [1:0] T_1453_header_src;
+ wire [1:0] T_1453_header_dst;
+ wire [1:0] T_1453_payload_addr_beat;
+ wire [25:0] T_1453_payload_addr_block;
+ wire [1:0] T_1453_payload_client_xact_id;
+ wire T_1453_payload_voluntary;
+ wire [2:0] T_1453_payload_r_type;
+ wire [127:0] T_1453_payload_data;
+ wire [1:0] T_1579;
+ wire ptr_diff;
+ wire T_1581;
+ wire [1:0] T_1582;
+ assign io_enq_ready = T_1326;
+ assign io_deq_valid = T_1321;
+ assign io_deq_bits_header_src = T_1453_header_src;
+ assign io_deq_bits_header_dst = T_1453_header_dst;
+ assign io_deq_bits_payload_addr_beat = T_1453_payload_addr_beat;
+ assign io_deq_bits_payload_addr_block = T_1453_payload_addr_block;
+ assign io_deq_bits_payload_client_xact_id = T_1453_payload_client_xact_id;
+ assign io_deq_bits_payload_voluntary = T_1453_payload_voluntary;
+ assign io_deq_bits_payload_r_type = T_1453_payload_r_type;
+ assign io_deq_bits_payload_data = T_1453_payload_data;
+ assign io_count = T_1582;
+ assign ram_header_src_T_1327_addr = T_1153;
+ assign ram_header_src_T_1327_en = 1'h1;
+ assign ram_header_src_T_1327_clk = clk;
+ assign ram_header_src_T_1327_data = ram_header_src[ram_header_src_T_1327_addr];
+ assign ram_header_src_T_1172_data = io_enq_bits_header_src;
+ assign ram_header_src_T_1172_addr = T_1151;
+ assign ram_header_src_T_1172_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_header_src_T_1172_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_header_src_T_1172_clk = clk;
+ assign ram_header_dst_T_1327_addr = T_1153;
+ assign ram_header_dst_T_1327_en = 1'h1;
+ assign ram_header_dst_T_1327_clk = clk;
+ assign ram_header_dst_T_1327_data = ram_header_dst[ram_header_dst_T_1327_addr];
+ assign ram_header_dst_T_1172_data = io_enq_bits_header_dst;
+ assign ram_header_dst_T_1172_addr = T_1151;
+ assign ram_header_dst_T_1172_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_header_dst_T_1172_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_header_dst_T_1172_clk = clk;
+ assign ram_payload_addr_beat_T_1327_addr = T_1153;
+ assign ram_payload_addr_beat_T_1327_en = 1'h1;
+ assign ram_payload_addr_beat_T_1327_clk = clk;
+ assign ram_payload_addr_beat_T_1327_data = ram_payload_addr_beat[ram_payload_addr_beat_T_1327_addr];
+ assign ram_payload_addr_beat_T_1172_data = io_enq_bits_payload_addr_beat;
+ assign ram_payload_addr_beat_T_1172_addr = T_1151;
+ assign ram_payload_addr_beat_T_1172_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_addr_beat_T_1172_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_addr_beat_T_1172_clk = clk;
+ assign ram_payload_addr_block_T_1327_addr = T_1153;
+ assign ram_payload_addr_block_T_1327_en = 1'h1;
+ assign ram_payload_addr_block_T_1327_clk = clk;
+ assign ram_payload_addr_block_T_1327_data = ram_payload_addr_block[ram_payload_addr_block_T_1327_addr];
+ assign ram_payload_addr_block_T_1172_data = io_enq_bits_payload_addr_block;
+ assign ram_payload_addr_block_T_1172_addr = T_1151;
+ assign ram_payload_addr_block_T_1172_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_addr_block_T_1172_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_addr_block_T_1172_clk = clk;
+ assign ram_payload_client_xact_id_T_1327_addr = T_1153;
+ assign ram_payload_client_xact_id_T_1327_en = 1'h1;
+ assign ram_payload_client_xact_id_T_1327_clk = clk;
+ assign ram_payload_client_xact_id_T_1327_data = ram_payload_client_xact_id[ram_payload_client_xact_id_T_1327_addr];
+ assign ram_payload_client_xact_id_T_1172_data = io_enq_bits_payload_client_xact_id;
+ assign ram_payload_client_xact_id_T_1172_addr = T_1151;
+ assign ram_payload_client_xact_id_T_1172_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_client_xact_id_T_1172_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_client_xact_id_T_1172_clk = clk;
+ assign ram_payload_voluntary_T_1327_addr = T_1153;
+ assign ram_payload_voluntary_T_1327_en = 1'h1;
+ assign ram_payload_voluntary_T_1327_clk = clk;
+ assign ram_payload_voluntary_T_1327_data = ram_payload_voluntary[ram_payload_voluntary_T_1327_addr];
+ assign ram_payload_voluntary_T_1172_data = io_enq_bits_payload_voluntary;
+ assign ram_payload_voluntary_T_1172_addr = T_1151;
+ assign ram_payload_voluntary_T_1172_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_voluntary_T_1172_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_voluntary_T_1172_clk = clk;
+ assign ram_payload_r_type_T_1327_addr = T_1153;
+ assign ram_payload_r_type_T_1327_en = 1'h1;
+ assign ram_payload_r_type_T_1327_clk = clk;
+ assign ram_payload_r_type_T_1327_data = ram_payload_r_type[ram_payload_r_type_T_1327_addr];
+ assign ram_payload_r_type_T_1172_data = io_enq_bits_payload_r_type;
+ assign ram_payload_r_type_T_1172_addr = T_1151;
+ assign ram_payload_r_type_T_1172_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_r_type_T_1172_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_r_type_T_1172_clk = clk;
+ assign ram_payload_data_T_1327_addr = T_1153;
+ assign ram_payload_data_T_1327_en = 1'h1;
+ assign ram_payload_data_T_1327_clk = clk;
+ assign ram_payload_data_T_1327_data = ram_payload_data[ram_payload_data_T_1327_addr];
+ assign ram_payload_data_T_1172_data = io_enq_bits_payload_data;
+ assign ram_payload_data_T_1172_addr = T_1151;
+ assign ram_payload_data_T_1172_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_data_T_1172_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_data_T_1172_clk = clk;
+ assign ptr_match = T_1151 == T_1153;
+ assign T_1158 = maybe_full == 1'h0;
+ assign empty = ptr_match & T_1158;
+ assign full = ptr_match & maybe_full;
+ assign maybe_flow = 1'h0 & empty;
+ assign do_flow = maybe_flow & io_deq_ready;
+ assign T_1164 = io_enq_ready & io_enq_valid;
+ assign T_1166 = do_flow == 1'h0;
+ assign do_enq = T_1164 & T_1166;
+ assign T_1168 = io_deq_ready & io_deq_valid;
+ assign T_1170 = do_flow == 1'h0;
+ assign do_deq = T_1168 & T_1170;
+ assign T_1299 = T_1151 == 1'h1;
+ assign T_1301 = 1'h0 & T_1299;
+ assign T_1304 = T_1151 + 1'h1;
+ assign T_1305 = T_1304[0:0];
+ assign T_1306 = T_1301 ? 1'h0 : T_1305;
+ assign T_1308 = T_1153 == 1'h1;
+ assign T_1310 = 1'h0 & T_1308;
+ assign T_1313 = T_1153 + 1'h1;
+ assign T_1314 = T_1313[0:0];
+ assign T_1315 = T_1310 ? 1'h0 : T_1314;
+ assign T_1316 = do_enq != do_deq;
+ assign T_1318 = empty == 1'h0;
+ assign T_1320 = 1'h0 & io_enq_valid;
+ assign T_1321 = T_1318 | T_1320;
+ assign T_1323 = full == 1'h0;
+ assign T_1325 = 1'h0 & io_deq_ready;
+ assign T_1326 = T_1323 | T_1325;
+ assign T_1453_header_src = maybe_flow ? io_enq_bits_header_src : ram_header_src_T_1327_data;
+ assign T_1453_header_dst = maybe_flow ? io_enq_bits_header_dst : ram_header_dst_T_1327_data;
+ assign T_1453_payload_addr_beat = maybe_flow ? io_enq_bits_payload_addr_beat : ram_payload_addr_beat_T_1327_data;
+ assign T_1453_payload_addr_block = maybe_flow ? io_enq_bits_payload_addr_block : ram_payload_addr_block_T_1327_data;
+ assign T_1453_payload_client_xact_id = maybe_flow ? io_enq_bits_payload_client_xact_id : ram_payload_client_xact_id_T_1327_data;
+ assign T_1453_payload_voluntary = maybe_flow ? io_enq_bits_payload_voluntary : ram_payload_voluntary_T_1327_data;
+ assign T_1453_payload_r_type = maybe_flow ? io_enq_bits_payload_r_type : ram_payload_r_type_T_1327_data;
+ assign T_1453_payload_data = maybe_flow ? io_enq_bits_payload_data : ram_payload_data_T_1327_data;
+ assign T_1579 = T_1151 - T_1153;
+ assign ptr_diff = T_1579[0:0];
+ assign T_1581 = maybe_full & ptr_match;
+ assign T_1582 = {T_1581,ptr_diff};
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_header_src[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_header_dst[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_payload_addr_beat[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_payload_addr_block[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_payload_client_xact_id[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_payload_voluntary[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_payload_r_type[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_payload_data[initvar] = {4{$random}};
+ T_1151 = {1{$random}};
+ T_1153 = {1{$random}};
+ maybe_full = {1{$random}};
+ end
+`endif
+ always @(posedge ram_header_src_T_1172_clk) begin
+ if(ram_header_src_T_1172_en & ram_header_src_T_1172_mask) begin
+ ram_header_src[ram_header_src_T_1172_addr] <= ram_header_src_T_1172_data;
+ end
+ end
+ always @(posedge ram_header_dst_T_1172_clk) begin
+ if(ram_header_dst_T_1172_en & ram_header_dst_T_1172_mask) begin
+ ram_header_dst[ram_header_dst_T_1172_addr] <= ram_header_dst_T_1172_data;
+ end
+ end
+ always @(posedge ram_payload_addr_beat_T_1172_clk) begin
+ if(ram_payload_addr_beat_T_1172_en & ram_payload_addr_beat_T_1172_mask) begin
+ ram_payload_addr_beat[ram_payload_addr_beat_T_1172_addr] <= ram_payload_addr_beat_T_1172_data;
+ end
+ end
+ always @(posedge ram_payload_addr_block_T_1172_clk) begin
+ if(ram_payload_addr_block_T_1172_en & ram_payload_addr_block_T_1172_mask) begin
+ ram_payload_addr_block[ram_payload_addr_block_T_1172_addr] <= ram_payload_addr_block_T_1172_data;
+ end
+ end
+ always @(posedge ram_payload_client_xact_id_T_1172_clk) begin
+ if(ram_payload_client_xact_id_T_1172_en & ram_payload_client_xact_id_T_1172_mask) begin
+ ram_payload_client_xact_id[ram_payload_client_xact_id_T_1172_addr] <= ram_payload_client_xact_id_T_1172_data;
+ end
+ end
+ always @(posedge ram_payload_voluntary_T_1172_clk) begin
+ if(ram_payload_voluntary_T_1172_en & ram_payload_voluntary_T_1172_mask) begin
+ ram_payload_voluntary[ram_payload_voluntary_T_1172_addr] <= ram_payload_voluntary_T_1172_data;
+ end
+ end
+ always @(posedge ram_payload_r_type_T_1172_clk) begin
+ if(ram_payload_r_type_T_1172_en & ram_payload_r_type_T_1172_mask) begin
+ ram_payload_r_type[ram_payload_r_type_T_1172_addr] <= ram_payload_r_type_T_1172_data;
+ end
+ end
+ always @(posedge ram_payload_data_T_1172_clk) begin
+ if(ram_payload_data_T_1172_en & ram_payload_data_T_1172_mask) begin
+ ram_payload_data[ram_payload_data_T_1172_addr] <= ram_payload_data_T_1172_data;
+ end
+ end
+ always @(posedge clk) begin
+ if(reset) begin
+ T_1151 <= 1'h0;
+ end else begin
+ if(do_enq) begin
+ T_1151 <= T_1306;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_1153 <= 1'h0;
+ end else begin
+ if(do_deq) begin
+ T_1153 <= T_1315;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ maybe_full <= 1'h0;
+ end else begin
+ if(T_1316) begin
+ maybe_full <= do_enq;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module Queue_4(
+ input clk,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [1:0] io_enq_bits_header_src,
+ input [1:0] io_enq_bits_header_dst,
+ input [1:0] io_enq_bits_payload_addr_beat,
+ input [1:0] io_enq_bits_payload_client_xact_id,
+ input [3:0] io_enq_bits_payload_manager_xact_id,
+ input io_enq_bits_payload_is_builtin_type,
+ input [3:0] io_enq_bits_payload_g_type,
+ input [127:0] io_enq_bits_payload_data,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [1:0] io_deq_bits_header_src,
+ output [1:0] io_deq_bits_header_dst,
+ output [1:0] io_deq_bits_payload_addr_beat,
+ output [1:0] io_deq_bits_payload_client_xact_id,
+ output [3:0] io_deq_bits_payload_manager_xact_id,
+ output io_deq_bits_payload_is_builtin_type,
+ output [3:0] io_deq_bits_payload_g_type,
+ output [127:0] io_deq_bits_payload_data,
+ output [1:0] io_count
+);
+ reg [1:0] ram_header_src [0:1];
+ wire [1:0] ram_header_src_T_1327_data;
+ wire ram_header_src_T_1327_addr;
+ wire ram_header_src_T_1327_en;
+ wire ram_header_src_T_1327_clk;
+ wire [1:0] ram_header_src_T_1172_data;
+ wire ram_header_src_T_1172_addr;
+ wire ram_header_src_T_1172_mask;
+ wire ram_header_src_T_1172_en;
+ wire ram_header_src_T_1172_clk;
+ reg [1:0] ram_header_dst [0:1];
+ wire [1:0] ram_header_dst_T_1327_data;
+ wire ram_header_dst_T_1327_addr;
+ wire ram_header_dst_T_1327_en;
+ wire ram_header_dst_T_1327_clk;
+ wire [1:0] ram_header_dst_T_1172_data;
+ wire ram_header_dst_T_1172_addr;
+ wire ram_header_dst_T_1172_mask;
+ wire ram_header_dst_T_1172_en;
+ wire ram_header_dst_T_1172_clk;
+ reg [1:0] ram_payload_addr_beat [0:1];
+ wire [1:0] ram_payload_addr_beat_T_1327_data;
+ wire ram_payload_addr_beat_T_1327_addr;
+ wire ram_payload_addr_beat_T_1327_en;
+ wire ram_payload_addr_beat_T_1327_clk;
+ wire [1:0] ram_payload_addr_beat_T_1172_data;
+ wire ram_payload_addr_beat_T_1172_addr;
+ wire ram_payload_addr_beat_T_1172_mask;
+ wire ram_payload_addr_beat_T_1172_en;
+ wire ram_payload_addr_beat_T_1172_clk;
+ reg [1:0] ram_payload_client_xact_id [0:1];
+ wire [1:0] ram_payload_client_xact_id_T_1327_data;
+ wire ram_payload_client_xact_id_T_1327_addr;
+ wire ram_payload_client_xact_id_T_1327_en;
+ wire ram_payload_client_xact_id_T_1327_clk;
+ wire [1:0] ram_payload_client_xact_id_T_1172_data;
+ wire ram_payload_client_xact_id_T_1172_addr;
+ wire ram_payload_client_xact_id_T_1172_mask;
+ wire ram_payload_client_xact_id_T_1172_en;
+ wire ram_payload_client_xact_id_T_1172_clk;
+ reg [3:0] ram_payload_manager_xact_id [0:1];
+ wire [3:0] ram_payload_manager_xact_id_T_1327_data;
+ wire ram_payload_manager_xact_id_T_1327_addr;
+ wire ram_payload_manager_xact_id_T_1327_en;
+ wire ram_payload_manager_xact_id_T_1327_clk;
+ wire [3:0] ram_payload_manager_xact_id_T_1172_data;
+ wire ram_payload_manager_xact_id_T_1172_addr;
+ wire ram_payload_manager_xact_id_T_1172_mask;
+ wire ram_payload_manager_xact_id_T_1172_en;
+ wire ram_payload_manager_xact_id_T_1172_clk;
+ reg ram_payload_is_builtin_type [0:1];
+ wire ram_payload_is_builtin_type_T_1327_data;
+ wire ram_payload_is_builtin_type_T_1327_addr;
+ wire ram_payload_is_builtin_type_T_1327_en;
+ wire ram_payload_is_builtin_type_T_1327_clk;
+ wire ram_payload_is_builtin_type_T_1172_data;
+ wire ram_payload_is_builtin_type_T_1172_addr;
+ wire ram_payload_is_builtin_type_T_1172_mask;
+ wire ram_payload_is_builtin_type_T_1172_en;
+ wire ram_payload_is_builtin_type_T_1172_clk;
+ reg [3:0] ram_payload_g_type [0:1];
+ wire [3:0] ram_payload_g_type_T_1327_data;
+ wire ram_payload_g_type_T_1327_addr;
+ wire ram_payload_g_type_T_1327_en;
+ wire ram_payload_g_type_T_1327_clk;
+ wire [3:0] ram_payload_g_type_T_1172_data;
+ wire ram_payload_g_type_T_1172_addr;
+ wire ram_payload_g_type_T_1172_mask;
+ wire ram_payload_g_type_T_1172_en;
+ wire ram_payload_g_type_T_1172_clk;
+ reg [127:0] ram_payload_data [0:1];
+ wire [127:0] ram_payload_data_T_1327_data;
+ wire ram_payload_data_T_1327_addr;
+ wire ram_payload_data_T_1327_en;
+ wire ram_payload_data_T_1327_clk;
+ wire [127:0] ram_payload_data_T_1172_data;
+ wire ram_payload_data_T_1172_addr;
+ wire ram_payload_data_T_1172_mask;
+ wire ram_payload_data_T_1172_en;
+ wire ram_payload_data_T_1172_clk;
+ reg T_1151;
+ reg T_1153;
+ reg maybe_full;
+ wire ptr_match;
+ wire T_1158;
+ wire empty;
+ wire full;
+ wire maybe_flow;
+ wire do_flow;
+ wire T_1164;
+ wire T_1166;
+ wire do_enq;
+ wire T_1168;
+ wire T_1170;
+ wire do_deq;
+ wire T_1299;
+ wire T_1301;
+ wire [1:0] T_1304;
+ wire T_1305;
+ wire T_1306;
+ wire T_1308;
+ wire T_1310;
+ wire [1:0] T_1313;
+ wire T_1314;
+ wire T_1315;
+ wire T_1316;
+ wire T_1318;
+ wire T_1320;
+ wire T_1321;
+ wire T_1323;
+ wire T_1325;
+ wire T_1326;
+ wire [1:0] T_1453_header_src;
+ wire [1:0] T_1453_header_dst;
+ wire [1:0] T_1453_payload_addr_beat;
+ wire [1:0] T_1453_payload_client_xact_id;
+ wire [3:0] T_1453_payload_manager_xact_id;
+ wire T_1453_payload_is_builtin_type;
+ wire [3:0] T_1453_payload_g_type;
+ wire [127:0] T_1453_payload_data;
+ wire [1:0] T_1579;
+ wire ptr_diff;
+ wire T_1581;
+ wire [1:0] T_1582;
+ assign io_enq_ready = T_1326;
+ assign io_deq_valid = T_1321;
+ assign io_deq_bits_header_src = T_1453_header_src;
+ assign io_deq_bits_header_dst = T_1453_header_dst;
+ assign io_deq_bits_payload_addr_beat = T_1453_payload_addr_beat;
+ assign io_deq_bits_payload_client_xact_id = T_1453_payload_client_xact_id;
+ assign io_deq_bits_payload_manager_xact_id = T_1453_payload_manager_xact_id;
+ assign io_deq_bits_payload_is_builtin_type = T_1453_payload_is_builtin_type;
+ assign io_deq_bits_payload_g_type = T_1453_payload_g_type;
+ assign io_deq_bits_payload_data = T_1453_payload_data;
+ assign io_count = T_1582;
+ assign ram_header_src_T_1327_addr = T_1153;
+ assign ram_header_src_T_1327_en = 1'h1;
+ assign ram_header_src_T_1327_clk = clk;
+ assign ram_header_src_T_1327_data = ram_header_src[ram_header_src_T_1327_addr];
+ assign ram_header_src_T_1172_data = io_enq_bits_header_src;
+ assign ram_header_src_T_1172_addr = T_1151;
+ assign ram_header_src_T_1172_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_header_src_T_1172_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_header_src_T_1172_clk = clk;
+ assign ram_header_dst_T_1327_addr = T_1153;
+ assign ram_header_dst_T_1327_en = 1'h1;
+ assign ram_header_dst_T_1327_clk = clk;
+ assign ram_header_dst_T_1327_data = ram_header_dst[ram_header_dst_T_1327_addr];
+ assign ram_header_dst_T_1172_data = io_enq_bits_header_dst;
+ assign ram_header_dst_T_1172_addr = T_1151;
+ assign ram_header_dst_T_1172_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_header_dst_T_1172_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_header_dst_T_1172_clk = clk;
+ assign ram_payload_addr_beat_T_1327_addr = T_1153;
+ assign ram_payload_addr_beat_T_1327_en = 1'h1;
+ assign ram_payload_addr_beat_T_1327_clk = clk;
+ assign ram_payload_addr_beat_T_1327_data = ram_payload_addr_beat[ram_payload_addr_beat_T_1327_addr];
+ assign ram_payload_addr_beat_T_1172_data = io_enq_bits_payload_addr_beat;
+ assign ram_payload_addr_beat_T_1172_addr = T_1151;
+ assign ram_payload_addr_beat_T_1172_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_addr_beat_T_1172_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_addr_beat_T_1172_clk = clk;
+ assign ram_payload_client_xact_id_T_1327_addr = T_1153;
+ assign ram_payload_client_xact_id_T_1327_en = 1'h1;
+ assign ram_payload_client_xact_id_T_1327_clk = clk;
+ assign ram_payload_client_xact_id_T_1327_data = ram_payload_client_xact_id[ram_payload_client_xact_id_T_1327_addr];
+ assign ram_payload_client_xact_id_T_1172_data = io_enq_bits_payload_client_xact_id;
+ assign ram_payload_client_xact_id_T_1172_addr = T_1151;
+ assign ram_payload_client_xact_id_T_1172_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_client_xact_id_T_1172_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_client_xact_id_T_1172_clk = clk;
+ assign ram_payload_manager_xact_id_T_1327_addr = T_1153;
+ assign ram_payload_manager_xact_id_T_1327_en = 1'h1;
+ assign ram_payload_manager_xact_id_T_1327_clk = clk;
+ assign ram_payload_manager_xact_id_T_1327_data = ram_payload_manager_xact_id[ram_payload_manager_xact_id_T_1327_addr];
+ assign ram_payload_manager_xact_id_T_1172_data = io_enq_bits_payload_manager_xact_id;
+ assign ram_payload_manager_xact_id_T_1172_addr = T_1151;
+ assign ram_payload_manager_xact_id_T_1172_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_manager_xact_id_T_1172_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_manager_xact_id_T_1172_clk = clk;
+ assign ram_payload_is_builtin_type_T_1327_addr = T_1153;
+ assign ram_payload_is_builtin_type_T_1327_en = 1'h1;
+ assign ram_payload_is_builtin_type_T_1327_clk = clk;
+ assign ram_payload_is_builtin_type_T_1327_data = ram_payload_is_builtin_type[ram_payload_is_builtin_type_T_1327_addr];
+ assign ram_payload_is_builtin_type_T_1172_data = io_enq_bits_payload_is_builtin_type;
+ assign ram_payload_is_builtin_type_T_1172_addr = T_1151;
+ assign ram_payload_is_builtin_type_T_1172_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_is_builtin_type_T_1172_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_is_builtin_type_T_1172_clk = clk;
+ assign ram_payload_g_type_T_1327_addr = T_1153;
+ assign ram_payload_g_type_T_1327_en = 1'h1;
+ assign ram_payload_g_type_T_1327_clk = clk;
+ assign ram_payload_g_type_T_1327_data = ram_payload_g_type[ram_payload_g_type_T_1327_addr];
+ assign ram_payload_g_type_T_1172_data = io_enq_bits_payload_g_type;
+ assign ram_payload_g_type_T_1172_addr = T_1151;
+ assign ram_payload_g_type_T_1172_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_g_type_T_1172_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_g_type_T_1172_clk = clk;
+ assign ram_payload_data_T_1327_addr = T_1153;
+ assign ram_payload_data_T_1327_en = 1'h1;
+ assign ram_payload_data_T_1327_clk = clk;
+ assign ram_payload_data_T_1327_data = ram_payload_data[ram_payload_data_T_1327_addr];
+ assign ram_payload_data_T_1172_data = io_enq_bits_payload_data;
+ assign ram_payload_data_T_1172_addr = T_1151;
+ assign ram_payload_data_T_1172_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_data_T_1172_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_data_T_1172_clk = clk;
+ assign ptr_match = T_1151 == T_1153;
+ assign T_1158 = maybe_full == 1'h0;
+ assign empty = ptr_match & T_1158;
+ assign full = ptr_match & maybe_full;
+ assign maybe_flow = 1'h0 & empty;
+ assign do_flow = maybe_flow & io_deq_ready;
+ assign T_1164 = io_enq_ready & io_enq_valid;
+ assign T_1166 = do_flow == 1'h0;
+ assign do_enq = T_1164 & T_1166;
+ assign T_1168 = io_deq_ready & io_deq_valid;
+ assign T_1170 = do_flow == 1'h0;
+ assign do_deq = T_1168 & T_1170;
+ assign T_1299 = T_1151 == 1'h1;
+ assign T_1301 = 1'h0 & T_1299;
+ assign T_1304 = T_1151 + 1'h1;
+ assign T_1305 = T_1304[0:0];
+ assign T_1306 = T_1301 ? 1'h0 : T_1305;
+ assign T_1308 = T_1153 == 1'h1;
+ assign T_1310 = 1'h0 & T_1308;
+ assign T_1313 = T_1153 + 1'h1;
+ assign T_1314 = T_1313[0:0];
+ assign T_1315 = T_1310 ? 1'h0 : T_1314;
+ assign T_1316 = do_enq != do_deq;
+ assign T_1318 = empty == 1'h0;
+ assign T_1320 = 1'h0 & io_enq_valid;
+ assign T_1321 = T_1318 | T_1320;
+ assign T_1323 = full == 1'h0;
+ assign T_1325 = 1'h0 & io_deq_ready;
+ assign T_1326 = T_1323 | T_1325;
+ assign T_1453_header_src = maybe_flow ? io_enq_bits_header_src : ram_header_src_T_1327_data;
+ assign T_1453_header_dst = maybe_flow ? io_enq_bits_header_dst : ram_header_dst_T_1327_data;
+ assign T_1453_payload_addr_beat = maybe_flow ? io_enq_bits_payload_addr_beat : ram_payload_addr_beat_T_1327_data;
+ assign T_1453_payload_client_xact_id = maybe_flow ? io_enq_bits_payload_client_xact_id : ram_payload_client_xact_id_T_1327_data;
+ assign T_1453_payload_manager_xact_id = maybe_flow ? io_enq_bits_payload_manager_xact_id : ram_payload_manager_xact_id_T_1327_data;
+ assign T_1453_payload_is_builtin_type = maybe_flow ? io_enq_bits_payload_is_builtin_type : ram_payload_is_builtin_type_T_1327_data;
+ assign T_1453_payload_g_type = maybe_flow ? io_enq_bits_payload_g_type : ram_payload_g_type_T_1327_data;
+ assign T_1453_payload_data = maybe_flow ? io_enq_bits_payload_data : ram_payload_data_T_1327_data;
+ assign T_1579 = T_1151 - T_1153;
+ assign ptr_diff = T_1579[0:0];
+ assign T_1581 = maybe_full & ptr_match;
+ assign T_1582 = {T_1581,ptr_diff};
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_header_src[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_header_dst[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_payload_addr_beat[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_payload_client_xact_id[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_payload_manager_xact_id[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_payload_is_builtin_type[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_payload_g_type[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_payload_data[initvar] = {4{$random}};
+ T_1151 = {1{$random}};
+ T_1153 = {1{$random}};
+ maybe_full = {1{$random}};
+ end
+`endif
+ always @(posedge ram_header_src_T_1172_clk) begin
+ if(ram_header_src_T_1172_en & ram_header_src_T_1172_mask) begin
+ ram_header_src[ram_header_src_T_1172_addr] <= ram_header_src_T_1172_data;
+ end
+ end
+ always @(posedge ram_header_dst_T_1172_clk) begin
+ if(ram_header_dst_T_1172_en & ram_header_dst_T_1172_mask) begin
+ ram_header_dst[ram_header_dst_T_1172_addr] <= ram_header_dst_T_1172_data;
+ end
+ end
+ always @(posedge ram_payload_addr_beat_T_1172_clk) begin
+ if(ram_payload_addr_beat_T_1172_en & ram_payload_addr_beat_T_1172_mask) begin
+ ram_payload_addr_beat[ram_payload_addr_beat_T_1172_addr] <= ram_payload_addr_beat_T_1172_data;
+ end
+ end
+ always @(posedge ram_payload_client_xact_id_T_1172_clk) begin
+ if(ram_payload_client_xact_id_T_1172_en & ram_payload_client_xact_id_T_1172_mask) begin
+ ram_payload_client_xact_id[ram_payload_client_xact_id_T_1172_addr] <= ram_payload_client_xact_id_T_1172_data;
+ end
+ end
+ always @(posedge ram_payload_manager_xact_id_T_1172_clk) begin
+ if(ram_payload_manager_xact_id_T_1172_en & ram_payload_manager_xact_id_T_1172_mask) begin
+ ram_payload_manager_xact_id[ram_payload_manager_xact_id_T_1172_addr] <= ram_payload_manager_xact_id_T_1172_data;
+ end
+ end
+ always @(posedge ram_payload_is_builtin_type_T_1172_clk) begin
+ if(ram_payload_is_builtin_type_T_1172_en & ram_payload_is_builtin_type_T_1172_mask) begin
+ ram_payload_is_builtin_type[ram_payload_is_builtin_type_T_1172_addr] <= ram_payload_is_builtin_type_T_1172_data;
+ end
+ end
+ always @(posedge ram_payload_g_type_T_1172_clk) begin
+ if(ram_payload_g_type_T_1172_en & ram_payload_g_type_T_1172_mask) begin
+ ram_payload_g_type[ram_payload_g_type_T_1172_addr] <= ram_payload_g_type_T_1172_data;
+ end
+ end
+ always @(posedge ram_payload_data_T_1172_clk) begin
+ if(ram_payload_data_T_1172_en & ram_payload_data_T_1172_mask) begin
+ ram_payload_data[ram_payload_data_T_1172_addr] <= ram_payload_data_T_1172_data;
+ end
+ end
+ always @(posedge clk) begin
+ if(reset) begin
+ T_1151 <= 1'h0;
+ end else begin
+ if(do_enq) begin
+ T_1151 <= T_1306;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_1153 <= 1'h0;
+ end else begin
+ if(do_deq) begin
+ T_1153 <= T_1315;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ maybe_full <= 1'h0;
+ end else begin
+ if(T_1316) begin
+ maybe_full <= do_enq;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module Queue_5(
+ input clk,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [1:0] io_enq_bits_header_src,
+ input [1:0] io_enq_bits_header_dst,
+ input [3:0] io_enq_bits_payload_manager_xact_id,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [1:0] io_deq_bits_header_src,
+ output [1:0] io_deq_bits_header_dst,
+ output [3:0] io_deq_bits_payload_manager_xact_id,
+ output [1:0] io_count
+);
+ reg [1:0] ram_header_src [0:1];
+ wire [1:0] ram_header_src_T_1277_data;
+ wire ram_header_src_T_1277_addr;
+ wire ram_header_src_T_1277_en;
+ wire ram_header_src_T_1277_clk;
+ wire [1:0] ram_header_src_T_1127_data;
+ wire ram_header_src_T_1127_addr;
+ wire ram_header_src_T_1127_mask;
+ wire ram_header_src_T_1127_en;
+ wire ram_header_src_T_1127_clk;
+ reg [1:0] ram_header_dst [0:1];
+ wire [1:0] ram_header_dst_T_1277_data;
+ wire ram_header_dst_T_1277_addr;
+ wire ram_header_dst_T_1277_en;
+ wire ram_header_dst_T_1277_clk;
+ wire [1:0] ram_header_dst_T_1127_data;
+ wire ram_header_dst_T_1127_addr;
+ wire ram_header_dst_T_1127_mask;
+ wire ram_header_dst_T_1127_en;
+ wire ram_header_dst_T_1127_clk;
+ reg [3:0] ram_payload_manager_xact_id [0:1];
+ wire [3:0] ram_payload_manager_xact_id_T_1277_data;
+ wire ram_payload_manager_xact_id_T_1277_addr;
+ wire ram_payload_manager_xact_id_T_1277_en;
+ wire ram_payload_manager_xact_id_T_1277_clk;
+ wire [3:0] ram_payload_manager_xact_id_T_1127_data;
+ wire ram_payload_manager_xact_id_T_1127_addr;
+ wire ram_payload_manager_xact_id_T_1127_mask;
+ wire ram_payload_manager_xact_id_T_1127_en;
+ wire ram_payload_manager_xact_id_T_1127_clk;
+ reg T_1106;
+ reg T_1108;
+ reg maybe_full;
+ wire ptr_match;
+ wire T_1113;
+ wire empty;
+ wire full;
+ wire maybe_flow;
+ wire do_flow;
+ wire T_1119;
+ wire T_1121;
+ wire do_enq;
+ wire T_1123;
+ wire T_1125;
+ wire do_deq;
+ wire T_1249;
+ wire T_1251;
+ wire [1:0] T_1254;
+ wire T_1255;
+ wire T_1256;
+ wire T_1258;
+ wire T_1260;
+ wire [1:0] T_1263;
+ wire T_1264;
+ wire T_1265;
+ wire T_1266;
+ wire T_1268;
+ wire T_1270;
+ wire T_1271;
+ wire T_1273;
+ wire T_1275;
+ wire T_1276;
+ wire [1:0] T_1398_header_src;
+ wire [1:0] T_1398_header_dst;
+ wire [3:0] T_1398_payload_manager_xact_id;
+ wire [1:0] T_1519;
+ wire ptr_diff;
+ wire T_1521;
+ wire [1:0] T_1522;
+ assign io_enq_ready = T_1276;
+ assign io_deq_valid = T_1271;
+ assign io_deq_bits_header_src = T_1398_header_src;
+ assign io_deq_bits_header_dst = T_1398_header_dst;
+ assign io_deq_bits_payload_manager_xact_id = T_1398_payload_manager_xact_id;
+ assign io_count = T_1522;
+ assign ram_header_src_T_1277_addr = T_1108;
+ assign ram_header_src_T_1277_en = 1'h1;
+ assign ram_header_src_T_1277_clk = clk;
+ assign ram_header_src_T_1277_data = ram_header_src[ram_header_src_T_1277_addr];
+ assign ram_header_src_T_1127_data = io_enq_bits_header_src;
+ assign ram_header_src_T_1127_addr = T_1106;
+ assign ram_header_src_T_1127_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_header_src_T_1127_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_header_src_T_1127_clk = clk;
+ assign ram_header_dst_T_1277_addr = T_1108;
+ assign ram_header_dst_T_1277_en = 1'h1;
+ assign ram_header_dst_T_1277_clk = clk;
+ assign ram_header_dst_T_1277_data = ram_header_dst[ram_header_dst_T_1277_addr];
+ assign ram_header_dst_T_1127_data = io_enq_bits_header_dst;
+ assign ram_header_dst_T_1127_addr = T_1106;
+ assign ram_header_dst_T_1127_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_header_dst_T_1127_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_header_dst_T_1127_clk = clk;
+ assign ram_payload_manager_xact_id_T_1277_addr = T_1108;
+ assign ram_payload_manager_xact_id_T_1277_en = 1'h1;
+ assign ram_payload_manager_xact_id_T_1277_clk = clk;
+ assign ram_payload_manager_xact_id_T_1277_data = ram_payload_manager_xact_id[ram_payload_manager_xact_id_T_1277_addr];
+ assign ram_payload_manager_xact_id_T_1127_data = io_enq_bits_payload_manager_xact_id;
+ assign ram_payload_manager_xact_id_T_1127_addr = T_1106;
+ assign ram_payload_manager_xact_id_T_1127_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_manager_xact_id_T_1127_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_manager_xact_id_T_1127_clk = clk;
+ assign ptr_match = T_1106 == T_1108;
+ assign T_1113 = maybe_full == 1'h0;
+ assign empty = ptr_match & T_1113;
+ assign full = ptr_match & maybe_full;
+ assign maybe_flow = 1'h0 & empty;
+ assign do_flow = maybe_flow & io_deq_ready;
+ assign T_1119 = io_enq_ready & io_enq_valid;
+ assign T_1121 = do_flow == 1'h0;
+ assign do_enq = T_1119 & T_1121;
+ assign T_1123 = io_deq_ready & io_deq_valid;
+ assign T_1125 = do_flow == 1'h0;
+ assign do_deq = T_1123 & T_1125;
+ assign T_1249 = T_1106 == 1'h1;
+ assign T_1251 = 1'h0 & T_1249;
+ assign T_1254 = T_1106 + 1'h1;
+ assign T_1255 = T_1254[0:0];
+ assign T_1256 = T_1251 ? 1'h0 : T_1255;
+ assign T_1258 = T_1108 == 1'h1;
+ assign T_1260 = 1'h0 & T_1258;
+ assign T_1263 = T_1108 + 1'h1;
+ assign T_1264 = T_1263[0:0];
+ assign T_1265 = T_1260 ? 1'h0 : T_1264;
+ assign T_1266 = do_enq != do_deq;
+ assign T_1268 = empty == 1'h0;
+ assign T_1270 = 1'h0 & io_enq_valid;
+ assign T_1271 = T_1268 | T_1270;
+ assign T_1273 = full == 1'h0;
+ assign T_1275 = 1'h0 & io_deq_ready;
+ assign T_1276 = T_1273 | T_1275;
+ assign T_1398_header_src = maybe_flow ? io_enq_bits_header_src : ram_header_src_T_1277_data;
+ assign T_1398_header_dst = maybe_flow ? io_enq_bits_header_dst : ram_header_dst_T_1277_data;
+ assign T_1398_payload_manager_xact_id = maybe_flow ? io_enq_bits_payload_manager_xact_id : ram_payload_manager_xact_id_T_1277_data;
+ assign T_1519 = T_1106 - T_1108;
+ assign ptr_diff = T_1519[0:0];
+ assign T_1521 = maybe_full & ptr_match;
+ assign T_1522 = {T_1521,ptr_diff};
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_header_src[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_header_dst[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_payload_manager_xact_id[initvar] = {1{$random}};
+ T_1106 = {1{$random}};
+ T_1108 = {1{$random}};
+ maybe_full = {1{$random}};
+ end
+`endif
+ always @(posedge ram_header_src_T_1127_clk) begin
+ if(ram_header_src_T_1127_en & ram_header_src_T_1127_mask) begin
+ ram_header_src[ram_header_src_T_1127_addr] <= ram_header_src_T_1127_data;
+ end
+ end
+ always @(posedge ram_header_dst_T_1127_clk) begin
+ if(ram_header_dst_T_1127_en & ram_header_dst_T_1127_mask) begin
+ ram_header_dst[ram_header_dst_T_1127_addr] <= ram_header_dst_T_1127_data;
+ end
+ end
+ always @(posedge ram_payload_manager_xact_id_T_1127_clk) begin
+ if(ram_payload_manager_xact_id_T_1127_en & ram_payload_manager_xact_id_T_1127_mask) begin
+ ram_payload_manager_xact_id[ram_payload_manager_xact_id_T_1127_addr] <= ram_payload_manager_xact_id_T_1127_data;
+ end
+ end
+ always @(posedge clk) begin
+ if(reset) begin
+ T_1106 <= 1'h0;
+ end else begin
+ if(do_enq) begin
+ T_1106 <= T_1256;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_1108 <= 1'h0;
+ end else begin
+ if(do_deq) begin
+ T_1108 <= T_1265;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ maybe_full <= 1'h0;
+ end else begin
+ if(T_1266) begin
+ maybe_full <= do_enq;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module TileLinkEnqueuer(
+ input clk,
+ input reset,
+ output io_client_acquire_ready,
+ input io_client_acquire_valid,
+ input [1:0] io_client_acquire_bits_header_src,
+ input [1:0] io_client_acquire_bits_header_dst,
+ input [25:0] io_client_acquire_bits_payload_addr_block,
+ input [1:0] io_client_acquire_bits_payload_client_xact_id,
+ input [1:0] io_client_acquire_bits_payload_addr_beat,
+ input io_client_acquire_bits_payload_is_builtin_type,
+ input [2:0] io_client_acquire_bits_payload_a_type,
+ input [16:0] io_client_acquire_bits_payload_union,
+ input [127:0] io_client_acquire_bits_payload_data,
+ input io_client_grant_ready,
+ output io_client_grant_valid,
+ output [1:0] io_client_grant_bits_header_src,
+ output [1:0] io_client_grant_bits_header_dst,
+ output [1:0] io_client_grant_bits_payload_addr_beat,
+ output [1:0] io_client_grant_bits_payload_client_xact_id,
+ output [3:0] io_client_grant_bits_payload_manager_xact_id,
+ output io_client_grant_bits_payload_is_builtin_type,
+ output [3:0] io_client_grant_bits_payload_g_type,
+ output [127:0] io_client_grant_bits_payload_data,
+ output io_client_finish_ready,
+ input io_client_finish_valid,
+ input [1:0] io_client_finish_bits_header_src,
+ input [1:0] io_client_finish_bits_header_dst,
+ input [3:0] io_client_finish_bits_payload_manager_xact_id,
+ input io_client_probe_ready,
+ output io_client_probe_valid,
+ output [1:0] io_client_probe_bits_header_src,
+ output [1:0] io_client_probe_bits_header_dst,
+ output [25:0] io_client_probe_bits_payload_addr_block,
+ output [1:0] io_client_probe_bits_payload_p_type,
+ output io_client_release_ready,
+ input io_client_release_valid,
+ input [1:0] io_client_release_bits_header_src,
+ input [1:0] io_client_release_bits_header_dst,
+ input [1:0] io_client_release_bits_payload_addr_beat,
+ input [25:0] io_client_release_bits_payload_addr_block,
+ input [1:0] io_client_release_bits_payload_client_xact_id,
+ input io_client_release_bits_payload_voluntary,
+ input [2:0] io_client_release_bits_payload_r_type,
+ input [127:0] io_client_release_bits_payload_data,
+ input io_manager_acquire_ready,
+ output io_manager_acquire_valid,
+ output [1:0] io_manager_acquire_bits_header_src,
+ output [1:0] io_manager_acquire_bits_header_dst,
+ output [25:0] io_manager_acquire_bits_payload_addr_block,
+ output [1:0] io_manager_acquire_bits_payload_client_xact_id,
+ output [1:0] io_manager_acquire_bits_payload_addr_beat,
+ output io_manager_acquire_bits_payload_is_builtin_type,
+ output [2:0] io_manager_acquire_bits_payload_a_type,
+ output [16:0] io_manager_acquire_bits_payload_union,
+ output [127:0] io_manager_acquire_bits_payload_data,
+ output io_manager_grant_ready,
+ input io_manager_grant_valid,
+ input [1:0] io_manager_grant_bits_header_src,
+ input [1:0] io_manager_grant_bits_header_dst,
+ input [1:0] io_manager_grant_bits_payload_addr_beat,
+ input [1:0] io_manager_grant_bits_payload_client_xact_id,
+ input [3:0] io_manager_grant_bits_payload_manager_xact_id,
+ input io_manager_grant_bits_payload_is_builtin_type,
+ input [3:0] io_manager_grant_bits_payload_g_type,
+ input [127:0] io_manager_grant_bits_payload_data,
+ input io_manager_finish_ready,
+ output io_manager_finish_valid,
+ output [1:0] io_manager_finish_bits_header_src,
+ output [1:0] io_manager_finish_bits_header_dst,
+ output [3:0] io_manager_finish_bits_payload_manager_xact_id,
+ output io_manager_probe_ready,
+ input io_manager_probe_valid,
+ input [1:0] io_manager_probe_bits_header_src,
+ input [1:0] io_manager_probe_bits_header_dst,
+ input [25:0] io_manager_probe_bits_payload_addr_block,
+ input [1:0] io_manager_probe_bits_payload_p_type,
+ input io_manager_release_ready,
+ output io_manager_release_valid,
+ output [1:0] io_manager_release_bits_header_src,
+ output [1:0] io_manager_release_bits_header_dst,
+ output [1:0] io_manager_release_bits_payload_addr_beat,
+ output [25:0] io_manager_release_bits_payload_addr_block,
+ output [1:0] io_manager_release_bits_payload_client_xact_id,
+ output io_manager_release_bits_payload_voluntary,
+ output [2:0] io_manager_release_bits_payload_r_type,
+ output [127:0] io_manager_release_bits_payload_data
+);
+ wire T_7778_clk;
+ wire T_7778_reset;
+ wire T_7778_io_enq_ready;
+ wire T_7778_io_enq_valid;
+ wire [1:0] T_7778_io_enq_bits_header_src;
+ wire [1:0] T_7778_io_enq_bits_header_dst;
+ wire [25:0] T_7778_io_enq_bits_payload_addr_block;
+ wire [1:0] T_7778_io_enq_bits_payload_client_xact_id;
+ wire [1:0] T_7778_io_enq_bits_payload_addr_beat;
+ wire T_7778_io_enq_bits_payload_is_builtin_type;
+ wire [2:0] T_7778_io_enq_bits_payload_a_type;
+ wire [16:0] T_7778_io_enq_bits_payload_union;
+ wire [127:0] T_7778_io_enq_bits_payload_data;
+ wire T_7778_io_deq_ready;
+ wire T_7778_io_deq_valid;
+ wire [1:0] T_7778_io_deq_bits_header_src;
+ wire [1:0] T_7778_io_deq_bits_header_dst;
+ wire [25:0] T_7778_io_deq_bits_payload_addr_block;
+ wire [1:0] T_7778_io_deq_bits_payload_client_xact_id;
+ wire [1:0] T_7778_io_deq_bits_payload_addr_beat;
+ wire T_7778_io_deq_bits_payload_is_builtin_type;
+ wire [2:0] T_7778_io_deq_bits_payload_a_type;
+ wire [16:0] T_7778_io_deq_bits_payload_union;
+ wire [127:0] T_7778_io_deq_bits_payload_data;
+ wire [1:0] T_7778_io_count;
+ wire T_7901_clk;
+ wire T_7901_reset;
+ wire T_7901_io_enq_ready;
+ wire T_7901_io_enq_valid;
+ wire [1:0] T_7901_io_enq_bits_header_src;
+ wire [1:0] T_7901_io_enq_bits_header_dst;
+ wire [25:0] T_7901_io_enq_bits_payload_addr_block;
+ wire [1:0] T_7901_io_enq_bits_payload_p_type;
+ wire T_7901_io_deq_ready;
+ wire T_7901_io_deq_valid;
+ wire [1:0] T_7901_io_deq_bits_header_src;
+ wire [1:0] T_7901_io_deq_bits_header_dst;
+ wire [25:0] T_7901_io_deq_bits_payload_addr_block;
+ wire [1:0] T_7901_io_deq_bits_payload_p_type;
+ wire [1:0] T_7901_io_count;
+ wire T_8028_clk;
+ wire T_8028_reset;
+ wire T_8028_io_enq_ready;
+ wire T_8028_io_enq_valid;
+ wire [1:0] T_8028_io_enq_bits_header_src;
+ wire [1:0] T_8028_io_enq_bits_header_dst;
+ wire [1:0] T_8028_io_enq_bits_payload_addr_beat;
+ wire [25:0] T_8028_io_enq_bits_payload_addr_block;
+ wire [1:0] T_8028_io_enq_bits_payload_client_xact_id;
+ wire T_8028_io_enq_bits_payload_voluntary;
+ wire [2:0] T_8028_io_enq_bits_payload_r_type;
+ wire [127:0] T_8028_io_enq_bits_payload_data;
+ wire T_8028_io_deq_ready;
+ wire T_8028_io_deq_valid;
+ wire [1:0] T_8028_io_deq_bits_header_src;
+ wire [1:0] T_8028_io_deq_bits_header_dst;
+ wire [1:0] T_8028_io_deq_bits_payload_addr_beat;
+ wire [25:0] T_8028_io_deq_bits_payload_addr_block;
+ wire [1:0] T_8028_io_deq_bits_payload_client_xact_id;
+ wire T_8028_io_deq_bits_payload_voluntary;
+ wire [2:0] T_8028_io_deq_bits_payload_r_type;
+ wire [127:0] T_8028_io_deq_bits_payload_data;
+ wire [1:0] T_8028_io_count;
+ wire T_8155_clk;
+ wire T_8155_reset;
+ wire T_8155_io_enq_ready;
+ wire T_8155_io_enq_valid;
+ wire [1:0] T_8155_io_enq_bits_header_src;
+ wire [1:0] T_8155_io_enq_bits_header_dst;
+ wire [1:0] T_8155_io_enq_bits_payload_addr_beat;
+ wire [1:0] T_8155_io_enq_bits_payload_client_xact_id;
+ wire [3:0] T_8155_io_enq_bits_payload_manager_xact_id;
+ wire T_8155_io_enq_bits_payload_is_builtin_type;
+ wire [3:0] T_8155_io_enq_bits_payload_g_type;
+ wire [127:0] T_8155_io_enq_bits_payload_data;
+ wire T_8155_io_deq_ready;
+ wire T_8155_io_deq_valid;
+ wire [1:0] T_8155_io_deq_bits_header_src;
+ wire [1:0] T_8155_io_deq_bits_header_dst;
+ wire [1:0] T_8155_io_deq_bits_payload_addr_beat;
+ wire [1:0] T_8155_io_deq_bits_payload_client_xact_id;
+ wire [3:0] T_8155_io_deq_bits_payload_manager_xact_id;
+ wire T_8155_io_deq_bits_payload_is_builtin_type;
+ wire [3:0] T_8155_io_deq_bits_payload_g_type;
+ wire [127:0] T_8155_io_deq_bits_payload_data;
+ wire [1:0] T_8155_io_count;
+ wire T_8277_clk;
+ wire T_8277_reset;
+ wire T_8277_io_enq_ready;
+ wire T_8277_io_enq_valid;
+ wire [1:0] T_8277_io_enq_bits_header_src;
+ wire [1:0] T_8277_io_enq_bits_header_dst;
+ wire [3:0] T_8277_io_enq_bits_payload_manager_xact_id;
+ wire T_8277_io_deq_ready;
+ wire T_8277_io_deq_valid;
+ wire [1:0] T_8277_io_deq_bits_header_src;
+ wire [1:0] T_8277_io_deq_bits_header_dst;
+ wire [3:0] T_8277_io_deq_bits_payload_manager_xact_id;
+ wire [1:0] T_8277_io_count;
+ Queue T_7778 (
+ .clk(T_7778_clk),
+ .reset(T_7778_reset),
+ .io_enq_ready(T_7778_io_enq_ready),
+ .io_enq_valid(T_7778_io_enq_valid),
+ .io_enq_bits_header_src(T_7778_io_enq_bits_header_src),
+ .io_enq_bits_header_dst(T_7778_io_enq_bits_header_dst),
+ .io_enq_bits_payload_addr_block(T_7778_io_enq_bits_payload_addr_block),
+ .io_enq_bits_payload_client_xact_id(T_7778_io_enq_bits_payload_client_xact_id),
+ .io_enq_bits_payload_addr_beat(T_7778_io_enq_bits_payload_addr_beat),
+ .io_enq_bits_payload_is_builtin_type(T_7778_io_enq_bits_payload_is_builtin_type),
+ .io_enq_bits_payload_a_type(T_7778_io_enq_bits_payload_a_type),
+ .io_enq_bits_payload_union(T_7778_io_enq_bits_payload_union),
+ .io_enq_bits_payload_data(T_7778_io_enq_bits_payload_data),
+ .io_deq_ready(T_7778_io_deq_ready),
+ .io_deq_valid(T_7778_io_deq_valid),
+ .io_deq_bits_header_src(T_7778_io_deq_bits_header_src),
+ .io_deq_bits_header_dst(T_7778_io_deq_bits_header_dst),
+ .io_deq_bits_payload_addr_block(T_7778_io_deq_bits_payload_addr_block),
+ .io_deq_bits_payload_client_xact_id(T_7778_io_deq_bits_payload_client_xact_id),
+ .io_deq_bits_payload_addr_beat(T_7778_io_deq_bits_payload_addr_beat),
+ .io_deq_bits_payload_is_builtin_type(T_7778_io_deq_bits_payload_is_builtin_type),
+ .io_deq_bits_payload_a_type(T_7778_io_deq_bits_payload_a_type),
+ .io_deq_bits_payload_union(T_7778_io_deq_bits_payload_union),
+ .io_deq_bits_payload_data(T_7778_io_deq_bits_payload_data),
+ .io_count(T_7778_io_count)
+ );
+ Queue_2 T_7901 (
+ .clk(T_7901_clk),
+ .reset(T_7901_reset),
+ .io_enq_ready(T_7901_io_enq_ready),
+ .io_enq_valid(T_7901_io_enq_valid),
+ .io_enq_bits_header_src(T_7901_io_enq_bits_header_src),
+ .io_enq_bits_header_dst(T_7901_io_enq_bits_header_dst),
+ .io_enq_bits_payload_addr_block(T_7901_io_enq_bits_payload_addr_block),
+ .io_enq_bits_payload_p_type(T_7901_io_enq_bits_payload_p_type),
+ .io_deq_ready(T_7901_io_deq_ready),
+ .io_deq_valid(T_7901_io_deq_valid),
+ .io_deq_bits_header_src(T_7901_io_deq_bits_header_src),
+ .io_deq_bits_header_dst(T_7901_io_deq_bits_header_dst),
+ .io_deq_bits_payload_addr_block(T_7901_io_deq_bits_payload_addr_block),
+ .io_deq_bits_payload_p_type(T_7901_io_deq_bits_payload_p_type),
+ .io_count(T_7901_io_count)
+ );
+ Queue_3 T_8028 (
+ .clk(T_8028_clk),
+ .reset(T_8028_reset),
+ .io_enq_ready(T_8028_io_enq_ready),
+ .io_enq_valid(T_8028_io_enq_valid),
+ .io_enq_bits_header_src(T_8028_io_enq_bits_header_src),
+ .io_enq_bits_header_dst(T_8028_io_enq_bits_header_dst),
+ .io_enq_bits_payload_addr_beat(T_8028_io_enq_bits_payload_addr_beat),
+ .io_enq_bits_payload_addr_block(T_8028_io_enq_bits_payload_addr_block),
+ .io_enq_bits_payload_client_xact_id(T_8028_io_enq_bits_payload_client_xact_id),
+ .io_enq_bits_payload_voluntary(T_8028_io_enq_bits_payload_voluntary),
+ .io_enq_bits_payload_r_type(T_8028_io_enq_bits_payload_r_type),
+ .io_enq_bits_payload_data(T_8028_io_enq_bits_payload_data),
+ .io_deq_ready(T_8028_io_deq_ready),
+ .io_deq_valid(T_8028_io_deq_valid),
+ .io_deq_bits_header_src(T_8028_io_deq_bits_header_src),
+ .io_deq_bits_header_dst(T_8028_io_deq_bits_header_dst),
+ .io_deq_bits_payload_addr_beat(T_8028_io_deq_bits_payload_addr_beat),
+ .io_deq_bits_payload_addr_block(T_8028_io_deq_bits_payload_addr_block),
+ .io_deq_bits_payload_client_xact_id(T_8028_io_deq_bits_payload_client_xact_id),
+ .io_deq_bits_payload_voluntary(T_8028_io_deq_bits_payload_voluntary),
+ .io_deq_bits_payload_r_type(T_8028_io_deq_bits_payload_r_type),
+ .io_deq_bits_payload_data(T_8028_io_deq_bits_payload_data),
+ .io_count(T_8028_io_count)
+ );
+ Queue_4 T_8155 (
+ .clk(T_8155_clk),
+ .reset(T_8155_reset),
+ .io_enq_ready(T_8155_io_enq_ready),
+ .io_enq_valid(T_8155_io_enq_valid),
+ .io_enq_bits_header_src(T_8155_io_enq_bits_header_src),
+ .io_enq_bits_header_dst(T_8155_io_enq_bits_header_dst),
+ .io_enq_bits_payload_addr_beat(T_8155_io_enq_bits_payload_addr_beat),
+ .io_enq_bits_payload_client_xact_id(T_8155_io_enq_bits_payload_client_xact_id),
+ .io_enq_bits_payload_manager_xact_id(T_8155_io_enq_bits_payload_manager_xact_id),
+ .io_enq_bits_payload_is_builtin_type(T_8155_io_enq_bits_payload_is_builtin_type),
+ .io_enq_bits_payload_g_type(T_8155_io_enq_bits_payload_g_type),
+ .io_enq_bits_payload_data(T_8155_io_enq_bits_payload_data),
+ .io_deq_ready(T_8155_io_deq_ready),
+ .io_deq_valid(T_8155_io_deq_valid),
+ .io_deq_bits_header_src(T_8155_io_deq_bits_header_src),
+ .io_deq_bits_header_dst(T_8155_io_deq_bits_header_dst),
+ .io_deq_bits_payload_addr_beat(T_8155_io_deq_bits_payload_addr_beat),
+ .io_deq_bits_payload_client_xact_id(T_8155_io_deq_bits_payload_client_xact_id),
+ .io_deq_bits_payload_manager_xact_id(T_8155_io_deq_bits_payload_manager_xact_id),
+ .io_deq_bits_payload_is_builtin_type(T_8155_io_deq_bits_payload_is_builtin_type),
+ .io_deq_bits_payload_g_type(T_8155_io_deq_bits_payload_g_type),
+ .io_deq_bits_payload_data(T_8155_io_deq_bits_payload_data),
+ .io_count(T_8155_io_count)
+ );
+ Queue_5 T_8277 (
+ .clk(T_8277_clk),
+ .reset(T_8277_reset),
+ .io_enq_ready(T_8277_io_enq_ready),
+ .io_enq_valid(T_8277_io_enq_valid),
+ .io_enq_bits_header_src(T_8277_io_enq_bits_header_src),
+ .io_enq_bits_header_dst(T_8277_io_enq_bits_header_dst),
+ .io_enq_bits_payload_manager_xact_id(T_8277_io_enq_bits_payload_manager_xact_id),
+ .io_deq_ready(T_8277_io_deq_ready),
+ .io_deq_valid(T_8277_io_deq_valid),
+ .io_deq_bits_header_src(T_8277_io_deq_bits_header_src),
+ .io_deq_bits_header_dst(T_8277_io_deq_bits_header_dst),
+ .io_deq_bits_payload_manager_xact_id(T_8277_io_deq_bits_payload_manager_xact_id),
+ .io_count(T_8277_io_count)
+ );
+ assign io_client_acquire_ready = T_7778_io_enq_ready;
+ assign io_client_grant_valid = T_8155_io_deq_valid;
+ assign io_client_grant_bits_header_src = T_8155_io_deq_bits_header_src;
+ assign io_client_grant_bits_header_dst = T_8155_io_deq_bits_header_dst;
+ assign io_client_grant_bits_payload_addr_beat = T_8155_io_deq_bits_payload_addr_beat;
+ assign io_client_grant_bits_payload_client_xact_id = T_8155_io_deq_bits_payload_client_xact_id;
+ assign io_client_grant_bits_payload_manager_xact_id = T_8155_io_deq_bits_payload_manager_xact_id;
+ assign io_client_grant_bits_payload_is_builtin_type = T_8155_io_deq_bits_payload_is_builtin_type;
+ assign io_client_grant_bits_payload_g_type = T_8155_io_deq_bits_payload_g_type;
+ assign io_client_grant_bits_payload_data = T_8155_io_deq_bits_payload_data;
+ assign io_client_finish_ready = T_8277_io_enq_ready;
+ assign io_client_probe_valid = T_7901_io_deq_valid;
+ assign io_client_probe_bits_header_src = T_7901_io_deq_bits_header_src;
+ assign io_client_probe_bits_header_dst = T_7901_io_deq_bits_header_dst;
+ assign io_client_probe_bits_payload_addr_block = T_7901_io_deq_bits_payload_addr_block;
+ assign io_client_probe_bits_payload_p_type = T_7901_io_deq_bits_payload_p_type;
+ assign io_client_release_ready = T_8028_io_enq_ready;
+ assign io_manager_acquire_valid = T_7778_io_deq_valid;
+ assign io_manager_acquire_bits_header_src = T_7778_io_deq_bits_header_src;
+ assign io_manager_acquire_bits_header_dst = T_7778_io_deq_bits_header_dst;
+ assign io_manager_acquire_bits_payload_addr_block = T_7778_io_deq_bits_payload_addr_block;
+ assign io_manager_acquire_bits_payload_client_xact_id = T_7778_io_deq_bits_payload_client_xact_id;
+ assign io_manager_acquire_bits_payload_addr_beat = T_7778_io_deq_bits_payload_addr_beat;
+ assign io_manager_acquire_bits_payload_is_builtin_type = T_7778_io_deq_bits_payload_is_builtin_type;
+ assign io_manager_acquire_bits_payload_a_type = T_7778_io_deq_bits_payload_a_type;
+ assign io_manager_acquire_bits_payload_union = T_7778_io_deq_bits_payload_union;
+ assign io_manager_acquire_bits_payload_data = T_7778_io_deq_bits_payload_data;
+ assign io_manager_grant_ready = T_8155_io_enq_ready;
+ assign io_manager_finish_valid = T_8277_io_deq_valid;
+ assign io_manager_finish_bits_header_src = T_8277_io_deq_bits_header_src;
+ assign io_manager_finish_bits_header_dst = T_8277_io_deq_bits_header_dst;
+ assign io_manager_finish_bits_payload_manager_xact_id = T_8277_io_deq_bits_payload_manager_xact_id;
+ assign io_manager_probe_ready = T_7901_io_enq_ready;
+ assign io_manager_release_valid = T_8028_io_deq_valid;
+ assign io_manager_release_bits_header_src = T_8028_io_deq_bits_header_src;
+ assign io_manager_release_bits_header_dst = T_8028_io_deq_bits_header_dst;
+ assign io_manager_release_bits_payload_addr_beat = T_8028_io_deq_bits_payload_addr_beat;
+ assign io_manager_release_bits_payload_addr_block = T_8028_io_deq_bits_payload_addr_block;
+ assign io_manager_release_bits_payload_client_xact_id = T_8028_io_deq_bits_payload_client_xact_id;
+ assign io_manager_release_bits_payload_voluntary = T_8028_io_deq_bits_payload_voluntary;
+ assign io_manager_release_bits_payload_r_type = T_8028_io_deq_bits_payload_r_type;
+ assign io_manager_release_bits_payload_data = T_8028_io_deq_bits_payload_data;
+ assign T_7778_clk = clk;
+ assign T_7778_reset = reset;
+ assign T_7778_io_enq_valid = io_client_acquire_valid;
+ assign T_7778_io_enq_bits_header_src = io_client_acquire_bits_header_src;
+ assign T_7778_io_enq_bits_header_dst = io_client_acquire_bits_header_dst;
+ assign T_7778_io_enq_bits_payload_addr_block = io_client_acquire_bits_payload_addr_block;
+ assign T_7778_io_enq_bits_payload_client_xact_id = io_client_acquire_bits_payload_client_xact_id;
+ assign T_7778_io_enq_bits_payload_addr_beat = io_client_acquire_bits_payload_addr_beat;
+ assign T_7778_io_enq_bits_payload_is_builtin_type = io_client_acquire_bits_payload_is_builtin_type;
+ assign T_7778_io_enq_bits_payload_a_type = io_client_acquire_bits_payload_a_type;
+ assign T_7778_io_enq_bits_payload_union = io_client_acquire_bits_payload_union;
+ assign T_7778_io_enq_bits_payload_data = io_client_acquire_bits_payload_data;
+ assign T_7778_io_deq_ready = io_manager_acquire_ready;
+ assign T_7901_clk = clk;
+ assign T_7901_reset = reset;
+ assign T_7901_io_enq_valid = io_manager_probe_valid;
+ assign T_7901_io_enq_bits_header_src = io_manager_probe_bits_header_src;
+ assign T_7901_io_enq_bits_header_dst = io_manager_probe_bits_header_dst;
+ assign T_7901_io_enq_bits_payload_addr_block = io_manager_probe_bits_payload_addr_block;
+ assign T_7901_io_enq_bits_payload_p_type = io_manager_probe_bits_payload_p_type;
+ assign T_7901_io_deq_ready = io_client_probe_ready;
+ assign T_8028_clk = clk;
+ assign T_8028_reset = reset;
+ assign T_8028_io_enq_valid = io_client_release_valid;
+ assign T_8028_io_enq_bits_header_src = io_client_release_bits_header_src;
+ assign T_8028_io_enq_bits_header_dst = io_client_release_bits_header_dst;
+ assign T_8028_io_enq_bits_payload_addr_beat = io_client_release_bits_payload_addr_beat;
+ assign T_8028_io_enq_bits_payload_addr_block = io_client_release_bits_payload_addr_block;
+ assign T_8028_io_enq_bits_payload_client_xact_id = io_client_release_bits_payload_client_xact_id;
+ assign T_8028_io_enq_bits_payload_voluntary = io_client_release_bits_payload_voluntary;
+ assign T_8028_io_enq_bits_payload_r_type = io_client_release_bits_payload_r_type;
+ assign T_8028_io_enq_bits_payload_data = io_client_release_bits_payload_data;
+ assign T_8028_io_deq_ready = io_manager_release_ready;
+ assign T_8155_clk = clk;
+ assign T_8155_reset = reset;
+ assign T_8155_io_enq_valid = io_manager_grant_valid;
+ assign T_8155_io_enq_bits_header_src = io_manager_grant_bits_header_src;
+ assign T_8155_io_enq_bits_header_dst = io_manager_grant_bits_header_dst;
+ assign T_8155_io_enq_bits_payload_addr_beat = io_manager_grant_bits_payload_addr_beat;
+ assign T_8155_io_enq_bits_payload_client_xact_id = io_manager_grant_bits_payload_client_xact_id;
+ assign T_8155_io_enq_bits_payload_manager_xact_id = io_manager_grant_bits_payload_manager_xact_id;
+ assign T_8155_io_enq_bits_payload_is_builtin_type = io_manager_grant_bits_payload_is_builtin_type;
+ assign T_8155_io_enq_bits_payload_g_type = io_manager_grant_bits_payload_g_type;
+ assign T_8155_io_enq_bits_payload_data = io_manager_grant_bits_payload_data;
+ assign T_8155_io_deq_ready = io_client_grant_ready;
+ assign T_8277_clk = clk;
+ assign T_8277_reset = reset;
+ assign T_8277_io_enq_valid = io_client_finish_valid;
+ assign T_8277_io_enq_bits_header_src = io_client_finish_bits_header_src;
+ assign T_8277_io_enq_bits_header_dst = io_client_finish_bits_header_dst;
+ assign T_8277_io_enq_bits_payload_manager_xact_id = io_client_finish_bits_payload_manager_xact_id;
+ assign T_8277_io_deq_ready = io_manager_finish_ready;
+endmodule
+module FinishUnit_7(
+ input clk,
+ input reset,
+ output io_grant_ready,
+ input io_grant_valid,
+ input [1:0] io_grant_bits_header_src,
+ input [1:0] io_grant_bits_header_dst,
+ input [1:0] io_grant_bits_payload_addr_beat,
+ input [1:0] io_grant_bits_payload_client_xact_id,
+ input [3:0] io_grant_bits_payload_manager_xact_id,
+ input io_grant_bits_payload_is_builtin_type,
+ input [3:0] io_grant_bits_payload_g_type,
+ input [127:0] io_grant_bits_payload_data,
+ input io_refill_ready,
+ output io_refill_valid,
+ output [1:0] io_refill_bits_addr_beat,
+ output [1:0] io_refill_bits_client_xact_id,
+ output [3:0] io_refill_bits_manager_xact_id,
+ output io_refill_bits_is_builtin_type,
+ output [3:0] io_refill_bits_g_type,
+ output [127:0] io_refill_bits_data,
+ input io_finish_ready,
+ output io_finish_valid,
+ output [1:0] io_finish_bits_header_src,
+ output [1:0] io_finish_bits_header_dst,
+ output [3:0] io_finish_bits_payload_manager_xact_id,
+ output io_ready
+);
+ wire T_1178;
+ wire [2:0] T_1183_0;
+ wire T_1186;
+ wire T_1188;
+ wire T_1190_0;
+ wire T_1190_1;
+ wire T_1194;
+ wire T_1195;
+ wire T_1197;
+ wire T_1198;
+ wire T_1199;
+ wire T_1200;
+ wire T_1201;
+ reg [1:0] T_1203;
+ wire T_1205;
+ wire T_1207;
+ wire [2:0] T_1210;
+ wire [1:0] T_1211;
+ wire [1:0] T_1212;
+ wire T_1213;
+ wire [1:0] T_1214;
+ wire T_1215;
+ wire T_1312_clk;
+ wire T_1312_reset;
+ wire T_1312_io_enq_ready;
+ wire T_1312_io_enq_valid;
+ wire [3:0] T_1312_io_enq_bits_fin_manager_xact_id;
+ wire [1:0] T_1312_io_enq_bits_dst;
+ wire T_1312_io_deq_ready;
+ wire T_1312_io_deq_valid;
+ wire [3:0] T_1312_io_deq_bits_fin_manager_xact_id;
+ wire [1:0] T_1312_io_deq_bits_dst;
+ wire [1:0] T_1312_io_count;
+ wire T_1313;
+ wire T_1316;
+ wire T_1318;
+ wire T_1319;
+ wire T_1321;
+ wire T_1322;
+ wire T_1323;
+ wire [2:0] T_1327_0;
+ wire T_1330;
+ wire T_1332;
+ wire T_1334_0;
+ wire T_1334_1;
+ wire T_1338;
+ wire T_1339;
+ wire T_1341;
+ wire T_1342;
+ wire T_1343;
+ wire T_1344;
+ wire T_1346;
+ wire T_1347;
+ wire T_1348;
+ wire [3:0] T_1374_manager_xact_id;
+ wire T_1402;
+ wire T_1404;
+ wire T_1405;
+ wire T_1407;
+ wire T_1408;
+ wire T_1410;
+ wire T_1411;
+ wire T_1412;
+ wire T_1415;
+ wire T_1417;
+ wire T_1418;
+ wire T_1420;
+ wire T_1421;
+ wire T_1423;
+ wire T_1424;
+ wire T_1425;
+ FinishQueue T_1312 (
+ .clk(T_1312_clk),
+ .reset(T_1312_reset),
+ .io_enq_ready(T_1312_io_enq_ready),
+ .io_enq_valid(T_1312_io_enq_valid),
+ .io_enq_bits_fin_manager_xact_id(T_1312_io_enq_bits_fin_manager_xact_id),
+ .io_enq_bits_dst(T_1312_io_enq_bits_dst),
+ .io_deq_ready(T_1312_io_deq_ready),
+ .io_deq_valid(T_1312_io_deq_valid),
+ .io_deq_bits_fin_manager_xact_id(T_1312_io_deq_bits_fin_manager_xact_id),
+ .io_deq_bits_dst(T_1312_io_deq_bits_dst),
+ .io_count(T_1312_io_count)
+ );
+ assign io_grant_ready = T_1425;
+ assign io_refill_valid = T_1412;
+ assign io_refill_bits_addr_beat = io_grant_bits_payload_addr_beat;
+ assign io_refill_bits_client_xact_id = io_grant_bits_payload_client_xact_id;
+ assign io_refill_bits_manager_xact_id = io_grant_bits_payload_manager_xact_id;
+ assign io_refill_bits_is_builtin_type = io_grant_bits_payload_is_builtin_type;
+ assign io_refill_bits_g_type = io_grant_bits_payload_g_type;
+ assign io_refill_bits_data = io_grant_bits_payload_data;
+ assign io_finish_valid = T_1312_io_deq_valid;
+ assign io_finish_bits_header_src = 1'h1;
+ assign io_finish_bits_header_dst = T_1312_io_deq_bits_dst;
+ assign io_finish_bits_payload_manager_xact_id = T_1312_io_deq_bits_fin_manager_xact_id;
+ assign io_ready = T_1312_io_enq_ready;
+ assign T_1178 = io_grant_ready & io_grant_valid;
+ assign T_1183_0 = 3'h5;
+ assign T_1186 = T_1183_0 == io_grant_bits_payload_g_type;
+ assign T_1188 = 1'h0 | T_1186;
+ assign T_1190_0 = 1'h0;
+ assign T_1190_1 = 1'h1;
+ assign T_1194 = T_1190_0 == io_grant_bits_payload_g_type;
+ assign T_1195 = T_1190_1 == io_grant_bits_payload_g_type;
+ assign T_1197 = 1'h0 | T_1194;
+ assign T_1198 = T_1197 | T_1195;
+ assign T_1199 = io_grant_bits_payload_is_builtin_type ? T_1188 : T_1198;
+ assign T_1200 = 1'h1 & T_1199;
+ assign T_1201 = T_1178 & T_1200;
+ assign T_1205 = T_1203 == 2'h3;
+ assign T_1207 = 1'h0 & T_1205;
+ assign T_1210 = T_1203 + 1'h1;
+ assign T_1211 = T_1210[1:0];
+ assign T_1212 = T_1207 ? 1'h0 : T_1211;
+ assign T_1213 = T_1201 & T_1205;
+ assign T_1214 = T_1200 ? T_1203 : 1'h0;
+ assign T_1215 = T_1200 ? T_1213 : T_1178;
+ assign T_1312_clk = clk;
+ assign T_1312_reset = reset;
+ assign T_1312_io_enq_valid = T_1348;
+ assign T_1312_io_enq_bits_fin_manager_xact_id = T_1374_manager_xact_id;
+ assign T_1312_io_enq_bits_dst = io_grant_bits_header_src;
+ assign T_1312_io_deq_ready = io_finish_ready;
+ assign T_1313 = io_grant_ready & io_grant_valid;
+ assign T_1316 = 1'h0 == 1'h0;
+ assign T_1318 = io_grant_bits_payload_g_type == 3'h0;
+ assign T_1319 = io_grant_bits_payload_is_builtin_type & T_1318;
+ assign T_1321 = T_1319 == 1'h0;
+ assign T_1322 = T_1316 & T_1321;
+ assign T_1323 = T_1313 & T_1322;
+ assign T_1327_0 = 3'h5;
+ assign T_1330 = T_1327_0 == io_grant_bits_payload_g_type;
+ assign T_1332 = 1'h0 | T_1330;
+ assign T_1334_0 = 1'h0;
+ assign T_1334_1 = 1'h1;
+ assign T_1338 = T_1334_0 == io_grant_bits_payload_g_type;
+ assign T_1339 = T_1334_1 == io_grant_bits_payload_g_type;
+ assign T_1341 = 1'h0 | T_1338;
+ assign T_1342 = T_1341 | T_1339;
+ assign T_1343 = io_grant_bits_payload_is_builtin_type ? T_1332 : T_1342;
+ assign T_1344 = 1'h1 & T_1343;
+ assign T_1346 = T_1344 == 1'h0;
+ assign T_1347 = T_1346 | T_1215;
+ assign T_1348 = T_1323 & T_1347;
+ assign T_1374_manager_xact_id = io_grant_bits_payload_manager_xact_id;
+ assign T_1402 = 1'h0 == 1'h0;
+ assign T_1404 = io_grant_bits_payload_g_type == 3'h0;
+ assign T_1405 = io_grant_bits_payload_is_builtin_type & T_1404;
+ assign T_1407 = T_1405 == 1'h0;
+ assign T_1408 = T_1402 & T_1407;
+ assign T_1410 = T_1408 == 1'h0;
+ assign T_1411 = T_1312_io_enq_ready | T_1410;
+ assign T_1412 = T_1411 & io_grant_valid;
+ assign T_1415 = 1'h0 == 1'h0;
+ assign T_1417 = io_grant_bits_payload_g_type == 3'h0;
+ assign T_1418 = io_grant_bits_payload_is_builtin_type & T_1417;
+ assign T_1420 = T_1418 == 1'h0;
+ assign T_1421 = T_1415 & T_1420;
+ assign T_1423 = T_1421 == 1'h0;
+ assign T_1424 = T_1312_io_enq_ready | T_1423;
+ assign T_1425 = T_1424 & io_refill_ready;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_1203 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ T_1203 <= 2'h0;
+ end else begin
+ if(T_1201) begin
+ T_1203 <= T_1212;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module ClientTileLinkNetworkPort_6(
+ input clk,
+ input reset,
+ output io_client_acquire_ready,
+ input io_client_acquire_valid,
+ input [25:0] io_client_acquire_bits_addr_block,
+ input [1:0] io_client_acquire_bits_client_xact_id,
+ input [1:0] io_client_acquire_bits_addr_beat,
+ input io_client_acquire_bits_is_builtin_type,
+ input [2:0] io_client_acquire_bits_a_type,
+ input [16:0] io_client_acquire_bits_union,
+ input [127:0] io_client_acquire_bits_data,
+ input io_client_grant_ready,
+ output io_client_grant_valid,
+ output [1:0] io_client_grant_bits_addr_beat,
+ output [1:0] io_client_grant_bits_client_xact_id,
+ output [3:0] io_client_grant_bits_manager_xact_id,
+ output io_client_grant_bits_is_builtin_type,
+ output [3:0] io_client_grant_bits_g_type,
+ output [127:0] io_client_grant_bits_data,
+ input io_client_probe_ready,
+ output io_client_probe_valid,
+ output [25:0] io_client_probe_bits_addr_block,
+ output [1:0] io_client_probe_bits_p_type,
+ output io_client_release_ready,
+ input io_client_release_valid,
+ input [1:0] io_client_release_bits_addr_beat,
+ input [25:0] io_client_release_bits_addr_block,
+ input [1:0] io_client_release_bits_client_xact_id,
+ input io_client_release_bits_voluntary,
+ input [2:0] io_client_release_bits_r_type,
+ input [127:0] io_client_release_bits_data,
+ input io_network_acquire_ready,
+ output io_network_acquire_valid,
+ output [1:0] io_network_acquire_bits_header_src,
+ output [1:0] io_network_acquire_bits_header_dst,
+ output [25:0] io_network_acquire_bits_payload_addr_block,
+ output [1:0] io_network_acquire_bits_payload_client_xact_id,
+ output [1:0] io_network_acquire_bits_payload_addr_beat,
+ output io_network_acquire_bits_payload_is_builtin_type,
+ output [2:0] io_network_acquire_bits_payload_a_type,
+ output [16:0] io_network_acquire_bits_payload_union,
+ output [127:0] io_network_acquire_bits_payload_data,
+ output io_network_grant_ready,
+ input io_network_grant_valid,
+ input [1:0] io_network_grant_bits_header_src,
+ input [1:0] io_network_grant_bits_header_dst,
+ input [1:0] io_network_grant_bits_payload_addr_beat,
+ input [1:0] io_network_grant_bits_payload_client_xact_id,
+ input [3:0] io_network_grant_bits_payload_manager_xact_id,
+ input io_network_grant_bits_payload_is_builtin_type,
+ input [3:0] io_network_grant_bits_payload_g_type,
+ input [127:0] io_network_grant_bits_payload_data,
+ input io_network_finish_ready,
+ output io_network_finish_valid,
+ output [1:0] io_network_finish_bits_header_src,
+ output [1:0] io_network_finish_bits_header_dst,
+ output [3:0] io_network_finish_bits_payload_manager_xact_id,
+ output io_network_probe_ready,
+ input io_network_probe_valid,
+ input [1:0] io_network_probe_bits_header_src,
+ input [1:0] io_network_probe_bits_header_dst,
+ input [25:0] io_network_probe_bits_payload_addr_block,
+ input [1:0] io_network_probe_bits_payload_p_type,
+ input io_network_release_ready,
+ output io_network_release_valid,
+ output [1:0] io_network_release_bits_header_src,
+ output [1:0] io_network_release_bits_header_dst,
+ output [1:0] io_network_release_bits_payload_addr_beat,
+ output [25:0] io_network_release_bits_payload_addr_block,
+ output [1:0] io_network_release_bits_payload_client_xact_id,
+ output io_network_release_bits_payload_voluntary,
+ output [2:0] io_network_release_bits_payload_r_type,
+ output [127:0] io_network_release_bits_payload_data
+);
+ wire finisher_clk;
+ wire finisher_reset;
+ wire finisher_io_grant_ready;
+ wire finisher_io_grant_valid;
+ wire [1:0] finisher_io_grant_bits_header_src;
+ wire [1:0] finisher_io_grant_bits_header_dst;
+ wire [1:0] finisher_io_grant_bits_payload_addr_beat;
+ wire [1:0] finisher_io_grant_bits_payload_client_xact_id;
+ wire [3:0] finisher_io_grant_bits_payload_manager_xact_id;
+ wire finisher_io_grant_bits_payload_is_builtin_type;
+ wire [3:0] finisher_io_grant_bits_payload_g_type;
+ wire [127:0] finisher_io_grant_bits_payload_data;
+ wire finisher_io_refill_ready;
+ wire finisher_io_refill_valid;
+ wire [1:0] finisher_io_refill_bits_addr_beat;
+ wire [1:0] finisher_io_refill_bits_client_xact_id;
+ wire [3:0] finisher_io_refill_bits_manager_xact_id;
+ wire finisher_io_refill_bits_is_builtin_type;
+ wire [3:0] finisher_io_refill_bits_g_type;
+ wire [127:0] finisher_io_refill_bits_data;
+ wire finisher_io_finish_ready;
+ wire finisher_io_finish_valid;
+ wire [1:0] finisher_io_finish_bits_header_src;
+ wire [1:0] finisher_io_finish_bits_header_dst;
+ wire [3:0] finisher_io_finish_bits_payload_manager_xact_id;
+ wire finisher_io_ready;
+ wire acq_with_header_ready;
+ wire acq_with_header_valid;
+ wire [1:0] acq_with_header_bits_header_src;
+ wire [1:0] acq_with_header_bits_header_dst;
+ wire [25:0] acq_with_header_bits_payload_addr_block;
+ wire [1:0] acq_with_header_bits_payload_client_xact_id;
+ wire [1:0] acq_with_header_bits_payload_addr_beat;
+ wire acq_with_header_bits_payload_is_builtin_type;
+ wire [2:0] acq_with_header_bits_payload_a_type;
+ wire [16:0] acq_with_header_bits_payload_union;
+ wire [127:0] acq_with_header_bits_payload_data;
+ wire rel_with_header_ready;
+ wire rel_with_header_valid;
+ wire [1:0] rel_with_header_bits_header_src;
+ wire [1:0] rel_with_header_bits_header_dst;
+ wire [1:0] rel_with_header_bits_payload_addr_beat;
+ wire [25:0] rel_with_header_bits_payload_addr_block;
+ wire [1:0] rel_with_header_bits_payload_client_xact_id;
+ wire rel_with_header_bits_payload_voluntary;
+ wire [2:0] rel_with_header_bits_payload_r_type;
+ wire [127:0] rel_with_header_bits_payload_data;
+ wire prb_without_header_ready;
+ wire prb_without_header_valid;
+ wire [25:0] prb_without_header_bits_addr_block;
+ wire [1:0] prb_without_header_bits_p_type;
+ wire T_4978;
+ wire T_4979;
+ FinishUnit_7 finisher (
+ .clk(finisher_clk),
+ .reset(finisher_reset),
+ .io_grant_ready(finisher_io_grant_ready),
+ .io_grant_valid(finisher_io_grant_valid),
+ .io_grant_bits_header_src(finisher_io_grant_bits_header_src),
+ .io_grant_bits_header_dst(finisher_io_grant_bits_header_dst),
+ .io_grant_bits_payload_addr_beat(finisher_io_grant_bits_payload_addr_beat),
+ .io_grant_bits_payload_client_xact_id(finisher_io_grant_bits_payload_client_xact_id),
+ .io_grant_bits_payload_manager_xact_id(finisher_io_grant_bits_payload_manager_xact_id),
+ .io_grant_bits_payload_is_builtin_type(finisher_io_grant_bits_payload_is_builtin_type),
+ .io_grant_bits_payload_g_type(finisher_io_grant_bits_payload_g_type),
+ .io_grant_bits_payload_data(finisher_io_grant_bits_payload_data),
+ .io_refill_ready(finisher_io_refill_ready),
+ .io_refill_valid(finisher_io_refill_valid),
+ .io_refill_bits_addr_beat(finisher_io_refill_bits_addr_beat),
+ .io_refill_bits_client_xact_id(finisher_io_refill_bits_client_xact_id),
+ .io_refill_bits_manager_xact_id(finisher_io_refill_bits_manager_xact_id),
+ .io_refill_bits_is_builtin_type(finisher_io_refill_bits_is_builtin_type),
+ .io_refill_bits_g_type(finisher_io_refill_bits_g_type),
+ .io_refill_bits_data(finisher_io_refill_bits_data),
+ .io_finish_ready(finisher_io_finish_ready),
+ .io_finish_valid(finisher_io_finish_valid),
+ .io_finish_bits_header_src(finisher_io_finish_bits_header_src),
+ .io_finish_bits_header_dst(finisher_io_finish_bits_header_dst),
+ .io_finish_bits_payload_manager_xact_id(finisher_io_finish_bits_payload_manager_xact_id),
+ .io_ready(finisher_io_ready)
+ );
+ assign io_client_acquire_ready = acq_with_header_ready;
+ assign io_client_grant_valid = finisher_io_refill_valid;
+ assign io_client_grant_bits_addr_beat = finisher_io_refill_bits_addr_beat;
+ assign io_client_grant_bits_client_xact_id = finisher_io_refill_bits_client_xact_id;
+ assign io_client_grant_bits_manager_xact_id = finisher_io_refill_bits_manager_xact_id;
+ assign io_client_grant_bits_is_builtin_type = finisher_io_refill_bits_is_builtin_type;
+ assign io_client_grant_bits_g_type = finisher_io_refill_bits_g_type;
+ assign io_client_grant_bits_data = finisher_io_refill_bits_data;
+ assign io_client_probe_valid = prb_without_header_valid;
+ assign io_client_probe_bits_addr_block = prb_without_header_bits_addr_block;
+ assign io_client_probe_bits_p_type = prb_without_header_bits_p_type;
+ assign io_client_release_ready = rel_with_header_ready;
+ assign io_network_acquire_valid = T_4978;
+ assign io_network_acquire_bits_header_src = acq_with_header_bits_header_src;
+ assign io_network_acquire_bits_header_dst = acq_with_header_bits_header_dst;
+ assign io_network_acquire_bits_payload_addr_block = acq_with_header_bits_payload_addr_block;
+ assign io_network_acquire_bits_payload_client_xact_id = acq_with_header_bits_payload_client_xact_id;
+ assign io_network_acquire_bits_payload_addr_beat = acq_with_header_bits_payload_addr_beat;
+ assign io_network_acquire_bits_payload_is_builtin_type = acq_with_header_bits_payload_is_builtin_type;
+ assign io_network_acquire_bits_payload_a_type = acq_with_header_bits_payload_a_type;
+ assign io_network_acquire_bits_payload_union = acq_with_header_bits_payload_union;
+ assign io_network_acquire_bits_payload_data = acq_with_header_bits_payload_data;
+ assign io_network_grant_ready = finisher_io_grant_ready;
+ assign io_network_finish_valid = finisher_io_finish_valid;
+ assign io_network_finish_bits_header_src = finisher_io_finish_bits_header_src;
+ assign io_network_finish_bits_header_dst = finisher_io_finish_bits_header_dst;
+ assign io_network_finish_bits_payload_manager_xact_id = finisher_io_finish_bits_payload_manager_xact_id;
+ assign io_network_probe_ready = prb_without_header_ready;
+ assign io_network_release_valid = rel_with_header_valid;
+ assign io_network_release_bits_header_src = rel_with_header_bits_header_src;
+ assign io_network_release_bits_header_dst = rel_with_header_bits_header_dst;
+ assign io_network_release_bits_payload_addr_beat = rel_with_header_bits_payload_addr_beat;
+ assign io_network_release_bits_payload_addr_block = rel_with_header_bits_payload_addr_block;
+ assign io_network_release_bits_payload_client_xact_id = rel_with_header_bits_payload_client_xact_id;
+ assign io_network_release_bits_payload_voluntary = rel_with_header_bits_payload_voluntary;
+ assign io_network_release_bits_payload_r_type = rel_with_header_bits_payload_r_type;
+ assign io_network_release_bits_payload_data = rel_with_header_bits_payload_data;
+ assign finisher_clk = clk;
+ assign finisher_reset = reset;
+ assign finisher_io_grant_valid = io_network_grant_valid;
+ assign finisher_io_grant_bits_header_src = io_network_grant_bits_header_src;
+ assign finisher_io_grant_bits_header_dst = io_network_grant_bits_header_dst;
+ assign finisher_io_grant_bits_payload_addr_beat = io_network_grant_bits_payload_addr_beat;
+ assign finisher_io_grant_bits_payload_client_xact_id = io_network_grant_bits_payload_client_xact_id;
+ assign finisher_io_grant_bits_payload_manager_xact_id = io_network_grant_bits_payload_manager_xact_id;
+ assign finisher_io_grant_bits_payload_is_builtin_type = io_network_grant_bits_payload_is_builtin_type;
+ assign finisher_io_grant_bits_payload_g_type = io_network_grant_bits_payload_g_type;
+ assign finisher_io_grant_bits_payload_data = io_network_grant_bits_payload_data;
+ assign finisher_io_refill_ready = io_client_grant_ready;
+ assign finisher_io_finish_ready = io_network_finish_ready;
+ assign acq_with_header_ready = T_4979;
+ assign acq_with_header_valid = io_client_acquire_valid;
+ assign acq_with_header_bits_header_src = 1'h1;
+ assign acq_with_header_bits_header_dst = 1'h0;
+ assign acq_with_header_bits_payload_addr_block = io_client_acquire_bits_addr_block;
+ assign acq_with_header_bits_payload_client_xact_id = io_client_acquire_bits_client_xact_id;
+ assign acq_with_header_bits_payload_addr_beat = io_client_acquire_bits_addr_beat;
+ assign acq_with_header_bits_payload_is_builtin_type = io_client_acquire_bits_is_builtin_type;
+ assign acq_with_header_bits_payload_a_type = io_client_acquire_bits_a_type;
+ assign acq_with_header_bits_payload_union = io_client_acquire_bits_union;
+ assign acq_with_header_bits_payload_data = io_client_acquire_bits_data;
+ assign rel_with_header_ready = io_network_release_ready;
+ assign rel_with_header_valid = io_client_release_valid;
+ assign rel_with_header_bits_header_src = 1'h1;
+ assign rel_with_header_bits_header_dst = 1'h0;
+ assign rel_with_header_bits_payload_addr_beat = io_client_release_bits_addr_beat;
+ assign rel_with_header_bits_payload_addr_block = io_client_release_bits_addr_block;
+ assign rel_with_header_bits_payload_client_xact_id = io_client_release_bits_client_xact_id;
+ assign rel_with_header_bits_payload_voluntary = io_client_release_bits_voluntary;
+ assign rel_with_header_bits_payload_r_type = io_client_release_bits_r_type;
+ assign rel_with_header_bits_payload_data = io_client_release_bits_data;
+ assign prb_without_header_ready = io_client_probe_ready;
+ assign prb_without_header_valid = io_network_probe_valid;
+ assign prb_without_header_bits_addr_block = io_network_probe_bits_payload_addr_block;
+ assign prb_without_header_bits_p_type = io_network_probe_bits_payload_p_type;
+ assign T_4978 = acq_with_header_valid & finisher_io_ready;
+ assign T_4979 = io_network_acquire_ready & finisher_io_ready;
+endmodule
+module FinishUnit_16(
+ input clk,
+ input reset,
+ output io_grant_ready,
+ input io_grant_valid,
+ input [1:0] io_grant_bits_header_src,
+ input [1:0] io_grant_bits_header_dst,
+ input [1:0] io_grant_bits_payload_addr_beat,
+ input [1:0] io_grant_bits_payload_client_xact_id,
+ input [3:0] io_grant_bits_payload_manager_xact_id,
+ input io_grant_bits_payload_is_builtin_type,
+ input [3:0] io_grant_bits_payload_g_type,
+ input [127:0] io_grant_bits_payload_data,
+ input io_refill_ready,
+ output io_refill_valid,
+ output [1:0] io_refill_bits_addr_beat,
+ output [1:0] io_refill_bits_client_xact_id,
+ output [3:0] io_refill_bits_manager_xact_id,
+ output io_refill_bits_is_builtin_type,
+ output [3:0] io_refill_bits_g_type,
+ output [127:0] io_refill_bits_data,
+ input io_finish_ready,
+ output io_finish_valid,
+ output [1:0] io_finish_bits_header_src,
+ output [1:0] io_finish_bits_header_dst,
+ output [3:0] io_finish_bits_payload_manager_xact_id,
+ output io_ready
+);
+ wire T_1178;
+ wire [2:0] T_1183_0;
+ wire T_1186;
+ wire T_1188;
+ wire T_1190_0;
+ wire T_1190_1;
+ wire T_1194;
+ wire T_1195;
+ wire T_1197;
+ wire T_1198;
+ wire T_1199;
+ wire T_1200;
+ wire T_1201;
+ reg [1:0] T_1203;
+ wire T_1205;
+ wire T_1207;
+ wire [2:0] T_1210;
+ wire [1:0] T_1211;
+ wire [1:0] T_1212;
+ wire T_1213;
+ wire [1:0] T_1214;
+ wire T_1215;
+ wire T_1312_clk;
+ wire T_1312_reset;
+ wire T_1312_io_enq_ready;
+ wire T_1312_io_enq_valid;
+ wire [3:0] T_1312_io_enq_bits_fin_manager_xact_id;
+ wire [1:0] T_1312_io_enq_bits_dst;
+ wire T_1312_io_deq_ready;
+ wire T_1312_io_deq_valid;
+ wire [3:0] T_1312_io_deq_bits_fin_manager_xact_id;
+ wire [1:0] T_1312_io_deq_bits_dst;
+ wire [1:0] T_1312_io_count;
+ wire T_1313;
+ wire T_1316;
+ wire T_1318;
+ wire T_1319;
+ wire T_1321;
+ wire T_1322;
+ wire T_1323;
+ wire [2:0] T_1327_0;
+ wire T_1330;
+ wire T_1332;
+ wire T_1334_0;
+ wire T_1334_1;
+ wire T_1338;
+ wire T_1339;
+ wire T_1341;
+ wire T_1342;
+ wire T_1343;
+ wire T_1344;
+ wire T_1346;
+ wire T_1347;
+ wire T_1348;
+ wire [3:0] T_1374_manager_xact_id;
+ wire T_1402;
+ wire T_1404;
+ wire T_1405;
+ wire T_1407;
+ wire T_1408;
+ wire T_1410;
+ wire T_1411;
+ wire T_1412;
+ wire T_1415;
+ wire T_1417;
+ wire T_1418;
+ wire T_1420;
+ wire T_1421;
+ wire T_1423;
+ wire T_1424;
+ wire T_1425;
+ FinishQueue T_1312 (
+ .clk(T_1312_clk),
+ .reset(T_1312_reset),
+ .io_enq_ready(T_1312_io_enq_ready),
+ .io_enq_valid(T_1312_io_enq_valid),
+ .io_enq_bits_fin_manager_xact_id(T_1312_io_enq_bits_fin_manager_xact_id),
+ .io_enq_bits_dst(T_1312_io_enq_bits_dst),
+ .io_deq_ready(T_1312_io_deq_ready),
+ .io_deq_valid(T_1312_io_deq_valid),
+ .io_deq_bits_fin_manager_xact_id(T_1312_io_deq_bits_fin_manager_xact_id),
+ .io_deq_bits_dst(T_1312_io_deq_bits_dst),
+ .io_count(T_1312_io_count)
+ );
+ assign io_grant_ready = T_1425;
+ assign io_refill_valid = T_1412;
+ assign io_refill_bits_addr_beat = io_grant_bits_payload_addr_beat;
+ assign io_refill_bits_client_xact_id = io_grant_bits_payload_client_xact_id;
+ assign io_refill_bits_manager_xact_id = io_grant_bits_payload_manager_xact_id;
+ assign io_refill_bits_is_builtin_type = io_grant_bits_payload_is_builtin_type;
+ assign io_refill_bits_g_type = io_grant_bits_payload_g_type;
+ assign io_refill_bits_data = io_grant_bits_payload_data;
+ assign io_finish_valid = T_1312_io_deq_valid;
+ assign io_finish_bits_header_src = 2'h2;
+ assign io_finish_bits_header_dst = T_1312_io_deq_bits_dst;
+ assign io_finish_bits_payload_manager_xact_id = T_1312_io_deq_bits_fin_manager_xact_id;
+ assign io_ready = T_1312_io_enq_ready;
+ assign T_1178 = io_grant_ready & io_grant_valid;
+ assign T_1183_0 = 3'h5;
+ assign T_1186 = T_1183_0 == io_grant_bits_payload_g_type;
+ assign T_1188 = 1'h0 | T_1186;
+ assign T_1190_0 = 1'h0;
+ assign T_1190_1 = 1'h1;
+ assign T_1194 = T_1190_0 == io_grant_bits_payload_g_type;
+ assign T_1195 = T_1190_1 == io_grant_bits_payload_g_type;
+ assign T_1197 = 1'h0 | T_1194;
+ assign T_1198 = T_1197 | T_1195;
+ assign T_1199 = io_grant_bits_payload_is_builtin_type ? T_1188 : T_1198;
+ assign T_1200 = 1'h1 & T_1199;
+ assign T_1201 = T_1178 & T_1200;
+ assign T_1205 = T_1203 == 2'h3;
+ assign T_1207 = 1'h0 & T_1205;
+ assign T_1210 = T_1203 + 1'h1;
+ assign T_1211 = T_1210[1:0];
+ assign T_1212 = T_1207 ? 1'h0 : T_1211;
+ assign T_1213 = T_1201 & T_1205;
+ assign T_1214 = T_1200 ? T_1203 : 1'h0;
+ assign T_1215 = T_1200 ? T_1213 : T_1178;
+ assign T_1312_clk = clk;
+ assign T_1312_reset = reset;
+ assign T_1312_io_enq_valid = T_1348;
+ assign T_1312_io_enq_bits_fin_manager_xact_id = T_1374_manager_xact_id;
+ assign T_1312_io_enq_bits_dst = io_grant_bits_header_src;
+ assign T_1312_io_deq_ready = io_finish_ready;
+ assign T_1313 = io_grant_ready & io_grant_valid;
+ assign T_1316 = 1'h0 == 1'h0;
+ assign T_1318 = io_grant_bits_payload_g_type == 3'h0;
+ assign T_1319 = io_grant_bits_payload_is_builtin_type & T_1318;
+ assign T_1321 = T_1319 == 1'h0;
+ assign T_1322 = T_1316 & T_1321;
+ assign T_1323 = T_1313 & T_1322;
+ assign T_1327_0 = 3'h5;
+ assign T_1330 = T_1327_0 == io_grant_bits_payload_g_type;
+ assign T_1332 = 1'h0 | T_1330;
+ assign T_1334_0 = 1'h0;
+ assign T_1334_1 = 1'h1;
+ assign T_1338 = T_1334_0 == io_grant_bits_payload_g_type;
+ assign T_1339 = T_1334_1 == io_grant_bits_payload_g_type;
+ assign T_1341 = 1'h0 | T_1338;
+ assign T_1342 = T_1341 | T_1339;
+ assign T_1343 = io_grant_bits_payload_is_builtin_type ? T_1332 : T_1342;
+ assign T_1344 = 1'h1 & T_1343;
+ assign T_1346 = T_1344 == 1'h0;
+ assign T_1347 = T_1346 | T_1215;
+ assign T_1348 = T_1323 & T_1347;
+ assign T_1374_manager_xact_id = io_grant_bits_payload_manager_xact_id;
+ assign T_1402 = 1'h0 == 1'h0;
+ assign T_1404 = io_grant_bits_payload_g_type == 3'h0;
+ assign T_1405 = io_grant_bits_payload_is_builtin_type & T_1404;
+ assign T_1407 = T_1405 == 1'h0;
+ assign T_1408 = T_1402 & T_1407;
+ assign T_1410 = T_1408 == 1'h0;
+ assign T_1411 = T_1312_io_enq_ready | T_1410;
+ assign T_1412 = T_1411 & io_grant_valid;
+ assign T_1415 = 1'h0 == 1'h0;
+ assign T_1417 = io_grant_bits_payload_g_type == 3'h0;
+ assign T_1418 = io_grant_bits_payload_is_builtin_type & T_1417;
+ assign T_1420 = T_1418 == 1'h0;
+ assign T_1421 = T_1415 & T_1420;
+ assign T_1423 = T_1421 == 1'h0;
+ assign T_1424 = T_1312_io_enq_ready | T_1423;
+ assign T_1425 = T_1424 & io_refill_ready;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_1203 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ T_1203 <= 2'h0;
+ end else begin
+ if(T_1201) begin
+ T_1203 <= T_1212;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module ClientTileLinkNetworkPort_15(
+ input clk,
+ input reset,
+ output io_client_acquire_ready,
+ input io_client_acquire_valid,
+ input [25:0] io_client_acquire_bits_addr_block,
+ input [1:0] io_client_acquire_bits_client_xact_id,
+ input [1:0] io_client_acquire_bits_addr_beat,
+ input io_client_acquire_bits_is_builtin_type,
+ input [2:0] io_client_acquire_bits_a_type,
+ input [16:0] io_client_acquire_bits_union,
+ input [127:0] io_client_acquire_bits_data,
+ input io_client_grant_ready,
+ output io_client_grant_valid,
+ output [1:0] io_client_grant_bits_addr_beat,
+ output [1:0] io_client_grant_bits_client_xact_id,
+ output [3:0] io_client_grant_bits_manager_xact_id,
+ output io_client_grant_bits_is_builtin_type,
+ output [3:0] io_client_grant_bits_g_type,
+ output [127:0] io_client_grant_bits_data,
+ input io_client_probe_ready,
+ output io_client_probe_valid,
+ output [25:0] io_client_probe_bits_addr_block,
+ output [1:0] io_client_probe_bits_p_type,
+ output io_client_release_ready,
+ input io_client_release_valid,
+ input [1:0] io_client_release_bits_addr_beat,
+ input [25:0] io_client_release_bits_addr_block,
+ input [1:0] io_client_release_bits_client_xact_id,
+ input io_client_release_bits_voluntary,
+ input [2:0] io_client_release_bits_r_type,
+ input [127:0] io_client_release_bits_data,
+ input io_network_acquire_ready,
+ output io_network_acquire_valid,
+ output [1:0] io_network_acquire_bits_header_src,
+ output [1:0] io_network_acquire_bits_header_dst,
+ output [25:0] io_network_acquire_bits_payload_addr_block,
+ output [1:0] io_network_acquire_bits_payload_client_xact_id,
+ output [1:0] io_network_acquire_bits_payload_addr_beat,
+ output io_network_acquire_bits_payload_is_builtin_type,
+ output [2:0] io_network_acquire_bits_payload_a_type,
+ output [16:0] io_network_acquire_bits_payload_union,
+ output [127:0] io_network_acquire_bits_payload_data,
+ output io_network_grant_ready,
+ input io_network_grant_valid,
+ input [1:0] io_network_grant_bits_header_src,
+ input [1:0] io_network_grant_bits_header_dst,
+ input [1:0] io_network_grant_bits_payload_addr_beat,
+ input [1:0] io_network_grant_bits_payload_client_xact_id,
+ input [3:0] io_network_grant_bits_payload_manager_xact_id,
+ input io_network_grant_bits_payload_is_builtin_type,
+ input [3:0] io_network_grant_bits_payload_g_type,
+ input [127:0] io_network_grant_bits_payload_data,
+ input io_network_finish_ready,
+ output io_network_finish_valid,
+ output [1:0] io_network_finish_bits_header_src,
+ output [1:0] io_network_finish_bits_header_dst,
+ output [3:0] io_network_finish_bits_payload_manager_xact_id,
+ output io_network_probe_ready,
+ input io_network_probe_valid,
+ input [1:0] io_network_probe_bits_header_src,
+ input [1:0] io_network_probe_bits_header_dst,
+ input [25:0] io_network_probe_bits_payload_addr_block,
+ input [1:0] io_network_probe_bits_payload_p_type,
+ input io_network_release_ready,
+ output io_network_release_valid,
+ output [1:0] io_network_release_bits_header_src,
+ output [1:0] io_network_release_bits_header_dst,
+ output [1:0] io_network_release_bits_payload_addr_beat,
+ output [25:0] io_network_release_bits_payload_addr_block,
+ output [1:0] io_network_release_bits_payload_client_xact_id,
+ output io_network_release_bits_payload_voluntary,
+ output [2:0] io_network_release_bits_payload_r_type,
+ output [127:0] io_network_release_bits_payload_data
+);
+ wire finisher_clk;
+ wire finisher_reset;
+ wire finisher_io_grant_ready;
+ wire finisher_io_grant_valid;
+ wire [1:0] finisher_io_grant_bits_header_src;
+ wire [1:0] finisher_io_grant_bits_header_dst;
+ wire [1:0] finisher_io_grant_bits_payload_addr_beat;
+ wire [1:0] finisher_io_grant_bits_payload_client_xact_id;
+ wire [3:0] finisher_io_grant_bits_payload_manager_xact_id;
+ wire finisher_io_grant_bits_payload_is_builtin_type;
+ wire [3:0] finisher_io_grant_bits_payload_g_type;
+ wire [127:0] finisher_io_grant_bits_payload_data;
+ wire finisher_io_refill_ready;
+ wire finisher_io_refill_valid;
+ wire [1:0] finisher_io_refill_bits_addr_beat;
+ wire [1:0] finisher_io_refill_bits_client_xact_id;
+ wire [3:0] finisher_io_refill_bits_manager_xact_id;
+ wire finisher_io_refill_bits_is_builtin_type;
+ wire [3:0] finisher_io_refill_bits_g_type;
+ wire [127:0] finisher_io_refill_bits_data;
+ wire finisher_io_finish_ready;
+ wire finisher_io_finish_valid;
+ wire [1:0] finisher_io_finish_bits_header_src;
+ wire [1:0] finisher_io_finish_bits_header_dst;
+ wire [3:0] finisher_io_finish_bits_payload_manager_xact_id;
+ wire finisher_io_ready;
+ wire acq_with_header_ready;
+ wire acq_with_header_valid;
+ wire [1:0] acq_with_header_bits_header_src;
+ wire [1:0] acq_with_header_bits_header_dst;
+ wire [25:0] acq_with_header_bits_payload_addr_block;
+ wire [1:0] acq_with_header_bits_payload_client_xact_id;
+ wire [1:0] acq_with_header_bits_payload_addr_beat;
+ wire acq_with_header_bits_payload_is_builtin_type;
+ wire [2:0] acq_with_header_bits_payload_a_type;
+ wire [16:0] acq_with_header_bits_payload_union;
+ wire [127:0] acq_with_header_bits_payload_data;
+ wire rel_with_header_ready;
+ wire rel_with_header_valid;
+ wire [1:0] rel_with_header_bits_header_src;
+ wire [1:0] rel_with_header_bits_header_dst;
+ wire [1:0] rel_with_header_bits_payload_addr_beat;
+ wire [25:0] rel_with_header_bits_payload_addr_block;
+ wire [1:0] rel_with_header_bits_payload_client_xact_id;
+ wire rel_with_header_bits_payload_voluntary;
+ wire [2:0] rel_with_header_bits_payload_r_type;
+ wire [127:0] rel_with_header_bits_payload_data;
+ wire prb_without_header_ready;
+ wire prb_without_header_valid;
+ wire [25:0] prb_without_header_bits_addr_block;
+ wire [1:0] prb_without_header_bits_p_type;
+ wire T_4978;
+ wire T_4979;
+ FinishUnit_16 finisher (
+ .clk(finisher_clk),
+ .reset(finisher_reset),
+ .io_grant_ready(finisher_io_grant_ready),
+ .io_grant_valid(finisher_io_grant_valid),
+ .io_grant_bits_header_src(finisher_io_grant_bits_header_src),
+ .io_grant_bits_header_dst(finisher_io_grant_bits_header_dst),
+ .io_grant_bits_payload_addr_beat(finisher_io_grant_bits_payload_addr_beat),
+ .io_grant_bits_payload_client_xact_id(finisher_io_grant_bits_payload_client_xact_id),
+ .io_grant_bits_payload_manager_xact_id(finisher_io_grant_bits_payload_manager_xact_id),
+ .io_grant_bits_payload_is_builtin_type(finisher_io_grant_bits_payload_is_builtin_type),
+ .io_grant_bits_payload_g_type(finisher_io_grant_bits_payload_g_type),
+ .io_grant_bits_payload_data(finisher_io_grant_bits_payload_data),
+ .io_refill_ready(finisher_io_refill_ready),
+ .io_refill_valid(finisher_io_refill_valid),
+ .io_refill_bits_addr_beat(finisher_io_refill_bits_addr_beat),
+ .io_refill_bits_client_xact_id(finisher_io_refill_bits_client_xact_id),
+ .io_refill_bits_manager_xact_id(finisher_io_refill_bits_manager_xact_id),
+ .io_refill_bits_is_builtin_type(finisher_io_refill_bits_is_builtin_type),
+ .io_refill_bits_g_type(finisher_io_refill_bits_g_type),
+ .io_refill_bits_data(finisher_io_refill_bits_data),
+ .io_finish_ready(finisher_io_finish_ready),
+ .io_finish_valid(finisher_io_finish_valid),
+ .io_finish_bits_header_src(finisher_io_finish_bits_header_src),
+ .io_finish_bits_header_dst(finisher_io_finish_bits_header_dst),
+ .io_finish_bits_payload_manager_xact_id(finisher_io_finish_bits_payload_manager_xact_id),
+ .io_ready(finisher_io_ready)
+ );
+ assign io_client_acquire_ready = acq_with_header_ready;
+ assign io_client_grant_valid = finisher_io_refill_valid;
+ assign io_client_grant_bits_addr_beat = finisher_io_refill_bits_addr_beat;
+ assign io_client_grant_bits_client_xact_id = finisher_io_refill_bits_client_xact_id;
+ assign io_client_grant_bits_manager_xact_id = finisher_io_refill_bits_manager_xact_id;
+ assign io_client_grant_bits_is_builtin_type = finisher_io_refill_bits_is_builtin_type;
+ assign io_client_grant_bits_g_type = finisher_io_refill_bits_g_type;
+ assign io_client_grant_bits_data = finisher_io_refill_bits_data;
+ assign io_client_probe_valid = prb_without_header_valid;
+ assign io_client_probe_bits_addr_block = prb_without_header_bits_addr_block;
+ assign io_client_probe_bits_p_type = prb_without_header_bits_p_type;
+ assign io_client_release_ready = rel_with_header_ready;
+ assign io_network_acquire_valid = T_4978;
+ assign io_network_acquire_bits_header_src = acq_with_header_bits_header_src;
+ assign io_network_acquire_bits_header_dst = acq_with_header_bits_header_dst;
+ assign io_network_acquire_bits_payload_addr_block = acq_with_header_bits_payload_addr_block;
+ assign io_network_acquire_bits_payload_client_xact_id = acq_with_header_bits_payload_client_xact_id;
+ assign io_network_acquire_bits_payload_addr_beat = acq_with_header_bits_payload_addr_beat;
+ assign io_network_acquire_bits_payload_is_builtin_type = acq_with_header_bits_payload_is_builtin_type;
+ assign io_network_acquire_bits_payload_a_type = acq_with_header_bits_payload_a_type;
+ assign io_network_acquire_bits_payload_union = acq_with_header_bits_payload_union;
+ assign io_network_acquire_bits_payload_data = acq_with_header_bits_payload_data;
+ assign io_network_grant_ready = finisher_io_grant_ready;
+ assign io_network_finish_valid = finisher_io_finish_valid;
+ assign io_network_finish_bits_header_src = finisher_io_finish_bits_header_src;
+ assign io_network_finish_bits_header_dst = finisher_io_finish_bits_header_dst;
+ assign io_network_finish_bits_payload_manager_xact_id = finisher_io_finish_bits_payload_manager_xact_id;
+ assign io_network_probe_ready = prb_without_header_ready;
+ assign io_network_release_valid = rel_with_header_valid;
+ assign io_network_release_bits_header_src = rel_with_header_bits_header_src;
+ assign io_network_release_bits_header_dst = rel_with_header_bits_header_dst;
+ assign io_network_release_bits_payload_addr_beat = rel_with_header_bits_payload_addr_beat;
+ assign io_network_release_bits_payload_addr_block = rel_with_header_bits_payload_addr_block;
+ assign io_network_release_bits_payload_client_xact_id = rel_with_header_bits_payload_client_xact_id;
+ assign io_network_release_bits_payload_voluntary = rel_with_header_bits_payload_voluntary;
+ assign io_network_release_bits_payload_r_type = rel_with_header_bits_payload_r_type;
+ assign io_network_release_bits_payload_data = rel_with_header_bits_payload_data;
+ assign finisher_clk = clk;
+ assign finisher_reset = reset;
+ assign finisher_io_grant_valid = io_network_grant_valid;
+ assign finisher_io_grant_bits_header_src = io_network_grant_bits_header_src;
+ assign finisher_io_grant_bits_header_dst = io_network_grant_bits_header_dst;
+ assign finisher_io_grant_bits_payload_addr_beat = io_network_grant_bits_payload_addr_beat;
+ assign finisher_io_grant_bits_payload_client_xact_id = io_network_grant_bits_payload_client_xact_id;
+ assign finisher_io_grant_bits_payload_manager_xact_id = io_network_grant_bits_payload_manager_xact_id;
+ assign finisher_io_grant_bits_payload_is_builtin_type = io_network_grant_bits_payload_is_builtin_type;
+ assign finisher_io_grant_bits_payload_g_type = io_network_grant_bits_payload_g_type;
+ assign finisher_io_grant_bits_payload_data = io_network_grant_bits_payload_data;
+ assign finisher_io_refill_ready = io_client_grant_ready;
+ assign finisher_io_finish_ready = io_network_finish_ready;
+ assign acq_with_header_ready = T_4979;
+ assign acq_with_header_valid = io_client_acquire_valid;
+ assign acq_with_header_bits_header_src = 2'h2;
+ assign acq_with_header_bits_header_dst = 1'h0;
+ assign acq_with_header_bits_payload_addr_block = io_client_acquire_bits_addr_block;
+ assign acq_with_header_bits_payload_client_xact_id = io_client_acquire_bits_client_xact_id;
+ assign acq_with_header_bits_payload_addr_beat = io_client_acquire_bits_addr_beat;
+ assign acq_with_header_bits_payload_is_builtin_type = io_client_acquire_bits_is_builtin_type;
+ assign acq_with_header_bits_payload_a_type = io_client_acquire_bits_a_type;
+ assign acq_with_header_bits_payload_union = io_client_acquire_bits_union;
+ assign acq_with_header_bits_payload_data = io_client_acquire_bits_data;
+ assign rel_with_header_ready = io_network_release_ready;
+ assign rel_with_header_valid = io_client_release_valid;
+ assign rel_with_header_bits_header_src = 2'h2;
+ assign rel_with_header_bits_header_dst = 1'h0;
+ assign rel_with_header_bits_payload_addr_beat = io_client_release_bits_addr_beat;
+ assign rel_with_header_bits_payload_addr_block = io_client_release_bits_addr_block;
+ assign rel_with_header_bits_payload_client_xact_id = io_client_release_bits_client_xact_id;
+ assign rel_with_header_bits_payload_voluntary = io_client_release_bits_voluntary;
+ assign rel_with_header_bits_payload_r_type = io_client_release_bits_r_type;
+ assign rel_with_header_bits_payload_data = io_client_release_bits_data;
+ assign prb_without_header_ready = io_client_probe_ready;
+ assign prb_without_header_valid = io_network_probe_valid;
+ assign prb_without_header_bits_addr_block = io_network_probe_bits_payload_addr_block;
+ assign prb_without_header_bits_p_type = io_network_probe_bits_payload_p_type;
+ assign T_4978 = acq_with_header_valid & finisher_io_ready;
+ assign T_4979 = io_network_acquire_ready & finisher_io_ready;
+endmodule
+module ManagerTileLinkNetworkPort(
+ input clk,
+ input reset,
+ input io_manager_acquire_ready,
+ output io_manager_acquire_valid,
+ output [25:0] io_manager_acquire_bits_addr_block,
+ output [1:0] io_manager_acquire_bits_client_xact_id,
+ output [1:0] io_manager_acquire_bits_addr_beat,
+ output io_manager_acquire_bits_is_builtin_type,
+ output [2:0] io_manager_acquire_bits_a_type,
+ output [16:0] io_manager_acquire_bits_union,
+ output [127:0] io_manager_acquire_bits_data,
+ output [1:0] io_manager_acquire_bits_client_id,
+ output io_manager_grant_ready,
+ input io_manager_grant_valid,
+ input [1:0] io_manager_grant_bits_addr_beat,
+ input [1:0] io_manager_grant_bits_client_xact_id,
+ input [3:0] io_manager_grant_bits_manager_xact_id,
+ input io_manager_grant_bits_is_builtin_type,
+ input [3:0] io_manager_grant_bits_g_type,
+ input [127:0] io_manager_grant_bits_data,
+ input [1:0] io_manager_grant_bits_client_id,
+ input io_manager_finish_ready,
+ output io_manager_finish_valid,
+ output [3:0] io_manager_finish_bits_manager_xact_id,
+ output io_manager_probe_ready,
+ input io_manager_probe_valid,
+ input [25:0] io_manager_probe_bits_addr_block,
+ input [1:0] io_manager_probe_bits_p_type,
+ input [1:0] io_manager_probe_bits_client_id,
+ input io_manager_release_ready,
+ output io_manager_release_valid,
+ output [1:0] io_manager_release_bits_addr_beat,
+ output [25:0] io_manager_release_bits_addr_block,
+ output [1:0] io_manager_release_bits_client_xact_id,
+ output io_manager_release_bits_voluntary,
+ output [2:0] io_manager_release_bits_r_type,
+ output [127:0] io_manager_release_bits_data,
+ output [1:0] io_manager_release_bits_client_id,
+ output io_network_acquire_ready,
+ input io_network_acquire_valid,
+ input [1:0] io_network_acquire_bits_header_src,
+ input [1:0] io_network_acquire_bits_header_dst,
+ input [25:0] io_network_acquire_bits_payload_addr_block,
+ input [1:0] io_network_acquire_bits_payload_client_xact_id,
+ input [1:0] io_network_acquire_bits_payload_addr_beat,
+ input io_network_acquire_bits_payload_is_builtin_type,
+ input [2:0] io_network_acquire_bits_payload_a_type,
+ input [16:0] io_network_acquire_bits_payload_union,
+ input [127:0] io_network_acquire_bits_payload_data,
+ input io_network_grant_ready,
+ output io_network_grant_valid,
+ output [1:0] io_network_grant_bits_header_src,
+ output [1:0] io_network_grant_bits_header_dst,
+ output [1:0] io_network_grant_bits_payload_addr_beat,
+ output [1:0] io_network_grant_bits_payload_client_xact_id,
+ output [3:0] io_network_grant_bits_payload_manager_xact_id,
+ output io_network_grant_bits_payload_is_builtin_type,
+ output [3:0] io_network_grant_bits_payload_g_type,
+ output [127:0] io_network_grant_bits_payload_data,
+ output io_network_finish_ready,
+ input io_network_finish_valid,
+ input [1:0] io_network_finish_bits_header_src,
+ input [1:0] io_network_finish_bits_header_dst,
+ input [3:0] io_network_finish_bits_payload_manager_xact_id,
+ input io_network_probe_ready,
+ output io_network_probe_valid,
+ output [1:0] io_network_probe_bits_header_src,
+ output [1:0] io_network_probe_bits_header_dst,
+ output [25:0] io_network_probe_bits_payload_addr_block,
+ output [1:0] io_network_probe_bits_payload_p_type,
+ output io_network_release_ready,
+ input io_network_release_valid,
+ input [1:0] io_network_release_bits_header_src,
+ input [1:0] io_network_release_bits_header_dst,
+ input [1:0] io_network_release_bits_payload_addr_beat,
+ input [25:0] io_network_release_bits_payload_addr_block,
+ input [1:0] io_network_release_bits_payload_client_xact_id,
+ input io_network_release_bits_payload_voluntary,
+ input [2:0] io_network_release_bits_payload_r_type,
+ input [127:0] io_network_release_bits_payload_data
+);
+ wire T_6833_ready;
+ wire T_6833_valid;
+ wire [1:0] T_6833_bits_header_src;
+ wire [1:0] T_6833_bits_header_dst;
+ wire [1:0] T_6833_bits_payload_addr_beat;
+ wire [1:0] T_6833_bits_payload_client_xact_id;
+ wire [3:0] T_6833_bits_payload_manager_xact_id;
+ wire T_6833_bits_payload_is_builtin_type;
+ wire [3:0] T_6833_bits_payload_g_type;
+ wire [127:0] T_6833_bits_payload_data;
+ wire [1:0] T_6833_bits_payload_client_id;
+ wire T_7463_ready;
+ wire T_7463_valid;
+ wire [1:0] T_7463_bits_header_src;
+ wire [1:0] T_7463_bits_header_dst;
+ wire [25:0] T_7463_bits_payload_addr_block;
+ wire [1:0] T_7463_bits_payload_p_type;
+ wire [1:0] T_7463_bits_payload_client_id;
+ wire T_7778_ready;
+ wire T_7778_valid;
+ wire [25:0] T_7778_bits_addr_block;
+ wire [1:0] T_7778_bits_client_xact_id;
+ wire [1:0] T_7778_bits_addr_beat;
+ wire T_7778_bits_is_builtin_type;
+ wire [2:0] T_7778_bits_a_type;
+ wire [16:0] T_7778_bits_union;
+ wire [127:0] T_7778_bits_data;
+ wire T_7906_ready;
+ wire T_7906_valid;
+ wire [1:0] T_7906_bits_addr_beat;
+ wire [25:0] T_7906_bits_addr_block;
+ wire [1:0] T_7906_bits_client_xact_id;
+ wire T_7906_bits_voluntary;
+ wire [2:0] T_7906_bits_r_type;
+ wire [127:0] T_7906_bits_data;
+ wire T_8022_ready;
+ wire T_8022_valid;
+ wire [3:0] T_8022_bits_manager_xact_id;
+ assign io_manager_acquire_valid = T_7778_valid;
+ assign io_manager_acquire_bits_addr_block = T_7778_bits_addr_block;
+ assign io_manager_acquire_bits_client_xact_id = T_7778_bits_client_xact_id;
+ assign io_manager_acquire_bits_addr_beat = T_7778_bits_addr_beat;
+ assign io_manager_acquire_bits_is_builtin_type = T_7778_bits_is_builtin_type;
+ assign io_manager_acquire_bits_a_type = T_7778_bits_a_type;
+ assign io_manager_acquire_bits_union = T_7778_bits_union;
+ assign io_manager_acquire_bits_data = T_7778_bits_data;
+ assign io_manager_acquire_bits_client_id = io_network_acquire_bits_header_src;
+ assign io_manager_grant_ready = T_6833_ready;
+ assign io_manager_finish_valid = T_8022_valid;
+ assign io_manager_finish_bits_manager_xact_id = T_8022_bits_manager_xact_id;
+ assign io_manager_probe_ready = T_7463_ready;
+ assign io_manager_release_valid = T_7906_valid;
+ assign io_manager_release_bits_addr_beat = T_7906_bits_addr_beat;
+ assign io_manager_release_bits_addr_block = T_7906_bits_addr_block;
+ assign io_manager_release_bits_client_xact_id = T_7906_bits_client_xact_id;
+ assign io_manager_release_bits_voluntary = T_7906_bits_voluntary;
+ assign io_manager_release_bits_r_type = T_7906_bits_r_type;
+ assign io_manager_release_bits_data = T_7906_bits_data;
+ assign io_manager_release_bits_client_id = io_network_release_bits_header_src;
+ assign io_network_acquire_ready = T_7778_ready;
+ assign io_network_grant_valid = T_6833_valid;
+ assign io_network_grant_bits_header_src = T_6833_bits_header_src;
+ assign io_network_grant_bits_header_dst = T_6833_bits_header_dst;
+ assign io_network_grant_bits_payload_addr_beat = T_6833_bits_payload_addr_beat;
+ assign io_network_grant_bits_payload_client_xact_id = T_6833_bits_payload_client_xact_id;
+ assign io_network_grant_bits_payload_manager_xact_id = T_6833_bits_payload_manager_xact_id;
+ assign io_network_grant_bits_payload_is_builtin_type = T_6833_bits_payload_is_builtin_type;
+ assign io_network_grant_bits_payload_g_type = T_6833_bits_payload_g_type;
+ assign io_network_grant_bits_payload_data = T_6833_bits_payload_data;
+ assign io_network_finish_ready = T_8022_ready;
+ assign io_network_probe_valid = T_7463_valid;
+ assign io_network_probe_bits_header_src = T_7463_bits_header_src;
+ assign io_network_probe_bits_header_dst = T_7463_bits_header_dst;
+ assign io_network_probe_bits_payload_addr_block = T_7463_bits_payload_addr_block;
+ assign io_network_probe_bits_payload_p_type = T_7463_bits_payload_p_type;
+ assign io_network_release_ready = T_7906_ready;
+ assign T_6833_ready = io_network_grant_ready;
+ assign T_6833_valid = io_manager_grant_valid;
+ assign T_6833_bits_header_src = 1'h0;
+ assign T_6833_bits_header_dst = io_manager_grant_bits_client_id;
+ assign T_6833_bits_payload_addr_beat = io_manager_grant_bits_addr_beat;
+ assign T_6833_bits_payload_client_xact_id = io_manager_grant_bits_client_xact_id;
+ assign T_6833_bits_payload_manager_xact_id = io_manager_grant_bits_manager_xact_id;
+ assign T_6833_bits_payload_is_builtin_type = io_manager_grant_bits_is_builtin_type;
+ assign T_6833_bits_payload_g_type = io_manager_grant_bits_g_type;
+ assign T_6833_bits_payload_data = io_manager_grant_bits_data;
+ assign T_6833_bits_payload_client_id = io_manager_grant_bits_client_id;
+ assign T_7463_ready = io_network_probe_ready;
+ assign T_7463_valid = io_manager_probe_valid;
+ assign T_7463_bits_header_src = 1'h0;
+ assign T_7463_bits_header_dst = io_manager_probe_bits_client_id;
+ assign T_7463_bits_payload_addr_block = io_manager_probe_bits_addr_block;
+ assign T_7463_bits_payload_p_type = io_manager_probe_bits_p_type;
+ assign T_7463_bits_payload_client_id = io_manager_probe_bits_client_id;
+ assign T_7778_ready = io_manager_acquire_ready;
+ assign T_7778_valid = io_network_acquire_valid;
+ assign T_7778_bits_addr_block = io_network_acquire_bits_payload_addr_block;
+ assign T_7778_bits_client_xact_id = io_network_acquire_bits_payload_client_xact_id;
+ assign T_7778_bits_addr_beat = io_network_acquire_bits_payload_addr_beat;
+ assign T_7778_bits_is_builtin_type = io_network_acquire_bits_payload_is_builtin_type;
+ assign T_7778_bits_a_type = io_network_acquire_bits_payload_a_type;
+ assign T_7778_bits_union = io_network_acquire_bits_payload_union;
+ assign T_7778_bits_data = io_network_acquire_bits_payload_data;
+ assign T_7906_ready = io_manager_release_ready;
+ assign T_7906_valid = io_network_release_valid;
+ assign T_7906_bits_addr_beat = io_network_release_bits_payload_addr_beat;
+ assign T_7906_bits_addr_block = io_network_release_bits_payload_addr_block;
+ assign T_7906_bits_client_xact_id = io_network_release_bits_payload_client_xact_id;
+ assign T_7906_bits_voluntary = io_network_release_bits_payload_voluntary;
+ assign T_7906_bits_r_type = io_network_release_bits_payload_r_type;
+ assign T_7906_bits_data = io_network_release_bits_payload_data;
+ assign T_8022_ready = io_manager_finish_ready;
+ assign T_8022_valid = io_network_finish_valid;
+ assign T_8022_bits_manager_xact_id = io_network_finish_bits_payload_manager_xact_id;
+endmodule
+module Queue_25(
+ input clk,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [1:0] io_enq_bits_header_src,
+ input [1:0] io_enq_bits_header_dst,
+ input [1:0] io_enq_bits_payload_addr_beat,
+ input [25:0] io_enq_bits_payload_addr_block,
+ input [1:0] io_enq_bits_payload_client_xact_id,
+ input io_enq_bits_payload_voluntary,
+ input [2:0] io_enq_bits_payload_r_type,
+ input [127:0] io_enq_bits_payload_data,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [1:0] io_deq_bits_header_src,
+ output [1:0] io_deq_bits_header_dst,
+ output [1:0] io_deq_bits_payload_addr_beat,
+ output [25:0] io_deq_bits_payload_addr_block,
+ output [1:0] io_deq_bits_payload_client_xact_id,
+ output io_deq_bits_payload_voluntary,
+ output [2:0] io_deq_bits_payload_r_type,
+ output [127:0] io_deq_bits_payload_data,
+ output io_count
+);
+ reg [1:0] ram_header_src [0:0];
+ wire [1:0] ram_header_src_T_1309_data;
+ wire ram_header_src_T_1309_addr;
+ wire ram_header_src_T_1309_en;
+ wire ram_header_src_T_1309_clk;
+ wire [1:0] ram_header_src_T_1170_data;
+ wire ram_header_src_T_1170_addr;
+ wire ram_header_src_T_1170_mask;
+ wire ram_header_src_T_1170_en;
+ wire ram_header_src_T_1170_clk;
+ reg [1:0] ram_header_dst [0:0];
+ wire [1:0] ram_header_dst_T_1309_data;
+ wire ram_header_dst_T_1309_addr;
+ wire ram_header_dst_T_1309_en;
+ wire ram_header_dst_T_1309_clk;
+ wire [1:0] ram_header_dst_T_1170_data;
+ wire ram_header_dst_T_1170_addr;
+ wire ram_header_dst_T_1170_mask;
+ wire ram_header_dst_T_1170_en;
+ wire ram_header_dst_T_1170_clk;
+ reg [1:0] ram_payload_addr_beat [0:0];
+ wire [1:0] ram_payload_addr_beat_T_1309_data;
+ wire ram_payload_addr_beat_T_1309_addr;
+ wire ram_payload_addr_beat_T_1309_en;
+ wire ram_payload_addr_beat_T_1309_clk;
+ wire [1:0] ram_payload_addr_beat_T_1170_data;
+ wire ram_payload_addr_beat_T_1170_addr;
+ wire ram_payload_addr_beat_T_1170_mask;
+ wire ram_payload_addr_beat_T_1170_en;
+ wire ram_payload_addr_beat_T_1170_clk;
+ reg [25:0] ram_payload_addr_block [0:0];
+ wire [25:0] ram_payload_addr_block_T_1309_data;
+ wire ram_payload_addr_block_T_1309_addr;
+ wire ram_payload_addr_block_T_1309_en;
+ wire ram_payload_addr_block_T_1309_clk;
+ wire [25:0] ram_payload_addr_block_T_1170_data;
+ wire ram_payload_addr_block_T_1170_addr;
+ wire ram_payload_addr_block_T_1170_mask;
+ wire ram_payload_addr_block_T_1170_en;
+ wire ram_payload_addr_block_T_1170_clk;
+ reg [1:0] ram_payload_client_xact_id [0:0];
+ wire [1:0] ram_payload_client_xact_id_T_1309_data;
+ wire ram_payload_client_xact_id_T_1309_addr;
+ wire ram_payload_client_xact_id_T_1309_en;
+ wire ram_payload_client_xact_id_T_1309_clk;
+ wire [1:0] ram_payload_client_xact_id_T_1170_data;
+ wire ram_payload_client_xact_id_T_1170_addr;
+ wire ram_payload_client_xact_id_T_1170_mask;
+ wire ram_payload_client_xact_id_T_1170_en;
+ wire ram_payload_client_xact_id_T_1170_clk;
+ reg ram_payload_voluntary [0:0];
+ wire ram_payload_voluntary_T_1309_data;
+ wire ram_payload_voluntary_T_1309_addr;
+ wire ram_payload_voluntary_T_1309_en;
+ wire ram_payload_voluntary_T_1309_clk;
+ wire ram_payload_voluntary_T_1170_data;
+ wire ram_payload_voluntary_T_1170_addr;
+ wire ram_payload_voluntary_T_1170_mask;
+ wire ram_payload_voluntary_T_1170_en;
+ wire ram_payload_voluntary_T_1170_clk;
+ reg [2:0] ram_payload_r_type [0:0];
+ wire [2:0] ram_payload_r_type_T_1309_data;
+ wire ram_payload_r_type_T_1309_addr;
+ wire ram_payload_r_type_T_1309_en;
+ wire ram_payload_r_type_T_1309_clk;
+ wire [2:0] ram_payload_r_type_T_1170_data;
+ wire ram_payload_r_type_T_1170_addr;
+ wire ram_payload_r_type_T_1170_mask;
+ wire ram_payload_r_type_T_1170_en;
+ wire ram_payload_r_type_T_1170_clk;
+ reg [127:0] ram_payload_data [0:0];
+ wire [127:0] ram_payload_data_T_1309_data;
+ wire ram_payload_data_T_1309_addr;
+ wire ram_payload_data_T_1309_en;
+ wire ram_payload_data_T_1309_clk;
+ wire [127:0] ram_payload_data_T_1170_data;
+ wire ram_payload_data_T_1170_addr;
+ wire ram_payload_data_T_1170_mask;
+ wire ram_payload_data_T_1170_en;
+ wire ram_payload_data_T_1170_clk;
+ reg maybe_full;
+ wire ptr_match;
+ wire T_1156;
+ wire empty;
+ wire full;
+ wire maybe_flow;
+ wire do_flow;
+ wire T_1162;
+ wire T_1164;
+ wire do_enq;
+ wire T_1166;
+ wire T_1168;
+ wire do_deq;
+ wire T_1298;
+ wire T_1300;
+ wire T_1302;
+ wire T_1303;
+ wire T_1305;
+ wire T_1307;
+ wire T_1308;
+ wire [1:0] T_1435_header_src;
+ wire [1:0] T_1435_header_dst;
+ wire [1:0] T_1435_payload_addr_beat;
+ wire [25:0] T_1435_payload_addr_block;
+ wire [1:0] T_1435_payload_client_xact_id;
+ wire T_1435_payload_voluntary;
+ wire [2:0] T_1435_payload_r_type;
+ wire [127:0] T_1435_payload_data;
+ wire [1:0] T_1561;
+ wire ptr_diff;
+ wire T_1563;
+ wire [1:0] T_1564;
+ assign io_enq_ready = T_1308;
+ assign io_deq_valid = T_1303;
+ assign io_deq_bits_header_src = T_1435_header_src;
+ assign io_deq_bits_header_dst = T_1435_header_dst;
+ assign io_deq_bits_payload_addr_beat = T_1435_payload_addr_beat;
+ assign io_deq_bits_payload_addr_block = T_1435_payload_addr_block;
+ assign io_deq_bits_payload_client_xact_id = T_1435_payload_client_xact_id;
+ assign io_deq_bits_payload_voluntary = T_1435_payload_voluntary;
+ assign io_deq_bits_payload_r_type = T_1435_payload_r_type;
+ assign io_deq_bits_payload_data = T_1435_payload_data;
+ assign io_count = T_1564;
+ assign ram_header_src_T_1309_addr = 1'h0;
+ assign ram_header_src_T_1309_en = 1'h1;
+ assign ram_header_src_T_1309_clk = clk;
+ assign ram_header_src_T_1309_data = ram_header_src[ram_header_src_T_1309_addr];
+ assign ram_header_src_T_1170_data = io_enq_bits_header_src;
+ assign ram_header_src_T_1170_addr = 1'h0;
+ assign ram_header_src_T_1170_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_header_src_T_1170_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_header_src_T_1170_clk = clk;
+ assign ram_header_dst_T_1309_addr = 1'h0;
+ assign ram_header_dst_T_1309_en = 1'h1;
+ assign ram_header_dst_T_1309_clk = clk;
+ assign ram_header_dst_T_1309_data = ram_header_dst[ram_header_dst_T_1309_addr];
+ assign ram_header_dst_T_1170_data = io_enq_bits_header_dst;
+ assign ram_header_dst_T_1170_addr = 1'h0;
+ assign ram_header_dst_T_1170_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_header_dst_T_1170_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_header_dst_T_1170_clk = clk;
+ assign ram_payload_addr_beat_T_1309_addr = 1'h0;
+ assign ram_payload_addr_beat_T_1309_en = 1'h1;
+ assign ram_payload_addr_beat_T_1309_clk = clk;
+ assign ram_payload_addr_beat_T_1309_data = ram_payload_addr_beat[ram_payload_addr_beat_T_1309_addr];
+ assign ram_payload_addr_beat_T_1170_data = io_enq_bits_payload_addr_beat;
+ assign ram_payload_addr_beat_T_1170_addr = 1'h0;
+ assign ram_payload_addr_beat_T_1170_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_addr_beat_T_1170_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_addr_beat_T_1170_clk = clk;
+ assign ram_payload_addr_block_T_1309_addr = 1'h0;
+ assign ram_payload_addr_block_T_1309_en = 1'h1;
+ assign ram_payload_addr_block_T_1309_clk = clk;
+ assign ram_payload_addr_block_T_1309_data = ram_payload_addr_block[ram_payload_addr_block_T_1309_addr];
+ assign ram_payload_addr_block_T_1170_data = io_enq_bits_payload_addr_block;
+ assign ram_payload_addr_block_T_1170_addr = 1'h0;
+ assign ram_payload_addr_block_T_1170_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_addr_block_T_1170_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_addr_block_T_1170_clk = clk;
+ assign ram_payload_client_xact_id_T_1309_addr = 1'h0;
+ assign ram_payload_client_xact_id_T_1309_en = 1'h1;
+ assign ram_payload_client_xact_id_T_1309_clk = clk;
+ assign ram_payload_client_xact_id_T_1309_data = ram_payload_client_xact_id[ram_payload_client_xact_id_T_1309_addr];
+ assign ram_payload_client_xact_id_T_1170_data = io_enq_bits_payload_client_xact_id;
+ assign ram_payload_client_xact_id_T_1170_addr = 1'h0;
+ assign ram_payload_client_xact_id_T_1170_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_client_xact_id_T_1170_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_client_xact_id_T_1170_clk = clk;
+ assign ram_payload_voluntary_T_1309_addr = 1'h0;
+ assign ram_payload_voluntary_T_1309_en = 1'h1;
+ assign ram_payload_voluntary_T_1309_clk = clk;
+ assign ram_payload_voluntary_T_1309_data = ram_payload_voluntary[ram_payload_voluntary_T_1309_addr];
+ assign ram_payload_voluntary_T_1170_data = io_enq_bits_payload_voluntary;
+ assign ram_payload_voluntary_T_1170_addr = 1'h0;
+ assign ram_payload_voluntary_T_1170_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_voluntary_T_1170_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_voluntary_T_1170_clk = clk;
+ assign ram_payload_r_type_T_1309_addr = 1'h0;
+ assign ram_payload_r_type_T_1309_en = 1'h1;
+ assign ram_payload_r_type_T_1309_clk = clk;
+ assign ram_payload_r_type_T_1309_data = ram_payload_r_type[ram_payload_r_type_T_1309_addr];
+ assign ram_payload_r_type_T_1170_data = io_enq_bits_payload_r_type;
+ assign ram_payload_r_type_T_1170_addr = 1'h0;
+ assign ram_payload_r_type_T_1170_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_r_type_T_1170_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_r_type_T_1170_clk = clk;
+ assign ram_payload_data_T_1309_addr = 1'h0;
+ assign ram_payload_data_T_1309_en = 1'h1;
+ assign ram_payload_data_T_1309_clk = clk;
+ assign ram_payload_data_T_1309_data = ram_payload_data[ram_payload_data_T_1309_addr];
+ assign ram_payload_data_T_1170_data = io_enq_bits_payload_data;
+ assign ram_payload_data_T_1170_addr = 1'h0;
+ assign ram_payload_data_T_1170_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_data_T_1170_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_payload_data_T_1170_clk = clk;
+ assign ptr_match = 1'h0 == 1'h0;
+ assign T_1156 = maybe_full == 1'h0;
+ assign empty = ptr_match & T_1156;
+ assign full = ptr_match & maybe_full;
+ assign maybe_flow = 1'h0 & empty;
+ assign do_flow = maybe_flow & io_deq_ready;
+ assign T_1162 = io_enq_ready & io_enq_valid;
+ assign T_1164 = do_flow == 1'h0;
+ assign do_enq = T_1162 & T_1164;
+ assign T_1166 = io_deq_ready & io_deq_valid;
+ assign T_1168 = do_flow == 1'h0;
+ assign do_deq = T_1166 & T_1168;
+ assign T_1298 = do_enq != do_deq;
+ assign T_1300 = empty == 1'h0;
+ assign T_1302 = 1'h0 & io_enq_valid;
+ assign T_1303 = T_1300 | T_1302;
+ assign T_1305 = full == 1'h0;
+ assign T_1307 = 1'h0 & io_deq_ready;
+ assign T_1308 = T_1305 | T_1307;
+ assign T_1435_header_src = maybe_flow ? io_enq_bits_header_src : ram_header_src_T_1309_data;
+ assign T_1435_header_dst = maybe_flow ? io_enq_bits_header_dst : ram_header_dst_T_1309_data;
+ assign T_1435_payload_addr_beat = maybe_flow ? io_enq_bits_payload_addr_beat : ram_payload_addr_beat_T_1309_data;
+ assign T_1435_payload_addr_block = maybe_flow ? io_enq_bits_payload_addr_block : ram_payload_addr_block_T_1309_data;
+ assign T_1435_payload_client_xact_id = maybe_flow ? io_enq_bits_payload_client_xact_id : ram_payload_client_xact_id_T_1309_data;
+ assign T_1435_payload_voluntary = maybe_flow ? io_enq_bits_payload_voluntary : ram_payload_voluntary_T_1309_data;
+ assign T_1435_payload_r_type = maybe_flow ? io_enq_bits_payload_r_type : ram_payload_r_type_T_1309_data;
+ assign T_1435_payload_data = maybe_flow ? io_enq_bits_payload_data : ram_payload_data_T_1309_data;
+ assign T_1561 = 1'h0 - 1'h0;
+ assign ptr_diff = T_1561[0:0];
+ assign T_1563 = maybe_full & ptr_match;
+ assign T_1564 = {T_1563,ptr_diff};
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_header_src[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_header_dst[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_payload_addr_beat[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_payload_addr_block[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_payload_client_xact_id[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_payload_voluntary[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_payload_r_type[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_payload_data[initvar] = {4{$random}};
+ maybe_full = {1{$random}};
+ end
+`endif
+ always @(posedge ram_header_src_T_1170_clk) begin
+ if(ram_header_src_T_1170_en & ram_header_src_T_1170_mask) begin
+ ram_header_src[ram_header_src_T_1170_addr] <= ram_header_src_T_1170_data;
+ end
+ end
+ always @(posedge ram_header_dst_T_1170_clk) begin
+ if(ram_header_dst_T_1170_en & ram_header_dst_T_1170_mask) begin
+ ram_header_dst[ram_header_dst_T_1170_addr] <= ram_header_dst_T_1170_data;
+ end
+ end
+ always @(posedge ram_payload_addr_beat_T_1170_clk) begin
+ if(ram_payload_addr_beat_T_1170_en & ram_payload_addr_beat_T_1170_mask) begin
+ ram_payload_addr_beat[ram_payload_addr_beat_T_1170_addr] <= ram_payload_addr_beat_T_1170_data;
+ end
+ end
+ always @(posedge ram_payload_addr_block_T_1170_clk) begin
+ if(ram_payload_addr_block_T_1170_en & ram_payload_addr_block_T_1170_mask) begin
+ ram_payload_addr_block[ram_payload_addr_block_T_1170_addr] <= ram_payload_addr_block_T_1170_data;
+ end
+ end
+ always @(posedge ram_payload_client_xact_id_T_1170_clk) begin
+ if(ram_payload_client_xact_id_T_1170_en & ram_payload_client_xact_id_T_1170_mask) begin
+ ram_payload_client_xact_id[ram_payload_client_xact_id_T_1170_addr] <= ram_payload_client_xact_id_T_1170_data;
+ end
+ end
+ always @(posedge ram_payload_voluntary_T_1170_clk) begin
+ if(ram_payload_voluntary_T_1170_en & ram_payload_voluntary_T_1170_mask) begin
+ ram_payload_voluntary[ram_payload_voluntary_T_1170_addr] <= ram_payload_voluntary_T_1170_data;
+ end
+ end
+ always @(posedge ram_payload_r_type_T_1170_clk) begin
+ if(ram_payload_r_type_T_1170_en & ram_payload_r_type_T_1170_mask) begin
+ ram_payload_r_type[ram_payload_r_type_T_1170_addr] <= ram_payload_r_type_T_1170_data;
+ end
+ end
+ always @(posedge ram_payload_data_T_1170_clk) begin
+ if(ram_payload_data_T_1170_en & ram_payload_data_T_1170_mask) begin
+ ram_payload_data[ram_payload_data_T_1170_addr] <= ram_payload_data_T_1170_data;
+ end
+ end
+ always @(posedge clk) begin
+ if(reset) begin
+ maybe_full <= 1'h0;
+ end else begin
+ if(T_1298) begin
+ maybe_full <= do_enq;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module TileLinkEnqueuer_24(
+ input clk,
+ input reset,
+ output io_client_acquire_ready,
+ input io_client_acquire_valid,
+ input [1:0] io_client_acquire_bits_header_src,
+ input [1:0] io_client_acquire_bits_header_dst,
+ input [25:0] io_client_acquire_bits_payload_addr_block,
+ input [1:0] io_client_acquire_bits_payload_client_xact_id,
+ input [1:0] io_client_acquire_bits_payload_addr_beat,
+ input io_client_acquire_bits_payload_is_builtin_type,
+ input [2:0] io_client_acquire_bits_payload_a_type,
+ input [16:0] io_client_acquire_bits_payload_union,
+ input [127:0] io_client_acquire_bits_payload_data,
+ input io_client_grant_ready,
+ output io_client_grant_valid,
+ output [1:0] io_client_grant_bits_header_src,
+ output [1:0] io_client_grant_bits_header_dst,
+ output [1:0] io_client_grant_bits_payload_addr_beat,
+ output [1:0] io_client_grant_bits_payload_client_xact_id,
+ output [3:0] io_client_grant_bits_payload_manager_xact_id,
+ output io_client_grant_bits_payload_is_builtin_type,
+ output [3:0] io_client_grant_bits_payload_g_type,
+ output [127:0] io_client_grant_bits_payload_data,
+ output io_client_finish_ready,
+ input io_client_finish_valid,
+ input [1:0] io_client_finish_bits_header_src,
+ input [1:0] io_client_finish_bits_header_dst,
+ input [3:0] io_client_finish_bits_payload_manager_xact_id,
+ input io_client_probe_ready,
+ output io_client_probe_valid,
+ output [1:0] io_client_probe_bits_header_src,
+ output [1:0] io_client_probe_bits_header_dst,
+ output [25:0] io_client_probe_bits_payload_addr_block,
+ output [1:0] io_client_probe_bits_payload_p_type,
+ output io_client_release_ready,
+ input io_client_release_valid,
+ input [1:0] io_client_release_bits_header_src,
+ input [1:0] io_client_release_bits_header_dst,
+ input [1:0] io_client_release_bits_payload_addr_beat,
+ input [25:0] io_client_release_bits_payload_addr_block,
+ input [1:0] io_client_release_bits_payload_client_xact_id,
+ input io_client_release_bits_payload_voluntary,
+ input [2:0] io_client_release_bits_payload_r_type,
+ input [127:0] io_client_release_bits_payload_data,
+ input io_manager_acquire_ready,
+ output io_manager_acquire_valid,
+ output [1:0] io_manager_acquire_bits_header_src,
+ output [1:0] io_manager_acquire_bits_header_dst,
+ output [25:0] io_manager_acquire_bits_payload_addr_block,
+ output [1:0] io_manager_acquire_bits_payload_client_xact_id,
+ output [1:0] io_manager_acquire_bits_payload_addr_beat,
+ output io_manager_acquire_bits_payload_is_builtin_type,
+ output [2:0] io_manager_acquire_bits_payload_a_type,
+ output [16:0] io_manager_acquire_bits_payload_union,
+ output [127:0] io_manager_acquire_bits_payload_data,
+ output io_manager_grant_ready,
+ input io_manager_grant_valid,
+ input [1:0] io_manager_grant_bits_header_src,
+ input [1:0] io_manager_grant_bits_header_dst,
+ input [1:0] io_manager_grant_bits_payload_addr_beat,
+ input [1:0] io_manager_grant_bits_payload_client_xact_id,
+ input [3:0] io_manager_grant_bits_payload_manager_xact_id,
+ input io_manager_grant_bits_payload_is_builtin_type,
+ input [3:0] io_manager_grant_bits_payload_g_type,
+ input [127:0] io_manager_grant_bits_payload_data,
+ input io_manager_finish_ready,
+ output io_manager_finish_valid,
+ output [1:0] io_manager_finish_bits_header_src,
+ output [1:0] io_manager_finish_bits_header_dst,
+ output [3:0] io_manager_finish_bits_payload_manager_xact_id,
+ output io_manager_probe_ready,
+ input io_manager_probe_valid,
+ input [1:0] io_manager_probe_bits_header_src,
+ input [1:0] io_manager_probe_bits_header_dst,
+ input [25:0] io_manager_probe_bits_payload_addr_block,
+ input [1:0] io_manager_probe_bits_payload_p_type,
+ input io_manager_release_ready,
+ output io_manager_release_valid,
+ output [1:0] io_manager_release_bits_header_src,
+ output [1:0] io_manager_release_bits_header_dst,
+ output [1:0] io_manager_release_bits_payload_addr_beat,
+ output [25:0] io_manager_release_bits_payload_addr_block,
+ output [1:0] io_manager_release_bits_payload_client_xact_id,
+ output io_manager_release_bits_payload_voluntary,
+ output [2:0] io_manager_release_bits_payload_r_type,
+ output [127:0] io_manager_release_bits_payload_data
+);
+ wire T_7777_clk;
+ wire T_7777_reset;
+ wire T_7777_io_enq_ready;
+ wire T_7777_io_enq_valid;
+ wire [1:0] T_7777_io_enq_bits_header_src;
+ wire [1:0] T_7777_io_enq_bits_header_dst;
+ wire [1:0] T_7777_io_enq_bits_payload_addr_beat;
+ wire [25:0] T_7777_io_enq_bits_payload_addr_block;
+ wire [1:0] T_7777_io_enq_bits_payload_client_xact_id;
+ wire T_7777_io_enq_bits_payload_voluntary;
+ wire [2:0] T_7777_io_enq_bits_payload_r_type;
+ wire [127:0] T_7777_io_enq_bits_payload_data;
+ wire T_7777_io_deq_ready;
+ wire T_7777_io_deq_valid;
+ wire [1:0] T_7777_io_deq_bits_header_src;
+ wire [1:0] T_7777_io_deq_bits_header_dst;
+ wire [1:0] T_7777_io_deq_bits_payload_addr_beat;
+ wire [25:0] T_7777_io_deq_bits_payload_addr_block;
+ wire [1:0] T_7777_io_deq_bits_payload_client_xact_id;
+ wire T_7777_io_deq_bits_payload_voluntary;
+ wire [2:0] T_7777_io_deq_bits_payload_r_type;
+ wire [127:0] T_7777_io_deq_bits_payload_data;
+ wire T_7777_io_count;
+ Queue_25 T_7777 (
+ .clk(T_7777_clk),
+ .reset(T_7777_reset),
+ .io_enq_ready(T_7777_io_enq_ready),
+ .io_enq_valid(T_7777_io_enq_valid),
+ .io_enq_bits_header_src(T_7777_io_enq_bits_header_src),
+ .io_enq_bits_header_dst(T_7777_io_enq_bits_header_dst),
+ .io_enq_bits_payload_addr_beat(T_7777_io_enq_bits_payload_addr_beat),
+ .io_enq_bits_payload_addr_block(T_7777_io_enq_bits_payload_addr_block),
+ .io_enq_bits_payload_client_xact_id(T_7777_io_enq_bits_payload_client_xact_id),
+ .io_enq_bits_payload_voluntary(T_7777_io_enq_bits_payload_voluntary),
+ .io_enq_bits_payload_r_type(T_7777_io_enq_bits_payload_r_type),
+ .io_enq_bits_payload_data(T_7777_io_enq_bits_payload_data),
+ .io_deq_ready(T_7777_io_deq_ready),
+ .io_deq_valid(T_7777_io_deq_valid),
+ .io_deq_bits_header_src(T_7777_io_deq_bits_header_src),
+ .io_deq_bits_header_dst(T_7777_io_deq_bits_header_dst),
+ .io_deq_bits_payload_addr_beat(T_7777_io_deq_bits_payload_addr_beat),
+ .io_deq_bits_payload_addr_block(T_7777_io_deq_bits_payload_addr_block),
+ .io_deq_bits_payload_client_xact_id(T_7777_io_deq_bits_payload_client_xact_id),
+ .io_deq_bits_payload_voluntary(T_7777_io_deq_bits_payload_voluntary),
+ .io_deq_bits_payload_r_type(T_7777_io_deq_bits_payload_r_type),
+ .io_deq_bits_payload_data(T_7777_io_deq_bits_payload_data),
+ .io_count(T_7777_io_count)
+ );
+ assign io_client_acquire_ready = io_manager_acquire_ready;
+ assign io_client_grant_valid = io_manager_grant_valid;
+ assign io_client_grant_bits_header_src = io_manager_grant_bits_header_src;
+ assign io_client_grant_bits_header_dst = io_manager_grant_bits_header_dst;
+ assign io_client_grant_bits_payload_addr_beat = io_manager_grant_bits_payload_addr_beat;
+ assign io_client_grant_bits_payload_client_xact_id = io_manager_grant_bits_payload_client_xact_id;
+ assign io_client_grant_bits_payload_manager_xact_id = io_manager_grant_bits_payload_manager_xact_id;
+ assign io_client_grant_bits_payload_is_builtin_type = io_manager_grant_bits_payload_is_builtin_type;
+ assign io_client_grant_bits_payload_g_type = io_manager_grant_bits_payload_g_type;
+ assign io_client_grant_bits_payload_data = io_manager_grant_bits_payload_data;
+ assign io_client_finish_ready = io_manager_finish_ready;
+ assign io_client_probe_valid = io_manager_probe_valid;
+ assign io_client_probe_bits_header_src = io_manager_probe_bits_header_src;
+ assign io_client_probe_bits_header_dst = io_manager_probe_bits_header_dst;
+ assign io_client_probe_bits_payload_addr_block = io_manager_probe_bits_payload_addr_block;
+ assign io_client_probe_bits_payload_p_type = io_manager_probe_bits_payload_p_type;
+ assign io_client_release_ready = T_7777_io_enq_ready;
+ assign io_manager_acquire_valid = io_client_acquire_valid;
+ assign io_manager_acquire_bits_header_src = io_client_acquire_bits_header_src;
+ assign io_manager_acquire_bits_header_dst = io_client_acquire_bits_header_dst;
+ assign io_manager_acquire_bits_payload_addr_block = io_client_acquire_bits_payload_addr_block;
+ assign io_manager_acquire_bits_payload_client_xact_id = io_client_acquire_bits_payload_client_xact_id;
+ assign io_manager_acquire_bits_payload_addr_beat = io_client_acquire_bits_payload_addr_beat;
+ assign io_manager_acquire_bits_payload_is_builtin_type = io_client_acquire_bits_payload_is_builtin_type;
+ assign io_manager_acquire_bits_payload_a_type = io_client_acquire_bits_payload_a_type;
+ assign io_manager_acquire_bits_payload_union = io_client_acquire_bits_payload_union;
+ assign io_manager_acquire_bits_payload_data = io_client_acquire_bits_payload_data;
+ assign io_manager_grant_ready = io_client_grant_ready;
+ assign io_manager_finish_valid = io_client_finish_valid;
+ assign io_manager_finish_bits_header_src = io_client_finish_bits_header_src;
+ assign io_manager_finish_bits_header_dst = io_client_finish_bits_header_dst;
+ assign io_manager_finish_bits_payload_manager_xact_id = io_client_finish_bits_payload_manager_xact_id;
+ assign io_manager_probe_ready = io_client_probe_ready;
+ assign io_manager_release_valid = T_7777_io_deq_valid;
+ assign io_manager_release_bits_header_src = T_7777_io_deq_bits_header_src;
+ assign io_manager_release_bits_header_dst = T_7777_io_deq_bits_header_dst;
+ assign io_manager_release_bits_payload_addr_beat = T_7777_io_deq_bits_payload_addr_beat;
+ assign io_manager_release_bits_payload_addr_block = T_7777_io_deq_bits_payload_addr_block;
+ assign io_manager_release_bits_payload_client_xact_id = T_7777_io_deq_bits_payload_client_xact_id;
+ assign io_manager_release_bits_payload_voluntary = T_7777_io_deq_bits_payload_voluntary;
+ assign io_manager_release_bits_payload_r_type = T_7777_io_deq_bits_payload_r_type;
+ assign io_manager_release_bits_payload_data = T_7777_io_deq_bits_payload_data;
+ assign T_7777_clk = clk;
+ assign T_7777_reset = reset;
+ assign T_7777_io_enq_valid = io_client_release_valid;
+ assign T_7777_io_enq_bits_header_src = io_client_release_bits_header_src;
+ assign T_7777_io_enq_bits_header_dst = io_client_release_bits_header_dst;
+ assign T_7777_io_enq_bits_payload_addr_beat = io_client_release_bits_payload_addr_beat;
+ assign T_7777_io_enq_bits_payload_addr_block = io_client_release_bits_payload_addr_block;
+ assign T_7777_io_enq_bits_payload_client_xact_id = io_client_release_bits_payload_client_xact_id;
+ assign T_7777_io_enq_bits_payload_voluntary = io_client_release_bits_payload_voluntary;
+ assign T_7777_io_enq_bits_payload_r_type = io_client_release_bits_payload_r_type;
+ assign T_7777_io_enq_bits_payload_data = io_client_release_bits_payload_data;
+ assign T_7777_io_deq_ready = io_manager_release_ready;
+endmodule
+module LockingRRArbiter(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input [1:0] io_in_0_bits_header_src,
+ input [1:0] io_in_0_bits_header_dst,
+ input [25:0] io_in_0_bits_payload_addr_block,
+ input [1:0] io_in_0_bits_payload_client_xact_id,
+ input [1:0] io_in_0_bits_payload_addr_beat,
+ input io_in_0_bits_payload_is_builtin_type,
+ input [2:0] io_in_0_bits_payload_a_type,
+ input [16:0] io_in_0_bits_payload_union,
+ input [127:0] io_in_0_bits_payload_data,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input [1:0] io_in_1_bits_header_src,
+ input [1:0] io_in_1_bits_header_dst,
+ input [25:0] io_in_1_bits_payload_addr_block,
+ input [1:0] io_in_1_bits_payload_client_xact_id,
+ input [1:0] io_in_1_bits_payload_addr_beat,
+ input io_in_1_bits_payload_is_builtin_type,
+ input [2:0] io_in_1_bits_payload_a_type,
+ input [16:0] io_in_1_bits_payload_union,
+ input [127:0] io_in_1_bits_payload_data,
+ output io_in_2_ready,
+ input io_in_2_valid,
+ input [1:0] io_in_2_bits_header_src,
+ input [1:0] io_in_2_bits_header_dst,
+ input [25:0] io_in_2_bits_payload_addr_block,
+ input [1:0] io_in_2_bits_payload_client_xact_id,
+ input [1:0] io_in_2_bits_payload_addr_beat,
+ input io_in_2_bits_payload_is_builtin_type,
+ input [2:0] io_in_2_bits_payload_a_type,
+ input [16:0] io_in_2_bits_payload_union,
+ input [127:0] io_in_2_bits_payload_data,
+ input io_out_ready,
+ output io_out_valid,
+ output [1:0] io_out_bits_header_src,
+ output [1:0] io_out_bits_header_dst,
+ output [25:0] io_out_bits_payload_addr_block,
+ output [1:0] io_out_bits_payload_client_xact_id,
+ output [1:0] io_out_bits_payload_addr_beat,
+ output io_out_bits_payload_is_builtin_type,
+ output [2:0] io_out_bits_payload_a_type,
+ output [16:0] io_out_bits_payload_union,
+ output [127:0] io_out_bits_payload_data,
+ output [1:0] io_chosen
+);
+ reg T_3348;
+ reg [1:0] T_3350;
+ wire [1:0] T_3352;
+ wire GEN_0;
+ wire [1:0] GEN_1;
+ wire [1:0] GEN_2;
+ wire [25:0] GEN_3;
+ wire [1:0] GEN_4;
+ wire [1:0] GEN_5;
+ wire GEN_6;
+ wire [2:0] GEN_7;
+ wire [16:0] GEN_8;
+ wire [127:0] GEN_9;
+ wire GEN_10;
+ reg [1:0] last_grant;
+ wire T_4128;
+ wire T_4129;
+ wire T_4131;
+ wire T_4132;
+ wire T_4134;
+ wire T_4135;
+ wire T_4138;
+ wire T_4140;
+ wire T_4142;
+ wire T_4143;
+ wire T_4145;
+ wire T_4147;
+ wire T_4148;
+ wire T_4149;
+ wire T_4151;
+ wire T_4153;
+ wire T_4154;
+ wire T_4155;
+ wire T_4156;
+ wire T_4158;
+ wire T_4160;
+ wire T_4161;
+ wire T_4162;
+ wire T_4163;
+ wire T_4164;
+ wire T_4166;
+ wire T_4168;
+ wire T_4169;
+ wire T_4170;
+ wire T_4172;
+ wire T_4173;
+ wire T_4174;
+ wire T_4176;
+ wire T_4177;
+ wire T_4178;
+ wire T_4180;
+ wire T_4181;
+ wire T_4182;
+ wire T_4184;
+ wire T_4185;
+ wire T_4186;
+ wire T_4188;
+ wire T_4189;
+ wire T_4190;
+ reg [1:0] T_4192;
+ wire [2:0] T_4194;
+ wire [1:0] T_4195;
+ wire T_4196;
+ wire T_4198;
+ wire [2:0] T_4201_0;
+ wire T_4204;
+ wire T_4206;
+ wire T_4207;
+ wire T_4209;
+ wire T_4211;
+ wire T_4212;
+ wire T_4213;
+ wire T_4215_0;
+ wire T_4215_1;
+ wire T_4215_2;
+ wire [1:0] T_4223;
+ wire [1:0] T_4224;
+ wire T_4226;
+ wire [1:0] T_4230;
+ wire [1:0] T_4232;
+ wire T_4234;
+ wire T_4235;
+ wire [1:0] T_4237;
+ wire T_4239;
+ wire T_4240;
+ wire [1:0] choose;
+ wire [1:0] T_4243;
+ wire T_4244;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ wire GEN_17;
+ wire GEN_18;
+ wire GEN_19;
+ wire GEN_20;
+ wire GEN_21;
+ wire GEN_22;
+ wire GEN_23;
+ wire GEN_24;
+ wire GEN_25;
+ wire GEN_26;
+ wire GEN_27;
+ wire GEN_28;
+ wire GEN_29;
+ wire GEN_30;
+ assign io_in_0_ready = T_4182;
+ assign io_in_1_ready = T_4186;
+ assign io_in_2_ready = T_4190;
+ assign io_out_valid = GEN_0;
+ assign io_out_bits_header_src = GEN_1;
+ assign io_out_bits_header_dst = GEN_2;
+ assign io_out_bits_payload_addr_block = GEN_3;
+ assign io_out_bits_payload_client_xact_id = GEN_4;
+ assign io_out_bits_payload_addr_beat = GEN_5;
+ assign io_out_bits_payload_is_builtin_type = GEN_6;
+ assign io_out_bits_payload_a_type = GEN_7;
+ assign io_out_bits_payload_union = GEN_8;
+ assign io_out_bits_payload_data = GEN_9;
+ assign io_chosen = T_3352;
+ assign T_3352 = T_4243;
+ assign GEN_0 = GEN_11 ? io_in_2_valid : GEN_12 ? io_in_1_valid : io_in_0_valid;
+ assign GEN_1 = GEN_13 ? io_in_2_bits_header_src : GEN_14 ? io_in_1_bits_header_src : io_in_0_bits_header_src;
+ assign GEN_2 = GEN_15 ? io_in_2_bits_header_dst : GEN_16 ? io_in_1_bits_header_dst : io_in_0_bits_header_dst;
+ assign GEN_3 = GEN_17 ? io_in_2_bits_payload_addr_block : GEN_18 ? io_in_1_bits_payload_addr_block : io_in_0_bits_payload_addr_block;
+ assign GEN_4 = GEN_19 ? io_in_2_bits_payload_client_xact_id : GEN_20 ? io_in_1_bits_payload_client_xact_id : io_in_0_bits_payload_client_xact_id;
+ assign GEN_5 = GEN_21 ? io_in_2_bits_payload_addr_beat : GEN_22 ? io_in_1_bits_payload_addr_beat : io_in_0_bits_payload_addr_beat;
+ assign GEN_6 = GEN_23 ? io_in_2_bits_payload_is_builtin_type : GEN_24 ? io_in_1_bits_payload_is_builtin_type : io_in_0_bits_payload_is_builtin_type;
+ assign GEN_7 = GEN_25 ? io_in_2_bits_payload_a_type : GEN_26 ? io_in_1_bits_payload_a_type : io_in_0_bits_payload_a_type;
+ assign GEN_8 = GEN_27 ? io_in_2_bits_payload_union : GEN_28 ? io_in_1_bits_payload_union : io_in_0_bits_payload_union;
+ assign GEN_9 = GEN_29 ? io_in_2_bits_payload_data : GEN_30 ? io_in_1_bits_payload_data : io_in_0_bits_payload_data;
+ assign GEN_10 = 1'h0;
+ assign T_4128 = 1'h0 > last_grant;
+ assign T_4129 = io_in_0_valid & T_4128;
+ assign T_4131 = 1'h1 > last_grant;
+ assign T_4132 = io_in_1_valid & T_4131;
+ assign T_4134 = 2'h2 > last_grant;
+ assign T_4135 = io_in_2_valid & T_4134;
+ assign T_4138 = 1'h0 | T_4129;
+ assign T_4140 = T_4138 == 1'h0;
+ assign T_4142 = 1'h0 | T_4129;
+ assign T_4143 = T_4142 | T_4132;
+ assign T_4145 = T_4143 == 1'h0;
+ assign T_4147 = 1'h0 | T_4129;
+ assign T_4148 = T_4147 | T_4132;
+ assign T_4149 = T_4148 | T_4135;
+ assign T_4151 = T_4149 == 1'h0;
+ assign T_4153 = 1'h0 | T_4129;
+ assign T_4154 = T_4153 | T_4132;
+ assign T_4155 = T_4154 | T_4135;
+ assign T_4156 = T_4155 | io_in_0_valid;
+ assign T_4158 = T_4156 == 1'h0;
+ assign T_4160 = 1'h0 | T_4129;
+ assign T_4161 = T_4160 | T_4132;
+ assign T_4162 = T_4161 | T_4135;
+ assign T_4163 = T_4162 | io_in_0_valid;
+ assign T_4164 = T_4163 | io_in_1_valid;
+ assign T_4166 = T_4164 == 1'h0;
+ assign T_4168 = 1'h0 > last_grant;
+ assign T_4169 = 1'h1 & T_4168;
+ assign T_4170 = T_4169 | T_4151;
+ assign T_4172 = 1'h1 > last_grant;
+ assign T_4173 = T_4140 & T_4172;
+ assign T_4174 = T_4173 | T_4158;
+ assign T_4176 = 2'h2 > last_grant;
+ assign T_4177 = T_4145 & T_4176;
+ assign T_4178 = T_4177 | T_4166;
+ assign T_4180 = T_3350 == 1'h0;
+ assign T_4181 = T_3348 ? T_4180 : T_4170;
+ assign T_4182 = T_4181 & io_out_ready;
+ assign T_4184 = T_3350 == 1'h1;
+ assign T_4185 = T_3348 ? T_4184 : T_4174;
+ assign T_4186 = T_4185 & io_out_ready;
+ assign T_4188 = T_3350 == 2'h2;
+ assign T_4189 = T_3348 ? T_4188 : T_4178;
+ assign T_4190 = T_4189 & io_out_ready;
+ assign T_4194 = T_4192 + 1'h1;
+ assign T_4195 = T_4194[1:0];
+ assign T_4196 = io_out_ready & io_out_valid;
+ assign T_4198 = 1'h1 & io_out_bits_payload_is_builtin_type;
+ assign T_4201_0 = 3'h3;
+ assign T_4204 = T_4201_0 == io_out_bits_payload_a_type;
+ assign T_4206 = 1'h0 | T_4204;
+ assign T_4207 = T_4198 & T_4206;
+ assign T_4209 = T_3348 == 1'h0;
+ assign T_4211 = io_in_0_ready & io_in_0_valid;
+ assign T_4212 = io_in_1_ready & io_in_1_valid;
+ assign T_4213 = io_in_2_ready & io_in_2_valid;
+ assign T_4215_0 = T_4211;
+ assign T_4215_1 = T_4212;
+ assign T_4215_2 = T_4213;
+ assign T_4223 = T_4215_1 ? 1'h1 : 2'h2;
+ assign T_4224 = T_4215_0 ? 1'h0 : T_4223;
+ assign T_4226 = T_4195 == 1'h0;
+ assign T_4230 = io_in_1_valid ? 1'h1 : 2'h2;
+ assign T_4232 = io_in_0_valid ? 1'h0 : T_4230;
+ assign T_4234 = 2'h2 > last_grant;
+ assign T_4235 = io_in_2_valid & T_4234;
+ assign T_4237 = T_4235 ? 2'h2 : T_4232;
+ assign T_4239 = 1'h1 > last_grant;
+ assign T_4240 = io_in_1_valid & T_4239;
+ assign choose = T_4240 ? 1'h1 : T_4237;
+ assign T_4243 = T_3348 ? T_3350 : choose;
+ assign T_4244 = io_out_ready & io_out_valid;
+ assign GEN_11 = 2'h2 == T_3352;
+ assign GEN_12 = 1'h1 == T_3352;
+ assign GEN_13 = 2'h2 == T_3352;
+ assign GEN_14 = 1'h1 == T_3352;
+ assign GEN_15 = 2'h2 == T_3352;
+ assign GEN_16 = 1'h1 == T_3352;
+ assign GEN_17 = 2'h2 == T_3352;
+ assign GEN_18 = 1'h1 == T_3352;
+ assign GEN_19 = 2'h2 == T_3352;
+ assign GEN_20 = 1'h1 == T_3352;
+ assign GEN_21 = 2'h2 == T_3352;
+ assign GEN_22 = 1'h1 == T_3352;
+ assign GEN_23 = 2'h2 == T_3352;
+ assign GEN_24 = 1'h1 == T_3352;
+ assign GEN_25 = 2'h2 == T_3352;
+ assign GEN_26 = 1'h1 == T_3352;
+ assign GEN_27 = 2'h2 == T_3352;
+ assign GEN_28 = 1'h1 == T_3352;
+ assign GEN_29 = 2'h2 == T_3352;
+ assign GEN_30 = 1'h1 == T_3352;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_3348 = {1{$random}};
+ T_3350 = {1{$random}};
+ last_grant = {1{$random}};
+ T_4192 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ T_3348 <= 1'h0;
+ end else begin
+ if(T_4196) begin
+ if(T_4226) begin
+ T_3348 <= 1'h0;
+ end else begin
+ if(T_4207) begin
+ if(T_4209) begin
+ T_3348 <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_3350 <= 2'h2;
+ end else begin
+ if(T_4196) begin
+ if(T_4207) begin
+ if(T_4209) begin
+ T_3350 <= T_4224;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ last_grant <= 2'h0;
+ end else begin
+ if(T_4244) begin
+ last_grant <= T_3352;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4192 <= 2'h0;
+ end else begin
+ if(T_4196) begin
+ if(T_4207) begin
+ T_4192 <= T_4195;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module LockingRRArbiter_26(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input [1:0] io_in_0_bits_header_src,
+ input [1:0] io_in_0_bits_header_dst,
+ input [1:0] io_in_0_bits_payload_addr_beat,
+ input [25:0] io_in_0_bits_payload_addr_block,
+ input [1:0] io_in_0_bits_payload_client_xact_id,
+ input io_in_0_bits_payload_voluntary,
+ input [2:0] io_in_0_bits_payload_r_type,
+ input [127:0] io_in_0_bits_payload_data,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input [1:0] io_in_1_bits_header_src,
+ input [1:0] io_in_1_bits_header_dst,
+ input [1:0] io_in_1_bits_payload_addr_beat,
+ input [25:0] io_in_1_bits_payload_addr_block,
+ input [1:0] io_in_1_bits_payload_client_xact_id,
+ input io_in_1_bits_payload_voluntary,
+ input [2:0] io_in_1_bits_payload_r_type,
+ input [127:0] io_in_1_bits_payload_data,
+ output io_in_2_ready,
+ input io_in_2_valid,
+ input [1:0] io_in_2_bits_header_src,
+ input [1:0] io_in_2_bits_header_dst,
+ input [1:0] io_in_2_bits_payload_addr_beat,
+ input [25:0] io_in_2_bits_payload_addr_block,
+ input [1:0] io_in_2_bits_payload_client_xact_id,
+ input io_in_2_bits_payload_voluntary,
+ input [2:0] io_in_2_bits_payload_r_type,
+ input [127:0] io_in_2_bits_payload_data,
+ input io_out_ready,
+ output io_out_valid,
+ output [1:0] io_out_bits_header_src,
+ output [1:0] io_out_bits_header_dst,
+ output [1:0] io_out_bits_payload_addr_beat,
+ output [25:0] io_out_bits_payload_addr_block,
+ output [1:0] io_out_bits_payload_client_xact_id,
+ output io_out_bits_payload_voluntary,
+ output [2:0] io_out_bits_payload_r_type,
+ output [127:0] io_out_bits_payload_data,
+ output [1:0] io_chosen
+);
+ reg T_3322;
+ reg [1:0] T_3324;
+ wire [1:0] T_3326;
+ wire GEN_0;
+ wire [1:0] GEN_1;
+ wire [1:0] GEN_2;
+ wire [1:0] GEN_3;
+ wire [25:0] GEN_4;
+ wire [1:0] GEN_5;
+ wire GEN_6;
+ wire [2:0] GEN_7;
+ wire [127:0] GEN_8;
+ wire GEN_9;
+ reg [1:0] last_grant;
+ wire T_4096;
+ wire T_4097;
+ wire T_4099;
+ wire T_4100;
+ wire T_4102;
+ wire T_4103;
+ wire T_4106;
+ wire T_4108;
+ wire T_4110;
+ wire T_4111;
+ wire T_4113;
+ wire T_4115;
+ wire T_4116;
+ wire T_4117;
+ wire T_4119;
+ wire T_4121;
+ wire T_4122;
+ wire T_4123;
+ wire T_4124;
+ wire T_4126;
+ wire T_4128;
+ wire T_4129;
+ wire T_4130;
+ wire T_4131;
+ wire T_4132;
+ wire T_4134;
+ wire T_4136;
+ wire T_4137;
+ wire T_4138;
+ wire T_4140;
+ wire T_4141;
+ wire T_4142;
+ wire T_4144;
+ wire T_4145;
+ wire T_4146;
+ wire T_4148;
+ wire T_4149;
+ wire T_4150;
+ wire T_4152;
+ wire T_4153;
+ wire T_4154;
+ wire T_4156;
+ wire T_4157;
+ wire T_4158;
+ reg [1:0] T_4160;
+ wire [2:0] T_4162;
+ wire [1:0] T_4163;
+ wire T_4164;
+ wire [1:0] T_4167_0;
+ wire [1:0] T_4167_1;
+ wire [1:0] T_4167_2;
+ wire T_4172;
+ wire T_4173;
+ wire T_4174;
+ wire T_4176;
+ wire T_4177;
+ wire T_4178;
+ wire T_4179;
+ wire T_4181;
+ wire T_4183;
+ wire T_4184;
+ wire T_4185;
+ wire T_4187_0;
+ wire T_4187_1;
+ wire T_4187_2;
+ wire [1:0] T_4195;
+ wire [1:0] T_4196;
+ wire T_4198;
+ wire [1:0] T_4202;
+ wire [1:0] T_4204;
+ wire T_4206;
+ wire T_4207;
+ wire [1:0] T_4209;
+ wire T_4211;
+ wire T_4212;
+ wire [1:0] choose;
+ wire [1:0] T_4215;
+ wire T_4216;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ wire GEN_17;
+ wire GEN_18;
+ wire GEN_19;
+ wire GEN_20;
+ wire GEN_21;
+ wire GEN_22;
+ wire GEN_23;
+ wire GEN_24;
+ wire GEN_25;
+ wire GEN_26;
+ wire GEN_27;
+ assign io_in_0_ready = T_4150;
+ assign io_in_1_ready = T_4154;
+ assign io_in_2_ready = T_4158;
+ assign io_out_valid = GEN_0;
+ assign io_out_bits_header_src = GEN_1;
+ assign io_out_bits_header_dst = GEN_2;
+ assign io_out_bits_payload_addr_beat = GEN_3;
+ assign io_out_bits_payload_addr_block = GEN_4;
+ assign io_out_bits_payload_client_xact_id = GEN_5;
+ assign io_out_bits_payload_voluntary = GEN_6;
+ assign io_out_bits_payload_r_type = GEN_7;
+ assign io_out_bits_payload_data = GEN_8;
+ assign io_chosen = T_3326;
+ assign T_3326 = T_4215;
+ assign GEN_0 = GEN_10 ? io_in_2_valid : GEN_11 ? io_in_1_valid : io_in_0_valid;
+ assign GEN_1 = GEN_12 ? io_in_2_bits_header_src : GEN_13 ? io_in_1_bits_header_src : io_in_0_bits_header_src;
+ assign GEN_2 = GEN_14 ? io_in_2_bits_header_dst : GEN_15 ? io_in_1_bits_header_dst : io_in_0_bits_header_dst;
+ assign GEN_3 = GEN_16 ? io_in_2_bits_payload_addr_beat : GEN_17 ? io_in_1_bits_payload_addr_beat : io_in_0_bits_payload_addr_beat;
+ assign GEN_4 = GEN_18 ? io_in_2_bits_payload_addr_block : GEN_19 ? io_in_1_bits_payload_addr_block : io_in_0_bits_payload_addr_block;
+ assign GEN_5 = GEN_20 ? io_in_2_bits_payload_client_xact_id : GEN_21 ? io_in_1_bits_payload_client_xact_id : io_in_0_bits_payload_client_xact_id;
+ assign GEN_6 = GEN_22 ? io_in_2_bits_payload_voluntary : GEN_23 ? io_in_1_bits_payload_voluntary : io_in_0_bits_payload_voluntary;
+ assign GEN_7 = GEN_24 ? io_in_2_bits_payload_r_type : GEN_25 ? io_in_1_bits_payload_r_type : io_in_0_bits_payload_r_type;
+ assign GEN_8 = GEN_26 ? io_in_2_bits_payload_data : GEN_27 ? io_in_1_bits_payload_data : io_in_0_bits_payload_data;
+ assign GEN_9 = 1'h0;
+ assign T_4096 = 1'h0 > last_grant;
+ assign T_4097 = io_in_0_valid & T_4096;
+ assign T_4099 = 1'h1 > last_grant;
+ assign T_4100 = io_in_1_valid & T_4099;
+ assign T_4102 = 2'h2 > last_grant;
+ assign T_4103 = io_in_2_valid & T_4102;
+ assign T_4106 = 1'h0 | T_4097;
+ assign T_4108 = T_4106 == 1'h0;
+ assign T_4110 = 1'h0 | T_4097;
+ assign T_4111 = T_4110 | T_4100;
+ assign T_4113 = T_4111 == 1'h0;
+ assign T_4115 = 1'h0 | T_4097;
+ assign T_4116 = T_4115 | T_4100;
+ assign T_4117 = T_4116 | T_4103;
+ assign T_4119 = T_4117 == 1'h0;
+ assign T_4121 = 1'h0 | T_4097;
+ assign T_4122 = T_4121 | T_4100;
+ assign T_4123 = T_4122 | T_4103;
+ assign T_4124 = T_4123 | io_in_0_valid;
+ assign T_4126 = T_4124 == 1'h0;
+ assign T_4128 = 1'h0 | T_4097;
+ assign T_4129 = T_4128 | T_4100;
+ assign T_4130 = T_4129 | T_4103;
+ assign T_4131 = T_4130 | io_in_0_valid;
+ assign T_4132 = T_4131 | io_in_1_valid;
+ assign T_4134 = T_4132 == 1'h0;
+ assign T_4136 = 1'h0 > last_grant;
+ assign T_4137 = 1'h1 & T_4136;
+ assign T_4138 = T_4137 | T_4119;
+ assign T_4140 = 1'h1 > last_grant;
+ assign T_4141 = T_4108 & T_4140;
+ assign T_4142 = T_4141 | T_4126;
+ assign T_4144 = 2'h2 > last_grant;
+ assign T_4145 = T_4113 & T_4144;
+ assign T_4146 = T_4145 | T_4134;
+ assign T_4148 = T_3324 == 1'h0;
+ assign T_4149 = T_3322 ? T_4148 : T_4138;
+ assign T_4150 = T_4149 & io_out_ready;
+ assign T_4152 = T_3324 == 1'h1;
+ assign T_4153 = T_3322 ? T_4152 : T_4142;
+ assign T_4154 = T_4153 & io_out_ready;
+ assign T_4156 = T_3324 == 2'h2;
+ assign T_4157 = T_3322 ? T_4156 : T_4146;
+ assign T_4158 = T_4157 & io_out_ready;
+ assign T_4162 = T_4160 + 1'h1;
+ assign T_4163 = T_4162[1:0];
+ assign T_4164 = io_out_ready & io_out_valid;
+ assign T_4167_0 = 1'h0;
+ assign T_4167_1 = 1'h1;
+ assign T_4167_2 = 2'h2;
+ assign T_4172 = T_4167_0 == io_out_bits_payload_r_type;
+ assign T_4173 = T_4167_1 == io_out_bits_payload_r_type;
+ assign T_4174 = T_4167_2 == io_out_bits_payload_r_type;
+ assign T_4176 = 1'h0 | T_4172;
+ assign T_4177 = T_4176 | T_4173;
+ assign T_4178 = T_4177 | T_4174;
+ assign T_4179 = 1'h1 & T_4178;
+ assign T_4181 = T_3322 == 1'h0;
+ assign T_4183 = io_in_0_ready & io_in_0_valid;
+ assign T_4184 = io_in_1_ready & io_in_1_valid;
+ assign T_4185 = io_in_2_ready & io_in_2_valid;
+ assign T_4187_0 = T_4183;
+ assign T_4187_1 = T_4184;
+ assign T_4187_2 = T_4185;
+ assign T_4195 = T_4187_1 ? 1'h1 : 2'h2;
+ assign T_4196 = T_4187_0 ? 1'h0 : T_4195;
+ assign T_4198 = T_4163 == 1'h0;
+ assign T_4202 = io_in_1_valid ? 1'h1 : 2'h2;
+ assign T_4204 = io_in_0_valid ? 1'h0 : T_4202;
+ assign T_4206 = 2'h2 > last_grant;
+ assign T_4207 = io_in_2_valid & T_4206;
+ assign T_4209 = T_4207 ? 2'h2 : T_4204;
+ assign T_4211 = 1'h1 > last_grant;
+ assign T_4212 = io_in_1_valid & T_4211;
+ assign choose = T_4212 ? 1'h1 : T_4209;
+ assign T_4215 = T_3322 ? T_3324 : choose;
+ assign T_4216 = io_out_ready & io_out_valid;
+ assign GEN_10 = 2'h2 == T_3326;
+ assign GEN_11 = 1'h1 == T_3326;
+ assign GEN_12 = 2'h2 == T_3326;
+ assign GEN_13 = 1'h1 == T_3326;
+ assign GEN_14 = 2'h2 == T_3326;
+ assign GEN_15 = 1'h1 == T_3326;
+ assign GEN_16 = 2'h2 == T_3326;
+ assign GEN_17 = 1'h1 == T_3326;
+ assign GEN_18 = 2'h2 == T_3326;
+ assign GEN_19 = 1'h1 == T_3326;
+ assign GEN_20 = 2'h2 == T_3326;
+ assign GEN_21 = 1'h1 == T_3326;
+ assign GEN_22 = 2'h2 == T_3326;
+ assign GEN_23 = 1'h1 == T_3326;
+ assign GEN_24 = 2'h2 == T_3326;
+ assign GEN_25 = 1'h1 == T_3326;
+ assign GEN_26 = 2'h2 == T_3326;
+ assign GEN_27 = 1'h1 == T_3326;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_3322 = {1{$random}};
+ T_3324 = {1{$random}};
+ last_grant = {1{$random}};
+ T_4160 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ T_3322 <= 1'h0;
+ end else begin
+ if(T_4164) begin
+ if(T_4198) begin
+ T_3322 <= 1'h0;
+ end else begin
+ if(T_4179) begin
+ if(T_4181) begin
+ T_3322 <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_3324 <= 2'h2;
+ end else begin
+ if(T_4164) begin
+ if(T_4179) begin
+ if(T_4181) begin
+ T_3324 <= T_4196;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ last_grant <= 2'h0;
+ end else begin
+ if(T_4216) begin
+ last_grant <= T_3326;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4160 <= 2'h0;
+ end else begin
+ if(T_4164) begin
+ if(T_4179) begin
+ T_4160 <= T_4163;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module RRArbiter(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input [1:0] io_in_0_bits_header_src,
+ input [1:0] io_in_0_bits_header_dst,
+ input [3:0] io_in_0_bits_payload_manager_xact_id,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input [1:0] io_in_1_bits_header_src,
+ input [1:0] io_in_1_bits_header_dst,
+ input [3:0] io_in_1_bits_payload_manager_xact_id,
+ output io_in_2_ready,
+ input io_in_2_valid,
+ input [1:0] io_in_2_bits_header_src,
+ input [1:0] io_in_2_bits_header_dst,
+ input [3:0] io_in_2_bits_payload_manager_xact_id,
+ input io_out_ready,
+ output io_out_valid,
+ output [1:0] io_out_bits_header_src,
+ output [1:0] io_out_bits_header_dst,
+ output [3:0] io_out_bits_payload_manager_xact_id,
+ output [1:0] io_chosen
+);
+ wire [1:0] T_3194;
+ wire GEN_0;
+ wire [1:0] GEN_1;
+ wire [1:0] GEN_2;
+ wire [3:0] GEN_3;
+ wire GEN_4;
+ reg [1:0] T_3933;
+ wire T_3934;
+ wire T_3935;
+ wire T_3937;
+ wire T_3938;
+ wire T_3940;
+ wire T_3941;
+ wire T_3944;
+ wire T_3946;
+ wire T_3948;
+ wire T_3949;
+ wire T_3951;
+ wire T_3953;
+ wire T_3954;
+ wire T_3955;
+ wire T_3957;
+ wire T_3959;
+ wire T_3960;
+ wire T_3961;
+ wire T_3962;
+ wire T_3964;
+ wire T_3966;
+ wire T_3967;
+ wire T_3968;
+ wire T_3969;
+ wire T_3970;
+ wire T_3972;
+ wire T_3974;
+ wire T_3975;
+ wire T_3976;
+ wire T_3978;
+ wire T_3979;
+ wire T_3980;
+ wire T_3982;
+ wire T_3983;
+ wire T_3984;
+ wire T_3986;
+ wire T_3987;
+ wire T_3988;
+ wire T_3990;
+ wire T_3991;
+ wire T_3992;
+ wire T_3994;
+ wire T_3995;
+ wire T_3996;
+ wire [1:0] T_3999;
+ wire [1:0] T_4001;
+ wire T_4003;
+ wire T_4004;
+ wire [1:0] T_4006;
+ wire T_4008;
+ wire T_4009;
+ wire [1:0] T_4011;
+ wire [1:0] T_4012;
+ wire T_4013;
+ wire GEN_5;
+ wire GEN_6;
+ wire GEN_7;
+ wire GEN_8;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ assign io_in_0_ready = T_3988;
+ assign io_in_1_ready = T_3992;
+ assign io_in_2_ready = T_3996;
+ assign io_out_valid = GEN_0;
+ assign io_out_bits_header_src = GEN_1;
+ assign io_out_bits_header_dst = GEN_2;
+ assign io_out_bits_payload_manager_xact_id = GEN_3;
+ assign io_chosen = T_3194;
+ assign T_3194 = T_4012;
+ assign GEN_0 = GEN_5 ? io_in_2_valid : GEN_6 ? io_in_1_valid : io_in_0_valid;
+ assign GEN_1 = GEN_7 ? io_in_2_bits_header_src : GEN_8 ? io_in_1_bits_header_src : io_in_0_bits_header_src;
+ assign GEN_2 = GEN_9 ? io_in_2_bits_header_dst : GEN_10 ? io_in_1_bits_header_dst : io_in_0_bits_header_dst;
+ assign GEN_3 = GEN_11 ? io_in_2_bits_payload_manager_xact_id : GEN_12 ? io_in_1_bits_payload_manager_xact_id : io_in_0_bits_payload_manager_xact_id;
+ assign GEN_4 = 1'h0;
+ assign T_3934 = 1'h0 > T_3933;
+ assign T_3935 = io_in_0_valid & T_3934;
+ assign T_3937 = 1'h1 > T_3933;
+ assign T_3938 = io_in_1_valid & T_3937;
+ assign T_3940 = 2'h2 > T_3933;
+ assign T_3941 = io_in_2_valid & T_3940;
+ assign T_3944 = 1'h0 | T_3935;
+ assign T_3946 = T_3944 == 1'h0;
+ assign T_3948 = 1'h0 | T_3935;
+ assign T_3949 = T_3948 | T_3938;
+ assign T_3951 = T_3949 == 1'h0;
+ assign T_3953 = 1'h0 | T_3935;
+ assign T_3954 = T_3953 | T_3938;
+ assign T_3955 = T_3954 | T_3941;
+ assign T_3957 = T_3955 == 1'h0;
+ assign T_3959 = 1'h0 | T_3935;
+ assign T_3960 = T_3959 | T_3938;
+ assign T_3961 = T_3960 | T_3941;
+ assign T_3962 = T_3961 | io_in_0_valid;
+ assign T_3964 = T_3962 == 1'h0;
+ assign T_3966 = 1'h0 | T_3935;
+ assign T_3967 = T_3966 | T_3938;
+ assign T_3968 = T_3967 | T_3941;
+ assign T_3969 = T_3968 | io_in_0_valid;
+ assign T_3970 = T_3969 | io_in_1_valid;
+ assign T_3972 = T_3970 == 1'h0;
+ assign T_3974 = 1'h0 > T_3933;
+ assign T_3975 = 1'h1 & T_3974;
+ assign T_3976 = T_3975 | T_3957;
+ assign T_3978 = 1'h1 > T_3933;
+ assign T_3979 = T_3946 & T_3978;
+ assign T_3980 = T_3979 | T_3964;
+ assign T_3982 = 2'h2 > T_3933;
+ assign T_3983 = T_3951 & T_3982;
+ assign T_3984 = T_3983 | T_3972;
+ assign T_3986 = 2'h2 == 1'h0;
+ assign T_3987 = 1'h0 ? T_3986 : T_3976;
+ assign T_3988 = T_3987 & io_out_ready;
+ assign T_3990 = 2'h2 == 1'h1;
+ assign T_3991 = 1'h0 ? T_3990 : T_3980;
+ assign T_3992 = T_3991 & io_out_ready;
+ assign T_3994 = 2'h2 == 2'h2;
+ assign T_3995 = 1'h0 ? T_3994 : T_3984;
+ assign T_3996 = T_3995 & io_out_ready;
+ assign T_3999 = io_in_1_valid ? 1'h1 : 2'h2;
+ assign T_4001 = io_in_0_valid ? 1'h0 : T_3999;
+ assign T_4003 = 2'h2 > T_3933;
+ assign T_4004 = io_in_2_valid & T_4003;
+ assign T_4006 = T_4004 ? 2'h2 : T_4001;
+ assign T_4008 = 1'h1 > T_3933;
+ assign T_4009 = io_in_1_valid & T_4008;
+ assign T_4011 = T_4009 ? 1'h1 : T_4006;
+ assign T_4012 = 1'h0 ? 2'h2 : T_4011;
+ assign T_4013 = io_out_ready & io_out_valid;
+ assign GEN_5 = 2'h2 == T_3194;
+ assign GEN_6 = 1'h1 == T_3194;
+ assign GEN_7 = 2'h2 == T_3194;
+ assign GEN_8 = 1'h1 == T_3194;
+ assign GEN_9 = 2'h2 == T_3194;
+ assign GEN_10 = 1'h1 == T_3194;
+ assign GEN_11 = 2'h2 == T_3194;
+ assign GEN_12 = 1'h1 == T_3194;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_3933 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ T_3933 <= 2'h0;
+ end else begin
+ if(T_4013) begin
+ T_3933 <= T_3194;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module RocketChipTileLinkArbiter(
+ input clk,
+ input reset,
+ output io_clients_0_acquire_ready,
+ input io_clients_0_acquire_valid,
+ input [25:0] io_clients_0_acquire_bits_addr_block,
+ input [1:0] io_clients_0_acquire_bits_client_xact_id,
+ input [1:0] io_clients_0_acquire_bits_addr_beat,
+ input io_clients_0_acquire_bits_is_builtin_type,
+ input [2:0] io_clients_0_acquire_bits_a_type,
+ input [16:0] io_clients_0_acquire_bits_union,
+ input [127:0] io_clients_0_acquire_bits_data,
+ input io_clients_0_grant_ready,
+ output io_clients_0_grant_valid,
+ output [1:0] io_clients_0_grant_bits_addr_beat,
+ output [1:0] io_clients_0_grant_bits_client_xact_id,
+ output [3:0] io_clients_0_grant_bits_manager_xact_id,
+ output io_clients_0_grant_bits_is_builtin_type,
+ output [3:0] io_clients_0_grant_bits_g_type,
+ output [127:0] io_clients_0_grant_bits_data,
+ input io_clients_0_probe_ready,
+ output io_clients_0_probe_valid,
+ output [25:0] io_clients_0_probe_bits_addr_block,
+ output [1:0] io_clients_0_probe_bits_p_type,
+ output io_clients_0_release_ready,
+ input io_clients_0_release_valid,
+ input [1:0] io_clients_0_release_bits_addr_beat,
+ input [25:0] io_clients_0_release_bits_addr_block,
+ input [1:0] io_clients_0_release_bits_client_xact_id,
+ input io_clients_0_release_bits_voluntary,
+ input [2:0] io_clients_0_release_bits_r_type,
+ input [127:0] io_clients_0_release_bits_data,
+ output io_clients_1_acquire_ready,
+ input io_clients_1_acquire_valid,
+ input [25:0] io_clients_1_acquire_bits_addr_block,
+ input [1:0] io_clients_1_acquire_bits_client_xact_id,
+ input [1:0] io_clients_1_acquire_bits_addr_beat,
+ input io_clients_1_acquire_bits_is_builtin_type,
+ input [2:0] io_clients_1_acquire_bits_a_type,
+ input [16:0] io_clients_1_acquire_bits_union,
+ input [127:0] io_clients_1_acquire_bits_data,
+ input io_clients_1_grant_ready,
+ output io_clients_1_grant_valid,
+ output [1:0] io_clients_1_grant_bits_addr_beat,
+ output [1:0] io_clients_1_grant_bits_client_xact_id,
+ output [3:0] io_clients_1_grant_bits_manager_xact_id,
+ output io_clients_1_grant_bits_is_builtin_type,
+ output [3:0] io_clients_1_grant_bits_g_type,
+ output [127:0] io_clients_1_grant_bits_data,
+ input io_clients_1_probe_ready,
+ output io_clients_1_probe_valid,
+ output [25:0] io_clients_1_probe_bits_addr_block,
+ output [1:0] io_clients_1_probe_bits_p_type,
+ output io_clients_1_release_ready,
+ input io_clients_1_release_valid,
+ input [1:0] io_clients_1_release_bits_addr_beat,
+ input [25:0] io_clients_1_release_bits_addr_block,
+ input [1:0] io_clients_1_release_bits_client_xact_id,
+ input io_clients_1_release_bits_voluntary,
+ input [2:0] io_clients_1_release_bits_r_type,
+ input [127:0] io_clients_1_release_bits_data,
+ output io_clients_2_acquire_ready,
+ input io_clients_2_acquire_valid,
+ input [25:0] io_clients_2_acquire_bits_addr_block,
+ input [1:0] io_clients_2_acquire_bits_client_xact_id,
+ input [1:0] io_clients_2_acquire_bits_addr_beat,
+ input io_clients_2_acquire_bits_is_builtin_type,
+ input [2:0] io_clients_2_acquire_bits_a_type,
+ input [16:0] io_clients_2_acquire_bits_union,
+ input [127:0] io_clients_2_acquire_bits_data,
+ input io_clients_2_grant_ready,
+ output io_clients_2_grant_valid,
+ output [1:0] io_clients_2_grant_bits_addr_beat,
+ output [1:0] io_clients_2_grant_bits_client_xact_id,
+ output [3:0] io_clients_2_grant_bits_manager_xact_id,
+ output io_clients_2_grant_bits_is_builtin_type,
+ output [3:0] io_clients_2_grant_bits_g_type,
+ output [127:0] io_clients_2_grant_bits_data,
+ input io_clients_2_probe_ready,
+ output io_clients_2_probe_valid,
+ output [25:0] io_clients_2_probe_bits_addr_block,
+ output [1:0] io_clients_2_probe_bits_p_type,
+ output io_clients_2_release_ready,
+ input io_clients_2_release_valid,
+ input [1:0] io_clients_2_release_bits_addr_beat,
+ input [25:0] io_clients_2_release_bits_addr_block,
+ input [1:0] io_clients_2_release_bits_client_xact_id,
+ input io_clients_2_release_bits_voluntary,
+ input [2:0] io_clients_2_release_bits_r_type,
+ input [127:0] io_clients_2_release_bits_data,
+ input io_managers_0_acquire_ready,
+ output io_managers_0_acquire_valid,
+ output [25:0] io_managers_0_acquire_bits_addr_block,
+ output [1:0] io_managers_0_acquire_bits_client_xact_id,
+ output [1:0] io_managers_0_acquire_bits_addr_beat,
+ output io_managers_0_acquire_bits_is_builtin_type,
+ output [2:0] io_managers_0_acquire_bits_a_type,
+ output [16:0] io_managers_0_acquire_bits_union,
+ output [127:0] io_managers_0_acquire_bits_data,
+ output [1:0] io_managers_0_acquire_bits_client_id,
+ output io_managers_0_grant_ready,
+ input io_managers_0_grant_valid,
+ input [1:0] io_managers_0_grant_bits_addr_beat,
+ input [1:0] io_managers_0_grant_bits_client_xact_id,
+ input [3:0] io_managers_0_grant_bits_manager_xact_id,
+ input io_managers_0_grant_bits_is_builtin_type,
+ input [3:0] io_managers_0_grant_bits_g_type,
+ input [127:0] io_managers_0_grant_bits_data,
+ input [1:0] io_managers_0_grant_bits_client_id,
+ input io_managers_0_finish_ready,
+ output io_managers_0_finish_valid,
+ output [3:0] io_managers_0_finish_bits_manager_xact_id,
+ output io_managers_0_probe_ready,
+ input io_managers_0_probe_valid,
+ input [25:0] io_managers_0_probe_bits_addr_block,
+ input [1:0] io_managers_0_probe_bits_p_type,
+ input [1:0] io_managers_0_probe_bits_client_id,
+ input io_managers_0_release_ready,
+ output io_managers_0_release_valid,
+ output [1:0] io_managers_0_release_bits_addr_beat,
+ output [25:0] io_managers_0_release_bits_addr_block,
+ output [1:0] io_managers_0_release_bits_client_xact_id,
+ output io_managers_0_release_bits_voluntary,
+ output [2:0] io_managers_0_release_bits_r_type,
+ output [127:0] io_managers_0_release_bits_data,
+ output [1:0] io_managers_0_release_bits_client_id
+);
+ wire T_11386_clk;
+ wire T_11386_reset;
+ wire T_11386_io_client_acquire_ready;
+ wire T_11386_io_client_acquire_valid;
+ wire [25:0] T_11386_io_client_acquire_bits_addr_block;
+ wire [1:0] T_11386_io_client_acquire_bits_client_xact_id;
+ wire [1:0] T_11386_io_client_acquire_bits_addr_beat;
+ wire T_11386_io_client_acquire_bits_is_builtin_type;
+ wire [2:0] T_11386_io_client_acquire_bits_a_type;
+ wire [16:0] T_11386_io_client_acquire_bits_union;
+ wire [127:0] T_11386_io_client_acquire_bits_data;
+ wire T_11386_io_client_grant_ready;
+ wire T_11386_io_client_grant_valid;
+ wire [1:0] T_11386_io_client_grant_bits_addr_beat;
+ wire [1:0] T_11386_io_client_grant_bits_client_xact_id;
+ wire [3:0] T_11386_io_client_grant_bits_manager_xact_id;
+ wire T_11386_io_client_grant_bits_is_builtin_type;
+ wire [3:0] T_11386_io_client_grant_bits_g_type;
+ wire [127:0] T_11386_io_client_grant_bits_data;
+ wire T_11386_io_client_probe_ready;
+ wire T_11386_io_client_probe_valid;
+ wire [25:0] T_11386_io_client_probe_bits_addr_block;
+ wire [1:0] T_11386_io_client_probe_bits_p_type;
+ wire T_11386_io_client_release_ready;
+ wire T_11386_io_client_release_valid;
+ wire [1:0] T_11386_io_client_release_bits_addr_beat;
+ wire [25:0] T_11386_io_client_release_bits_addr_block;
+ wire [1:0] T_11386_io_client_release_bits_client_xact_id;
+ wire T_11386_io_client_release_bits_voluntary;
+ wire [2:0] T_11386_io_client_release_bits_r_type;
+ wire [127:0] T_11386_io_client_release_bits_data;
+ wire T_11386_io_network_acquire_ready;
+ wire T_11386_io_network_acquire_valid;
+ wire [1:0] T_11386_io_network_acquire_bits_header_src;
+ wire [1:0] T_11386_io_network_acquire_bits_header_dst;
+ wire [25:0] T_11386_io_network_acquire_bits_payload_addr_block;
+ wire [1:0] T_11386_io_network_acquire_bits_payload_client_xact_id;
+ wire [1:0] T_11386_io_network_acquire_bits_payload_addr_beat;
+ wire T_11386_io_network_acquire_bits_payload_is_builtin_type;
+ wire [2:0] T_11386_io_network_acquire_bits_payload_a_type;
+ wire [16:0] T_11386_io_network_acquire_bits_payload_union;
+ wire [127:0] T_11386_io_network_acquire_bits_payload_data;
+ wire T_11386_io_network_grant_ready;
+ wire T_11386_io_network_grant_valid;
+ wire [1:0] T_11386_io_network_grant_bits_header_src;
+ wire [1:0] T_11386_io_network_grant_bits_header_dst;
+ wire [1:0] T_11386_io_network_grant_bits_payload_addr_beat;
+ wire [1:0] T_11386_io_network_grant_bits_payload_client_xact_id;
+ wire [3:0] T_11386_io_network_grant_bits_payload_manager_xact_id;
+ wire T_11386_io_network_grant_bits_payload_is_builtin_type;
+ wire [3:0] T_11386_io_network_grant_bits_payload_g_type;
+ wire [127:0] T_11386_io_network_grant_bits_payload_data;
+ wire T_11386_io_network_finish_ready;
+ wire T_11386_io_network_finish_valid;
+ wire [1:0] T_11386_io_network_finish_bits_header_src;
+ wire [1:0] T_11386_io_network_finish_bits_header_dst;
+ wire [3:0] T_11386_io_network_finish_bits_payload_manager_xact_id;
+ wire T_11386_io_network_probe_ready;
+ wire T_11386_io_network_probe_valid;
+ wire [1:0] T_11386_io_network_probe_bits_header_src;
+ wire [1:0] T_11386_io_network_probe_bits_header_dst;
+ wire [25:0] T_11386_io_network_probe_bits_payload_addr_block;
+ wire [1:0] T_11386_io_network_probe_bits_payload_p_type;
+ wire T_11386_io_network_release_ready;
+ wire T_11386_io_network_release_valid;
+ wire [1:0] T_11386_io_network_release_bits_header_src;
+ wire [1:0] T_11386_io_network_release_bits_header_dst;
+ wire [1:0] T_11386_io_network_release_bits_payload_addr_beat;
+ wire [25:0] T_11386_io_network_release_bits_payload_addr_block;
+ wire [1:0] T_11386_io_network_release_bits_payload_client_xact_id;
+ wire T_11386_io_network_release_bits_payload_voluntary;
+ wire [2:0] T_11386_io_network_release_bits_payload_r_type;
+ wire [127:0] T_11386_io_network_release_bits_payload_data;
+ wire T_11387_clk;
+ wire T_11387_reset;
+ wire T_11387_io_client_acquire_ready;
+ wire T_11387_io_client_acquire_valid;
+ wire [1:0] T_11387_io_client_acquire_bits_header_src;
+ wire [1:0] T_11387_io_client_acquire_bits_header_dst;
+ wire [25:0] T_11387_io_client_acquire_bits_payload_addr_block;
+ wire [1:0] T_11387_io_client_acquire_bits_payload_client_xact_id;
+ wire [1:0] T_11387_io_client_acquire_bits_payload_addr_beat;
+ wire T_11387_io_client_acquire_bits_payload_is_builtin_type;
+ wire [2:0] T_11387_io_client_acquire_bits_payload_a_type;
+ wire [16:0] T_11387_io_client_acquire_bits_payload_union;
+ wire [127:0] T_11387_io_client_acquire_bits_payload_data;
+ wire T_11387_io_client_grant_ready;
+ wire T_11387_io_client_grant_valid;
+ wire [1:0] T_11387_io_client_grant_bits_header_src;
+ wire [1:0] T_11387_io_client_grant_bits_header_dst;
+ wire [1:0] T_11387_io_client_grant_bits_payload_addr_beat;
+ wire [1:0] T_11387_io_client_grant_bits_payload_client_xact_id;
+ wire [3:0] T_11387_io_client_grant_bits_payload_manager_xact_id;
+ wire T_11387_io_client_grant_bits_payload_is_builtin_type;
+ wire [3:0] T_11387_io_client_grant_bits_payload_g_type;
+ wire [127:0] T_11387_io_client_grant_bits_payload_data;
+ wire T_11387_io_client_finish_ready;
+ wire T_11387_io_client_finish_valid;
+ wire [1:0] T_11387_io_client_finish_bits_header_src;
+ wire [1:0] T_11387_io_client_finish_bits_header_dst;
+ wire [3:0] T_11387_io_client_finish_bits_payload_manager_xact_id;
+ wire T_11387_io_client_probe_ready;
+ wire T_11387_io_client_probe_valid;
+ wire [1:0] T_11387_io_client_probe_bits_header_src;
+ wire [1:0] T_11387_io_client_probe_bits_header_dst;
+ wire [25:0] T_11387_io_client_probe_bits_payload_addr_block;
+ wire [1:0] T_11387_io_client_probe_bits_payload_p_type;
+ wire T_11387_io_client_release_ready;
+ wire T_11387_io_client_release_valid;
+ wire [1:0] T_11387_io_client_release_bits_header_src;
+ wire [1:0] T_11387_io_client_release_bits_header_dst;
+ wire [1:0] T_11387_io_client_release_bits_payload_addr_beat;
+ wire [25:0] T_11387_io_client_release_bits_payload_addr_block;
+ wire [1:0] T_11387_io_client_release_bits_payload_client_xact_id;
+ wire T_11387_io_client_release_bits_payload_voluntary;
+ wire [2:0] T_11387_io_client_release_bits_payload_r_type;
+ wire [127:0] T_11387_io_client_release_bits_payload_data;
+ wire T_11387_io_manager_acquire_ready;
+ wire T_11387_io_manager_acquire_valid;
+ wire [1:0] T_11387_io_manager_acquire_bits_header_src;
+ wire [1:0] T_11387_io_manager_acquire_bits_header_dst;
+ wire [25:0] T_11387_io_manager_acquire_bits_payload_addr_block;
+ wire [1:0] T_11387_io_manager_acquire_bits_payload_client_xact_id;
+ wire [1:0] T_11387_io_manager_acquire_bits_payload_addr_beat;
+ wire T_11387_io_manager_acquire_bits_payload_is_builtin_type;
+ wire [2:0] T_11387_io_manager_acquire_bits_payload_a_type;
+ wire [16:0] T_11387_io_manager_acquire_bits_payload_union;
+ wire [127:0] T_11387_io_manager_acquire_bits_payload_data;
+ wire T_11387_io_manager_grant_ready;
+ wire T_11387_io_manager_grant_valid;
+ wire [1:0] T_11387_io_manager_grant_bits_header_src;
+ wire [1:0] T_11387_io_manager_grant_bits_header_dst;
+ wire [1:0] T_11387_io_manager_grant_bits_payload_addr_beat;
+ wire [1:0] T_11387_io_manager_grant_bits_payload_client_xact_id;
+ wire [3:0] T_11387_io_manager_grant_bits_payload_manager_xact_id;
+ wire T_11387_io_manager_grant_bits_payload_is_builtin_type;
+ wire [3:0] T_11387_io_manager_grant_bits_payload_g_type;
+ wire [127:0] T_11387_io_manager_grant_bits_payload_data;
+ wire T_11387_io_manager_finish_ready;
+ wire T_11387_io_manager_finish_valid;
+ wire [1:0] T_11387_io_manager_finish_bits_header_src;
+ wire [1:0] T_11387_io_manager_finish_bits_header_dst;
+ wire [3:0] T_11387_io_manager_finish_bits_payload_manager_xact_id;
+ wire T_11387_io_manager_probe_ready;
+ wire T_11387_io_manager_probe_valid;
+ wire [1:0] T_11387_io_manager_probe_bits_header_src;
+ wire [1:0] T_11387_io_manager_probe_bits_header_dst;
+ wire [25:0] T_11387_io_manager_probe_bits_payload_addr_block;
+ wire [1:0] T_11387_io_manager_probe_bits_payload_p_type;
+ wire T_11387_io_manager_release_ready;
+ wire T_11387_io_manager_release_valid;
+ wire [1:0] T_11387_io_manager_release_bits_header_src;
+ wire [1:0] T_11387_io_manager_release_bits_header_dst;
+ wire [1:0] T_11387_io_manager_release_bits_payload_addr_beat;
+ wire [25:0] T_11387_io_manager_release_bits_payload_addr_block;
+ wire [1:0] T_11387_io_manager_release_bits_payload_client_xact_id;
+ wire T_11387_io_manager_release_bits_payload_voluntary;
+ wire [2:0] T_11387_io_manager_release_bits_payload_r_type;
+ wire [127:0] T_11387_io_manager_release_bits_payload_data;
+ wire T_11388_clk;
+ wire T_11388_reset;
+ wire T_11388_io_client_acquire_ready;
+ wire T_11388_io_client_acquire_valid;
+ wire [25:0] T_11388_io_client_acquire_bits_addr_block;
+ wire [1:0] T_11388_io_client_acquire_bits_client_xact_id;
+ wire [1:0] T_11388_io_client_acquire_bits_addr_beat;
+ wire T_11388_io_client_acquire_bits_is_builtin_type;
+ wire [2:0] T_11388_io_client_acquire_bits_a_type;
+ wire [16:0] T_11388_io_client_acquire_bits_union;
+ wire [127:0] T_11388_io_client_acquire_bits_data;
+ wire T_11388_io_client_grant_ready;
+ wire T_11388_io_client_grant_valid;
+ wire [1:0] T_11388_io_client_grant_bits_addr_beat;
+ wire [1:0] T_11388_io_client_grant_bits_client_xact_id;
+ wire [3:0] T_11388_io_client_grant_bits_manager_xact_id;
+ wire T_11388_io_client_grant_bits_is_builtin_type;
+ wire [3:0] T_11388_io_client_grant_bits_g_type;
+ wire [127:0] T_11388_io_client_grant_bits_data;
+ wire T_11388_io_client_probe_ready;
+ wire T_11388_io_client_probe_valid;
+ wire [25:0] T_11388_io_client_probe_bits_addr_block;
+ wire [1:0] T_11388_io_client_probe_bits_p_type;
+ wire T_11388_io_client_release_ready;
+ wire T_11388_io_client_release_valid;
+ wire [1:0] T_11388_io_client_release_bits_addr_beat;
+ wire [25:0] T_11388_io_client_release_bits_addr_block;
+ wire [1:0] T_11388_io_client_release_bits_client_xact_id;
+ wire T_11388_io_client_release_bits_voluntary;
+ wire [2:0] T_11388_io_client_release_bits_r_type;
+ wire [127:0] T_11388_io_client_release_bits_data;
+ wire T_11388_io_network_acquire_ready;
+ wire T_11388_io_network_acquire_valid;
+ wire [1:0] T_11388_io_network_acquire_bits_header_src;
+ wire [1:0] T_11388_io_network_acquire_bits_header_dst;
+ wire [25:0] T_11388_io_network_acquire_bits_payload_addr_block;
+ wire [1:0] T_11388_io_network_acquire_bits_payload_client_xact_id;
+ wire [1:0] T_11388_io_network_acquire_bits_payload_addr_beat;
+ wire T_11388_io_network_acquire_bits_payload_is_builtin_type;
+ wire [2:0] T_11388_io_network_acquire_bits_payload_a_type;
+ wire [16:0] T_11388_io_network_acquire_bits_payload_union;
+ wire [127:0] T_11388_io_network_acquire_bits_payload_data;
+ wire T_11388_io_network_grant_ready;
+ wire T_11388_io_network_grant_valid;
+ wire [1:0] T_11388_io_network_grant_bits_header_src;
+ wire [1:0] T_11388_io_network_grant_bits_header_dst;
+ wire [1:0] T_11388_io_network_grant_bits_payload_addr_beat;
+ wire [1:0] T_11388_io_network_grant_bits_payload_client_xact_id;
+ wire [3:0] T_11388_io_network_grant_bits_payload_manager_xact_id;
+ wire T_11388_io_network_grant_bits_payload_is_builtin_type;
+ wire [3:0] T_11388_io_network_grant_bits_payload_g_type;
+ wire [127:0] T_11388_io_network_grant_bits_payload_data;
+ wire T_11388_io_network_finish_ready;
+ wire T_11388_io_network_finish_valid;
+ wire [1:0] T_11388_io_network_finish_bits_header_src;
+ wire [1:0] T_11388_io_network_finish_bits_header_dst;
+ wire [3:0] T_11388_io_network_finish_bits_payload_manager_xact_id;
+ wire T_11388_io_network_probe_ready;
+ wire T_11388_io_network_probe_valid;
+ wire [1:0] T_11388_io_network_probe_bits_header_src;
+ wire [1:0] T_11388_io_network_probe_bits_header_dst;
+ wire [25:0] T_11388_io_network_probe_bits_payload_addr_block;
+ wire [1:0] T_11388_io_network_probe_bits_payload_p_type;
+ wire T_11388_io_network_release_ready;
+ wire T_11388_io_network_release_valid;
+ wire [1:0] T_11388_io_network_release_bits_header_src;
+ wire [1:0] T_11388_io_network_release_bits_header_dst;
+ wire [1:0] T_11388_io_network_release_bits_payload_addr_beat;
+ wire [25:0] T_11388_io_network_release_bits_payload_addr_block;
+ wire [1:0] T_11388_io_network_release_bits_payload_client_xact_id;
+ wire T_11388_io_network_release_bits_payload_voluntary;
+ wire [2:0] T_11388_io_network_release_bits_payload_r_type;
+ wire [127:0] T_11388_io_network_release_bits_payload_data;
+ wire T_11389_clk;
+ wire T_11389_reset;
+ wire T_11389_io_client_acquire_ready;
+ wire T_11389_io_client_acquire_valid;
+ wire [1:0] T_11389_io_client_acquire_bits_header_src;
+ wire [1:0] T_11389_io_client_acquire_bits_header_dst;
+ wire [25:0] T_11389_io_client_acquire_bits_payload_addr_block;
+ wire [1:0] T_11389_io_client_acquire_bits_payload_client_xact_id;
+ wire [1:0] T_11389_io_client_acquire_bits_payload_addr_beat;
+ wire T_11389_io_client_acquire_bits_payload_is_builtin_type;
+ wire [2:0] T_11389_io_client_acquire_bits_payload_a_type;
+ wire [16:0] T_11389_io_client_acquire_bits_payload_union;
+ wire [127:0] T_11389_io_client_acquire_bits_payload_data;
+ wire T_11389_io_client_grant_ready;
+ wire T_11389_io_client_grant_valid;
+ wire [1:0] T_11389_io_client_grant_bits_header_src;
+ wire [1:0] T_11389_io_client_grant_bits_header_dst;
+ wire [1:0] T_11389_io_client_grant_bits_payload_addr_beat;
+ wire [1:0] T_11389_io_client_grant_bits_payload_client_xact_id;
+ wire [3:0] T_11389_io_client_grant_bits_payload_manager_xact_id;
+ wire T_11389_io_client_grant_bits_payload_is_builtin_type;
+ wire [3:0] T_11389_io_client_grant_bits_payload_g_type;
+ wire [127:0] T_11389_io_client_grant_bits_payload_data;
+ wire T_11389_io_client_finish_ready;
+ wire T_11389_io_client_finish_valid;
+ wire [1:0] T_11389_io_client_finish_bits_header_src;
+ wire [1:0] T_11389_io_client_finish_bits_header_dst;
+ wire [3:0] T_11389_io_client_finish_bits_payload_manager_xact_id;
+ wire T_11389_io_client_probe_ready;
+ wire T_11389_io_client_probe_valid;
+ wire [1:0] T_11389_io_client_probe_bits_header_src;
+ wire [1:0] T_11389_io_client_probe_bits_header_dst;
+ wire [25:0] T_11389_io_client_probe_bits_payload_addr_block;
+ wire [1:0] T_11389_io_client_probe_bits_payload_p_type;
+ wire T_11389_io_client_release_ready;
+ wire T_11389_io_client_release_valid;
+ wire [1:0] T_11389_io_client_release_bits_header_src;
+ wire [1:0] T_11389_io_client_release_bits_header_dst;
+ wire [1:0] T_11389_io_client_release_bits_payload_addr_beat;
+ wire [25:0] T_11389_io_client_release_bits_payload_addr_block;
+ wire [1:0] T_11389_io_client_release_bits_payload_client_xact_id;
+ wire T_11389_io_client_release_bits_payload_voluntary;
+ wire [2:0] T_11389_io_client_release_bits_payload_r_type;
+ wire [127:0] T_11389_io_client_release_bits_payload_data;
+ wire T_11389_io_manager_acquire_ready;
+ wire T_11389_io_manager_acquire_valid;
+ wire [1:0] T_11389_io_manager_acquire_bits_header_src;
+ wire [1:0] T_11389_io_manager_acquire_bits_header_dst;
+ wire [25:0] T_11389_io_manager_acquire_bits_payload_addr_block;
+ wire [1:0] T_11389_io_manager_acquire_bits_payload_client_xact_id;
+ wire [1:0] T_11389_io_manager_acquire_bits_payload_addr_beat;
+ wire T_11389_io_manager_acquire_bits_payload_is_builtin_type;
+ wire [2:0] T_11389_io_manager_acquire_bits_payload_a_type;
+ wire [16:0] T_11389_io_manager_acquire_bits_payload_union;
+ wire [127:0] T_11389_io_manager_acquire_bits_payload_data;
+ wire T_11389_io_manager_grant_ready;
+ wire T_11389_io_manager_grant_valid;
+ wire [1:0] T_11389_io_manager_grant_bits_header_src;
+ wire [1:0] T_11389_io_manager_grant_bits_header_dst;
+ wire [1:0] T_11389_io_manager_grant_bits_payload_addr_beat;
+ wire [1:0] T_11389_io_manager_grant_bits_payload_client_xact_id;
+ wire [3:0] T_11389_io_manager_grant_bits_payload_manager_xact_id;
+ wire T_11389_io_manager_grant_bits_payload_is_builtin_type;
+ wire [3:0] T_11389_io_manager_grant_bits_payload_g_type;
+ wire [127:0] T_11389_io_manager_grant_bits_payload_data;
+ wire T_11389_io_manager_finish_ready;
+ wire T_11389_io_manager_finish_valid;
+ wire [1:0] T_11389_io_manager_finish_bits_header_src;
+ wire [1:0] T_11389_io_manager_finish_bits_header_dst;
+ wire [3:0] T_11389_io_manager_finish_bits_payload_manager_xact_id;
+ wire T_11389_io_manager_probe_ready;
+ wire T_11389_io_manager_probe_valid;
+ wire [1:0] T_11389_io_manager_probe_bits_header_src;
+ wire [1:0] T_11389_io_manager_probe_bits_header_dst;
+ wire [25:0] T_11389_io_manager_probe_bits_payload_addr_block;
+ wire [1:0] T_11389_io_manager_probe_bits_payload_p_type;
+ wire T_11389_io_manager_release_ready;
+ wire T_11389_io_manager_release_valid;
+ wire [1:0] T_11389_io_manager_release_bits_header_src;
+ wire [1:0] T_11389_io_manager_release_bits_header_dst;
+ wire [1:0] T_11389_io_manager_release_bits_payload_addr_beat;
+ wire [25:0] T_11389_io_manager_release_bits_payload_addr_block;
+ wire [1:0] T_11389_io_manager_release_bits_payload_client_xact_id;
+ wire T_11389_io_manager_release_bits_payload_voluntary;
+ wire [2:0] T_11389_io_manager_release_bits_payload_r_type;
+ wire [127:0] T_11389_io_manager_release_bits_payload_data;
+ wire T_11390_clk;
+ wire T_11390_reset;
+ wire T_11390_io_client_acquire_ready;
+ wire T_11390_io_client_acquire_valid;
+ wire [25:0] T_11390_io_client_acquire_bits_addr_block;
+ wire [1:0] T_11390_io_client_acquire_bits_client_xact_id;
+ wire [1:0] T_11390_io_client_acquire_bits_addr_beat;
+ wire T_11390_io_client_acquire_bits_is_builtin_type;
+ wire [2:0] T_11390_io_client_acquire_bits_a_type;
+ wire [16:0] T_11390_io_client_acquire_bits_union;
+ wire [127:0] T_11390_io_client_acquire_bits_data;
+ wire T_11390_io_client_grant_ready;
+ wire T_11390_io_client_grant_valid;
+ wire [1:0] T_11390_io_client_grant_bits_addr_beat;
+ wire [1:0] T_11390_io_client_grant_bits_client_xact_id;
+ wire [3:0] T_11390_io_client_grant_bits_manager_xact_id;
+ wire T_11390_io_client_grant_bits_is_builtin_type;
+ wire [3:0] T_11390_io_client_grant_bits_g_type;
+ wire [127:0] T_11390_io_client_grant_bits_data;
+ wire T_11390_io_client_probe_ready;
+ wire T_11390_io_client_probe_valid;
+ wire [25:0] T_11390_io_client_probe_bits_addr_block;
+ wire [1:0] T_11390_io_client_probe_bits_p_type;
+ wire T_11390_io_client_release_ready;
+ wire T_11390_io_client_release_valid;
+ wire [1:0] T_11390_io_client_release_bits_addr_beat;
+ wire [25:0] T_11390_io_client_release_bits_addr_block;
+ wire [1:0] T_11390_io_client_release_bits_client_xact_id;
+ wire T_11390_io_client_release_bits_voluntary;
+ wire [2:0] T_11390_io_client_release_bits_r_type;
+ wire [127:0] T_11390_io_client_release_bits_data;
+ wire T_11390_io_network_acquire_ready;
+ wire T_11390_io_network_acquire_valid;
+ wire [1:0] T_11390_io_network_acquire_bits_header_src;
+ wire [1:0] T_11390_io_network_acquire_bits_header_dst;
+ wire [25:0] T_11390_io_network_acquire_bits_payload_addr_block;
+ wire [1:0] T_11390_io_network_acquire_bits_payload_client_xact_id;
+ wire [1:0] T_11390_io_network_acquire_bits_payload_addr_beat;
+ wire T_11390_io_network_acquire_bits_payload_is_builtin_type;
+ wire [2:0] T_11390_io_network_acquire_bits_payload_a_type;
+ wire [16:0] T_11390_io_network_acquire_bits_payload_union;
+ wire [127:0] T_11390_io_network_acquire_bits_payload_data;
+ wire T_11390_io_network_grant_ready;
+ wire T_11390_io_network_grant_valid;
+ wire [1:0] T_11390_io_network_grant_bits_header_src;
+ wire [1:0] T_11390_io_network_grant_bits_header_dst;
+ wire [1:0] T_11390_io_network_grant_bits_payload_addr_beat;
+ wire [1:0] T_11390_io_network_grant_bits_payload_client_xact_id;
+ wire [3:0] T_11390_io_network_grant_bits_payload_manager_xact_id;
+ wire T_11390_io_network_grant_bits_payload_is_builtin_type;
+ wire [3:0] T_11390_io_network_grant_bits_payload_g_type;
+ wire [127:0] T_11390_io_network_grant_bits_payload_data;
+ wire T_11390_io_network_finish_ready;
+ wire T_11390_io_network_finish_valid;
+ wire [1:0] T_11390_io_network_finish_bits_header_src;
+ wire [1:0] T_11390_io_network_finish_bits_header_dst;
+ wire [3:0] T_11390_io_network_finish_bits_payload_manager_xact_id;
+ wire T_11390_io_network_probe_ready;
+ wire T_11390_io_network_probe_valid;
+ wire [1:0] T_11390_io_network_probe_bits_header_src;
+ wire [1:0] T_11390_io_network_probe_bits_header_dst;
+ wire [25:0] T_11390_io_network_probe_bits_payload_addr_block;
+ wire [1:0] T_11390_io_network_probe_bits_payload_p_type;
+ wire T_11390_io_network_release_ready;
+ wire T_11390_io_network_release_valid;
+ wire [1:0] T_11390_io_network_release_bits_header_src;
+ wire [1:0] T_11390_io_network_release_bits_header_dst;
+ wire [1:0] T_11390_io_network_release_bits_payload_addr_beat;
+ wire [25:0] T_11390_io_network_release_bits_payload_addr_block;
+ wire [1:0] T_11390_io_network_release_bits_payload_client_xact_id;
+ wire T_11390_io_network_release_bits_payload_voluntary;
+ wire [2:0] T_11390_io_network_release_bits_payload_r_type;
+ wire [127:0] T_11390_io_network_release_bits_payload_data;
+ wire T_11391_clk;
+ wire T_11391_reset;
+ wire T_11391_io_client_acquire_ready;
+ wire T_11391_io_client_acquire_valid;
+ wire [1:0] T_11391_io_client_acquire_bits_header_src;
+ wire [1:0] T_11391_io_client_acquire_bits_header_dst;
+ wire [25:0] T_11391_io_client_acquire_bits_payload_addr_block;
+ wire [1:0] T_11391_io_client_acquire_bits_payload_client_xact_id;
+ wire [1:0] T_11391_io_client_acquire_bits_payload_addr_beat;
+ wire T_11391_io_client_acquire_bits_payload_is_builtin_type;
+ wire [2:0] T_11391_io_client_acquire_bits_payload_a_type;
+ wire [16:0] T_11391_io_client_acquire_bits_payload_union;
+ wire [127:0] T_11391_io_client_acquire_bits_payload_data;
+ wire T_11391_io_client_grant_ready;
+ wire T_11391_io_client_grant_valid;
+ wire [1:0] T_11391_io_client_grant_bits_header_src;
+ wire [1:0] T_11391_io_client_grant_bits_header_dst;
+ wire [1:0] T_11391_io_client_grant_bits_payload_addr_beat;
+ wire [1:0] T_11391_io_client_grant_bits_payload_client_xact_id;
+ wire [3:0] T_11391_io_client_grant_bits_payload_manager_xact_id;
+ wire T_11391_io_client_grant_bits_payload_is_builtin_type;
+ wire [3:0] T_11391_io_client_grant_bits_payload_g_type;
+ wire [127:0] T_11391_io_client_grant_bits_payload_data;
+ wire T_11391_io_client_finish_ready;
+ wire T_11391_io_client_finish_valid;
+ wire [1:0] T_11391_io_client_finish_bits_header_src;
+ wire [1:0] T_11391_io_client_finish_bits_header_dst;
+ wire [3:0] T_11391_io_client_finish_bits_payload_manager_xact_id;
+ wire T_11391_io_client_probe_ready;
+ wire T_11391_io_client_probe_valid;
+ wire [1:0] T_11391_io_client_probe_bits_header_src;
+ wire [1:0] T_11391_io_client_probe_bits_header_dst;
+ wire [25:0] T_11391_io_client_probe_bits_payload_addr_block;
+ wire [1:0] T_11391_io_client_probe_bits_payload_p_type;
+ wire T_11391_io_client_release_ready;
+ wire T_11391_io_client_release_valid;
+ wire [1:0] T_11391_io_client_release_bits_header_src;
+ wire [1:0] T_11391_io_client_release_bits_header_dst;
+ wire [1:0] T_11391_io_client_release_bits_payload_addr_beat;
+ wire [25:0] T_11391_io_client_release_bits_payload_addr_block;
+ wire [1:0] T_11391_io_client_release_bits_payload_client_xact_id;
+ wire T_11391_io_client_release_bits_payload_voluntary;
+ wire [2:0] T_11391_io_client_release_bits_payload_r_type;
+ wire [127:0] T_11391_io_client_release_bits_payload_data;
+ wire T_11391_io_manager_acquire_ready;
+ wire T_11391_io_manager_acquire_valid;
+ wire [1:0] T_11391_io_manager_acquire_bits_header_src;
+ wire [1:0] T_11391_io_manager_acquire_bits_header_dst;
+ wire [25:0] T_11391_io_manager_acquire_bits_payload_addr_block;
+ wire [1:0] T_11391_io_manager_acquire_bits_payload_client_xact_id;
+ wire [1:0] T_11391_io_manager_acquire_bits_payload_addr_beat;
+ wire T_11391_io_manager_acquire_bits_payload_is_builtin_type;
+ wire [2:0] T_11391_io_manager_acquire_bits_payload_a_type;
+ wire [16:0] T_11391_io_manager_acquire_bits_payload_union;
+ wire [127:0] T_11391_io_manager_acquire_bits_payload_data;
+ wire T_11391_io_manager_grant_ready;
+ wire T_11391_io_manager_grant_valid;
+ wire [1:0] T_11391_io_manager_grant_bits_header_src;
+ wire [1:0] T_11391_io_manager_grant_bits_header_dst;
+ wire [1:0] T_11391_io_manager_grant_bits_payload_addr_beat;
+ wire [1:0] T_11391_io_manager_grant_bits_payload_client_xact_id;
+ wire [3:0] T_11391_io_manager_grant_bits_payload_manager_xact_id;
+ wire T_11391_io_manager_grant_bits_payload_is_builtin_type;
+ wire [3:0] T_11391_io_manager_grant_bits_payload_g_type;
+ wire [127:0] T_11391_io_manager_grant_bits_payload_data;
+ wire T_11391_io_manager_finish_ready;
+ wire T_11391_io_manager_finish_valid;
+ wire [1:0] T_11391_io_manager_finish_bits_header_src;
+ wire [1:0] T_11391_io_manager_finish_bits_header_dst;
+ wire [3:0] T_11391_io_manager_finish_bits_payload_manager_xact_id;
+ wire T_11391_io_manager_probe_ready;
+ wire T_11391_io_manager_probe_valid;
+ wire [1:0] T_11391_io_manager_probe_bits_header_src;
+ wire [1:0] T_11391_io_manager_probe_bits_header_dst;
+ wire [25:0] T_11391_io_manager_probe_bits_payload_addr_block;
+ wire [1:0] T_11391_io_manager_probe_bits_payload_p_type;
+ wire T_11391_io_manager_release_ready;
+ wire T_11391_io_manager_release_valid;
+ wire [1:0] T_11391_io_manager_release_bits_header_src;
+ wire [1:0] T_11391_io_manager_release_bits_header_dst;
+ wire [1:0] T_11391_io_manager_release_bits_payload_addr_beat;
+ wire [25:0] T_11391_io_manager_release_bits_payload_addr_block;
+ wire [1:0] T_11391_io_manager_release_bits_payload_client_xact_id;
+ wire T_11391_io_manager_release_bits_payload_voluntary;
+ wire [2:0] T_11391_io_manager_release_bits_payload_r_type;
+ wire [127:0] T_11391_io_manager_release_bits_payload_data;
+ wire T_11392_clk;
+ wire T_11392_reset;
+ wire T_11392_io_manager_acquire_ready;
+ wire T_11392_io_manager_acquire_valid;
+ wire [25:0] T_11392_io_manager_acquire_bits_addr_block;
+ wire [1:0] T_11392_io_manager_acquire_bits_client_xact_id;
+ wire [1:0] T_11392_io_manager_acquire_bits_addr_beat;
+ wire T_11392_io_manager_acquire_bits_is_builtin_type;
+ wire [2:0] T_11392_io_manager_acquire_bits_a_type;
+ wire [16:0] T_11392_io_manager_acquire_bits_union;
+ wire [127:0] T_11392_io_manager_acquire_bits_data;
+ wire [1:0] T_11392_io_manager_acquire_bits_client_id;
+ wire T_11392_io_manager_grant_ready;
+ wire T_11392_io_manager_grant_valid;
+ wire [1:0] T_11392_io_manager_grant_bits_addr_beat;
+ wire [1:0] T_11392_io_manager_grant_bits_client_xact_id;
+ wire [3:0] T_11392_io_manager_grant_bits_manager_xact_id;
+ wire T_11392_io_manager_grant_bits_is_builtin_type;
+ wire [3:0] T_11392_io_manager_grant_bits_g_type;
+ wire [127:0] T_11392_io_manager_grant_bits_data;
+ wire [1:0] T_11392_io_manager_grant_bits_client_id;
+ wire T_11392_io_manager_finish_ready;
+ wire T_11392_io_manager_finish_valid;
+ wire [3:0] T_11392_io_manager_finish_bits_manager_xact_id;
+ wire T_11392_io_manager_probe_ready;
+ wire T_11392_io_manager_probe_valid;
+ wire [25:0] T_11392_io_manager_probe_bits_addr_block;
+ wire [1:0] T_11392_io_manager_probe_bits_p_type;
+ wire [1:0] T_11392_io_manager_probe_bits_client_id;
+ wire T_11392_io_manager_release_ready;
+ wire T_11392_io_manager_release_valid;
+ wire [1:0] T_11392_io_manager_release_bits_addr_beat;
+ wire [25:0] T_11392_io_manager_release_bits_addr_block;
+ wire [1:0] T_11392_io_manager_release_bits_client_xact_id;
+ wire T_11392_io_manager_release_bits_voluntary;
+ wire [2:0] T_11392_io_manager_release_bits_r_type;
+ wire [127:0] T_11392_io_manager_release_bits_data;
+ wire [1:0] T_11392_io_manager_release_bits_client_id;
+ wire T_11392_io_network_acquire_ready;
+ wire T_11392_io_network_acquire_valid;
+ wire [1:0] T_11392_io_network_acquire_bits_header_src;
+ wire [1:0] T_11392_io_network_acquire_bits_header_dst;
+ wire [25:0] T_11392_io_network_acquire_bits_payload_addr_block;
+ wire [1:0] T_11392_io_network_acquire_bits_payload_client_xact_id;
+ wire [1:0] T_11392_io_network_acquire_bits_payload_addr_beat;
+ wire T_11392_io_network_acquire_bits_payload_is_builtin_type;
+ wire [2:0] T_11392_io_network_acquire_bits_payload_a_type;
+ wire [16:0] T_11392_io_network_acquire_bits_payload_union;
+ wire [127:0] T_11392_io_network_acquire_bits_payload_data;
+ wire T_11392_io_network_grant_ready;
+ wire T_11392_io_network_grant_valid;
+ wire [1:0] T_11392_io_network_grant_bits_header_src;
+ wire [1:0] T_11392_io_network_grant_bits_header_dst;
+ wire [1:0] T_11392_io_network_grant_bits_payload_addr_beat;
+ wire [1:0] T_11392_io_network_grant_bits_payload_client_xact_id;
+ wire [3:0] T_11392_io_network_grant_bits_payload_manager_xact_id;
+ wire T_11392_io_network_grant_bits_payload_is_builtin_type;
+ wire [3:0] T_11392_io_network_grant_bits_payload_g_type;
+ wire [127:0] T_11392_io_network_grant_bits_payload_data;
+ wire T_11392_io_network_finish_ready;
+ wire T_11392_io_network_finish_valid;
+ wire [1:0] T_11392_io_network_finish_bits_header_src;
+ wire [1:0] T_11392_io_network_finish_bits_header_dst;
+ wire [3:0] T_11392_io_network_finish_bits_payload_manager_xact_id;
+ wire T_11392_io_network_probe_ready;
+ wire T_11392_io_network_probe_valid;
+ wire [1:0] T_11392_io_network_probe_bits_header_src;
+ wire [1:0] T_11392_io_network_probe_bits_header_dst;
+ wire [25:0] T_11392_io_network_probe_bits_payload_addr_block;
+ wire [1:0] T_11392_io_network_probe_bits_payload_p_type;
+ wire T_11392_io_network_release_ready;
+ wire T_11392_io_network_release_valid;
+ wire [1:0] T_11392_io_network_release_bits_header_src;
+ wire [1:0] T_11392_io_network_release_bits_header_dst;
+ wire [1:0] T_11392_io_network_release_bits_payload_addr_beat;
+ wire [25:0] T_11392_io_network_release_bits_payload_addr_block;
+ wire [1:0] T_11392_io_network_release_bits_payload_client_xact_id;
+ wire T_11392_io_network_release_bits_payload_voluntary;
+ wire [2:0] T_11392_io_network_release_bits_payload_r_type;
+ wire [127:0] T_11392_io_network_release_bits_payload_data;
+ wire T_11393_clk;
+ wire T_11393_reset;
+ wire T_11393_io_client_acquire_ready;
+ wire T_11393_io_client_acquire_valid;
+ wire [1:0] T_11393_io_client_acquire_bits_header_src;
+ wire [1:0] T_11393_io_client_acquire_bits_header_dst;
+ wire [25:0] T_11393_io_client_acquire_bits_payload_addr_block;
+ wire [1:0] T_11393_io_client_acquire_bits_payload_client_xact_id;
+ wire [1:0] T_11393_io_client_acquire_bits_payload_addr_beat;
+ wire T_11393_io_client_acquire_bits_payload_is_builtin_type;
+ wire [2:0] T_11393_io_client_acquire_bits_payload_a_type;
+ wire [16:0] T_11393_io_client_acquire_bits_payload_union;
+ wire [127:0] T_11393_io_client_acquire_bits_payload_data;
+ wire T_11393_io_client_grant_ready;
+ wire T_11393_io_client_grant_valid;
+ wire [1:0] T_11393_io_client_grant_bits_header_src;
+ wire [1:0] T_11393_io_client_grant_bits_header_dst;
+ wire [1:0] T_11393_io_client_grant_bits_payload_addr_beat;
+ wire [1:0] T_11393_io_client_grant_bits_payload_client_xact_id;
+ wire [3:0] T_11393_io_client_grant_bits_payload_manager_xact_id;
+ wire T_11393_io_client_grant_bits_payload_is_builtin_type;
+ wire [3:0] T_11393_io_client_grant_bits_payload_g_type;
+ wire [127:0] T_11393_io_client_grant_bits_payload_data;
+ wire T_11393_io_client_finish_ready;
+ wire T_11393_io_client_finish_valid;
+ wire [1:0] T_11393_io_client_finish_bits_header_src;
+ wire [1:0] T_11393_io_client_finish_bits_header_dst;
+ wire [3:0] T_11393_io_client_finish_bits_payload_manager_xact_id;
+ wire T_11393_io_client_probe_ready;
+ wire T_11393_io_client_probe_valid;
+ wire [1:0] T_11393_io_client_probe_bits_header_src;
+ wire [1:0] T_11393_io_client_probe_bits_header_dst;
+ wire [25:0] T_11393_io_client_probe_bits_payload_addr_block;
+ wire [1:0] T_11393_io_client_probe_bits_payload_p_type;
+ wire T_11393_io_client_release_ready;
+ wire T_11393_io_client_release_valid;
+ wire [1:0] T_11393_io_client_release_bits_header_src;
+ wire [1:0] T_11393_io_client_release_bits_header_dst;
+ wire [1:0] T_11393_io_client_release_bits_payload_addr_beat;
+ wire [25:0] T_11393_io_client_release_bits_payload_addr_block;
+ wire [1:0] T_11393_io_client_release_bits_payload_client_xact_id;
+ wire T_11393_io_client_release_bits_payload_voluntary;
+ wire [2:0] T_11393_io_client_release_bits_payload_r_type;
+ wire [127:0] T_11393_io_client_release_bits_payload_data;
+ wire T_11393_io_manager_acquire_ready;
+ wire T_11393_io_manager_acquire_valid;
+ wire [1:0] T_11393_io_manager_acquire_bits_header_src;
+ wire [1:0] T_11393_io_manager_acquire_bits_header_dst;
+ wire [25:0] T_11393_io_manager_acquire_bits_payload_addr_block;
+ wire [1:0] T_11393_io_manager_acquire_bits_payload_client_xact_id;
+ wire [1:0] T_11393_io_manager_acquire_bits_payload_addr_beat;
+ wire T_11393_io_manager_acquire_bits_payload_is_builtin_type;
+ wire [2:0] T_11393_io_manager_acquire_bits_payload_a_type;
+ wire [16:0] T_11393_io_manager_acquire_bits_payload_union;
+ wire [127:0] T_11393_io_manager_acquire_bits_payload_data;
+ wire T_11393_io_manager_grant_ready;
+ wire T_11393_io_manager_grant_valid;
+ wire [1:0] T_11393_io_manager_grant_bits_header_src;
+ wire [1:0] T_11393_io_manager_grant_bits_header_dst;
+ wire [1:0] T_11393_io_manager_grant_bits_payload_addr_beat;
+ wire [1:0] T_11393_io_manager_grant_bits_payload_client_xact_id;
+ wire [3:0] T_11393_io_manager_grant_bits_payload_manager_xact_id;
+ wire T_11393_io_manager_grant_bits_payload_is_builtin_type;
+ wire [3:0] T_11393_io_manager_grant_bits_payload_g_type;
+ wire [127:0] T_11393_io_manager_grant_bits_payload_data;
+ wire T_11393_io_manager_finish_ready;
+ wire T_11393_io_manager_finish_valid;
+ wire [1:0] T_11393_io_manager_finish_bits_header_src;
+ wire [1:0] T_11393_io_manager_finish_bits_header_dst;
+ wire [3:0] T_11393_io_manager_finish_bits_payload_manager_xact_id;
+ wire T_11393_io_manager_probe_ready;
+ wire T_11393_io_manager_probe_valid;
+ wire [1:0] T_11393_io_manager_probe_bits_header_src;
+ wire [1:0] T_11393_io_manager_probe_bits_header_dst;
+ wire [25:0] T_11393_io_manager_probe_bits_payload_addr_block;
+ wire [1:0] T_11393_io_manager_probe_bits_payload_p_type;
+ wire T_11393_io_manager_release_ready;
+ wire T_11393_io_manager_release_valid;
+ wire [1:0] T_11393_io_manager_release_bits_header_src;
+ wire [1:0] T_11393_io_manager_release_bits_header_dst;
+ wire [1:0] T_11393_io_manager_release_bits_payload_addr_beat;
+ wire [25:0] T_11393_io_manager_release_bits_payload_addr_block;
+ wire [1:0] T_11393_io_manager_release_bits_payload_client_xact_id;
+ wire T_11393_io_manager_release_bits_payload_voluntary;
+ wire [2:0] T_11393_io_manager_release_bits_payload_r_type;
+ wire [127:0] T_11393_io_manager_release_bits_payload_data;
+ wire T_11394_clk;
+ wire T_11394_reset;
+ wire T_11394_io_in_0_ready;
+ wire T_11394_io_in_0_valid;
+ wire [1:0] T_11394_io_in_0_bits_header_src;
+ wire [1:0] T_11394_io_in_0_bits_header_dst;
+ wire [25:0] T_11394_io_in_0_bits_payload_addr_block;
+ wire [1:0] T_11394_io_in_0_bits_payload_client_xact_id;
+ wire [1:0] T_11394_io_in_0_bits_payload_addr_beat;
+ wire T_11394_io_in_0_bits_payload_is_builtin_type;
+ wire [2:0] T_11394_io_in_0_bits_payload_a_type;
+ wire [16:0] T_11394_io_in_0_bits_payload_union;
+ wire [127:0] T_11394_io_in_0_bits_payload_data;
+ wire T_11394_io_in_1_ready;
+ wire T_11394_io_in_1_valid;
+ wire [1:0] T_11394_io_in_1_bits_header_src;
+ wire [1:0] T_11394_io_in_1_bits_header_dst;
+ wire [25:0] T_11394_io_in_1_bits_payload_addr_block;
+ wire [1:0] T_11394_io_in_1_bits_payload_client_xact_id;
+ wire [1:0] T_11394_io_in_1_bits_payload_addr_beat;
+ wire T_11394_io_in_1_bits_payload_is_builtin_type;
+ wire [2:0] T_11394_io_in_1_bits_payload_a_type;
+ wire [16:0] T_11394_io_in_1_bits_payload_union;
+ wire [127:0] T_11394_io_in_1_bits_payload_data;
+ wire T_11394_io_in_2_ready;
+ wire T_11394_io_in_2_valid;
+ wire [1:0] T_11394_io_in_2_bits_header_src;
+ wire [1:0] T_11394_io_in_2_bits_header_dst;
+ wire [25:0] T_11394_io_in_2_bits_payload_addr_block;
+ wire [1:0] T_11394_io_in_2_bits_payload_client_xact_id;
+ wire [1:0] T_11394_io_in_2_bits_payload_addr_beat;
+ wire T_11394_io_in_2_bits_payload_is_builtin_type;
+ wire [2:0] T_11394_io_in_2_bits_payload_a_type;
+ wire [16:0] T_11394_io_in_2_bits_payload_union;
+ wire [127:0] T_11394_io_in_2_bits_payload_data;
+ wire T_11394_io_out_ready;
+ wire T_11394_io_out_valid;
+ wire [1:0] T_11394_io_out_bits_header_src;
+ wire [1:0] T_11394_io_out_bits_header_dst;
+ wire [25:0] T_11394_io_out_bits_payload_addr_block;
+ wire [1:0] T_11394_io_out_bits_payload_client_xact_id;
+ wire [1:0] T_11394_io_out_bits_payload_addr_beat;
+ wire T_11394_io_out_bits_payload_is_builtin_type;
+ wire [2:0] T_11394_io_out_bits_payload_a_type;
+ wire [16:0] T_11394_io_out_bits_payload_union;
+ wire [127:0] T_11394_io_out_bits_payload_data;
+ wire [1:0] T_11394_io_chosen;
+ wire T_11395_clk;
+ wire T_11395_reset;
+ wire T_11395_io_in_0_ready;
+ wire T_11395_io_in_0_valid;
+ wire [1:0] T_11395_io_in_0_bits_header_src;
+ wire [1:0] T_11395_io_in_0_bits_header_dst;
+ wire [1:0] T_11395_io_in_0_bits_payload_addr_beat;
+ wire [25:0] T_11395_io_in_0_bits_payload_addr_block;
+ wire [1:0] T_11395_io_in_0_bits_payload_client_xact_id;
+ wire T_11395_io_in_0_bits_payload_voluntary;
+ wire [2:0] T_11395_io_in_0_bits_payload_r_type;
+ wire [127:0] T_11395_io_in_0_bits_payload_data;
+ wire T_11395_io_in_1_ready;
+ wire T_11395_io_in_1_valid;
+ wire [1:0] T_11395_io_in_1_bits_header_src;
+ wire [1:0] T_11395_io_in_1_bits_header_dst;
+ wire [1:0] T_11395_io_in_1_bits_payload_addr_beat;
+ wire [25:0] T_11395_io_in_1_bits_payload_addr_block;
+ wire [1:0] T_11395_io_in_1_bits_payload_client_xact_id;
+ wire T_11395_io_in_1_bits_payload_voluntary;
+ wire [2:0] T_11395_io_in_1_bits_payload_r_type;
+ wire [127:0] T_11395_io_in_1_bits_payload_data;
+ wire T_11395_io_in_2_ready;
+ wire T_11395_io_in_2_valid;
+ wire [1:0] T_11395_io_in_2_bits_header_src;
+ wire [1:0] T_11395_io_in_2_bits_header_dst;
+ wire [1:0] T_11395_io_in_2_bits_payload_addr_beat;
+ wire [25:0] T_11395_io_in_2_bits_payload_addr_block;
+ wire [1:0] T_11395_io_in_2_bits_payload_client_xact_id;
+ wire T_11395_io_in_2_bits_payload_voluntary;
+ wire [2:0] T_11395_io_in_2_bits_payload_r_type;
+ wire [127:0] T_11395_io_in_2_bits_payload_data;
+ wire T_11395_io_out_ready;
+ wire T_11395_io_out_valid;
+ wire [1:0] T_11395_io_out_bits_header_src;
+ wire [1:0] T_11395_io_out_bits_header_dst;
+ wire [1:0] T_11395_io_out_bits_payload_addr_beat;
+ wire [25:0] T_11395_io_out_bits_payload_addr_block;
+ wire [1:0] T_11395_io_out_bits_payload_client_xact_id;
+ wire T_11395_io_out_bits_payload_voluntary;
+ wire [2:0] T_11395_io_out_bits_payload_r_type;
+ wire [127:0] T_11395_io_out_bits_payload_data;
+ wire [1:0] T_11395_io_chosen;
+ wire T_11396_clk;
+ wire T_11396_reset;
+ wire T_11396_io_in_0_ready;
+ wire T_11396_io_in_0_valid;
+ wire [1:0] T_11396_io_in_0_bits_header_src;
+ wire [1:0] T_11396_io_in_0_bits_header_dst;
+ wire [3:0] T_11396_io_in_0_bits_payload_manager_xact_id;
+ wire T_11396_io_in_1_ready;
+ wire T_11396_io_in_1_valid;
+ wire [1:0] T_11396_io_in_1_bits_header_src;
+ wire [1:0] T_11396_io_in_1_bits_header_dst;
+ wire [3:0] T_11396_io_in_1_bits_payload_manager_xact_id;
+ wire T_11396_io_in_2_ready;
+ wire T_11396_io_in_2_valid;
+ wire [1:0] T_11396_io_in_2_bits_header_src;
+ wire [1:0] T_11396_io_in_2_bits_header_dst;
+ wire [3:0] T_11396_io_in_2_bits_payload_manager_xact_id;
+ wire T_11396_io_out_ready;
+ wire T_11396_io_out_valid;
+ wire [1:0] T_11396_io_out_bits_header_src;
+ wire [1:0] T_11396_io_out_bits_header_dst;
+ wire [3:0] T_11396_io_out_bits_payload_manager_xact_id;
+ wire [1:0] T_11396_io_chosen;
+ wire T_11400;
+ wire T_11403;
+ wire T_11406;
+ wire T_11410;
+ wire T_11413;
+ wire T_11416;
+ ClientTileLinkNetworkPort T_11386 (
+ .clk(T_11386_clk),
+ .reset(T_11386_reset),
+ .io_client_acquire_ready(T_11386_io_client_acquire_ready),
+ .io_client_acquire_valid(T_11386_io_client_acquire_valid),
+ .io_client_acquire_bits_addr_block(T_11386_io_client_acquire_bits_addr_block),
+ .io_client_acquire_bits_client_xact_id(T_11386_io_client_acquire_bits_client_xact_id),
+ .io_client_acquire_bits_addr_beat(T_11386_io_client_acquire_bits_addr_beat),
+ .io_client_acquire_bits_is_builtin_type(T_11386_io_client_acquire_bits_is_builtin_type),
+ .io_client_acquire_bits_a_type(T_11386_io_client_acquire_bits_a_type),
+ .io_client_acquire_bits_union(T_11386_io_client_acquire_bits_union),
+ .io_client_acquire_bits_data(T_11386_io_client_acquire_bits_data),
+ .io_client_grant_ready(T_11386_io_client_grant_ready),
+ .io_client_grant_valid(T_11386_io_client_grant_valid),
+ .io_client_grant_bits_addr_beat(T_11386_io_client_grant_bits_addr_beat),
+ .io_client_grant_bits_client_xact_id(T_11386_io_client_grant_bits_client_xact_id),
+ .io_client_grant_bits_manager_xact_id(T_11386_io_client_grant_bits_manager_xact_id),
+ .io_client_grant_bits_is_builtin_type(T_11386_io_client_grant_bits_is_builtin_type),
+ .io_client_grant_bits_g_type(T_11386_io_client_grant_bits_g_type),
+ .io_client_grant_bits_data(T_11386_io_client_grant_bits_data),
+ .io_client_probe_ready(T_11386_io_client_probe_ready),
+ .io_client_probe_valid(T_11386_io_client_probe_valid),
+ .io_client_probe_bits_addr_block(T_11386_io_client_probe_bits_addr_block),
+ .io_client_probe_bits_p_type(T_11386_io_client_probe_bits_p_type),
+ .io_client_release_ready(T_11386_io_client_release_ready),
+ .io_client_release_valid(T_11386_io_client_release_valid),
+ .io_client_release_bits_addr_beat(T_11386_io_client_release_bits_addr_beat),
+ .io_client_release_bits_addr_block(T_11386_io_client_release_bits_addr_block),
+ .io_client_release_bits_client_xact_id(T_11386_io_client_release_bits_client_xact_id),
+ .io_client_release_bits_voluntary(T_11386_io_client_release_bits_voluntary),
+ .io_client_release_bits_r_type(T_11386_io_client_release_bits_r_type),
+ .io_client_release_bits_data(T_11386_io_client_release_bits_data),
+ .io_network_acquire_ready(T_11386_io_network_acquire_ready),
+ .io_network_acquire_valid(T_11386_io_network_acquire_valid),
+ .io_network_acquire_bits_header_src(T_11386_io_network_acquire_bits_header_src),
+ .io_network_acquire_bits_header_dst(T_11386_io_network_acquire_bits_header_dst),
+ .io_network_acquire_bits_payload_addr_block(T_11386_io_network_acquire_bits_payload_addr_block),
+ .io_network_acquire_bits_payload_client_xact_id(T_11386_io_network_acquire_bits_payload_client_xact_id),
+ .io_network_acquire_bits_payload_addr_beat(T_11386_io_network_acquire_bits_payload_addr_beat),
+ .io_network_acquire_bits_payload_is_builtin_type(T_11386_io_network_acquire_bits_payload_is_builtin_type),
+ .io_network_acquire_bits_payload_a_type(T_11386_io_network_acquire_bits_payload_a_type),
+ .io_network_acquire_bits_payload_union(T_11386_io_network_acquire_bits_payload_union),
+ .io_network_acquire_bits_payload_data(T_11386_io_network_acquire_bits_payload_data),
+ .io_network_grant_ready(T_11386_io_network_grant_ready),
+ .io_network_grant_valid(T_11386_io_network_grant_valid),
+ .io_network_grant_bits_header_src(T_11386_io_network_grant_bits_header_src),
+ .io_network_grant_bits_header_dst(T_11386_io_network_grant_bits_header_dst),
+ .io_network_grant_bits_payload_addr_beat(T_11386_io_network_grant_bits_payload_addr_beat),
+ .io_network_grant_bits_payload_client_xact_id(T_11386_io_network_grant_bits_payload_client_xact_id),
+ .io_network_grant_bits_payload_manager_xact_id(T_11386_io_network_grant_bits_payload_manager_xact_id),
+ .io_network_grant_bits_payload_is_builtin_type(T_11386_io_network_grant_bits_payload_is_builtin_type),
+ .io_network_grant_bits_payload_g_type(T_11386_io_network_grant_bits_payload_g_type),
+ .io_network_grant_bits_payload_data(T_11386_io_network_grant_bits_payload_data),
+ .io_network_finish_ready(T_11386_io_network_finish_ready),
+ .io_network_finish_valid(T_11386_io_network_finish_valid),
+ .io_network_finish_bits_header_src(T_11386_io_network_finish_bits_header_src),
+ .io_network_finish_bits_header_dst(T_11386_io_network_finish_bits_header_dst),
+ .io_network_finish_bits_payload_manager_xact_id(T_11386_io_network_finish_bits_payload_manager_xact_id),
+ .io_network_probe_ready(T_11386_io_network_probe_ready),
+ .io_network_probe_valid(T_11386_io_network_probe_valid),
+ .io_network_probe_bits_header_src(T_11386_io_network_probe_bits_header_src),
+ .io_network_probe_bits_header_dst(T_11386_io_network_probe_bits_header_dst),
+ .io_network_probe_bits_payload_addr_block(T_11386_io_network_probe_bits_payload_addr_block),
+ .io_network_probe_bits_payload_p_type(T_11386_io_network_probe_bits_payload_p_type),
+ .io_network_release_ready(T_11386_io_network_release_ready),
+ .io_network_release_valid(T_11386_io_network_release_valid),
+ .io_network_release_bits_header_src(T_11386_io_network_release_bits_header_src),
+ .io_network_release_bits_header_dst(T_11386_io_network_release_bits_header_dst),
+ .io_network_release_bits_payload_addr_beat(T_11386_io_network_release_bits_payload_addr_beat),
+ .io_network_release_bits_payload_addr_block(T_11386_io_network_release_bits_payload_addr_block),
+ .io_network_release_bits_payload_client_xact_id(T_11386_io_network_release_bits_payload_client_xact_id),
+ .io_network_release_bits_payload_voluntary(T_11386_io_network_release_bits_payload_voluntary),
+ .io_network_release_bits_payload_r_type(T_11386_io_network_release_bits_payload_r_type),
+ .io_network_release_bits_payload_data(T_11386_io_network_release_bits_payload_data)
+ );
+ TileLinkEnqueuer T_11387 (
+ .clk(T_11387_clk),
+ .reset(T_11387_reset),
+ .io_client_acquire_ready(T_11387_io_client_acquire_ready),
+ .io_client_acquire_valid(T_11387_io_client_acquire_valid),
+ .io_client_acquire_bits_header_src(T_11387_io_client_acquire_bits_header_src),
+ .io_client_acquire_bits_header_dst(T_11387_io_client_acquire_bits_header_dst),
+ .io_client_acquire_bits_payload_addr_block(T_11387_io_client_acquire_bits_payload_addr_block),
+ .io_client_acquire_bits_payload_client_xact_id(T_11387_io_client_acquire_bits_payload_client_xact_id),
+ .io_client_acquire_bits_payload_addr_beat(T_11387_io_client_acquire_bits_payload_addr_beat),
+ .io_client_acquire_bits_payload_is_builtin_type(T_11387_io_client_acquire_bits_payload_is_builtin_type),
+ .io_client_acquire_bits_payload_a_type(T_11387_io_client_acquire_bits_payload_a_type),
+ .io_client_acquire_bits_payload_union(T_11387_io_client_acquire_bits_payload_union),
+ .io_client_acquire_bits_payload_data(T_11387_io_client_acquire_bits_payload_data),
+ .io_client_grant_ready(T_11387_io_client_grant_ready),
+ .io_client_grant_valid(T_11387_io_client_grant_valid),
+ .io_client_grant_bits_header_src(T_11387_io_client_grant_bits_header_src),
+ .io_client_grant_bits_header_dst(T_11387_io_client_grant_bits_header_dst),
+ .io_client_grant_bits_payload_addr_beat(T_11387_io_client_grant_bits_payload_addr_beat),
+ .io_client_grant_bits_payload_client_xact_id(T_11387_io_client_grant_bits_payload_client_xact_id),
+ .io_client_grant_bits_payload_manager_xact_id(T_11387_io_client_grant_bits_payload_manager_xact_id),
+ .io_client_grant_bits_payload_is_builtin_type(T_11387_io_client_grant_bits_payload_is_builtin_type),
+ .io_client_grant_bits_payload_g_type(T_11387_io_client_grant_bits_payload_g_type),
+ .io_client_grant_bits_payload_data(T_11387_io_client_grant_bits_payload_data),
+ .io_client_finish_ready(T_11387_io_client_finish_ready),
+ .io_client_finish_valid(T_11387_io_client_finish_valid),
+ .io_client_finish_bits_header_src(T_11387_io_client_finish_bits_header_src),
+ .io_client_finish_bits_header_dst(T_11387_io_client_finish_bits_header_dst),
+ .io_client_finish_bits_payload_manager_xact_id(T_11387_io_client_finish_bits_payload_manager_xact_id),
+ .io_client_probe_ready(T_11387_io_client_probe_ready),
+ .io_client_probe_valid(T_11387_io_client_probe_valid),
+ .io_client_probe_bits_header_src(T_11387_io_client_probe_bits_header_src),
+ .io_client_probe_bits_header_dst(T_11387_io_client_probe_bits_header_dst),
+ .io_client_probe_bits_payload_addr_block(T_11387_io_client_probe_bits_payload_addr_block),
+ .io_client_probe_bits_payload_p_type(T_11387_io_client_probe_bits_payload_p_type),
+ .io_client_release_ready(T_11387_io_client_release_ready),
+ .io_client_release_valid(T_11387_io_client_release_valid),
+ .io_client_release_bits_header_src(T_11387_io_client_release_bits_header_src),
+ .io_client_release_bits_header_dst(T_11387_io_client_release_bits_header_dst),
+ .io_client_release_bits_payload_addr_beat(T_11387_io_client_release_bits_payload_addr_beat),
+ .io_client_release_bits_payload_addr_block(T_11387_io_client_release_bits_payload_addr_block),
+ .io_client_release_bits_payload_client_xact_id(T_11387_io_client_release_bits_payload_client_xact_id),
+ .io_client_release_bits_payload_voluntary(T_11387_io_client_release_bits_payload_voluntary),
+ .io_client_release_bits_payload_r_type(T_11387_io_client_release_bits_payload_r_type),
+ .io_client_release_bits_payload_data(T_11387_io_client_release_bits_payload_data),
+ .io_manager_acquire_ready(T_11387_io_manager_acquire_ready),
+ .io_manager_acquire_valid(T_11387_io_manager_acquire_valid),
+ .io_manager_acquire_bits_header_src(T_11387_io_manager_acquire_bits_header_src),
+ .io_manager_acquire_bits_header_dst(T_11387_io_manager_acquire_bits_header_dst),
+ .io_manager_acquire_bits_payload_addr_block(T_11387_io_manager_acquire_bits_payload_addr_block),
+ .io_manager_acquire_bits_payload_client_xact_id(T_11387_io_manager_acquire_bits_payload_client_xact_id),
+ .io_manager_acquire_bits_payload_addr_beat(T_11387_io_manager_acquire_bits_payload_addr_beat),
+ .io_manager_acquire_bits_payload_is_builtin_type(T_11387_io_manager_acquire_bits_payload_is_builtin_type),
+ .io_manager_acquire_bits_payload_a_type(T_11387_io_manager_acquire_bits_payload_a_type),
+ .io_manager_acquire_bits_payload_union(T_11387_io_manager_acquire_bits_payload_union),
+ .io_manager_acquire_bits_payload_data(T_11387_io_manager_acquire_bits_payload_data),
+ .io_manager_grant_ready(T_11387_io_manager_grant_ready),
+ .io_manager_grant_valid(T_11387_io_manager_grant_valid),
+ .io_manager_grant_bits_header_src(T_11387_io_manager_grant_bits_header_src),
+ .io_manager_grant_bits_header_dst(T_11387_io_manager_grant_bits_header_dst),
+ .io_manager_grant_bits_payload_addr_beat(T_11387_io_manager_grant_bits_payload_addr_beat),
+ .io_manager_grant_bits_payload_client_xact_id(T_11387_io_manager_grant_bits_payload_client_xact_id),
+ .io_manager_grant_bits_payload_manager_xact_id(T_11387_io_manager_grant_bits_payload_manager_xact_id),
+ .io_manager_grant_bits_payload_is_builtin_type(T_11387_io_manager_grant_bits_payload_is_builtin_type),
+ .io_manager_grant_bits_payload_g_type(T_11387_io_manager_grant_bits_payload_g_type),
+ .io_manager_grant_bits_payload_data(T_11387_io_manager_grant_bits_payload_data),
+ .io_manager_finish_ready(T_11387_io_manager_finish_ready),
+ .io_manager_finish_valid(T_11387_io_manager_finish_valid),
+ .io_manager_finish_bits_header_src(T_11387_io_manager_finish_bits_header_src),
+ .io_manager_finish_bits_header_dst(T_11387_io_manager_finish_bits_header_dst),
+ .io_manager_finish_bits_payload_manager_xact_id(T_11387_io_manager_finish_bits_payload_manager_xact_id),
+ .io_manager_probe_ready(T_11387_io_manager_probe_ready),
+ .io_manager_probe_valid(T_11387_io_manager_probe_valid),
+ .io_manager_probe_bits_header_src(T_11387_io_manager_probe_bits_header_src),
+ .io_manager_probe_bits_header_dst(T_11387_io_manager_probe_bits_header_dst),
+ .io_manager_probe_bits_payload_addr_block(T_11387_io_manager_probe_bits_payload_addr_block),
+ .io_manager_probe_bits_payload_p_type(T_11387_io_manager_probe_bits_payload_p_type),
+ .io_manager_release_ready(T_11387_io_manager_release_ready),
+ .io_manager_release_valid(T_11387_io_manager_release_valid),
+ .io_manager_release_bits_header_src(T_11387_io_manager_release_bits_header_src),
+ .io_manager_release_bits_header_dst(T_11387_io_manager_release_bits_header_dst),
+ .io_manager_release_bits_payload_addr_beat(T_11387_io_manager_release_bits_payload_addr_beat),
+ .io_manager_release_bits_payload_addr_block(T_11387_io_manager_release_bits_payload_addr_block),
+ .io_manager_release_bits_payload_client_xact_id(T_11387_io_manager_release_bits_payload_client_xact_id),
+ .io_manager_release_bits_payload_voluntary(T_11387_io_manager_release_bits_payload_voluntary),
+ .io_manager_release_bits_payload_r_type(T_11387_io_manager_release_bits_payload_r_type),
+ .io_manager_release_bits_payload_data(T_11387_io_manager_release_bits_payload_data)
+ );
+ ClientTileLinkNetworkPort_6 T_11388 (
+ .clk(T_11388_clk),
+ .reset(T_11388_reset),
+ .io_client_acquire_ready(T_11388_io_client_acquire_ready),
+ .io_client_acquire_valid(T_11388_io_client_acquire_valid),
+ .io_client_acquire_bits_addr_block(T_11388_io_client_acquire_bits_addr_block),
+ .io_client_acquire_bits_client_xact_id(T_11388_io_client_acquire_bits_client_xact_id),
+ .io_client_acquire_bits_addr_beat(T_11388_io_client_acquire_bits_addr_beat),
+ .io_client_acquire_bits_is_builtin_type(T_11388_io_client_acquire_bits_is_builtin_type),
+ .io_client_acquire_bits_a_type(T_11388_io_client_acquire_bits_a_type),
+ .io_client_acquire_bits_union(T_11388_io_client_acquire_bits_union),
+ .io_client_acquire_bits_data(T_11388_io_client_acquire_bits_data),
+ .io_client_grant_ready(T_11388_io_client_grant_ready),
+ .io_client_grant_valid(T_11388_io_client_grant_valid),
+ .io_client_grant_bits_addr_beat(T_11388_io_client_grant_bits_addr_beat),
+ .io_client_grant_bits_client_xact_id(T_11388_io_client_grant_bits_client_xact_id),
+ .io_client_grant_bits_manager_xact_id(T_11388_io_client_grant_bits_manager_xact_id),
+ .io_client_grant_bits_is_builtin_type(T_11388_io_client_grant_bits_is_builtin_type),
+ .io_client_grant_bits_g_type(T_11388_io_client_grant_bits_g_type),
+ .io_client_grant_bits_data(T_11388_io_client_grant_bits_data),
+ .io_client_probe_ready(T_11388_io_client_probe_ready),
+ .io_client_probe_valid(T_11388_io_client_probe_valid),
+ .io_client_probe_bits_addr_block(T_11388_io_client_probe_bits_addr_block),
+ .io_client_probe_bits_p_type(T_11388_io_client_probe_bits_p_type),
+ .io_client_release_ready(T_11388_io_client_release_ready),
+ .io_client_release_valid(T_11388_io_client_release_valid),
+ .io_client_release_bits_addr_beat(T_11388_io_client_release_bits_addr_beat),
+ .io_client_release_bits_addr_block(T_11388_io_client_release_bits_addr_block),
+ .io_client_release_bits_client_xact_id(T_11388_io_client_release_bits_client_xact_id),
+ .io_client_release_bits_voluntary(T_11388_io_client_release_bits_voluntary),
+ .io_client_release_bits_r_type(T_11388_io_client_release_bits_r_type),
+ .io_client_release_bits_data(T_11388_io_client_release_bits_data),
+ .io_network_acquire_ready(T_11388_io_network_acquire_ready),
+ .io_network_acquire_valid(T_11388_io_network_acquire_valid),
+ .io_network_acquire_bits_header_src(T_11388_io_network_acquire_bits_header_src),
+ .io_network_acquire_bits_header_dst(T_11388_io_network_acquire_bits_header_dst),
+ .io_network_acquire_bits_payload_addr_block(T_11388_io_network_acquire_bits_payload_addr_block),
+ .io_network_acquire_bits_payload_client_xact_id(T_11388_io_network_acquire_bits_payload_client_xact_id),
+ .io_network_acquire_bits_payload_addr_beat(T_11388_io_network_acquire_bits_payload_addr_beat),
+ .io_network_acquire_bits_payload_is_builtin_type(T_11388_io_network_acquire_bits_payload_is_builtin_type),
+ .io_network_acquire_bits_payload_a_type(T_11388_io_network_acquire_bits_payload_a_type),
+ .io_network_acquire_bits_payload_union(T_11388_io_network_acquire_bits_payload_union),
+ .io_network_acquire_bits_payload_data(T_11388_io_network_acquire_bits_payload_data),
+ .io_network_grant_ready(T_11388_io_network_grant_ready),
+ .io_network_grant_valid(T_11388_io_network_grant_valid),
+ .io_network_grant_bits_header_src(T_11388_io_network_grant_bits_header_src),
+ .io_network_grant_bits_header_dst(T_11388_io_network_grant_bits_header_dst),
+ .io_network_grant_bits_payload_addr_beat(T_11388_io_network_grant_bits_payload_addr_beat),
+ .io_network_grant_bits_payload_client_xact_id(T_11388_io_network_grant_bits_payload_client_xact_id),
+ .io_network_grant_bits_payload_manager_xact_id(T_11388_io_network_grant_bits_payload_manager_xact_id),
+ .io_network_grant_bits_payload_is_builtin_type(T_11388_io_network_grant_bits_payload_is_builtin_type),
+ .io_network_grant_bits_payload_g_type(T_11388_io_network_grant_bits_payload_g_type),
+ .io_network_grant_bits_payload_data(T_11388_io_network_grant_bits_payload_data),
+ .io_network_finish_ready(T_11388_io_network_finish_ready),
+ .io_network_finish_valid(T_11388_io_network_finish_valid),
+ .io_network_finish_bits_header_src(T_11388_io_network_finish_bits_header_src),
+ .io_network_finish_bits_header_dst(T_11388_io_network_finish_bits_header_dst),
+ .io_network_finish_bits_payload_manager_xact_id(T_11388_io_network_finish_bits_payload_manager_xact_id),
+ .io_network_probe_ready(T_11388_io_network_probe_ready),
+ .io_network_probe_valid(T_11388_io_network_probe_valid),
+ .io_network_probe_bits_header_src(T_11388_io_network_probe_bits_header_src),
+ .io_network_probe_bits_header_dst(T_11388_io_network_probe_bits_header_dst),
+ .io_network_probe_bits_payload_addr_block(T_11388_io_network_probe_bits_payload_addr_block),
+ .io_network_probe_bits_payload_p_type(T_11388_io_network_probe_bits_payload_p_type),
+ .io_network_release_ready(T_11388_io_network_release_ready),
+ .io_network_release_valid(T_11388_io_network_release_valid),
+ .io_network_release_bits_header_src(T_11388_io_network_release_bits_header_src),
+ .io_network_release_bits_header_dst(T_11388_io_network_release_bits_header_dst),
+ .io_network_release_bits_payload_addr_beat(T_11388_io_network_release_bits_payload_addr_beat),
+ .io_network_release_bits_payload_addr_block(T_11388_io_network_release_bits_payload_addr_block),
+ .io_network_release_bits_payload_client_xact_id(T_11388_io_network_release_bits_payload_client_xact_id),
+ .io_network_release_bits_payload_voluntary(T_11388_io_network_release_bits_payload_voluntary),
+ .io_network_release_bits_payload_r_type(T_11388_io_network_release_bits_payload_r_type),
+ .io_network_release_bits_payload_data(T_11388_io_network_release_bits_payload_data)
+ );
+ TileLinkEnqueuer T_11389 (
+ .clk(T_11389_clk),
+ .reset(T_11389_reset),
+ .io_client_acquire_ready(T_11389_io_client_acquire_ready),
+ .io_client_acquire_valid(T_11389_io_client_acquire_valid),
+ .io_client_acquire_bits_header_src(T_11389_io_client_acquire_bits_header_src),
+ .io_client_acquire_bits_header_dst(T_11389_io_client_acquire_bits_header_dst),
+ .io_client_acquire_bits_payload_addr_block(T_11389_io_client_acquire_bits_payload_addr_block),
+ .io_client_acquire_bits_payload_client_xact_id(T_11389_io_client_acquire_bits_payload_client_xact_id),
+ .io_client_acquire_bits_payload_addr_beat(T_11389_io_client_acquire_bits_payload_addr_beat),
+ .io_client_acquire_bits_payload_is_builtin_type(T_11389_io_client_acquire_bits_payload_is_builtin_type),
+ .io_client_acquire_bits_payload_a_type(T_11389_io_client_acquire_bits_payload_a_type),
+ .io_client_acquire_bits_payload_union(T_11389_io_client_acquire_bits_payload_union),
+ .io_client_acquire_bits_payload_data(T_11389_io_client_acquire_bits_payload_data),
+ .io_client_grant_ready(T_11389_io_client_grant_ready),
+ .io_client_grant_valid(T_11389_io_client_grant_valid),
+ .io_client_grant_bits_header_src(T_11389_io_client_grant_bits_header_src),
+ .io_client_grant_bits_header_dst(T_11389_io_client_grant_bits_header_dst),
+ .io_client_grant_bits_payload_addr_beat(T_11389_io_client_grant_bits_payload_addr_beat),
+ .io_client_grant_bits_payload_client_xact_id(T_11389_io_client_grant_bits_payload_client_xact_id),
+ .io_client_grant_bits_payload_manager_xact_id(T_11389_io_client_grant_bits_payload_manager_xact_id),
+ .io_client_grant_bits_payload_is_builtin_type(T_11389_io_client_grant_bits_payload_is_builtin_type),
+ .io_client_grant_bits_payload_g_type(T_11389_io_client_grant_bits_payload_g_type),
+ .io_client_grant_bits_payload_data(T_11389_io_client_grant_bits_payload_data),
+ .io_client_finish_ready(T_11389_io_client_finish_ready),
+ .io_client_finish_valid(T_11389_io_client_finish_valid),
+ .io_client_finish_bits_header_src(T_11389_io_client_finish_bits_header_src),
+ .io_client_finish_bits_header_dst(T_11389_io_client_finish_bits_header_dst),
+ .io_client_finish_bits_payload_manager_xact_id(T_11389_io_client_finish_bits_payload_manager_xact_id),
+ .io_client_probe_ready(T_11389_io_client_probe_ready),
+ .io_client_probe_valid(T_11389_io_client_probe_valid),
+ .io_client_probe_bits_header_src(T_11389_io_client_probe_bits_header_src),
+ .io_client_probe_bits_header_dst(T_11389_io_client_probe_bits_header_dst),
+ .io_client_probe_bits_payload_addr_block(T_11389_io_client_probe_bits_payload_addr_block),
+ .io_client_probe_bits_payload_p_type(T_11389_io_client_probe_bits_payload_p_type),
+ .io_client_release_ready(T_11389_io_client_release_ready),
+ .io_client_release_valid(T_11389_io_client_release_valid),
+ .io_client_release_bits_header_src(T_11389_io_client_release_bits_header_src),
+ .io_client_release_bits_header_dst(T_11389_io_client_release_bits_header_dst),
+ .io_client_release_bits_payload_addr_beat(T_11389_io_client_release_bits_payload_addr_beat),
+ .io_client_release_bits_payload_addr_block(T_11389_io_client_release_bits_payload_addr_block),
+ .io_client_release_bits_payload_client_xact_id(T_11389_io_client_release_bits_payload_client_xact_id),
+ .io_client_release_bits_payload_voluntary(T_11389_io_client_release_bits_payload_voluntary),
+ .io_client_release_bits_payload_r_type(T_11389_io_client_release_bits_payload_r_type),
+ .io_client_release_bits_payload_data(T_11389_io_client_release_bits_payload_data),
+ .io_manager_acquire_ready(T_11389_io_manager_acquire_ready),
+ .io_manager_acquire_valid(T_11389_io_manager_acquire_valid),
+ .io_manager_acquire_bits_header_src(T_11389_io_manager_acquire_bits_header_src),
+ .io_manager_acquire_bits_header_dst(T_11389_io_manager_acquire_bits_header_dst),
+ .io_manager_acquire_bits_payload_addr_block(T_11389_io_manager_acquire_bits_payload_addr_block),
+ .io_manager_acquire_bits_payload_client_xact_id(T_11389_io_manager_acquire_bits_payload_client_xact_id),
+ .io_manager_acquire_bits_payload_addr_beat(T_11389_io_manager_acquire_bits_payload_addr_beat),
+ .io_manager_acquire_bits_payload_is_builtin_type(T_11389_io_manager_acquire_bits_payload_is_builtin_type),
+ .io_manager_acquire_bits_payload_a_type(T_11389_io_manager_acquire_bits_payload_a_type),
+ .io_manager_acquire_bits_payload_union(T_11389_io_manager_acquire_bits_payload_union),
+ .io_manager_acquire_bits_payload_data(T_11389_io_manager_acquire_bits_payload_data),
+ .io_manager_grant_ready(T_11389_io_manager_grant_ready),
+ .io_manager_grant_valid(T_11389_io_manager_grant_valid),
+ .io_manager_grant_bits_header_src(T_11389_io_manager_grant_bits_header_src),
+ .io_manager_grant_bits_header_dst(T_11389_io_manager_grant_bits_header_dst),
+ .io_manager_grant_bits_payload_addr_beat(T_11389_io_manager_grant_bits_payload_addr_beat),
+ .io_manager_grant_bits_payload_client_xact_id(T_11389_io_manager_grant_bits_payload_client_xact_id),
+ .io_manager_grant_bits_payload_manager_xact_id(T_11389_io_manager_grant_bits_payload_manager_xact_id),
+ .io_manager_grant_bits_payload_is_builtin_type(T_11389_io_manager_grant_bits_payload_is_builtin_type),
+ .io_manager_grant_bits_payload_g_type(T_11389_io_manager_grant_bits_payload_g_type),
+ .io_manager_grant_bits_payload_data(T_11389_io_manager_grant_bits_payload_data),
+ .io_manager_finish_ready(T_11389_io_manager_finish_ready),
+ .io_manager_finish_valid(T_11389_io_manager_finish_valid),
+ .io_manager_finish_bits_header_src(T_11389_io_manager_finish_bits_header_src),
+ .io_manager_finish_bits_header_dst(T_11389_io_manager_finish_bits_header_dst),
+ .io_manager_finish_bits_payload_manager_xact_id(T_11389_io_manager_finish_bits_payload_manager_xact_id),
+ .io_manager_probe_ready(T_11389_io_manager_probe_ready),
+ .io_manager_probe_valid(T_11389_io_manager_probe_valid),
+ .io_manager_probe_bits_header_src(T_11389_io_manager_probe_bits_header_src),
+ .io_manager_probe_bits_header_dst(T_11389_io_manager_probe_bits_header_dst),
+ .io_manager_probe_bits_payload_addr_block(T_11389_io_manager_probe_bits_payload_addr_block),
+ .io_manager_probe_bits_payload_p_type(T_11389_io_manager_probe_bits_payload_p_type),
+ .io_manager_release_ready(T_11389_io_manager_release_ready),
+ .io_manager_release_valid(T_11389_io_manager_release_valid),
+ .io_manager_release_bits_header_src(T_11389_io_manager_release_bits_header_src),
+ .io_manager_release_bits_header_dst(T_11389_io_manager_release_bits_header_dst),
+ .io_manager_release_bits_payload_addr_beat(T_11389_io_manager_release_bits_payload_addr_beat),
+ .io_manager_release_bits_payload_addr_block(T_11389_io_manager_release_bits_payload_addr_block),
+ .io_manager_release_bits_payload_client_xact_id(T_11389_io_manager_release_bits_payload_client_xact_id),
+ .io_manager_release_bits_payload_voluntary(T_11389_io_manager_release_bits_payload_voluntary),
+ .io_manager_release_bits_payload_r_type(T_11389_io_manager_release_bits_payload_r_type),
+ .io_manager_release_bits_payload_data(T_11389_io_manager_release_bits_payload_data)
+ );
+ ClientTileLinkNetworkPort_15 T_11390 (
+ .clk(T_11390_clk),
+ .reset(T_11390_reset),
+ .io_client_acquire_ready(T_11390_io_client_acquire_ready),
+ .io_client_acquire_valid(T_11390_io_client_acquire_valid),
+ .io_client_acquire_bits_addr_block(T_11390_io_client_acquire_bits_addr_block),
+ .io_client_acquire_bits_client_xact_id(T_11390_io_client_acquire_bits_client_xact_id),
+ .io_client_acquire_bits_addr_beat(T_11390_io_client_acquire_bits_addr_beat),
+ .io_client_acquire_bits_is_builtin_type(T_11390_io_client_acquire_bits_is_builtin_type),
+ .io_client_acquire_bits_a_type(T_11390_io_client_acquire_bits_a_type),
+ .io_client_acquire_bits_union(T_11390_io_client_acquire_bits_union),
+ .io_client_acquire_bits_data(T_11390_io_client_acquire_bits_data),
+ .io_client_grant_ready(T_11390_io_client_grant_ready),
+ .io_client_grant_valid(T_11390_io_client_grant_valid),
+ .io_client_grant_bits_addr_beat(T_11390_io_client_grant_bits_addr_beat),
+ .io_client_grant_bits_client_xact_id(T_11390_io_client_grant_bits_client_xact_id),
+ .io_client_grant_bits_manager_xact_id(T_11390_io_client_grant_bits_manager_xact_id),
+ .io_client_grant_bits_is_builtin_type(T_11390_io_client_grant_bits_is_builtin_type),
+ .io_client_grant_bits_g_type(T_11390_io_client_grant_bits_g_type),
+ .io_client_grant_bits_data(T_11390_io_client_grant_bits_data),
+ .io_client_probe_ready(T_11390_io_client_probe_ready),
+ .io_client_probe_valid(T_11390_io_client_probe_valid),
+ .io_client_probe_bits_addr_block(T_11390_io_client_probe_bits_addr_block),
+ .io_client_probe_bits_p_type(T_11390_io_client_probe_bits_p_type),
+ .io_client_release_ready(T_11390_io_client_release_ready),
+ .io_client_release_valid(T_11390_io_client_release_valid),
+ .io_client_release_bits_addr_beat(T_11390_io_client_release_bits_addr_beat),
+ .io_client_release_bits_addr_block(T_11390_io_client_release_bits_addr_block),
+ .io_client_release_bits_client_xact_id(T_11390_io_client_release_bits_client_xact_id),
+ .io_client_release_bits_voluntary(T_11390_io_client_release_bits_voluntary),
+ .io_client_release_bits_r_type(T_11390_io_client_release_bits_r_type),
+ .io_client_release_bits_data(T_11390_io_client_release_bits_data),
+ .io_network_acquire_ready(T_11390_io_network_acquire_ready),
+ .io_network_acquire_valid(T_11390_io_network_acquire_valid),
+ .io_network_acquire_bits_header_src(T_11390_io_network_acquire_bits_header_src),
+ .io_network_acquire_bits_header_dst(T_11390_io_network_acquire_bits_header_dst),
+ .io_network_acquire_bits_payload_addr_block(T_11390_io_network_acquire_bits_payload_addr_block),
+ .io_network_acquire_bits_payload_client_xact_id(T_11390_io_network_acquire_bits_payload_client_xact_id),
+ .io_network_acquire_bits_payload_addr_beat(T_11390_io_network_acquire_bits_payload_addr_beat),
+ .io_network_acquire_bits_payload_is_builtin_type(T_11390_io_network_acquire_bits_payload_is_builtin_type),
+ .io_network_acquire_bits_payload_a_type(T_11390_io_network_acquire_bits_payload_a_type),
+ .io_network_acquire_bits_payload_union(T_11390_io_network_acquire_bits_payload_union),
+ .io_network_acquire_bits_payload_data(T_11390_io_network_acquire_bits_payload_data),
+ .io_network_grant_ready(T_11390_io_network_grant_ready),
+ .io_network_grant_valid(T_11390_io_network_grant_valid),
+ .io_network_grant_bits_header_src(T_11390_io_network_grant_bits_header_src),
+ .io_network_grant_bits_header_dst(T_11390_io_network_grant_bits_header_dst),
+ .io_network_grant_bits_payload_addr_beat(T_11390_io_network_grant_bits_payload_addr_beat),
+ .io_network_grant_bits_payload_client_xact_id(T_11390_io_network_grant_bits_payload_client_xact_id),
+ .io_network_grant_bits_payload_manager_xact_id(T_11390_io_network_grant_bits_payload_manager_xact_id),
+ .io_network_grant_bits_payload_is_builtin_type(T_11390_io_network_grant_bits_payload_is_builtin_type),
+ .io_network_grant_bits_payload_g_type(T_11390_io_network_grant_bits_payload_g_type),
+ .io_network_grant_bits_payload_data(T_11390_io_network_grant_bits_payload_data),
+ .io_network_finish_ready(T_11390_io_network_finish_ready),
+ .io_network_finish_valid(T_11390_io_network_finish_valid),
+ .io_network_finish_bits_header_src(T_11390_io_network_finish_bits_header_src),
+ .io_network_finish_bits_header_dst(T_11390_io_network_finish_bits_header_dst),
+ .io_network_finish_bits_payload_manager_xact_id(T_11390_io_network_finish_bits_payload_manager_xact_id),
+ .io_network_probe_ready(T_11390_io_network_probe_ready),
+ .io_network_probe_valid(T_11390_io_network_probe_valid),
+ .io_network_probe_bits_header_src(T_11390_io_network_probe_bits_header_src),
+ .io_network_probe_bits_header_dst(T_11390_io_network_probe_bits_header_dst),
+ .io_network_probe_bits_payload_addr_block(T_11390_io_network_probe_bits_payload_addr_block),
+ .io_network_probe_bits_payload_p_type(T_11390_io_network_probe_bits_payload_p_type),
+ .io_network_release_ready(T_11390_io_network_release_ready),
+ .io_network_release_valid(T_11390_io_network_release_valid),
+ .io_network_release_bits_header_src(T_11390_io_network_release_bits_header_src),
+ .io_network_release_bits_header_dst(T_11390_io_network_release_bits_header_dst),
+ .io_network_release_bits_payload_addr_beat(T_11390_io_network_release_bits_payload_addr_beat),
+ .io_network_release_bits_payload_addr_block(T_11390_io_network_release_bits_payload_addr_block),
+ .io_network_release_bits_payload_client_xact_id(T_11390_io_network_release_bits_payload_client_xact_id),
+ .io_network_release_bits_payload_voluntary(T_11390_io_network_release_bits_payload_voluntary),
+ .io_network_release_bits_payload_r_type(T_11390_io_network_release_bits_payload_r_type),
+ .io_network_release_bits_payload_data(T_11390_io_network_release_bits_payload_data)
+ );
+ TileLinkEnqueuer T_11391 (
+ .clk(T_11391_clk),
+ .reset(T_11391_reset),
+ .io_client_acquire_ready(T_11391_io_client_acquire_ready),
+ .io_client_acquire_valid(T_11391_io_client_acquire_valid),
+ .io_client_acquire_bits_header_src(T_11391_io_client_acquire_bits_header_src),
+ .io_client_acquire_bits_header_dst(T_11391_io_client_acquire_bits_header_dst),
+ .io_client_acquire_bits_payload_addr_block(T_11391_io_client_acquire_bits_payload_addr_block),
+ .io_client_acquire_bits_payload_client_xact_id(T_11391_io_client_acquire_bits_payload_client_xact_id),
+ .io_client_acquire_bits_payload_addr_beat(T_11391_io_client_acquire_bits_payload_addr_beat),
+ .io_client_acquire_bits_payload_is_builtin_type(T_11391_io_client_acquire_bits_payload_is_builtin_type),
+ .io_client_acquire_bits_payload_a_type(T_11391_io_client_acquire_bits_payload_a_type),
+ .io_client_acquire_bits_payload_union(T_11391_io_client_acquire_bits_payload_union),
+ .io_client_acquire_bits_payload_data(T_11391_io_client_acquire_bits_payload_data),
+ .io_client_grant_ready(T_11391_io_client_grant_ready),
+ .io_client_grant_valid(T_11391_io_client_grant_valid),
+ .io_client_grant_bits_header_src(T_11391_io_client_grant_bits_header_src),
+ .io_client_grant_bits_header_dst(T_11391_io_client_grant_bits_header_dst),
+ .io_client_grant_bits_payload_addr_beat(T_11391_io_client_grant_bits_payload_addr_beat),
+ .io_client_grant_bits_payload_client_xact_id(T_11391_io_client_grant_bits_payload_client_xact_id),
+ .io_client_grant_bits_payload_manager_xact_id(T_11391_io_client_grant_bits_payload_manager_xact_id),
+ .io_client_grant_bits_payload_is_builtin_type(T_11391_io_client_grant_bits_payload_is_builtin_type),
+ .io_client_grant_bits_payload_g_type(T_11391_io_client_grant_bits_payload_g_type),
+ .io_client_grant_bits_payload_data(T_11391_io_client_grant_bits_payload_data),
+ .io_client_finish_ready(T_11391_io_client_finish_ready),
+ .io_client_finish_valid(T_11391_io_client_finish_valid),
+ .io_client_finish_bits_header_src(T_11391_io_client_finish_bits_header_src),
+ .io_client_finish_bits_header_dst(T_11391_io_client_finish_bits_header_dst),
+ .io_client_finish_bits_payload_manager_xact_id(T_11391_io_client_finish_bits_payload_manager_xact_id),
+ .io_client_probe_ready(T_11391_io_client_probe_ready),
+ .io_client_probe_valid(T_11391_io_client_probe_valid),
+ .io_client_probe_bits_header_src(T_11391_io_client_probe_bits_header_src),
+ .io_client_probe_bits_header_dst(T_11391_io_client_probe_bits_header_dst),
+ .io_client_probe_bits_payload_addr_block(T_11391_io_client_probe_bits_payload_addr_block),
+ .io_client_probe_bits_payload_p_type(T_11391_io_client_probe_bits_payload_p_type),
+ .io_client_release_ready(T_11391_io_client_release_ready),
+ .io_client_release_valid(T_11391_io_client_release_valid),
+ .io_client_release_bits_header_src(T_11391_io_client_release_bits_header_src),
+ .io_client_release_bits_header_dst(T_11391_io_client_release_bits_header_dst),
+ .io_client_release_bits_payload_addr_beat(T_11391_io_client_release_bits_payload_addr_beat),
+ .io_client_release_bits_payload_addr_block(T_11391_io_client_release_bits_payload_addr_block),
+ .io_client_release_bits_payload_client_xact_id(T_11391_io_client_release_bits_payload_client_xact_id),
+ .io_client_release_bits_payload_voluntary(T_11391_io_client_release_bits_payload_voluntary),
+ .io_client_release_bits_payload_r_type(T_11391_io_client_release_bits_payload_r_type),
+ .io_client_release_bits_payload_data(T_11391_io_client_release_bits_payload_data),
+ .io_manager_acquire_ready(T_11391_io_manager_acquire_ready),
+ .io_manager_acquire_valid(T_11391_io_manager_acquire_valid),
+ .io_manager_acquire_bits_header_src(T_11391_io_manager_acquire_bits_header_src),
+ .io_manager_acquire_bits_header_dst(T_11391_io_manager_acquire_bits_header_dst),
+ .io_manager_acquire_bits_payload_addr_block(T_11391_io_manager_acquire_bits_payload_addr_block),
+ .io_manager_acquire_bits_payload_client_xact_id(T_11391_io_manager_acquire_bits_payload_client_xact_id),
+ .io_manager_acquire_bits_payload_addr_beat(T_11391_io_manager_acquire_bits_payload_addr_beat),
+ .io_manager_acquire_bits_payload_is_builtin_type(T_11391_io_manager_acquire_bits_payload_is_builtin_type),
+ .io_manager_acquire_bits_payload_a_type(T_11391_io_manager_acquire_bits_payload_a_type),
+ .io_manager_acquire_bits_payload_union(T_11391_io_manager_acquire_bits_payload_union),
+ .io_manager_acquire_bits_payload_data(T_11391_io_manager_acquire_bits_payload_data),
+ .io_manager_grant_ready(T_11391_io_manager_grant_ready),
+ .io_manager_grant_valid(T_11391_io_manager_grant_valid),
+ .io_manager_grant_bits_header_src(T_11391_io_manager_grant_bits_header_src),
+ .io_manager_grant_bits_header_dst(T_11391_io_manager_grant_bits_header_dst),
+ .io_manager_grant_bits_payload_addr_beat(T_11391_io_manager_grant_bits_payload_addr_beat),
+ .io_manager_grant_bits_payload_client_xact_id(T_11391_io_manager_grant_bits_payload_client_xact_id),
+ .io_manager_grant_bits_payload_manager_xact_id(T_11391_io_manager_grant_bits_payload_manager_xact_id),
+ .io_manager_grant_bits_payload_is_builtin_type(T_11391_io_manager_grant_bits_payload_is_builtin_type),
+ .io_manager_grant_bits_payload_g_type(T_11391_io_manager_grant_bits_payload_g_type),
+ .io_manager_grant_bits_payload_data(T_11391_io_manager_grant_bits_payload_data),
+ .io_manager_finish_ready(T_11391_io_manager_finish_ready),
+ .io_manager_finish_valid(T_11391_io_manager_finish_valid),
+ .io_manager_finish_bits_header_src(T_11391_io_manager_finish_bits_header_src),
+ .io_manager_finish_bits_header_dst(T_11391_io_manager_finish_bits_header_dst),
+ .io_manager_finish_bits_payload_manager_xact_id(T_11391_io_manager_finish_bits_payload_manager_xact_id),
+ .io_manager_probe_ready(T_11391_io_manager_probe_ready),
+ .io_manager_probe_valid(T_11391_io_manager_probe_valid),
+ .io_manager_probe_bits_header_src(T_11391_io_manager_probe_bits_header_src),
+ .io_manager_probe_bits_header_dst(T_11391_io_manager_probe_bits_header_dst),
+ .io_manager_probe_bits_payload_addr_block(T_11391_io_manager_probe_bits_payload_addr_block),
+ .io_manager_probe_bits_payload_p_type(T_11391_io_manager_probe_bits_payload_p_type),
+ .io_manager_release_ready(T_11391_io_manager_release_ready),
+ .io_manager_release_valid(T_11391_io_manager_release_valid),
+ .io_manager_release_bits_header_src(T_11391_io_manager_release_bits_header_src),
+ .io_manager_release_bits_header_dst(T_11391_io_manager_release_bits_header_dst),
+ .io_manager_release_bits_payload_addr_beat(T_11391_io_manager_release_bits_payload_addr_beat),
+ .io_manager_release_bits_payload_addr_block(T_11391_io_manager_release_bits_payload_addr_block),
+ .io_manager_release_bits_payload_client_xact_id(T_11391_io_manager_release_bits_payload_client_xact_id),
+ .io_manager_release_bits_payload_voluntary(T_11391_io_manager_release_bits_payload_voluntary),
+ .io_manager_release_bits_payload_r_type(T_11391_io_manager_release_bits_payload_r_type),
+ .io_manager_release_bits_payload_data(T_11391_io_manager_release_bits_payload_data)
+ );
+ ManagerTileLinkNetworkPort T_11392 (
+ .clk(T_11392_clk),
+ .reset(T_11392_reset),
+ .io_manager_acquire_ready(T_11392_io_manager_acquire_ready),
+ .io_manager_acquire_valid(T_11392_io_manager_acquire_valid),
+ .io_manager_acquire_bits_addr_block(T_11392_io_manager_acquire_bits_addr_block),
+ .io_manager_acquire_bits_client_xact_id(T_11392_io_manager_acquire_bits_client_xact_id),
+ .io_manager_acquire_bits_addr_beat(T_11392_io_manager_acquire_bits_addr_beat),
+ .io_manager_acquire_bits_is_builtin_type(T_11392_io_manager_acquire_bits_is_builtin_type),
+ .io_manager_acquire_bits_a_type(T_11392_io_manager_acquire_bits_a_type),
+ .io_manager_acquire_bits_union(T_11392_io_manager_acquire_bits_union),
+ .io_manager_acquire_bits_data(T_11392_io_manager_acquire_bits_data),
+ .io_manager_acquire_bits_client_id(T_11392_io_manager_acquire_bits_client_id),
+ .io_manager_grant_ready(T_11392_io_manager_grant_ready),
+ .io_manager_grant_valid(T_11392_io_manager_grant_valid),
+ .io_manager_grant_bits_addr_beat(T_11392_io_manager_grant_bits_addr_beat),
+ .io_manager_grant_bits_client_xact_id(T_11392_io_manager_grant_bits_client_xact_id),
+ .io_manager_grant_bits_manager_xact_id(T_11392_io_manager_grant_bits_manager_xact_id),
+ .io_manager_grant_bits_is_builtin_type(T_11392_io_manager_grant_bits_is_builtin_type),
+ .io_manager_grant_bits_g_type(T_11392_io_manager_grant_bits_g_type),
+ .io_manager_grant_bits_data(T_11392_io_manager_grant_bits_data),
+ .io_manager_grant_bits_client_id(T_11392_io_manager_grant_bits_client_id),
+ .io_manager_finish_ready(T_11392_io_manager_finish_ready),
+ .io_manager_finish_valid(T_11392_io_manager_finish_valid),
+ .io_manager_finish_bits_manager_xact_id(T_11392_io_manager_finish_bits_manager_xact_id),
+ .io_manager_probe_ready(T_11392_io_manager_probe_ready),
+ .io_manager_probe_valid(T_11392_io_manager_probe_valid),
+ .io_manager_probe_bits_addr_block(T_11392_io_manager_probe_bits_addr_block),
+ .io_manager_probe_bits_p_type(T_11392_io_manager_probe_bits_p_type),
+ .io_manager_probe_bits_client_id(T_11392_io_manager_probe_bits_client_id),
+ .io_manager_release_ready(T_11392_io_manager_release_ready),
+ .io_manager_release_valid(T_11392_io_manager_release_valid),
+ .io_manager_release_bits_addr_beat(T_11392_io_manager_release_bits_addr_beat),
+ .io_manager_release_bits_addr_block(T_11392_io_manager_release_bits_addr_block),
+ .io_manager_release_bits_client_xact_id(T_11392_io_manager_release_bits_client_xact_id),
+ .io_manager_release_bits_voluntary(T_11392_io_manager_release_bits_voluntary),
+ .io_manager_release_bits_r_type(T_11392_io_manager_release_bits_r_type),
+ .io_manager_release_bits_data(T_11392_io_manager_release_bits_data),
+ .io_manager_release_bits_client_id(T_11392_io_manager_release_bits_client_id),
+ .io_network_acquire_ready(T_11392_io_network_acquire_ready),
+ .io_network_acquire_valid(T_11392_io_network_acquire_valid),
+ .io_network_acquire_bits_header_src(T_11392_io_network_acquire_bits_header_src),
+ .io_network_acquire_bits_header_dst(T_11392_io_network_acquire_bits_header_dst),
+ .io_network_acquire_bits_payload_addr_block(T_11392_io_network_acquire_bits_payload_addr_block),
+ .io_network_acquire_bits_payload_client_xact_id(T_11392_io_network_acquire_bits_payload_client_xact_id),
+ .io_network_acquire_bits_payload_addr_beat(T_11392_io_network_acquire_bits_payload_addr_beat),
+ .io_network_acquire_bits_payload_is_builtin_type(T_11392_io_network_acquire_bits_payload_is_builtin_type),
+ .io_network_acquire_bits_payload_a_type(T_11392_io_network_acquire_bits_payload_a_type),
+ .io_network_acquire_bits_payload_union(T_11392_io_network_acquire_bits_payload_union),
+ .io_network_acquire_bits_payload_data(T_11392_io_network_acquire_bits_payload_data),
+ .io_network_grant_ready(T_11392_io_network_grant_ready),
+ .io_network_grant_valid(T_11392_io_network_grant_valid),
+ .io_network_grant_bits_header_src(T_11392_io_network_grant_bits_header_src),
+ .io_network_grant_bits_header_dst(T_11392_io_network_grant_bits_header_dst),
+ .io_network_grant_bits_payload_addr_beat(T_11392_io_network_grant_bits_payload_addr_beat),
+ .io_network_grant_bits_payload_client_xact_id(T_11392_io_network_grant_bits_payload_client_xact_id),
+ .io_network_grant_bits_payload_manager_xact_id(T_11392_io_network_grant_bits_payload_manager_xact_id),
+ .io_network_grant_bits_payload_is_builtin_type(T_11392_io_network_grant_bits_payload_is_builtin_type),
+ .io_network_grant_bits_payload_g_type(T_11392_io_network_grant_bits_payload_g_type),
+ .io_network_grant_bits_payload_data(T_11392_io_network_grant_bits_payload_data),
+ .io_network_finish_ready(T_11392_io_network_finish_ready),
+ .io_network_finish_valid(T_11392_io_network_finish_valid),
+ .io_network_finish_bits_header_src(T_11392_io_network_finish_bits_header_src),
+ .io_network_finish_bits_header_dst(T_11392_io_network_finish_bits_header_dst),
+ .io_network_finish_bits_payload_manager_xact_id(T_11392_io_network_finish_bits_payload_manager_xact_id),
+ .io_network_probe_ready(T_11392_io_network_probe_ready),
+ .io_network_probe_valid(T_11392_io_network_probe_valid),
+ .io_network_probe_bits_header_src(T_11392_io_network_probe_bits_header_src),
+ .io_network_probe_bits_header_dst(T_11392_io_network_probe_bits_header_dst),
+ .io_network_probe_bits_payload_addr_block(T_11392_io_network_probe_bits_payload_addr_block),
+ .io_network_probe_bits_payload_p_type(T_11392_io_network_probe_bits_payload_p_type),
+ .io_network_release_ready(T_11392_io_network_release_ready),
+ .io_network_release_valid(T_11392_io_network_release_valid),
+ .io_network_release_bits_header_src(T_11392_io_network_release_bits_header_src),
+ .io_network_release_bits_header_dst(T_11392_io_network_release_bits_header_dst),
+ .io_network_release_bits_payload_addr_beat(T_11392_io_network_release_bits_payload_addr_beat),
+ .io_network_release_bits_payload_addr_block(T_11392_io_network_release_bits_payload_addr_block),
+ .io_network_release_bits_payload_client_xact_id(T_11392_io_network_release_bits_payload_client_xact_id),
+ .io_network_release_bits_payload_voluntary(T_11392_io_network_release_bits_payload_voluntary),
+ .io_network_release_bits_payload_r_type(T_11392_io_network_release_bits_payload_r_type),
+ .io_network_release_bits_payload_data(T_11392_io_network_release_bits_payload_data)
+ );
+ TileLinkEnqueuer_24 T_11393 (
+ .clk(T_11393_clk),
+ .reset(T_11393_reset),
+ .io_client_acquire_ready(T_11393_io_client_acquire_ready),
+ .io_client_acquire_valid(T_11393_io_client_acquire_valid),
+ .io_client_acquire_bits_header_src(T_11393_io_client_acquire_bits_header_src),
+ .io_client_acquire_bits_header_dst(T_11393_io_client_acquire_bits_header_dst),
+ .io_client_acquire_bits_payload_addr_block(T_11393_io_client_acquire_bits_payload_addr_block),
+ .io_client_acquire_bits_payload_client_xact_id(T_11393_io_client_acquire_bits_payload_client_xact_id),
+ .io_client_acquire_bits_payload_addr_beat(T_11393_io_client_acquire_bits_payload_addr_beat),
+ .io_client_acquire_bits_payload_is_builtin_type(T_11393_io_client_acquire_bits_payload_is_builtin_type),
+ .io_client_acquire_bits_payload_a_type(T_11393_io_client_acquire_bits_payload_a_type),
+ .io_client_acquire_bits_payload_union(T_11393_io_client_acquire_bits_payload_union),
+ .io_client_acquire_bits_payload_data(T_11393_io_client_acquire_bits_payload_data),
+ .io_client_grant_ready(T_11393_io_client_grant_ready),
+ .io_client_grant_valid(T_11393_io_client_grant_valid),
+ .io_client_grant_bits_header_src(T_11393_io_client_grant_bits_header_src),
+ .io_client_grant_bits_header_dst(T_11393_io_client_grant_bits_header_dst),
+ .io_client_grant_bits_payload_addr_beat(T_11393_io_client_grant_bits_payload_addr_beat),
+ .io_client_grant_bits_payload_client_xact_id(T_11393_io_client_grant_bits_payload_client_xact_id),
+ .io_client_grant_bits_payload_manager_xact_id(T_11393_io_client_grant_bits_payload_manager_xact_id),
+ .io_client_grant_bits_payload_is_builtin_type(T_11393_io_client_grant_bits_payload_is_builtin_type),
+ .io_client_grant_bits_payload_g_type(T_11393_io_client_grant_bits_payload_g_type),
+ .io_client_grant_bits_payload_data(T_11393_io_client_grant_bits_payload_data),
+ .io_client_finish_ready(T_11393_io_client_finish_ready),
+ .io_client_finish_valid(T_11393_io_client_finish_valid),
+ .io_client_finish_bits_header_src(T_11393_io_client_finish_bits_header_src),
+ .io_client_finish_bits_header_dst(T_11393_io_client_finish_bits_header_dst),
+ .io_client_finish_bits_payload_manager_xact_id(T_11393_io_client_finish_bits_payload_manager_xact_id),
+ .io_client_probe_ready(T_11393_io_client_probe_ready),
+ .io_client_probe_valid(T_11393_io_client_probe_valid),
+ .io_client_probe_bits_header_src(T_11393_io_client_probe_bits_header_src),
+ .io_client_probe_bits_header_dst(T_11393_io_client_probe_bits_header_dst),
+ .io_client_probe_bits_payload_addr_block(T_11393_io_client_probe_bits_payload_addr_block),
+ .io_client_probe_bits_payload_p_type(T_11393_io_client_probe_bits_payload_p_type),
+ .io_client_release_ready(T_11393_io_client_release_ready),
+ .io_client_release_valid(T_11393_io_client_release_valid),
+ .io_client_release_bits_header_src(T_11393_io_client_release_bits_header_src),
+ .io_client_release_bits_header_dst(T_11393_io_client_release_bits_header_dst),
+ .io_client_release_bits_payload_addr_beat(T_11393_io_client_release_bits_payload_addr_beat),
+ .io_client_release_bits_payload_addr_block(T_11393_io_client_release_bits_payload_addr_block),
+ .io_client_release_bits_payload_client_xact_id(T_11393_io_client_release_bits_payload_client_xact_id),
+ .io_client_release_bits_payload_voluntary(T_11393_io_client_release_bits_payload_voluntary),
+ .io_client_release_bits_payload_r_type(T_11393_io_client_release_bits_payload_r_type),
+ .io_client_release_bits_payload_data(T_11393_io_client_release_bits_payload_data),
+ .io_manager_acquire_ready(T_11393_io_manager_acquire_ready),
+ .io_manager_acquire_valid(T_11393_io_manager_acquire_valid),
+ .io_manager_acquire_bits_header_src(T_11393_io_manager_acquire_bits_header_src),
+ .io_manager_acquire_bits_header_dst(T_11393_io_manager_acquire_bits_header_dst),
+ .io_manager_acquire_bits_payload_addr_block(T_11393_io_manager_acquire_bits_payload_addr_block),
+ .io_manager_acquire_bits_payload_client_xact_id(T_11393_io_manager_acquire_bits_payload_client_xact_id),
+ .io_manager_acquire_bits_payload_addr_beat(T_11393_io_manager_acquire_bits_payload_addr_beat),
+ .io_manager_acquire_bits_payload_is_builtin_type(T_11393_io_manager_acquire_bits_payload_is_builtin_type),
+ .io_manager_acquire_bits_payload_a_type(T_11393_io_manager_acquire_bits_payload_a_type),
+ .io_manager_acquire_bits_payload_union(T_11393_io_manager_acquire_bits_payload_union),
+ .io_manager_acquire_bits_payload_data(T_11393_io_manager_acquire_bits_payload_data),
+ .io_manager_grant_ready(T_11393_io_manager_grant_ready),
+ .io_manager_grant_valid(T_11393_io_manager_grant_valid),
+ .io_manager_grant_bits_header_src(T_11393_io_manager_grant_bits_header_src),
+ .io_manager_grant_bits_header_dst(T_11393_io_manager_grant_bits_header_dst),
+ .io_manager_grant_bits_payload_addr_beat(T_11393_io_manager_grant_bits_payload_addr_beat),
+ .io_manager_grant_bits_payload_client_xact_id(T_11393_io_manager_grant_bits_payload_client_xact_id),
+ .io_manager_grant_bits_payload_manager_xact_id(T_11393_io_manager_grant_bits_payload_manager_xact_id),
+ .io_manager_grant_bits_payload_is_builtin_type(T_11393_io_manager_grant_bits_payload_is_builtin_type),
+ .io_manager_grant_bits_payload_g_type(T_11393_io_manager_grant_bits_payload_g_type),
+ .io_manager_grant_bits_payload_data(T_11393_io_manager_grant_bits_payload_data),
+ .io_manager_finish_ready(T_11393_io_manager_finish_ready),
+ .io_manager_finish_valid(T_11393_io_manager_finish_valid),
+ .io_manager_finish_bits_header_src(T_11393_io_manager_finish_bits_header_src),
+ .io_manager_finish_bits_header_dst(T_11393_io_manager_finish_bits_header_dst),
+ .io_manager_finish_bits_payload_manager_xact_id(T_11393_io_manager_finish_bits_payload_manager_xact_id),
+ .io_manager_probe_ready(T_11393_io_manager_probe_ready),
+ .io_manager_probe_valid(T_11393_io_manager_probe_valid),
+ .io_manager_probe_bits_header_src(T_11393_io_manager_probe_bits_header_src),
+ .io_manager_probe_bits_header_dst(T_11393_io_manager_probe_bits_header_dst),
+ .io_manager_probe_bits_payload_addr_block(T_11393_io_manager_probe_bits_payload_addr_block),
+ .io_manager_probe_bits_payload_p_type(T_11393_io_manager_probe_bits_payload_p_type),
+ .io_manager_release_ready(T_11393_io_manager_release_ready),
+ .io_manager_release_valid(T_11393_io_manager_release_valid),
+ .io_manager_release_bits_header_src(T_11393_io_manager_release_bits_header_src),
+ .io_manager_release_bits_header_dst(T_11393_io_manager_release_bits_header_dst),
+ .io_manager_release_bits_payload_addr_beat(T_11393_io_manager_release_bits_payload_addr_beat),
+ .io_manager_release_bits_payload_addr_block(T_11393_io_manager_release_bits_payload_addr_block),
+ .io_manager_release_bits_payload_client_xact_id(T_11393_io_manager_release_bits_payload_client_xact_id),
+ .io_manager_release_bits_payload_voluntary(T_11393_io_manager_release_bits_payload_voluntary),
+ .io_manager_release_bits_payload_r_type(T_11393_io_manager_release_bits_payload_r_type),
+ .io_manager_release_bits_payload_data(T_11393_io_manager_release_bits_payload_data)
+ );
+ LockingRRArbiter T_11394 (
+ .clk(T_11394_clk),
+ .reset(T_11394_reset),
+ .io_in_0_ready(T_11394_io_in_0_ready),
+ .io_in_0_valid(T_11394_io_in_0_valid),
+ .io_in_0_bits_header_src(T_11394_io_in_0_bits_header_src),
+ .io_in_0_bits_header_dst(T_11394_io_in_0_bits_header_dst),
+ .io_in_0_bits_payload_addr_block(T_11394_io_in_0_bits_payload_addr_block),
+ .io_in_0_bits_payload_client_xact_id(T_11394_io_in_0_bits_payload_client_xact_id),
+ .io_in_0_bits_payload_addr_beat(T_11394_io_in_0_bits_payload_addr_beat),
+ .io_in_0_bits_payload_is_builtin_type(T_11394_io_in_0_bits_payload_is_builtin_type),
+ .io_in_0_bits_payload_a_type(T_11394_io_in_0_bits_payload_a_type),
+ .io_in_0_bits_payload_union(T_11394_io_in_0_bits_payload_union),
+ .io_in_0_bits_payload_data(T_11394_io_in_0_bits_payload_data),
+ .io_in_1_ready(T_11394_io_in_1_ready),
+ .io_in_1_valid(T_11394_io_in_1_valid),
+ .io_in_1_bits_header_src(T_11394_io_in_1_bits_header_src),
+ .io_in_1_bits_header_dst(T_11394_io_in_1_bits_header_dst),
+ .io_in_1_bits_payload_addr_block(T_11394_io_in_1_bits_payload_addr_block),
+ .io_in_1_bits_payload_client_xact_id(T_11394_io_in_1_bits_payload_client_xact_id),
+ .io_in_1_bits_payload_addr_beat(T_11394_io_in_1_bits_payload_addr_beat),
+ .io_in_1_bits_payload_is_builtin_type(T_11394_io_in_1_bits_payload_is_builtin_type),
+ .io_in_1_bits_payload_a_type(T_11394_io_in_1_bits_payload_a_type),
+ .io_in_1_bits_payload_union(T_11394_io_in_1_bits_payload_union),
+ .io_in_1_bits_payload_data(T_11394_io_in_1_bits_payload_data),
+ .io_in_2_ready(T_11394_io_in_2_ready),
+ .io_in_2_valid(T_11394_io_in_2_valid),
+ .io_in_2_bits_header_src(T_11394_io_in_2_bits_header_src),
+ .io_in_2_bits_header_dst(T_11394_io_in_2_bits_header_dst),
+ .io_in_2_bits_payload_addr_block(T_11394_io_in_2_bits_payload_addr_block),
+ .io_in_2_bits_payload_client_xact_id(T_11394_io_in_2_bits_payload_client_xact_id),
+ .io_in_2_bits_payload_addr_beat(T_11394_io_in_2_bits_payload_addr_beat),
+ .io_in_2_bits_payload_is_builtin_type(T_11394_io_in_2_bits_payload_is_builtin_type),
+ .io_in_2_bits_payload_a_type(T_11394_io_in_2_bits_payload_a_type),
+ .io_in_2_bits_payload_union(T_11394_io_in_2_bits_payload_union),
+ .io_in_2_bits_payload_data(T_11394_io_in_2_bits_payload_data),
+ .io_out_ready(T_11394_io_out_ready),
+ .io_out_valid(T_11394_io_out_valid),
+ .io_out_bits_header_src(T_11394_io_out_bits_header_src),
+ .io_out_bits_header_dst(T_11394_io_out_bits_header_dst),
+ .io_out_bits_payload_addr_block(T_11394_io_out_bits_payload_addr_block),
+ .io_out_bits_payload_client_xact_id(T_11394_io_out_bits_payload_client_xact_id),
+ .io_out_bits_payload_addr_beat(T_11394_io_out_bits_payload_addr_beat),
+ .io_out_bits_payload_is_builtin_type(T_11394_io_out_bits_payload_is_builtin_type),
+ .io_out_bits_payload_a_type(T_11394_io_out_bits_payload_a_type),
+ .io_out_bits_payload_union(T_11394_io_out_bits_payload_union),
+ .io_out_bits_payload_data(T_11394_io_out_bits_payload_data),
+ .io_chosen(T_11394_io_chosen)
+ );
+ LockingRRArbiter_26 T_11395 (
+ .clk(T_11395_clk),
+ .reset(T_11395_reset),
+ .io_in_0_ready(T_11395_io_in_0_ready),
+ .io_in_0_valid(T_11395_io_in_0_valid),
+ .io_in_0_bits_header_src(T_11395_io_in_0_bits_header_src),
+ .io_in_0_bits_header_dst(T_11395_io_in_0_bits_header_dst),
+ .io_in_0_bits_payload_addr_beat(T_11395_io_in_0_bits_payload_addr_beat),
+ .io_in_0_bits_payload_addr_block(T_11395_io_in_0_bits_payload_addr_block),
+ .io_in_0_bits_payload_client_xact_id(T_11395_io_in_0_bits_payload_client_xact_id),
+ .io_in_0_bits_payload_voluntary(T_11395_io_in_0_bits_payload_voluntary),
+ .io_in_0_bits_payload_r_type(T_11395_io_in_0_bits_payload_r_type),
+ .io_in_0_bits_payload_data(T_11395_io_in_0_bits_payload_data),
+ .io_in_1_ready(T_11395_io_in_1_ready),
+ .io_in_1_valid(T_11395_io_in_1_valid),
+ .io_in_1_bits_header_src(T_11395_io_in_1_bits_header_src),
+ .io_in_1_bits_header_dst(T_11395_io_in_1_bits_header_dst),
+ .io_in_1_bits_payload_addr_beat(T_11395_io_in_1_bits_payload_addr_beat),
+ .io_in_1_bits_payload_addr_block(T_11395_io_in_1_bits_payload_addr_block),
+ .io_in_1_bits_payload_client_xact_id(T_11395_io_in_1_bits_payload_client_xact_id),
+ .io_in_1_bits_payload_voluntary(T_11395_io_in_1_bits_payload_voluntary),
+ .io_in_1_bits_payload_r_type(T_11395_io_in_1_bits_payload_r_type),
+ .io_in_1_bits_payload_data(T_11395_io_in_1_bits_payload_data),
+ .io_in_2_ready(T_11395_io_in_2_ready),
+ .io_in_2_valid(T_11395_io_in_2_valid),
+ .io_in_2_bits_header_src(T_11395_io_in_2_bits_header_src),
+ .io_in_2_bits_header_dst(T_11395_io_in_2_bits_header_dst),
+ .io_in_2_bits_payload_addr_beat(T_11395_io_in_2_bits_payload_addr_beat),
+ .io_in_2_bits_payload_addr_block(T_11395_io_in_2_bits_payload_addr_block),
+ .io_in_2_bits_payload_client_xact_id(T_11395_io_in_2_bits_payload_client_xact_id),
+ .io_in_2_bits_payload_voluntary(T_11395_io_in_2_bits_payload_voluntary),
+ .io_in_2_bits_payload_r_type(T_11395_io_in_2_bits_payload_r_type),
+ .io_in_2_bits_payload_data(T_11395_io_in_2_bits_payload_data),
+ .io_out_ready(T_11395_io_out_ready),
+ .io_out_valid(T_11395_io_out_valid),
+ .io_out_bits_header_src(T_11395_io_out_bits_header_src),
+ .io_out_bits_header_dst(T_11395_io_out_bits_header_dst),
+ .io_out_bits_payload_addr_beat(T_11395_io_out_bits_payload_addr_beat),
+ .io_out_bits_payload_addr_block(T_11395_io_out_bits_payload_addr_block),
+ .io_out_bits_payload_client_xact_id(T_11395_io_out_bits_payload_client_xact_id),
+ .io_out_bits_payload_voluntary(T_11395_io_out_bits_payload_voluntary),
+ .io_out_bits_payload_r_type(T_11395_io_out_bits_payload_r_type),
+ .io_out_bits_payload_data(T_11395_io_out_bits_payload_data),
+ .io_chosen(T_11395_io_chosen)
+ );
+ RRArbiter T_11396 (
+ .clk(T_11396_clk),
+ .reset(T_11396_reset),
+ .io_in_0_ready(T_11396_io_in_0_ready),
+ .io_in_0_valid(T_11396_io_in_0_valid),
+ .io_in_0_bits_header_src(T_11396_io_in_0_bits_header_src),
+ .io_in_0_bits_header_dst(T_11396_io_in_0_bits_header_dst),
+ .io_in_0_bits_payload_manager_xact_id(T_11396_io_in_0_bits_payload_manager_xact_id),
+ .io_in_1_ready(T_11396_io_in_1_ready),
+ .io_in_1_valid(T_11396_io_in_1_valid),
+ .io_in_1_bits_header_src(T_11396_io_in_1_bits_header_src),
+ .io_in_1_bits_header_dst(T_11396_io_in_1_bits_header_dst),
+ .io_in_1_bits_payload_manager_xact_id(T_11396_io_in_1_bits_payload_manager_xact_id),
+ .io_in_2_ready(T_11396_io_in_2_ready),
+ .io_in_2_valid(T_11396_io_in_2_valid),
+ .io_in_2_bits_header_src(T_11396_io_in_2_bits_header_src),
+ .io_in_2_bits_header_dst(T_11396_io_in_2_bits_header_dst),
+ .io_in_2_bits_payload_manager_xact_id(T_11396_io_in_2_bits_payload_manager_xact_id),
+ .io_out_ready(T_11396_io_out_ready),
+ .io_out_valid(T_11396_io_out_valid),
+ .io_out_bits_header_src(T_11396_io_out_bits_header_src),
+ .io_out_bits_header_dst(T_11396_io_out_bits_header_dst),
+ .io_out_bits_payload_manager_xact_id(T_11396_io_out_bits_payload_manager_xact_id),
+ .io_chosen(T_11396_io_chosen)
+ );
+ assign io_clients_0_acquire_ready = T_11386_io_client_acquire_ready;
+ assign io_clients_0_grant_valid = T_11386_io_client_grant_valid;
+ assign io_clients_0_grant_bits_addr_beat = T_11386_io_client_grant_bits_addr_beat;
+ assign io_clients_0_grant_bits_client_xact_id = T_11386_io_client_grant_bits_client_xact_id;
+ assign io_clients_0_grant_bits_manager_xact_id = T_11386_io_client_grant_bits_manager_xact_id;
+ assign io_clients_0_grant_bits_is_builtin_type = T_11386_io_client_grant_bits_is_builtin_type;
+ assign io_clients_0_grant_bits_g_type = T_11386_io_client_grant_bits_g_type;
+ assign io_clients_0_grant_bits_data = T_11386_io_client_grant_bits_data;
+ assign io_clients_0_probe_valid = T_11386_io_client_probe_valid;
+ assign io_clients_0_probe_bits_addr_block = T_11386_io_client_probe_bits_addr_block;
+ assign io_clients_0_probe_bits_p_type = T_11386_io_client_probe_bits_p_type;
+ assign io_clients_0_release_ready = T_11386_io_client_release_ready;
+ assign io_clients_1_acquire_ready = T_11388_io_client_acquire_ready;
+ assign io_clients_1_grant_valid = T_11388_io_client_grant_valid;
+ assign io_clients_1_grant_bits_addr_beat = T_11388_io_client_grant_bits_addr_beat;
+ assign io_clients_1_grant_bits_client_xact_id = T_11388_io_client_grant_bits_client_xact_id;
+ assign io_clients_1_grant_bits_manager_xact_id = T_11388_io_client_grant_bits_manager_xact_id;
+ assign io_clients_1_grant_bits_is_builtin_type = T_11388_io_client_grant_bits_is_builtin_type;
+ assign io_clients_1_grant_bits_g_type = T_11388_io_client_grant_bits_g_type;
+ assign io_clients_1_grant_bits_data = T_11388_io_client_grant_bits_data;
+ assign io_clients_1_probe_valid = T_11388_io_client_probe_valid;
+ assign io_clients_1_probe_bits_addr_block = T_11388_io_client_probe_bits_addr_block;
+ assign io_clients_1_probe_bits_p_type = T_11388_io_client_probe_bits_p_type;
+ assign io_clients_1_release_ready = T_11388_io_client_release_ready;
+ assign io_clients_2_acquire_ready = T_11390_io_client_acquire_ready;
+ assign io_clients_2_grant_valid = T_11390_io_client_grant_valid;
+ assign io_clients_2_grant_bits_addr_beat = T_11390_io_client_grant_bits_addr_beat;
+ assign io_clients_2_grant_bits_client_xact_id = T_11390_io_client_grant_bits_client_xact_id;
+ assign io_clients_2_grant_bits_manager_xact_id = T_11390_io_client_grant_bits_manager_xact_id;
+ assign io_clients_2_grant_bits_is_builtin_type = T_11390_io_client_grant_bits_is_builtin_type;
+ assign io_clients_2_grant_bits_g_type = T_11390_io_client_grant_bits_g_type;
+ assign io_clients_2_grant_bits_data = T_11390_io_client_grant_bits_data;
+ assign io_clients_2_probe_valid = T_11390_io_client_probe_valid;
+ assign io_clients_2_probe_bits_addr_block = T_11390_io_client_probe_bits_addr_block;
+ assign io_clients_2_probe_bits_p_type = T_11390_io_client_probe_bits_p_type;
+ assign io_clients_2_release_ready = T_11390_io_client_release_ready;
+ assign io_managers_0_acquire_valid = T_11392_io_manager_acquire_valid;
+ assign io_managers_0_acquire_bits_addr_block = T_11392_io_manager_acquire_bits_addr_block;
+ assign io_managers_0_acquire_bits_client_xact_id = T_11392_io_manager_acquire_bits_client_xact_id;
+ assign io_managers_0_acquire_bits_addr_beat = T_11392_io_manager_acquire_bits_addr_beat;
+ assign io_managers_0_acquire_bits_is_builtin_type = T_11392_io_manager_acquire_bits_is_builtin_type;
+ assign io_managers_0_acquire_bits_a_type = T_11392_io_manager_acquire_bits_a_type;
+ assign io_managers_0_acquire_bits_union = T_11392_io_manager_acquire_bits_union;
+ assign io_managers_0_acquire_bits_data = T_11392_io_manager_acquire_bits_data;
+ assign io_managers_0_acquire_bits_client_id = T_11392_io_manager_acquire_bits_client_id;
+ assign io_managers_0_grant_ready = T_11392_io_manager_grant_ready;
+ assign io_managers_0_finish_valid = T_11392_io_manager_finish_valid;
+ assign io_managers_0_finish_bits_manager_xact_id = T_11392_io_manager_finish_bits_manager_xact_id;
+ assign io_managers_0_probe_ready = T_11392_io_manager_probe_ready;
+ assign io_managers_0_release_valid = T_11392_io_manager_release_valid;
+ assign io_managers_0_release_bits_addr_beat = T_11392_io_manager_release_bits_addr_beat;
+ assign io_managers_0_release_bits_addr_block = T_11392_io_manager_release_bits_addr_block;
+ assign io_managers_0_release_bits_client_xact_id = T_11392_io_manager_release_bits_client_xact_id;
+ assign io_managers_0_release_bits_voluntary = T_11392_io_manager_release_bits_voluntary;
+ assign io_managers_0_release_bits_r_type = T_11392_io_manager_release_bits_r_type;
+ assign io_managers_0_release_bits_data = T_11392_io_manager_release_bits_data;
+ assign io_managers_0_release_bits_client_id = T_11392_io_manager_release_bits_client_id;
+ assign T_11386_clk = clk;
+ assign T_11386_reset = reset;
+ assign T_11386_io_client_acquire_valid = io_clients_0_acquire_valid;
+ assign T_11386_io_client_acquire_bits_addr_block = io_clients_0_acquire_bits_addr_block;
+ assign T_11386_io_client_acquire_bits_client_xact_id = io_clients_0_acquire_bits_client_xact_id;
+ assign T_11386_io_client_acquire_bits_addr_beat = io_clients_0_acquire_bits_addr_beat;
+ assign T_11386_io_client_acquire_bits_is_builtin_type = io_clients_0_acquire_bits_is_builtin_type;
+ assign T_11386_io_client_acquire_bits_a_type = io_clients_0_acquire_bits_a_type;
+ assign T_11386_io_client_acquire_bits_union = io_clients_0_acquire_bits_union;
+ assign T_11386_io_client_acquire_bits_data = io_clients_0_acquire_bits_data;
+ assign T_11386_io_client_grant_ready = io_clients_0_grant_ready;
+ assign T_11386_io_client_probe_ready = io_clients_0_probe_ready;
+ assign T_11386_io_client_release_valid = io_clients_0_release_valid;
+ assign T_11386_io_client_release_bits_addr_beat = io_clients_0_release_bits_addr_beat;
+ assign T_11386_io_client_release_bits_addr_block = io_clients_0_release_bits_addr_block;
+ assign T_11386_io_client_release_bits_client_xact_id = io_clients_0_release_bits_client_xact_id;
+ assign T_11386_io_client_release_bits_voluntary = io_clients_0_release_bits_voluntary;
+ assign T_11386_io_client_release_bits_r_type = io_clients_0_release_bits_r_type;
+ assign T_11386_io_client_release_bits_data = io_clients_0_release_bits_data;
+ assign T_11386_io_network_acquire_ready = T_11387_io_client_acquire_ready;
+ assign T_11386_io_network_grant_valid = T_11387_io_client_grant_valid;
+ assign T_11386_io_network_grant_bits_header_src = T_11387_io_client_grant_bits_header_src;
+ assign T_11386_io_network_grant_bits_header_dst = T_11387_io_client_grant_bits_header_dst;
+ assign T_11386_io_network_grant_bits_payload_addr_beat = T_11387_io_client_grant_bits_payload_addr_beat;
+ assign T_11386_io_network_grant_bits_payload_client_xact_id = T_11387_io_client_grant_bits_payload_client_xact_id;
+ assign T_11386_io_network_grant_bits_payload_manager_xact_id = T_11387_io_client_grant_bits_payload_manager_xact_id;
+ assign T_11386_io_network_grant_bits_payload_is_builtin_type = T_11387_io_client_grant_bits_payload_is_builtin_type;
+ assign T_11386_io_network_grant_bits_payload_g_type = T_11387_io_client_grant_bits_payload_g_type;
+ assign T_11386_io_network_grant_bits_payload_data = T_11387_io_client_grant_bits_payload_data;
+ assign T_11386_io_network_finish_ready = T_11387_io_client_finish_ready;
+ assign T_11386_io_network_probe_valid = T_11387_io_client_probe_valid;
+ assign T_11386_io_network_probe_bits_header_src = T_11387_io_client_probe_bits_header_src;
+ assign T_11386_io_network_probe_bits_header_dst = T_11387_io_client_probe_bits_header_dst;
+ assign T_11386_io_network_probe_bits_payload_addr_block = T_11387_io_client_probe_bits_payload_addr_block;
+ assign T_11386_io_network_probe_bits_payload_p_type = T_11387_io_client_probe_bits_payload_p_type;
+ assign T_11386_io_network_release_ready = T_11387_io_client_release_ready;
+ assign T_11387_clk = clk;
+ assign T_11387_reset = reset;
+ assign T_11387_io_client_acquire_valid = T_11386_io_network_acquire_valid;
+ assign T_11387_io_client_acquire_bits_header_src = T_11386_io_network_acquire_bits_header_src;
+ assign T_11387_io_client_acquire_bits_header_dst = T_11386_io_network_acquire_bits_header_dst;
+ assign T_11387_io_client_acquire_bits_payload_addr_block = T_11386_io_network_acquire_bits_payload_addr_block;
+ assign T_11387_io_client_acquire_bits_payload_client_xact_id = T_11386_io_network_acquire_bits_payload_client_xact_id;
+ assign T_11387_io_client_acquire_bits_payload_addr_beat = T_11386_io_network_acquire_bits_payload_addr_beat;
+ assign T_11387_io_client_acquire_bits_payload_is_builtin_type = T_11386_io_network_acquire_bits_payload_is_builtin_type;
+ assign T_11387_io_client_acquire_bits_payload_a_type = T_11386_io_network_acquire_bits_payload_a_type;
+ assign T_11387_io_client_acquire_bits_payload_union = T_11386_io_network_acquire_bits_payload_union;
+ assign T_11387_io_client_acquire_bits_payload_data = T_11386_io_network_acquire_bits_payload_data;
+ assign T_11387_io_client_grant_ready = T_11386_io_network_grant_ready;
+ assign T_11387_io_client_finish_valid = T_11386_io_network_finish_valid;
+ assign T_11387_io_client_finish_bits_header_src = T_11386_io_network_finish_bits_header_src;
+ assign T_11387_io_client_finish_bits_header_dst = T_11386_io_network_finish_bits_header_dst;
+ assign T_11387_io_client_finish_bits_payload_manager_xact_id = T_11386_io_network_finish_bits_payload_manager_xact_id;
+ assign T_11387_io_client_probe_ready = T_11386_io_network_probe_ready;
+ assign T_11387_io_client_release_valid = T_11386_io_network_release_valid;
+ assign T_11387_io_client_release_bits_header_src = T_11386_io_network_release_bits_header_src;
+ assign T_11387_io_client_release_bits_header_dst = T_11386_io_network_release_bits_header_dst;
+ assign T_11387_io_client_release_bits_payload_addr_beat = T_11386_io_network_release_bits_payload_addr_beat;
+ assign T_11387_io_client_release_bits_payload_addr_block = T_11386_io_network_release_bits_payload_addr_block;
+ assign T_11387_io_client_release_bits_payload_client_xact_id = T_11386_io_network_release_bits_payload_client_xact_id;
+ assign T_11387_io_client_release_bits_payload_voluntary = T_11386_io_network_release_bits_payload_voluntary;
+ assign T_11387_io_client_release_bits_payload_r_type = T_11386_io_network_release_bits_payload_r_type;
+ assign T_11387_io_client_release_bits_payload_data = T_11386_io_network_release_bits_payload_data;
+ assign T_11387_io_manager_acquire_ready = T_11394_io_in_0_ready;
+ assign T_11387_io_manager_grant_valid = T_11410 ? T_11393_io_client_grant_valid : 1'h0;
+ assign T_11387_io_manager_grant_bits_header_src = T_11393_io_client_grant_bits_header_src;
+ assign T_11387_io_manager_grant_bits_header_dst = T_11393_io_client_grant_bits_header_dst;
+ assign T_11387_io_manager_grant_bits_payload_addr_beat = T_11393_io_client_grant_bits_payload_addr_beat;
+ assign T_11387_io_manager_grant_bits_payload_client_xact_id = T_11393_io_client_grant_bits_payload_client_xact_id;
+ assign T_11387_io_manager_grant_bits_payload_manager_xact_id = T_11393_io_client_grant_bits_payload_manager_xact_id;
+ assign T_11387_io_manager_grant_bits_payload_is_builtin_type = T_11393_io_client_grant_bits_payload_is_builtin_type;
+ assign T_11387_io_manager_grant_bits_payload_g_type = T_11393_io_client_grant_bits_payload_g_type;
+ assign T_11387_io_manager_grant_bits_payload_data = T_11393_io_client_grant_bits_payload_data;
+ assign T_11387_io_manager_finish_ready = T_11396_io_in_0_ready;
+ assign T_11387_io_manager_probe_valid = T_11400 ? T_11393_io_client_probe_valid : 1'h0;
+ assign T_11387_io_manager_probe_bits_header_src = T_11393_io_client_probe_bits_header_src;
+ assign T_11387_io_manager_probe_bits_header_dst = T_11393_io_client_probe_bits_header_dst;
+ assign T_11387_io_manager_probe_bits_payload_addr_block = T_11393_io_client_probe_bits_payload_addr_block;
+ assign T_11387_io_manager_probe_bits_payload_p_type = T_11393_io_client_probe_bits_payload_p_type;
+ assign T_11387_io_manager_release_ready = T_11395_io_in_0_ready;
+ assign T_11388_clk = clk;
+ assign T_11388_reset = reset;
+ assign T_11388_io_client_acquire_valid = io_clients_1_acquire_valid;
+ assign T_11388_io_client_acquire_bits_addr_block = io_clients_1_acquire_bits_addr_block;
+ assign T_11388_io_client_acquire_bits_client_xact_id = io_clients_1_acquire_bits_client_xact_id;
+ assign T_11388_io_client_acquire_bits_addr_beat = io_clients_1_acquire_bits_addr_beat;
+ assign T_11388_io_client_acquire_bits_is_builtin_type = io_clients_1_acquire_bits_is_builtin_type;
+ assign T_11388_io_client_acquire_bits_a_type = io_clients_1_acquire_bits_a_type;
+ assign T_11388_io_client_acquire_bits_union = io_clients_1_acquire_bits_union;
+ assign T_11388_io_client_acquire_bits_data = io_clients_1_acquire_bits_data;
+ assign T_11388_io_client_grant_ready = io_clients_1_grant_ready;
+ assign T_11388_io_client_probe_ready = io_clients_1_probe_ready;
+ assign T_11388_io_client_release_valid = io_clients_1_release_valid;
+ assign T_11388_io_client_release_bits_addr_beat = io_clients_1_release_bits_addr_beat;
+ assign T_11388_io_client_release_bits_addr_block = io_clients_1_release_bits_addr_block;
+ assign T_11388_io_client_release_bits_client_xact_id = io_clients_1_release_bits_client_xact_id;
+ assign T_11388_io_client_release_bits_voluntary = io_clients_1_release_bits_voluntary;
+ assign T_11388_io_client_release_bits_r_type = io_clients_1_release_bits_r_type;
+ assign T_11388_io_client_release_bits_data = io_clients_1_release_bits_data;
+ assign T_11388_io_network_acquire_ready = T_11389_io_client_acquire_ready;
+ assign T_11388_io_network_grant_valid = T_11389_io_client_grant_valid;
+ assign T_11388_io_network_grant_bits_header_src = T_11389_io_client_grant_bits_header_src;
+ assign T_11388_io_network_grant_bits_header_dst = T_11389_io_client_grant_bits_header_dst;
+ assign T_11388_io_network_grant_bits_payload_addr_beat = T_11389_io_client_grant_bits_payload_addr_beat;
+ assign T_11388_io_network_grant_bits_payload_client_xact_id = T_11389_io_client_grant_bits_payload_client_xact_id;
+ assign T_11388_io_network_grant_bits_payload_manager_xact_id = T_11389_io_client_grant_bits_payload_manager_xact_id;
+ assign T_11388_io_network_grant_bits_payload_is_builtin_type = T_11389_io_client_grant_bits_payload_is_builtin_type;
+ assign T_11388_io_network_grant_bits_payload_g_type = T_11389_io_client_grant_bits_payload_g_type;
+ assign T_11388_io_network_grant_bits_payload_data = T_11389_io_client_grant_bits_payload_data;
+ assign T_11388_io_network_finish_ready = T_11389_io_client_finish_ready;
+ assign T_11388_io_network_probe_valid = T_11389_io_client_probe_valid;
+ assign T_11388_io_network_probe_bits_header_src = T_11389_io_client_probe_bits_header_src;
+ assign T_11388_io_network_probe_bits_header_dst = T_11389_io_client_probe_bits_header_dst;
+ assign T_11388_io_network_probe_bits_payload_addr_block = T_11389_io_client_probe_bits_payload_addr_block;
+ assign T_11388_io_network_probe_bits_payload_p_type = T_11389_io_client_probe_bits_payload_p_type;
+ assign T_11388_io_network_release_ready = T_11389_io_client_release_ready;
+ assign T_11389_clk = clk;
+ assign T_11389_reset = reset;
+ assign T_11389_io_client_acquire_valid = T_11388_io_network_acquire_valid;
+ assign T_11389_io_client_acquire_bits_header_src = T_11388_io_network_acquire_bits_header_src;
+ assign T_11389_io_client_acquire_bits_header_dst = T_11388_io_network_acquire_bits_header_dst;
+ assign T_11389_io_client_acquire_bits_payload_addr_block = T_11388_io_network_acquire_bits_payload_addr_block;
+ assign T_11389_io_client_acquire_bits_payload_client_xact_id = T_11388_io_network_acquire_bits_payload_client_xact_id;
+ assign T_11389_io_client_acquire_bits_payload_addr_beat = T_11388_io_network_acquire_bits_payload_addr_beat;
+ assign T_11389_io_client_acquire_bits_payload_is_builtin_type = T_11388_io_network_acquire_bits_payload_is_builtin_type;
+ assign T_11389_io_client_acquire_bits_payload_a_type = T_11388_io_network_acquire_bits_payload_a_type;
+ assign T_11389_io_client_acquire_bits_payload_union = T_11388_io_network_acquire_bits_payload_union;
+ assign T_11389_io_client_acquire_bits_payload_data = T_11388_io_network_acquire_bits_payload_data;
+ assign T_11389_io_client_grant_ready = T_11388_io_network_grant_ready;
+ assign T_11389_io_client_finish_valid = T_11388_io_network_finish_valid;
+ assign T_11389_io_client_finish_bits_header_src = T_11388_io_network_finish_bits_header_src;
+ assign T_11389_io_client_finish_bits_header_dst = T_11388_io_network_finish_bits_header_dst;
+ assign T_11389_io_client_finish_bits_payload_manager_xact_id = T_11388_io_network_finish_bits_payload_manager_xact_id;
+ assign T_11389_io_client_probe_ready = T_11388_io_network_probe_ready;
+ assign T_11389_io_client_release_valid = T_11388_io_network_release_valid;
+ assign T_11389_io_client_release_bits_header_src = T_11388_io_network_release_bits_header_src;
+ assign T_11389_io_client_release_bits_header_dst = T_11388_io_network_release_bits_header_dst;
+ assign T_11389_io_client_release_bits_payload_addr_beat = T_11388_io_network_release_bits_payload_addr_beat;
+ assign T_11389_io_client_release_bits_payload_addr_block = T_11388_io_network_release_bits_payload_addr_block;
+ assign T_11389_io_client_release_bits_payload_client_xact_id = T_11388_io_network_release_bits_payload_client_xact_id;
+ assign T_11389_io_client_release_bits_payload_voluntary = T_11388_io_network_release_bits_payload_voluntary;
+ assign T_11389_io_client_release_bits_payload_r_type = T_11388_io_network_release_bits_payload_r_type;
+ assign T_11389_io_client_release_bits_payload_data = T_11388_io_network_release_bits_payload_data;
+ assign T_11389_io_manager_acquire_ready = T_11394_io_in_1_ready;
+ assign T_11389_io_manager_grant_valid = T_11413 ? T_11393_io_client_grant_valid : 1'h0;
+ assign T_11389_io_manager_grant_bits_header_src = T_11393_io_client_grant_bits_header_src;
+ assign T_11389_io_manager_grant_bits_header_dst = T_11393_io_client_grant_bits_header_dst;
+ assign T_11389_io_manager_grant_bits_payload_addr_beat = T_11393_io_client_grant_bits_payload_addr_beat;
+ assign T_11389_io_manager_grant_bits_payload_client_xact_id = T_11393_io_client_grant_bits_payload_client_xact_id;
+ assign T_11389_io_manager_grant_bits_payload_manager_xact_id = T_11393_io_client_grant_bits_payload_manager_xact_id;
+ assign T_11389_io_manager_grant_bits_payload_is_builtin_type = T_11393_io_client_grant_bits_payload_is_builtin_type;
+ assign T_11389_io_manager_grant_bits_payload_g_type = T_11393_io_client_grant_bits_payload_g_type;
+ assign T_11389_io_manager_grant_bits_payload_data = T_11393_io_client_grant_bits_payload_data;
+ assign T_11389_io_manager_finish_ready = T_11396_io_in_1_ready;
+ assign T_11389_io_manager_probe_valid = T_11403 ? T_11393_io_client_probe_valid : 1'h0;
+ assign T_11389_io_manager_probe_bits_header_src = T_11393_io_client_probe_bits_header_src;
+ assign T_11389_io_manager_probe_bits_header_dst = T_11393_io_client_probe_bits_header_dst;
+ assign T_11389_io_manager_probe_bits_payload_addr_block = T_11393_io_client_probe_bits_payload_addr_block;
+ assign T_11389_io_manager_probe_bits_payload_p_type = T_11393_io_client_probe_bits_payload_p_type;
+ assign T_11389_io_manager_release_ready = T_11395_io_in_1_ready;
+ assign T_11390_clk = clk;
+ assign T_11390_reset = reset;
+ assign T_11390_io_client_acquire_valid = io_clients_2_acquire_valid;
+ assign T_11390_io_client_acquire_bits_addr_block = io_clients_2_acquire_bits_addr_block;
+ assign T_11390_io_client_acquire_bits_client_xact_id = io_clients_2_acquire_bits_client_xact_id;
+ assign T_11390_io_client_acquire_bits_addr_beat = io_clients_2_acquire_bits_addr_beat;
+ assign T_11390_io_client_acquire_bits_is_builtin_type = io_clients_2_acquire_bits_is_builtin_type;
+ assign T_11390_io_client_acquire_bits_a_type = io_clients_2_acquire_bits_a_type;
+ assign T_11390_io_client_acquire_bits_union = io_clients_2_acquire_bits_union;
+ assign T_11390_io_client_acquire_bits_data = io_clients_2_acquire_bits_data;
+ assign T_11390_io_client_grant_ready = io_clients_2_grant_ready;
+ assign T_11390_io_client_probe_ready = io_clients_2_probe_ready;
+ assign T_11390_io_client_release_valid = io_clients_2_release_valid;
+ assign T_11390_io_client_release_bits_addr_beat = io_clients_2_release_bits_addr_beat;
+ assign T_11390_io_client_release_bits_addr_block = io_clients_2_release_bits_addr_block;
+ assign T_11390_io_client_release_bits_client_xact_id = io_clients_2_release_bits_client_xact_id;
+ assign T_11390_io_client_release_bits_voluntary = io_clients_2_release_bits_voluntary;
+ assign T_11390_io_client_release_bits_r_type = io_clients_2_release_bits_r_type;
+ assign T_11390_io_client_release_bits_data = io_clients_2_release_bits_data;
+ assign T_11390_io_network_acquire_ready = T_11391_io_client_acquire_ready;
+ assign T_11390_io_network_grant_valid = T_11391_io_client_grant_valid;
+ assign T_11390_io_network_grant_bits_header_src = T_11391_io_client_grant_bits_header_src;
+ assign T_11390_io_network_grant_bits_header_dst = T_11391_io_client_grant_bits_header_dst;
+ assign T_11390_io_network_grant_bits_payload_addr_beat = T_11391_io_client_grant_bits_payload_addr_beat;
+ assign T_11390_io_network_grant_bits_payload_client_xact_id = T_11391_io_client_grant_bits_payload_client_xact_id;
+ assign T_11390_io_network_grant_bits_payload_manager_xact_id = T_11391_io_client_grant_bits_payload_manager_xact_id;
+ assign T_11390_io_network_grant_bits_payload_is_builtin_type = T_11391_io_client_grant_bits_payload_is_builtin_type;
+ assign T_11390_io_network_grant_bits_payload_g_type = T_11391_io_client_grant_bits_payload_g_type;
+ assign T_11390_io_network_grant_bits_payload_data = T_11391_io_client_grant_bits_payload_data;
+ assign T_11390_io_network_finish_ready = T_11391_io_client_finish_ready;
+ assign T_11390_io_network_probe_valid = T_11391_io_client_probe_valid;
+ assign T_11390_io_network_probe_bits_header_src = T_11391_io_client_probe_bits_header_src;
+ assign T_11390_io_network_probe_bits_header_dst = T_11391_io_client_probe_bits_header_dst;
+ assign T_11390_io_network_probe_bits_payload_addr_block = T_11391_io_client_probe_bits_payload_addr_block;
+ assign T_11390_io_network_probe_bits_payload_p_type = T_11391_io_client_probe_bits_payload_p_type;
+ assign T_11390_io_network_release_ready = T_11391_io_client_release_ready;
+ assign T_11391_clk = clk;
+ assign T_11391_reset = reset;
+ assign T_11391_io_client_acquire_valid = T_11390_io_network_acquire_valid;
+ assign T_11391_io_client_acquire_bits_header_src = T_11390_io_network_acquire_bits_header_src;
+ assign T_11391_io_client_acquire_bits_header_dst = T_11390_io_network_acquire_bits_header_dst;
+ assign T_11391_io_client_acquire_bits_payload_addr_block = T_11390_io_network_acquire_bits_payload_addr_block;
+ assign T_11391_io_client_acquire_bits_payload_client_xact_id = T_11390_io_network_acquire_bits_payload_client_xact_id;
+ assign T_11391_io_client_acquire_bits_payload_addr_beat = T_11390_io_network_acquire_bits_payload_addr_beat;
+ assign T_11391_io_client_acquire_bits_payload_is_builtin_type = T_11390_io_network_acquire_bits_payload_is_builtin_type;
+ assign T_11391_io_client_acquire_bits_payload_a_type = T_11390_io_network_acquire_bits_payload_a_type;
+ assign T_11391_io_client_acquire_bits_payload_union = T_11390_io_network_acquire_bits_payload_union;
+ assign T_11391_io_client_acquire_bits_payload_data = T_11390_io_network_acquire_bits_payload_data;
+ assign T_11391_io_client_grant_ready = T_11390_io_network_grant_ready;
+ assign T_11391_io_client_finish_valid = T_11390_io_network_finish_valid;
+ assign T_11391_io_client_finish_bits_header_src = T_11390_io_network_finish_bits_header_src;
+ assign T_11391_io_client_finish_bits_header_dst = T_11390_io_network_finish_bits_header_dst;
+ assign T_11391_io_client_finish_bits_payload_manager_xact_id = T_11390_io_network_finish_bits_payload_manager_xact_id;
+ assign T_11391_io_client_probe_ready = T_11390_io_network_probe_ready;
+ assign T_11391_io_client_release_valid = T_11390_io_network_release_valid;
+ assign T_11391_io_client_release_bits_header_src = T_11390_io_network_release_bits_header_src;
+ assign T_11391_io_client_release_bits_header_dst = T_11390_io_network_release_bits_header_dst;
+ assign T_11391_io_client_release_bits_payload_addr_beat = T_11390_io_network_release_bits_payload_addr_beat;
+ assign T_11391_io_client_release_bits_payload_addr_block = T_11390_io_network_release_bits_payload_addr_block;
+ assign T_11391_io_client_release_bits_payload_client_xact_id = T_11390_io_network_release_bits_payload_client_xact_id;
+ assign T_11391_io_client_release_bits_payload_voluntary = T_11390_io_network_release_bits_payload_voluntary;
+ assign T_11391_io_client_release_bits_payload_r_type = T_11390_io_network_release_bits_payload_r_type;
+ assign T_11391_io_client_release_bits_payload_data = T_11390_io_network_release_bits_payload_data;
+ assign T_11391_io_manager_acquire_ready = T_11394_io_in_2_ready;
+ assign T_11391_io_manager_grant_valid = T_11416 ? T_11393_io_client_grant_valid : 1'h0;
+ assign T_11391_io_manager_grant_bits_header_src = T_11393_io_client_grant_bits_header_src;
+ assign T_11391_io_manager_grant_bits_header_dst = T_11393_io_client_grant_bits_header_dst;
+ assign T_11391_io_manager_grant_bits_payload_addr_beat = T_11393_io_client_grant_bits_payload_addr_beat;
+ assign T_11391_io_manager_grant_bits_payload_client_xact_id = T_11393_io_client_grant_bits_payload_client_xact_id;
+ assign T_11391_io_manager_grant_bits_payload_manager_xact_id = T_11393_io_client_grant_bits_payload_manager_xact_id;
+ assign T_11391_io_manager_grant_bits_payload_is_builtin_type = T_11393_io_client_grant_bits_payload_is_builtin_type;
+ assign T_11391_io_manager_grant_bits_payload_g_type = T_11393_io_client_grant_bits_payload_g_type;
+ assign T_11391_io_manager_grant_bits_payload_data = T_11393_io_client_grant_bits_payload_data;
+ assign T_11391_io_manager_finish_ready = T_11396_io_in_2_ready;
+ assign T_11391_io_manager_probe_valid = T_11406 ? T_11393_io_client_probe_valid : 1'h0;
+ assign T_11391_io_manager_probe_bits_header_src = T_11393_io_client_probe_bits_header_src;
+ assign T_11391_io_manager_probe_bits_header_dst = T_11393_io_client_probe_bits_header_dst;
+ assign T_11391_io_manager_probe_bits_payload_addr_block = T_11393_io_client_probe_bits_payload_addr_block;
+ assign T_11391_io_manager_probe_bits_payload_p_type = T_11393_io_client_probe_bits_payload_p_type;
+ assign T_11391_io_manager_release_ready = T_11395_io_in_2_ready;
+ assign T_11392_clk = clk;
+ assign T_11392_reset = reset;
+ assign T_11392_io_manager_acquire_ready = io_managers_0_acquire_ready;
+ assign T_11392_io_manager_grant_valid = io_managers_0_grant_valid;
+ assign T_11392_io_manager_grant_bits_addr_beat = io_managers_0_grant_bits_addr_beat;
+ assign T_11392_io_manager_grant_bits_client_xact_id = io_managers_0_grant_bits_client_xact_id;
+ assign T_11392_io_manager_grant_bits_manager_xact_id = io_managers_0_grant_bits_manager_xact_id;
+ assign T_11392_io_manager_grant_bits_is_builtin_type = io_managers_0_grant_bits_is_builtin_type;
+ assign T_11392_io_manager_grant_bits_g_type = io_managers_0_grant_bits_g_type;
+ assign T_11392_io_manager_grant_bits_data = io_managers_0_grant_bits_data;
+ assign T_11392_io_manager_grant_bits_client_id = io_managers_0_grant_bits_client_id;
+ assign T_11392_io_manager_finish_ready = io_managers_0_finish_ready;
+ assign T_11392_io_manager_probe_valid = io_managers_0_probe_valid;
+ assign T_11392_io_manager_probe_bits_addr_block = io_managers_0_probe_bits_addr_block;
+ assign T_11392_io_manager_probe_bits_p_type = io_managers_0_probe_bits_p_type;
+ assign T_11392_io_manager_probe_bits_client_id = io_managers_0_probe_bits_client_id;
+ assign T_11392_io_manager_release_ready = io_managers_0_release_ready;
+ assign T_11392_io_network_acquire_valid = T_11393_io_manager_acquire_valid;
+ assign T_11392_io_network_acquire_bits_header_src = T_11393_io_manager_acquire_bits_header_src;
+ assign T_11392_io_network_acquire_bits_header_dst = T_11393_io_manager_acquire_bits_header_dst;
+ assign T_11392_io_network_acquire_bits_payload_addr_block = T_11393_io_manager_acquire_bits_payload_addr_block;
+ assign T_11392_io_network_acquire_bits_payload_client_xact_id = T_11393_io_manager_acquire_bits_payload_client_xact_id;
+ assign T_11392_io_network_acquire_bits_payload_addr_beat = T_11393_io_manager_acquire_bits_payload_addr_beat;
+ assign T_11392_io_network_acquire_bits_payload_is_builtin_type = T_11393_io_manager_acquire_bits_payload_is_builtin_type;
+ assign T_11392_io_network_acquire_bits_payload_a_type = T_11393_io_manager_acquire_bits_payload_a_type;
+ assign T_11392_io_network_acquire_bits_payload_union = T_11393_io_manager_acquire_bits_payload_union;
+ assign T_11392_io_network_acquire_bits_payload_data = T_11393_io_manager_acquire_bits_payload_data;
+ assign T_11392_io_network_grant_ready = T_11393_io_manager_grant_ready;
+ assign T_11392_io_network_finish_valid = T_11393_io_manager_finish_valid;
+ assign T_11392_io_network_finish_bits_header_src = T_11393_io_manager_finish_bits_header_src;
+ assign T_11392_io_network_finish_bits_header_dst = T_11393_io_manager_finish_bits_header_dst;
+ assign T_11392_io_network_finish_bits_payload_manager_xact_id = T_11393_io_manager_finish_bits_payload_manager_xact_id;
+ assign T_11392_io_network_probe_ready = T_11393_io_manager_probe_ready;
+ assign T_11392_io_network_release_valid = T_11393_io_manager_release_valid;
+ assign T_11392_io_network_release_bits_header_src = T_11393_io_manager_release_bits_header_src;
+ assign T_11392_io_network_release_bits_header_dst = T_11393_io_manager_release_bits_header_dst;
+ assign T_11392_io_network_release_bits_payload_addr_beat = T_11393_io_manager_release_bits_payload_addr_beat;
+ assign T_11392_io_network_release_bits_payload_addr_block = T_11393_io_manager_release_bits_payload_addr_block;
+ assign T_11392_io_network_release_bits_payload_client_xact_id = T_11393_io_manager_release_bits_payload_client_xact_id;
+ assign T_11392_io_network_release_bits_payload_voluntary = T_11393_io_manager_release_bits_payload_voluntary;
+ assign T_11392_io_network_release_bits_payload_r_type = T_11393_io_manager_release_bits_payload_r_type;
+ assign T_11392_io_network_release_bits_payload_data = T_11393_io_manager_release_bits_payload_data;
+ assign T_11393_clk = clk;
+ assign T_11393_reset = reset;
+ assign T_11393_io_client_acquire_valid = T_11394_io_out_valid;
+ assign T_11393_io_client_acquire_bits_header_src = T_11394_io_out_bits_header_src;
+ assign T_11393_io_client_acquire_bits_header_dst = T_11394_io_out_bits_header_dst;
+ assign T_11393_io_client_acquire_bits_payload_addr_block = T_11394_io_out_bits_payload_addr_block;
+ assign T_11393_io_client_acquire_bits_payload_client_xact_id = T_11394_io_out_bits_payload_client_xact_id;
+ assign T_11393_io_client_acquire_bits_payload_addr_beat = T_11394_io_out_bits_payload_addr_beat;
+ assign T_11393_io_client_acquire_bits_payload_is_builtin_type = T_11394_io_out_bits_payload_is_builtin_type;
+ assign T_11393_io_client_acquire_bits_payload_a_type = T_11394_io_out_bits_payload_a_type;
+ assign T_11393_io_client_acquire_bits_payload_union = T_11394_io_out_bits_payload_union;
+ assign T_11393_io_client_acquire_bits_payload_data = T_11394_io_out_bits_payload_data;
+ assign T_11393_io_client_grant_ready = T_11416 ? T_11391_io_manager_grant_ready : T_11413 ? T_11389_io_manager_grant_ready : T_11410 ? T_11387_io_manager_grant_ready : 1'h0;
+ assign T_11393_io_client_finish_valid = T_11396_io_out_valid;
+ assign T_11393_io_client_finish_bits_header_src = T_11396_io_out_bits_header_src;
+ assign T_11393_io_client_finish_bits_header_dst = T_11396_io_out_bits_header_dst;
+ assign T_11393_io_client_finish_bits_payload_manager_xact_id = T_11396_io_out_bits_payload_manager_xact_id;
+ assign T_11393_io_client_probe_ready = T_11406 ? T_11391_io_manager_probe_ready : T_11403 ? T_11389_io_manager_probe_ready : T_11400 ? T_11387_io_manager_probe_ready : 1'h0;
+ assign T_11393_io_client_release_valid = T_11395_io_out_valid;
+ assign T_11393_io_client_release_bits_header_src = T_11395_io_out_bits_header_src;
+ assign T_11393_io_client_release_bits_header_dst = T_11395_io_out_bits_header_dst;
+ assign T_11393_io_client_release_bits_payload_addr_beat = T_11395_io_out_bits_payload_addr_beat;
+ assign T_11393_io_client_release_bits_payload_addr_block = T_11395_io_out_bits_payload_addr_block;
+ assign T_11393_io_client_release_bits_payload_client_xact_id = T_11395_io_out_bits_payload_client_xact_id;
+ assign T_11393_io_client_release_bits_payload_voluntary = T_11395_io_out_bits_payload_voluntary;
+ assign T_11393_io_client_release_bits_payload_r_type = T_11395_io_out_bits_payload_r_type;
+ assign T_11393_io_client_release_bits_payload_data = T_11395_io_out_bits_payload_data;
+ assign T_11393_io_manager_acquire_ready = T_11392_io_network_acquire_ready;
+ assign T_11393_io_manager_grant_valid = T_11392_io_network_grant_valid;
+ assign T_11393_io_manager_grant_bits_header_src = T_11392_io_network_grant_bits_header_src;
+ assign T_11393_io_manager_grant_bits_header_dst = T_11392_io_network_grant_bits_header_dst;
+ assign T_11393_io_manager_grant_bits_payload_addr_beat = T_11392_io_network_grant_bits_payload_addr_beat;
+ assign T_11393_io_manager_grant_bits_payload_client_xact_id = T_11392_io_network_grant_bits_payload_client_xact_id;
+ assign T_11393_io_manager_grant_bits_payload_manager_xact_id = T_11392_io_network_grant_bits_payload_manager_xact_id;
+ assign T_11393_io_manager_grant_bits_payload_is_builtin_type = T_11392_io_network_grant_bits_payload_is_builtin_type;
+ assign T_11393_io_manager_grant_bits_payload_g_type = T_11392_io_network_grant_bits_payload_g_type;
+ assign T_11393_io_manager_grant_bits_payload_data = T_11392_io_network_grant_bits_payload_data;
+ assign T_11393_io_manager_finish_ready = T_11392_io_network_finish_ready;
+ assign T_11393_io_manager_probe_valid = T_11392_io_network_probe_valid;
+ assign T_11393_io_manager_probe_bits_header_src = T_11392_io_network_probe_bits_header_src;
+ assign T_11393_io_manager_probe_bits_header_dst = T_11392_io_network_probe_bits_header_dst;
+ assign T_11393_io_manager_probe_bits_payload_addr_block = T_11392_io_network_probe_bits_payload_addr_block;
+ assign T_11393_io_manager_probe_bits_payload_p_type = T_11392_io_network_probe_bits_payload_p_type;
+ assign T_11393_io_manager_release_ready = T_11392_io_network_release_ready;
+ assign T_11394_clk = clk;
+ assign T_11394_reset = reset;
+ assign T_11394_io_in_0_valid = T_11387_io_manager_acquire_valid;
+ assign T_11394_io_in_0_bits_header_src = T_11387_io_manager_acquire_bits_header_src;
+ assign T_11394_io_in_0_bits_header_dst = T_11387_io_manager_acquire_bits_header_dst;
+ assign T_11394_io_in_0_bits_payload_addr_block = T_11387_io_manager_acquire_bits_payload_addr_block;
+ assign T_11394_io_in_0_bits_payload_client_xact_id = T_11387_io_manager_acquire_bits_payload_client_xact_id;
+ assign T_11394_io_in_0_bits_payload_addr_beat = T_11387_io_manager_acquire_bits_payload_addr_beat;
+ assign T_11394_io_in_0_bits_payload_is_builtin_type = T_11387_io_manager_acquire_bits_payload_is_builtin_type;
+ assign T_11394_io_in_0_bits_payload_a_type = T_11387_io_manager_acquire_bits_payload_a_type;
+ assign T_11394_io_in_0_bits_payload_union = T_11387_io_manager_acquire_bits_payload_union;
+ assign T_11394_io_in_0_bits_payload_data = T_11387_io_manager_acquire_bits_payload_data;
+ assign T_11394_io_in_1_valid = T_11389_io_manager_acquire_valid;
+ assign T_11394_io_in_1_bits_header_src = T_11389_io_manager_acquire_bits_header_src;
+ assign T_11394_io_in_1_bits_header_dst = T_11389_io_manager_acquire_bits_header_dst;
+ assign T_11394_io_in_1_bits_payload_addr_block = T_11389_io_manager_acquire_bits_payload_addr_block;
+ assign T_11394_io_in_1_bits_payload_client_xact_id = T_11389_io_manager_acquire_bits_payload_client_xact_id;
+ assign T_11394_io_in_1_bits_payload_addr_beat = T_11389_io_manager_acquire_bits_payload_addr_beat;
+ assign T_11394_io_in_1_bits_payload_is_builtin_type = T_11389_io_manager_acquire_bits_payload_is_builtin_type;
+ assign T_11394_io_in_1_bits_payload_a_type = T_11389_io_manager_acquire_bits_payload_a_type;
+ assign T_11394_io_in_1_bits_payload_union = T_11389_io_manager_acquire_bits_payload_union;
+ assign T_11394_io_in_1_bits_payload_data = T_11389_io_manager_acquire_bits_payload_data;
+ assign T_11394_io_in_2_valid = T_11391_io_manager_acquire_valid;
+ assign T_11394_io_in_2_bits_header_src = T_11391_io_manager_acquire_bits_header_src;
+ assign T_11394_io_in_2_bits_header_dst = T_11391_io_manager_acquire_bits_header_dst;
+ assign T_11394_io_in_2_bits_payload_addr_block = T_11391_io_manager_acquire_bits_payload_addr_block;
+ assign T_11394_io_in_2_bits_payload_client_xact_id = T_11391_io_manager_acquire_bits_payload_client_xact_id;
+ assign T_11394_io_in_2_bits_payload_addr_beat = T_11391_io_manager_acquire_bits_payload_addr_beat;
+ assign T_11394_io_in_2_bits_payload_is_builtin_type = T_11391_io_manager_acquire_bits_payload_is_builtin_type;
+ assign T_11394_io_in_2_bits_payload_a_type = T_11391_io_manager_acquire_bits_payload_a_type;
+ assign T_11394_io_in_2_bits_payload_union = T_11391_io_manager_acquire_bits_payload_union;
+ assign T_11394_io_in_2_bits_payload_data = T_11391_io_manager_acquire_bits_payload_data;
+ assign T_11394_io_out_ready = T_11393_io_client_acquire_ready;
+ assign T_11395_clk = clk;
+ assign T_11395_reset = reset;
+ assign T_11395_io_in_0_valid = T_11387_io_manager_release_valid;
+ assign T_11395_io_in_0_bits_header_src = T_11387_io_manager_release_bits_header_src;
+ assign T_11395_io_in_0_bits_header_dst = T_11387_io_manager_release_bits_header_dst;
+ assign T_11395_io_in_0_bits_payload_addr_beat = T_11387_io_manager_release_bits_payload_addr_beat;
+ assign T_11395_io_in_0_bits_payload_addr_block = T_11387_io_manager_release_bits_payload_addr_block;
+ assign T_11395_io_in_0_bits_payload_client_xact_id = T_11387_io_manager_release_bits_payload_client_xact_id;
+ assign T_11395_io_in_0_bits_payload_voluntary = T_11387_io_manager_release_bits_payload_voluntary;
+ assign T_11395_io_in_0_bits_payload_r_type = T_11387_io_manager_release_bits_payload_r_type;
+ assign T_11395_io_in_0_bits_payload_data = T_11387_io_manager_release_bits_payload_data;
+ assign T_11395_io_in_1_valid = T_11389_io_manager_release_valid;
+ assign T_11395_io_in_1_bits_header_src = T_11389_io_manager_release_bits_header_src;
+ assign T_11395_io_in_1_bits_header_dst = T_11389_io_manager_release_bits_header_dst;
+ assign T_11395_io_in_1_bits_payload_addr_beat = T_11389_io_manager_release_bits_payload_addr_beat;
+ assign T_11395_io_in_1_bits_payload_addr_block = T_11389_io_manager_release_bits_payload_addr_block;
+ assign T_11395_io_in_1_bits_payload_client_xact_id = T_11389_io_manager_release_bits_payload_client_xact_id;
+ assign T_11395_io_in_1_bits_payload_voluntary = T_11389_io_manager_release_bits_payload_voluntary;
+ assign T_11395_io_in_1_bits_payload_r_type = T_11389_io_manager_release_bits_payload_r_type;
+ assign T_11395_io_in_1_bits_payload_data = T_11389_io_manager_release_bits_payload_data;
+ assign T_11395_io_in_2_valid = T_11391_io_manager_release_valid;
+ assign T_11395_io_in_2_bits_header_src = T_11391_io_manager_release_bits_header_src;
+ assign T_11395_io_in_2_bits_header_dst = T_11391_io_manager_release_bits_header_dst;
+ assign T_11395_io_in_2_bits_payload_addr_beat = T_11391_io_manager_release_bits_payload_addr_beat;
+ assign T_11395_io_in_2_bits_payload_addr_block = T_11391_io_manager_release_bits_payload_addr_block;
+ assign T_11395_io_in_2_bits_payload_client_xact_id = T_11391_io_manager_release_bits_payload_client_xact_id;
+ assign T_11395_io_in_2_bits_payload_voluntary = T_11391_io_manager_release_bits_payload_voluntary;
+ assign T_11395_io_in_2_bits_payload_r_type = T_11391_io_manager_release_bits_payload_r_type;
+ assign T_11395_io_in_2_bits_payload_data = T_11391_io_manager_release_bits_payload_data;
+ assign T_11395_io_out_ready = T_11393_io_client_release_ready;
+ assign T_11396_clk = clk;
+ assign T_11396_reset = reset;
+ assign T_11396_io_in_0_valid = T_11387_io_manager_finish_valid;
+ assign T_11396_io_in_0_bits_header_src = T_11387_io_manager_finish_bits_header_src;
+ assign T_11396_io_in_0_bits_header_dst = T_11387_io_manager_finish_bits_header_dst;
+ assign T_11396_io_in_0_bits_payload_manager_xact_id = T_11387_io_manager_finish_bits_payload_manager_xact_id;
+ assign T_11396_io_in_1_valid = T_11389_io_manager_finish_valid;
+ assign T_11396_io_in_1_bits_header_src = T_11389_io_manager_finish_bits_header_src;
+ assign T_11396_io_in_1_bits_header_dst = T_11389_io_manager_finish_bits_header_dst;
+ assign T_11396_io_in_1_bits_payload_manager_xact_id = T_11389_io_manager_finish_bits_payload_manager_xact_id;
+ assign T_11396_io_in_2_valid = T_11391_io_manager_finish_valid;
+ assign T_11396_io_in_2_bits_header_src = T_11391_io_manager_finish_bits_header_src;
+ assign T_11396_io_in_2_bits_header_dst = T_11391_io_manager_finish_bits_header_dst;
+ assign T_11396_io_in_2_bits_payload_manager_xact_id = T_11391_io_manager_finish_bits_payload_manager_xact_id;
+ assign T_11396_io_out_ready = T_11393_io_client_finish_ready;
+ assign T_11400 = T_11393_io_client_probe_bits_header_dst == 1'h0;
+ assign T_11403 = T_11393_io_client_probe_bits_header_dst == 1'h1;
+ assign T_11406 = T_11393_io_client_probe_bits_header_dst == 2'h2;
+ assign T_11410 = T_11393_io_client_grant_bits_header_dst == 1'h0;
+ assign T_11413 = T_11393_io_client_grant_bits_header_dst == 1'h1;
+ assign T_11416 = T_11393_io_client_grant_bits_header_dst == 2'h2;
+endmodule
+module BroadcastVoluntaryReleaseTracker(
+ input clk,
+ input reset,
+ output io_inner_acquire_ready,
+ input io_inner_acquire_valid,
+ input [25:0] io_inner_acquire_bits_addr_block,
+ input [1:0] io_inner_acquire_bits_client_xact_id,
+ input [1:0] io_inner_acquire_bits_addr_beat,
+ input io_inner_acquire_bits_is_builtin_type,
+ input [2:0] io_inner_acquire_bits_a_type,
+ input [16:0] io_inner_acquire_bits_union,
+ input [3:0] io_inner_acquire_bits_data,
+ input [1:0] io_inner_acquire_bits_client_id,
+ input io_inner_grant_ready,
+ output io_inner_grant_valid,
+ output [1:0] io_inner_grant_bits_addr_beat,
+ output [1:0] io_inner_grant_bits_client_xact_id,
+ output [3:0] io_inner_grant_bits_manager_xact_id,
+ output io_inner_grant_bits_is_builtin_type,
+ output [3:0] io_inner_grant_bits_g_type,
+ output [3:0] io_inner_grant_bits_data,
+ output [1:0] io_inner_grant_bits_client_id,
+ output io_inner_finish_ready,
+ input io_inner_finish_valid,
+ input [3:0] io_inner_finish_bits_manager_xact_id,
+ input io_inner_probe_ready,
+ output io_inner_probe_valid,
+ output [25:0] io_inner_probe_bits_addr_block,
+ output [1:0] io_inner_probe_bits_p_type,
+ output [1:0] io_inner_probe_bits_client_id,
+ output io_inner_release_ready,
+ input io_inner_release_valid,
+ input [1:0] io_inner_release_bits_addr_beat,
+ input [25:0] io_inner_release_bits_addr_block,
+ input [1:0] io_inner_release_bits_client_xact_id,
+ input io_inner_release_bits_voluntary,
+ input [2:0] io_inner_release_bits_r_type,
+ input [3:0] io_inner_release_bits_data,
+ input [1:0] io_inner_release_bits_client_id,
+ input io_incoherent_0,
+ input io_outer_acquire_ready,
+ output io_outer_acquire_valid,
+ output [25:0] io_outer_acquire_bits_addr_block,
+ output [3:0] io_outer_acquire_bits_client_xact_id,
+ output [1:0] io_outer_acquire_bits_addr_beat,
+ output io_outer_acquire_bits_is_builtin_type,
+ output [2:0] io_outer_acquire_bits_a_type,
+ output [16:0] io_outer_acquire_bits_union,
+ output [3:0] io_outer_acquire_bits_data,
+ output io_outer_grant_ready,
+ input io_outer_grant_valid,
+ input [1:0] io_outer_grant_bits_addr_beat,
+ input [3:0] io_outer_grant_bits_client_xact_id,
+ input io_outer_grant_bits_manager_xact_id,
+ input io_outer_grant_bits_is_builtin_type,
+ input [3:0] io_outer_grant_bits_g_type,
+ input [3:0] io_outer_grant_bits_data,
+ output io_has_acquire_conflict,
+ output io_has_acquire_match,
+ output io_has_release_match
+);
+ reg [1:0] state;
+ reg [1:0] xact_addr_beat;
+ reg [25:0] xact_addr_block;
+ reg [1:0] xact_client_xact_id;
+ reg xact_voluntary;
+ reg [2:0] xact_r_type;
+ reg [3:0] xact_data_buffer_0;
+ reg [3:0] xact_data_buffer_1;
+ reg [3:0] xact_data_buffer_2;
+ reg [3:0] xact_data_buffer_3;
+ reg [15:0] xact_wmask_buffer_0;
+ reg [15:0] xact_wmask_buffer_1;
+ reg [15:0] xact_wmask_buffer_2;
+ reg [15:0] xact_wmask_buffer_3;
+ reg [1:0] xact_client_id;
+ wire coh_sharers;
+ reg collect_irel_data;
+ reg [3:0] irel_data_valid;
+ wire T_302;
+ wire [1:0] T_306_0;
+ wire [1:0] T_306_1;
+ wire [1:0] T_306_2;
+ wire T_311;
+ wire T_312;
+ wire T_313;
+ wire T_315;
+ wire T_316;
+ wire T_317;
+ wire T_318;
+ wire T_319;
+ reg [1:0] T_321;
+ wire T_323;
+ wire T_325;
+ wire [2:0] T_328;
+ wire [1:0] T_329;
+ wire [1:0] T_330;
+ wire T_331;
+ wire [1:0] T_332;
+ wire irel_data_done;
+ wire T_335;
+ wire T_337;
+ wire [2:0] T_340_0;
+ wire T_343;
+ wire T_345;
+ wire T_346;
+ wire T_347;
+ reg [1:0] T_349;
+ wire T_351;
+ wire T_353;
+ wire [2:0] T_356;
+ wire [1:0] T_357;
+ wire [1:0] T_358;
+ wire T_359;
+ wire [1:0] oacq_data_cnt;
+ wire oacq_data_done;
+ wire [1:0] T_384_addr_beat;
+ wire [1:0] T_384_client_xact_id;
+ wire [3:0] T_384_manager_xact_id;
+ wire T_384_is_builtin_type;
+ wire [3:0] T_384_g_type;
+ wire [3:0] T_384_data;
+ wire [1:0] T_384_client_id;
+ wire [15:0] GEN_3;
+ wire [15:0] T_397;
+ wire [3:0] T_403;
+ wire [1:0] T_404;
+ wire [5:0] T_405;
+ wire [1:0] T_407;
+ wire [4:0] T_408;
+ wire [16:0] T_410;
+ wire [16:0] T_412;
+ wire [3:0] T_414;
+ wire [1:0] T_415;
+ wire [5:0] T_416;
+ wire [5:0] T_418;
+ wire [5:0] T_420;
+ wire T_421;
+ wire [5:0] T_422;
+ wire T_423;
+ wire [5:0] T_424;
+ wire T_425;
+ wire [5:0] T_426;
+ wire T_427;
+ wire [16:0] T_428;
+ wire T_429;
+ wire [16:0] T_430;
+ wire T_431;
+ wire [16:0] T_432;
+ wire T_433;
+ wire [16:0] T_434;
+ wire [25:0] T_443_addr_block;
+ wire [1:0] T_443_client_xact_id;
+ wire [1:0] T_443_addr_beat;
+ wire T_443_is_builtin_type;
+ wire [2:0] T_443_a_type;
+ wire [16:0] T_443_union;
+ wire [3:0] T_443_data;
+ wire [3:0] GEN_0;
+ wire [3:0] GEN_1;
+ wire [3:0] T_455;
+ wire [3:0] T_456;
+ wire [3:0] T_457;
+ wire [3:0] T_458;
+ wire [3:0] T_459;
+ wire [3:0] T_460;
+ wire T_462;
+ wire [3:0] GEN_2;
+ wire [1:0] T_468_0;
+ wire [1:0] T_468_1;
+ wire [1:0] T_468_2;
+ wire T_473;
+ wire T_474;
+ wire T_475;
+ wire T_477;
+ wire T_478;
+ wire T_479;
+ wire T_480;
+ wire [1:0] T_482_0;
+ wire [1:0] T_482_1;
+ wire [1:0] T_482_2;
+ wire T_487;
+ wire T_488;
+ wire T_489;
+ wire T_491;
+ wire T_492;
+ wire T_493;
+ wire [3:0] T_494;
+ wire [1:0] T_496_0;
+ wire [1:0] T_496_1;
+ wire [1:0] T_496_2;
+ wire T_501;
+ wire T_502;
+ wire T_503;
+ wire T_505;
+ wire T_506;
+ wire T_507;
+ wire T_510;
+ wire [1:0] T_511;
+ wire [1:0] T_512;
+ wire T_513;
+ wire T_515;
+ wire [3:0] T_516;
+ wire T_517;
+ wire T_518;
+ wire T_519;
+ wire T_520;
+ wire T_523;
+ wire T_525;
+ wire T_526;
+ wire T_528;
+ wire T_529;
+ wire [1:0] T_530;
+ wire T_531;
+ wire GEN_4;
+ wire GEN_5;
+ wire GEN_6;
+ wire GEN_7;
+ wire GEN_8;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ wire GEN_17;
+ wire GEN_18;
+ wire GEN_19;
+ wire GEN_20;
+ wire GEN_21;
+ wire GEN_22;
+ reg [25:0] GEN_23;
+ reg [1:0] GEN_24;
+ reg [1:0] GEN_25;
+ assign io_inner_acquire_ready = 1'h0;
+ assign io_inner_grant_valid = T_519 ? io_outer_grant_valid : 1'h0;
+ assign io_inner_grant_bits_addr_beat = T_384_addr_beat;
+ assign io_inner_grant_bits_client_xact_id = T_384_client_xact_id;
+ assign io_inner_grant_bits_manager_xact_id = T_384_manager_xact_id;
+ assign io_inner_grant_bits_is_builtin_type = T_384_is_builtin_type;
+ assign io_inner_grant_bits_g_type = T_384_g_type;
+ assign io_inner_grant_bits_data = T_384_data;
+ assign io_inner_grant_bits_client_id = T_384_client_id;
+ assign io_inner_finish_ready = T_531 ? 1'h1 : 1'h0;
+ assign io_inner_probe_valid = 1'h0;
+ assign io_inner_probe_bits_addr_block = GEN_23;
+ assign io_inner_probe_bits_p_type = GEN_24;
+ assign io_inner_probe_bits_client_id = GEN_25;
+ assign io_inner_release_ready = T_462 ? 1'h1 : collect_irel_data ? 1'h1 : 1'h0;
+ assign io_outer_acquire_valid = T_513 ? T_518 : 1'h0;
+ assign io_outer_acquire_bits_addr_block = T_443_addr_block;
+ assign io_outer_acquire_bits_client_xact_id = T_443_client_xact_id;
+ assign io_outer_acquire_bits_addr_beat = T_443_addr_beat;
+ assign io_outer_acquire_bits_is_builtin_type = T_443_is_builtin_type;
+ assign io_outer_acquire_bits_a_type = T_443_a_type;
+ assign io_outer_acquire_bits_union = T_443_union;
+ assign io_outer_acquire_bits_data = T_443_data;
+ assign io_outer_grant_ready = T_519 ? io_inner_grant_ready : 1'h0;
+ assign io_has_acquire_conflict = 1'h0;
+ assign io_has_acquire_match = 1'h0;
+ assign io_has_release_match = io_inner_release_bits_voluntary;
+ assign coh_sharers = 1'h0;
+ assign T_302 = io_inner_release_ready & io_inner_release_valid;
+ assign T_306_0 = 1'h0;
+ assign T_306_1 = 1'h1;
+ assign T_306_2 = 2'h2;
+ assign T_311 = T_306_0 == io_inner_release_bits_r_type;
+ assign T_312 = T_306_1 == io_inner_release_bits_r_type;
+ assign T_313 = T_306_2 == io_inner_release_bits_r_type;
+ assign T_315 = 1'h0 | T_311;
+ assign T_316 = T_315 | T_312;
+ assign T_317 = T_316 | T_313;
+ assign T_318 = 1'h1 & T_317;
+ assign T_319 = T_302 & T_318;
+ assign T_323 = T_321 == 2'h3;
+ assign T_325 = 1'h0 & T_323;
+ assign T_328 = T_321 + 1'h1;
+ assign T_329 = T_328[1:0];
+ assign T_330 = T_325 ? 1'h0 : T_329;
+ assign T_331 = T_319 & T_323;
+ assign T_332 = T_318 ? T_321 : 1'h0;
+ assign irel_data_done = T_318 ? T_331 : T_302;
+ assign T_335 = io_outer_acquire_ready & io_outer_acquire_valid;
+ assign T_337 = 1'h1 & io_outer_acquire_bits_is_builtin_type;
+ assign T_340_0 = 3'h3;
+ assign T_343 = T_340_0 == io_outer_acquire_bits_a_type;
+ assign T_345 = 1'h0 | T_343;
+ assign T_346 = T_337 & T_345;
+ assign T_347 = T_335 & T_346;
+ assign T_351 = T_349 == 2'h3;
+ assign T_353 = 1'h0 & T_351;
+ assign T_356 = T_349 + 1'h1;
+ assign T_357 = T_356[1:0];
+ assign T_358 = T_353 ? 1'h0 : T_357;
+ assign T_359 = T_347 & T_351;
+ assign oacq_data_cnt = T_346 ? T_349 : 1'h0;
+ assign oacq_data_done = T_346 ? T_359 : T_335;
+ assign T_384_addr_beat = 1'h0;
+ assign T_384_client_xact_id = xact_client_xact_id;
+ assign T_384_manager_xact_id = 1'h0;
+ assign T_384_is_builtin_type = 1'h1;
+ assign T_384_g_type = 3'h0;
+ assign T_384_data = 1'h0;
+ assign T_384_client_id = xact_client_id;
+ assign GEN_3 = $signed(16'hffff);
+ assign T_397 = $unsigned(GEN_3);
+ assign T_403 = {1'h0,3'h7};
+ assign T_404 = {1'h0,1'h1};
+ assign T_405 = {T_403,T_404};
+ assign T_407 = {1'h0,1'h1};
+ assign T_408 = {3'h7,T_407};
+ assign T_410 = {T_397,1'h1};
+ assign T_412 = {T_397,1'h1};
+ assign T_414 = {1'h0,3'h7};
+ assign T_415 = {1'h0,1'h1};
+ assign T_416 = {T_414,T_415};
+ assign T_418 = {5'h0,1'h1};
+ assign T_420 = {5'h1,1'h1};
+ assign T_421 = 3'h6 == 3'h3;
+ assign T_422 = T_421 ? T_420 : 1'h0;
+ assign T_423 = 3'h5 == 3'h3;
+ assign T_424 = T_423 ? T_418 : T_422;
+ assign T_425 = 3'h4 == 3'h3;
+ assign T_426 = T_425 ? T_416 : T_424;
+ assign T_427 = 3'h3 == 3'h3;
+ assign T_428 = T_427 ? T_412 : T_426;
+ assign T_429 = 3'h2 == 3'h3;
+ assign T_430 = T_429 ? T_410 : T_428;
+ assign T_431 = 3'h1 == 3'h3;
+ assign T_432 = T_431 ? T_408 : T_430;
+ assign T_433 = 3'h0 == 3'h3;
+ assign T_434 = T_433 ? T_405 : T_432;
+ assign T_443_addr_block = xact_addr_block;
+ assign T_443_client_xact_id = 1'h0;
+ assign T_443_addr_beat = oacq_data_cnt;
+ assign T_443_is_builtin_type = 1'h1;
+ assign T_443_a_type = 3'h3;
+ assign T_443_union = T_434;
+ assign T_443_data = GEN_0;
+ assign GEN_0 = GEN_20 ? xact_data_buffer_3 : GEN_21 ? xact_data_buffer_2 : GEN_22 ? xact_data_buffer_1 : xact_data_buffer_0;
+ assign GEN_1 = io_inner_release_bits_data;
+ assign T_455 = 1'h1 << io_inner_release_bits_addr_beat;
+ assign T_456 = irel_data_valid | T_455;
+ assign T_457 = ~ irel_data_valid;
+ assign T_458 = T_457 | T_455;
+ assign T_459 = ~ T_458;
+ assign T_460 = 1'h1 ? T_456 : T_459;
+ assign T_462 = 1'h0 == state;
+ assign GEN_2 = io_inner_release_bits_data;
+ assign T_468_0 = 1'h0;
+ assign T_468_1 = 1'h1;
+ assign T_468_2 = 2'h2;
+ assign T_473 = T_468_0 == io_inner_release_bits_r_type;
+ assign T_474 = T_468_1 == io_inner_release_bits_r_type;
+ assign T_475 = T_468_2 == io_inner_release_bits_r_type;
+ assign T_477 = 1'h0 | T_473;
+ assign T_478 = T_477 | T_474;
+ assign T_479 = T_478 | T_475;
+ assign T_480 = 1'h1 & T_479;
+ assign T_482_0 = 1'h0;
+ assign T_482_1 = 1'h1;
+ assign T_482_2 = 2'h2;
+ assign T_487 = T_482_0 == io_inner_release_bits_r_type;
+ assign T_488 = T_482_1 == io_inner_release_bits_r_type;
+ assign T_489 = T_482_2 == io_inner_release_bits_r_type;
+ assign T_491 = 1'h0 | T_487;
+ assign T_492 = T_491 | T_488;
+ assign T_493 = T_492 | T_489;
+ assign T_494 = T_493 << io_inner_release_bits_addr_beat;
+ assign T_496_0 = 1'h0;
+ assign T_496_1 = 1'h1;
+ assign T_496_2 = 2'h2;
+ assign T_501 = T_496_0 == io_inner_release_bits_r_type;
+ assign T_502 = T_496_1 == io_inner_release_bits_r_type;
+ assign T_503 = T_496_2 == io_inner_release_bits_r_type;
+ assign T_505 = 1'h0 | T_501;
+ assign T_506 = T_505 | T_502;
+ assign T_507 = T_506 | T_503;
+ assign T_510 = 1'h0 == 1'h0;
+ assign T_511 = T_510 ? 2'h3 : 1'h0;
+ assign T_512 = T_507 ? 1'h1 : T_511;
+ assign T_513 = 1'h1 == state;
+ assign T_515 = collect_irel_data == 1'h0;
+ assign T_516 = irel_data_valid >> oacq_data_cnt;
+ assign T_517 = T_516[0];
+ assign T_518 = T_515 | T_517;
+ assign T_519 = 2'h2 == state;
+ assign T_520 = io_inner_grant_ready & io_inner_grant_valid;
+ assign T_523 = 1'h0 == 1'h0;
+ assign T_525 = io_inner_grant_bits_g_type == 3'h0;
+ assign T_526 = io_inner_grant_bits_is_builtin_type & T_525;
+ assign T_528 = T_526 == 1'h0;
+ assign T_529 = T_523 & T_528;
+ assign T_530 = T_529 ? 2'h3 : 1'h0;
+ assign T_531 = 2'h3 == state;
+ assign GEN_4 = 1'h0 == 1'h0;
+ assign GEN_5 = 1'h0 == io_inner_release_bits_addr_beat;
+ assign GEN_6 = 1'h0 == io_inner_release_bits_addr_beat;
+ assign GEN_7 = 1'h0 == io_inner_release_bits_addr_beat;
+ assign GEN_8 = 1'h1 == 1'h0;
+ assign GEN_9 = 1'h1 == io_inner_release_bits_addr_beat;
+ assign GEN_10 = 1'h1 == io_inner_release_bits_addr_beat;
+ assign GEN_11 = 1'h1 == io_inner_release_bits_addr_beat;
+ assign GEN_12 = 2'h2 == 1'h0;
+ assign GEN_13 = 2'h2 == io_inner_release_bits_addr_beat;
+ assign GEN_14 = 2'h2 == io_inner_release_bits_addr_beat;
+ assign GEN_15 = 2'h2 == io_inner_release_bits_addr_beat;
+ assign GEN_16 = 2'h3 == 1'h0;
+ assign GEN_17 = 2'h3 == io_inner_release_bits_addr_beat;
+ assign GEN_18 = 2'h3 == io_inner_release_bits_addr_beat;
+ assign GEN_19 = 2'h3 == io_inner_release_bits_addr_beat;
+ assign GEN_20 = 2'h3 == oacq_data_cnt;
+ assign GEN_21 = 2'h2 == oacq_data_cnt;
+ assign GEN_22 = 1'h1 == oacq_data_cnt;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ state = {1{$random}};
+ xact_addr_beat = {1{$random}};
+ xact_addr_block = {1{$random}};
+ xact_client_xact_id = {1{$random}};
+ xact_voluntary = {1{$random}};
+ xact_r_type = {1{$random}};
+ xact_data_buffer_0 = {1{$random}};
+ xact_data_buffer_1 = {1{$random}};
+ xact_data_buffer_2 = {1{$random}};
+ xact_data_buffer_3 = {1{$random}};
+ xact_wmask_buffer_0 = {1{$random}};
+ xact_wmask_buffer_1 = {1{$random}};
+ xact_wmask_buffer_2 = {1{$random}};
+ xact_wmask_buffer_3 = {1{$random}};
+ xact_client_id = {1{$random}};
+ collect_irel_data = {1{$random}};
+ irel_data_valid = {1{$random}};
+ T_321 = {1{$random}};
+ T_349 = {1{$random}};
+ GEN_23 = {1{$random}};
+ GEN_24 = {1{$random}};
+ GEN_25 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ state <= 1'h0;
+ end else begin
+ if(T_531) begin
+ if(io_inner_finish_valid) begin
+ state <= 1'h0;
+ end else begin
+ if(T_519) begin
+ if(T_520) begin
+ state <= T_530;
+ end else begin
+ if(T_513) begin
+ if(oacq_data_done) begin
+ state <= 2'h2;
+ end else begin
+ if(T_462) begin
+ if(io_inner_release_valid) begin
+ state <= T_512;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_462) begin
+ if(io_inner_release_valid) begin
+ state <= T_512;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_513) begin
+ if(oacq_data_done) begin
+ state <= 2'h2;
+ end else begin
+ if(T_462) begin
+ if(io_inner_release_valid) begin
+ state <= T_512;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_462) begin
+ if(io_inner_release_valid) begin
+ state <= T_512;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_519) begin
+ if(T_520) begin
+ state <= T_530;
+ end else begin
+ if(T_513) begin
+ if(oacq_data_done) begin
+ state <= 2'h2;
+ end else begin
+ if(T_462) begin
+ if(io_inner_release_valid) begin
+ state <= T_512;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_462) begin
+ if(io_inner_release_valid) begin
+ state <= T_512;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_513) begin
+ if(oacq_data_done) begin
+ state <= 2'h2;
+ end else begin
+ if(T_462) begin
+ if(io_inner_release_valid) begin
+ state <= T_512;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_462) begin
+ if(io_inner_release_valid) begin
+ state <= T_512;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_462) begin
+ if(io_inner_release_valid) begin
+ xact_addr_beat <= io_inner_release_bits_addr_beat;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_462) begin
+ if(io_inner_release_valid) begin
+ xact_addr_block <= io_inner_release_bits_addr_block;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_462) begin
+ if(io_inner_release_valid) begin
+ xact_client_xact_id <= io_inner_release_bits_client_xact_id;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_462) begin
+ if(io_inner_release_valid) begin
+ xact_voluntary <= io_inner_release_bits_voluntary;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_462) begin
+ if(io_inner_release_valid) begin
+ xact_r_type <= io_inner_release_bits_r_type;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_462) begin
+ if(io_inner_release_valid) begin
+ if(GEN_4) begin
+ xact_data_buffer_0 <= GEN_2;
+ end else begin
+ if(collect_irel_data) begin
+ if(io_inner_release_valid) begin
+ if(GEN_5) begin
+ xact_data_buffer_0 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_irel_data) begin
+ if(io_inner_release_valid) begin
+ if(GEN_6) begin
+ xact_data_buffer_0 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_irel_data) begin
+ if(io_inner_release_valid) begin
+ if(GEN_7) begin
+ xact_data_buffer_0 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_462) begin
+ if(io_inner_release_valid) begin
+ if(GEN_8) begin
+ xact_data_buffer_1 <= GEN_2;
+ end else begin
+ if(collect_irel_data) begin
+ if(io_inner_release_valid) begin
+ if(GEN_9) begin
+ xact_data_buffer_1 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_irel_data) begin
+ if(io_inner_release_valid) begin
+ if(GEN_10) begin
+ xact_data_buffer_1 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_irel_data) begin
+ if(io_inner_release_valid) begin
+ if(GEN_11) begin
+ xact_data_buffer_1 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_462) begin
+ if(io_inner_release_valid) begin
+ if(GEN_12) begin
+ xact_data_buffer_2 <= GEN_2;
+ end else begin
+ if(collect_irel_data) begin
+ if(io_inner_release_valid) begin
+ if(GEN_13) begin
+ xact_data_buffer_2 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_irel_data) begin
+ if(io_inner_release_valid) begin
+ if(GEN_14) begin
+ xact_data_buffer_2 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_irel_data) begin
+ if(io_inner_release_valid) begin
+ if(GEN_15) begin
+ xact_data_buffer_2 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_462) begin
+ if(io_inner_release_valid) begin
+ if(GEN_16) begin
+ xact_data_buffer_3 <= GEN_2;
+ end else begin
+ if(collect_irel_data) begin
+ if(io_inner_release_valid) begin
+ if(GEN_17) begin
+ xact_data_buffer_3 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_irel_data) begin
+ if(io_inner_release_valid) begin
+ if(GEN_18) begin
+ xact_data_buffer_3 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_irel_data) begin
+ if(io_inner_release_valid) begin
+ if(GEN_19) begin
+ xact_data_buffer_3 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ ;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ ;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ ;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ ;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_462) begin
+ if(io_inner_release_valid) begin
+ xact_client_id <= io_inner_release_bits_client_id;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ collect_irel_data <= 1'h0;
+ end else begin
+ if(T_462) begin
+ if(io_inner_release_valid) begin
+ collect_irel_data <= T_480;
+ end else begin
+ if(collect_irel_data) begin
+ if(irel_data_done) begin
+ collect_irel_data <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_irel_data) begin
+ if(irel_data_done) begin
+ collect_irel_data <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ irel_data_valid <= 4'h0;
+ end else begin
+ if(T_462) begin
+ if(io_inner_release_valid) begin
+ irel_data_valid <= T_494;
+ end else begin
+ if(collect_irel_data) begin
+ if(io_inner_release_valid) begin
+ irel_data_valid <= T_460;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_irel_data) begin
+ if(io_inner_release_valid) begin
+ irel_data_valid <= T_460;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ T_321 <= 2'h0;
+ end else begin
+ if(T_319) begin
+ T_321 <= T_330;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_349 <= 2'h0;
+ end else begin
+ if(T_347) begin
+ T_349 <= T_358;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module BroadcastAcquireTracker(
+ input clk,
+ input reset,
+ output io_inner_acquire_ready,
+ input io_inner_acquire_valid,
+ input [25:0] io_inner_acquire_bits_addr_block,
+ input [1:0] io_inner_acquire_bits_client_xact_id,
+ input [1:0] io_inner_acquire_bits_addr_beat,
+ input io_inner_acquire_bits_is_builtin_type,
+ input [2:0] io_inner_acquire_bits_a_type,
+ input [16:0] io_inner_acquire_bits_union,
+ input [3:0] io_inner_acquire_bits_data,
+ input [1:0] io_inner_acquire_bits_client_id,
+ input io_inner_grant_ready,
+ output io_inner_grant_valid,
+ output [1:0] io_inner_grant_bits_addr_beat,
+ output [1:0] io_inner_grant_bits_client_xact_id,
+ output [3:0] io_inner_grant_bits_manager_xact_id,
+ output io_inner_grant_bits_is_builtin_type,
+ output [3:0] io_inner_grant_bits_g_type,
+ output [3:0] io_inner_grant_bits_data,
+ output [1:0] io_inner_grant_bits_client_id,
+ output io_inner_finish_ready,
+ input io_inner_finish_valid,
+ input [3:0] io_inner_finish_bits_manager_xact_id,
+ input io_inner_probe_ready,
+ output io_inner_probe_valid,
+ output [25:0] io_inner_probe_bits_addr_block,
+ output [1:0] io_inner_probe_bits_p_type,
+ output [1:0] io_inner_probe_bits_client_id,
+ output io_inner_release_ready,
+ input io_inner_release_valid,
+ input [1:0] io_inner_release_bits_addr_beat,
+ input [25:0] io_inner_release_bits_addr_block,
+ input [1:0] io_inner_release_bits_client_xact_id,
+ input io_inner_release_bits_voluntary,
+ input [2:0] io_inner_release_bits_r_type,
+ input [3:0] io_inner_release_bits_data,
+ input [1:0] io_inner_release_bits_client_id,
+ input io_incoherent_0,
+ input io_outer_acquire_ready,
+ output io_outer_acquire_valid,
+ output [25:0] io_outer_acquire_bits_addr_block,
+ output [3:0] io_outer_acquire_bits_client_xact_id,
+ output [1:0] io_outer_acquire_bits_addr_beat,
+ output io_outer_acquire_bits_is_builtin_type,
+ output [2:0] io_outer_acquire_bits_a_type,
+ output [16:0] io_outer_acquire_bits_union,
+ output [3:0] io_outer_acquire_bits_data,
+ output io_outer_grant_ready,
+ input io_outer_grant_valid,
+ input [1:0] io_outer_grant_bits_addr_beat,
+ input [3:0] io_outer_grant_bits_client_xact_id,
+ input io_outer_grant_bits_manager_xact_id,
+ input io_outer_grant_bits_is_builtin_type,
+ input [3:0] io_outer_grant_bits_g_type,
+ input [3:0] io_outer_grant_bits_data,
+ output io_has_acquire_conflict,
+ output io_has_acquire_match,
+ output io_has_release_match
+);
+ reg [2:0] state;
+ reg [25:0] xact_addr_block;
+ reg [1:0] xact_client_xact_id;
+ reg [1:0] xact_addr_beat;
+ reg xact_is_builtin_type;
+ reg [2:0] xact_a_type;
+ reg [16:0] xact_union;
+ reg [3:0] xact_data_buffer_0;
+ reg [3:0] xact_data_buffer_1;
+ reg [3:0] xact_data_buffer_2;
+ reg [3:0] xact_data_buffer_3;
+ reg [15:0] xact_wmask_buffer_0;
+ reg [15:0] xact_wmask_buffer_1;
+ reg [15:0] xact_wmask_buffer_2;
+ reg [15:0] xact_wmask_buffer_3;
+ reg [1:0] xact_client_id;
+ wire coh_sharers;
+ wire T_303;
+ wire T_304;
+ wire [2:0] T_309_0;
+ wire [2:0] T_309_1;
+ wire [2:0] T_309_2;
+ wire T_314;
+ wire T_315;
+ wire T_316;
+ wire T_318;
+ wire T_319;
+ wire T_320;
+ wire T_321;
+ wire T_323;
+ wire T_325;
+ wire T_327;
+ wire T_329;
+ reg release_count;
+ reg pending_probes;
+ wire T_334;
+ wire T_336_0;
+ wire GEN_7;
+ wire T_341;
+ wire [3:0] T_344;
+ wire [3:0] T_345;
+ wire T_346;
+ wire [3:0] T_347;
+ wire [3:0] T_348;
+ wire [3:0] mask_self;
+ wire T_350;
+ wire [3:0] mask_incoherent;
+ reg collect_iacq_data;
+ reg [3:0] iacq_data_valid;
+ wire T_356;
+ wire T_359;
+ wire [2:0] T_362_0;
+ wire T_365;
+ wire T_367;
+ wire T_368;
+ wire T_369;
+ reg [1:0] T_371;
+ wire T_373;
+ wire T_375;
+ wire [2:0] T_378;
+ wire [1:0] T_379;
+ wire [1:0] T_380;
+ wire T_381;
+ wire [1:0] T_382;
+ wire iacq_data_done;
+ wire T_384;
+ wire [1:0] T_388_0;
+ wire [1:0] T_388_1;
+ wire [1:0] T_388_2;
+ wire T_393;
+ wire T_394;
+ wire T_395;
+ wire T_397;
+ wire T_398;
+ wire T_399;
+ wire T_400;
+ wire T_401;
+ reg [1:0] T_403;
+ wire T_405;
+ wire T_407;
+ wire [2:0] T_410;
+ wire [1:0] T_411;
+ wire [1:0] T_412;
+ wire T_413;
+ wire [1:0] T_414;
+ wire irel_data_done;
+ wire T_417;
+ wire [2:0] T_421_0;
+ wire T_424;
+ wire T_426;
+ wire T_428_0;
+ wire T_428_1;
+ wire T_432;
+ wire T_433;
+ wire T_435;
+ wire T_436;
+ wire T_437;
+ wire T_438;
+ wire T_439;
+ reg [1:0] T_441;
+ wire T_443;
+ wire T_445;
+ wire [2:0] T_448;
+ wire [1:0] T_449;
+ wire [1:0] T_450;
+ wire T_451;
+ wire [1:0] ignt_data_cnt;
+ wire ignt_data_done;
+ wire T_455;
+ wire T_457;
+ wire [2:0] T_460_0;
+ wire T_463;
+ wire T_465;
+ wire T_466;
+ wire T_467;
+ reg [1:0] T_469;
+ wire T_471;
+ wire T_473;
+ wire [2:0] T_476;
+ wire [1:0] T_477;
+ wire [1:0] T_478;
+ wire T_479;
+ wire [1:0] oacq_data_cnt;
+ wire oacq_data_done;
+ wire T_482;
+ wire [2:0] T_487_0;
+ wire T_490;
+ wire T_492;
+ wire T_494_0;
+ wire T_497;
+ wire T_499;
+ wire T_500;
+ wire T_501;
+ wire T_502;
+ reg [1:0] T_504;
+ wire T_506;
+ wire T_508;
+ wire [2:0] T_511;
+ wire [1:0] T_512;
+ wire [1:0] T_513;
+ wire T_514;
+ wire [1:0] T_515;
+ wire ognt_data_done;
+ reg pending_ognt_ack;
+ wire [2:0] T_523_0;
+ wire [2:0] T_523_1;
+ wire [2:0] T_523_2;
+ wire T_528;
+ wire T_529;
+ wire T_530;
+ wire T_532;
+ wire T_533;
+ wire T_534;
+ wire pending_outer_write;
+ wire [2:0] T_540_0;
+ wire [2:0] T_540_1;
+ wire [2:0] T_540_2;
+ wire T_545;
+ wire T_546;
+ wire T_547;
+ wire T_549;
+ wire T_550;
+ wire T_551;
+ wire pending_outer_write_;
+ wire [2:0] T_556_0;
+ wire [2:0] T_556_1;
+ wire T_560;
+ wire T_561;
+ wire T_563;
+ wire T_564;
+ wire T_566_0;
+ wire T_566_1;
+ wire T_570;
+ wire T_571;
+ wire T_573;
+ wire T_574;
+ wire pending_outer_read;
+ wire T_594;
+ wire [2:0] T_595;
+ wire T_596;
+ wire [2:0] T_597;
+ wire T_598;
+ wire [2:0] T_599;
+ wire T_600;
+ wire [2:0] T_601;
+ wire T_602;
+ wire [2:0] T_603;
+ wire T_604;
+ wire [2:0] T_605;
+ wire T_606;
+ wire [2:0] T_607;
+ wire T_608;
+ wire T_611;
+ wire T_612;
+ wire T_613;
+ wire [2:0] T_614;
+ wire [1:0] T_623_addr_beat;
+ wire [1:0] T_623_client_xact_id;
+ wire [3:0] T_623_manager_xact_id;
+ wire T_623_is_builtin_type;
+ wire [3:0] T_623_g_type;
+ wire [3:0] T_623_data;
+ wire [1:0] T_623_client_id;
+ wire [2:0] T_634_0;
+ wire [2:0] T_634_1;
+ wire T_638;
+ wire T_639;
+ wire T_641;
+ wire T_642;
+ wire T_644_0;
+ wire T_644_1;
+ wire T_648;
+ wire T_649;
+ wire T_651;
+ wire T_652;
+ wire pending_outer_read_;
+ wire [2:0] T_658_0;
+ wire [2:0] T_658_1;
+ wire [2:0] T_658_2;
+ wire T_663;
+ wire T_664;
+ wire T_665;
+ wire T_667;
+ wire T_668;
+ wire T_669;
+ wire subblock_type;
+ wire T_671;
+ wire T_672;
+ wire T_673;
+ wire T_675;
+ wire T_676;
+ wire T_677;
+ wire T_678;
+ wire T_679;
+ wire T_681;
+ wire T_682;
+ wire T_683;
+ wire T_684;
+ wire [15:0] GEN_8;
+ wire [15:0] T_689;
+ wire [3:0] T_695;
+ wire [1:0] T_696;
+ wire [5:0] T_697;
+ wire [1:0] T_699;
+ wire [4:0] T_700;
+ wire [16:0] T_702;
+ wire [16:0] T_704;
+ wire [3:0] T_706;
+ wire [1:0] T_707;
+ wire [5:0] T_708;
+ wire [5:0] T_710;
+ wire [5:0] T_712;
+ wire T_713;
+ wire [5:0] T_714;
+ wire T_715;
+ wire [5:0] T_716;
+ wire T_717;
+ wire [5:0] T_718;
+ wire T_719;
+ wire [16:0] T_720;
+ wire T_721;
+ wire [16:0] T_722;
+ wire T_723;
+ wire [16:0] T_724;
+ wire T_725;
+ wire [16:0] T_726;
+ wire [25:0] oacq_probe_addr_block;
+ wire [3:0] oacq_probe_client_xact_id;
+ wire [1:0] oacq_probe_addr_beat;
+ wire oacq_probe_is_builtin_type;
+ wire [2:0] oacq_probe_a_type;
+ wire [16:0] oacq_probe_union;
+ wire [3:0] oacq_probe_data;
+ wire [3:0] T_744;
+ wire T_745;
+ wire [1:0] T_747;
+ wire T_749;
+ wire T_750;
+ wire T_751;
+ wire T_752;
+ wire T_754_0;
+ wire T_754_1;
+ wire [8:0] T_759;
+ wire [7:0] T_760;
+ wire [8:0] T_762;
+ wire [7:0] T_763;
+ wire [7:0] T_765_0;
+ wire [7:0] T_765_1;
+ wire [15:0] T_769;
+ wire T_771;
+ wire T_772;
+ wire T_774;
+ wire T_775;
+ wire T_776;
+ wire [15:0] T_777;
+ wire [15:0] T_779;
+ wire [15:0] T_780;
+ wire [3:0] T_788;
+ wire [1:0] T_789;
+ wire [5:0] T_790;
+ wire [1:0] T_792;
+ wire [4:0] T_793;
+ wire [16:0] T_795;
+ wire [16:0] T_797;
+ wire [3:0] T_799;
+ wire [1:0] T_800;
+ wire [5:0] T_801;
+ wire [5:0] T_803;
+ wire [5:0] T_805;
+ wire T_806;
+ wire [5:0] T_807;
+ wire T_808;
+ wire [5:0] T_809;
+ wire T_810;
+ wire [5:0] T_811;
+ wire T_812;
+ wire [16:0] T_813;
+ wire T_814;
+ wire [16:0] T_815;
+ wire T_816;
+ wire [16:0] T_817;
+ wire T_818;
+ wire [16:0] T_819;
+ wire [25:0] oacq_write_beat_addr_block;
+ wire [3:0] oacq_write_beat_client_xact_id;
+ wire [1:0] oacq_write_beat_addr_beat;
+ wire oacq_write_beat_is_builtin_type;
+ wire [2:0] oacq_write_beat_a_type;
+ wire [16:0] oacq_write_beat_union;
+ wire [3:0] oacq_write_beat_data;
+ wire [3:0] T_846;
+ wire [1:0] T_847;
+ wire [5:0] T_848;
+ wire [1:0] T_850;
+ wire [4:0] T_851;
+ wire [15:0] GEN_0;
+ wire [16:0] T_853;
+ wire [15:0] GEN_1;
+ wire [16:0] T_855;
+ wire [3:0] T_857;
+ wire [1:0] T_858;
+ wire [5:0] T_859;
+ wire [5:0] T_861;
+ wire [5:0] T_863;
+ wire T_864;
+ wire [5:0] T_865;
+ wire T_866;
+ wire [5:0] T_867;
+ wire T_868;
+ wire [5:0] T_869;
+ wire T_870;
+ wire [16:0] T_871;
+ wire T_872;
+ wire [16:0] T_873;
+ wire T_874;
+ wire [16:0] T_875;
+ wire T_876;
+ wire [16:0] T_877;
+ wire [25:0] oacq_write_block_addr_block;
+ wire [3:0] oacq_write_block_client_xact_id;
+ wire [1:0] oacq_write_block_addr_beat;
+ wire oacq_write_block_is_builtin_type;
+ wire [2:0] oacq_write_block_a_type;
+ wire [16:0] oacq_write_block_union;
+ wire [3:0] oacq_write_block_data;
+ wire [3:0] GEN_2;
+ wire [3:0] T_895;
+ wire [2:0] T_896;
+ wire [6:0] T_904;
+ wire [5:0] T_905;
+ wire [12:0] T_906;
+ wire [5:0] T_908;
+ wire [8:0] T_909;
+ wire [1:0] T_911;
+ wire [1:0] T_913;
+ wire [6:0] T_915;
+ wire [5:0] T_916;
+ wire [12:0] T_917;
+ wire [5:0] T_919;
+ wire [5:0] T_921;
+ wire T_922;
+ wire [5:0] T_923;
+ wire T_924;
+ wire [5:0] T_925;
+ wire T_926;
+ wire [12:0] T_927;
+ wire T_928;
+ wire [12:0] T_929;
+ wire T_930;
+ wire [12:0] T_931;
+ wire T_932;
+ wire [12:0] T_933;
+ wire T_934;
+ wire [12:0] T_935;
+ wire [25:0] oacq_read_beat_addr_block;
+ wire [3:0] oacq_read_beat_client_xact_id;
+ wire [1:0] oacq_read_beat_addr_beat;
+ wire oacq_read_beat_is_builtin_type;
+ wire [2:0] oacq_read_beat_a_type;
+ wire [16:0] oacq_read_beat_union;
+ wire [3:0] oacq_read_beat_data;
+ wire [3:0] T_962;
+ wire [5:0] T_963;
+ wire [9:0] T_964;
+ wire [5:0] T_966;
+ wire [8:0] T_967;
+ wire [1:0] T_969;
+ wire [1:0] T_971;
+ wire [3:0] T_973;
+ wire [5:0] T_974;
+ wire [9:0] T_975;
+ wire [5:0] T_977;
+ wire [5:0] T_979;
+ wire T_980;
+ wire [5:0] T_981;
+ wire T_982;
+ wire [5:0] T_983;
+ wire T_984;
+ wire [9:0] T_985;
+ wire T_986;
+ wire [9:0] T_987;
+ wire T_988;
+ wire [9:0] T_989;
+ wire T_990;
+ wire [9:0] T_991;
+ wire T_992;
+ wire [9:0] T_993;
+ wire [25:0] oacq_read_block_addr_block;
+ wire [3:0] oacq_read_block_client_xact_id;
+ wire [1:0] oacq_read_block_addr_beat;
+ wire oacq_read_block_is_builtin_type;
+ wire [2:0] oacq_read_block_a_type;
+ wire [16:0] oacq_read_block_union;
+ wire [3:0] oacq_read_block_data;
+ wire T_1011;
+ wire T_1012;
+ wire [25:0] T_1013_addr_block;
+ wire [3:0] T_1013_client_xact_id;
+ wire [1:0] T_1013_addr_beat;
+ wire T_1013_is_builtin_type;
+ wire [2:0] T_1013_a_type;
+ wire [16:0] T_1013_union;
+ wire [3:0] T_1013_data;
+ wire [25:0] T_1021_addr_block;
+ wire [3:0] T_1021_client_xact_id;
+ wire [1:0] T_1021_addr_beat;
+ wire T_1021_is_builtin_type;
+ wire [2:0] T_1021_a_type;
+ wire [16:0] T_1021_union;
+ wire [3:0] T_1021_data;
+ wire [25:0] T_1029_addr_block;
+ wire [3:0] T_1029_client_xact_id;
+ wire [1:0] T_1029_addr_beat;
+ wire T_1029_is_builtin_type;
+ wire [2:0] T_1029_a_type;
+ wire [16:0] T_1029_union;
+ wire [3:0] T_1029_data;
+ wire [25:0] T_1037_addr_block;
+ wire [3:0] T_1037_client_xact_id;
+ wire [1:0] T_1037_addr_beat;
+ wire T_1037_is_builtin_type;
+ wire [2:0] T_1037_a_type;
+ wire [16:0] T_1037_union;
+ wire [3:0] T_1037_data;
+ wire T_1054;
+ wire [1:0] T_1055;
+ wire T_1056;
+ wire [1:0] T_1057;
+ wire T_1058;
+ wire [1:0] T_1059;
+ wire T_1060;
+ wire [1:0] T_1061;
+ wire T_1062;
+ wire [1:0] T_1063;
+ wire T_1064;
+ wire [1:0] T_1065;
+ wire T_1066;
+ wire [1:0] T_1067;
+ wire T_1068;
+ wire [1:0] T_1069;
+ wire T_1070;
+ wire [1:0] T_1071;
+ wire [1:0] T_1072;
+ wire [25:0] T_1077_addr_block;
+ wire [1:0] T_1077_p_type;
+ wire [1:0] T_1077_client_id;
+ wire T_1100;
+ wire [2:0] T_1101;
+ wire T_1102;
+ wire [2:0] T_1103;
+ wire T_1104;
+ wire [2:0] T_1105;
+ wire T_1106;
+ wire [2:0] T_1107;
+ wire T_1108;
+ wire [2:0] T_1109;
+ wire T_1110;
+ wire [2:0] T_1111;
+ wire T_1112;
+ wire [2:0] T_1113;
+ wire T_1114;
+ wire T_1117;
+ wire T_1118;
+ wire T_1119;
+ wire [2:0] T_1120;
+ wire [1:0] T_1129_addr_beat;
+ wire [1:0] T_1129_client_xact_id;
+ wire [3:0] T_1129_manager_xact_id;
+ wire T_1129_is_builtin_type;
+ wire [3:0] T_1129_g_type;
+ wire [3:0] T_1129_data;
+ wire [1:0] T_1129_client_id;
+ wire T_1140;
+ wire T_1141;
+ wire T_1142;
+ wire T_1143;
+ wire T_1144;
+ wire T_1145;
+ wire T_1147;
+ wire T_1149;
+ wire T_1151;
+ wire T_1153;
+ wire T_1154;
+ wire T_1155;
+ wire T_1156;
+ wire T_1157;
+ wire T_1158;
+ wire T_1159;
+ wire T_1161;
+ wire T_1163;
+ wire T_1165;
+ wire T_1167;
+ wire T_1168;
+ wire T_1169;
+ wire T_1170;
+ wire T_1172;
+ wire [2:0] T_1175_0;
+ wire T_1178;
+ wire T_1180;
+ wire T_1181;
+ wire T_1182;
+ wire T_1184;
+ wire T_1185;
+ wire T_1187;
+ wire T_1189;
+ wire T_1191;
+ wire T_1193;
+ wire [3:0] GEN_3;
+ wire [3:0] T_1197;
+ wire T_1198;
+ wire [1:0] T_1200;
+ wire T_1202;
+ wire T_1203;
+ wire T_1204;
+ wire T_1205;
+ wire T_1207_0;
+ wire T_1207_1;
+ wire [8:0] T_1212;
+ wire [7:0] T_1213;
+ wire [8:0] T_1215;
+ wire [7:0] T_1216;
+ wire [7:0] T_1218_0;
+ wire [7:0] T_1218_1;
+ wire [15:0] T_1222;
+ wire T_1224;
+ wire T_1225;
+ wire T_1227;
+ wire T_1228;
+ wire T_1229;
+ wire [15:0] T_1230;
+ wire [15:0] T_1232;
+ wire [15:0] T_1233;
+ wire [15:0] GEN_4;
+ wire [3:0] T_1236;
+ wire [3:0] T_1237;
+ wire [3:0] T_1238;
+ wire [3:0] T_1239;
+ wire [3:0] T_1240;
+ wire [3:0] T_1241;
+ wire T_1245;
+ wire [3:0] GEN_5;
+ wire [3:0] T_1251;
+ wire T_1252;
+ wire [1:0] T_1254;
+ wire T_1256;
+ wire T_1257;
+ wire T_1258;
+ wire T_1259;
+ wire T_1261_0;
+ wire T_1261_1;
+ wire [8:0] T_1266;
+ wire [7:0] T_1267;
+ wire [8:0] T_1269;
+ wire [7:0] T_1270;
+ wire [7:0] T_1272_0;
+ wire [7:0] T_1272_1;
+ wire [15:0] T_1276;
+ wire T_1278;
+ wire T_1279;
+ wire T_1281;
+ wire T_1282;
+ wire T_1283;
+ wire [15:0] T_1284;
+ wire [15:0] T_1286;
+ wire [15:0] T_1287;
+ wire [15:0] GEN_6;
+ wire T_1289;
+ wire [2:0] T_1292_0;
+ wire T_1295;
+ wire T_1297;
+ wire T_1298;
+ wire [2:0] T_1303_0;
+ wire [2:0] T_1303_1;
+ wire [2:0] T_1303_2;
+ wire T_1308;
+ wire T_1309;
+ wire T_1310;
+ wire T_1312;
+ wire T_1313;
+ wire T_1314;
+ wire T_1315;
+ wire [3:0] T_1316;
+ wire T_1318;
+ wire T_1319;
+ wire T_1320;
+ wire T_1321;
+ wire T_1322;
+ wire [1:0] T_1324;
+ wire [2:0] T_1325;
+ wire [1:0] T_1326;
+ wire [1:0] T_1329;
+ wire [2:0] T_1330;
+ wire [1:0] T_1331;
+ wire [2:0] T_1332;
+ wire [3:0] T_1333;
+ wire [2:0] T_1334;
+ wire [2:0] T_1335;
+ wire [2:0] T_1336;
+ wire [2:0] T_1337;
+ wire T_1338;
+ wire T_1340;
+ wire [1:0] T_1342;
+ wire [1:0] T_1343;
+ wire [1:0] T_1344;
+ wire [1:0] T_1346_0;
+ wire [1:0] T_1346_1;
+ wire [1:0] T_1346_2;
+ wire T_1351;
+ wire T_1352;
+ wire T_1353;
+ wire T_1355;
+ wire T_1356;
+ wire T_1357;
+ wire T_1359;
+ wire T_1360;
+ wire [1:0] T_1362_0;
+ wire [1:0] T_1362_1;
+ wire [1:0] T_1362_2;
+ wire T_1367;
+ wire T_1368;
+ wire T_1369;
+ wire T_1371;
+ wire T_1372;
+ wire T_1373;
+ wire [1:0] T_1377;
+ wire T_1378;
+ wire T_1380;
+ wire [2:0] T_1381;
+ wire [2:0] T_1382;
+ wire T_1384;
+ wire [1:0] T_1386;
+ wire T_1387;
+ wire T_1389;
+ wire [2:0] T_1390;
+ wire [2:0] T_1391;
+ wire T_1392;
+ wire T_1394;
+ wire T_1396;
+ wire [3:0] T_1397;
+ wire T_1398;
+ wire T_1399;
+ wire T_1400;
+ wire [2:0] T_1402;
+ wire T_1403;
+ wire T_1405;
+ wire T_1406;
+ wire T_1407;
+ wire T_1410;
+ wire T_1412;
+ wire T_1413;
+ wire T_1415;
+ wire T_1416;
+ wire [2:0] T_1417;
+ wire T_1418;
+ wire T_1422;
+ wire T_1424;
+ wire T_1425;
+ wire T_1427;
+ wire T_1428;
+ wire [2:0] T_1429;
+ wire T_1430;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ wire GEN_17;
+ wire GEN_18;
+ wire GEN_19;
+ wire GEN_20;
+ wire GEN_21;
+ wire GEN_22;
+ wire GEN_23;
+ wire GEN_24;
+ wire GEN_25;
+ wire GEN_26;
+ wire GEN_27;
+ wire GEN_28;
+ wire GEN_29;
+ wire GEN_30;
+ wire GEN_31;
+ wire GEN_32;
+ wire GEN_33;
+ wire GEN_34;
+ wire GEN_35;
+ wire GEN_36;
+ wire GEN_37;
+ wire GEN_38;
+ wire GEN_39;
+ wire GEN_40;
+ wire GEN_41;
+ wire GEN_42;
+ wire GEN_43;
+ wire GEN_44;
+ wire GEN_45;
+ wire GEN_46;
+ wire GEN_47;
+ wire GEN_48;
+ wire GEN_49;
+ wire GEN_50;
+ wire GEN_51;
+ wire GEN_52;
+ wire GEN_53;
+ assign io_inner_acquire_ready = T_1245 ? 1'h1 : collect_iacq_data ? 1'h1 : 1'h0;
+ assign io_inner_grant_valid = T_1418 ? 1'h1 : T_1407 ? io_outer_grant_valid : 1'h0;
+ assign io_inner_grant_bits_addr_beat = T_1129_addr_beat;
+ assign io_inner_grant_bits_client_xact_id = T_1129_client_xact_id;
+ assign io_inner_grant_bits_manager_xact_id = T_1129_manager_xact_id;
+ assign io_inner_grant_bits_is_builtin_type = T_1129_is_builtin_type;
+ assign io_inner_grant_bits_g_type = T_1129_g_type;
+ assign io_inner_grant_bits_data = T_1129_data;
+ assign io_inner_grant_bits_client_id = T_1129_client_id;
+ assign io_inner_finish_ready = T_1430 ? 1'h1 : 1'h0;
+ assign io_inner_probe_valid = T_1338 ? T_1340 : 1'h0;
+ assign io_inner_probe_bits_addr_block = T_1077_addr_block;
+ assign io_inner_probe_bits_p_type = T_1077_p_type;
+ assign io_inner_probe_bits_client_id = T_1077_client_id;
+ assign io_inner_release_ready = T_1338 ? T_1360 : 1'h0;
+ assign io_outer_acquire_valid = T_1403 ? T_1405 : T_1392 ? T_1400 : T_1338 ? io_inner_release_valid ? T_1373 ? 1'h1 : 1'h0 : 1'h0 : 1'h0;
+ assign io_outer_acquire_bits_addr_block = T_1037_addr_block;
+ assign io_outer_acquire_bits_client_xact_id = T_1037_client_xact_id;
+ assign io_outer_acquire_bits_addr_beat = T_1037_addr_beat;
+ assign io_outer_acquire_bits_is_builtin_type = T_1037_is_builtin_type;
+ assign io_outer_acquire_bits_a_type = T_1037_a_type;
+ assign io_outer_acquire_bits_union = T_1037_union;
+ assign io_outer_acquire_bits_data = T_1037_data;
+ assign io_outer_grant_ready = T_1407 ? io_inner_grant_ready : pending_ognt_ack ? 1'h1 : 1'h0;
+ assign io_has_acquire_conflict = T_676;
+ assign io_has_acquire_match = T_678;
+ assign io_has_release_match = T_684;
+ assign coh_sharers = 1'h0;
+ assign T_303 = state != 1'h0;
+ assign T_304 = T_303 & xact_is_builtin_type;
+ assign T_309_0 = 3'h4;
+ assign T_309_1 = 3'h5;
+ assign T_309_2 = 3'h6;
+ assign T_314 = T_309_0 == xact_a_type;
+ assign T_315 = T_309_1 == xact_a_type;
+ assign T_316 = T_309_2 == xact_a_type;
+ assign T_318 = 1'h0 | T_314;
+ assign T_319 = T_318 | T_315;
+ assign T_320 = T_319 | T_316;
+ assign T_321 = T_304 & T_320;
+ assign T_323 = T_321 == 1'h0;
+ assign T_325 = reset == 1'h0;
+ assign T_327 = T_323 == 1'h0;
+ assign T_329 = reset == 1'h0;
+ assign T_334 = pending_probes;
+ assign T_336_0 = T_334;
+ assign GEN_7 = $signed(1'h1);
+ assign T_341 = $unsigned(GEN_7);
+ assign T_344 = 1'h1 << io_inner_acquire_bits_client_id;
+ assign T_345 = T_341 | T_344;
+ assign T_346 = ~ T_341;
+ assign T_347 = T_346 | T_344;
+ assign T_348 = ~ T_347;
+ assign mask_self = 1'h0 ? T_345 : T_348;
+ assign T_350 = ~ io_incoherent_0;
+ assign mask_incoherent = mask_self & T_350;
+ assign T_356 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_359 = 1'h1 & io_inner_acquire_bits_is_builtin_type;
+ assign T_362_0 = 3'h3;
+ assign T_365 = T_362_0 == io_inner_acquire_bits_a_type;
+ assign T_367 = 1'h0 | T_365;
+ assign T_368 = T_359 & T_367;
+ assign T_369 = T_356 & T_368;
+ assign T_373 = T_371 == 2'h3;
+ assign T_375 = 1'h0 & T_373;
+ assign T_378 = T_371 + 1'h1;
+ assign T_379 = T_378[1:0];
+ assign T_380 = T_375 ? 1'h0 : T_379;
+ assign T_381 = T_369 & T_373;
+ assign T_382 = T_368 ? T_371 : 1'h0;
+ assign iacq_data_done = T_368 ? T_381 : T_356;
+ assign T_384 = io_inner_release_ready & io_inner_release_valid;
+ assign T_388_0 = 1'h0;
+ assign T_388_1 = 1'h1;
+ assign T_388_2 = 2'h2;
+ assign T_393 = T_388_0 == io_inner_release_bits_r_type;
+ assign T_394 = T_388_1 == io_inner_release_bits_r_type;
+ assign T_395 = T_388_2 == io_inner_release_bits_r_type;
+ assign T_397 = 1'h0 | T_393;
+ assign T_398 = T_397 | T_394;
+ assign T_399 = T_398 | T_395;
+ assign T_400 = 1'h1 & T_399;
+ assign T_401 = T_384 & T_400;
+ assign T_405 = T_403 == 2'h3;
+ assign T_407 = 1'h0 & T_405;
+ assign T_410 = T_403 + 1'h1;
+ assign T_411 = T_410[1:0];
+ assign T_412 = T_407 ? 1'h0 : T_411;
+ assign T_413 = T_401 & T_405;
+ assign T_414 = T_400 ? T_403 : 1'h0;
+ assign irel_data_done = T_400 ? T_413 : T_384;
+ assign T_417 = io_inner_grant_ready & io_inner_grant_valid;
+ assign T_421_0 = 3'h5;
+ assign T_424 = T_421_0 == io_inner_grant_bits_g_type;
+ assign T_426 = 1'h0 | T_424;
+ assign T_428_0 = 1'h0;
+ assign T_428_1 = 1'h1;
+ assign T_432 = T_428_0 == io_inner_grant_bits_g_type;
+ assign T_433 = T_428_1 == io_inner_grant_bits_g_type;
+ assign T_435 = 1'h0 | T_432;
+ assign T_436 = T_435 | T_433;
+ assign T_437 = io_inner_grant_bits_is_builtin_type ? T_426 : T_436;
+ assign T_438 = 1'h1 & T_437;
+ assign T_439 = T_417 & T_438;
+ assign T_443 = T_441 == 2'h3;
+ assign T_445 = 1'h0 & T_443;
+ assign T_448 = T_441 + 1'h1;
+ assign T_449 = T_448[1:0];
+ assign T_450 = T_445 ? 1'h0 : T_449;
+ assign T_451 = T_439 & T_443;
+ assign ignt_data_cnt = T_438 ? T_441 : 1'h0;
+ assign ignt_data_done = T_438 ? T_451 : T_417;
+ assign T_455 = io_outer_acquire_ready & io_outer_acquire_valid;
+ assign T_457 = 1'h1 & io_outer_acquire_bits_is_builtin_type;
+ assign T_460_0 = 3'h3;
+ assign T_463 = T_460_0 == io_outer_acquire_bits_a_type;
+ assign T_465 = 1'h0 | T_463;
+ assign T_466 = T_457 & T_465;
+ assign T_467 = T_455 & T_466;
+ assign T_471 = T_469 == 2'h3;
+ assign T_473 = 1'h0 & T_471;
+ assign T_476 = T_469 + 1'h1;
+ assign T_477 = T_476[1:0];
+ assign T_478 = T_473 ? 1'h0 : T_477;
+ assign T_479 = T_467 & T_471;
+ assign oacq_data_cnt = T_466 ? T_469 : 1'h0;
+ assign oacq_data_done = T_466 ? T_479 : T_455;
+ assign T_482 = io_outer_grant_ready & io_outer_grant_valid;
+ assign T_487_0 = 3'h5;
+ assign T_490 = T_487_0 == io_outer_grant_bits_g_type;
+ assign T_492 = 1'h0 | T_490;
+ assign T_494_0 = 1'h0;
+ assign T_497 = T_494_0 == io_outer_grant_bits_g_type;
+ assign T_499 = 1'h0 | T_497;
+ assign T_500 = io_outer_grant_bits_is_builtin_type ? T_492 : T_499;
+ assign T_501 = 1'h1 & T_500;
+ assign T_502 = T_482 & T_501;
+ assign T_506 = T_504 == 2'h3;
+ assign T_508 = 1'h0 & T_506;
+ assign T_511 = T_504 + 1'h1;
+ assign T_512 = T_511[1:0];
+ assign T_513 = T_508 ? 1'h0 : T_512;
+ assign T_514 = T_502 & T_506;
+ assign T_515 = T_501 ? T_504 : 1'h0;
+ assign ognt_data_done = T_501 ? T_514 : T_482;
+ assign T_523_0 = 3'h2;
+ assign T_523_1 = 3'h3;
+ assign T_523_2 = 3'h4;
+ assign T_528 = T_523_0 == xact_a_type;
+ assign T_529 = T_523_1 == xact_a_type;
+ assign T_530 = T_523_2 == xact_a_type;
+ assign T_532 = 1'h0 | T_528;
+ assign T_533 = T_532 | T_529;
+ assign T_534 = T_533 | T_530;
+ assign pending_outer_write = xact_is_builtin_type & T_534;
+ assign T_540_0 = 3'h2;
+ assign T_540_1 = 3'h3;
+ assign T_540_2 = 3'h4;
+ assign T_545 = T_540_0 == io_inner_acquire_bits_a_type;
+ assign T_546 = T_540_1 == io_inner_acquire_bits_a_type;
+ assign T_547 = T_540_2 == io_inner_acquire_bits_a_type;
+ assign T_549 = 1'h0 | T_545;
+ assign T_550 = T_549 | T_546;
+ assign T_551 = T_550 | T_547;
+ assign pending_outer_write_ = io_inner_acquire_bits_is_builtin_type & T_551;
+ assign T_556_0 = 3'h5;
+ assign T_556_1 = 3'h4;
+ assign T_560 = T_556_0 == io_inner_grant_bits_g_type;
+ assign T_561 = T_556_1 == io_inner_grant_bits_g_type;
+ assign T_563 = 1'h0 | T_560;
+ assign T_564 = T_563 | T_561;
+ assign T_566_0 = 1'h0;
+ assign T_566_1 = 1'h1;
+ assign T_570 = T_566_0 == io_inner_grant_bits_g_type;
+ assign T_571 = T_566_1 == io_inner_grant_bits_g_type;
+ assign T_573 = 1'h0 | T_570;
+ assign T_574 = T_573 | T_571;
+ assign pending_outer_read = io_inner_grant_bits_is_builtin_type ? T_564 : T_574;
+ assign T_594 = 3'h6 == io_inner_acquire_bits_a_type;
+ assign T_595 = T_594 ? 3'h1 : 3'h3;
+ assign T_596 = 3'h5 == io_inner_acquire_bits_a_type;
+ assign T_597 = T_596 ? 3'h1 : T_595;
+ assign T_598 = 3'h4 == io_inner_acquire_bits_a_type;
+ assign T_599 = T_598 ? 3'h4 : T_597;
+ assign T_600 = 3'h3 == io_inner_acquire_bits_a_type;
+ assign T_601 = T_600 ? 3'h3 : T_599;
+ assign T_602 = 3'h2 == io_inner_acquire_bits_a_type;
+ assign T_603 = T_602 ? 3'h3 : T_601;
+ assign T_604 = 3'h1 == io_inner_acquire_bits_a_type;
+ assign T_605 = T_604 ? 3'h5 : T_603;
+ assign T_606 = 3'h0 == io_inner_acquire_bits_a_type;
+ assign T_607 = T_606 ? 3'h4 : T_605;
+ assign T_608 = io_inner_acquire_bits_a_type == 1'h0;
+ assign T_611 = 1'h0 == 1'h0;
+ assign T_612 = T_611 ? 1'h0 : 1'h1;
+ assign T_613 = T_608 ? T_612 : 1'h1;
+ assign T_614 = io_inner_acquire_bits_is_builtin_type ? T_607 : T_613;
+ assign T_623_addr_beat = 1'h0;
+ assign T_623_client_xact_id = io_inner_acquire_bits_client_xact_id;
+ assign T_623_manager_xact_id = 1'h1;
+ assign T_623_is_builtin_type = io_inner_acquire_bits_is_builtin_type;
+ assign T_623_g_type = T_614;
+ assign T_623_data = 1'h0;
+ assign T_623_client_id = io_inner_acquire_bits_client_id;
+ assign T_634_0 = 3'h5;
+ assign T_634_1 = 3'h4;
+ assign T_638 = T_634_0 == T_623_g_type;
+ assign T_639 = T_634_1 == T_623_g_type;
+ assign T_641 = 1'h0 | T_638;
+ assign T_642 = T_641 | T_639;
+ assign T_644_0 = 1'h0;
+ assign T_644_1 = 1'h1;
+ assign T_648 = T_644_0 == T_623_g_type;
+ assign T_649 = T_644_1 == T_623_g_type;
+ assign T_651 = 1'h0 | T_648;
+ assign T_652 = T_651 | T_649;
+ assign pending_outer_read_ = T_623_is_builtin_type ? T_642 : T_652;
+ assign T_658_0 = 3'h2;
+ assign T_658_1 = 3'h0;
+ assign T_658_2 = 3'h4;
+ assign T_663 = T_658_0 == xact_a_type;
+ assign T_664 = T_658_1 == xact_a_type;
+ assign T_665 = T_658_2 == xact_a_type;
+ assign T_667 = 1'h0 | T_663;
+ assign T_668 = T_667 | T_664;
+ assign T_669 = T_668 | T_665;
+ assign subblock_type = xact_is_builtin_type & T_669;
+ assign T_671 = xact_addr_block == io_inner_acquire_bits_addr_block;
+ assign T_672 = state != 1'h0;
+ assign T_673 = T_671 & T_672;
+ assign T_675 = collect_iacq_data == 1'h0;
+ assign T_676 = T_673 & T_675;
+ assign T_677 = xact_addr_block == io_inner_acquire_bits_addr_block;
+ assign T_678 = T_677 & collect_iacq_data;
+ assign T_679 = xact_addr_block == io_inner_release_bits_addr_block;
+ assign T_681 = io_inner_release_bits_voluntary == 1'h0;
+ assign T_682 = T_679 & T_681;
+ assign T_683 = state == 1'h1;
+ assign T_684 = T_682 & T_683;
+ assign GEN_8 = $signed(16'hffff);
+ assign T_689 = $unsigned(GEN_8);
+ assign T_695 = {1'h0,3'h7};
+ assign T_696 = {1'h0,1'h1};
+ assign T_697 = {T_695,T_696};
+ assign T_699 = {1'h0,1'h1};
+ assign T_700 = {3'h7,T_699};
+ assign T_702 = {T_689,1'h1};
+ assign T_704 = {T_689,1'h1};
+ assign T_706 = {1'h0,3'h7};
+ assign T_707 = {1'h0,1'h1};
+ assign T_708 = {T_706,T_707};
+ assign T_710 = {5'h0,1'h1};
+ assign T_712 = {5'h1,1'h1};
+ assign T_713 = 3'h6 == 3'h3;
+ assign T_714 = T_713 ? T_712 : 1'h0;
+ assign T_715 = 3'h5 == 3'h3;
+ assign T_716 = T_715 ? T_710 : T_714;
+ assign T_717 = 3'h4 == 3'h3;
+ assign T_718 = T_717 ? T_708 : T_716;
+ assign T_719 = 3'h3 == 3'h3;
+ assign T_720 = T_719 ? T_704 : T_718;
+ assign T_721 = 3'h2 == 3'h3;
+ assign T_722 = T_721 ? T_702 : T_720;
+ assign T_723 = 3'h1 == 3'h3;
+ assign T_724 = T_723 ? T_700 : T_722;
+ assign T_725 = 3'h0 == 3'h3;
+ assign T_726 = T_725 ? T_697 : T_724;
+ assign oacq_probe_addr_block = io_inner_release_bits_addr_block;
+ assign oacq_probe_client_xact_id = 1'h1;
+ assign oacq_probe_addr_beat = io_inner_release_bits_addr_beat;
+ assign oacq_probe_is_builtin_type = 1'h1;
+ assign oacq_probe_a_type = 3'h3;
+ assign oacq_probe_union = T_726;
+ assign oacq_probe_data = io_inner_release_bits_data;
+ assign T_744 = xact_union[12:9];
+ assign T_745 = T_744[3];
+ assign T_747 = 1'h1 << T_745;
+ assign T_749 = xact_a_type == 3'h4;
+ assign T_750 = xact_is_builtin_type & T_749;
+ assign T_751 = T_747[0];
+ assign T_752 = T_747[1];
+ assign T_754_0 = T_751;
+ assign T_754_1 = T_752;
+ assign T_759 = 8'h0 - T_754_0;
+ assign T_760 = T_759[7:0];
+ assign T_762 = 8'h0 - T_754_1;
+ assign T_763 = T_762[7:0];
+ assign T_765_0 = T_760;
+ assign T_765_1 = T_763;
+ assign T_769 = {T_765_1,T_765_0};
+ assign T_771 = xact_a_type == 3'h3;
+ assign T_772 = xact_is_builtin_type & T_771;
+ assign T_774 = xact_a_type == 3'h2;
+ assign T_775 = xact_is_builtin_type & T_774;
+ assign T_776 = T_772 | T_775;
+ assign T_777 = xact_union[16:1];
+ assign T_779 = T_776 ? T_777 : 16'h0;
+ assign T_780 = T_750 ? T_769 : T_779;
+ assign T_788 = {1'h0,3'h7};
+ assign T_789 = {1'h0,1'h1};
+ assign T_790 = {T_788,T_789};
+ assign T_792 = {1'h0,1'h1};
+ assign T_793 = {3'h7,T_792};
+ assign T_795 = {T_780,1'h1};
+ assign T_797 = {T_780,1'h1};
+ assign T_799 = {1'h0,3'h7};
+ assign T_800 = {1'h0,1'h1};
+ assign T_801 = {T_799,T_800};
+ assign T_803 = {5'h0,1'h1};
+ assign T_805 = {5'h1,1'h1};
+ assign T_806 = 3'h6 == 3'h2;
+ assign T_807 = T_806 ? T_805 : 1'h0;
+ assign T_808 = 3'h5 == 3'h2;
+ assign T_809 = T_808 ? T_803 : T_807;
+ assign T_810 = 3'h4 == 3'h2;
+ assign T_811 = T_810 ? T_801 : T_809;
+ assign T_812 = 3'h3 == 3'h2;
+ assign T_813 = T_812 ? T_797 : T_811;
+ assign T_814 = 3'h2 == 3'h2;
+ assign T_815 = T_814 ? T_795 : T_813;
+ assign T_816 = 3'h1 == 3'h2;
+ assign T_817 = T_816 ? T_793 : T_815;
+ assign T_818 = 3'h0 == 3'h2;
+ assign T_819 = T_818 ? T_790 : T_817;
+ assign oacq_write_beat_addr_block = xact_addr_block;
+ assign oacq_write_beat_client_xact_id = 1'h1;
+ assign oacq_write_beat_addr_beat = xact_addr_beat;
+ assign oacq_write_beat_is_builtin_type = 1'h1;
+ assign oacq_write_beat_a_type = 3'h2;
+ assign oacq_write_beat_union = T_819;
+ assign oacq_write_beat_data = xact_data_buffer_0;
+ assign T_846 = {1'h0,3'h7};
+ assign T_847 = {1'h0,1'h1};
+ assign T_848 = {T_846,T_847};
+ assign T_850 = {1'h0,1'h1};
+ assign T_851 = {3'h7,T_850};
+ assign GEN_0 = GEN_45 ? xact_wmask_buffer_3 : GEN_46 ? xact_wmask_buffer_2 : GEN_47 ? xact_wmask_buffer_1 : xact_wmask_buffer_0;
+ assign T_853 = {GEN_0,1'h1};
+ assign GEN_1 = GEN_48 ? xact_wmask_buffer_3 : GEN_49 ? xact_wmask_buffer_2 : GEN_50 ? xact_wmask_buffer_1 : xact_wmask_buffer_0;
+ assign T_855 = {GEN_1,1'h1};
+ assign T_857 = {1'h0,3'h7};
+ assign T_858 = {1'h0,1'h1};
+ assign T_859 = {T_857,T_858};
+ assign T_861 = {5'h0,1'h1};
+ assign T_863 = {5'h1,1'h1};
+ assign T_864 = 3'h6 == 3'h3;
+ assign T_865 = T_864 ? T_863 : 1'h0;
+ assign T_866 = 3'h5 == 3'h3;
+ assign T_867 = T_866 ? T_861 : T_865;
+ assign T_868 = 3'h4 == 3'h3;
+ assign T_869 = T_868 ? T_859 : T_867;
+ assign T_870 = 3'h3 == 3'h3;
+ assign T_871 = T_870 ? T_855 : T_869;
+ assign T_872 = 3'h2 == 3'h3;
+ assign T_873 = T_872 ? T_853 : T_871;
+ assign T_874 = 3'h1 == 3'h3;
+ assign T_875 = T_874 ? T_851 : T_873;
+ assign T_876 = 3'h0 == 3'h3;
+ assign T_877 = T_876 ? T_848 : T_875;
+ assign oacq_write_block_addr_block = xact_addr_block;
+ assign oacq_write_block_client_xact_id = 1'h1;
+ assign oacq_write_block_addr_beat = oacq_data_cnt;
+ assign oacq_write_block_is_builtin_type = 1'h1;
+ assign oacq_write_block_a_type = 3'h3;
+ assign oacq_write_block_union = T_877;
+ assign oacq_write_block_data = GEN_2;
+ assign GEN_2 = GEN_51 ? xact_data_buffer_3 : GEN_52 ? xact_data_buffer_2 : GEN_53 ? xact_data_buffer_1 : xact_data_buffer_0;
+ assign T_895 = xact_union[12:9];
+ assign T_896 = xact_union[8:6];
+ assign T_904 = {T_895,T_896};
+ assign T_905 = {5'h0,1'h0};
+ assign T_906 = {T_904,T_905};
+ assign T_908 = {5'h0,1'h0};
+ assign T_909 = {T_896,T_908};
+ assign T_911 = {1'h0,1'h0};
+ assign T_913 = {1'h0,1'h0};
+ assign T_915 = {T_895,T_896};
+ assign T_916 = {5'h0,1'h0};
+ assign T_917 = {T_915,T_916};
+ assign T_919 = {5'h0,1'h0};
+ assign T_921 = {5'h1,1'h0};
+ assign T_922 = 3'h6 == 3'h0;
+ assign T_923 = T_922 ? T_921 : 1'h0;
+ assign T_924 = 3'h5 == 3'h0;
+ assign T_925 = T_924 ? T_919 : T_923;
+ assign T_926 = 3'h4 == 3'h0;
+ assign T_927 = T_926 ? T_917 : T_925;
+ assign T_928 = 3'h3 == 3'h0;
+ assign T_929 = T_928 ? T_913 : T_927;
+ assign T_930 = 3'h2 == 3'h0;
+ assign T_931 = T_930 ? T_911 : T_929;
+ assign T_932 = 3'h1 == 3'h0;
+ assign T_933 = T_932 ? T_909 : T_931;
+ assign T_934 = 3'h0 == 3'h0;
+ assign T_935 = T_934 ? T_906 : T_933;
+ assign oacq_read_beat_addr_block = xact_addr_block;
+ assign oacq_read_beat_client_xact_id = 1'h1;
+ assign oacq_read_beat_addr_beat = xact_addr_beat;
+ assign oacq_read_beat_is_builtin_type = 1'h1;
+ assign oacq_read_beat_a_type = 3'h0;
+ assign oacq_read_beat_union = T_935;
+ assign oacq_read_beat_data = 1'h0;
+ assign T_962 = {1'h0,3'h7};
+ assign T_963 = {5'h0,1'h1};
+ assign T_964 = {T_962,T_963};
+ assign T_966 = {5'h0,1'h1};
+ assign T_967 = {3'h7,T_966};
+ assign T_969 = {1'h0,1'h1};
+ assign T_971 = {1'h0,1'h1};
+ assign T_973 = {1'h0,3'h7};
+ assign T_974 = {5'h0,1'h1};
+ assign T_975 = {T_973,T_974};
+ assign T_977 = {5'h0,1'h1};
+ assign T_979 = {5'h1,1'h1};
+ assign T_980 = 3'h6 == 3'h1;
+ assign T_981 = T_980 ? T_979 : 1'h0;
+ assign T_982 = 3'h5 == 3'h1;
+ assign T_983 = T_982 ? T_977 : T_981;
+ assign T_984 = 3'h4 == 3'h1;
+ assign T_985 = T_984 ? T_975 : T_983;
+ assign T_986 = 3'h3 == 3'h1;
+ assign T_987 = T_986 ? T_971 : T_985;
+ assign T_988 = 3'h2 == 3'h1;
+ assign T_989 = T_988 ? T_969 : T_987;
+ assign T_990 = 3'h1 == 3'h1;
+ assign T_991 = T_990 ? T_967 : T_989;
+ assign T_992 = 3'h0 == 3'h1;
+ assign T_993 = T_992 ? T_964 : T_991;
+ assign oacq_read_block_addr_block = xact_addr_block;
+ assign oacq_read_block_client_xact_id = 1'h1;
+ assign oacq_read_block_addr_beat = 1'h0;
+ assign oacq_read_block_is_builtin_type = 1'h1;
+ assign oacq_read_block_a_type = 3'h1;
+ assign oacq_read_block_union = T_993;
+ assign oacq_read_block_data = 1'h0;
+ assign T_1011 = state == 1'h1;
+ assign T_1012 = state == 2'h3;
+ assign T_1013_addr_block = subblock_type ? oacq_write_beat_addr_block : oacq_write_block_addr_block;
+ assign T_1013_client_xact_id = subblock_type ? oacq_write_beat_client_xact_id : oacq_write_block_client_xact_id;
+ assign T_1013_addr_beat = subblock_type ? oacq_write_beat_addr_beat : oacq_write_block_addr_beat;
+ assign T_1013_is_builtin_type = subblock_type ? oacq_write_beat_is_builtin_type : oacq_write_block_is_builtin_type;
+ assign T_1013_a_type = subblock_type ? oacq_write_beat_a_type : oacq_write_block_a_type;
+ assign T_1013_union = subblock_type ? oacq_write_beat_union : oacq_write_block_union;
+ assign T_1013_data = subblock_type ? oacq_write_beat_data : oacq_write_block_data;
+ assign T_1021_addr_block = subblock_type ? oacq_read_beat_addr_block : oacq_read_block_addr_block;
+ assign T_1021_client_xact_id = subblock_type ? oacq_read_beat_client_xact_id : oacq_read_block_client_xact_id;
+ assign T_1021_addr_beat = subblock_type ? oacq_read_beat_addr_beat : oacq_read_block_addr_beat;
+ assign T_1021_is_builtin_type = subblock_type ? oacq_read_beat_is_builtin_type : oacq_read_block_is_builtin_type;
+ assign T_1021_a_type = subblock_type ? oacq_read_beat_a_type : oacq_read_block_a_type;
+ assign T_1021_union = subblock_type ? oacq_read_beat_union : oacq_read_block_union;
+ assign T_1021_data = subblock_type ? oacq_read_beat_data : oacq_read_block_data;
+ assign T_1029_addr_block = T_1012 ? T_1013_addr_block : T_1021_addr_block;
+ assign T_1029_client_xact_id = T_1012 ? T_1013_client_xact_id : T_1021_client_xact_id;
+ assign T_1029_addr_beat = T_1012 ? T_1013_addr_beat : T_1021_addr_beat;
+ assign T_1029_is_builtin_type = T_1012 ? T_1013_is_builtin_type : T_1021_is_builtin_type;
+ assign T_1029_a_type = T_1012 ? T_1013_a_type : T_1021_a_type;
+ assign T_1029_union = T_1012 ? T_1013_union : T_1021_union;
+ assign T_1029_data = T_1012 ? T_1013_data : T_1021_data;
+ assign T_1037_addr_block = T_1011 ? oacq_probe_addr_block : T_1029_addr_block;
+ assign T_1037_client_xact_id = T_1011 ? oacq_probe_client_xact_id : T_1029_client_xact_id;
+ assign T_1037_addr_beat = T_1011 ? oacq_probe_addr_beat : T_1029_addr_beat;
+ assign T_1037_is_builtin_type = T_1011 ? oacq_probe_is_builtin_type : T_1029_is_builtin_type;
+ assign T_1037_a_type = T_1011 ? oacq_probe_a_type : T_1029_a_type;
+ assign T_1037_union = T_1011 ? oacq_probe_union : T_1029_union;
+ assign T_1037_data = T_1011 ? oacq_probe_data : T_1029_data;
+ assign T_1054 = 3'h4 == xact_a_type;
+ assign T_1055 = T_1054 ? 1'h0 : 2'h2;
+ assign T_1056 = 3'h6 == xact_a_type;
+ assign T_1057 = T_1056 ? 1'h0 : T_1055;
+ assign T_1058 = 3'h5 == xact_a_type;
+ assign T_1059 = T_1058 ? 2'h2 : T_1057;
+ assign T_1060 = 3'h2 == xact_a_type;
+ assign T_1061 = T_1060 ? 1'h0 : T_1059;
+ assign T_1062 = 3'h0 == xact_a_type;
+ assign T_1063 = T_1062 ? 2'h2 : T_1061;
+ assign T_1064 = 3'h3 == xact_a_type;
+ assign T_1065 = T_1064 ? 1'h0 : T_1063;
+ assign T_1066 = 3'h1 == xact_a_type;
+ assign T_1067 = T_1066 ? 2'h2 : T_1065;
+ assign T_1068 = 1'h1 == xact_a_type;
+ assign T_1069 = T_1068 ? 1'h0 : 2'h2;
+ assign T_1070 = 1'h0 == xact_a_type;
+ assign T_1071 = T_1070 ? 1'h1 : T_1069;
+ assign T_1072 = xact_is_builtin_type ? T_1067 : T_1071;
+ assign T_1077_addr_block = xact_addr_block;
+ assign T_1077_p_type = T_1072;
+ assign T_1077_client_id = 1'h0;
+ assign T_1100 = 3'h6 == xact_a_type;
+ assign T_1101 = T_1100 ? 3'h1 : 3'h3;
+ assign T_1102 = 3'h5 == xact_a_type;
+ assign T_1103 = T_1102 ? 3'h1 : T_1101;
+ assign T_1104 = 3'h4 == xact_a_type;
+ assign T_1105 = T_1104 ? 3'h4 : T_1103;
+ assign T_1106 = 3'h3 == xact_a_type;
+ assign T_1107 = T_1106 ? 3'h3 : T_1105;
+ assign T_1108 = 3'h2 == xact_a_type;
+ assign T_1109 = T_1108 ? 3'h3 : T_1107;
+ assign T_1110 = 3'h1 == xact_a_type;
+ assign T_1111 = T_1110 ? 3'h5 : T_1109;
+ assign T_1112 = 3'h0 == xact_a_type;
+ assign T_1113 = T_1112 ? 3'h4 : T_1111;
+ assign T_1114 = xact_a_type == 1'h0;
+ assign T_1117 = 1'h0 == 1'h0;
+ assign T_1118 = T_1117 ? 1'h0 : 1'h1;
+ assign T_1119 = T_1114 ? T_1118 : 1'h1;
+ assign T_1120 = xact_is_builtin_type ? T_1113 : T_1119;
+ assign T_1129_addr_beat = 1'h0;
+ assign T_1129_client_xact_id = xact_client_xact_id;
+ assign T_1129_manager_xact_id = 1'h1;
+ assign T_1129_is_builtin_type = xact_is_builtin_type;
+ assign T_1129_g_type = T_1120;
+ assign T_1129_data = 1'h0;
+ assign T_1129_client_id = xact_client_id;
+ assign T_1140 = state != 1'h0;
+ assign T_1141 = T_1140 & collect_iacq_data;
+ assign T_1142 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_1143 = T_1141 & T_1142;
+ assign T_1144 = io_inner_acquire_bits_client_id != xact_client_id;
+ assign T_1145 = T_1143 & T_1144;
+ assign T_1147 = T_1145 == 1'h0;
+ assign T_1149 = reset == 1'h0;
+ assign T_1151 = T_1147 == 1'h0;
+ assign T_1153 = reset == 1'h0;
+ assign T_1154 = state != 1'h0;
+ assign T_1155 = T_1154 & collect_iacq_data;
+ assign T_1156 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_1157 = T_1155 & T_1156;
+ assign T_1158 = io_inner_acquire_bits_client_xact_id != xact_client_xact_id;
+ assign T_1159 = T_1157 & T_1158;
+ assign T_1161 = T_1159 == 1'h0;
+ assign T_1163 = reset == 1'h0;
+ assign T_1165 = T_1161 == 1'h0;
+ assign T_1167 = reset == 1'h0;
+ assign T_1168 = state == 1'h0;
+ assign T_1169 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_1170 = T_1168 & T_1169;
+ assign T_1172 = 1'h1 & io_inner_acquire_bits_is_builtin_type;
+ assign T_1175_0 = 3'h3;
+ assign T_1178 = T_1175_0 == io_inner_acquire_bits_a_type;
+ assign T_1180 = 1'h0 | T_1178;
+ assign T_1181 = T_1172 & T_1180;
+ assign T_1182 = T_1170 & T_1181;
+ assign T_1184 = io_inner_acquire_bits_addr_beat != 1'h0;
+ assign T_1185 = T_1182 & T_1184;
+ assign T_1187 = T_1185 == 1'h0;
+ assign T_1189 = reset == 1'h0;
+ assign T_1191 = T_1187 == 1'h0;
+ assign T_1193 = reset == 1'h0;
+ assign GEN_3 = io_inner_acquire_bits_data;
+ assign T_1197 = io_inner_acquire_bits_union[12:9];
+ assign T_1198 = T_1197[3];
+ assign T_1200 = 1'h1 << T_1198;
+ assign T_1202 = io_inner_acquire_bits_a_type == 3'h4;
+ assign T_1203 = io_inner_acquire_bits_is_builtin_type & T_1202;
+ assign T_1204 = T_1200[0];
+ assign T_1205 = T_1200[1];
+ assign T_1207_0 = T_1204;
+ assign T_1207_1 = T_1205;
+ assign T_1212 = 8'h0 - T_1207_0;
+ assign T_1213 = T_1212[7:0];
+ assign T_1215 = 8'h0 - T_1207_1;
+ assign T_1216 = T_1215[7:0];
+ assign T_1218_0 = T_1213;
+ assign T_1218_1 = T_1216;
+ assign T_1222 = {T_1218_1,T_1218_0};
+ assign T_1224 = io_inner_acquire_bits_a_type == 3'h3;
+ assign T_1225 = io_inner_acquire_bits_is_builtin_type & T_1224;
+ assign T_1227 = io_inner_acquire_bits_a_type == 3'h2;
+ assign T_1228 = io_inner_acquire_bits_is_builtin_type & T_1227;
+ assign T_1229 = T_1225 | T_1228;
+ assign T_1230 = io_inner_acquire_bits_union[16:1];
+ assign T_1232 = T_1229 ? T_1230 : 16'h0;
+ assign T_1233 = T_1203 ? T_1222 : T_1232;
+ assign GEN_4 = T_1233;
+ assign T_1236 = 1'h1 << io_inner_acquire_bits_addr_beat;
+ assign T_1237 = iacq_data_valid | T_1236;
+ assign T_1238 = ~ iacq_data_valid;
+ assign T_1239 = T_1238 | T_1236;
+ assign T_1240 = ~ T_1239;
+ assign T_1241 = 1'h1 ? T_1237 : T_1240;
+ assign T_1245 = 1'h0 == state;
+ assign GEN_5 = io_inner_acquire_bits_data;
+ assign T_1251 = io_inner_acquire_bits_union[12:9];
+ assign T_1252 = T_1251[3];
+ assign T_1254 = 1'h1 << T_1252;
+ assign T_1256 = io_inner_acquire_bits_a_type == 3'h4;
+ assign T_1257 = io_inner_acquire_bits_is_builtin_type & T_1256;
+ assign T_1258 = T_1254[0];
+ assign T_1259 = T_1254[1];
+ assign T_1261_0 = T_1258;
+ assign T_1261_1 = T_1259;
+ assign T_1266 = 8'h0 - T_1261_0;
+ assign T_1267 = T_1266[7:0];
+ assign T_1269 = 8'h0 - T_1261_1;
+ assign T_1270 = T_1269[7:0];
+ assign T_1272_0 = T_1267;
+ assign T_1272_1 = T_1270;
+ assign T_1276 = {T_1272_1,T_1272_0};
+ assign T_1278 = io_inner_acquire_bits_a_type == 3'h3;
+ assign T_1279 = io_inner_acquire_bits_is_builtin_type & T_1278;
+ assign T_1281 = io_inner_acquire_bits_a_type == 3'h2;
+ assign T_1282 = io_inner_acquire_bits_is_builtin_type & T_1281;
+ assign T_1283 = T_1279 | T_1282;
+ assign T_1284 = io_inner_acquire_bits_union[16:1];
+ assign T_1286 = T_1283 ? T_1284 : 16'h0;
+ assign T_1287 = T_1257 ? T_1276 : T_1286;
+ assign GEN_6 = T_1287;
+ assign T_1289 = 1'h1 & io_inner_acquire_bits_is_builtin_type;
+ assign T_1292_0 = 3'h3;
+ assign T_1295 = T_1292_0 == io_inner_acquire_bits_a_type;
+ assign T_1297 = 1'h0 | T_1295;
+ assign T_1298 = T_1289 & T_1297;
+ assign T_1303_0 = 3'h2;
+ assign T_1303_1 = 3'h3;
+ assign T_1303_2 = 3'h4;
+ assign T_1308 = T_1303_0 == io_inner_acquire_bits_a_type;
+ assign T_1309 = T_1303_1 == io_inner_acquire_bits_a_type;
+ assign T_1310 = T_1303_2 == io_inner_acquire_bits_a_type;
+ assign T_1312 = 1'h0 | T_1308;
+ assign T_1313 = T_1312 | T_1309;
+ assign T_1314 = T_1313 | T_1310;
+ assign T_1315 = io_inner_acquire_bits_is_builtin_type & T_1314;
+ assign T_1316 = T_1315 << io_inner_acquire_bits_addr_beat;
+ assign T_1318 = mask_incoherent != 1'h0;
+ assign T_1319 = mask_incoherent[0];
+ assign T_1320 = mask_incoherent[1];
+ assign T_1321 = mask_incoherent[2];
+ assign T_1322 = mask_incoherent[3];
+ assign T_1324 = {1'h0,T_1320};
+ assign T_1325 = T_1319 + T_1324;
+ assign T_1326 = T_1325[1:0];
+ assign T_1329 = {1'h0,T_1322};
+ assign T_1330 = T_1321 + T_1329;
+ assign T_1331 = T_1330[1:0];
+ assign T_1332 = {1'h0,T_1331};
+ assign T_1333 = T_1326 + T_1332;
+ assign T_1334 = T_1333[2:0];
+ assign T_1335 = pending_outer_read_ ? 2'h2 : 3'h4;
+ assign T_1336 = pending_outer_write_ ? 2'h3 : T_1335;
+ assign T_1337 = T_1318 ? 1'h1 : T_1336;
+ assign T_1338 = 1'h1 == state;
+ assign T_1340 = pending_probes != 1'h0;
+ assign T_1342 = 1'h1 << 1'h0;
+ assign T_1343 = ~ T_1342;
+ assign T_1344 = pending_probes & T_1343;
+ assign T_1346_0 = 1'h0;
+ assign T_1346_1 = 1'h1;
+ assign T_1346_2 = 2'h2;
+ assign T_1351 = T_1346_0 == io_inner_release_bits_r_type;
+ assign T_1352 = T_1346_1 == io_inner_release_bits_r_type;
+ assign T_1353 = T_1346_2 == io_inner_release_bits_r_type;
+ assign T_1355 = 1'h0 | T_1351;
+ assign T_1356 = T_1355 | T_1352;
+ assign T_1357 = T_1356 | T_1353;
+ assign T_1359 = T_1357 == 1'h0;
+ assign T_1360 = T_1359 | io_outer_acquire_ready;
+ assign T_1362_0 = 1'h0;
+ assign T_1362_1 = 1'h1;
+ assign T_1362_2 = 2'h2;
+ assign T_1367 = T_1362_0 == io_inner_release_bits_r_type;
+ assign T_1368 = T_1362_1 == io_inner_release_bits_r_type;
+ assign T_1369 = T_1362_2 == io_inner_release_bits_r_type;
+ assign T_1371 = 1'h0 | T_1367;
+ assign T_1372 = T_1371 | T_1368;
+ assign T_1373 = T_1372 | T_1369;
+ assign T_1377 = release_count - 1'h1;
+ assign T_1378 = T_1377[0:0];
+ assign T_1380 = release_count == 1'h1;
+ assign T_1381 = pending_outer_read ? 2'h2 : 3'h4;
+ assign T_1382 = pending_outer_write ? 2'h3 : T_1381;
+ assign T_1384 = T_1373 == 1'h0;
+ assign T_1386 = release_count - 1'h1;
+ assign T_1387 = T_1386[0:0];
+ assign T_1389 = release_count == 1'h1;
+ assign T_1390 = pending_outer_read ? 2'h2 : 3'h4;
+ assign T_1391 = pending_outer_write ? 2'h3 : T_1390;
+ assign T_1392 = 2'h3 == state;
+ assign T_1394 = pending_ognt_ack == 1'h0;
+ assign T_1396 = collect_iacq_data == 1'h0;
+ assign T_1397 = iacq_data_valid >> oacq_data_cnt;
+ assign T_1398 = T_1397[0];
+ assign T_1399 = T_1396 | T_1398;
+ assign T_1400 = T_1394 & T_1399;
+ assign T_1402 = pending_outer_read ? 2'h2 : 3'h5;
+ assign T_1403 = 2'h2 == state;
+ assign T_1405 = pending_ognt_ack == 1'h0;
+ assign T_1406 = io_outer_acquire_ready & io_outer_acquire_valid;
+ assign T_1407 = 3'h5 == state;
+ assign T_1410 = 1'h0 == 1'h0;
+ assign T_1412 = io_inner_grant_bits_g_type == 3'h0;
+ assign T_1413 = io_inner_grant_bits_is_builtin_type & T_1412;
+ assign T_1415 = T_1413 == 1'h0;
+ assign T_1416 = T_1410 & T_1415;
+ assign T_1417 = T_1416 ? 3'h6 : 1'h0;
+ assign T_1418 = 3'h4 == state;
+ assign T_1422 = 1'h0 == 1'h0;
+ assign T_1424 = io_inner_grant_bits_g_type == 3'h0;
+ assign T_1425 = io_inner_grant_bits_is_builtin_type & T_1424;
+ assign T_1427 = T_1425 == 1'h0;
+ assign T_1428 = T_1422 & T_1427;
+ assign T_1429 = T_1428 ? 3'h6 : 1'h0;
+ assign T_1430 = 3'h6 == state;
+ assign GEN_9 = T_325 & T_327;
+ assign GEN_10 = T_1149 & T_1151;
+ assign GEN_11 = T_1163 & T_1165;
+ assign GEN_12 = T_1189 & T_1191;
+ assign GEN_13 = 1'h0 == 1'h0;
+ assign GEN_14 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_15 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_16 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_17 = 1'h1 == 1'h0;
+ assign GEN_18 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_19 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_20 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_21 = 2'h2 == 1'h0;
+ assign GEN_22 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_23 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_24 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_25 = 2'h3 == 1'h0;
+ assign GEN_26 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_27 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_28 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_29 = 1'h0 == 1'h0;
+ assign GEN_30 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_31 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_32 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_33 = 1'h1 == 1'h0;
+ assign GEN_34 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_35 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_36 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_37 = 2'h2 == 1'h0;
+ assign GEN_38 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_39 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_40 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_41 = 2'h3 == 1'h0;
+ assign GEN_42 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_43 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_44 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_45 = 2'h3 == oacq_data_cnt;
+ assign GEN_46 = 2'h2 == oacq_data_cnt;
+ assign GEN_47 = 1'h1 == oacq_data_cnt;
+ assign GEN_48 = 2'h3 == oacq_data_cnt;
+ assign GEN_49 = 2'h2 == oacq_data_cnt;
+ assign GEN_50 = 1'h1 == oacq_data_cnt;
+ assign GEN_51 = 2'h3 == oacq_data_cnt;
+ assign GEN_52 = 2'h2 == oacq_data_cnt;
+ assign GEN_53 = 1'h1 == oacq_data_cnt;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ state = {1{$random}};
+ xact_addr_block = {1{$random}};
+ xact_client_xact_id = {1{$random}};
+ xact_addr_beat = {1{$random}};
+ xact_is_builtin_type = {1{$random}};
+ xact_a_type = {1{$random}};
+ xact_union = {1{$random}};
+ xact_data_buffer_0 = {1{$random}};
+ xact_data_buffer_1 = {1{$random}};
+ xact_data_buffer_2 = {1{$random}};
+ xact_data_buffer_3 = {1{$random}};
+ xact_wmask_buffer_0 = {1{$random}};
+ xact_wmask_buffer_1 = {1{$random}};
+ xact_wmask_buffer_2 = {1{$random}};
+ xact_wmask_buffer_3 = {1{$random}};
+ xact_client_id = {1{$random}};
+ release_count = {1{$random}};
+ pending_probes = {1{$random}};
+ collect_iacq_data = {1{$random}};
+ iacq_data_valid = {1{$random}};
+ T_371 = {1{$random}};
+ T_403 = {1{$random}};
+ T_441 = {1{$random}};
+ T_469 = {1{$random}};
+ T_504 = {1{$random}};
+ pending_ognt_ack = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1430) begin
+ if(io_inner_finish_valid) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1418) begin
+ if(io_inner_grant_ready) begin
+ state <= T_1429;
+ end else begin
+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
+ end else begin
+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end
+ end else begin
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+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end else begin
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+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
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+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
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+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
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+ end
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+ end
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+ state <= T_1402;
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ end else begin
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
+ end else begin
+ ;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ end else begin
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end
+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1418) begin
+ if(io_inner_grant_ready) begin
+ state <= T_1429;
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+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
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+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
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+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end
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+ end
+ end else begin
+ if(T_1392) begin
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+ state <= T_1402;
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ if(T_1380) begin
+ state <= T_1382;
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ end
+ end else begin
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
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+ end
+ end else begin
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+ if(T_1406) begin
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ state <= T_1337;
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+ end
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ state <= T_1337;
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+ end
+ end else begin
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
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+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
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+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1382;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_addr_block <= io_inner_acquire_bits_addr_block;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_client_xact_id <= io_inner_acquire_bits_client_xact_id;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_addr_beat <= io_inner_acquire_bits_addr_beat;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_is_builtin_type <= io_inner_acquire_bits_is_builtin_type;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_a_type <= io_inner_acquire_bits_a_type;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_union <= io_inner_acquire_bits_union;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_13) begin
+ xact_data_buffer_0 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_14) begin
+ xact_data_buffer_0 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_15) begin
+ xact_data_buffer_0 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_16) begin
+ xact_data_buffer_0 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_17) begin
+ xact_data_buffer_1 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_18) begin
+ xact_data_buffer_1 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_19) begin
+ xact_data_buffer_1 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_20) begin
+ xact_data_buffer_1 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_21) begin
+ xact_data_buffer_2 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_22) begin
+ xact_data_buffer_2 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_23) begin
+ xact_data_buffer_2 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_24) begin
+ xact_data_buffer_2 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_25) begin
+ xact_data_buffer_3 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_26) begin
+ xact_data_buffer_3 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_27) begin
+ xact_data_buffer_3 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_28) begin
+ xact_data_buffer_3 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_29) begin
+ xact_wmask_buffer_0 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_30) begin
+ xact_wmask_buffer_0 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_31) begin
+ xact_wmask_buffer_0 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_32) begin
+ xact_wmask_buffer_0 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_33) begin
+ xact_wmask_buffer_1 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_34) begin
+ xact_wmask_buffer_1 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_35) begin
+ xact_wmask_buffer_1 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_36) begin
+ xact_wmask_buffer_1 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_37) begin
+ xact_wmask_buffer_2 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_38) begin
+ xact_wmask_buffer_2 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_39) begin
+ xact_wmask_buffer_2 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_40) begin
+ xact_wmask_buffer_2 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_41) begin
+ xact_wmask_buffer_3 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_42) begin
+ xact_wmask_buffer_3 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_43) begin
+ xact_wmask_buffer_3 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_44) begin
+ xact_wmask_buffer_3 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_client_id <= io_inner_acquire_bits_client_id;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ release_count <= 1'h0;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ release_count <= T_1387;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ release_count <= T_1378;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ pending_probes <= 1'h0;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_probe_ready) begin
+ pending_probes <= T_1344;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ pending_probes <= mask_incoherent;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ pending_probes <= mask_incoherent;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ collect_iacq_data <= 1'h0;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ collect_iacq_data <= T_1298;
+ end else begin
+ if(collect_iacq_data) begin
+ if(iacq_data_done) begin
+ collect_iacq_data <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(iacq_data_done) begin
+ collect_iacq_data <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ iacq_data_valid <= 4'h0;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ iacq_data_valid <= T_1316;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ iacq_data_valid <= T_1241;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ iacq_data_valid <= T_1241;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ T_371 <= 2'h0;
+ end else begin
+ if(T_369) begin
+ T_371 <= T_380;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_403 <= 2'h0;
+ end else begin
+ if(T_401) begin
+ T_403 <= T_412;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_441 <= 2'h0;
+ end else begin
+ if(T_439) begin
+ T_441 <= T_450;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_469 <= 2'h0;
+ end else begin
+ if(T_467) begin
+ T_469 <= T_478;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_504 <= 2'h0;
+ end else begin
+ if(T_502) begin
+ T_504 <= T_513;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ pending_ognt_ack <= 1'h1;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ pending_ognt_ack <= 1'h1;
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ pending_ognt_ack <= 1'h1;
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ `ifndef SYNTHESIS
+ if(GEN_9 & T_329) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_325 & T_327) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_10 & T_1153) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_1149 & T_1151) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_11 & T_1167) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_1163 & T_1165) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_12 & T_1193) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_1189 & T_1191) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ end
+endmodule
+module BroadcastAcquireTracker_27(
+ input clk,
+ input reset,
+ output io_inner_acquire_ready,
+ input io_inner_acquire_valid,
+ input [25:0] io_inner_acquire_bits_addr_block,
+ input [1:0] io_inner_acquire_bits_client_xact_id,
+ input [1:0] io_inner_acquire_bits_addr_beat,
+ input io_inner_acquire_bits_is_builtin_type,
+ input [2:0] io_inner_acquire_bits_a_type,
+ input [16:0] io_inner_acquire_bits_union,
+ input [3:0] io_inner_acquire_bits_data,
+ input [1:0] io_inner_acquire_bits_client_id,
+ input io_inner_grant_ready,
+ output io_inner_grant_valid,
+ output [1:0] io_inner_grant_bits_addr_beat,
+ output [1:0] io_inner_grant_bits_client_xact_id,
+ output [3:0] io_inner_grant_bits_manager_xact_id,
+ output io_inner_grant_bits_is_builtin_type,
+ output [3:0] io_inner_grant_bits_g_type,
+ output [3:0] io_inner_grant_bits_data,
+ output [1:0] io_inner_grant_bits_client_id,
+ output io_inner_finish_ready,
+ input io_inner_finish_valid,
+ input [3:0] io_inner_finish_bits_manager_xact_id,
+ input io_inner_probe_ready,
+ output io_inner_probe_valid,
+ output [25:0] io_inner_probe_bits_addr_block,
+ output [1:0] io_inner_probe_bits_p_type,
+ output [1:0] io_inner_probe_bits_client_id,
+ output io_inner_release_ready,
+ input io_inner_release_valid,
+ input [1:0] io_inner_release_bits_addr_beat,
+ input [25:0] io_inner_release_bits_addr_block,
+ input [1:0] io_inner_release_bits_client_xact_id,
+ input io_inner_release_bits_voluntary,
+ input [2:0] io_inner_release_bits_r_type,
+ input [3:0] io_inner_release_bits_data,
+ input [1:0] io_inner_release_bits_client_id,
+ input io_incoherent_0,
+ input io_outer_acquire_ready,
+ output io_outer_acquire_valid,
+ output [25:0] io_outer_acquire_bits_addr_block,
+ output [3:0] io_outer_acquire_bits_client_xact_id,
+ output [1:0] io_outer_acquire_bits_addr_beat,
+ output io_outer_acquire_bits_is_builtin_type,
+ output [2:0] io_outer_acquire_bits_a_type,
+ output [16:0] io_outer_acquire_bits_union,
+ output [3:0] io_outer_acquire_bits_data,
+ output io_outer_grant_ready,
+ input io_outer_grant_valid,
+ input [1:0] io_outer_grant_bits_addr_beat,
+ input [3:0] io_outer_grant_bits_client_xact_id,
+ input io_outer_grant_bits_manager_xact_id,
+ input io_outer_grant_bits_is_builtin_type,
+ input [3:0] io_outer_grant_bits_g_type,
+ input [3:0] io_outer_grant_bits_data,
+ output io_has_acquire_conflict,
+ output io_has_acquire_match,
+ output io_has_release_match
+);
+ reg [2:0] state;
+ reg [25:0] xact_addr_block;
+ reg [1:0] xact_client_xact_id;
+ reg [1:0] xact_addr_beat;
+ reg xact_is_builtin_type;
+ reg [2:0] xact_a_type;
+ reg [16:0] xact_union;
+ reg [3:0] xact_data_buffer_0;
+ reg [3:0] xact_data_buffer_1;
+ reg [3:0] xact_data_buffer_2;
+ reg [3:0] xact_data_buffer_3;
+ reg [15:0] xact_wmask_buffer_0;
+ reg [15:0] xact_wmask_buffer_1;
+ reg [15:0] xact_wmask_buffer_2;
+ reg [15:0] xact_wmask_buffer_3;
+ reg [1:0] xact_client_id;
+ wire coh_sharers;
+ wire T_303;
+ wire T_304;
+ wire [2:0] T_309_0;
+ wire [2:0] T_309_1;
+ wire [2:0] T_309_2;
+ wire T_314;
+ wire T_315;
+ wire T_316;
+ wire T_318;
+ wire T_319;
+ wire T_320;
+ wire T_321;
+ wire T_323;
+ wire T_325;
+ wire T_327;
+ wire T_329;
+ reg release_count;
+ reg pending_probes;
+ wire T_334;
+ wire T_336_0;
+ wire GEN_7;
+ wire T_341;
+ wire [3:0] T_344;
+ wire [3:0] T_345;
+ wire T_346;
+ wire [3:0] T_347;
+ wire [3:0] T_348;
+ wire [3:0] mask_self;
+ wire T_350;
+ wire [3:0] mask_incoherent;
+ reg collect_iacq_data;
+ reg [3:0] iacq_data_valid;
+ wire T_356;
+ wire T_359;
+ wire [2:0] T_362_0;
+ wire T_365;
+ wire T_367;
+ wire T_368;
+ wire T_369;
+ reg [1:0] T_371;
+ wire T_373;
+ wire T_375;
+ wire [2:0] T_378;
+ wire [1:0] T_379;
+ wire [1:0] T_380;
+ wire T_381;
+ wire [1:0] T_382;
+ wire iacq_data_done;
+ wire T_384;
+ wire [1:0] T_388_0;
+ wire [1:0] T_388_1;
+ wire [1:0] T_388_2;
+ wire T_393;
+ wire T_394;
+ wire T_395;
+ wire T_397;
+ wire T_398;
+ wire T_399;
+ wire T_400;
+ wire T_401;
+ reg [1:0] T_403;
+ wire T_405;
+ wire T_407;
+ wire [2:0] T_410;
+ wire [1:0] T_411;
+ wire [1:0] T_412;
+ wire T_413;
+ wire [1:0] T_414;
+ wire irel_data_done;
+ wire T_417;
+ wire [2:0] T_421_0;
+ wire T_424;
+ wire T_426;
+ wire T_428_0;
+ wire T_428_1;
+ wire T_432;
+ wire T_433;
+ wire T_435;
+ wire T_436;
+ wire T_437;
+ wire T_438;
+ wire T_439;
+ reg [1:0] T_441;
+ wire T_443;
+ wire T_445;
+ wire [2:0] T_448;
+ wire [1:0] T_449;
+ wire [1:0] T_450;
+ wire T_451;
+ wire [1:0] ignt_data_cnt;
+ wire ignt_data_done;
+ wire T_455;
+ wire T_457;
+ wire [2:0] T_460_0;
+ wire T_463;
+ wire T_465;
+ wire T_466;
+ wire T_467;
+ reg [1:0] T_469;
+ wire T_471;
+ wire T_473;
+ wire [2:0] T_476;
+ wire [1:0] T_477;
+ wire [1:0] T_478;
+ wire T_479;
+ wire [1:0] oacq_data_cnt;
+ wire oacq_data_done;
+ wire T_482;
+ wire [2:0] T_487_0;
+ wire T_490;
+ wire T_492;
+ wire T_494_0;
+ wire T_497;
+ wire T_499;
+ wire T_500;
+ wire T_501;
+ wire T_502;
+ reg [1:0] T_504;
+ wire T_506;
+ wire T_508;
+ wire [2:0] T_511;
+ wire [1:0] T_512;
+ wire [1:0] T_513;
+ wire T_514;
+ wire [1:0] T_515;
+ wire ognt_data_done;
+ reg pending_ognt_ack;
+ wire [2:0] T_523_0;
+ wire [2:0] T_523_1;
+ wire [2:0] T_523_2;
+ wire T_528;
+ wire T_529;
+ wire T_530;
+ wire T_532;
+ wire T_533;
+ wire T_534;
+ wire pending_outer_write;
+ wire [2:0] T_540_0;
+ wire [2:0] T_540_1;
+ wire [2:0] T_540_2;
+ wire T_545;
+ wire T_546;
+ wire T_547;
+ wire T_549;
+ wire T_550;
+ wire T_551;
+ wire pending_outer_write_;
+ wire [2:0] T_556_0;
+ wire [2:0] T_556_1;
+ wire T_560;
+ wire T_561;
+ wire T_563;
+ wire T_564;
+ wire T_566_0;
+ wire T_566_1;
+ wire T_570;
+ wire T_571;
+ wire T_573;
+ wire T_574;
+ wire pending_outer_read;
+ wire T_594;
+ wire [2:0] T_595;
+ wire T_596;
+ wire [2:0] T_597;
+ wire T_598;
+ wire [2:0] T_599;
+ wire T_600;
+ wire [2:0] T_601;
+ wire T_602;
+ wire [2:0] T_603;
+ wire T_604;
+ wire [2:0] T_605;
+ wire T_606;
+ wire [2:0] T_607;
+ wire T_608;
+ wire T_611;
+ wire T_612;
+ wire T_613;
+ wire [2:0] T_614;
+ wire [1:0] T_623_addr_beat;
+ wire [1:0] T_623_client_xact_id;
+ wire [3:0] T_623_manager_xact_id;
+ wire T_623_is_builtin_type;
+ wire [3:0] T_623_g_type;
+ wire [3:0] T_623_data;
+ wire [1:0] T_623_client_id;
+ wire [2:0] T_634_0;
+ wire [2:0] T_634_1;
+ wire T_638;
+ wire T_639;
+ wire T_641;
+ wire T_642;
+ wire T_644_0;
+ wire T_644_1;
+ wire T_648;
+ wire T_649;
+ wire T_651;
+ wire T_652;
+ wire pending_outer_read_;
+ wire [2:0] T_658_0;
+ wire [2:0] T_658_1;
+ wire [2:0] T_658_2;
+ wire T_663;
+ wire T_664;
+ wire T_665;
+ wire T_667;
+ wire T_668;
+ wire T_669;
+ wire subblock_type;
+ wire T_671;
+ wire T_672;
+ wire T_673;
+ wire T_675;
+ wire T_676;
+ wire T_677;
+ wire T_678;
+ wire T_679;
+ wire T_681;
+ wire T_682;
+ wire T_683;
+ wire T_684;
+ wire [15:0] GEN_8;
+ wire [15:0] T_689;
+ wire [3:0] T_695;
+ wire [1:0] T_696;
+ wire [5:0] T_697;
+ wire [1:0] T_699;
+ wire [4:0] T_700;
+ wire [16:0] T_702;
+ wire [16:0] T_704;
+ wire [3:0] T_706;
+ wire [1:0] T_707;
+ wire [5:0] T_708;
+ wire [5:0] T_710;
+ wire [5:0] T_712;
+ wire T_713;
+ wire [5:0] T_714;
+ wire T_715;
+ wire [5:0] T_716;
+ wire T_717;
+ wire [5:0] T_718;
+ wire T_719;
+ wire [16:0] T_720;
+ wire T_721;
+ wire [16:0] T_722;
+ wire T_723;
+ wire [16:0] T_724;
+ wire T_725;
+ wire [16:0] T_726;
+ wire [25:0] oacq_probe_addr_block;
+ wire [3:0] oacq_probe_client_xact_id;
+ wire [1:0] oacq_probe_addr_beat;
+ wire oacq_probe_is_builtin_type;
+ wire [2:0] oacq_probe_a_type;
+ wire [16:0] oacq_probe_union;
+ wire [3:0] oacq_probe_data;
+ wire [3:0] T_744;
+ wire T_745;
+ wire [1:0] T_747;
+ wire T_749;
+ wire T_750;
+ wire T_751;
+ wire T_752;
+ wire T_754_0;
+ wire T_754_1;
+ wire [8:0] T_759;
+ wire [7:0] T_760;
+ wire [8:0] T_762;
+ wire [7:0] T_763;
+ wire [7:0] T_765_0;
+ wire [7:0] T_765_1;
+ wire [15:0] T_769;
+ wire T_771;
+ wire T_772;
+ wire T_774;
+ wire T_775;
+ wire T_776;
+ wire [15:0] T_777;
+ wire [15:0] T_779;
+ wire [15:0] T_780;
+ wire [3:0] T_788;
+ wire [1:0] T_789;
+ wire [5:0] T_790;
+ wire [1:0] T_792;
+ wire [4:0] T_793;
+ wire [16:0] T_795;
+ wire [16:0] T_797;
+ wire [3:0] T_799;
+ wire [1:0] T_800;
+ wire [5:0] T_801;
+ wire [5:0] T_803;
+ wire [5:0] T_805;
+ wire T_806;
+ wire [5:0] T_807;
+ wire T_808;
+ wire [5:0] T_809;
+ wire T_810;
+ wire [5:0] T_811;
+ wire T_812;
+ wire [16:0] T_813;
+ wire T_814;
+ wire [16:0] T_815;
+ wire T_816;
+ wire [16:0] T_817;
+ wire T_818;
+ wire [16:0] T_819;
+ wire [25:0] oacq_write_beat_addr_block;
+ wire [3:0] oacq_write_beat_client_xact_id;
+ wire [1:0] oacq_write_beat_addr_beat;
+ wire oacq_write_beat_is_builtin_type;
+ wire [2:0] oacq_write_beat_a_type;
+ wire [16:0] oacq_write_beat_union;
+ wire [3:0] oacq_write_beat_data;
+ wire [3:0] T_846;
+ wire [1:0] T_847;
+ wire [5:0] T_848;
+ wire [1:0] T_850;
+ wire [4:0] T_851;
+ wire [15:0] GEN_0;
+ wire [16:0] T_853;
+ wire [15:0] GEN_1;
+ wire [16:0] T_855;
+ wire [3:0] T_857;
+ wire [1:0] T_858;
+ wire [5:0] T_859;
+ wire [5:0] T_861;
+ wire [5:0] T_863;
+ wire T_864;
+ wire [5:0] T_865;
+ wire T_866;
+ wire [5:0] T_867;
+ wire T_868;
+ wire [5:0] T_869;
+ wire T_870;
+ wire [16:0] T_871;
+ wire T_872;
+ wire [16:0] T_873;
+ wire T_874;
+ wire [16:0] T_875;
+ wire T_876;
+ wire [16:0] T_877;
+ wire [25:0] oacq_write_block_addr_block;
+ wire [3:0] oacq_write_block_client_xact_id;
+ wire [1:0] oacq_write_block_addr_beat;
+ wire oacq_write_block_is_builtin_type;
+ wire [2:0] oacq_write_block_a_type;
+ wire [16:0] oacq_write_block_union;
+ wire [3:0] oacq_write_block_data;
+ wire [3:0] GEN_2;
+ wire [3:0] T_895;
+ wire [2:0] T_896;
+ wire [6:0] T_904;
+ wire [5:0] T_905;
+ wire [12:0] T_906;
+ wire [5:0] T_908;
+ wire [8:0] T_909;
+ wire [1:0] T_911;
+ wire [1:0] T_913;
+ wire [6:0] T_915;
+ wire [5:0] T_916;
+ wire [12:0] T_917;
+ wire [5:0] T_919;
+ wire [5:0] T_921;
+ wire T_922;
+ wire [5:0] T_923;
+ wire T_924;
+ wire [5:0] T_925;
+ wire T_926;
+ wire [12:0] T_927;
+ wire T_928;
+ wire [12:0] T_929;
+ wire T_930;
+ wire [12:0] T_931;
+ wire T_932;
+ wire [12:0] T_933;
+ wire T_934;
+ wire [12:0] T_935;
+ wire [25:0] oacq_read_beat_addr_block;
+ wire [3:0] oacq_read_beat_client_xact_id;
+ wire [1:0] oacq_read_beat_addr_beat;
+ wire oacq_read_beat_is_builtin_type;
+ wire [2:0] oacq_read_beat_a_type;
+ wire [16:0] oacq_read_beat_union;
+ wire [3:0] oacq_read_beat_data;
+ wire [3:0] T_962;
+ wire [5:0] T_963;
+ wire [9:0] T_964;
+ wire [5:0] T_966;
+ wire [8:0] T_967;
+ wire [1:0] T_969;
+ wire [1:0] T_971;
+ wire [3:0] T_973;
+ wire [5:0] T_974;
+ wire [9:0] T_975;
+ wire [5:0] T_977;
+ wire [5:0] T_979;
+ wire T_980;
+ wire [5:0] T_981;
+ wire T_982;
+ wire [5:0] T_983;
+ wire T_984;
+ wire [9:0] T_985;
+ wire T_986;
+ wire [9:0] T_987;
+ wire T_988;
+ wire [9:0] T_989;
+ wire T_990;
+ wire [9:0] T_991;
+ wire T_992;
+ wire [9:0] T_993;
+ wire [25:0] oacq_read_block_addr_block;
+ wire [3:0] oacq_read_block_client_xact_id;
+ wire [1:0] oacq_read_block_addr_beat;
+ wire oacq_read_block_is_builtin_type;
+ wire [2:0] oacq_read_block_a_type;
+ wire [16:0] oacq_read_block_union;
+ wire [3:0] oacq_read_block_data;
+ wire T_1011;
+ wire T_1012;
+ wire [25:0] T_1013_addr_block;
+ wire [3:0] T_1013_client_xact_id;
+ wire [1:0] T_1013_addr_beat;
+ wire T_1013_is_builtin_type;
+ wire [2:0] T_1013_a_type;
+ wire [16:0] T_1013_union;
+ wire [3:0] T_1013_data;
+ wire [25:0] T_1021_addr_block;
+ wire [3:0] T_1021_client_xact_id;
+ wire [1:0] T_1021_addr_beat;
+ wire T_1021_is_builtin_type;
+ wire [2:0] T_1021_a_type;
+ wire [16:0] T_1021_union;
+ wire [3:0] T_1021_data;
+ wire [25:0] T_1029_addr_block;
+ wire [3:0] T_1029_client_xact_id;
+ wire [1:0] T_1029_addr_beat;
+ wire T_1029_is_builtin_type;
+ wire [2:0] T_1029_a_type;
+ wire [16:0] T_1029_union;
+ wire [3:0] T_1029_data;
+ wire [25:0] T_1037_addr_block;
+ wire [3:0] T_1037_client_xact_id;
+ wire [1:0] T_1037_addr_beat;
+ wire T_1037_is_builtin_type;
+ wire [2:0] T_1037_a_type;
+ wire [16:0] T_1037_union;
+ wire [3:0] T_1037_data;
+ wire T_1054;
+ wire [1:0] T_1055;
+ wire T_1056;
+ wire [1:0] T_1057;
+ wire T_1058;
+ wire [1:0] T_1059;
+ wire T_1060;
+ wire [1:0] T_1061;
+ wire T_1062;
+ wire [1:0] T_1063;
+ wire T_1064;
+ wire [1:0] T_1065;
+ wire T_1066;
+ wire [1:0] T_1067;
+ wire T_1068;
+ wire [1:0] T_1069;
+ wire T_1070;
+ wire [1:0] T_1071;
+ wire [1:0] T_1072;
+ wire [25:0] T_1077_addr_block;
+ wire [1:0] T_1077_p_type;
+ wire [1:0] T_1077_client_id;
+ wire T_1100;
+ wire [2:0] T_1101;
+ wire T_1102;
+ wire [2:0] T_1103;
+ wire T_1104;
+ wire [2:0] T_1105;
+ wire T_1106;
+ wire [2:0] T_1107;
+ wire T_1108;
+ wire [2:0] T_1109;
+ wire T_1110;
+ wire [2:0] T_1111;
+ wire T_1112;
+ wire [2:0] T_1113;
+ wire T_1114;
+ wire T_1117;
+ wire T_1118;
+ wire T_1119;
+ wire [2:0] T_1120;
+ wire [1:0] T_1129_addr_beat;
+ wire [1:0] T_1129_client_xact_id;
+ wire [3:0] T_1129_manager_xact_id;
+ wire T_1129_is_builtin_type;
+ wire [3:0] T_1129_g_type;
+ wire [3:0] T_1129_data;
+ wire [1:0] T_1129_client_id;
+ wire T_1140;
+ wire T_1141;
+ wire T_1142;
+ wire T_1143;
+ wire T_1144;
+ wire T_1145;
+ wire T_1147;
+ wire T_1149;
+ wire T_1151;
+ wire T_1153;
+ wire T_1154;
+ wire T_1155;
+ wire T_1156;
+ wire T_1157;
+ wire T_1158;
+ wire T_1159;
+ wire T_1161;
+ wire T_1163;
+ wire T_1165;
+ wire T_1167;
+ wire T_1168;
+ wire T_1169;
+ wire T_1170;
+ wire T_1172;
+ wire [2:0] T_1175_0;
+ wire T_1178;
+ wire T_1180;
+ wire T_1181;
+ wire T_1182;
+ wire T_1184;
+ wire T_1185;
+ wire T_1187;
+ wire T_1189;
+ wire T_1191;
+ wire T_1193;
+ wire [3:0] GEN_3;
+ wire [3:0] T_1197;
+ wire T_1198;
+ wire [1:0] T_1200;
+ wire T_1202;
+ wire T_1203;
+ wire T_1204;
+ wire T_1205;
+ wire T_1207_0;
+ wire T_1207_1;
+ wire [8:0] T_1212;
+ wire [7:0] T_1213;
+ wire [8:0] T_1215;
+ wire [7:0] T_1216;
+ wire [7:0] T_1218_0;
+ wire [7:0] T_1218_1;
+ wire [15:0] T_1222;
+ wire T_1224;
+ wire T_1225;
+ wire T_1227;
+ wire T_1228;
+ wire T_1229;
+ wire [15:0] T_1230;
+ wire [15:0] T_1232;
+ wire [15:0] T_1233;
+ wire [15:0] GEN_4;
+ wire [3:0] T_1236;
+ wire [3:0] T_1237;
+ wire [3:0] T_1238;
+ wire [3:0] T_1239;
+ wire [3:0] T_1240;
+ wire [3:0] T_1241;
+ wire T_1245;
+ wire [3:0] GEN_5;
+ wire [3:0] T_1251;
+ wire T_1252;
+ wire [1:0] T_1254;
+ wire T_1256;
+ wire T_1257;
+ wire T_1258;
+ wire T_1259;
+ wire T_1261_0;
+ wire T_1261_1;
+ wire [8:0] T_1266;
+ wire [7:0] T_1267;
+ wire [8:0] T_1269;
+ wire [7:0] T_1270;
+ wire [7:0] T_1272_0;
+ wire [7:0] T_1272_1;
+ wire [15:0] T_1276;
+ wire T_1278;
+ wire T_1279;
+ wire T_1281;
+ wire T_1282;
+ wire T_1283;
+ wire [15:0] T_1284;
+ wire [15:0] T_1286;
+ wire [15:0] T_1287;
+ wire [15:0] GEN_6;
+ wire T_1289;
+ wire [2:0] T_1292_0;
+ wire T_1295;
+ wire T_1297;
+ wire T_1298;
+ wire [2:0] T_1303_0;
+ wire [2:0] T_1303_1;
+ wire [2:0] T_1303_2;
+ wire T_1308;
+ wire T_1309;
+ wire T_1310;
+ wire T_1312;
+ wire T_1313;
+ wire T_1314;
+ wire T_1315;
+ wire [3:0] T_1316;
+ wire T_1318;
+ wire T_1319;
+ wire T_1320;
+ wire T_1321;
+ wire T_1322;
+ wire [1:0] T_1324;
+ wire [2:0] T_1325;
+ wire [1:0] T_1326;
+ wire [1:0] T_1329;
+ wire [2:0] T_1330;
+ wire [1:0] T_1331;
+ wire [2:0] T_1332;
+ wire [3:0] T_1333;
+ wire [2:0] T_1334;
+ wire [2:0] T_1335;
+ wire [2:0] T_1336;
+ wire [2:0] T_1337;
+ wire T_1338;
+ wire T_1340;
+ wire [1:0] T_1342;
+ wire [1:0] T_1343;
+ wire [1:0] T_1344;
+ wire [1:0] T_1346_0;
+ wire [1:0] T_1346_1;
+ wire [1:0] T_1346_2;
+ wire T_1351;
+ wire T_1352;
+ wire T_1353;
+ wire T_1355;
+ wire T_1356;
+ wire T_1357;
+ wire T_1359;
+ wire T_1360;
+ wire [1:0] T_1362_0;
+ wire [1:0] T_1362_1;
+ wire [1:0] T_1362_2;
+ wire T_1367;
+ wire T_1368;
+ wire T_1369;
+ wire T_1371;
+ wire T_1372;
+ wire T_1373;
+ wire [1:0] T_1377;
+ wire T_1378;
+ wire T_1380;
+ wire [2:0] T_1381;
+ wire [2:0] T_1382;
+ wire T_1384;
+ wire [1:0] T_1386;
+ wire T_1387;
+ wire T_1389;
+ wire [2:0] T_1390;
+ wire [2:0] T_1391;
+ wire T_1392;
+ wire T_1394;
+ wire T_1396;
+ wire [3:0] T_1397;
+ wire T_1398;
+ wire T_1399;
+ wire T_1400;
+ wire [2:0] T_1402;
+ wire T_1403;
+ wire T_1405;
+ wire T_1406;
+ wire T_1407;
+ wire T_1410;
+ wire T_1412;
+ wire T_1413;
+ wire T_1415;
+ wire T_1416;
+ wire [2:0] T_1417;
+ wire T_1418;
+ wire T_1422;
+ wire T_1424;
+ wire T_1425;
+ wire T_1427;
+ wire T_1428;
+ wire [2:0] T_1429;
+ wire T_1430;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ wire GEN_17;
+ wire GEN_18;
+ wire GEN_19;
+ wire GEN_20;
+ wire GEN_21;
+ wire GEN_22;
+ wire GEN_23;
+ wire GEN_24;
+ wire GEN_25;
+ wire GEN_26;
+ wire GEN_27;
+ wire GEN_28;
+ wire GEN_29;
+ wire GEN_30;
+ wire GEN_31;
+ wire GEN_32;
+ wire GEN_33;
+ wire GEN_34;
+ wire GEN_35;
+ wire GEN_36;
+ wire GEN_37;
+ wire GEN_38;
+ wire GEN_39;
+ wire GEN_40;
+ wire GEN_41;
+ wire GEN_42;
+ wire GEN_43;
+ wire GEN_44;
+ wire GEN_45;
+ wire GEN_46;
+ wire GEN_47;
+ wire GEN_48;
+ wire GEN_49;
+ wire GEN_50;
+ wire GEN_51;
+ wire GEN_52;
+ wire GEN_53;
+ assign io_inner_acquire_ready = T_1245 ? 1'h1 : collect_iacq_data ? 1'h1 : 1'h0;
+ assign io_inner_grant_valid = T_1418 ? 1'h1 : T_1407 ? io_outer_grant_valid : 1'h0;
+ assign io_inner_grant_bits_addr_beat = T_1129_addr_beat;
+ assign io_inner_grant_bits_client_xact_id = T_1129_client_xact_id;
+ assign io_inner_grant_bits_manager_xact_id = T_1129_manager_xact_id;
+ assign io_inner_grant_bits_is_builtin_type = T_1129_is_builtin_type;
+ assign io_inner_grant_bits_g_type = T_1129_g_type;
+ assign io_inner_grant_bits_data = T_1129_data;
+ assign io_inner_grant_bits_client_id = T_1129_client_id;
+ assign io_inner_finish_ready = T_1430 ? 1'h1 : 1'h0;
+ assign io_inner_probe_valid = T_1338 ? T_1340 : 1'h0;
+ assign io_inner_probe_bits_addr_block = T_1077_addr_block;
+ assign io_inner_probe_bits_p_type = T_1077_p_type;
+ assign io_inner_probe_bits_client_id = T_1077_client_id;
+ assign io_inner_release_ready = T_1338 ? T_1360 : 1'h0;
+ assign io_outer_acquire_valid = T_1403 ? T_1405 : T_1392 ? T_1400 : T_1338 ? io_inner_release_valid ? T_1373 ? 1'h1 : 1'h0 : 1'h0 : 1'h0;
+ assign io_outer_acquire_bits_addr_block = T_1037_addr_block;
+ assign io_outer_acquire_bits_client_xact_id = T_1037_client_xact_id;
+ assign io_outer_acquire_bits_addr_beat = T_1037_addr_beat;
+ assign io_outer_acquire_bits_is_builtin_type = T_1037_is_builtin_type;
+ assign io_outer_acquire_bits_a_type = T_1037_a_type;
+ assign io_outer_acquire_bits_union = T_1037_union;
+ assign io_outer_acquire_bits_data = T_1037_data;
+ assign io_outer_grant_ready = T_1407 ? io_inner_grant_ready : pending_ognt_ack ? 1'h1 : 1'h0;
+ assign io_has_acquire_conflict = T_676;
+ assign io_has_acquire_match = T_678;
+ assign io_has_release_match = T_684;
+ assign coh_sharers = 1'h0;
+ assign T_303 = state != 1'h0;
+ assign T_304 = T_303 & xact_is_builtin_type;
+ assign T_309_0 = 3'h4;
+ assign T_309_1 = 3'h5;
+ assign T_309_2 = 3'h6;
+ assign T_314 = T_309_0 == xact_a_type;
+ assign T_315 = T_309_1 == xact_a_type;
+ assign T_316 = T_309_2 == xact_a_type;
+ assign T_318 = 1'h0 | T_314;
+ assign T_319 = T_318 | T_315;
+ assign T_320 = T_319 | T_316;
+ assign T_321 = T_304 & T_320;
+ assign T_323 = T_321 == 1'h0;
+ assign T_325 = reset == 1'h0;
+ assign T_327 = T_323 == 1'h0;
+ assign T_329 = reset == 1'h0;
+ assign T_334 = pending_probes;
+ assign T_336_0 = T_334;
+ assign GEN_7 = $signed(1'h1);
+ assign T_341 = $unsigned(GEN_7);
+ assign T_344 = 1'h1 << io_inner_acquire_bits_client_id;
+ assign T_345 = T_341 | T_344;
+ assign T_346 = ~ T_341;
+ assign T_347 = T_346 | T_344;
+ assign T_348 = ~ T_347;
+ assign mask_self = 1'h0 ? T_345 : T_348;
+ assign T_350 = ~ io_incoherent_0;
+ assign mask_incoherent = mask_self & T_350;
+ assign T_356 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_359 = 1'h1 & io_inner_acquire_bits_is_builtin_type;
+ assign T_362_0 = 3'h3;
+ assign T_365 = T_362_0 == io_inner_acquire_bits_a_type;
+ assign T_367 = 1'h0 | T_365;
+ assign T_368 = T_359 & T_367;
+ assign T_369 = T_356 & T_368;
+ assign T_373 = T_371 == 2'h3;
+ assign T_375 = 1'h0 & T_373;
+ assign T_378 = T_371 + 1'h1;
+ assign T_379 = T_378[1:0];
+ assign T_380 = T_375 ? 1'h0 : T_379;
+ assign T_381 = T_369 & T_373;
+ assign T_382 = T_368 ? T_371 : 1'h0;
+ assign iacq_data_done = T_368 ? T_381 : T_356;
+ assign T_384 = io_inner_release_ready & io_inner_release_valid;
+ assign T_388_0 = 1'h0;
+ assign T_388_1 = 1'h1;
+ assign T_388_2 = 2'h2;
+ assign T_393 = T_388_0 == io_inner_release_bits_r_type;
+ assign T_394 = T_388_1 == io_inner_release_bits_r_type;
+ assign T_395 = T_388_2 == io_inner_release_bits_r_type;
+ assign T_397 = 1'h0 | T_393;
+ assign T_398 = T_397 | T_394;
+ assign T_399 = T_398 | T_395;
+ assign T_400 = 1'h1 & T_399;
+ assign T_401 = T_384 & T_400;
+ assign T_405 = T_403 == 2'h3;
+ assign T_407 = 1'h0 & T_405;
+ assign T_410 = T_403 + 1'h1;
+ assign T_411 = T_410[1:0];
+ assign T_412 = T_407 ? 1'h0 : T_411;
+ assign T_413 = T_401 & T_405;
+ assign T_414 = T_400 ? T_403 : 1'h0;
+ assign irel_data_done = T_400 ? T_413 : T_384;
+ assign T_417 = io_inner_grant_ready & io_inner_grant_valid;
+ assign T_421_0 = 3'h5;
+ assign T_424 = T_421_0 == io_inner_grant_bits_g_type;
+ assign T_426 = 1'h0 | T_424;
+ assign T_428_0 = 1'h0;
+ assign T_428_1 = 1'h1;
+ assign T_432 = T_428_0 == io_inner_grant_bits_g_type;
+ assign T_433 = T_428_1 == io_inner_grant_bits_g_type;
+ assign T_435 = 1'h0 | T_432;
+ assign T_436 = T_435 | T_433;
+ assign T_437 = io_inner_grant_bits_is_builtin_type ? T_426 : T_436;
+ assign T_438 = 1'h1 & T_437;
+ assign T_439 = T_417 & T_438;
+ assign T_443 = T_441 == 2'h3;
+ assign T_445 = 1'h0 & T_443;
+ assign T_448 = T_441 + 1'h1;
+ assign T_449 = T_448[1:0];
+ assign T_450 = T_445 ? 1'h0 : T_449;
+ assign T_451 = T_439 & T_443;
+ assign ignt_data_cnt = T_438 ? T_441 : 1'h0;
+ assign ignt_data_done = T_438 ? T_451 : T_417;
+ assign T_455 = io_outer_acquire_ready & io_outer_acquire_valid;
+ assign T_457 = 1'h1 & io_outer_acquire_bits_is_builtin_type;
+ assign T_460_0 = 3'h3;
+ assign T_463 = T_460_0 == io_outer_acquire_bits_a_type;
+ assign T_465 = 1'h0 | T_463;
+ assign T_466 = T_457 & T_465;
+ assign T_467 = T_455 & T_466;
+ assign T_471 = T_469 == 2'h3;
+ assign T_473 = 1'h0 & T_471;
+ assign T_476 = T_469 + 1'h1;
+ assign T_477 = T_476[1:0];
+ assign T_478 = T_473 ? 1'h0 : T_477;
+ assign T_479 = T_467 & T_471;
+ assign oacq_data_cnt = T_466 ? T_469 : 1'h0;
+ assign oacq_data_done = T_466 ? T_479 : T_455;
+ assign T_482 = io_outer_grant_ready & io_outer_grant_valid;
+ assign T_487_0 = 3'h5;
+ assign T_490 = T_487_0 == io_outer_grant_bits_g_type;
+ assign T_492 = 1'h0 | T_490;
+ assign T_494_0 = 1'h0;
+ assign T_497 = T_494_0 == io_outer_grant_bits_g_type;
+ assign T_499 = 1'h0 | T_497;
+ assign T_500 = io_outer_grant_bits_is_builtin_type ? T_492 : T_499;
+ assign T_501 = 1'h1 & T_500;
+ assign T_502 = T_482 & T_501;
+ assign T_506 = T_504 == 2'h3;
+ assign T_508 = 1'h0 & T_506;
+ assign T_511 = T_504 + 1'h1;
+ assign T_512 = T_511[1:0];
+ assign T_513 = T_508 ? 1'h0 : T_512;
+ assign T_514 = T_502 & T_506;
+ assign T_515 = T_501 ? T_504 : 1'h0;
+ assign ognt_data_done = T_501 ? T_514 : T_482;
+ assign T_523_0 = 3'h2;
+ assign T_523_1 = 3'h3;
+ assign T_523_2 = 3'h4;
+ assign T_528 = T_523_0 == xact_a_type;
+ assign T_529 = T_523_1 == xact_a_type;
+ assign T_530 = T_523_2 == xact_a_type;
+ assign T_532 = 1'h0 | T_528;
+ assign T_533 = T_532 | T_529;
+ assign T_534 = T_533 | T_530;
+ assign pending_outer_write = xact_is_builtin_type & T_534;
+ assign T_540_0 = 3'h2;
+ assign T_540_1 = 3'h3;
+ assign T_540_2 = 3'h4;
+ assign T_545 = T_540_0 == io_inner_acquire_bits_a_type;
+ assign T_546 = T_540_1 == io_inner_acquire_bits_a_type;
+ assign T_547 = T_540_2 == io_inner_acquire_bits_a_type;
+ assign T_549 = 1'h0 | T_545;
+ assign T_550 = T_549 | T_546;
+ assign T_551 = T_550 | T_547;
+ assign pending_outer_write_ = io_inner_acquire_bits_is_builtin_type & T_551;
+ assign T_556_0 = 3'h5;
+ assign T_556_1 = 3'h4;
+ assign T_560 = T_556_0 == io_inner_grant_bits_g_type;
+ assign T_561 = T_556_1 == io_inner_grant_bits_g_type;
+ assign T_563 = 1'h0 | T_560;
+ assign T_564 = T_563 | T_561;
+ assign T_566_0 = 1'h0;
+ assign T_566_1 = 1'h1;
+ assign T_570 = T_566_0 == io_inner_grant_bits_g_type;
+ assign T_571 = T_566_1 == io_inner_grant_bits_g_type;
+ assign T_573 = 1'h0 | T_570;
+ assign T_574 = T_573 | T_571;
+ assign pending_outer_read = io_inner_grant_bits_is_builtin_type ? T_564 : T_574;
+ assign T_594 = 3'h6 == io_inner_acquire_bits_a_type;
+ assign T_595 = T_594 ? 3'h1 : 3'h3;
+ assign T_596 = 3'h5 == io_inner_acquire_bits_a_type;
+ assign T_597 = T_596 ? 3'h1 : T_595;
+ assign T_598 = 3'h4 == io_inner_acquire_bits_a_type;
+ assign T_599 = T_598 ? 3'h4 : T_597;
+ assign T_600 = 3'h3 == io_inner_acquire_bits_a_type;
+ assign T_601 = T_600 ? 3'h3 : T_599;
+ assign T_602 = 3'h2 == io_inner_acquire_bits_a_type;
+ assign T_603 = T_602 ? 3'h3 : T_601;
+ assign T_604 = 3'h1 == io_inner_acquire_bits_a_type;
+ assign T_605 = T_604 ? 3'h5 : T_603;
+ assign T_606 = 3'h0 == io_inner_acquire_bits_a_type;
+ assign T_607 = T_606 ? 3'h4 : T_605;
+ assign T_608 = io_inner_acquire_bits_a_type == 1'h0;
+ assign T_611 = 1'h0 == 1'h0;
+ assign T_612 = T_611 ? 1'h0 : 1'h1;
+ assign T_613 = T_608 ? T_612 : 1'h1;
+ assign T_614 = io_inner_acquire_bits_is_builtin_type ? T_607 : T_613;
+ assign T_623_addr_beat = 1'h0;
+ assign T_623_client_xact_id = io_inner_acquire_bits_client_xact_id;
+ assign T_623_manager_xact_id = 2'h2;
+ assign T_623_is_builtin_type = io_inner_acquire_bits_is_builtin_type;
+ assign T_623_g_type = T_614;
+ assign T_623_data = 1'h0;
+ assign T_623_client_id = io_inner_acquire_bits_client_id;
+ assign T_634_0 = 3'h5;
+ assign T_634_1 = 3'h4;
+ assign T_638 = T_634_0 == T_623_g_type;
+ assign T_639 = T_634_1 == T_623_g_type;
+ assign T_641 = 1'h0 | T_638;
+ assign T_642 = T_641 | T_639;
+ assign T_644_0 = 1'h0;
+ assign T_644_1 = 1'h1;
+ assign T_648 = T_644_0 == T_623_g_type;
+ assign T_649 = T_644_1 == T_623_g_type;
+ assign T_651 = 1'h0 | T_648;
+ assign T_652 = T_651 | T_649;
+ assign pending_outer_read_ = T_623_is_builtin_type ? T_642 : T_652;
+ assign T_658_0 = 3'h2;
+ assign T_658_1 = 3'h0;
+ assign T_658_2 = 3'h4;
+ assign T_663 = T_658_0 == xact_a_type;
+ assign T_664 = T_658_1 == xact_a_type;
+ assign T_665 = T_658_2 == xact_a_type;
+ assign T_667 = 1'h0 | T_663;
+ assign T_668 = T_667 | T_664;
+ assign T_669 = T_668 | T_665;
+ assign subblock_type = xact_is_builtin_type & T_669;
+ assign T_671 = xact_addr_block == io_inner_acquire_bits_addr_block;
+ assign T_672 = state != 1'h0;
+ assign T_673 = T_671 & T_672;
+ assign T_675 = collect_iacq_data == 1'h0;
+ assign T_676 = T_673 & T_675;
+ assign T_677 = xact_addr_block == io_inner_acquire_bits_addr_block;
+ assign T_678 = T_677 & collect_iacq_data;
+ assign T_679 = xact_addr_block == io_inner_release_bits_addr_block;
+ assign T_681 = io_inner_release_bits_voluntary == 1'h0;
+ assign T_682 = T_679 & T_681;
+ assign T_683 = state == 1'h1;
+ assign T_684 = T_682 & T_683;
+ assign GEN_8 = $signed(16'hffff);
+ assign T_689 = $unsigned(GEN_8);
+ assign T_695 = {1'h0,3'h7};
+ assign T_696 = {1'h0,1'h1};
+ assign T_697 = {T_695,T_696};
+ assign T_699 = {1'h0,1'h1};
+ assign T_700 = {3'h7,T_699};
+ assign T_702 = {T_689,1'h1};
+ assign T_704 = {T_689,1'h1};
+ assign T_706 = {1'h0,3'h7};
+ assign T_707 = {1'h0,1'h1};
+ assign T_708 = {T_706,T_707};
+ assign T_710 = {5'h0,1'h1};
+ assign T_712 = {5'h1,1'h1};
+ assign T_713 = 3'h6 == 3'h3;
+ assign T_714 = T_713 ? T_712 : 1'h0;
+ assign T_715 = 3'h5 == 3'h3;
+ assign T_716 = T_715 ? T_710 : T_714;
+ assign T_717 = 3'h4 == 3'h3;
+ assign T_718 = T_717 ? T_708 : T_716;
+ assign T_719 = 3'h3 == 3'h3;
+ assign T_720 = T_719 ? T_704 : T_718;
+ assign T_721 = 3'h2 == 3'h3;
+ assign T_722 = T_721 ? T_702 : T_720;
+ assign T_723 = 3'h1 == 3'h3;
+ assign T_724 = T_723 ? T_700 : T_722;
+ assign T_725 = 3'h0 == 3'h3;
+ assign T_726 = T_725 ? T_697 : T_724;
+ assign oacq_probe_addr_block = io_inner_release_bits_addr_block;
+ assign oacq_probe_client_xact_id = 2'h2;
+ assign oacq_probe_addr_beat = io_inner_release_bits_addr_beat;
+ assign oacq_probe_is_builtin_type = 1'h1;
+ assign oacq_probe_a_type = 3'h3;
+ assign oacq_probe_union = T_726;
+ assign oacq_probe_data = io_inner_release_bits_data;
+ assign T_744 = xact_union[12:9];
+ assign T_745 = T_744[3];
+ assign T_747 = 1'h1 << T_745;
+ assign T_749 = xact_a_type == 3'h4;
+ assign T_750 = xact_is_builtin_type & T_749;
+ assign T_751 = T_747[0];
+ assign T_752 = T_747[1];
+ assign T_754_0 = T_751;
+ assign T_754_1 = T_752;
+ assign T_759 = 8'h0 - T_754_0;
+ assign T_760 = T_759[7:0];
+ assign T_762 = 8'h0 - T_754_1;
+ assign T_763 = T_762[7:0];
+ assign T_765_0 = T_760;
+ assign T_765_1 = T_763;
+ assign T_769 = {T_765_1,T_765_0};
+ assign T_771 = xact_a_type == 3'h3;
+ assign T_772 = xact_is_builtin_type & T_771;
+ assign T_774 = xact_a_type == 3'h2;
+ assign T_775 = xact_is_builtin_type & T_774;
+ assign T_776 = T_772 | T_775;
+ assign T_777 = xact_union[16:1];
+ assign T_779 = T_776 ? T_777 : 16'h0;
+ assign T_780 = T_750 ? T_769 : T_779;
+ assign T_788 = {1'h0,3'h7};
+ assign T_789 = {1'h0,1'h1};
+ assign T_790 = {T_788,T_789};
+ assign T_792 = {1'h0,1'h1};
+ assign T_793 = {3'h7,T_792};
+ assign T_795 = {T_780,1'h1};
+ assign T_797 = {T_780,1'h1};
+ assign T_799 = {1'h0,3'h7};
+ assign T_800 = {1'h0,1'h1};
+ assign T_801 = {T_799,T_800};
+ assign T_803 = {5'h0,1'h1};
+ assign T_805 = {5'h1,1'h1};
+ assign T_806 = 3'h6 == 3'h2;
+ assign T_807 = T_806 ? T_805 : 1'h0;
+ assign T_808 = 3'h5 == 3'h2;
+ assign T_809 = T_808 ? T_803 : T_807;
+ assign T_810 = 3'h4 == 3'h2;
+ assign T_811 = T_810 ? T_801 : T_809;
+ assign T_812 = 3'h3 == 3'h2;
+ assign T_813 = T_812 ? T_797 : T_811;
+ assign T_814 = 3'h2 == 3'h2;
+ assign T_815 = T_814 ? T_795 : T_813;
+ assign T_816 = 3'h1 == 3'h2;
+ assign T_817 = T_816 ? T_793 : T_815;
+ assign T_818 = 3'h0 == 3'h2;
+ assign T_819 = T_818 ? T_790 : T_817;
+ assign oacq_write_beat_addr_block = xact_addr_block;
+ assign oacq_write_beat_client_xact_id = 2'h2;
+ assign oacq_write_beat_addr_beat = xact_addr_beat;
+ assign oacq_write_beat_is_builtin_type = 1'h1;
+ assign oacq_write_beat_a_type = 3'h2;
+ assign oacq_write_beat_union = T_819;
+ assign oacq_write_beat_data = xact_data_buffer_0;
+ assign T_846 = {1'h0,3'h7};
+ assign T_847 = {1'h0,1'h1};
+ assign T_848 = {T_846,T_847};
+ assign T_850 = {1'h0,1'h1};
+ assign T_851 = {3'h7,T_850};
+ assign GEN_0 = GEN_45 ? xact_wmask_buffer_3 : GEN_46 ? xact_wmask_buffer_2 : GEN_47 ? xact_wmask_buffer_1 : xact_wmask_buffer_0;
+ assign T_853 = {GEN_0,1'h1};
+ assign GEN_1 = GEN_48 ? xact_wmask_buffer_3 : GEN_49 ? xact_wmask_buffer_2 : GEN_50 ? xact_wmask_buffer_1 : xact_wmask_buffer_0;
+ assign T_855 = {GEN_1,1'h1};
+ assign T_857 = {1'h0,3'h7};
+ assign T_858 = {1'h0,1'h1};
+ assign T_859 = {T_857,T_858};
+ assign T_861 = {5'h0,1'h1};
+ assign T_863 = {5'h1,1'h1};
+ assign T_864 = 3'h6 == 3'h3;
+ assign T_865 = T_864 ? T_863 : 1'h0;
+ assign T_866 = 3'h5 == 3'h3;
+ assign T_867 = T_866 ? T_861 : T_865;
+ assign T_868 = 3'h4 == 3'h3;
+ assign T_869 = T_868 ? T_859 : T_867;
+ assign T_870 = 3'h3 == 3'h3;
+ assign T_871 = T_870 ? T_855 : T_869;
+ assign T_872 = 3'h2 == 3'h3;
+ assign T_873 = T_872 ? T_853 : T_871;
+ assign T_874 = 3'h1 == 3'h3;
+ assign T_875 = T_874 ? T_851 : T_873;
+ assign T_876 = 3'h0 == 3'h3;
+ assign T_877 = T_876 ? T_848 : T_875;
+ assign oacq_write_block_addr_block = xact_addr_block;
+ assign oacq_write_block_client_xact_id = 2'h2;
+ assign oacq_write_block_addr_beat = oacq_data_cnt;
+ assign oacq_write_block_is_builtin_type = 1'h1;
+ assign oacq_write_block_a_type = 3'h3;
+ assign oacq_write_block_union = T_877;
+ assign oacq_write_block_data = GEN_2;
+ assign GEN_2 = GEN_51 ? xact_data_buffer_3 : GEN_52 ? xact_data_buffer_2 : GEN_53 ? xact_data_buffer_1 : xact_data_buffer_0;
+ assign T_895 = xact_union[12:9];
+ assign T_896 = xact_union[8:6];
+ assign T_904 = {T_895,T_896};
+ assign T_905 = {5'h0,1'h0};
+ assign T_906 = {T_904,T_905};
+ assign T_908 = {5'h0,1'h0};
+ assign T_909 = {T_896,T_908};
+ assign T_911 = {1'h0,1'h0};
+ assign T_913 = {1'h0,1'h0};
+ assign T_915 = {T_895,T_896};
+ assign T_916 = {5'h0,1'h0};
+ assign T_917 = {T_915,T_916};
+ assign T_919 = {5'h0,1'h0};
+ assign T_921 = {5'h1,1'h0};
+ assign T_922 = 3'h6 == 3'h0;
+ assign T_923 = T_922 ? T_921 : 1'h0;
+ assign T_924 = 3'h5 == 3'h0;
+ assign T_925 = T_924 ? T_919 : T_923;
+ assign T_926 = 3'h4 == 3'h0;
+ assign T_927 = T_926 ? T_917 : T_925;
+ assign T_928 = 3'h3 == 3'h0;
+ assign T_929 = T_928 ? T_913 : T_927;
+ assign T_930 = 3'h2 == 3'h0;
+ assign T_931 = T_930 ? T_911 : T_929;
+ assign T_932 = 3'h1 == 3'h0;
+ assign T_933 = T_932 ? T_909 : T_931;
+ assign T_934 = 3'h0 == 3'h0;
+ assign T_935 = T_934 ? T_906 : T_933;
+ assign oacq_read_beat_addr_block = xact_addr_block;
+ assign oacq_read_beat_client_xact_id = 2'h2;
+ assign oacq_read_beat_addr_beat = xact_addr_beat;
+ assign oacq_read_beat_is_builtin_type = 1'h1;
+ assign oacq_read_beat_a_type = 3'h0;
+ assign oacq_read_beat_union = T_935;
+ assign oacq_read_beat_data = 1'h0;
+ assign T_962 = {1'h0,3'h7};
+ assign T_963 = {5'h0,1'h1};
+ assign T_964 = {T_962,T_963};
+ assign T_966 = {5'h0,1'h1};
+ assign T_967 = {3'h7,T_966};
+ assign T_969 = {1'h0,1'h1};
+ assign T_971 = {1'h0,1'h1};
+ assign T_973 = {1'h0,3'h7};
+ assign T_974 = {5'h0,1'h1};
+ assign T_975 = {T_973,T_974};
+ assign T_977 = {5'h0,1'h1};
+ assign T_979 = {5'h1,1'h1};
+ assign T_980 = 3'h6 == 3'h1;
+ assign T_981 = T_980 ? T_979 : 1'h0;
+ assign T_982 = 3'h5 == 3'h1;
+ assign T_983 = T_982 ? T_977 : T_981;
+ assign T_984 = 3'h4 == 3'h1;
+ assign T_985 = T_984 ? T_975 : T_983;
+ assign T_986 = 3'h3 == 3'h1;
+ assign T_987 = T_986 ? T_971 : T_985;
+ assign T_988 = 3'h2 == 3'h1;
+ assign T_989 = T_988 ? T_969 : T_987;
+ assign T_990 = 3'h1 == 3'h1;
+ assign T_991 = T_990 ? T_967 : T_989;
+ assign T_992 = 3'h0 == 3'h1;
+ assign T_993 = T_992 ? T_964 : T_991;
+ assign oacq_read_block_addr_block = xact_addr_block;
+ assign oacq_read_block_client_xact_id = 2'h2;
+ assign oacq_read_block_addr_beat = 1'h0;
+ assign oacq_read_block_is_builtin_type = 1'h1;
+ assign oacq_read_block_a_type = 3'h1;
+ assign oacq_read_block_union = T_993;
+ assign oacq_read_block_data = 1'h0;
+ assign T_1011 = state == 1'h1;
+ assign T_1012 = state == 2'h3;
+ assign T_1013_addr_block = subblock_type ? oacq_write_beat_addr_block : oacq_write_block_addr_block;
+ assign T_1013_client_xact_id = subblock_type ? oacq_write_beat_client_xact_id : oacq_write_block_client_xact_id;
+ assign T_1013_addr_beat = subblock_type ? oacq_write_beat_addr_beat : oacq_write_block_addr_beat;
+ assign T_1013_is_builtin_type = subblock_type ? oacq_write_beat_is_builtin_type : oacq_write_block_is_builtin_type;
+ assign T_1013_a_type = subblock_type ? oacq_write_beat_a_type : oacq_write_block_a_type;
+ assign T_1013_union = subblock_type ? oacq_write_beat_union : oacq_write_block_union;
+ assign T_1013_data = subblock_type ? oacq_write_beat_data : oacq_write_block_data;
+ assign T_1021_addr_block = subblock_type ? oacq_read_beat_addr_block : oacq_read_block_addr_block;
+ assign T_1021_client_xact_id = subblock_type ? oacq_read_beat_client_xact_id : oacq_read_block_client_xact_id;
+ assign T_1021_addr_beat = subblock_type ? oacq_read_beat_addr_beat : oacq_read_block_addr_beat;
+ assign T_1021_is_builtin_type = subblock_type ? oacq_read_beat_is_builtin_type : oacq_read_block_is_builtin_type;
+ assign T_1021_a_type = subblock_type ? oacq_read_beat_a_type : oacq_read_block_a_type;
+ assign T_1021_union = subblock_type ? oacq_read_beat_union : oacq_read_block_union;
+ assign T_1021_data = subblock_type ? oacq_read_beat_data : oacq_read_block_data;
+ assign T_1029_addr_block = T_1012 ? T_1013_addr_block : T_1021_addr_block;
+ assign T_1029_client_xact_id = T_1012 ? T_1013_client_xact_id : T_1021_client_xact_id;
+ assign T_1029_addr_beat = T_1012 ? T_1013_addr_beat : T_1021_addr_beat;
+ assign T_1029_is_builtin_type = T_1012 ? T_1013_is_builtin_type : T_1021_is_builtin_type;
+ assign T_1029_a_type = T_1012 ? T_1013_a_type : T_1021_a_type;
+ assign T_1029_union = T_1012 ? T_1013_union : T_1021_union;
+ assign T_1029_data = T_1012 ? T_1013_data : T_1021_data;
+ assign T_1037_addr_block = T_1011 ? oacq_probe_addr_block : T_1029_addr_block;
+ assign T_1037_client_xact_id = T_1011 ? oacq_probe_client_xact_id : T_1029_client_xact_id;
+ assign T_1037_addr_beat = T_1011 ? oacq_probe_addr_beat : T_1029_addr_beat;
+ assign T_1037_is_builtin_type = T_1011 ? oacq_probe_is_builtin_type : T_1029_is_builtin_type;
+ assign T_1037_a_type = T_1011 ? oacq_probe_a_type : T_1029_a_type;
+ assign T_1037_union = T_1011 ? oacq_probe_union : T_1029_union;
+ assign T_1037_data = T_1011 ? oacq_probe_data : T_1029_data;
+ assign T_1054 = 3'h4 == xact_a_type;
+ assign T_1055 = T_1054 ? 1'h0 : 2'h2;
+ assign T_1056 = 3'h6 == xact_a_type;
+ assign T_1057 = T_1056 ? 1'h0 : T_1055;
+ assign T_1058 = 3'h5 == xact_a_type;
+ assign T_1059 = T_1058 ? 2'h2 : T_1057;
+ assign T_1060 = 3'h2 == xact_a_type;
+ assign T_1061 = T_1060 ? 1'h0 : T_1059;
+ assign T_1062 = 3'h0 == xact_a_type;
+ assign T_1063 = T_1062 ? 2'h2 : T_1061;
+ assign T_1064 = 3'h3 == xact_a_type;
+ assign T_1065 = T_1064 ? 1'h0 : T_1063;
+ assign T_1066 = 3'h1 == xact_a_type;
+ assign T_1067 = T_1066 ? 2'h2 : T_1065;
+ assign T_1068 = 1'h1 == xact_a_type;
+ assign T_1069 = T_1068 ? 1'h0 : 2'h2;
+ assign T_1070 = 1'h0 == xact_a_type;
+ assign T_1071 = T_1070 ? 1'h1 : T_1069;
+ assign T_1072 = xact_is_builtin_type ? T_1067 : T_1071;
+ assign T_1077_addr_block = xact_addr_block;
+ assign T_1077_p_type = T_1072;
+ assign T_1077_client_id = 1'h0;
+ assign T_1100 = 3'h6 == xact_a_type;
+ assign T_1101 = T_1100 ? 3'h1 : 3'h3;
+ assign T_1102 = 3'h5 == xact_a_type;
+ assign T_1103 = T_1102 ? 3'h1 : T_1101;
+ assign T_1104 = 3'h4 == xact_a_type;
+ assign T_1105 = T_1104 ? 3'h4 : T_1103;
+ assign T_1106 = 3'h3 == xact_a_type;
+ assign T_1107 = T_1106 ? 3'h3 : T_1105;
+ assign T_1108 = 3'h2 == xact_a_type;
+ assign T_1109 = T_1108 ? 3'h3 : T_1107;
+ assign T_1110 = 3'h1 == xact_a_type;
+ assign T_1111 = T_1110 ? 3'h5 : T_1109;
+ assign T_1112 = 3'h0 == xact_a_type;
+ assign T_1113 = T_1112 ? 3'h4 : T_1111;
+ assign T_1114 = xact_a_type == 1'h0;
+ assign T_1117 = 1'h0 == 1'h0;
+ assign T_1118 = T_1117 ? 1'h0 : 1'h1;
+ assign T_1119 = T_1114 ? T_1118 : 1'h1;
+ assign T_1120 = xact_is_builtin_type ? T_1113 : T_1119;
+ assign T_1129_addr_beat = 1'h0;
+ assign T_1129_client_xact_id = xact_client_xact_id;
+ assign T_1129_manager_xact_id = 2'h2;
+ assign T_1129_is_builtin_type = xact_is_builtin_type;
+ assign T_1129_g_type = T_1120;
+ assign T_1129_data = 1'h0;
+ assign T_1129_client_id = xact_client_id;
+ assign T_1140 = state != 1'h0;
+ assign T_1141 = T_1140 & collect_iacq_data;
+ assign T_1142 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_1143 = T_1141 & T_1142;
+ assign T_1144 = io_inner_acquire_bits_client_id != xact_client_id;
+ assign T_1145 = T_1143 & T_1144;
+ assign T_1147 = T_1145 == 1'h0;
+ assign T_1149 = reset == 1'h0;
+ assign T_1151 = T_1147 == 1'h0;
+ assign T_1153 = reset == 1'h0;
+ assign T_1154 = state != 1'h0;
+ assign T_1155 = T_1154 & collect_iacq_data;
+ assign T_1156 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_1157 = T_1155 & T_1156;
+ assign T_1158 = io_inner_acquire_bits_client_xact_id != xact_client_xact_id;
+ assign T_1159 = T_1157 & T_1158;
+ assign T_1161 = T_1159 == 1'h0;
+ assign T_1163 = reset == 1'h0;
+ assign T_1165 = T_1161 == 1'h0;
+ assign T_1167 = reset == 1'h0;
+ assign T_1168 = state == 1'h0;
+ assign T_1169 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_1170 = T_1168 & T_1169;
+ assign T_1172 = 1'h1 & io_inner_acquire_bits_is_builtin_type;
+ assign T_1175_0 = 3'h3;
+ assign T_1178 = T_1175_0 == io_inner_acquire_bits_a_type;
+ assign T_1180 = 1'h0 | T_1178;
+ assign T_1181 = T_1172 & T_1180;
+ assign T_1182 = T_1170 & T_1181;
+ assign T_1184 = io_inner_acquire_bits_addr_beat != 1'h0;
+ assign T_1185 = T_1182 & T_1184;
+ assign T_1187 = T_1185 == 1'h0;
+ assign T_1189 = reset == 1'h0;
+ assign T_1191 = T_1187 == 1'h0;
+ assign T_1193 = reset == 1'h0;
+ assign GEN_3 = io_inner_acquire_bits_data;
+ assign T_1197 = io_inner_acquire_bits_union[12:9];
+ assign T_1198 = T_1197[3];
+ assign T_1200 = 1'h1 << T_1198;
+ assign T_1202 = io_inner_acquire_bits_a_type == 3'h4;
+ assign T_1203 = io_inner_acquire_bits_is_builtin_type & T_1202;
+ assign T_1204 = T_1200[0];
+ assign T_1205 = T_1200[1];
+ assign T_1207_0 = T_1204;
+ assign T_1207_1 = T_1205;
+ assign T_1212 = 8'h0 - T_1207_0;
+ assign T_1213 = T_1212[7:0];
+ assign T_1215 = 8'h0 - T_1207_1;
+ assign T_1216 = T_1215[7:0];
+ assign T_1218_0 = T_1213;
+ assign T_1218_1 = T_1216;
+ assign T_1222 = {T_1218_1,T_1218_0};
+ assign T_1224 = io_inner_acquire_bits_a_type == 3'h3;
+ assign T_1225 = io_inner_acquire_bits_is_builtin_type & T_1224;
+ assign T_1227 = io_inner_acquire_bits_a_type == 3'h2;
+ assign T_1228 = io_inner_acquire_bits_is_builtin_type & T_1227;
+ assign T_1229 = T_1225 | T_1228;
+ assign T_1230 = io_inner_acquire_bits_union[16:1];
+ assign T_1232 = T_1229 ? T_1230 : 16'h0;
+ assign T_1233 = T_1203 ? T_1222 : T_1232;
+ assign GEN_4 = T_1233;
+ assign T_1236 = 1'h1 << io_inner_acquire_bits_addr_beat;
+ assign T_1237 = iacq_data_valid | T_1236;
+ assign T_1238 = ~ iacq_data_valid;
+ assign T_1239 = T_1238 | T_1236;
+ assign T_1240 = ~ T_1239;
+ assign T_1241 = 1'h1 ? T_1237 : T_1240;
+ assign T_1245 = 1'h0 == state;
+ assign GEN_5 = io_inner_acquire_bits_data;
+ assign T_1251 = io_inner_acquire_bits_union[12:9];
+ assign T_1252 = T_1251[3];
+ assign T_1254 = 1'h1 << T_1252;
+ assign T_1256 = io_inner_acquire_bits_a_type == 3'h4;
+ assign T_1257 = io_inner_acquire_bits_is_builtin_type & T_1256;
+ assign T_1258 = T_1254[0];
+ assign T_1259 = T_1254[1];
+ assign T_1261_0 = T_1258;
+ assign T_1261_1 = T_1259;
+ assign T_1266 = 8'h0 - T_1261_0;
+ assign T_1267 = T_1266[7:0];
+ assign T_1269 = 8'h0 - T_1261_1;
+ assign T_1270 = T_1269[7:0];
+ assign T_1272_0 = T_1267;
+ assign T_1272_1 = T_1270;
+ assign T_1276 = {T_1272_1,T_1272_0};
+ assign T_1278 = io_inner_acquire_bits_a_type == 3'h3;
+ assign T_1279 = io_inner_acquire_bits_is_builtin_type & T_1278;
+ assign T_1281 = io_inner_acquire_bits_a_type == 3'h2;
+ assign T_1282 = io_inner_acquire_bits_is_builtin_type & T_1281;
+ assign T_1283 = T_1279 | T_1282;
+ assign T_1284 = io_inner_acquire_bits_union[16:1];
+ assign T_1286 = T_1283 ? T_1284 : 16'h0;
+ assign T_1287 = T_1257 ? T_1276 : T_1286;
+ assign GEN_6 = T_1287;
+ assign T_1289 = 1'h1 & io_inner_acquire_bits_is_builtin_type;
+ assign T_1292_0 = 3'h3;
+ assign T_1295 = T_1292_0 == io_inner_acquire_bits_a_type;
+ assign T_1297 = 1'h0 | T_1295;
+ assign T_1298 = T_1289 & T_1297;
+ assign T_1303_0 = 3'h2;
+ assign T_1303_1 = 3'h3;
+ assign T_1303_2 = 3'h4;
+ assign T_1308 = T_1303_0 == io_inner_acquire_bits_a_type;
+ assign T_1309 = T_1303_1 == io_inner_acquire_bits_a_type;
+ assign T_1310 = T_1303_2 == io_inner_acquire_bits_a_type;
+ assign T_1312 = 1'h0 | T_1308;
+ assign T_1313 = T_1312 | T_1309;
+ assign T_1314 = T_1313 | T_1310;
+ assign T_1315 = io_inner_acquire_bits_is_builtin_type & T_1314;
+ assign T_1316 = T_1315 << io_inner_acquire_bits_addr_beat;
+ assign T_1318 = mask_incoherent != 1'h0;
+ assign T_1319 = mask_incoherent[0];
+ assign T_1320 = mask_incoherent[1];
+ assign T_1321 = mask_incoherent[2];
+ assign T_1322 = mask_incoherent[3];
+ assign T_1324 = {1'h0,T_1320};
+ assign T_1325 = T_1319 + T_1324;
+ assign T_1326 = T_1325[1:0];
+ assign T_1329 = {1'h0,T_1322};
+ assign T_1330 = T_1321 + T_1329;
+ assign T_1331 = T_1330[1:0];
+ assign T_1332 = {1'h0,T_1331};
+ assign T_1333 = T_1326 + T_1332;
+ assign T_1334 = T_1333[2:0];
+ assign T_1335 = pending_outer_read_ ? 2'h2 : 3'h4;
+ assign T_1336 = pending_outer_write_ ? 2'h3 : T_1335;
+ assign T_1337 = T_1318 ? 1'h1 : T_1336;
+ assign T_1338 = 1'h1 == state;
+ assign T_1340 = pending_probes != 1'h0;
+ assign T_1342 = 1'h1 << 1'h0;
+ assign T_1343 = ~ T_1342;
+ assign T_1344 = pending_probes & T_1343;
+ assign T_1346_0 = 1'h0;
+ assign T_1346_1 = 1'h1;
+ assign T_1346_2 = 2'h2;
+ assign T_1351 = T_1346_0 == io_inner_release_bits_r_type;
+ assign T_1352 = T_1346_1 == io_inner_release_bits_r_type;
+ assign T_1353 = T_1346_2 == io_inner_release_bits_r_type;
+ assign T_1355 = 1'h0 | T_1351;
+ assign T_1356 = T_1355 | T_1352;
+ assign T_1357 = T_1356 | T_1353;
+ assign T_1359 = T_1357 == 1'h0;
+ assign T_1360 = T_1359 | io_outer_acquire_ready;
+ assign T_1362_0 = 1'h0;
+ assign T_1362_1 = 1'h1;
+ assign T_1362_2 = 2'h2;
+ assign T_1367 = T_1362_0 == io_inner_release_bits_r_type;
+ assign T_1368 = T_1362_1 == io_inner_release_bits_r_type;
+ assign T_1369 = T_1362_2 == io_inner_release_bits_r_type;
+ assign T_1371 = 1'h0 | T_1367;
+ assign T_1372 = T_1371 | T_1368;
+ assign T_1373 = T_1372 | T_1369;
+ assign T_1377 = release_count - 1'h1;
+ assign T_1378 = T_1377[0:0];
+ assign T_1380 = release_count == 1'h1;
+ assign T_1381 = pending_outer_read ? 2'h2 : 3'h4;
+ assign T_1382 = pending_outer_write ? 2'h3 : T_1381;
+ assign T_1384 = T_1373 == 1'h0;
+ assign T_1386 = release_count - 1'h1;
+ assign T_1387 = T_1386[0:0];
+ assign T_1389 = release_count == 1'h1;
+ assign T_1390 = pending_outer_read ? 2'h2 : 3'h4;
+ assign T_1391 = pending_outer_write ? 2'h3 : T_1390;
+ assign T_1392 = 2'h3 == state;
+ assign T_1394 = pending_ognt_ack == 1'h0;
+ assign T_1396 = collect_iacq_data == 1'h0;
+ assign T_1397 = iacq_data_valid >> oacq_data_cnt;
+ assign T_1398 = T_1397[0];
+ assign T_1399 = T_1396 | T_1398;
+ assign T_1400 = T_1394 & T_1399;
+ assign T_1402 = pending_outer_read ? 2'h2 : 3'h5;
+ assign T_1403 = 2'h2 == state;
+ assign T_1405 = pending_ognt_ack == 1'h0;
+ assign T_1406 = io_outer_acquire_ready & io_outer_acquire_valid;
+ assign T_1407 = 3'h5 == state;
+ assign T_1410 = 1'h0 == 1'h0;
+ assign T_1412 = io_inner_grant_bits_g_type == 3'h0;
+ assign T_1413 = io_inner_grant_bits_is_builtin_type & T_1412;
+ assign T_1415 = T_1413 == 1'h0;
+ assign T_1416 = T_1410 & T_1415;
+ assign T_1417 = T_1416 ? 3'h6 : 1'h0;
+ assign T_1418 = 3'h4 == state;
+ assign T_1422 = 1'h0 == 1'h0;
+ assign T_1424 = io_inner_grant_bits_g_type == 3'h0;
+ assign T_1425 = io_inner_grant_bits_is_builtin_type & T_1424;
+ assign T_1427 = T_1425 == 1'h0;
+ assign T_1428 = T_1422 & T_1427;
+ assign T_1429 = T_1428 ? 3'h6 : 1'h0;
+ assign T_1430 = 3'h6 == state;
+ assign GEN_9 = T_325 & T_327;
+ assign GEN_10 = T_1149 & T_1151;
+ assign GEN_11 = T_1163 & T_1165;
+ assign GEN_12 = T_1189 & T_1191;
+ assign GEN_13 = 1'h0 == 1'h0;
+ assign GEN_14 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_15 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_16 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_17 = 1'h1 == 1'h0;
+ assign GEN_18 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_19 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_20 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_21 = 2'h2 == 1'h0;
+ assign GEN_22 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_23 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_24 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_25 = 2'h3 == 1'h0;
+ assign GEN_26 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_27 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_28 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_29 = 1'h0 == 1'h0;
+ assign GEN_30 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_31 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_32 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_33 = 1'h1 == 1'h0;
+ assign GEN_34 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_35 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_36 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_37 = 2'h2 == 1'h0;
+ assign GEN_38 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_39 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_40 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_41 = 2'h3 == 1'h0;
+ assign GEN_42 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_43 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_44 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_45 = 2'h3 == oacq_data_cnt;
+ assign GEN_46 = 2'h2 == oacq_data_cnt;
+ assign GEN_47 = 1'h1 == oacq_data_cnt;
+ assign GEN_48 = 2'h3 == oacq_data_cnt;
+ assign GEN_49 = 2'h2 == oacq_data_cnt;
+ assign GEN_50 = 1'h1 == oacq_data_cnt;
+ assign GEN_51 = 2'h3 == oacq_data_cnt;
+ assign GEN_52 = 2'h2 == oacq_data_cnt;
+ assign GEN_53 = 1'h1 == oacq_data_cnt;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ state = {1{$random}};
+ xact_addr_block = {1{$random}};
+ xact_client_xact_id = {1{$random}};
+ xact_addr_beat = {1{$random}};
+ xact_is_builtin_type = {1{$random}};
+ xact_a_type = {1{$random}};
+ xact_union = {1{$random}};
+ xact_data_buffer_0 = {1{$random}};
+ xact_data_buffer_1 = {1{$random}};
+ xact_data_buffer_2 = {1{$random}};
+ xact_data_buffer_3 = {1{$random}};
+ xact_wmask_buffer_0 = {1{$random}};
+ xact_wmask_buffer_1 = {1{$random}};
+ xact_wmask_buffer_2 = {1{$random}};
+ xact_wmask_buffer_3 = {1{$random}};
+ xact_client_id = {1{$random}};
+ release_count = {1{$random}};
+ pending_probes = {1{$random}};
+ collect_iacq_data = {1{$random}};
+ iacq_data_valid = {1{$random}};
+ T_371 = {1{$random}};
+ T_403 = {1{$random}};
+ T_441 = {1{$random}};
+ T_469 = {1{$random}};
+ T_504 = {1{$random}};
+ pending_ognt_ack = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1430) begin
+ if(io_inner_finish_valid) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1418) begin
+ if(io_inner_grant_ready) begin
+ state <= T_1429;
+ end else begin
+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
+ end else begin
+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end
+ end else begin
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+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end else begin
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+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
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+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
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+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
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+ end
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+ end
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+ state <= T_1402;
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ end else begin
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
+ end else begin
+ ;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ end else begin
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end
+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1418) begin
+ if(io_inner_grant_ready) begin
+ state <= T_1429;
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+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
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+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
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+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end
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+ end
+ end else begin
+ if(T_1392) begin
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+ state <= T_1402;
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ if(T_1380) begin
+ state <= T_1382;
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ end
+ end else begin
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
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+ end
+ end else begin
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+ if(T_1406) begin
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ state <= T_1337;
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+ end
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ state <= T_1337;
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+ end
+ end else begin
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
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+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
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+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1382;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_addr_block <= io_inner_acquire_bits_addr_block;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_client_xact_id <= io_inner_acquire_bits_client_xact_id;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_addr_beat <= io_inner_acquire_bits_addr_beat;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_is_builtin_type <= io_inner_acquire_bits_is_builtin_type;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_a_type <= io_inner_acquire_bits_a_type;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_union <= io_inner_acquire_bits_union;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_13) begin
+ xact_data_buffer_0 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_14) begin
+ xact_data_buffer_0 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_15) begin
+ xact_data_buffer_0 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_16) begin
+ xact_data_buffer_0 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_17) begin
+ xact_data_buffer_1 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_18) begin
+ xact_data_buffer_1 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_19) begin
+ xact_data_buffer_1 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_20) begin
+ xact_data_buffer_1 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_21) begin
+ xact_data_buffer_2 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_22) begin
+ xact_data_buffer_2 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_23) begin
+ xact_data_buffer_2 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_24) begin
+ xact_data_buffer_2 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_25) begin
+ xact_data_buffer_3 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_26) begin
+ xact_data_buffer_3 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_27) begin
+ xact_data_buffer_3 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_28) begin
+ xact_data_buffer_3 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_29) begin
+ xact_wmask_buffer_0 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_30) begin
+ xact_wmask_buffer_0 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_31) begin
+ xact_wmask_buffer_0 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_32) begin
+ xact_wmask_buffer_0 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_33) begin
+ xact_wmask_buffer_1 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_34) begin
+ xact_wmask_buffer_1 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_35) begin
+ xact_wmask_buffer_1 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_36) begin
+ xact_wmask_buffer_1 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_37) begin
+ xact_wmask_buffer_2 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_38) begin
+ xact_wmask_buffer_2 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_39) begin
+ xact_wmask_buffer_2 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_40) begin
+ xact_wmask_buffer_2 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_41) begin
+ xact_wmask_buffer_3 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_42) begin
+ xact_wmask_buffer_3 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_43) begin
+ xact_wmask_buffer_3 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_44) begin
+ xact_wmask_buffer_3 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_client_id <= io_inner_acquire_bits_client_id;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ release_count <= 1'h0;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ release_count <= T_1387;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ release_count <= T_1378;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ pending_probes <= 1'h0;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_probe_ready) begin
+ pending_probes <= T_1344;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ pending_probes <= mask_incoherent;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ pending_probes <= mask_incoherent;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ collect_iacq_data <= 1'h0;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ collect_iacq_data <= T_1298;
+ end else begin
+ if(collect_iacq_data) begin
+ if(iacq_data_done) begin
+ collect_iacq_data <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(iacq_data_done) begin
+ collect_iacq_data <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ iacq_data_valid <= 4'h0;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ iacq_data_valid <= T_1316;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ iacq_data_valid <= T_1241;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ iacq_data_valid <= T_1241;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ T_371 <= 2'h0;
+ end else begin
+ if(T_369) begin
+ T_371 <= T_380;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_403 <= 2'h0;
+ end else begin
+ if(T_401) begin
+ T_403 <= T_412;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_441 <= 2'h0;
+ end else begin
+ if(T_439) begin
+ T_441 <= T_450;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_469 <= 2'h0;
+ end else begin
+ if(T_467) begin
+ T_469 <= T_478;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_504 <= 2'h0;
+ end else begin
+ if(T_502) begin
+ T_504 <= T_513;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ pending_ognt_ack <= 1'h1;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ pending_ognt_ack <= 1'h1;
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ pending_ognt_ack <= 1'h1;
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ `ifndef SYNTHESIS
+ if(GEN_9 & T_329) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_325 & T_327) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_10 & T_1153) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_1149 & T_1151) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_11 & T_1167) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_1163 & T_1165) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_12 & T_1193) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_1189 & T_1191) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ end
+endmodule
+module BroadcastAcquireTracker_28(
+ input clk,
+ input reset,
+ output io_inner_acquire_ready,
+ input io_inner_acquire_valid,
+ input [25:0] io_inner_acquire_bits_addr_block,
+ input [1:0] io_inner_acquire_bits_client_xact_id,
+ input [1:0] io_inner_acquire_bits_addr_beat,
+ input io_inner_acquire_bits_is_builtin_type,
+ input [2:0] io_inner_acquire_bits_a_type,
+ input [16:0] io_inner_acquire_bits_union,
+ input [3:0] io_inner_acquire_bits_data,
+ input [1:0] io_inner_acquire_bits_client_id,
+ input io_inner_grant_ready,
+ output io_inner_grant_valid,
+ output [1:0] io_inner_grant_bits_addr_beat,
+ output [1:0] io_inner_grant_bits_client_xact_id,
+ output [3:0] io_inner_grant_bits_manager_xact_id,
+ output io_inner_grant_bits_is_builtin_type,
+ output [3:0] io_inner_grant_bits_g_type,
+ output [3:0] io_inner_grant_bits_data,
+ output [1:0] io_inner_grant_bits_client_id,
+ output io_inner_finish_ready,
+ input io_inner_finish_valid,
+ input [3:0] io_inner_finish_bits_manager_xact_id,
+ input io_inner_probe_ready,
+ output io_inner_probe_valid,
+ output [25:0] io_inner_probe_bits_addr_block,
+ output [1:0] io_inner_probe_bits_p_type,
+ output [1:0] io_inner_probe_bits_client_id,
+ output io_inner_release_ready,
+ input io_inner_release_valid,
+ input [1:0] io_inner_release_bits_addr_beat,
+ input [25:0] io_inner_release_bits_addr_block,
+ input [1:0] io_inner_release_bits_client_xact_id,
+ input io_inner_release_bits_voluntary,
+ input [2:0] io_inner_release_bits_r_type,
+ input [3:0] io_inner_release_bits_data,
+ input [1:0] io_inner_release_bits_client_id,
+ input io_incoherent_0,
+ input io_outer_acquire_ready,
+ output io_outer_acquire_valid,
+ output [25:0] io_outer_acquire_bits_addr_block,
+ output [3:0] io_outer_acquire_bits_client_xact_id,
+ output [1:0] io_outer_acquire_bits_addr_beat,
+ output io_outer_acquire_bits_is_builtin_type,
+ output [2:0] io_outer_acquire_bits_a_type,
+ output [16:0] io_outer_acquire_bits_union,
+ output [3:0] io_outer_acquire_bits_data,
+ output io_outer_grant_ready,
+ input io_outer_grant_valid,
+ input [1:0] io_outer_grant_bits_addr_beat,
+ input [3:0] io_outer_grant_bits_client_xact_id,
+ input io_outer_grant_bits_manager_xact_id,
+ input io_outer_grant_bits_is_builtin_type,
+ input [3:0] io_outer_grant_bits_g_type,
+ input [3:0] io_outer_grant_bits_data,
+ output io_has_acquire_conflict,
+ output io_has_acquire_match,
+ output io_has_release_match
+);
+ reg [2:0] state;
+ reg [25:0] xact_addr_block;
+ reg [1:0] xact_client_xact_id;
+ reg [1:0] xact_addr_beat;
+ reg xact_is_builtin_type;
+ reg [2:0] xact_a_type;
+ reg [16:0] xact_union;
+ reg [3:0] xact_data_buffer_0;
+ reg [3:0] xact_data_buffer_1;
+ reg [3:0] xact_data_buffer_2;
+ reg [3:0] xact_data_buffer_3;
+ reg [15:0] xact_wmask_buffer_0;
+ reg [15:0] xact_wmask_buffer_1;
+ reg [15:0] xact_wmask_buffer_2;
+ reg [15:0] xact_wmask_buffer_3;
+ reg [1:0] xact_client_id;
+ wire coh_sharers;
+ wire T_303;
+ wire T_304;
+ wire [2:0] T_309_0;
+ wire [2:0] T_309_1;
+ wire [2:0] T_309_2;
+ wire T_314;
+ wire T_315;
+ wire T_316;
+ wire T_318;
+ wire T_319;
+ wire T_320;
+ wire T_321;
+ wire T_323;
+ wire T_325;
+ wire T_327;
+ wire T_329;
+ reg release_count;
+ reg pending_probes;
+ wire T_334;
+ wire T_336_0;
+ wire GEN_7;
+ wire T_341;
+ wire [3:0] T_344;
+ wire [3:0] T_345;
+ wire T_346;
+ wire [3:0] T_347;
+ wire [3:0] T_348;
+ wire [3:0] mask_self;
+ wire T_350;
+ wire [3:0] mask_incoherent;
+ reg collect_iacq_data;
+ reg [3:0] iacq_data_valid;
+ wire T_356;
+ wire T_359;
+ wire [2:0] T_362_0;
+ wire T_365;
+ wire T_367;
+ wire T_368;
+ wire T_369;
+ reg [1:0] T_371;
+ wire T_373;
+ wire T_375;
+ wire [2:0] T_378;
+ wire [1:0] T_379;
+ wire [1:0] T_380;
+ wire T_381;
+ wire [1:0] T_382;
+ wire iacq_data_done;
+ wire T_384;
+ wire [1:0] T_388_0;
+ wire [1:0] T_388_1;
+ wire [1:0] T_388_2;
+ wire T_393;
+ wire T_394;
+ wire T_395;
+ wire T_397;
+ wire T_398;
+ wire T_399;
+ wire T_400;
+ wire T_401;
+ reg [1:0] T_403;
+ wire T_405;
+ wire T_407;
+ wire [2:0] T_410;
+ wire [1:0] T_411;
+ wire [1:0] T_412;
+ wire T_413;
+ wire [1:0] T_414;
+ wire irel_data_done;
+ wire T_417;
+ wire [2:0] T_421_0;
+ wire T_424;
+ wire T_426;
+ wire T_428_0;
+ wire T_428_1;
+ wire T_432;
+ wire T_433;
+ wire T_435;
+ wire T_436;
+ wire T_437;
+ wire T_438;
+ wire T_439;
+ reg [1:0] T_441;
+ wire T_443;
+ wire T_445;
+ wire [2:0] T_448;
+ wire [1:0] T_449;
+ wire [1:0] T_450;
+ wire T_451;
+ wire [1:0] ignt_data_cnt;
+ wire ignt_data_done;
+ wire T_455;
+ wire T_457;
+ wire [2:0] T_460_0;
+ wire T_463;
+ wire T_465;
+ wire T_466;
+ wire T_467;
+ reg [1:0] T_469;
+ wire T_471;
+ wire T_473;
+ wire [2:0] T_476;
+ wire [1:0] T_477;
+ wire [1:0] T_478;
+ wire T_479;
+ wire [1:0] oacq_data_cnt;
+ wire oacq_data_done;
+ wire T_482;
+ wire [2:0] T_487_0;
+ wire T_490;
+ wire T_492;
+ wire T_494_0;
+ wire T_497;
+ wire T_499;
+ wire T_500;
+ wire T_501;
+ wire T_502;
+ reg [1:0] T_504;
+ wire T_506;
+ wire T_508;
+ wire [2:0] T_511;
+ wire [1:0] T_512;
+ wire [1:0] T_513;
+ wire T_514;
+ wire [1:0] T_515;
+ wire ognt_data_done;
+ reg pending_ognt_ack;
+ wire [2:0] T_523_0;
+ wire [2:0] T_523_1;
+ wire [2:0] T_523_2;
+ wire T_528;
+ wire T_529;
+ wire T_530;
+ wire T_532;
+ wire T_533;
+ wire T_534;
+ wire pending_outer_write;
+ wire [2:0] T_540_0;
+ wire [2:0] T_540_1;
+ wire [2:0] T_540_2;
+ wire T_545;
+ wire T_546;
+ wire T_547;
+ wire T_549;
+ wire T_550;
+ wire T_551;
+ wire pending_outer_write_;
+ wire [2:0] T_556_0;
+ wire [2:0] T_556_1;
+ wire T_560;
+ wire T_561;
+ wire T_563;
+ wire T_564;
+ wire T_566_0;
+ wire T_566_1;
+ wire T_570;
+ wire T_571;
+ wire T_573;
+ wire T_574;
+ wire pending_outer_read;
+ wire T_594;
+ wire [2:0] T_595;
+ wire T_596;
+ wire [2:0] T_597;
+ wire T_598;
+ wire [2:0] T_599;
+ wire T_600;
+ wire [2:0] T_601;
+ wire T_602;
+ wire [2:0] T_603;
+ wire T_604;
+ wire [2:0] T_605;
+ wire T_606;
+ wire [2:0] T_607;
+ wire T_608;
+ wire T_611;
+ wire T_612;
+ wire T_613;
+ wire [2:0] T_614;
+ wire [1:0] T_623_addr_beat;
+ wire [1:0] T_623_client_xact_id;
+ wire [3:0] T_623_manager_xact_id;
+ wire T_623_is_builtin_type;
+ wire [3:0] T_623_g_type;
+ wire [3:0] T_623_data;
+ wire [1:0] T_623_client_id;
+ wire [2:0] T_634_0;
+ wire [2:0] T_634_1;
+ wire T_638;
+ wire T_639;
+ wire T_641;
+ wire T_642;
+ wire T_644_0;
+ wire T_644_1;
+ wire T_648;
+ wire T_649;
+ wire T_651;
+ wire T_652;
+ wire pending_outer_read_;
+ wire [2:0] T_658_0;
+ wire [2:0] T_658_1;
+ wire [2:0] T_658_2;
+ wire T_663;
+ wire T_664;
+ wire T_665;
+ wire T_667;
+ wire T_668;
+ wire T_669;
+ wire subblock_type;
+ wire T_671;
+ wire T_672;
+ wire T_673;
+ wire T_675;
+ wire T_676;
+ wire T_677;
+ wire T_678;
+ wire T_679;
+ wire T_681;
+ wire T_682;
+ wire T_683;
+ wire T_684;
+ wire [15:0] GEN_8;
+ wire [15:0] T_689;
+ wire [3:0] T_695;
+ wire [1:0] T_696;
+ wire [5:0] T_697;
+ wire [1:0] T_699;
+ wire [4:0] T_700;
+ wire [16:0] T_702;
+ wire [16:0] T_704;
+ wire [3:0] T_706;
+ wire [1:0] T_707;
+ wire [5:0] T_708;
+ wire [5:0] T_710;
+ wire [5:0] T_712;
+ wire T_713;
+ wire [5:0] T_714;
+ wire T_715;
+ wire [5:0] T_716;
+ wire T_717;
+ wire [5:0] T_718;
+ wire T_719;
+ wire [16:0] T_720;
+ wire T_721;
+ wire [16:0] T_722;
+ wire T_723;
+ wire [16:0] T_724;
+ wire T_725;
+ wire [16:0] T_726;
+ wire [25:0] oacq_probe_addr_block;
+ wire [3:0] oacq_probe_client_xact_id;
+ wire [1:0] oacq_probe_addr_beat;
+ wire oacq_probe_is_builtin_type;
+ wire [2:0] oacq_probe_a_type;
+ wire [16:0] oacq_probe_union;
+ wire [3:0] oacq_probe_data;
+ wire [3:0] T_744;
+ wire T_745;
+ wire [1:0] T_747;
+ wire T_749;
+ wire T_750;
+ wire T_751;
+ wire T_752;
+ wire T_754_0;
+ wire T_754_1;
+ wire [8:0] T_759;
+ wire [7:0] T_760;
+ wire [8:0] T_762;
+ wire [7:0] T_763;
+ wire [7:0] T_765_0;
+ wire [7:0] T_765_1;
+ wire [15:0] T_769;
+ wire T_771;
+ wire T_772;
+ wire T_774;
+ wire T_775;
+ wire T_776;
+ wire [15:0] T_777;
+ wire [15:0] T_779;
+ wire [15:0] T_780;
+ wire [3:0] T_788;
+ wire [1:0] T_789;
+ wire [5:0] T_790;
+ wire [1:0] T_792;
+ wire [4:0] T_793;
+ wire [16:0] T_795;
+ wire [16:0] T_797;
+ wire [3:0] T_799;
+ wire [1:0] T_800;
+ wire [5:0] T_801;
+ wire [5:0] T_803;
+ wire [5:0] T_805;
+ wire T_806;
+ wire [5:0] T_807;
+ wire T_808;
+ wire [5:0] T_809;
+ wire T_810;
+ wire [5:0] T_811;
+ wire T_812;
+ wire [16:0] T_813;
+ wire T_814;
+ wire [16:0] T_815;
+ wire T_816;
+ wire [16:0] T_817;
+ wire T_818;
+ wire [16:0] T_819;
+ wire [25:0] oacq_write_beat_addr_block;
+ wire [3:0] oacq_write_beat_client_xact_id;
+ wire [1:0] oacq_write_beat_addr_beat;
+ wire oacq_write_beat_is_builtin_type;
+ wire [2:0] oacq_write_beat_a_type;
+ wire [16:0] oacq_write_beat_union;
+ wire [3:0] oacq_write_beat_data;
+ wire [3:0] T_846;
+ wire [1:0] T_847;
+ wire [5:0] T_848;
+ wire [1:0] T_850;
+ wire [4:0] T_851;
+ wire [15:0] GEN_0;
+ wire [16:0] T_853;
+ wire [15:0] GEN_1;
+ wire [16:0] T_855;
+ wire [3:0] T_857;
+ wire [1:0] T_858;
+ wire [5:0] T_859;
+ wire [5:0] T_861;
+ wire [5:0] T_863;
+ wire T_864;
+ wire [5:0] T_865;
+ wire T_866;
+ wire [5:0] T_867;
+ wire T_868;
+ wire [5:0] T_869;
+ wire T_870;
+ wire [16:0] T_871;
+ wire T_872;
+ wire [16:0] T_873;
+ wire T_874;
+ wire [16:0] T_875;
+ wire T_876;
+ wire [16:0] T_877;
+ wire [25:0] oacq_write_block_addr_block;
+ wire [3:0] oacq_write_block_client_xact_id;
+ wire [1:0] oacq_write_block_addr_beat;
+ wire oacq_write_block_is_builtin_type;
+ wire [2:0] oacq_write_block_a_type;
+ wire [16:0] oacq_write_block_union;
+ wire [3:0] oacq_write_block_data;
+ wire [3:0] GEN_2;
+ wire [3:0] T_895;
+ wire [2:0] T_896;
+ wire [6:0] T_904;
+ wire [5:0] T_905;
+ wire [12:0] T_906;
+ wire [5:0] T_908;
+ wire [8:0] T_909;
+ wire [1:0] T_911;
+ wire [1:0] T_913;
+ wire [6:0] T_915;
+ wire [5:0] T_916;
+ wire [12:0] T_917;
+ wire [5:0] T_919;
+ wire [5:0] T_921;
+ wire T_922;
+ wire [5:0] T_923;
+ wire T_924;
+ wire [5:0] T_925;
+ wire T_926;
+ wire [12:0] T_927;
+ wire T_928;
+ wire [12:0] T_929;
+ wire T_930;
+ wire [12:0] T_931;
+ wire T_932;
+ wire [12:0] T_933;
+ wire T_934;
+ wire [12:0] T_935;
+ wire [25:0] oacq_read_beat_addr_block;
+ wire [3:0] oacq_read_beat_client_xact_id;
+ wire [1:0] oacq_read_beat_addr_beat;
+ wire oacq_read_beat_is_builtin_type;
+ wire [2:0] oacq_read_beat_a_type;
+ wire [16:0] oacq_read_beat_union;
+ wire [3:0] oacq_read_beat_data;
+ wire [3:0] T_962;
+ wire [5:0] T_963;
+ wire [9:0] T_964;
+ wire [5:0] T_966;
+ wire [8:0] T_967;
+ wire [1:0] T_969;
+ wire [1:0] T_971;
+ wire [3:0] T_973;
+ wire [5:0] T_974;
+ wire [9:0] T_975;
+ wire [5:0] T_977;
+ wire [5:0] T_979;
+ wire T_980;
+ wire [5:0] T_981;
+ wire T_982;
+ wire [5:0] T_983;
+ wire T_984;
+ wire [9:0] T_985;
+ wire T_986;
+ wire [9:0] T_987;
+ wire T_988;
+ wire [9:0] T_989;
+ wire T_990;
+ wire [9:0] T_991;
+ wire T_992;
+ wire [9:0] T_993;
+ wire [25:0] oacq_read_block_addr_block;
+ wire [3:0] oacq_read_block_client_xact_id;
+ wire [1:0] oacq_read_block_addr_beat;
+ wire oacq_read_block_is_builtin_type;
+ wire [2:0] oacq_read_block_a_type;
+ wire [16:0] oacq_read_block_union;
+ wire [3:0] oacq_read_block_data;
+ wire T_1011;
+ wire T_1012;
+ wire [25:0] T_1013_addr_block;
+ wire [3:0] T_1013_client_xact_id;
+ wire [1:0] T_1013_addr_beat;
+ wire T_1013_is_builtin_type;
+ wire [2:0] T_1013_a_type;
+ wire [16:0] T_1013_union;
+ wire [3:0] T_1013_data;
+ wire [25:0] T_1021_addr_block;
+ wire [3:0] T_1021_client_xact_id;
+ wire [1:0] T_1021_addr_beat;
+ wire T_1021_is_builtin_type;
+ wire [2:0] T_1021_a_type;
+ wire [16:0] T_1021_union;
+ wire [3:0] T_1021_data;
+ wire [25:0] T_1029_addr_block;
+ wire [3:0] T_1029_client_xact_id;
+ wire [1:0] T_1029_addr_beat;
+ wire T_1029_is_builtin_type;
+ wire [2:0] T_1029_a_type;
+ wire [16:0] T_1029_union;
+ wire [3:0] T_1029_data;
+ wire [25:0] T_1037_addr_block;
+ wire [3:0] T_1037_client_xact_id;
+ wire [1:0] T_1037_addr_beat;
+ wire T_1037_is_builtin_type;
+ wire [2:0] T_1037_a_type;
+ wire [16:0] T_1037_union;
+ wire [3:0] T_1037_data;
+ wire T_1054;
+ wire [1:0] T_1055;
+ wire T_1056;
+ wire [1:0] T_1057;
+ wire T_1058;
+ wire [1:0] T_1059;
+ wire T_1060;
+ wire [1:0] T_1061;
+ wire T_1062;
+ wire [1:0] T_1063;
+ wire T_1064;
+ wire [1:0] T_1065;
+ wire T_1066;
+ wire [1:0] T_1067;
+ wire T_1068;
+ wire [1:0] T_1069;
+ wire T_1070;
+ wire [1:0] T_1071;
+ wire [1:0] T_1072;
+ wire [25:0] T_1077_addr_block;
+ wire [1:0] T_1077_p_type;
+ wire [1:0] T_1077_client_id;
+ wire T_1100;
+ wire [2:0] T_1101;
+ wire T_1102;
+ wire [2:0] T_1103;
+ wire T_1104;
+ wire [2:0] T_1105;
+ wire T_1106;
+ wire [2:0] T_1107;
+ wire T_1108;
+ wire [2:0] T_1109;
+ wire T_1110;
+ wire [2:0] T_1111;
+ wire T_1112;
+ wire [2:0] T_1113;
+ wire T_1114;
+ wire T_1117;
+ wire T_1118;
+ wire T_1119;
+ wire [2:0] T_1120;
+ wire [1:0] T_1129_addr_beat;
+ wire [1:0] T_1129_client_xact_id;
+ wire [3:0] T_1129_manager_xact_id;
+ wire T_1129_is_builtin_type;
+ wire [3:0] T_1129_g_type;
+ wire [3:0] T_1129_data;
+ wire [1:0] T_1129_client_id;
+ wire T_1140;
+ wire T_1141;
+ wire T_1142;
+ wire T_1143;
+ wire T_1144;
+ wire T_1145;
+ wire T_1147;
+ wire T_1149;
+ wire T_1151;
+ wire T_1153;
+ wire T_1154;
+ wire T_1155;
+ wire T_1156;
+ wire T_1157;
+ wire T_1158;
+ wire T_1159;
+ wire T_1161;
+ wire T_1163;
+ wire T_1165;
+ wire T_1167;
+ wire T_1168;
+ wire T_1169;
+ wire T_1170;
+ wire T_1172;
+ wire [2:0] T_1175_0;
+ wire T_1178;
+ wire T_1180;
+ wire T_1181;
+ wire T_1182;
+ wire T_1184;
+ wire T_1185;
+ wire T_1187;
+ wire T_1189;
+ wire T_1191;
+ wire T_1193;
+ wire [3:0] GEN_3;
+ wire [3:0] T_1197;
+ wire T_1198;
+ wire [1:0] T_1200;
+ wire T_1202;
+ wire T_1203;
+ wire T_1204;
+ wire T_1205;
+ wire T_1207_0;
+ wire T_1207_1;
+ wire [8:0] T_1212;
+ wire [7:0] T_1213;
+ wire [8:0] T_1215;
+ wire [7:0] T_1216;
+ wire [7:0] T_1218_0;
+ wire [7:0] T_1218_1;
+ wire [15:0] T_1222;
+ wire T_1224;
+ wire T_1225;
+ wire T_1227;
+ wire T_1228;
+ wire T_1229;
+ wire [15:0] T_1230;
+ wire [15:0] T_1232;
+ wire [15:0] T_1233;
+ wire [15:0] GEN_4;
+ wire [3:0] T_1236;
+ wire [3:0] T_1237;
+ wire [3:0] T_1238;
+ wire [3:0] T_1239;
+ wire [3:0] T_1240;
+ wire [3:0] T_1241;
+ wire T_1245;
+ wire [3:0] GEN_5;
+ wire [3:0] T_1251;
+ wire T_1252;
+ wire [1:0] T_1254;
+ wire T_1256;
+ wire T_1257;
+ wire T_1258;
+ wire T_1259;
+ wire T_1261_0;
+ wire T_1261_1;
+ wire [8:0] T_1266;
+ wire [7:0] T_1267;
+ wire [8:0] T_1269;
+ wire [7:0] T_1270;
+ wire [7:0] T_1272_0;
+ wire [7:0] T_1272_1;
+ wire [15:0] T_1276;
+ wire T_1278;
+ wire T_1279;
+ wire T_1281;
+ wire T_1282;
+ wire T_1283;
+ wire [15:0] T_1284;
+ wire [15:0] T_1286;
+ wire [15:0] T_1287;
+ wire [15:0] GEN_6;
+ wire T_1289;
+ wire [2:0] T_1292_0;
+ wire T_1295;
+ wire T_1297;
+ wire T_1298;
+ wire [2:0] T_1303_0;
+ wire [2:0] T_1303_1;
+ wire [2:0] T_1303_2;
+ wire T_1308;
+ wire T_1309;
+ wire T_1310;
+ wire T_1312;
+ wire T_1313;
+ wire T_1314;
+ wire T_1315;
+ wire [3:0] T_1316;
+ wire T_1318;
+ wire T_1319;
+ wire T_1320;
+ wire T_1321;
+ wire T_1322;
+ wire [1:0] T_1324;
+ wire [2:0] T_1325;
+ wire [1:0] T_1326;
+ wire [1:0] T_1329;
+ wire [2:0] T_1330;
+ wire [1:0] T_1331;
+ wire [2:0] T_1332;
+ wire [3:0] T_1333;
+ wire [2:0] T_1334;
+ wire [2:0] T_1335;
+ wire [2:0] T_1336;
+ wire [2:0] T_1337;
+ wire T_1338;
+ wire T_1340;
+ wire [1:0] T_1342;
+ wire [1:0] T_1343;
+ wire [1:0] T_1344;
+ wire [1:0] T_1346_0;
+ wire [1:0] T_1346_1;
+ wire [1:0] T_1346_2;
+ wire T_1351;
+ wire T_1352;
+ wire T_1353;
+ wire T_1355;
+ wire T_1356;
+ wire T_1357;
+ wire T_1359;
+ wire T_1360;
+ wire [1:0] T_1362_0;
+ wire [1:0] T_1362_1;
+ wire [1:0] T_1362_2;
+ wire T_1367;
+ wire T_1368;
+ wire T_1369;
+ wire T_1371;
+ wire T_1372;
+ wire T_1373;
+ wire [1:0] T_1377;
+ wire T_1378;
+ wire T_1380;
+ wire [2:0] T_1381;
+ wire [2:0] T_1382;
+ wire T_1384;
+ wire [1:0] T_1386;
+ wire T_1387;
+ wire T_1389;
+ wire [2:0] T_1390;
+ wire [2:0] T_1391;
+ wire T_1392;
+ wire T_1394;
+ wire T_1396;
+ wire [3:0] T_1397;
+ wire T_1398;
+ wire T_1399;
+ wire T_1400;
+ wire [2:0] T_1402;
+ wire T_1403;
+ wire T_1405;
+ wire T_1406;
+ wire T_1407;
+ wire T_1410;
+ wire T_1412;
+ wire T_1413;
+ wire T_1415;
+ wire T_1416;
+ wire [2:0] T_1417;
+ wire T_1418;
+ wire T_1422;
+ wire T_1424;
+ wire T_1425;
+ wire T_1427;
+ wire T_1428;
+ wire [2:0] T_1429;
+ wire T_1430;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ wire GEN_17;
+ wire GEN_18;
+ wire GEN_19;
+ wire GEN_20;
+ wire GEN_21;
+ wire GEN_22;
+ wire GEN_23;
+ wire GEN_24;
+ wire GEN_25;
+ wire GEN_26;
+ wire GEN_27;
+ wire GEN_28;
+ wire GEN_29;
+ wire GEN_30;
+ wire GEN_31;
+ wire GEN_32;
+ wire GEN_33;
+ wire GEN_34;
+ wire GEN_35;
+ wire GEN_36;
+ wire GEN_37;
+ wire GEN_38;
+ wire GEN_39;
+ wire GEN_40;
+ wire GEN_41;
+ wire GEN_42;
+ wire GEN_43;
+ wire GEN_44;
+ wire GEN_45;
+ wire GEN_46;
+ wire GEN_47;
+ wire GEN_48;
+ wire GEN_49;
+ wire GEN_50;
+ wire GEN_51;
+ wire GEN_52;
+ wire GEN_53;
+ assign io_inner_acquire_ready = T_1245 ? 1'h1 : collect_iacq_data ? 1'h1 : 1'h0;
+ assign io_inner_grant_valid = T_1418 ? 1'h1 : T_1407 ? io_outer_grant_valid : 1'h0;
+ assign io_inner_grant_bits_addr_beat = T_1129_addr_beat;
+ assign io_inner_grant_bits_client_xact_id = T_1129_client_xact_id;
+ assign io_inner_grant_bits_manager_xact_id = T_1129_manager_xact_id;
+ assign io_inner_grant_bits_is_builtin_type = T_1129_is_builtin_type;
+ assign io_inner_grant_bits_g_type = T_1129_g_type;
+ assign io_inner_grant_bits_data = T_1129_data;
+ assign io_inner_grant_bits_client_id = T_1129_client_id;
+ assign io_inner_finish_ready = T_1430 ? 1'h1 : 1'h0;
+ assign io_inner_probe_valid = T_1338 ? T_1340 : 1'h0;
+ assign io_inner_probe_bits_addr_block = T_1077_addr_block;
+ assign io_inner_probe_bits_p_type = T_1077_p_type;
+ assign io_inner_probe_bits_client_id = T_1077_client_id;
+ assign io_inner_release_ready = T_1338 ? T_1360 : 1'h0;
+ assign io_outer_acquire_valid = T_1403 ? T_1405 : T_1392 ? T_1400 : T_1338 ? io_inner_release_valid ? T_1373 ? 1'h1 : 1'h0 : 1'h0 : 1'h0;
+ assign io_outer_acquire_bits_addr_block = T_1037_addr_block;
+ assign io_outer_acquire_bits_client_xact_id = T_1037_client_xact_id;
+ assign io_outer_acquire_bits_addr_beat = T_1037_addr_beat;
+ assign io_outer_acquire_bits_is_builtin_type = T_1037_is_builtin_type;
+ assign io_outer_acquire_bits_a_type = T_1037_a_type;
+ assign io_outer_acquire_bits_union = T_1037_union;
+ assign io_outer_acquire_bits_data = T_1037_data;
+ assign io_outer_grant_ready = T_1407 ? io_inner_grant_ready : pending_ognt_ack ? 1'h1 : 1'h0;
+ assign io_has_acquire_conflict = T_676;
+ assign io_has_acquire_match = T_678;
+ assign io_has_release_match = T_684;
+ assign coh_sharers = 1'h0;
+ assign T_303 = state != 1'h0;
+ assign T_304 = T_303 & xact_is_builtin_type;
+ assign T_309_0 = 3'h4;
+ assign T_309_1 = 3'h5;
+ assign T_309_2 = 3'h6;
+ assign T_314 = T_309_0 == xact_a_type;
+ assign T_315 = T_309_1 == xact_a_type;
+ assign T_316 = T_309_2 == xact_a_type;
+ assign T_318 = 1'h0 | T_314;
+ assign T_319 = T_318 | T_315;
+ assign T_320 = T_319 | T_316;
+ assign T_321 = T_304 & T_320;
+ assign T_323 = T_321 == 1'h0;
+ assign T_325 = reset == 1'h0;
+ assign T_327 = T_323 == 1'h0;
+ assign T_329 = reset == 1'h0;
+ assign T_334 = pending_probes;
+ assign T_336_0 = T_334;
+ assign GEN_7 = $signed(1'h1);
+ assign T_341 = $unsigned(GEN_7);
+ assign T_344 = 1'h1 << io_inner_acquire_bits_client_id;
+ assign T_345 = T_341 | T_344;
+ assign T_346 = ~ T_341;
+ assign T_347 = T_346 | T_344;
+ assign T_348 = ~ T_347;
+ assign mask_self = 1'h0 ? T_345 : T_348;
+ assign T_350 = ~ io_incoherent_0;
+ assign mask_incoherent = mask_self & T_350;
+ assign T_356 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_359 = 1'h1 & io_inner_acquire_bits_is_builtin_type;
+ assign T_362_0 = 3'h3;
+ assign T_365 = T_362_0 == io_inner_acquire_bits_a_type;
+ assign T_367 = 1'h0 | T_365;
+ assign T_368 = T_359 & T_367;
+ assign T_369 = T_356 & T_368;
+ assign T_373 = T_371 == 2'h3;
+ assign T_375 = 1'h0 & T_373;
+ assign T_378 = T_371 + 1'h1;
+ assign T_379 = T_378[1:0];
+ assign T_380 = T_375 ? 1'h0 : T_379;
+ assign T_381 = T_369 & T_373;
+ assign T_382 = T_368 ? T_371 : 1'h0;
+ assign iacq_data_done = T_368 ? T_381 : T_356;
+ assign T_384 = io_inner_release_ready & io_inner_release_valid;
+ assign T_388_0 = 1'h0;
+ assign T_388_1 = 1'h1;
+ assign T_388_2 = 2'h2;
+ assign T_393 = T_388_0 == io_inner_release_bits_r_type;
+ assign T_394 = T_388_1 == io_inner_release_bits_r_type;
+ assign T_395 = T_388_2 == io_inner_release_bits_r_type;
+ assign T_397 = 1'h0 | T_393;
+ assign T_398 = T_397 | T_394;
+ assign T_399 = T_398 | T_395;
+ assign T_400 = 1'h1 & T_399;
+ assign T_401 = T_384 & T_400;
+ assign T_405 = T_403 == 2'h3;
+ assign T_407 = 1'h0 & T_405;
+ assign T_410 = T_403 + 1'h1;
+ assign T_411 = T_410[1:0];
+ assign T_412 = T_407 ? 1'h0 : T_411;
+ assign T_413 = T_401 & T_405;
+ assign T_414 = T_400 ? T_403 : 1'h0;
+ assign irel_data_done = T_400 ? T_413 : T_384;
+ assign T_417 = io_inner_grant_ready & io_inner_grant_valid;
+ assign T_421_0 = 3'h5;
+ assign T_424 = T_421_0 == io_inner_grant_bits_g_type;
+ assign T_426 = 1'h0 | T_424;
+ assign T_428_0 = 1'h0;
+ assign T_428_1 = 1'h1;
+ assign T_432 = T_428_0 == io_inner_grant_bits_g_type;
+ assign T_433 = T_428_1 == io_inner_grant_bits_g_type;
+ assign T_435 = 1'h0 | T_432;
+ assign T_436 = T_435 | T_433;
+ assign T_437 = io_inner_grant_bits_is_builtin_type ? T_426 : T_436;
+ assign T_438 = 1'h1 & T_437;
+ assign T_439 = T_417 & T_438;
+ assign T_443 = T_441 == 2'h3;
+ assign T_445 = 1'h0 & T_443;
+ assign T_448 = T_441 + 1'h1;
+ assign T_449 = T_448[1:0];
+ assign T_450 = T_445 ? 1'h0 : T_449;
+ assign T_451 = T_439 & T_443;
+ assign ignt_data_cnt = T_438 ? T_441 : 1'h0;
+ assign ignt_data_done = T_438 ? T_451 : T_417;
+ assign T_455 = io_outer_acquire_ready & io_outer_acquire_valid;
+ assign T_457 = 1'h1 & io_outer_acquire_bits_is_builtin_type;
+ assign T_460_0 = 3'h3;
+ assign T_463 = T_460_0 == io_outer_acquire_bits_a_type;
+ assign T_465 = 1'h0 | T_463;
+ assign T_466 = T_457 & T_465;
+ assign T_467 = T_455 & T_466;
+ assign T_471 = T_469 == 2'h3;
+ assign T_473 = 1'h0 & T_471;
+ assign T_476 = T_469 + 1'h1;
+ assign T_477 = T_476[1:0];
+ assign T_478 = T_473 ? 1'h0 : T_477;
+ assign T_479 = T_467 & T_471;
+ assign oacq_data_cnt = T_466 ? T_469 : 1'h0;
+ assign oacq_data_done = T_466 ? T_479 : T_455;
+ assign T_482 = io_outer_grant_ready & io_outer_grant_valid;
+ assign T_487_0 = 3'h5;
+ assign T_490 = T_487_0 == io_outer_grant_bits_g_type;
+ assign T_492 = 1'h0 | T_490;
+ assign T_494_0 = 1'h0;
+ assign T_497 = T_494_0 == io_outer_grant_bits_g_type;
+ assign T_499 = 1'h0 | T_497;
+ assign T_500 = io_outer_grant_bits_is_builtin_type ? T_492 : T_499;
+ assign T_501 = 1'h1 & T_500;
+ assign T_502 = T_482 & T_501;
+ assign T_506 = T_504 == 2'h3;
+ assign T_508 = 1'h0 & T_506;
+ assign T_511 = T_504 + 1'h1;
+ assign T_512 = T_511[1:0];
+ assign T_513 = T_508 ? 1'h0 : T_512;
+ assign T_514 = T_502 & T_506;
+ assign T_515 = T_501 ? T_504 : 1'h0;
+ assign ognt_data_done = T_501 ? T_514 : T_482;
+ assign T_523_0 = 3'h2;
+ assign T_523_1 = 3'h3;
+ assign T_523_2 = 3'h4;
+ assign T_528 = T_523_0 == xact_a_type;
+ assign T_529 = T_523_1 == xact_a_type;
+ assign T_530 = T_523_2 == xact_a_type;
+ assign T_532 = 1'h0 | T_528;
+ assign T_533 = T_532 | T_529;
+ assign T_534 = T_533 | T_530;
+ assign pending_outer_write = xact_is_builtin_type & T_534;
+ assign T_540_0 = 3'h2;
+ assign T_540_1 = 3'h3;
+ assign T_540_2 = 3'h4;
+ assign T_545 = T_540_0 == io_inner_acquire_bits_a_type;
+ assign T_546 = T_540_1 == io_inner_acquire_bits_a_type;
+ assign T_547 = T_540_2 == io_inner_acquire_bits_a_type;
+ assign T_549 = 1'h0 | T_545;
+ assign T_550 = T_549 | T_546;
+ assign T_551 = T_550 | T_547;
+ assign pending_outer_write_ = io_inner_acquire_bits_is_builtin_type & T_551;
+ assign T_556_0 = 3'h5;
+ assign T_556_1 = 3'h4;
+ assign T_560 = T_556_0 == io_inner_grant_bits_g_type;
+ assign T_561 = T_556_1 == io_inner_grant_bits_g_type;
+ assign T_563 = 1'h0 | T_560;
+ assign T_564 = T_563 | T_561;
+ assign T_566_0 = 1'h0;
+ assign T_566_1 = 1'h1;
+ assign T_570 = T_566_0 == io_inner_grant_bits_g_type;
+ assign T_571 = T_566_1 == io_inner_grant_bits_g_type;
+ assign T_573 = 1'h0 | T_570;
+ assign T_574 = T_573 | T_571;
+ assign pending_outer_read = io_inner_grant_bits_is_builtin_type ? T_564 : T_574;
+ assign T_594 = 3'h6 == io_inner_acquire_bits_a_type;
+ assign T_595 = T_594 ? 3'h1 : 3'h3;
+ assign T_596 = 3'h5 == io_inner_acquire_bits_a_type;
+ assign T_597 = T_596 ? 3'h1 : T_595;
+ assign T_598 = 3'h4 == io_inner_acquire_bits_a_type;
+ assign T_599 = T_598 ? 3'h4 : T_597;
+ assign T_600 = 3'h3 == io_inner_acquire_bits_a_type;
+ assign T_601 = T_600 ? 3'h3 : T_599;
+ assign T_602 = 3'h2 == io_inner_acquire_bits_a_type;
+ assign T_603 = T_602 ? 3'h3 : T_601;
+ assign T_604 = 3'h1 == io_inner_acquire_bits_a_type;
+ assign T_605 = T_604 ? 3'h5 : T_603;
+ assign T_606 = 3'h0 == io_inner_acquire_bits_a_type;
+ assign T_607 = T_606 ? 3'h4 : T_605;
+ assign T_608 = io_inner_acquire_bits_a_type == 1'h0;
+ assign T_611 = 1'h0 == 1'h0;
+ assign T_612 = T_611 ? 1'h0 : 1'h1;
+ assign T_613 = T_608 ? T_612 : 1'h1;
+ assign T_614 = io_inner_acquire_bits_is_builtin_type ? T_607 : T_613;
+ assign T_623_addr_beat = 1'h0;
+ assign T_623_client_xact_id = io_inner_acquire_bits_client_xact_id;
+ assign T_623_manager_xact_id = 2'h3;
+ assign T_623_is_builtin_type = io_inner_acquire_bits_is_builtin_type;
+ assign T_623_g_type = T_614;
+ assign T_623_data = 1'h0;
+ assign T_623_client_id = io_inner_acquire_bits_client_id;
+ assign T_634_0 = 3'h5;
+ assign T_634_1 = 3'h4;
+ assign T_638 = T_634_0 == T_623_g_type;
+ assign T_639 = T_634_1 == T_623_g_type;
+ assign T_641 = 1'h0 | T_638;
+ assign T_642 = T_641 | T_639;
+ assign T_644_0 = 1'h0;
+ assign T_644_1 = 1'h1;
+ assign T_648 = T_644_0 == T_623_g_type;
+ assign T_649 = T_644_1 == T_623_g_type;
+ assign T_651 = 1'h0 | T_648;
+ assign T_652 = T_651 | T_649;
+ assign pending_outer_read_ = T_623_is_builtin_type ? T_642 : T_652;
+ assign T_658_0 = 3'h2;
+ assign T_658_1 = 3'h0;
+ assign T_658_2 = 3'h4;
+ assign T_663 = T_658_0 == xact_a_type;
+ assign T_664 = T_658_1 == xact_a_type;
+ assign T_665 = T_658_2 == xact_a_type;
+ assign T_667 = 1'h0 | T_663;
+ assign T_668 = T_667 | T_664;
+ assign T_669 = T_668 | T_665;
+ assign subblock_type = xact_is_builtin_type & T_669;
+ assign T_671 = xact_addr_block == io_inner_acquire_bits_addr_block;
+ assign T_672 = state != 1'h0;
+ assign T_673 = T_671 & T_672;
+ assign T_675 = collect_iacq_data == 1'h0;
+ assign T_676 = T_673 & T_675;
+ assign T_677 = xact_addr_block == io_inner_acquire_bits_addr_block;
+ assign T_678 = T_677 & collect_iacq_data;
+ assign T_679 = xact_addr_block == io_inner_release_bits_addr_block;
+ assign T_681 = io_inner_release_bits_voluntary == 1'h0;
+ assign T_682 = T_679 & T_681;
+ assign T_683 = state == 1'h1;
+ assign T_684 = T_682 & T_683;
+ assign GEN_8 = $signed(16'hffff);
+ assign T_689 = $unsigned(GEN_8);
+ assign T_695 = {1'h0,3'h7};
+ assign T_696 = {1'h0,1'h1};
+ assign T_697 = {T_695,T_696};
+ assign T_699 = {1'h0,1'h1};
+ assign T_700 = {3'h7,T_699};
+ assign T_702 = {T_689,1'h1};
+ assign T_704 = {T_689,1'h1};
+ assign T_706 = {1'h0,3'h7};
+ assign T_707 = {1'h0,1'h1};
+ assign T_708 = {T_706,T_707};
+ assign T_710 = {5'h0,1'h1};
+ assign T_712 = {5'h1,1'h1};
+ assign T_713 = 3'h6 == 3'h3;
+ assign T_714 = T_713 ? T_712 : 1'h0;
+ assign T_715 = 3'h5 == 3'h3;
+ assign T_716 = T_715 ? T_710 : T_714;
+ assign T_717 = 3'h4 == 3'h3;
+ assign T_718 = T_717 ? T_708 : T_716;
+ assign T_719 = 3'h3 == 3'h3;
+ assign T_720 = T_719 ? T_704 : T_718;
+ assign T_721 = 3'h2 == 3'h3;
+ assign T_722 = T_721 ? T_702 : T_720;
+ assign T_723 = 3'h1 == 3'h3;
+ assign T_724 = T_723 ? T_700 : T_722;
+ assign T_725 = 3'h0 == 3'h3;
+ assign T_726 = T_725 ? T_697 : T_724;
+ assign oacq_probe_addr_block = io_inner_release_bits_addr_block;
+ assign oacq_probe_client_xact_id = 2'h3;
+ assign oacq_probe_addr_beat = io_inner_release_bits_addr_beat;
+ assign oacq_probe_is_builtin_type = 1'h1;
+ assign oacq_probe_a_type = 3'h3;
+ assign oacq_probe_union = T_726;
+ assign oacq_probe_data = io_inner_release_bits_data;
+ assign T_744 = xact_union[12:9];
+ assign T_745 = T_744[3];
+ assign T_747 = 1'h1 << T_745;
+ assign T_749 = xact_a_type == 3'h4;
+ assign T_750 = xact_is_builtin_type & T_749;
+ assign T_751 = T_747[0];
+ assign T_752 = T_747[1];
+ assign T_754_0 = T_751;
+ assign T_754_1 = T_752;
+ assign T_759 = 8'h0 - T_754_0;
+ assign T_760 = T_759[7:0];
+ assign T_762 = 8'h0 - T_754_1;
+ assign T_763 = T_762[7:0];
+ assign T_765_0 = T_760;
+ assign T_765_1 = T_763;
+ assign T_769 = {T_765_1,T_765_0};
+ assign T_771 = xact_a_type == 3'h3;
+ assign T_772 = xact_is_builtin_type & T_771;
+ assign T_774 = xact_a_type == 3'h2;
+ assign T_775 = xact_is_builtin_type & T_774;
+ assign T_776 = T_772 | T_775;
+ assign T_777 = xact_union[16:1];
+ assign T_779 = T_776 ? T_777 : 16'h0;
+ assign T_780 = T_750 ? T_769 : T_779;
+ assign T_788 = {1'h0,3'h7};
+ assign T_789 = {1'h0,1'h1};
+ assign T_790 = {T_788,T_789};
+ assign T_792 = {1'h0,1'h1};
+ assign T_793 = {3'h7,T_792};
+ assign T_795 = {T_780,1'h1};
+ assign T_797 = {T_780,1'h1};
+ assign T_799 = {1'h0,3'h7};
+ assign T_800 = {1'h0,1'h1};
+ assign T_801 = {T_799,T_800};
+ assign T_803 = {5'h0,1'h1};
+ assign T_805 = {5'h1,1'h1};
+ assign T_806 = 3'h6 == 3'h2;
+ assign T_807 = T_806 ? T_805 : 1'h0;
+ assign T_808 = 3'h5 == 3'h2;
+ assign T_809 = T_808 ? T_803 : T_807;
+ assign T_810 = 3'h4 == 3'h2;
+ assign T_811 = T_810 ? T_801 : T_809;
+ assign T_812 = 3'h3 == 3'h2;
+ assign T_813 = T_812 ? T_797 : T_811;
+ assign T_814 = 3'h2 == 3'h2;
+ assign T_815 = T_814 ? T_795 : T_813;
+ assign T_816 = 3'h1 == 3'h2;
+ assign T_817 = T_816 ? T_793 : T_815;
+ assign T_818 = 3'h0 == 3'h2;
+ assign T_819 = T_818 ? T_790 : T_817;
+ assign oacq_write_beat_addr_block = xact_addr_block;
+ assign oacq_write_beat_client_xact_id = 2'h3;
+ assign oacq_write_beat_addr_beat = xact_addr_beat;
+ assign oacq_write_beat_is_builtin_type = 1'h1;
+ assign oacq_write_beat_a_type = 3'h2;
+ assign oacq_write_beat_union = T_819;
+ assign oacq_write_beat_data = xact_data_buffer_0;
+ assign T_846 = {1'h0,3'h7};
+ assign T_847 = {1'h0,1'h1};
+ assign T_848 = {T_846,T_847};
+ assign T_850 = {1'h0,1'h1};
+ assign T_851 = {3'h7,T_850};
+ assign GEN_0 = GEN_45 ? xact_wmask_buffer_3 : GEN_46 ? xact_wmask_buffer_2 : GEN_47 ? xact_wmask_buffer_1 : xact_wmask_buffer_0;
+ assign T_853 = {GEN_0,1'h1};
+ assign GEN_1 = GEN_48 ? xact_wmask_buffer_3 : GEN_49 ? xact_wmask_buffer_2 : GEN_50 ? xact_wmask_buffer_1 : xact_wmask_buffer_0;
+ assign T_855 = {GEN_1,1'h1};
+ assign T_857 = {1'h0,3'h7};
+ assign T_858 = {1'h0,1'h1};
+ assign T_859 = {T_857,T_858};
+ assign T_861 = {5'h0,1'h1};
+ assign T_863 = {5'h1,1'h1};
+ assign T_864 = 3'h6 == 3'h3;
+ assign T_865 = T_864 ? T_863 : 1'h0;
+ assign T_866 = 3'h5 == 3'h3;
+ assign T_867 = T_866 ? T_861 : T_865;
+ assign T_868 = 3'h4 == 3'h3;
+ assign T_869 = T_868 ? T_859 : T_867;
+ assign T_870 = 3'h3 == 3'h3;
+ assign T_871 = T_870 ? T_855 : T_869;
+ assign T_872 = 3'h2 == 3'h3;
+ assign T_873 = T_872 ? T_853 : T_871;
+ assign T_874 = 3'h1 == 3'h3;
+ assign T_875 = T_874 ? T_851 : T_873;
+ assign T_876 = 3'h0 == 3'h3;
+ assign T_877 = T_876 ? T_848 : T_875;
+ assign oacq_write_block_addr_block = xact_addr_block;
+ assign oacq_write_block_client_xact_id = 2'h3;
+ assign oacq_write_block_addr_beat = oacq_data_cnt;
+ assign oacq_write_block_is_builtin_type = 1'h1;
+ assign oacq_write_block_a_type = 3'h3;
+ assign oacq_write_block_union = T_877;
+ assign oacq_write_block_data = GEN_2;
+ assign GEN_2 = GEN_51 ? xact_data_buffer_3 : GEN_52 ? xact_data_buffer_2 : GEN_53 ? xact_data_buffer_1 : xact_data_buffer_0;
+ assign T_895 = xact_union[12:9];
+ assign T_896 = xact_union[8:6];
+ assign T_904 = {T_895,T_896};
+ assign T_905 = {5'h0,1'h0};
+ assign T_906 = {T_904,T_905};
+ assign T_908 = {5'h0,1'h0};
+ assign T_909 = {T_896,T_908};
+ assign T_911 = {1'h0,1'h0};
+ assign T_913 = {1'h0,1'h0};
+ assign T_915 = {T_895,T_896};
+ assign T_916 = {5'h0,1'h0};
+ assign T_917 = {T_915,T_916};
+ assign T_919 = {5'h0,1'h0};
+ assign T_921 = {5'h1,1'h0};
+ assign T_922 = 3'h6 == 3'h0;
+ assign T_923 = T_922 ? T_921 : 1'h0;
+ assign T_924 = 3'h5 == 3'h0;
+ assign T_925 = T_924 ? T_919 : T_923;
+ assign T_926 = 3'h4 == 3'h0;
+ assign T_927 = T_926 ? T_917 : T_925;
+ assign T_928 = 3'h3 == 3'h0;
+ assign T_929 = T_928 ? T_913 : T_927;
+ assign T_930 = 3'h2 == 3'h0;
+ assign T_931 = T_930 ? T_911 : T_929;
+ assign T_932 = 3'h1 == 3'h0;
+ assign T_933 = T_932 ? T_909 : T_931;
+ assign T_934 = 3'h0 == 3'h0;
+ assign T_935 = T_934 ? T_906 : T_933;
+ assign oacq_read_beat_addr_block = xact_addr_block;
+ assign oacq_read_beat_client_xact_id = 2'h3;
+ assign oacq_read_beat_addr_beat = xact_addr_beat;
+ assign oacq_read_beat_is_builtin_type = 1'h1;
+ assign oacq_read_beat_a_type = 3'h0;
+ assign oacq_read_beat_union = T_935;
+ assign oacq_read_beat_data = 1'h0;
+ assign T_962 = {1'h0,3'h7};
+ assign T_963 = {5'h0,1'h1};
+ assign T_964 = {T_962,T_963};
+ assign T_966 = {5'h0,1'h1};
+ assign T_967 = {3'h7,T_966};
+ assign T_969 = {1'h0,1'h1};
+ assign T_971 = {1'h0,1'h1};
+ assign T_973 = {1'h0,3'h7};
+ assign T_974 = {5'h0,1'h1};
+ assign T_975 = {T_973,T_974};
+ assign T_977 = {5'h0,1'h1};
+ assign T_979 = {5'h1,1'h1};
+ assign T_980 = 3'h6 == 3'h1;
+ assign T_981 = T_980 ? T_979 : 1'h0;
+ assign T_982 = 3'h5 == 3'h1;
+ assign T_983 = T_982 ? T_977 : T_981;
+ assign T_984 = 3'h4 == 3'h1;
+ assign T_985 = T_984 ? T_975 : T_983;
+ assign T_986 = 3'h3 == 3'h1;
+ assign T_987 = T_986 ? T_971 : T_985;
+ assign T_988 = 3'h2 == 3'h1;
+ assign T_989 = T_988 ? T_969 : T_987;
+ assign T_990 = 3'h1 == 3'h1;
+ assign T_991 = T_990 ? T_967 : T_989;
+ assign T_992 = 3'h0 == 3'h1;
+ assign T_993 = T_992 ? T_964 : T_991;
+ assign oacq_read_block_addr_block = xact_addr_block;
+ assign oacq_read_block_client_xact_id = 2'h3;
+ assign oacq_read_block_addr_beat = 1'h0;
+ assign oacq_read_block_is_builtin_type = 1'h1;
+ assign oacq_read_block_a_type = 3'h1;
+ assign oacq_read_block_union = T_993;
+ assign oacq_read_block_data = 1'h0;
+ assign T_1011 = state == 1'h1;
+ assign T_1012 = state == 2'h3;
+ assign T_1013_addr_block = subblock_type ? oacq_write_beat_addr_block : oacq_write_block_addr_block;
+ assign T_1013_client_xact_id = subblock_type ? oacq_write_beat_client_xact_id : oacq_write_block_client_xact_id;
+ assign T_1013_addr_beat = subblock_type ? oacq_write_beat_addr_beat : oacq_write_block_addr_beat;
+ assign T_1013_is_builtin_type = subblock_type ? oacq_write_beat_is_builtin_type : oacq_write_block_is_builtin_type;
+ assign T_1013_a_type = subblock_type ? oacq_write_beat_a_type : oacq_write_block_a_type;
+ assign T_1013_union = subblock_type ? oacq_write_beat_union : oacq_write_block_union;
+ assign T_1013_data = subblock_type ? oacq_write_beat_data : oacq_write_block_data;
+ assign T_1021_addr_block = subblock_type ? oacq_read_beat_addr_block : oacq_read_block_addr_block;
+ assign T_1021_client_xact_id = subblock_type ? oacq_read_beat_client_xact_id : oacq_read_block_client_xact_id;
+ assign T_1021_addr_beat = subblock_type ? oacq_read_beat_addr_beat : oacq_read_block_addr_beat;
+ assign T_1021_is_builtin_type = subblock_type ? oacq_read_beat_is_builtin_type : oacq_read_block_is_builtin_type;
+ assign T_1021_a_type = subblock_type ? oacq_read_beat_a_type : oacq_read_block_a_type;
+ assign T_1021_union = subblock_type ? oacq_read_beat_union : oacq_read_block_union;
+ assign T_1021_data = subblock_type ? oacq_read_beat_data : oacq_read_block_data;
+ assign T_1029_addr_block = T_1012 ? T_1013_addr_block : T_1021_addr_block;
+ assign T_1029_client_xact_id = T_1012 ? T_1013_client_xact_id : T_1021_client_xact_id;
+ assign T_1029_addr_beat = T_1012 ? T_1013_addr_beat : T_1021_addr_beat;
+ assign T_1029_is_builtin_type = T_1012 ? T_1013_is_builtin_type : T_1021_is_builtin_type;
+ assign T_1029_a_type = T_1012 ? T_1013_a_type : T_1021_a_type;
+ assign T_1029_union = T_1012 ? T_1013_union : T_1021_union;
+ assign T_1029_data = T_1012 ? T_1013_data : T_1021_data;
+ assign T_1037_addr_block = T_1011 ? oacq_probe_addr_block : T_1029_addr_block;
+ assign T_1037_client_xact_id = T_1011 ? oacq_probe_client_xact_id : T_1029_client_xact_id;
+ assign T_1037_addr_beat = T_1011 ? oacq_probe_addr_beat : T_1029_addr_beat;
+ assign T_1037_is_builtin_type = T_1011 ? oacq_probe_is_builtin_type : T_1029_is_builtin_type;
+ assign T_1037_a_type = T_1011 ? oacq_probe_a_type : T_1029_a_type;
+ assign T_1037_union = T_1011 ? oacq_probe_union : T_1029_union;
+ assign T_1037_data = T_1011 ? oacq_probe_data : T_1029_data;
+ assign T_1054 = 3'h4 == xact_a_type;
+ assign T_1055 = T_1054 ? 1'h0 : 2'h2;
+ assign T_1056 = 3'h6 == xact_a_type;
+ assign T_1057 = T_1056 ? 1'h0 : T_1055;
+ assign T_1058 = 3'h5 == xact_a_type;
+ assign T_1059 = T_1058 ? 2'h2 : T_1057;
+ assign T_1060 = 3'h2 == xact_a_type;
+ assign T_1061 = T_1060 ? 1'h0 : T_1059;
+ assign T_1062 = 3'h0 == xact_a_type;
+ assign T_1063 = T_1062 ? 2'h2 : T_1061;
+ assign T_1064 = 3'h3 == xact_a_type;
+ assign T_1065 = T_1064 ? 1'h0 : T_1063;
+ assign T_1066 = 3'h1 == xact_a_type;
+ assign T_1067 = T_1066 ? 2'h2 : T_1065;
+ assign T_1068 = 1'h1 == xact_a_type;
+ assign T_1069 = T_1068 ? 1'h0 : 2'h2;
+ assign T_1070 = 1'h0 == xact_a_type;
+ assign T_1071 = T_1070 ? 1'h1 : T_1069;
+ assign T_1072 = xact_is_builtin_type ? T_1067 : T_1071;
+ assign T_1077_addr_block = xact_addr_block;
+ assign T_1077_p_type = T_1072;
+ assign T_1077_client_id = 1'h0;
+ assign T_1100 = 3'h6 == xact_a_type;
+ assign T_1101 = T_1100 ? 3'h1 : 3'h3;
+ assign T_1102 = 3'h5 == xact_a_type;
+ assign T_1103 = T_1102 ? 3'h1 : T_1101;
+ assign T_1104 = 3'h4 == xact_a_type;
+ assign T_1105 = T_1104 ? 3'h4 : T_1103;
+ assign T_1106 = 3'h3 == xact_a_type;
+ assign T_1107 = T_1106 ? 3'h3 : T_1105;
+ assign T_1108 = 3'h2 == xact_a_type;
+ assign T_1109 = T_1108 ? 3'h3 : T_1107;
+ assign T_1110 = 3'h1 == xact_a_type;
+ assign T_1111 = T_1110 ? 3'h5 : T_1109;
+ assign T_1112 = 3'h0 == xact_a_type;
+ assign T_1113 = T_1112 ? 3'h4 : T_1111;
+ assign T_1114 = xact_a_type == 1'h0;
+ assign T_1117 = 1'h0 == 1'h0;
+ assign T_1118 = T_1117 ? 1'h0 : 1'h1;
+ assign T_1119 = T_1114 ? T_1118 : 1'h1;
+ assign T_1120 = xact_is_builtin_type ? T_1113 : T_1119;
+ assign T_1129_addr_beat = 1'h0;
+ assign T_1129_client_xact_id = xact_client_xact_id;
+ assign T_1129_manager_xact_id = 2'h3;
+ assign T_1129_is_builtin_type = xact_is_builtin_type;
+ assign T_1129_g_type = T_1120;
+ assign T_1129_data = 1'h0;
+ assign T_1129_client_id = xact_client_id;
+ assign T_1140 = state != 1'h0;
+ assign T_1141 = T_1140 & collect_iacq_data;
+ assign T_1142 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_1143 = T_1141 & T_1142;
+ assign T_1144 = io_inner_acquire_bits_client_id != xact_client_id;
+ assign T_1145 = T_1143 & T_1144;
+ assign T_1147 = T_1145 == 1'h0;
+ assign T_1149 = reset == 1'h0;
+ assign T_1151 = T_1147 == 1'h0;
+ assign T_1153 = reset == 1'h0;
+ assign T_1154 = state != 1'h0;
+ assign T_1155 = T_1154 & collect_iacq_data;
+ assign T_1156 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_1157 = T_1155 & T_1156;
+ assign T_1158 = io_inner_acquire_bits_client_xact_id != xact_client_xact_id;
+ assign T_1159 = T_1157 & T_1158;
+ assign T_1161 = T_1159 == 1'h0;
+ assign T_1163 = reset == 1'h0;
+ assign T_1165 = T_1161 == 1'h0;
+ assign T_1167 = reset == 1'h0;
+ assign T_1168 = state == 1'h0;
+ assign T_1169 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_1170 = T_1168 & T_1169;
+ assign T_1172 = 1'h1 & io_inner_acquire_bits_is_builtin_type;
+ assign T_1175_0 = 3'h3;
+ assign T_1178 = T_1175_0 == io_inner_acquire_bits_a_type;
+ assign T_1180 = 1'h0 | T_1178;
+ assign T_1181 = T_1172 & T_1180;
+ assign T_1182 = T_1170 & T_1181;
+ assign T_1184 = io_inner_acquire_bits_addr_beat != 1'h0;
+ assign T_1185 = T_1182 & T_1184;
+ assign T_1187 = T_1185 == 1'h0;
+ assign T_1189 = reset == 1'h0;
+ assign T_1191 = T_1187 == 1'h0;
+ assign T_1193 = reset == 1'h0;
+ assign GEN_3 = io_inner_acquire_bits_data;
+ assign T_1197 = io_inner_acquire_bits_union[12:9];
+ assign T_1198 = T_1197[3];
+ assign T_1200 = 1'h1 << T_1198;
+ assign T_1202 = io_inner_acquire_bits_a_type == 3'h4;
+ assign T_1203 = io_inner_acquire_bits_is_builtin_type & T_1202;
+ assign T_1204 = T_1200[0];
+ assign T_1205 = T_1200[1];
+ assign T_1207_0 = T_1204;
+ assign T_1207_1 = T_1205;
+ assign T_1212 = 8'h0 - T_1207_0;
+ assign T_1213 = T_1212[7:0];
+ assign T_1215 = 8'h0 - T_1207_1;
+ assign T_1216 = T_1215[7:0];
+ assign T_1218_0 = T_1213;
+ assign T_1218_1 = T_1216;
+ assign T_1222 = {T_1218_1,T_1218_0};
+ assign T_1224 = io_inner_acquire_bits_a_type == 3'h3;
+ assign T_1225 = io_inner_acquire_bits_is_builtin_type & T_1224;
+ assign T_1227 = io_inner_acquire_bits_a_type == 3'h2;
+ assign T_1228 = io_inner_acquire_bits_is_builtin_type & T_1227;
+ assign T_1229 = T_1225 | T_1228;
+ assign T_1230 = io_inner_acquire_bits_union[16:1];
+ assign T_1232 = T_1229 ? T_1230 : 16'h0;
+ assign T_1233 = T_1203 ? T_1222 : T_1232;
+ assign GEN_4 = T_1233;
+ assign T_1236 = 1'h1 << io_inner_acquire_bits_addr_beat;
+ assign T_1237 = iacq_data_valid | T_1236;
+ assign T_1238 = ~ iacq_data_valid;
+ assign T_1239 = T_1238 | T_1236;
+ assign T_1240 = ~ T_1239;
+ assign T_1241 = 1'h1 ? T_1237 : T_1240;
+ assign T_1245 = 1'h0 == state;
+ assign GEN_5 = io_inner_acquire_bits_data;
+ assign T_1251 = io_inner_acquire_bits_union[12:9];
+ assign T_1252 = T_1251[3];
+ assign T_1254 = 1'h1 << T_1252;
+ assign T_1256 = io_inner_acquire_bits_a_type == 3'h4;
+ assign T_1257 = io_inner_acquire_bits_is_builtin_type & T_1256;
+ assign T_1258 = T_1254[0];
+ assign T_1259 = T_1254[1];
+ assign T_1261_0 = T_1258;
+ assign T_1261_1 = T_1259;
+ assign T_1266 = 8'h0 - T_1261_0;
+ assign T_1267 = T_1266[7:0];
+ assign T_1269 = 8'h0 - T_1261_1;
+ assign T_1270 = T_1269[7:0];
+ assign T_1272_0 = T_1267;
+ assign T_1272_1 = T_1270;
+ assign T_1276 = {T_1272_1,T_1272_0};
+ assign T_1278 = io_inner_acquire_bits_a_type == 3'h3;
+ assign T_1279 = io_inner_acquire_bits_is_builtin_type & T_1278;
+ assign T_1281 = io_inner_acquire_bits_a_type == 3'h2;
+ assign T_1282 = io_inner_acquire_bits_is_builtin_type & T_1281;
+ assign T_1283 = T_1279 | T_1282;
+ assign T_1284 = io_inner_acquire_bits_union[16:1];
+ assign T_1286 = T_1283 ? T_1284 : 16'h0;
+ assign T_1287 = T_1257 ? T_1276 : T_1286;
+ assign GEN_6 = T_1287;
+ assign T_1289 = 1'h1 & io_inner_acquire_bits_is_builtin_type;
+ assign T_1292_0 = 3'h3;
+ assign T_1295 = T_1292_0 == io_inner_acquire_bits_a_type;
+ assign T_1297 = 1'h0 | T_1295;
+ assign T_1298 = T_1289 & T_1297;
+ assign T_1303_0 = 3'h2;
+ assign T_1303_1 = 3'h3;
+ assign T_1303_2 = 3'h4;
+ assign T_1308 = T_1303_0 == io_inner_acquire_bits_a_type;
+ assign T_1309 = T_1303_1 == io_inner_acquire_bits_a_type;
+ assign T_1310 = T_1303_2 == io_inner_acquire_bits_a_type;
+ assign T_1312 = 1'h0 | T_1308;
+ assign T_1313 = T_1312 | T_1309;
+ assign T_1314 = T_1313 | T_1310;
+ assign T_1315 = io_inner_acquire_bits_is_builtin_type & T_1314;
+ assign T_1316 = T_1315 << io_inner_acquire_bits_addr_beat;
+ assign T_1318 = mask_incoherent != 1'h0;
+ assign T_1319 = mask_incoherent[0];
+ assign T_1320 = mask_incoherent[1];
+ assign T_1321 = mask_incoherent[2];
+ assign T_1322 = mask_incoherent[3];
+ assign T_1324 = {1'h0,T_1320};
+ assign T_1325 = T_1319 + T_1324;
+ assign T_1326 = T_1325[1:0];
+ assign T_1329 = {1'h0,T_1322};
+ assign T_1330 = T_1321 + T_1329;
+ assign T_1331 = T_1330[1:0];
+ assign T_1332 = {1'h0,T_1331};
+ assign T_1333 = T_1326 + T_1332;
+ assign T_1334 = T_1333[2:0];
+ assign T_1335 = pending_outer_read_ ? 2'h2 : 3'h4;
+ assign T_1336 = pending_outer_write_ ? 2'h3 : T_1335;
+ assign T_1337 = T_1318 ? 1'h1 : T_1336;
+ assign T_1338 = 1'h1 == state;
+ assign T_1340 = pending_probes != 1'h0;
+ assign T_1342 = 1'h1 << 1'h0;
+ assign T_1343 = ~ T_1342;
+ assign T_1344 = pending_probes & T_1343;
+ assign T_1346_0 = 1'h0;
+ assign T_1346_1 = 1'h1;
+ assign T_1346_2 = 2'h2;
+ assign T_1351 = T_1346_0 == io_inner_release_bits_r_type;
+ assign T_1352 = T_1346_1 == io_inner_release_bits_r_type;
+ assign T_1353 = T_1346_2 == io_inner_release_bits_r_type;
+ assign T_1355 = 1'h0 | T_1351;
+ assign T_1356 = T_1355 | T_1352;
+ assign T_1357 = T_1356 | T_1353;
+ assign T_1359 = T_1357 == 1'h0;
+ assign T_1360 = T_1359 | io_outer_acquire_ready;
+ assign T_1362_0 = 1'h0;
+ assign T_1362_1 = 1'h1;
+ assign T_1362_2 = 2'h2;
+ assign T_1367 = T_1362_0 == io_inner_release_bits_r_type;
+ assign T_1368 = T_1362_1 == io_inner_release_bits_r_type;
+ assign T_1369 = T_1362_2 == io_inner_release_bits_r_type;
+ assign T_1371 = 1'h0 | T_1367;
+ assign T_1372 = T_1371 | T_1368;
+ assign T_1373 = T_1372 | T_1369;
+ assign T_1377 = release_count - 1'h1;
+ assign T_1378 = T_1377[0:0];
+ assign T_1380 = release_count == 1'h1;
+ assign T_1381 = pending_outer_read ? 2'h2 : 3'h4;
+ assign T_1382 = pending_outer_write ? 2'h3 : T_1381;
+ assign T_1384 = T_1373 == 1'h0;
+ assign T_1386 = release_count - 1'h1;
+ assign T_1387 = T_1386[0:0];
+ assign T_1389 = release_count == 1'h1;
+ assign T_1390 = pending_outer_read ? 2'h2 : 3'h4;
+ assign T_1391 = pending_outer_write ? 2'h3 : T_1390;
+ assign T_1392 = 2'h3 == state;
+ assign T_1394 = pending_ognt_ack == 1'h0;
+ assign T_1396 = collect_iacq_data == 1'h0;
+ assign T_1397 = iacq_data_valid >> oacq_data_cnt;
+ assign T_1398 = T_1397[0];
+ assign T_1399 = T_1396 | T_1398;
+ assign T_1400 = T_1394 & T_1399;
+ assign T_1402 = pending_outer_read ? 2'h2 : 3'h5;
+ assign T_1403 = 2'h2 == state;
+ assign T_1405 = pending_ognt_ack == 1'h0;
+ assign T_1406 = io_outer_acquire_ready & io_outer_acquire_valid;
+ assign T_1407 = 3'h5 == state;
+ assign T_1410 = 1'h0 == 1'h0;
+ assign T_1412 = io_inner_grant_bits_g_type == 3'h0;
+ assign T_1413 = io_inner_grant_bits_is_builtin_type & T_1412;
+ assign T_1415 = T_1413 == 1'h0;
+ assign T_1416 = T_1410 & T_1415;
+ assign T_1417 = T_1416 ? 3'h6 : 1'h0;
+ assign T_1418 = 3'h4 == state;
+ assign T_1422 = 1'h0 == 1'h0;
+ assign T_1424 = io_inner_grant_bits_g_type == 3'h0;
+ assign T_1425 = io_inner_grant_bits_is_builtin_type & T_1424;
+ assign T_1427 = T_1425 == 1'h0;
+ assign T_1428 = T_1422 & T_1427;
+ assign T_1429 = T_1428 ? 3'h6 : 1'h0;
+ assign T_1430 = 3'h6 == state;
+ assign GEN_9 = T_325 & T_327;
+ assign GEN_10 = T_1149 & T_1151;
+ assign GEN_11 = T_1163 & T_1165;
+ assign GEN_12 = T_1189 & T_1191;
+ assign GEN_13 = 1'h0 == 1'h0;
+ assign GEN_14 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_15 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_16 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_17 = 1'h1 == 1'h0;
+ assign GEN_18 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_19 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_20 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_21 = 2'h2 == 1'h0;
+ assign GEN_22 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_23 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_24 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_25 = 2'h3 == 1'h0;
+ assign GEN_26 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_27 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_28 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_29 = 1'h0 == 1'h0;
+ assign GEN_30 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_31 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_32 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_33 = 1'h1 == 1'h0;
+ assign GEN_34 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_35 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_36 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_37 = 2'h2 == 1'h0;
+ assign GEN_38 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_39 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_40 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_41 = 2'h3 == 1'h0;
+ assign GEN_42 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_43 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_44 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_45 = 2'h3 == oacq_data_cnt;
+ assign GEN_46 = 2'h2 == oacq_data_cnt;
+ assign GEN_47 = 1'h1 == oacq_data_cnt;
+ assign GEN_48 = 2'h3 == oacq_data_cnt;
+ assign GEN_49 = 2'h2 == oacq_data_cnt;
+ assign GEN_50 = 1'h1 == oacq_data_cnt;
+ assign GEN_51 = 2'h3 == oacq_data_cnt;
+ assign GEN_52 = 2'h2 == oacq_data_cnt;
+ assign GEN_53 = 1'h1 == oacq_data_cnt;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ state = {1{$random}};
+ xact_addr_block = {1{$random}};
+ xact_client_xact_id = {1{$random}};
+ xact_addr_beat = {1{$random}};
+ xact_is_builtin_type = {1{$random}};
+ xact_a_type = {1{$random}};
+ xact_union = {1{$random}};
+ xact_data_buffer_0 = {1{$random}};
+ xact_data_buffer_1 = {1{$random}};
+ xact_data_buffer_2 = {1{$random}};
+ xact_data_buffer_3 = {1{$random}};
+ xact_wmask_buffer_0 = {1{$random}};
+ xact_wmask_buffer_1 = {1{$random}};
+ xact_wmask_buffer_2 = {1{$random}};
+ xact_wmask_buffer_3 = {1{$random}};
+ xact_client_id = {1{$random}};
+ release_count = {1{$random}};
+ pending_probes = {1{$random}};
+ collect_iacq_data = {1{$random}};
+ iacq_data_valid = {1{$random}};
+ T_371 = {1{$random}};
+ T_403 = {1{$random}};
+ T_441 = {1{$random}};
+ T_469 = {1{$random}};
+ T_504 = {1{$random}};
+ pending_ognt_ack = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1430) begin
+ if(io_inner_finish_valid) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1418) begin
+ if(io_inner_grant_ready) begin
+ state <= T_1429;
+ end else begin
+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
+ end else begin
+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end
+ end else begin
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+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end else begin
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+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
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+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
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+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
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+ end
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+ end
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+ state <= T_1402;
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ end else begin
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
+ end else begin
+ ;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ end else begin
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end
+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1418) begin
+ if(io_inner_grant_ready) begin
+ state <= T_1429;
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+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
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+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
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+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end
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+ end
+ end else begin
+ if(T_1392) begin
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+ state <= T_1402;
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ if(T_1380) begin
+ state <= T_1382;
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ end
+ end else begin
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
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+ end
+ end else begin
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+ if(T_1406) begin
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ state <= T_1337;
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+ end
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ state <= T_1337;
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+ end
+ end else begin
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
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+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
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+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1382;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_addr_block <= io_inner_acquire_bits_addr_block;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_client_xact_id <= io_inner_acquire_bits_client_xact_id;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_addr_beat <= io_inner_acquire_bits_addr_beat;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_is_builtin_type <= io_inner_acquire_bits_is_builtin_type;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_a_type <= io_inner_acquire_bits_a_type;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_union <= io_inner_acquire_bits_union;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_13) begin
+ xact_data_buffer_0 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_14) begin
+ xact_data_buffer_0 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_15) begin
+ xact_data_buffer_0 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_16) begin
+ xact_data_buffer_0 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_17) begin
+ xact_data_buffer_1 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_18) begin
+ xact_data_buffer_1 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_19) begin
+ xact_data_buffer_1 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_20) begin
+ xact_data_buffer_1 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_21) begin
+ xact_data_buffer_2 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_22) begin
+ xact_data_buffer_2 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_23) begin
+ xact_data_buffer_2 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_24) begin
+ xact_data_buffer_2 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_25) begin
+ xact_data_buffer_3 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_26) begin
+ xact_data_buffer_3 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_27) begin
+ xact_data_buffer_3 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_28) begin
+ xact_data_buffer_3 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_29) begin
+ xact_wmask_buffer_0 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_30) begin
+ xact_wmask_buffer_0 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_31) begin
+ xact_wmask_buffer_0 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_32) begin
+ xact_wmask_buffer_0 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_33) begin
+ xact_wmask_buffer_1 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_34) begin
+ xact_wmask_buffer_1 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_35) begin
+ xact_wmask_buffer_1 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_36) begin
+ xact_wmask_buffer_1 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_37) begin
+ xact_wmask_buffer_2 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_38) begin
+ xact_wmask_buffer_2 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_39) begin
+ xact_wmask_buffer_2 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_40) begin
+ xact_wmask_buffer_2 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_41) begin
+ xact_wmask_buffer_3 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_42) begin
+ xact_wmask_buffer_3 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_43) begin
+ xact_wmask_buffer_3 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_44) begin
+ xact_wmask_buffer_3 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_client_id <= io_inner_acquire_bits_client_id;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ release_count <= 1'h0;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ release_count <= T_1387;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ release_count <= T_1378;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ pending_probes <= 1'h0;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_probe_ready) begin
+ pending_probes <= T_1344;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ pending_probes <= mask_incoherent;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ pending_probes <= mask_incoherent;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ collect_iacq_data <= 1'h0;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ collect_iacq_data <= T_1298;
+ end else begin
+ if(collect_iacq_data) begin
+ if(iacq_data_done) begin
+ collect_iacq_data <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(iacq_data_done) begin
+ collect_iacq_data <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ iacq_data_valid <= 4'h0;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ iacq_data_valid <= T_1316;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ iacq_data_valid <= T_1241;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ iacq_data_valid <= T_1241;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ T_371 <= 2'h0;
+ end else begin
+ if(T_369) begin
+ T_371 <= T_380;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_403 <= 2'h0;
+ end else begin
+ if(T_401) begin
+ T_403 <= T_412;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_441 <= 2'h0;
+ end else begin
+ if(T_439) begin
+ T_441 <= T_450;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_469 <= 2'h0;
+ end else begin
+ if(T_467) begin
+ T_469 <= T_478;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_504 <= 2'h0;
+ end else begin
+ if(T_502) begin
+ T_504 <= T_513;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ pending_ognt_ack <= 1'h1;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ pending_ognt_ack <= 1'h1;
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ pending_ognt_ack <= 1'h1;
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ `ifndef SYNTHESIS
+ if(GEN_9 & T_329) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_325 & T_327) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_10 & T_1153) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_1149 & T_1151) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_11 & T_1167) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_1163 & T_1165) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_12 & T_1193) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_1189 & T_1191) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ end
+endmodule
+module BroadcastAcquireTracker_29(
+ input clk,
+ input reset,
+ output io_inner_acquire_ready,
+ input io_inner_acquire_valid,
+ input [25:0] io_inner_acquire_bits_addr_block,
+ input [1:0] io_inner_acquire_bits_client_xact_id,
+ input [1:0] io_inner_acquire_bits_addr_beat,
+ input io_inner_acquire_bits_is_builtin_type,
+ input [2:0] io_inner_acquire_bits_a_type,
+ input [16:0] io_inner_acquire_bits_union,
+ input [3:0] io_inner_acquire_bits_data,
+ input [1:0] io_inner_acquire_bits_client_id,
+ input io_inner_grant_ready,
+ output io_inner_grant_valid,
+ output [1:0] io_inner_grant_bits_addr_beat,
+ output [1:0] io_inner_grant_bits_client_xact_id,
+ output [3:0] io_inner_grant_bits_manager_xact_id,
+ output io_inner_grant_bits_is_builtin_type,
+ output [3:0] io_inner_grant_bits_g_type,
+ output [3:0] io_inner_grant_bits_data,
+ output [1:0] io_inner_grant_bits_client_id,
+ output io_inner_finish_ready,
+ input io_inner_finish_valid,
+ input [3:0] io_inner_finish_bits_manager_xact_id,
+ input io_inner_probe_ready,
+ output io_inner_probe_valid,
+ output [25:0] io_inner_probe_bits_addr_block,
+ output [1:0] io_inner_probe_bits_p_type,
+ output [1:0] io_inner_probe_bits_client_id,
+ output io_inner_release_ready,
+ input io_inner_release_valid,
+ input [1:0] io_inner_release_bits_addr_beat,
+ input [25:0] io_inner_release_bits_addr_block,
+ input [1:0] io_inner_release_bits_client_xact_id,
+ input io_inner_release_bits_voluntary,
+ input [2:0] io_inner_release_bits_r_type,
+ input [3:0] io_inner_release_bits_data,
+ input [1:0] io_inner_release_bits_client_id,
+ input io_incoherent_0,
+ input io_outer_acquire_ready,
+ output io_outer_acquire_valid,
+ output [25:0] io_outer_acquire_bits_addr_block,
+ output [3:0] io_outer_acquire_bits_client_xact_id,
+ output [1:0] io_outer_acquire_bits_addr_beat,
+ output io_outer_acquire_bits_is_builtin_type,
+ output [2:0] io_outer_acquire_bits_a_type,
+ output [16:0] io_outer_acquire_bits_union,
+ output [3:0] io_outer_acquire_bits_data,
+ output io_outer_grant_ready,
+ input io_outer_grant_valid,
+ input [1:0] io_outer_grant_bits_addr_beat,
+ input [3:0] io_outer_grant_bits_client_xact_id,
+ input io_outer_grant_bits_manager_xact_id,
+ input io_outer_grant_bits_is_builtin_type,
+ input [3:0] io_outer_grant_bits_g_type,
+ input [3:0] io_outer_grant_bits_data,
+ output io_has_acquire_conflict,
+ output io_has_acquire_match,
+ output io_has_release_match
+);
+ reg [2:0] state;
+ reg [25:0] xact_addr_block;
+ reg [1:0] xact_client_xact_id;
+ reg [1:0] xact_addr_beat;
+ reg xact_is_builtin_type;
+ reg [2:0] xact_a_type;
+ reg [16:0] xact_union;
+ reg [3:0] xact_data_buffer_0;
+ reg [3:0] xact_data_buffer_1;
+ reg [3:0] xact_data_buffer_2;
+ reg [3:0] xact_data_buffer_3;
+ reg [15:0] xact_wmask_buffer_0;
+ reg [15:0] xact_wmask_buffer_1;
+ reg [15:0] xact_wmask_buffer_2;
+ reg [15:0] xact_wmask_buffer_3;
+ reg [1:0] xact_client_id;
+ wire coh_sharers;
+ wire T_303;
+ wire T_304;
+ wire [2:0] T_309_0;
+ wire [2:0] T_309_1;
+ wire [2:0] T_309_2;
+ wire T_314;
+ wire T_315;
+ wire T_316;
+ wire T_318;
+ wire T_319;
+ wire T_320;
+ wire T_321;
+ wire T_323;
+ wire T_325;
+ wire T_327;
+ wire T_329;
+ reg release_count;
+ reg pending_probes;
+ wire T_334;
+ wire T_336_0;
+ wire GEN_7;
+ wire T_341;
+ wire [3:0] T_344;
+ wire [3:0] T_345;
+ wire T_346;
+ wire [3:0] T_347;
+ wire [3:0] T_348;
+ wire [3:0] mask_self;
+ wire T_350;
+ wire [3:0] mask_incoherent;
+ reg collect_iacq_data;
+ reg [3:0] iacq_data_valid;
+ wire T_356;
+ wire T_359;
+ wire [2:0] T_362_0;
+ wire T_365;
+ wire T_367;
+ wire T_368;
+ wire T_369;
+ reg [1:0] T_371;
+ wire T_373;
+ wire T_375;
+ wire [2:0] T_378;
+ wire [1:0] T_379;
+ wire [1:0] T_380;
+ wire T_381;
+ wire [1:0] T_382;
+ wire iacq_data_done;
+ wire T_384;
+ wire [1:0] T_388_0;
+ wire [1:0] T_388_1;
+ wire [1:0] T_388_2;
+ wire T_393;
+ wire T_394;
+ wire T_395;
+ wire T_397;
+ wire T_398;
+ wire T_399;
+ wire T_400;
+ wire T_401;
+ reg [1:0] T_403;
+ wire T_405;
+ wire T_407;
+ wire [2:0] T_410;
+ wire [1:0] T_411;
+ wire [1:0] T_412;
+ wire T_413;
+ wire [1:0] T_414;
+ wire irel_data_done;
+ wire T_417;
+ wire [2:0] T_421_0;
+ wire T_424;
+ wire T_426;
+ wire T_428_0;
+ wire T_428_1;
+ wire T_432;
+ wire T_433;
+ wire T_435;
+ wire T_436;
+ wire T_437;
+ wire T_438;
+ wire T_439;
+ reg [1:0] T_441;
+ wire T_443;
+ wire T_445;
+ wire [2:0] T_448;
+ wire [1:0] T_449;
+ wire [1:0] T_450;
+ wire T_451;
+ wire [1:0] ignt_data_cnt;
+ wire ignt_data_done;
+ wire T_455;
+ wire T_457;
+ wire [2:0] T_460_0;
+ wire T_463;
+ wire T_465;
+ wire T_466;
+ wire T_467;
+ reg [1:0] T_469;
+ wire T_471;
+ wire T_473;
+ wire [2:0] T_476;
+ wire [1:0] T_477;
+ wire [1:0] T_478;
+ wire T_479;
+ wire [1:0] oacq_data_cnt;
+ wire oacq_data_done;
+ wire T_482;
+ wire [2:0] T_487_0;
+ wire T_490;
+ wire T_492;
+ wire T_494_0;
+ wire T_497;
+ wire T_499;
+ wire T_500;
+ wire T_501;
+ wire T_502;
+ reg [1:0] T_504;
+ wire T_506;
+ wire T_508;
+ wire [2:0] T_511;
+ wire [1:0] T_512;
+ wire [1:0] T_513;
+ wire T_514;
+ wire [1:0] T_515;
+ wire ognt_data_done;
+ reg pending_ognt_ack;
+ wire [2:0] T_523_0;
+ wire [2:0] T_523_1;
+ wire [2:0] T_523_2;
+ wire T_528;
+ wire T_529;
+ wire T_530;
+ wire T_532;
+ wire T_533;
+ wire T_534;
+ wire pending_outer_write;
+ wire [2:0] T_540_0;
+ wire [2:0] T_540_1;
+ wire [2:0] T_540_2;
+ wire T_545;
+ wire T_546;
+ wire T_547;
+ wire T_549;
+ wire T_550;
+ wire T_551;
+ wire pending_outer_write_;
+ wire [2:0] T_556_0;
+ wire [2:0] T_556_1;
+ wire T_560;
+ wire T_561;
+ wire T_563;
+ wire T_564;
+ wire T_566_0;
+ wire T_566_1;
+ wire T_570;
+ wire T_571;
+ wire T_573;
+ wire T_574;
+ wire pending_outer_read;
+ wire T_594;
+ wire [2:0] T_595;
+ wire T_596;
+ wire [2:0] T_597;
+ wire T_598;
+ wire [2:0] T_599;
+ wire T_600;
+ wire [2:0] T_601;
+ wire T_602;
+ wire [2:0] T_603;
+ wire T_604;
+ wire [2:0] T_605;
+ wire T_606;
+ wire [2:0] T_607;
+ wire T_608;
+ wire T_611;
+ wire T_612;
+ wire T_613;
+ wire [2:0] T_614;
+ wire [1:0] T_623_addr_beat;
+ wire [1:0] T_623_client_xact_id;
+ wire [3:0] T_623_manager_xact_id;
+ wire T_623_is_builtin_type;
+ wire [3:0] T_623_g_type;
+ wire [3:0] T_623_data;
+ wire [1:0] T_623_client_id;
+ wire [2:0] T_634_0;
+ wire [2:0] T_634_1;
+ wire T_638;
+ wire T_639;
+ wire T_641;
+ wire T_642;
+ wire T_644_0;
+ wire T_644_1;
+ wire T_648;
+ wire T_649;
+ wire T_651;
+ wire T_652;
+ wire pending_outer_read_;
+ wire [2:0] T_658_0;
+ wire [2:0] T_658_1;
+ wire [2:0] T_658_2;
+ wire T_663;
+ wire T_664;
+ wire T_665;
+ wire T_667;
+ wire T_668;
+ wire T_669;
+ wire subblock_type;
+ wire T_671;
+ wire T_672;
+ wire T_673;
+ wire T_675;
+ wire T_676;
+ wire T_677;
+ wire T_678;
+ wire T_679;
+ wire T_681;
+ wire T_682;
+ wire T_683;
+ wire T_684;
+ wire [15:0] GEN_8;
+ wire [15:0] T_689;
+ wire [3:0] T_695;
+ wire [1:0] T_696;
+ wire [5:0] T_697;
+ wire [1:0] T_699;
+ wire [4:0] T_700;
+ wire [16:0] T_702;
+ wire [16:0] T_704;
+ wire [3:0] T_706;
+ wire [1:0] T_707;
+ wire [5:0] T_708;
+ wire [5:0] T_710;
+ wire [5:0] T_712;
+ wire T_713;
+ wire [5:0] T_714;
+ wire T_715;
+ wire [5:0] T_716;
+ wire T_717;
+ wire [5:0] T_718;
+ wire T_719;
+ wire [16:0] T_720;
+ wire T_721;
+ wire [16:0] T_722;
+ wire T_723;
+ wire [16:0] T_724;
+ wire T_725;
+ wire [16:0] T_726;
+ wire [25:0] oacq_probe_addr_block;
+ wire [3:0] oacq_probe_client_xact_id;
+ wire [1:0] oacq_probe_addr_beat;
+ wire oacq_probe_is_builtin_type;
+ wire [2:0] oacq_probe_a_type;
+ wire [16:0] oacq_probe_union;
+ wire [3:0] oacq_probe_data;
+ wire [3:0] T_744;
+ wire T_745;
+ wire [1:0] T_747;
+ wire T_749;
+ wire T_750;
+ wire T_751;
+ wire T_752;
+ wire T_754_0;
+ wire T_754_1;
+ wire [8:0] T_759;
+ wire [7:0] T_760;
+ wire [8:0] T_762;
+ wire [7:0] T_763;
+ wire [7:0] T_765_0;
+ wire [7:0] T_765_1;
+ wire [15:0] T_769;
+ wire T_771;
+ wire T_772;
+ wire T_774;
+ wire T_775;
+ wire T_776;
+ wire [15:0] T_777;
+ wire [15:0] T_779;
+ wire [15:0] T_780;
+ wire [3:0] T_788;
+ wire [1:0] T_789;
+ wire [5:0] T_790;
+ wire [1:0] T_792;
+ wire [4:0] T_793;
+ wire [16:0] T_795;
+ wire [16:0] T_797;
+ wire [3:0] T_799;
+ wire [1:0] T_800;
+ wire [5:0] T_801;
+ wire [5:0] T_803;
+ wire [5:0] T_805;
+ wire T_806;
+ wire [5:0] T_807;
+ wire T_808;
+ wire [5:0] T_809;
+ wire T_810;
+ wire [5:0] T_811;
+ wire T_812;
+ wire [16:0] T_813;
+ wire T_814;
+ wire [16:0] T_815;
+ wire T_816;
+ wire [16:0] T_817;
+ wire T_818;
+ wire [16:0] T_819;
+ wire [25:0] oacq_write_beat_addr_block;
+ wire [3:0] oacq_write_beat_client_xact_id;
+ wire [1:0] oacq_write_beat_addr_beat;
+ wire oacq_write_beat_is_builtin_type;
+ wire [2:0] oacq_write_beat_a_type;
+ wire [16:0] oacq_write_beat_union;
+ wire [3:0] oacq_write_beat_data;
+ wire [3:0] T_846;
+ wire [1:0] T_847;
+ wire [5:0] T_848;
+ wire [1:0] T_850;
+ wire [4:0] T_851;
+ wire [15:0] GEN_0;
+ wire [16:0] T_853;
+ wire [15:0] GEN_1;
+ wire [16:0] T_855;
+ wire [3:0] T_857;
+ wire [1:0] T_858;
+ wire [5:0] T_859;
+ wire [5:0] T_861;
+ wire [5:0] T_863;
+ wire T_864;
+ wire [5:0] T_865;
+ wire T_866;
+ wire [5:0] T_867;
+ wire T_868;
+ wire [5:0] T_869;
+ wire T_870;
+ wire [16:0] T_871;
+ wire T_872;
+ wire [16:0] T_873;
+ wire T_874;
+ wire [16:0] T_875;
+ wire T_876;
+ wire [16:0] T_877;
+ wire [25:0] oacq_write_block_addr_block;
+ wire [3:0] oacq_write_block_client_xact_id;
+ wire [1:0] oacq_write_block_addr_beat;
+ wire oacq_write_block_is_builtin_type;
+ wire [2:0] oacq_write_block_a_type;
+ wire [16:0] oacq_write_block_union;
+ wire [3:0] oacq_write_block_data;
+ wire [3:0] GEN_2;
+ wire [3:0] T_895;
+ wire [2:0] T_896;
+ wire [6:0] T_904;
+ wire [5:0] T_905;
+ wire [12:0] T_906;
+ wire [5:0] T_908;
+ wire [8:0] T_909;
+ wire [1:0] T_911;
+ wire [1:0] T_913;
+ wire [6:0] T_915;
+ wire [5:0] T_916;
+ wire [12:0] T_917;
+ wire [5:0] T_919;
+ wire [5:0] T_921;
+ wire T_922;
+ wire [5:0] T_923;
+ wire T_924;
+ wire [5:0] T_925;
+ wire T_926;
+ wire [12:0] T_927;
+ wire T_928;
+ wire [12:0] T_929;
+ wire T_930;
+ wire [12:0] T_931;
+ wire T_932;
+ wire [12:0] T_933;
+ wire T_934;
+ wire [12:0] T_935;
+ wire [25:0] oacq_read_beat_addr_block;
+ wire [3:0] oacq_read_beat_client_xact_id;
+ wire [1:0] oacq_read_beat_addr_beat;
+ wire oacq_read_beat_is_builtin_type;
+ wire [2:0] oacq_read_beat_a_type;
+ wire [16:0] oacq_read_beat_union;
+ wire [3:0] oacq_read_beat_data;
+ wire [3:0] T_962;
+ wire [5:0] T_963;
+ wire [9:0] T_964;
+ wire [5:0] T_966;
+ wire [8:0] T_967;
+ wire [1:0] T_969;
+ wire [1:0] T_971;
+ wire [3:0] T_973;
+ wire [5:0] T_974;
+ wire [9:0] T_975;
+ wire [5:0] T_977;
+ wire [5:0] T_979;
+ wire T_980;
+ wire [5:0] T_981;
+ wire T_982;
+ wire [5:0] T_983;
+ wire T_984;
+ wire [9:0] T_985;
+ wire T_986;
+ wire [9:0] T_987;
+ wire T_988;
+ wire [9:0] T_989;
+ wire T_990;
+ wire [9:0] T_991;
+ wire T_992;
+ wire [9:0] T_993;
+ wire [25:0] oacq_read_block_addr_block;
+ wire [3:0] oacq_read_block_client_xact_id;
+ wire [1:0] oacq_read_block_addr_beat;
+ wire oacq_read_block_is_builtin_type;
+ wire [2:0] oacq_read_block_a_type;
+ wire [16:0] oacq_read_block_union;
+ wire [3:0] oacq_read_block_data;
+ wire T_1011;
+ wire T_1012;
+ wire [25:0] T_1013_addr_block;
+ wire [3:0] T_1013_client_xact_id;
+ wire [1:0] T_1013_addr_beat;
+ wire T_1013_is_builtin_type;
+ wire [2:0] T_1013_a_type;
+ wire [16:0] T_1013_union;
+ wire [3:0] T_1013_data;
+ wire [25:0] T_1021_addr_block;
+ wire [3:0] T_1021_client_xact_id;
+ wire [1:0] T_1021_addr_beat;
+ wire T_1021_is_builtin_type;
+ wire [2:0] T_1021_a_type;
+ wire [16:0] T_1021_union;
+ wire [3:0] T_1021_data;
+ wire [25:0] T_1029_addr_block;
+ wire [3:0] T_1029_client_xact_id;
+ wire [1:0] T_1029_addr_beat;
+ wire T_1029_is_builtin_type;
+ wire [2:0] T_1029_a_type;
+ wire [16:0] T_1029_union;
+ wire [3:0] T_1029_data;
+ wire [25:0] T_1037_addr_block;
+ wire [3:0] T_1037_client_xact_id;
+ wire [1:0] T_1037_addr_beat;
+ wire T_1037_is_builtin_type;
+ wire [2:0] T_1037_a_type;
+ wire [16:0] T_1037_union;
+ wire [3:0] T_1037_data;
+ wire T_1054;
+ wire [1:0] T_1055;
+ wire T_1056;
+ wire [1:0] T_1057;
+ wire T_1058;
+ wire [1:0] T_1059;
+ wire T_1060;
+ wire [1:0] T_1061;
+ wire T_1062;
+ wire [1:0] T_1063;
+ wire T_1064;
+ wire [1:0] T_1065;
+ wire T_1066;
+ wire [1:0] T_1067;
+ wire T_1068;
+ wire [1:0] T_1069;
+ wire T_1070;
+ wire [1:0] T_1071;
+ wire [1:0] T_1072;
+ wire [25:0] T_1077_addr_block;
+ wire [1:0] T_1077_p_type;
+ wire [1:0] T_1077_client_id;
+ wire T_1100;
+ wire [2:0] T_1101;
+ wire T_1102;
+ wire [2:0] T_1103;
+ wire T_1104;
+ wire [2:0] T_1105;
+ wire T_1106;
+ wire [2:0] T_1107;
+ wire T_1108;
+ wire [2:0] T_1109;
+ wire T_1110;
+ wire [2:0] T_1111;
+ wire T_1112;
+ wire [2:0] T_1113;
+ wire T_1114;
+ wire T_1117;
+ wire T_1118;
+ wire T_1119;
+ wire [2:0] T_1120;
+ wire [1:0] T_1129_addr_beat;
+ wire [1:0] T_1129_client_xact_id;
+ wire [3:0] T_1129_manager_xact_id;
+ wire T_1129_is_builtin_type;
+ wire [3:0] T_1129_g_type;
+ wire [3:0] T_1129_data;
+ wire [1:0] T_1129_client_id;
+ wire T_1140;
+ wire T_1141;
+ wire T_1142;
+ wire T_1143;
+ wire T_1144;
+ wire T_1145;
+ wire T_1147;
+ wire T_1149;
+ wire T_1151;
+ wire T_1153;
+ wire T_1154;
+ wire T_1155;
+ wire T_1156;
+ wire T_1157;
+ wire T_1158;
+ wire T_1159;
+ wire T_1161;
+ wire T_1163;
+ wire T_1165;
+ wire T_1167;
+ wire T_1168;
+ wire T_1169;
+ wire T_1170;
+ wire T_1172;
+ wire [2:0] T_1175_0;
+ wire T_1178;
+ wire T_1180;
+ wire T_1181;
+ wire T_1182;
+ wire T_1184;
+ wire T_1185;
+ wire T_1187;
+ wire T_1189;
+ wire T_1191;
+ wire T_1193;
+ wire [3:0] GEN_3;
+ wire [3:0] T_1197;
+ wire T_1198;
+ wire [1:0] T_1200;
+ wire T_1202;
+ wire T_1203;
+ wire T_1204;
+ wire T_1205;
+ wire T_1207_0;
+ wire T_1207_1;
+ wire [8:0] T_1212;
+ wire [7:0] T_1213;
+ wire [8:0] T_1215;
+ wire [7:0] T_1216;
+ wire [7:0] T_1218_0;
+ wire [7:0] T_1218_1;
+ wire [15:0] T_1222;
+ wire T_1224;
+ wire T_1225;
+ wire T_1227;
+ wire T_1228;
+ wire T_1229;
+ wire [15:0] T_1230;
+ wire [15:0] T_1232;
+ wire [15:0] T_1233;
+ wire [15:0] GEN_4;
+ wire [3:0] T_1236;
+ wire [3:0] T_1237;
+ wire [3:0] T_1238;
+ wire [3:0] T_1239;
+ wire [3:0] T_1240;
+ wire [3:0] T_1241;
+ wire T_1245;
+ wire [3:0] GEN_5;
+ wire [3:0] T_1251;
+ wire T_1252;
+ wire [1:0] T_1254;
+ wire T_1256;
+ wire T_1257;
+ wire T_1258;
+ wire T_1259;
+ wire T_1261_0;
+ wire T_1261_1;
+ wire [8:0] T_1266;
+ wire [7:0] T_1267;
+ wire [8:0] T_1269;
+ wire [7:0] T_1270;
+ wire [7:0] T_1272_0;
+ wire [7:0] T_1272_1;
+ wire [15:0] T_1276;
+ wire T_1278;
+ wire T_1279;
+ wire T_1281;
+ wire T_1282;
+ wire T_1283;
+ wire [15:0] T_1284;
+ wire [15:0] T_1286;
+ wire [15:0] T_1287;
+ wire [15:0] GEN_6;
+ wire T_1289;
+ wire [2:0] T_1292_0;
+ wire T_1295;
+ wire T_1297;
+ wire T_1298;
+ wire [2:0] T_1303_0;
+ wire [2:0] T_1303_1;
+ wire [2:0] T_1303_2;
+ wire T_1308;
+ wire T_1309;
+ wire T_1310;
+ wire T_1312;
+ wire T_1313;
+ wire T_1314;
+ wire T_1315;
+ wire [3:0] T_1316;
+ wire T_1318;
+ wire T_1319;
+ wire T_1320;
+ wire T_1321;
+ wire T_1322;
+ wire [1:0] T_1324;
+ wire [2:0] T_1325;
+ wire [1:0] T_1326;
+ wire [1:0] T_1329;
+ wire [2:0] T_1330;
+ wire [1:0] T_1331;
+ wire [2:0] T_1332;
+ wire [3:0] T_1333;
+ wire [2:0] T_1334;
+ wire [2:0] T_1335;
+ wire [2:0] T_1336;
+ wire [2:0] T_1337;
+ wire T_1338;
+ wire T_1340;
+ wire [1:0] T_1342;
+ wire [1:0] T_1343;
+ wire [1:0] T_1344;
+ wire [1:0] T_1346_0;
+ wire [1:0] T_1346_1;
+ wire [1:0] T_1346_2;
+ wire T_1351;
+ wire T_1352;
+ wire T_1353;
+ wire T_1355;
+ wire T_1356;
+ wire T_1357;
+ wire T_1359;
+ wire T_1360;
+ wire [1:0] T_1362_0;
+ wire [1:0] T_1362_1;
+ wire [1:0] T_1362_2;
+ wire T_1367;
+ wire T_1368;
+ wire T_1369;
+ wire T_1371;
+ wire T_1372;
+ wire T_1373;
+ wire [1:0] T_1377;
+ wire T_1378;
+ wire T_1380;
+ wire [2:0] T_1381;
+ wire [2:0] T_1382;
+ wire T_1384;
+ wire [1:0] T_1386;
+ wire T_1387;
+ wire T_1389;
+ wire [2:0] T_1390;
+ wire [2:0] T_1391;
+ wire T_1392;
+ wire T_1394;
+ wire T_1396;
+ wire [3:0] T_1397;
+ wire T_1398;
+ wire T_1399;
+ wire T_1400;
+ wire [2:0] T_1402;
+ wire T_1403;
+ wire T_1405;
+ wire T_1406;
+ wire T_1407;
+ wire T_1410;
+ wire T_1412;
+ wire T_1413;
+ wire T_1415;
+ wire T_1416;
+ wire [2:0] T_1417;
+ wire T_1418;
+ wire T_1422;
+ wire T_1424;
+ wire T_1425;
+ wire T_1427;
+ wire T_1428;
+ wire [2:0] T_1429;
+ wire T_1430;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ wire GEN_17;
+ wire GEN_18;
+ wire GEN_19;
+ wire GEN_20;
+ wire GEN_21;
+ wire GEN_22;
+ wire GEN_23;
+ wire GEN_24;
+ wire GEN_25;
+ wire GEN_26;
+ wire GEN_27;
+ wire GEN_28;
+ wire GEN_29;
+ wire GEN_30;
+ wire GEN_31;
+ wire GEN_32;
+ wire GEN_33;
+ wire GEN_34;
+ wire GEN_35;
+ wire GEN_36;
+ wire GEN_37;
+ wire GEN_38;
+ wire GEN_39;
+ wire GEN_40;
+ wire GEN_41;
+ wire GEN_42;
+ wire GEN_43;
+ wire GEN_44;
+ wire GEN_45;
+ wire GEN_46;
+ wire GEN_47;
+ wire GEN_48;
+ wire GEN_49;
+ wire GEN_50;
+ wire GEN_51;
+ wire GEN_52;
+ wire GEN_53;
+ assign io_inner_acquire_ready = T_1245 ? 1'h1 : collect_iacq_data ? 1'h1 : 1'h0;
+ assign io_inner_grant_valid = T_1418 ? 1'h1 : T_1407 ? io_outer_grant_valid : 1'h0;
+ assign io_inner_grant_bits_addr_beat = T_1129_addr_beat;
+ assign io_inner_grant_bits_client_xact_id = T_1129_client_xact_id;
+ assign io_inner_grant_bits_manager_xact_id = T_1129_manager_xact_id;
+ assign io_inner_grant_bits_is_builtin_type = T_1129_is_builtin_type;
+ assign io_inner_grant_bits_g_type = T_1129_g_type;
+ assign io_inner_grant_bits_data = T_1129_data;
+ assign io_inner_grant_bits_client_id = T_1129_client_id;
+ assign io_inner_finish_ready = T_1430 ? 1'h1 : 1'h0;
+ assign io_inner_probe_valid = T_1338 ? T_1340 : 1'h0;
+ assign io_inner_probe_bits_addr_block = T_1077_addr_block;
+ assign io_inner_probe_bits_p_type = T_1077_p_type;
+ assign io_inner_probe_bits_client_id = T_1077_client_id;
+ assign io_inner_release_ready = T_1338 ? T_1360 : 1'h0;
+ assign io_outer_acquire_valid = T_1403 ? T_1405 : T_1392 ? T_1400 : T_1338 ? io_inner_release_valid ? T_1373 ? 1'h1 : 1'h0 : 1'h0 : 1'h0;
+ assign io_outer_acquire_bits_addr_block = T_1037_addr_block;
+ assign io_outer_acquire_bits_client_xact_id = T_1037_client_xact_id;
+ assign io_outer_acquire_bits_addr_beat = T_1037_addr_beat;
+ assign io_outer_acquire_bits_is_builtin_type = T_1037_is_builtin_type;
+ assign io_outer_acquire_bits_a_type = T_1037_a_type;
+ assign io_outer_acquire_bits_union = T_1037_union;
+ assign io_outer_acquire_bits_data = T_1037_data;
+ assign io_outer_grant_ready = T_1407 ? io_inner_grant_ready : pending_ognt_ack ? 1'h1 : 1'h0;
+ assign io_has_acquire_conflict = T_676;
+ assign io_has_acquire_match = T_678;
+ assign io_has_release_match = T_684;
+ assign coh_sharers = 1'h0;
+ assign T_303 = state != 1'h0;
+ assign T_304 = T_303 & xact_is_builtin_type;
+ assign T_309_0 = 3'h4;
+ assign T_309_1 = 3'h5;
+ assign T_309_2 = 3'h6;
+ assign T_314 = T_309_0 == xact_a_type;
+ assign T_315 = T_309_1 == xact_a_type;
+ assign T_316 = T_309_2 == xact_a_type;
+ assign T_318 = 1'h0 | T_314;
+ assign T_319 = T_318 | T_315;
+ assign T_320 = T_319 | T_316;
+ assign T_321 = T_304 & T_320;
+ assign T_323 = T_321 == 1'h0;
+ assign T_325 = reset == 1'h0;
+ assign T_327 = T_323 == 1'h0;
+ assign T_329 = reset == 1'h0;
+ assign T_334 = pending_probes;
+ assign T_336_0 = T_334;
+ assign GEN_7 = $signed(1'h1);
+ assign T_341 = $unsigned(GEN_7);
+ assign T_344 = 1'h1 << io_inner_acquire_bits_client_id;
+ assign T_345 = T_341 | T_344;
+ assign T_346 = ~ T_341;
+ assign T_347 = T_346 | T_344;
+ assign T_348 = ~ T_347;
+ assign mask_self = 1'h0 ? T_345 : T_348;
+ assign T_350 = ~ io_incoherent_0;
+ assign mask_incoherent = mask_self & T_350;
+ assign T_356 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_359 = 1'h1 & io_inner_acquire_bits_is_builtin_type;
+ assign T_362_0 = 3'h3;
+ assign T_365 = T_362_0 == io_inner_acquire_bits_a_type;
+ assign T_367 = 1'h0 | T_365;
+ assign T_368 = T_359 & T_367;
+ assign T_369 = T_356 & T_368;
+ assign T_373 = T_371 == 2'h3;
+ assign T_375 = 1'h0 & T_373;
+ assign T_378 = T_371 + 1'h1;
+ assign T_379 = T_378[1:0];
+ assign T_380 = T_375 ? 1'h0 : T_379;
+ assign T_381 = T_369 & T_373;
+ assign T_382 = T_368 ? T_371 : 1'h0;
+ assign iacq_data_done = T_368 ? T_381 : T_356;
+ assign T_384 = io_inner_release_ready & io_inner_release_valid;
+ assign T_388_0 = 1'h0;
+ assign T_388_1 = 1'h1;
+ assign T_388_2 = 2'h2;
+ assign T_393 = T_388_0 == io_inner_release_bits_r_type;
+ assign T_394 = T_388_1 == io_inner_release_bits_r_type;
+ assign T_395 = T_388_2 == io_inner_release_bits_r_type;
+ assign T_397 = 1'h0 | T_393;
+ assign T_398 = T_397 | T_394;
+ assign T_399 = T_398 | T_395;
+ assign T_400 = 1'h1 & T_399;
+ assign T_401 = T_384 & T_400;
+ assign T_405 = T_403 == 2'h3;
+ assign T_407 = 1'h0 & T_405;
+ assign T_410 = T_403 + 1'h1;
+ assign T_411 = T_410[1:0];
+ assign T_412 = T_407 ? 1'h0 : T_411;
+ assign T_413 = T_401 & T_405;
+ assign T_414 = T_400 ? T_403 : 1'h0;
+ assign irel_data_done = T_400 ? T_413 : T_384;
+ assign T_417 = io_inner_grant_ready & io_inner_grant_valid;
+ assign T_421_0 = 3'h5;
+ assign T_424 = T_421_0 == io_inner_grant_bits_g_type;
+ assign T_426 = 1'h0 | T_424;
+ assign T_428_0 = 1'h0;
+ assign T_428_1 = 1'h1;
+ assign T_432 = T_428_0 == io_inner_grant_bits_g_type;
+ assign T_433 = T_428_1 == io_inner_grant_bits_g_type;
+ assign T_435 = 1'h0 | T_432;
+ assign T_436 = T_435 | T_433;
+ assign T_437 = io_inner_grant_bits_is_builtin_type ? T_426 : T_436;
+ assign T_438 = 1'h1 & T_437;
+ assign T_439 = T_417 & T_438;
+ assign T_443 = T_441 == 2'h3;
+ assign T_445 = 1'h0 & T_443;
+ assign T_448 = T_441 + 1'h1;
+ assign T_449 = T_448[1:0];
+ assign T_450 = T_445 ? 1'h0 : T_449;
+ assign T_451 = T_439 & T_443;
+ assign ignt_data_cnt = T_438 ? T_441 : 1'h0;
+ assign ignt_data_done = T_438 ? T_451 : T_417;
+ assign T_455 = io_outer_acquire_ready & io_outer_acquire_valid;
+ assign T_457 = 1'h1 & io_outer_acquire_bits_is_builtin_type;
+ assign T_460_0 = 3'h3;
+ assign T_463 = T_460_0 == io_outer_acquire_bits_a_type;
+ assign T_465 = 1'h0 | T_463;
+ assign T_466 = T_457 & T_465;
+ assign T_467 = T_455 & T_466;
+ assign T_471 = T_469 == 2'h3;
+ assign T_473 = 1'h0 & T_471;
+ assign T_476 = T_469 + 1'h1;
+ assign T_477 = T_476[1:0];
+ assign T_478 = T_473 ? 1'h0 : T_477;
+ assign T_479 = T_467 & T_471;
+ assign oacq_data_cnt = T_466 ? T_469 : 1'h0;
+ assign oacq_data_done = T_466 ? T_479 : T_455;
+ assign T_482 = io_outer_grant_ready & io_outer_grant_valid;
+ assign T_487_0 = 3'h5;
+ assign T_490 = T_487_0 == io_outer_grant_bits_g_type;
+ assign T_492 = 1'h0 | T_490;
+ assign T_494_0 = 1'h0;
+ assign T_497 = T_494_0 == io_outer_grant_bits_g_type;
+ assign T_499 = 1'h0 | T_497;
+ assign T_500 = io_outer_grant_bits_is_builtin_type ? T_492 : T_499;
+ assign T_501 = 1'h1 & T_500;
+ assign T_502 = T_482 & T_501;
+ assign T_506 = T_504 == 2'h3;
+ assign T_508 = 1'h0 & T_506;
+ assign T_511 = T_504 + 1'h1;
+ assign T_512 = T_511[1:0];
+ assign T_513 = T_508 ? 1'h0 : T_512;
+ assign T_514 = T_502 & T_506;
+ assign T_515 = T_501 ? T_504 : 1'h0;
+ assign ognt_data_done = T_501 ? T_514 : T_482;
+ assign T_523_0 = 3'h2;
+ assign T_523_1 = 3'h3;
+ assign T_523_2 = 3'h4;
+ assign T_528 = T_523_0 == xact_a_type;
+ assign T_529 = T_523_1 == xact_a_type;
+ assign T_530 = T_523_2 == xact_a_type;
+ assign T_532 = 1'h0 | T_528;
+ assign T_533 = T_532 | T_529;
+ assign T_534 = T_533 | T_530;
+ assign pending_outer_write = xact_is_builtin_type & T_534;
+ assign T_540_0 = 3'h2;
+ assign T_540_1 = 3'h3;
+ assign T_540_2 = 3'h4;
+ assign T_545 = T_540_0 == io_inner_acquire_bits_a_type;
+ assign T_546 = T_540_1 == io_inner_acquire_bits_a_type;
+ assign T_547 = T_540_2 == io_inner_acquire_bits_a_type;
+ assign T_549 = 1'h0 | T_545;
+ assign T_550 = T_549 | T_546;
+ assign T_551 = T_550 | T_547;
+ assign pending_outer_write_ = io_inner_acquire_bits_is_builtin_type & T_551;
+ assign T_556_0 = 3'h5;
+ assign T_556_1 = 3'h4;
+ assign T_560 = T_556_0 == io_inner_grant_bits_g_type;
+ assign T_561 = T_556_1 == io_inner_grant_bits_g_type;
+ assign T_563 = 1'h0 | T_560;
+ assign T_564 = T_563 | T_561;
+ assign T_566_0 = 1'h0;
+ assign T_566_1 = 1'h1;
+ assign T_570 = T_566_0 == io_inner_grant_bits_g_type;
+ assign T_571 = T_566_1 == io_inner_grant_bits_g_type;
+ assign T_573 = 1'h0 | T_570;
+ assign T_574 = T_573 | T_571;
+ assign pending_outer_read = io_inner_grant_bits_is_builtin_type ? T_564 : T_574;
+ assign T_594 = 3'h6 == io_inner_acquire_bits_a_type;
+ assign T_595 = T_594 ? 3'h1 : 3'h3;
+ assign T_596 = 3'h5 == io_inner_acquire_bits_a_type;
+ assign T_597 = T_596 ? 3'h1 : T_595;
+ assign T_598 = 3'h4 == io_inner_acquire_bits_a_type;
+ assign T_599 = T_598 ? 3'h4 : T_597;
+ assign T_600 = 3'h3 == io_inner_acquire_bits_a_type;
+ assign T_601 = T_600 ? 3'h3 : T_599;
+ assign T_602 = 3'h2 == io_inner_acquire_bits_a_type;
+ assign T_603 = T_602 ? 3'h3 : T_601;
+ assign T_604 = 3'h1 == io_inner_acquire_bits_a_type;
+ assign T_605 = T_604 ? 3'h5 : T_603;
+ assign T_606 = 3'h0 == io_inner_acquire_bits_a_type;
+ assign T_607 = T_606 ? 3'h4 : T_605;
+ assign T_608 = io_inner_acquire_bits_a_type == 1'h0;
+ assign T_611 = 1'h0 == 1'h0;
+ assign T_612 = T_611 ? 1'h0 : 1'h1;
+ assign T_613 = T_608 ? T_612 : 1'h1;
+ assign T_614 = io_inner_acquire_bits_is_builtin_type ? T_607 : T_613;
+ assign T_623_addr_beat = 1'h0;
+ assign T_623_client_xact_id = io_inner_acquire_bits_client_xact_id;
+ assign T_623_manager_xact_id = 3'h4;
+ assign T_623_is_builtin_type = io_inner_acquire_bits_is_builtin_type;
+ assign T_623_g_type = T_614;
+ assign T_623_data = 1'h0;
+ assign T_623_client_id = io_inner_acquire_bits_client_id;
+ assign T_634_0 = 3'h5;
+ assign T_634_1 = 3'h4;
+ assign T_638 = T_634_0 == T_623_g_type;
+ assign T_639 = T_634_1 == T_623_g_type;
+ assign T_641 = 1'h0 | T_638;
+ assign T_642 = T_641 | T_639;
+ assign T_644_0 = 1'h0;
+ assign T_644_1 = 1'h1;
+ assign T_648 = T_644_0 == T_623_g_type;
+ assign T_649 = T_644_1 == T_623_g_type;
+ assign T_651 = 1'h0 | T_648;
+ assign T_652 = T_651 | T_649;
+ assign pending_outer_read_ = T_623_is_builtin_type ? T_642 : T_652;
+ assign T_658_0 = 3'h2;
+ assign T_658_1 = 3'h0;
+ assign T_658_2 = 3'h4;
+ assign T_663 = T_658_0 == xact_a_type;
+ assign T_664 = T_658_1 == xact_a_type;
+ assign T_665 = T_658_2 == xact_a_type;
+ assign T_667 = 1'h0 | T_663;
+ assign T_668 = T_667 | T_664;
+ assign T_669 = T_668 | T_665;
+ assign subblock_type = xact_is_builtin_type & T_669;
+ assign T_671 = xact_addr_block == io_inner_acquire_bits_addr_block;
+ assign T_672 = state != 1'h0;
+ assign T_673 = T_671 & T_672;
+ assign T_675 = collect_iacq_data == 1'h0;
+ assign T_676 = T_673 & T_675;
+ assign T_677 = xact_addr_block == io_inner_acquire_bits_addr_block;
+ assign T_678 = T_677 & collect_iacq_data;
+ assign T_679 = xact_addr_block == io_inner_release_bits_addr_block;
+ assign T_681 = io_inner_release_bits_voluntary == 1'h0;
+ assign T_682 = T_679 & T_681;
+ assign T_683 = state == 1'h1;
+ assign T_684 = T_682 & T_683;
+ assign GEN_8 = $signed(16'hffff);
+ assign T_689 = $unsigned(GEN_8);
+ assign T_695 = {1'h0,3'h7};
+ assign T_696 = {1'h0,1'h1};
+ assign T_697 = {T_695,T_696};
+ assign T_699 = {1'h0,1'h1};
+ assign T_700 = {3'h7,T_699};
+ assign T_702 = {T_689,1'h1};
+ assign T_704 = {T_689,1'h1};
+ assign T_706 = {1'h0,3'h7};
+ assign T_707 = {1'h0,1'h1};
+ assign T_708 = {T_706,T_707};
+ assign T_710 = {5'h0,1'h1};
+ assign T_712 = {5'h1,1'h1};
+ assign T_713 = 3'h6 == 3'h3;
+ assign T_714 = T_713 ? T_712 : 1'h0;
+ assign T_715 = 3'h5 == 3'h3;
+ assign T_716 = T_715 ? T_710 : T_714;
+ assign T_717 = 3'h4 == 3'h3;
+ assign T_718 = T_717 ? T_708 : T_716;
+ assign T_719 = 3'h3 == 3'h3;
+ assign T_720 = T_719 ? T_704 : T_718;
+ assign T_721 = 3'h2 == 3'h3;
+ assign T_722 = T_721 ? T_702 : T_720;
+ assign T_723 = 3'h1 == 3'h3;
+ assign T_724 = T_723 ? T_700 : T_722;
+ assign T_725 = 3'h0 == 3'h3;
+ assign T_726 = T_725 ? T_697 : T_724;
+ assign oacq_probe_addr_block = io_inner_release_bits_addr_block;
+ assign oacq_probe_client_xact_id = 3'h4;
+ assign oacq_probe_addr_beat = io_inner_release_bits_addr_beat;
+ assign oacq_probe_is_builtin_type = 1'h1;
+ assign oacq_probe_a_type = 3'h3;
+ assign oacq_probe_union = T_726;
+ assign oacq_probe_data = io_inner_release_bits_data;
+ assign T_744 = xact_union[12:9];
+ assign T_745 = T_744[3];
+ assign T_747 = 1'h1 << T_745;
+ assign T_749 = xact_a_type == 3'h4;
+ assign T_750 = xact_is_builtin_type & T_749;
+ assign T_751 = T_747[0];
+ assign T_752 = T_747[1];
+ assign T_754_0 = T_751;
+ assign T_754_1 = T_752;
+ assign T_759 = 8'h0 - T_754_0;
+ assign T_760 = T_759[7:0];
+ assign T_762 = 8'h0 - T_754_1;
+ assign T_763 = T_762[7:0];
+ assign T_765_0 = T_760;
+ assign T_765_1 = T_763;
+ assign T_769 = {T_765_1,T_765_0};
+ assign T_771 = xact_a_type == 3'h3;
+ assign T_772 = xact_is_builtin_type & T_771;
+ assign T_774 = xact_a_type == 3'h2;
+ assign T_775 = xact_is_builtin_type & T_774;
+ assign T_776 = T_772 | T_775;
+ assign T_777 = xact_union[16:1];
+ assign T_779 = T_776 ? T_777 : 16'h0;
+ assign T_780 = T_750 ? T_769 : T_779;
+ assign T_788 = {1'h0,3'h7};
+ assign T_789 = {1'h0,1'h1};
+ assign T_790 = {T_788,T_789};
+ assign T_792 = {1'h0,1'h1};
+ assign T_793 = {3'h7,T_792};
+ assign T_795 = {T_780,1'h1};
+ assign T_797 = {T_780,1'h1};
+ assign T_799 = {1'h0,3'h7};
+ assign T_800 = {1'h0,1'h1};
+ assign T_801 = {T_799,T_800};
+ assign T_803 = {5'h0,1'h1};
+ assign T_805 = {5'h1,1'h1};
+ assign T_806 = 3'h6 == 3'h2;
+ assign T_807 = T_806 ? T_805 : 1'h0;
+ assign T_808 = 3'h5 == 3'h2;
+ assign T_809 = T_808 ? T_803 : T_807;
+ assign T_810 = 3'h4 == 3'h2;
+ assign T_811 = T_810 ? T_801 : T_809;
+ assign T_812 = 3'h3 == 3'h2;
+ assign T_813 = T_812 ? T_797 : T_811;
+ assign T_814 = 3'h2 == 3'h2;
+ assign T_815 = T_814 ? T_795 : T_813;
+ assign T_816 = 3'h1 == 3'h2;
+ assign T_817 = T_816 ? T_793 : T_815;
+ assign T_818 = 3'h0 == 3'h2;
+ assign T_819 = T_818 ? T_790 : T_817;
+ assign oacq_write_beat_addr_block = xact_addr_block;
+ assign oacq_write_beat_client_xact_id = 3'h4;
+ assign oacq_write_beat_addr_beat = xact_addr_beat;
+ assign oacq_write_beat_is_builtin_type = 1'h1;
+ assign oacq_write_beat_a_type = 3'h2;
+ assign oacq_write_beat_union = T_819;
+ assign oacq_write_beat_data = xact_data_buffer_0;
+ assign T_846 = {1'h0,3'h7};
+ assign T_847 = {1'h0,1'h1};
+ assign T_848 = {T_846,T_847};
+ assign T_850 = {1'h0,1'h1};
+ assign T_851 = {3'h7,T_850};
+ assign GEN_0 = GEN_45 ? xact_wmask_buffer_3 : GEN_46 ? xact_wmask_buffer_2 : GEN_47 ? xact_wmask_buffer_1 : xact_wmask_buffer_0;
+ assign T_853 = {GEN_0,1'h1};
+ assign GEN_1 = GEN_48 ? xact_wmask_buffer_3 : GEN_49 ? xact_wmask_buffer_2 : GEN_50 ? xact_wmask_buffer_1 : xact_wmask_buffer_0;
+ assign T_855 = {GEN_1,1'h1};
+ assign T_857 = {1'h0,3'h7};
+ assign T_858 = {1'h0,1'h1};
+ assign T_859 = {T_857,T_858};
+ assign T_861 = {5'h0,1'h1};
+ assign T_863 = {5'h1,1'h1};
+ assign T_864 = 3'h6 == 3'h3;
+ assign T_865 = T_864 ? T_863 : 1'h0;
+ assign T_866 = 3'h5 == 3'h3;
+ assign T_867 = T_866 ? T_861 : T_865;
+ assign T_868 = 3'h4 == 3'h3;
+ assign T_869 = T_868 ? T_859 : T_867;
+ assign T_870 = 3'h3 == 3'h3;
+ assign T_871 = T_870 ? T_855 : T_869;
+ assign T_872 = 3'h2 == 3'h3;
+ assign T_873 = T_872 ? T_853 : T_871;
+ assign T_874 = 3'h1 == 3'h3;
+ assign T_875 = T_874 ? T_851 : T_873;
+ assign T_876 = 3'h0 == 3'h3;
+ assign T_877 = T_876 ? T_848 : T_875;
+ assign oacq_write_block_addr_block = xact_addr_block;
+ assign oacq_write_block_client_xact_id = 3'h4;
+ assign oacq_write_block_addr_beat = oacq_data_cnt;
+ assign oacq_write_block_is_builtin_type = 1'h1;
+ assign oacq_write_block_a_type = 3'h3;
+ assign oacq_write_block_union = T_877;
+ assign oacq_write_block_data = GEN_2;
+ assign GEN_2 = GEN_51 ? xact_data_buffer_3 : GEN_52 ? xact_data_buffer_2 : GEN_53 ? xact_data_buffer_1 : xact_data_buffer_0;
+ assign T_895 = xact_union[12:9];
+ assign T_896 = xact_union[8:6];
+ assign T_904 = {T_895,T_896};
+ assign T_905 = {5'h0,1'h0};
+ assign T_906 = {T_904,T_905};
+ assign T_908 = {5'h0,1'h0};
+ assign T_909 = {T_896,T_908};
+ assign T_911 = {1'h0,1'h0};
+ assign T_913 = {1'h0,1'h0};
+ assign T_915 = {T_895,T_896};
+ assign T_916 = {5'h0,1'h0};
+ assign T_917 = {T_915,T_916};
+ assign T_919 = {5'h0,1'h0};
+ assign T_921 = {5'h1,1'h0};
+ assign T_922 = 3'h6 == 3'h0;
+ assign T_923 = T_922 ? T_921 : 1'h0;
+ assign T_924 = 3'h5 == 3'h0;
+ assign T_925 = T_924 ? T_919 : T_923;
+ assign T_926 = 3'h4 == 3'h0;
+ assign T_927 = T_926 ? T_917 : T_925;
+ assign T_928 = 3'h3 == 3'h0;
+ assign T_929 = T_928 ? T_913 : T_927;
+ assign T_930 = 3'h2 == 3'h0;
+ assign T_931 = T_930 ? T_911 : T_929;
+ assign T_932 = 3'h1 == 3'h0;
+ assign T_933 = T_932 ? T_909 : T_931;
+ assign T_934 = 3'h0 == 3'h0;
+ assign T_935 = T_934 ? T_906 : T_933;
+ assign oacq_read_beat_addr_block = xact_addr_block;
+ assign oacq_read_beat_client_xact_id = 3'h4;
+ assign oacq_read_beat_addr_beat = xact_addr_beat;
+ assign oacq_read_beat_is_builtin_type = 1'h1;
+ assign oacq_read_beat_a_type = 3'h0;
+ assign oacq_read_beat_union = T_935;
+ assign oacq_read_beat_data = 1'h0;
+ assign T_962 = {1'h0,3'h7};
+ assign T_963 = {5'h0,1'h1};
+ assign T_964 = {T_962,T_963};
+ assign T_966 = {5'h0,1'h1};
+ assign T_967 = {3'h7,T_966};
+ assign T_969 = {1'h0,1'h1};
+ assign T_971 = {1'h0,1'h1};
+ assign T_973 = {1'h0,3'h7};
+ assign T_974 = {5'h0,1'h1};
+ assign T_975 = {T_973,T_974};
+ assign T_977 = {5'h0,1'h1};
+ assign T_979 = {5'h1,1'h1};
+ assign T_980 = 3'h6 == 3'h1;
+ assign T_981 = T_980 ? T_979 : 1'h0;
+ assign T_982 = 3'h5 == 3'h1;
+ assign T_983 = T_982 ? T_977 : T_981;
+ assign T_984 = 3'h4 == 3'h1;
+ assign T_985 = T_984 ? T_975 : T_983;
+ assign T_986 = 3'h3 == 3'h1;
+ assign T_987 = T_986 ? T_971 : T_985;
+ assign T_988 = 3'h2 == 3'h1;
+ assign T_989 = T_988 ? T_969 : T_987;
+ assign T_990 = 3'h1 == 3'h1;
+ assign T_991 = T_990 ? T_967 : T_989;
+ assign T_992 = 3'h0 == 3'h1;
+ assign T_993 = T_992 ? T_964 : T_991;
+ assign oacq_read_block_addr_block = xact_addr_block;
+ assign oacq_read_block_client_xact_id = 3'h4;
+ assign oacq_read_block_addr_beat = 1'h0;
+ assign oacq_read_block_is_builtin_type = 1'h1;
+ assign oacq_read_block_a_type = 3'h1;
+ assign oacq_read_block_union = T_993;
+ assign oacq_read_block_data = 1'h0;
+ assign T_1011 = state == 1'h1;
+ assign T_1012 = state == 2'h3;
+ assign T_1013_addr_block = subblock_type ? oacq_write_beat_addr_block : oacq_write_block_addr_block;
+ assign T_1013_client_xact_id = subblock_type ? oacq_write_beat_client_xact_id : oacq_write_block_client_xact_id;
+ assign T_1013_addr_beat = subblock_type ? oacq_write_beat_addr_beat : oacq_write_block_addr_beat;
+ assign T_1013_is_builtin_type = subblock_type ? oacq_write_beat_is_builtin_type : oacq_write_block_is_builtin_type;
+ assign T_1013_a_type = subblock_type ? oacq_write_beat_a_type : oacq_write_block_a_type;
+ assign T_1013_union = subblock_type ? oacq_write_beat_union : oacq_write_block_union;
+ assign T_1013_data = subblock_type ? oacq_write_beat_data : oacq_write_block_data;
+ assign T_1021_addr_block = subblock_type ? oacq_read_beat_addr_block : oacq_read_block_addr_block;
+ assign T_1021_client_xact_id = subblock_type ? oacq_read_beat_client_xact_id : oacq_read_block_client_xact_id;
+ assign T_1021_addr_beat = subblock_type ? oacq_read_beat_addr_beat : oacq_read_block_addr_beat;
+ assign T_1021_is_builtin_type = subblock_type ? oacq_read_beat_is_builtin_type : oacq_read_block_is_builtin_type;
+ assign T_1021_a_type = subblock_type ? oacq_read_beat_a_type : oacq_read_block_a_type;
+ assign T_1021_union = subblock_type ? oacq_read_beat_union : oacq_read_block_union;
+ assign T_1021_data = subblock_type ? oacq_read_beat_data : oacq_read_block_data;
+ assign T_1029_addr_block = T_1012 ? T_1013_addr_block : T_1021_addr_block;
+ assign T_1029_client_xact_id = T_1012 ? T_1013_client_xact_id : T_1021_client_xact_id;
+ assign T_1029_addr_beat = T_1012 ? T_1013_addr_beat : T_1021_addr_beat;
+ assign T_1029_is_builtin_type = T_1012 ? T_1013_is_builtin_type : T_1021_is_builtin_type;
+ assign T_1029_a_type = T_1012 ? T_1013_a_type : T_1021_a_type;
+ assign T_1029_union = T_1012 ? T_1013_union : T_1021_union;
+ assign T_1029_data = T_1012 ? T_1013_data : T_1021_data;
+ assign T_1037_addr_block = T_1011 ? oacq_probe_addr_block : T_1029_addr_block;
+ assign T_1037_client_xact_id = T_1011 ? oacq_probe_client_xact_id : T_1029_client_xact_id;
+ assign T_1037_addr_beat = T_1011 ? oacq_probe_addr_beat : T_1029_addr_beat;
+ assign T_1037_is_builtin_type = T_1011 ? oacq_probe_is_builtin_type : T_1029_is_builtin_type;
+ assign T_1037_a_type = T_1011 ? oacq_probe_a_type : T_1029_a_type;
+ assign T_1037_union = T_1011 ? oacq_probe_union : T_1029_union;
+ assign T_1037_data = T_1011 ? oacq_probe_data : T_1029_data;
+ assign T_1054 = 3'h4 == xact_a_type;
+ assign T_1055 = T_1054 ? 1'h0 : 2'h2;
+ assign T_1056 = 3'h6 == xact_a_type;
+ assign T_1057 = T_1056 ? 1'h0 : T_1055;
+ assign T_1058 = 3'h5 == xact_a_type;
+ assign T_1059 = T_1058 ? 2'h2 : T_1057;
+ assign T_1060 = 3'h2 == xact_a_type;
+ assign T_1061 = T_1060 ? 1'h0 : T_1059;
+ assign T_1062 = 3'h0 == xact_a_type;
+ assign T_1063 = T_1062 ? 2'h2 : T_1061;
+ assign T_1064 = 3'h3 == xact_a_type;
+ assign T_1065 = T_1064 ? 1'h0 : T_1063;
+ assign T_1066 = 3'h1 == xact_a_type;
+ assign T_1067 = T_1066 ? 2'h2 : T_1065;
+ assign T_1068 = 1'h1 == xact_a_type;
+ assign T_1069 = T_1068 ? 1'h0 : 2'h2;
+ assign T_1070 = 1'h0 == xact_a_type;
+ assign T_1071 = T_1070 ? 1'h1 : T_1069;
+ assign T_1072 = xact_is_builtin_type ? T_1067 : T_1071;
+ assign T_1077_addr_block = xact_addr_block;
+ assign T_1077_p_type = T_1072;
+ assign T_1077_client_id = 1'h0;
+ assign T_1100 = 3'h6 == xact_a_type;
+ assign T_1101 = T_1100 ? 3'h1 : 3'h3;
+ assign T_1102 = 3'h5 == xact_a_type;
+ assign T_1103 = T_1102 ? 3'h1 : T_1101;
+ assign T_1104 = 3'h4 == xact_a_type;
+ assign T_1105 = T_1104 ? 3'h4 : T_1103;
+ assign T_1106 = 3'h3 == xact_a_type;
+ assign T_1107 = T_1106 ? 3'h3 : T_1105;
+ assign T_1108 = 3'h2 == xact_a_type;
+ assign T_1109 = T_1108 ? 3'h3 : T_1107;
+ assign T_1110 = 3'h1 == xact_a_type;
+ assign T_1111 = T_1110 ? 3'h5 : T_1109;
+ assign T_1112 = 3'h0 == xact_a_type;
+ assign T_1113 = T_1112 ? 3'h4 : T_1111;
+ assign T_1114 = xact_a_type == 1'h0;
+ assign T_1117 = 1'h0 == 1'h0;
+ assign T_1118 = T_1117 ? 1'h0 : 1'h1;
+ assign T_1119 = T_1114 ? T_1118 : 1'h1;
+ assign T_1120 = xact_is_builtin_type ? T_1113 : T_1119;
+ assign T_1129_addr_beat = 1'h0;
+ assign T_1129_client_xact_id = xact_client_xact_id;
+ assign T_1129_manager_xact_id = 3'h4;
+ assign T_1129_is_builtin_type = xact_is_builtin_type;
+ assign T_1129_g_type = T_1120;
+ assign T_1129_data = 1'h0;
+ assign T_1129_client_id = xact_client_id;
+ assign T_1140 = state != 1'h0;
+ assign T_1141 = T_1140 & collect_iacq_data;
+ assign T_1142 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_1143 = T_1141 & T_1142;
+ assign T_1144 = io_inner_acquire_bits_client_id != xact_client_id;
+ assign T_1145 = T_1143 & T_1144;
+ assign T_1147 = T_1145 == 1'h0;
+ assign T_1149 = reset == 1'h0;
+ assign T_1151 = T_1147 == 1'h0;
+ assign T_1153 = reset == 1'h0;
+ assign T_1154 = state != 1'h0;
+ assign T_1155 = T_1154 & collect_iacq_data;
+ assign T_1156 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_1157 = T_1155 & T_1156;
+ assign T_1158 = io_inner_acquire_bits_client_xact_id != xact_client_xact_id;
+ assign T_1159 = T_1157 & T_1158;
+ assign T_1161 = T_1159 == 1'h0;
+ assign T_1163 = reset == 1'h0;
+ assign T_1165 = T_1161 == 1'h0;
+ assign T_1167 = reset == 1'h0;
+ assign T_1168 = state == 1'h0;
+ assign T_1169 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_1170 = T_1168 & T_1169;
+ assign T_1172 = 1'h1 & io_inner_acquire_bits_is_builtin_type;
+ assign T_1175_0 = 3'h3;
+ assign T_1178 = T_1175_0 == io_inner_acquire_bits_a_type;
+ assign T_1180 = 1'h0 | T_1178;
+ assign T_1181 = T_1172 & T_1180;
+ assign T_1182 = T_1170 & T_1181;
+ assign T_1184 = io_inner_acquire_bits_addr_beat != 1'h0;
+ assign T_1185 = T_1182 & T_1184;
+ assign T_1187 = T_1185 == 1'h0;
+ assign T_1189 = reset == 1'h0;
+ assign T_1191 = T_1187 == 1'h0;
+ assign T_1193 = reset == 1'h0;
+ assign GEN_3 = io_inner_acquire_bits_data;
+ assign T_1197 = io_inner_acquire_bits_union[12:9];
+ assign T_1198 = T_1197[3];
+ assign T_1200 = 1'h1 << T_1198;
+ assign T_1202 = io_inner_acquire_bits_a_type == 3'h4;
+ assign T_1203 = io_inner_acquire_bits_is_builtin_type & T_1202;
+ assign T_1204 = T_1200[0];
+ assign T_1205 = T_1200[1];
+ assign T_1207_0 = T_1204;
+ assign T_1207_1 = T_1205;
+ assign T_1212 = 8'h0 - T_1207_0;
+ assign T_1213 = T_1212[7:0];
+ assign T_1215 = 8'h0 - T_1207_1;
+ assign T_1216 = T_1215[7:0];
+ assign T_1218_0 = T_1213;
+ assign T_1218_1 = T_1216;
+ assign T_1222 = {T_1218_1,T_1218_0};
+ assign T_1224 = io_inner_acquire_bits_a_type == 3'h3;
+ assign T_1225 = io_inner_acquire_bits_is_builtin_type & T_1224;
+ assign T_1227 = io_inner_acquire_bits_a_type == 3'h2;
+ assign T_1228 = io_inner_acquire_bits_is_builtin_type & T_1227;
+ assign T_1229 = T_1225 | T_1228;
+ assign T_1230 = io_inner_acquire_bits_union[16:1];
+ assign T_1232 = T_1229 ? T_1230 : 16'h0;
+ assign T_1233 = T_1203 ? T_1222 : T_1232;
+ assign GEN_4 = T_1233;
+ assign T_1236 = 1'h1 << io_inner_acquire_bits_addr_beat;
+ assign T_1237 = iacq_data_valid | T_1236;
+ assign T_1238 = ~ iacq_data_valid;
+ assign T_1239 = T_1238 | T_1236;
+ assign T_1240 = ~ T_1239;
+ assign T_1241 = 1'h1 ? T_1237 : T_1240;
+ assign T_1245 = 1'h0 == state;
+ assign GEN_5 = io_inner_acquire_bits_data;
+ assign T_1251 = io_inner_acquire_bits_union[12:9];
+ assign T_1252 = T_1251[3];
+ assign T_1254 = 1'h1 << T_1252;
+ assign T_1256 = io_inner_acquire_bits_a_type == 3'h4;
+ assign T_1257 = io_inner_acquire_bits_is_builtin_type & T_1256;
+ assign T_1258 = T_1254[0];
+ assign T_1259 = T_1254[1];
+ assign T_1261_0 = T_1258;
+ assign T_1261_1 = T_1259;
+ assign T_1266 = 8'h0 - T_1261_0;
+ assign T_1267 = T_1266[7:0];
+ assign T_1269 = 8'h0 - T_1261_1;
+ assign T_1270 = T_1269[7:0];
+ assign T_1272_0 = T_1267;
+ assign T_1272_1 = T_1270;
+ assign T_1276 = {T_1272_1,T_1272_0};
+ assign T_1278 = io_inner_acquire_bits_a_type == 3'h3;
+ assign T_1279 = io_inner_acquire_bits_is_builtin_type & T_1278;
+ assign T_1281 = io_inner_acquire_bits_a_type == 3'h2;
+ assign T_1282 = io_inner_acquire_bits_is_builtin_type & T_1281;
+ assign T_1283 = T_1279 | T_1282;
+ assign T_1284 = io_inner_acquire_bits_union[16:1];
+ assign T_1286 = T_1283 ? T_1284 : 16'h0;
+ assign T_1287 = T_1257 ? T_1276 : T_1286;
+ assign GEN_6 = T_1287;
+ assign T_1289 = 1'h1 & io_inner_acquire_bits_is_builtin_type;
+ assign T_1292_0 = 3'h3;
+ assign T_1295 = T_1292_0 == io_inner_acquire_bits_a_type;
+ assign T_1297 = 1'h0 | T_1295;
+ assign T_1298 = T_1289 & T_1297;
+ assign T_1303_0 = 3'h2;
+ assign T_1303_1 = 3'h3;
+ assign T_1303_2 = 3'h4;
+ assign T_1308 = T_1303_0 == io_inner_acquire_bits_a_type;
+ assign T_1309 = T_1303_1 == io_inner_acquire_bits_a_type;
+ assign T_1310 = T_1303_2 == io_inner_acquire_bits_a_type;
+ assign T_1312 = 1'h0 | T_1308;
+ assign T_1313 = T_1312 | T_1309;
+ assign T_1314 = T_1313 | T_1310;
+ assign T_1315 = io_inner_acquire_bits_is_builtin_type & T_1314;
+ assign T_1316 = T_1315 << io_inner_acquire_bits_addr_beat;
+ assign T_1318 = mask_incoherent != 1'h0;
+ assign T_1319 = mask_incoherent[0];
+ assign T_1320 = mask_incoherent[1];
+ assign T_1321 = mask_incoherent[2];
+ assign T_1322 = mask_incoherent[3];
+ assign T_1324 = {1'h0,T_1320};
+ assign T_1325 = T_1319 + T_1324;
+ assign T_1326 = T_1325[1:0];
+ assign T_1329 = {1'h0,T_1322};
+ assign T_1330 = T_1321 + T_1329;
+ assign T_1331 = T_1330[1:0];
+ assign T_1332 = {1'h0,T_1331};
+ assign T_1333 = T_1326 + T_1332;
+ assign T_1334 = T_1333[2:0];
+ assign T_1335 = pending_outer_read_ ? 2'h2 : 3'h4;
+ assign T_1336 = pending_outer_write_ ? 2'h3 : T_1335;
+ assign T_1337 = T_1318 ? 1'h1 : T_1336;
+ assign T_1338 = 1'h1 == state;
+ assign T_1340 = pending_probes != 1'h0;
+ assign T_1342 = 1'h1 << 1'h0;
+ assign T_1343 = ~ T_1342;
+ assign T_1344 = pending_probes & T_1343;
+ assign T_1346_0 = 1'h0;
+ assign T_1346_1 = 1'h1;
+ assign T_1346_2 = 2'h2;
+ assign T_1351 = T_1346_0 == io_inner_release_bits_r_type;
+ assign T_1352 = T_1346_1 == io_inner_release_bits_r_type;
+ assign T_1353 = T_1346_2 == io_inner_release_bits_r_type;
+ assign T_1355 = 1'h0 | T_1351;
+ assign T_1356 = T_1355 | T_1352;
+ assign T_1357 = T_1356 | T_1353;
+ assign T_1359 = T_1357 == 1'h0;
+ assign T_1360 = T_1359 | io_outer_acquire_ready;
+ assign T_1362_0 = 1'h0;
+ assign T_1362_1 = 1'h1;
+ assign T_1362_2 = 2'h2;
+ assign T_1367 = T_1362_0 == io_inner_release_bits_r_type;
+ assign T_1368 = T_1362_1 == io_inner_release_bits_r_type;
+ assign T_1369 = T_1362_2 == io_inner_release_bits_r_type;
+ assign T_1371 = 1'h0 | T_1367;
+ assign T_1372 = T_1371 | T_1368;
+ assign T_1373 = T_1372 | T_1369;
+ assign T_1377 = release_count - 1'h1;
+ assign T_1378 = T_1377[0:0];
+ assign T_1380 = release_count == 1'h1;
+ assign T_1381 = pending_outer_read ? 2'h2 : 3'h4;
+ assign T_1382 = pending_outer_write ? 2'h3 : T_1381;
+ assign T_1384 = T_1373 == 1'h0;
+ assign T_1386 = release_count - 1'h1;
+ assign T_1387 = T_1386[0:0];
+ assign T_1389 = release_count == 1'h1;
+ assign T_1390 = pending_outer_read ? 2'h2 : 3'h4;
+ assign T_1391 = pending_outer_write ? 2'h3 : T_1390;
+ assign T_1392 = 2'h3 == state;
+ assign T_1394 = pending_ognt_ack == 1'h0;
+ assign T_1396 = collect_iacq_data == 1'h0;
+ assign T_1397 = iacq_data_valid >> oacq_data_cnt;
+ assign T_1398 = T_1397[0];
+ assign T_1399 = T_1396 | T_1398;
+ assign T_1400 = T_1394 & T_1399;
+ assign T_1402 = pending_outer_read ? 2'h2 : 3'h5;
+ assign T_1403 = 2'h2 == state;
+ assign T_1405 = pending_ognt_ack == 1'h0;
+ assign T_1406 = io_outer_acquire_ready & io_outer_acquire_valid;
+ assign T_1407 = 3'h5 == state;
+ assign T_1410 = 1'h0 == 1'h0;
+ assign T_1412 = io_inner_grant_bits_g_type == 3'h0;
+ assign T_1413 = io_inner_grant_bits_is_builtin_type & T_1412;
+ assign T_1415 = T_1413 == 1'h0;
+ assign T_1416 = T_1410 & T_1415;
+ assign T_1417 = T_1416 ? 3'h6 : 1'h0;
+ assign T_1418 = 3'h4 == state;
+ assign T_1422 = 1'h0 == 1'h0;
+ assign T_1424 = io_inner_grant_bits_g_type == 3'h0;
+ assign T_1425 = io_inner_grant_bits_is_builtin_type & T_1424;
+ assign T_1427 = T_1425 == 1'h0;
+ assign T_1428 = T_1422 & T_1427;
+ assign T_1429 = T_1428 ? 3'h6 : 1'h0;
+ assign T_1430 = 3'h6 == state;
+ assign GEN_9 = T_325 & T_327;
+ assign GEN_10 = T_1149 & T_1151;
+ assign GEN_11 = T_1163 & T_1165;
+ assign GEN_12 = T_1189 & T_1191;
+ assign GEN_13 = 1'h0 == 1'h0;
+ assign GEN_14 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_15 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_16 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_17 = 1'h1 == 1'h0;
+ assign GEN_18 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_19 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_20 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_21 = 2'h2 == 1'h0;
+ assign GEN_22 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_23 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_24 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_25 = 2'h3 == 1'h0;
+ assign GEN_26 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_27 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_28 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_29 = 1'h0 == 1'h0;
+ assign GEN_30 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_31 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_32 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_33 = 1'h1 == 1'h0;
+ assign GEN_34 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_35 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_36 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_37 = 2'h2 == 1'h0;
+ assign GEN_38 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_39 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_40 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_41 = 2'h3 == 1'h0;
+ assign GEN_42 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_43 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_44 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_45 = 2'h3 == oacq_data_cnt;
+ assign GEN_46 = 2'h2 == oacq_data_cnt;
+ assign GEN_47 = 1'h1 == oacq_data_cnt;
+ assign GEN_48 = 2'h3 == oacq_data_cnt;
+ assign GEN_49 = 2'h2 == oacq_data_cnt;
+ assign GEN_50 = 1'h1 == oacq_data_cnt;
+ assign GEN_51 = 2'h3 == oacq_data_cnt;
+ assign GEN_52 = 2'h2 == oacq_data_cnt;
+ assign GEN_53 = 1'h1 == oacq_data_cnt;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ state = {1{$random}};
+ xact_addr_block = {1{$random}};
+ xact_client_xact_id = {1{$random}};
+ xact_addr_beat = {1{$random}};
+ xact_is_builtin_type = {1{$random}};
+ xact_a_type = {1{$random}};
+ xact_union = {1{$random}};
+ xact_data_buffer_0 = {1{$random}};
+ xact_data_buffer_1 = {1{$random}};
+ xact_data_buffer_2 = {1{$random}};
+ xact_data_buffer_3 = {1{$random}};
+ xact_wmask_buffer_0 = {1{$random}};
+ xact_wmask_buffer_1 = {1{$random}};
+ xact_wmask_buffer_2 = {1{$random}};
+ xact_wmask_buffer_3 = {1{$random}};
+ xact_client_id = {1{$random}};
+ release_count = {1{$random}};
+ pending_probes = {1{$random}};
+ collect_iacq_data = {1{$random}};
+ iacq_data_valid = {1{$random}};
+ T_371 = {1{$random}};
+ T_403 = {1{$random}};
+ T_441 = {1{$random}};
+ T_469 = {1{$random}};
+ T_504 = {1{$random}};
+ pending_ognt_ack = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1430) begin
+ if(io_inner_finish_valid) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1418) begin
+ if(io_inner_grant_ready) begin
+ state <= T_1429;
+ end else begin
+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
+ end else begin
+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end
+ end else begin
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+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end else begin
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+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
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+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
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+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
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+ end
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+ end
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+ state <= T_1402;
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ end else begin
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
+ end else begin
+ ;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ end else begin
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end
+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1418) begin
+ if(io_inner_grant_ready) begin
+ state <= T_1429;
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+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
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+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
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+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end
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+ end
+ end else begin
+ if(T_1392) begin
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+ state <= T_1402;
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ if(T_1380) begin
+ state <= T_1382;
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ end
+ end else begin
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
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+ end
+ end else begin
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+ if(T_1406) begin
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ state <= T_1337;
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+ end
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ state <= T_1337;
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+ end
+ end else begin
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
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+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
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+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1382;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_addr_block <= io_inner_acquire_bits_addr_block;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_client_xact_id <= io_inner_acquire_bits_client_xact_id;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_addr_beat <= io_inner_acquire_bits_addr_beat;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_is_builtin_type <= io_inner_acquire_bits_is_builtin_type;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_a_type <= io_inner_acquire_bits_a_type;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_union <= io_inner_acquire_bits_union;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_13) begin
+ xact_data_buffer_0 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_14) begin
+ xact_data_buffer_0 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_15) begin
+ xact_data_buffer_0 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_16) begin
+ xact_data_buffer_0 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_17) begin
+ xact_data_buffer_1 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_18) begin
+ xact_data_buffer_1 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_19) begin
+ xact_data_buffer_1 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_20) begin
+ xact_data_buffer_1 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_21) begin
+ xact_data_buffer_2 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_22) begin
+ xact_data_buffer_2 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_23) begin
+ xact_data_buffer_2 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_24) begin
+ xact_data_buffer_2 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_25) begin
+ xact_data_buffer_3 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_26) begin
+ xact_data_buffer_3 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_27) begin
+ xact_data_buffer_3 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_28) begin
+ xact_data_buffer_3 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_29) begin
+ xact_wmask_buffer_0 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_30) begin
+ xact_wmask_buffer_0 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_31) begin
+ xact_wmask_buffer_0 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_32) begin
+ xact_wmask_buffer_0 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_33) begin
+ xact_wmask_buffer_1 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_34) begin
+ xact_wmask_buffer_1 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_35) begin
+ xact_wmask_buffer_1 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_36) begin
+ xact_wmask_buffer_1 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_37) begin
+ xact_wmask_buffer_2 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_38) begin
+ xact_wmask_buffer_2 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_39) begin
+ xact_wmask_buffer_2 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_40) begin
+ xact_wmask_buffer_2 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_41) begin
+ xact_wmask_buffer_3 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_42) begin
+ xact_wmask_buffer_3 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_43) begin
+ xact_wmask_buffer_3 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_44) begin
+ xact_wmask_buffer_3 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_client_id <= io_inner_acquire_bits_client_id;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ release_count <= 1'h0;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ release_count <= T_1387;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ release_count <= T_1378;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ pending_probes <= 1'h0;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_probe_ready) begin
+ pending_probes <= T_1344;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ pending_probes <= mask_incoherent;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ pending_probes <= mask_incoherent;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ collect_iacq_data <= 1'h0;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ collect_iacq_data <= T_1298;
+ end else begin
+ if(collect_iacq_data) begin
+ if(iacq_data_done) begin
+ collect_iacq_data <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(iacq_data_done) begin
+ collect_iacq_data <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ iacq_data_valid <= 4'h0;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ iacq_data_valid <= T_1316;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ iacq_data_valid <= T_1241;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ iacq_data_valid <= T_1241;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ T_371 <= 2'h0;
+ end else begin
+ if(T_369) begin
+ T_371 <= T_380;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_403 <= 2'h0;
+ end else begin
+ if(T_401) begin
+ T_403 <= T_412;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_441 <= 2'h0;
+ end else begin
+ if(T_439) begin
+ T_441 <= T_450;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_469 <= 2'h0;
+ end else begin
+ if(T_467) begin
+ T_469 <= T_478;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_504 <= 2'h0;
+ end else begin
+ if(T_502) begin
+ T_504 <= T_513;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ pending_ognt_ack <= 1'h1;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ pending_ognt_ack <= 1'h1;
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ pending_ognt_ack <= 1'h1;
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ `ifndef SYNTHESIS
+ if(GEN_9 & T_329) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_325 & T_327) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_10 & T_1153) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_1149 & T_1151) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_11 & T_1167) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_1163 & T_1165) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_12 & T_1193) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_1189 & T_1191) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ end
+endmodule
+module BroadcastAcquireTracker_30(
+ input clk,
+ input reset,
+ output io_inner_acquire_ready,
+ input io_inner_acquire_valid,
+ input [25:0] io_inner_acquire_bits_addr_block,
+ input [1:0] io_inner_acquire_bits_client_xact_id,
+ input [1:0] io_inner_acquire_bits_addr_beat,
+ input io_inner_acquire_bits_is_builtin_type,
+ input [2:0] io_inner_acquire_bits_a_type,
+ input [16:0] io_inner_acquire_bits_union,
+ input [3:0] io_inner_acquire_bits_data,
+ input [1:0] io_inner_acquire_bits_client_id,
+ input io_inner_grant_ready,
+ output io_inner_grant_valid,
+ output [1:0] io_inner_grant_bits_addr_beat,
+ output [1:0] io_inner_grant_bits_client_xact_id,
+ output [3:0] io_inner_grant_bits_manager_xact_id,
+ output io_inner_grant_bits_is_builtin_type,
+ output [3:0] io_inner_grant_bits_g_type,
+ output [3:0] io_inner_grant_bits_data,
+ output [1:0] io_inner_grant_bits_client_id,
+ output io_inner_finish_ready,
+ input io_inner_finish_valid,
+ input [3:0] io_inner_finish_bits_manager_xact_id,
+ input io_inner_probe_ready,
+ output io_inner_probe_valid,
+ output [25:0] io_inner_probe_bits_addr_block,
+ output [1:0] io_inner_probe_bits_p_type,
+ output [1:0] io_inner_probe_bits_client_id,
+ output io_inner_release_ready,
+ input io_inner_release_valid,
+ input [1:0] io_inner_release_bits_addr_beat,
+ input [25:0] io_inner_release_bits_addr_block,
+ input [1:0] io_inner_release_bits_client_xact_id,
+ input io_inner_release_bits_voluntary,
+ input [2:0] io_inner_release_bits_r_type,
+ input [3:0] io_inner_release_bits_data,
+ input [1:0] io_inner_release_bits_client_id,
+ input io_incoherent_0,
+ input io_outer_acquire_ready,
+ output io_outer_acquire_valid,
+ output [25:0] io_outer_acquire_bits_addr_block,
+ output [3:0] io_outer_acquire_bits_client_xact_id,
+ output [1:0] io_outer_acquire_bits_addr_beat,
+ output io_outer_acquire_bits_is_builtin_type,
+ output [2:0] io_outer_acquire_bits_a_type,
+ output [16:0] io_outer_acquire_bits_union,
+ output [3:0] io_outer_acquire_bits_data,
+ output io_outer_grant_ready,
+ input io_outer_grant_valid,
+ input [1:0] io_outer_grant_bits_addr_beat,
+ input [3:0] io_outer_grant_bits_client_xact_id,
+ input io_outer_grant_bits_manager_xact_id,
+ input io_outer_grant_bits_is_builtin_type,
+ input [3:0] io_outer_grant_bits_g_type,
+ input [3:0] io_outer_grant_bits_data,
+ output io_has_acquire_conflict,
+ output io_has_acquire_match,
+ output io_has_release_match
+);
+ reg [2:0] state;
+ reg [25:0] xact_addr_block;
+ reg [1:0] xact_client_xact_id;
+ reg [1:0] xact_addr_beat;
+ reg xact_is_builtin_type;
+ reg [2:0] xact_a_type;
+ reg [16:0] xact_union;
+ reg [3:0] xact_data_buffer_0;
+ reg [3:0] xact_data_buffer_1;
+ reg [3:0] xact_data_buffer_2;
+ reg [3:0] xact_data_buffer_3;
+ reg [15:0] xact_wmask_buffer_0;
+ reg [15:0] xact_wmask_buffer_1;
+ reg [15:0] xact_wmask_buffer_2;
+ reg [15:0] xact_wmask_buffer_3;
+ reg [1:0] xact_client_id;
+ wire coh_sharers;
+ wire T_303;
+ wire T_304;
+ wire [2:0] T_309_0;
+ wire [2:0] T_309_1;
+ wire [2:0] T_309_2;
+ wire T_314;
+ wire T_315;
+ wire T_316;
+ wire T_318;
+ wire T_319;
+ wire T_320;
+ wire T_321;
+ wire T_323;
+ wire T_325;
+ wire T_327;
+ wire T_329;
+ reg release_count;
+ reg pending_probes;
+ wire T_334;
+ wire T_336_0;
+ wire GEN_7;
+ wire T_341;
+ wire [3:0] T_344;
+ wire [3:0] T_345;
+ wire T_346;
+ wire [3:0] T_347;
+ wire [3:0] T_348;
+ wire [3:0] mask_self;
+ wire T_350;
+ wire [3:0] mask_incoherent;
+ reg collect_iacq_data;
+ reg [3:0] iacq_data_valid;
+ wire T_356;
+ wire T_359;
+ wire [2:0] T_362_0;
+ wire T_365;
+ wire T_367;
+ wire T_368;
+ wire T_369;
+ reg [1:0] T_371;
+ wire T_373;
+ wire T_375;
+ wire [2:0] T_378;
+ wire [1:0] T_379;
+ wire [1:0] T_380;
+ wire T_381;
+ wire [1:0] T_382;
+ wire iacq_data_done;
+ wire T_384;
+ wire [1:0] T_388_0;
+ wire [1:0] T_388_1;
+ wire [1:0] T_388_2;
+ wire T_393;
+ wire T_394;
+ wire T_395;
+ wire T_397;
+ wire T_398;
+ wire T_399;
+ wire T_400;
+ wire T_401;
+ reg [1:0] T_403;
+ wire T_405;
+ wire T_407;
+ wire [2:0] T_410;
+ wire [1:0] T_411;
+ wire [1:0] T_412;
+ wire T_413;
+ wire [1:0] T_414;
+ wire irel_data_done;
+ wire T_417;
+ wire [2:0] T_421_0;
+ wire T_424;
+ wire T_426;
+ wire T_428_0;
+ wire T_428_1;
+ wire T_432;
+ wire T_433;
+ wire T_435;
+ wire T_436;
+ wire T_437;
+ wire T_438;
+ wire T_439;
+ reg [1:0] T_441;
+ wire T_443;
+ wire T_445;
+ wire [2:0] T_448;
+ wire [1:0] T_449;
+ wire [1:0] T_450;
+ wire T_451;
+ wire [1:0] ignt_data_cnt;
+ wire ignt_data_done;
+ wire T_455;
+ wire T_457;
+ wire [2:0] T_460_0;
+ wire T_463;
+ wire T_465;
+ wire T_466;
+ wire T_467;
+ reg [1:0] T_469;
+ wire T_471;
+ wire T_473;
+ wire [2:0] T_476;
+ wire [1:0] T_477;
+ wire [1:0] T_478;
+ wire T_479;
+ wire [1:0] oacq_data_cnt;
+ wire oacq_data_done;
+ wire T_482;
+ wire [2:0] T_487_0;
+ wire T_490;
+ wire T_492;
+ wire T_494_0;
+ wire T_497;
+ wire T_499;
+ wire T_500;
+ wire T_501;
+ wire T_502;
+ reg [1:0] T_504;
+ wire T_506;
+ wire T_508;
+ wire [2:0] T_511;
+ wire [1:0] T_512;
+ wire [1:0] T_513;
+ wire T_514;
+ wire [1:0] T_515;
+ wire ognt_data_done;
+ reg pending_ognt_ack;
+ wire [2:0] T_523_0;
+ wire [2:0] T_523_1;
+ wire [2:0] T_523_2;
+ wire T_528;
+ wire T_529;
+ wire T_530;
+ wire T_532;
+ wire T_533;
+ wire T_534;
+ wire pending_outer_write;
+ wire [2:0] T_540_0;
+ wire [2:0] T_540_1;
+ wire [2:0] T_540_2;
+ wire T_545;
+ wire T_546;
+ wire T_547;
+ wire T_549;
+ wire T_550;
+ wire T_551;
+ wire pending_outer_write_;
+ wire [2:0] T_556_0;
+ wire [2:0] T_556_1;
+ wire T_560;
+ wire T_561;
+ wire T_563;
+ wire T_564;
+ wire T_566_0;
+ wire T_566_1;
+ wire T_570;
+ wire T_571;
+ wire T_573;
+ wire T_574;
+ wire pending_outer_read;
+ wire T_594;
+ wire [2:0] T_595;
+ wire T_596;
+ wire [2:0] T_597;
+ wire T_598;
+ wire [2:0] T_599;
+ wire T_600;
+ wire [2:0] T_601;
+ wire T_602;
+ wire [2:0] T_603;
+ wire T_604;
+ wire [2:0] T_605;
+ wire T_606;
+ wire [2:0] T_607;
+ wire T_608;
+ wire T_611;
+ wire T_612;
+ wire T_613;
+ wire [2:0] T_614;
+ wire [1:0] T_623_addr_beat;
+ wire [1:0] T_623_client_xact_id;
+ wire [3:0] T_623_manager_xact_id;
+ wire T_623_is_builtin_type;
+ wire [3:0] T_623_g_type;
+ wire [3:0] T_623_data;
+ wire [1:0] T_623_client_id;
+ wire [2:0] T_634_0;
+ wire [2:0] T_634_1;
+ wire T_638;
+ wire T_639;
+ wire T_641;
+ wire T_642;
+ wire T_644_0;
+ wire T_644_1;
+ wire T_648;
+ wire T_649;
+ wire T_651;
+ wire T_652;
+ wire pending_outer_read_;
+ wire [2:0] T_658_0;
+ wire [2:0] T_658_1;
+ wire [2:0] T_658_2;
+ wire T_663;
+ wire T_664;
+ wire T_665;
+ wire T_667;
+ wire T_668;
+ wire T_669;
+ wire subblock_type;
+ wire T_671;
+ wire T_672;
+ wire T_673;
+ wire T_675;
+ wire T_676;
+ wire T_677;
+ wire T_678;
+ wire T_679;
+ wire T_681;
+ wire T_682;
+ wire T_683;
+ wire T_684;
+ wire [15:0] GEN_8;
+ wire [15:0] T_689;
+ wire [3:0] T_695;
+ wire [1:0] T_696;
+ wire [5:0] T_697;
+ wire [1:0] T_699;
+ wire [4:0] T_700;
+ wire [16:0] T_702;
+ wire [16:0] T_704;
+ wire [3:0] T_706;
+ wire [1:0] T_707;
+ wire [5:0] T_708;
+ wire [5:0] T_710;
+ wire [5:0] T_712;
+ wire T_713;
+ wire [5:0] T_714;
+ wire T_715;
+ wire [5:0] T_716;
+ wire T_717;
+ wire [5:0] T_718;
+ wire T_719;
+ wire [16:0] T_720;
+ wire T_721;
+ wire [16:0] T_722;
+ wire T_723;
+ wire [16:0] T_724;
+ wire T_725;
+ wire [16:0] T_726;
+ wire [25:0] oacq_probe_addr_block;
+ wire [3:0] oacq_probe_client_xact_id;
+ wire [1:0] oacq_probe_addr_beat;
+ wire oacq_probe_is_builtin_type;
+ wire [2:0] oacq_probe_a_type;
+ wire [16:0] oacq_probe_union;
+ wire [3:0] oacq_probe_data;
+ wire [3:0] T_744;
+ wire T_745;
+ wire [1:0] T_747;
+ wire T_749;
+ wire T_750;
+ wire T_751;
+ wire T_752;
+ wire T_754_0;
+ wire T_754_1;
+ wire [8:0] T_759;
+ wire [7:0] T_760;
+ wire [8:0] T_762;
+ wire [7:0] T_763;
+ wire [7:0] T_765_0;
+ wire [7:0] T_765_1;
+ wire [15:0] T_769;
+ wire T_771;
+ wire T_772;
+ wire T_774;
+ wire T_775;
+ wire T_776;
+ wire [15:0] T_777;
+ wire [15:0] T_779;
+ wire [15:0] T_780;
+ wire [3:0] T_788;
+ wire [1:0] T_789;
+ wire [5:0] T_790;
+ wire [1:0] T_792;
+ wire [4:0] T_793;
+ wire [16:0] T_795;
+ wire [16:0] T_797;
+ wire [3:0] T_799;
+ wire [1:0] T_800;
+ wire [5:0] T_801;
+ wire [5:0] T_803;
+ wire [5:0] T_805;
+ wire T_806;
+ wire [5:0] T_807;
+ wire T_808;
+ wire [5:0] T_809;
+ wire T_810;
+ wire [5:0] T_811;
+ wire T_812;
+ wire [16:0] T_813;
+ wire T_814;
+ wire [16:0] T_815;
+ wire T_816;
+ wire [16:0] T_817;
+ wire T_818;
+ wire [16:0] T_819;
+ wire [25:0] oacq_write_beat_addr_block;
+ wire [3:0] oacq_write_beat_client_xact_id;
+ wire [1:0] oacq_write_beat_addr_beat;
+ wire oacq_write_beat_is_builtin_type;
+ wire [2:0] oacq_write_beat_a_type;
+ wire [16:0] oacq_write_beat_union;
+ wire [3:0] oacq_write_beat_data;
+ wire [3:0] T_846;
+ wire [1:0] T_847;
+ wire [5:0] T_848;
+ wire [1:0] T_850;
+ wire [4:0] T_851;
+ wire [15:0] GEN_0;
+ wire [16:0] T_853;
+ wire [15:0] GEN_1;
+ wire [16:0] T_855;
+ wire [3:0] T_857;
+ wire [1:0] T_858;
+ wire [5:0] T_859;
+ wire [5:0] T_861;
+ wire [5:0] T_863;
+ wire T_864;
+ wire [5:0] T_865;
+ wire T_866;
+ wire [5:0] T_867;
+ wire T_868;
+ wire [5:0] T_869;
+ wire T_870;
+ wire [16:0] T_871;
+ wire T_872;
+ wire [16:0] T_873;
+ wire T_874;
+ wire [16:0] T_875;
+ wire T_876;
+ wire [16:0] T_877;
+ wire [25:0] oacq_write_block_addr_block;
+ wire [3:0] oacq_write_block_client_xact_id;
+ wire [1:0] oacq_write_block_addr_beat;
+ wire oacq_write_block_is_builtin_type;
+ wire [2:0] oacq_write_block_a_type;
+ wire [16:0] oacq_write_block_union;
+ wire [3:0] oacq_write_block_data;
+ wire [3:0] GEN_2;
+ wire [3:0] T_895;
+ wire [2:0] T_896;
+ wire [6:0] T_904;
+ wire [5:0] T_905;
+ wire [12:0] T_906;
+ wire [5:0] T_908;
+ wire [8:0] T_909;
+ wire [1:0] T_911;
+ wire [1:0] T_913;
+ wire [6:0] T_915;
+ wire [5:0] T_916;
+ wire [12:0] T_917;
+ wire [5:0] T_919;
+ wire [5:0] T_921;
+ wire T_922;
+ wire [5:0] T_923;
+ wire T_924;
+ wire [5:0] T_925;
+ wire T_926;
+ wire [12:0] T_927;
+ wire T_928;
+ wire [12:0] T_929;
+ wire T_930;
+ wire [12:0] T_931;
+ wire T_932;
+ wire [12:0] T_933;
+ wire T_934;
+ wire [12:0] T_935;
+ wire [25:0] oacq_read_beat_addr_block;
+ wire [3:0] oacq_read_beat_client_xact_id;
+ wire [1:0] oacq_read_beat_addr_beat;
+ wire oacq_read_beat_is_builtin_type;
+ wire [2:0] oacq_read_beat_a_type;
+ wire [16:0] oacq_read_beat_union;
+ wire [3:0] oacq_read_beat_data;
+ wire [3:0] T_962;
+ wire [5:0] T_963;
+ wire [9:0] T_964;
+ wire [5:0] T_966;
+ wire [8:0] T_967;
+ wire [1:0] T_969;
+ wire [1:0] T_971;
+ wire [3:0] T_973;
+ wire [5:0] T_974;
+ wire [9:0] T_975;
+ wire [5:0] T_977;
+ wire [5:0] T_979;
+ wire T_980;
+ wire [5:0] T_981;
+ wire T_982;
+ wire [5:0] T_983;
+ wire T_984;
+ wire [9:0] T_985;
+ wire T_986;
+ wire [9:0] T_987;
+ wire T_988;
+ wire [9:0] T_989;
+ wire T_990;
+ wire [9:0] T_991;
+ wire T_992;
+ wire [9:0] T_993;
+ wire [25:0] oacq_read_block_addr_block;
+ wire [3:0] oacq_read_block_client_xact_id;
+ wire [1:0] oacq_read_block_addr_beat;
+ wire oacq_read_block_is_builtin_type;
+ wire [2:0] oacq_read_block_a_type;
+ wire [16:0] oacq_read_block_union;
+ wire [3:0] oacq_read_block_data;
+ wire T_1011;
+ wire T_1012;
+ wire [25:0] T_1013_addr_block;
+ wire [3:0] T_1013_client_xact_id;
+ wire [1:0] T_1013_addr_beat;
+ wire T_1013_is_builtin_type;
+ wire [2:0] T_1013_a_type;
+ wire [16:0] T_1013_union;
+ wire [3:0] T_1013_data;
+ wire [25:0] T_1021_addr_block;
+ wire [3:0] T_1021_client_xact_id;
+ wire [1:0] T_1021_addr_beat;
+ wire T_1021_is_builtin_type;
+ wire [2:0] T_1021_a_type;
+ wire [16:0] T_1021_union;
+ wire [3:0] T_1021_data;
+ wire [25:0] T_1029_addr_block;
+ wire [3:0] T_1029_client_xact_id;
+ wire [1:0] T_1029_addr_beat;
+ wire T_1029_is_builtin_type;
+ wire [2:0] T_1029_a_type;
+ wire [16:0] T_1029_union;
+ wire [3:0] T_1029_data;
+ wire [25:0] T_1037_addr_block;
+ wire [3:0] T_1037_client_xact_id;
+ wire [1:0] T_1037_addr_beat;
+ wire T_1037_is_builtin_type;
+ wire [2:0] T_1037_a_type;
+ wire [16:0] T_1037_union;
+ wire [3:0] T_1037_data;
+ wire T_1054;
+ wire [1:0] T_1055;
+ wire T_1056;
+ wire [1:0] T_1057;
+ wire T_1058;
+ wire [1:0] T_1059;
+ wire T_1060;
+ wire [1:0] T_1061;
+ wire T_1062;
+ wire [1:0] T_1063;
+ wire T_1064;
+ wire [1:0] T_1065;
+ wire T_1066;
+ wire [1:0] T_1067;
+ wire T_1068;
+ wire [1:0] T_1069;
+ wire T_1070;
+ wire [1:0] T_1071;
+ wire [1:0] T_1072;
+ wire [25:0] T_1077_addr_block;
+ wire [1:0] T_1077_p_type;
+ wire [1:0] T_1077_client_id;
+ wire T_1100;
+ wire [2:0] T_1101;
+ wire T_1102;
+ wire [2:0] T_1103;
+ wire T_1104;
+ wire [2:0] T_1105;
+ wire T_1106;
+ wire [2:0] T_1107;
+ wire T_1108;
+ wire [2:0] T_1109;
+ wire T_1110;
+ wire [2:0] T_1111;
+ wire T_1112;
+ wire [2:0] T_1113;
+ wire T_1114;
+ wire T_1117;
+ wire T_1118;
+ wire T_1119;
+ wire [2:0] T_1120;
+ wire [1:0] T_1129_addr_beat;
+ wire [1:0] T_1129_client_xact_id;
+ wire [3:0] T_1129_manager_xact_id;
+ wire T_1129_is_builtin_type;
+ wire [3:0] T_1129_g_type;
+ wire [3:0] T_1129_data;
+ wire [1:0] T_1129_client_id;
+ wire T_1140;
+ wire T_1141;
+ wire T_1142;
+ wire T_1143;
+ wire T_1144;
+ wire T_1145;
+ wire T_1147;
+ wire T_1149;
+ wire T_1151;
+ wire T_1153;
+ wire T_1154;
+ wire T_1155;
+ wire T_1156;
+ wire T_1157;
+ wire T_1158;
+ wire T_1159;
+ wire T_1161;
+ wire T_1163;
+ wire T_1165;
+ wire T_1167;
+ wire T_1168;
+ wire T_1169;
+ wire T_1170;
+ wire T_1172;
+ wire [2:0] T_1175_0;
+ wire T_1178;
+ wire T_1180;
+ wire T_1181;
+ wire T_1182;
+ wire T_1184;
+ wire T_1185;
+ wire T_1187;
+ wire T_1189;
+ wire T_1191;
+ wire T_1193;
+ wire [3:0] GEN_3;
+ wire [3:0] T_1197;
+ wire T_1198;
+ wire [1:0] T_1200;
+ wire T_1202;
+ wire T_1203;
+ wire T_1204;
+ wire T_1205;
+ wire T_1207_0;
+ wire T_1207_1;
+ wire [8:0] T_1212;
+ wire [7:0] T_1213;
+ wire [8:0] T_1215;
+ wire [7:0] T_1216;
+ wire [7:0] T_1218_0;
+ wire [7:0] T_1218_1;
+ wire [15:0] T_1222;
+ wire T_1224;
+ wire T_1225;
+ wire T_1227;
+ wire T_1228;
+ wire T_1229;
+ wire [15:0] T_1230;
+ wire [15:0] T_1232;
+ wire [15:0] T_1233;
+ wire [15:0] GEN_4;
+ wire [3:0] T_1236;
+ wire [3:0] T_1237;
+ wire [3:0] T_1238;
+ wire [3:0] T_1239;
+ wire [3:0] T_1240;
+ wire [3:0] T_1241;
+ wire T_1245;
+ wire [3:0] GEN_5;
+ wire [3:0] T_1251;
+ wire T_1252;
+ wire [1:0] T_1254;
+ wire T_1256;
+ wire T_1257;
+ wire T_1258;
+ wire T_1259;
+ wire T_1261_0;
+ wire T_1261_1;
+ wire [8:0] T_1266;
+ wire [7:0] T_1267;
+ wire [8:0] T_1269;
+ wire [7:0] T_1270;
+ wire [7:0] T_1272_0;
+ wire [7:0] T_1272_1;
+ wire [15:0] T_1276;
+ wire T_1278;
+ wire T_1279;
+ wire T_1281;
+ wire T_1282;
+ wire T_1283;
+ wire [15:0] T_1284;
+ wire [15:0] T_1286;
+ wire [15:0] T_1287;
+ wire [15:0] GEN_6;
+ wire T_1289;
+ wire [2:0] T_1292_0;
+ wire T_1295;
+ wire T_1297;
+ wire T_1298;
+ wire [2:0] T_1303_0;
+ wire [2:0] T_1303_1;
+ wire [2:0] T_1303_2;
+ wire T_1308;
+ wire T_1309;
+ wire T_1310;
+ wire T_1312;
+ wire T_1313;
+ wire T_1314;
+ wire T_1315;
+ wire [3:0] T_1316;
+ wire T_1318;
+ wire T_1319;
+ wire T_1320;
+ wire T_1321;
+ wire T_1322;
+ wire [1:0] T_1324;
+ wire [2:0] T_1325;
+ wire [1:0] T_1326;
+ wire [1:0] T_1329;
+ wire [2:0] T_1330;
+ wire [1:0] T_1331;
+ wire [2:0] T_1332;
+ wire [3:0] T_1333;
+ wire [2:0] T_1334;
+ wire [2:0] T_1335;
+ wire [2:0] T_1336;
+ wire [2:0] T_1337;
+ wire T_1338;
+ wire T_1340;
+ wire [1:0] T_1342;
+ wire [1:0] T_1343;
+ wire [1:0] T_1344;
+ wire [1:0] T_1346_0;
+ wire [1:0] T_1346_1;
+ wire [1:0] T_1346_2;
+ wire T_1351;
+ wire T_1352;
+ wire T_1353;
+ wire T_1355;
+ wire T_1356;
+ wire T_1357;
+ wire T_1359;
+ wire T_1360;
+ wire [1:0] T_1362_0;
+ wire [1:0] T_1362_1;
+ wire [1:0] T_1362_2;
+ wire T_1367;
+ wire T_1368;
+ wire T_1369;
+ wire T_1371;
+ wire T_1372;
+ wire T_1373;
+ wire [1:0] T_1377;
+ wire T_1378;
+ wire T_1380;
+ wire [2:0] T_1381;
+ wire [2:0] T_1382;
+ wire T_1384;
+ wire [1:0] T_1386;
+ wire T_1387;
+ wire T_1389;
+ wire [2:0] T_1390;
+ wire [2:0] T_1391;
+ wire T_1392;
+ wire T_1394;
+ wire T_1396;
+ wire [3:0] T_1397;
+ wire T_1398;
+ wire T_1399;
+ wire T_1400;
+ wire [2:0] T_1402;
+ wire T_1403;
+ wire T_1405;
+ wire T_1406;
+ wire T_1407;
+ wire T_1410;
+ wire T_1412;
+ wire T_1413;
+ wire T_1415;
+ wire T_1416;
+ wire [2:0] T_1417;
+ wire T_1418;
+ wire T_1422;
+ wire T_1424;
+ wire T_1425;
+ wire T_1427;
+ wire T_1428;
+ wire [2:0] T_1429;
+ wire T_1430;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ wire GEN_17;
+ wire GEN_18;
+ wire GEN_19;
+ wire GEN_20;
+ wire GEN_21;
+ wire GEN_22;
+ wire GEN_23;
+ wire GEN_24;
+ wire GEN_25;
+ wire GEN_26;
+ wire GEN_27;
+ wire GEN_28;
+ wire GEN_29;
+ wire GEN_30;
+ wire GEN_31;
+ wire GEN_32;
+ wire GEN_33;
+ wire GEN_34;
+ wire GEN_35;
+ wire GEN_36;
+ wire GEN_37;
+ wire GEN_38;
+ wire GEN_39;
+ wire GEN_40;
+ wire GEN_41;
+ wire GEN_42;
+ wire GEN_43;
+ wire GEN_44;
+ wire GEN_45;
+ wire GEN_46;
+ wire GEN_47;
+ wire GEN_48;
+ wire GEN_49;
+ wire GEN_50;
+ wire GEN_51;
+ wire GEN_52;
+ wire GEN_53;
+ assign io_inner_acquire_ready = T_1245 ? 1'h1 : collect_iacq_data ? 1'h1 : 1'h0;
+ assign io_inner_grant_valid = T_1418 ? 1'h1 : T_1407 ? io_outer_grant_valid : 1'h0;
+ assign io_inner_grant_bits_addr_beat = T_1129_addr_beat;
+ assign io_inner_grant_bits_client_xact_id = T_1129_client_xact_id;
+ assign io_inner_grant_bits_manager_xact_id = T_1129_manager_xact_id;
+ assign io_inner_grant_bits_is_builtin_type = T_1129_is_builtin_type;
+ assign io_inner_grant_bits_g_type = T_1129_g_type;
+ assign io_inner_grant_bits_data = T_1129_data;
+ assign io_inner_grant_bits_client_id = T_1129_client_id;
+ assign io_inner_finish_ready = T_1430 ? 1'h1 : 1'h0;
+ assign io_inner_probe_valid = T_1338 ? T_1340 : 1'h0;
+ assign io_inner_probe_bits_addr_block = T_1077_addr_block;
+ assign io_inner_probe_bits_p_type = T_1077_p_type;
+ assign io_inner_probe_bits_client_id = T_1077_client_id;
+ assign io_inner_release_ready = T_1338 ? T_1360 : 1'h0;
+ assign io_outer_acquire_valid = T_1403 ? T_1405 : T_1392 ? T_1400 : T_1338 ? io_inner_release_valid ? T_1373 ? 1'h1 : 1'h0 : 1'h0 : 1'h0;
+ assign io_outer_acquire_bits_addr_block = T_1037_addr_block;
+ assign io_outer_acquire_bits_client_xact_id = T_1037_client_xact_id;
+ assign io_outer_acquire_bits_addr_beat = T_1037_addr_beat;
+ assign io_outer_acquire_bits_is_builtin_type = T_1037_is_builtin_type;
+ assign io_outer_acquire_bits_a_type = T_1037_a_type;
+ assign io_outer_acquire_bits_union = T_1037_union;
+ assign io_outer_acquire_bits_data = T_1037_data;
+ assign io_outer_grant_ready = T_1407 ? io_inner_grant_ready : pending_ognt_ack ? 1'h1 : 1'h0;
+ assign io_has_acquire_conflict = T_676;
+ assign io_has_acquire_match = T_678;
+ assign io_has_release_match = T_684;
+ assign coh_sharers = 1'h0;
+ assign T_303 = state != 1'h0;
+ assign T_304 = T_303 & xact_is_builtin_type;
+ assign T_309_0 = 3'h4;
+ assign T_309_1 = 3'h5;
+ assign T_309_2 = 3'h6;
+ assign T_314 = T_309_0 == xact_a_type;
+ assign T_315 = T_309_1 == xact_a_type;
+ assign T_316 = T_309_2 == xact_a_type;
+ assign T_318 = 1'h0 | T_314;
+ assign T_319 = T_318 | T_315;
+ assign T_320 = T_319 | T_316;
+ assign T_321 = T_304 & T_320;
+ assign T_323 = T_321 == 1'h0;
+ assign T_325 = reset == 1'h0;
+ assign T_327 = T_323 == 1'h0;
+ assign T_329 = reset == 1'h0;
+ assign T_334 = pending_probes;
+ assign T_336_0 = T_334;
+ assign GEN_7 = $signed(1'h1);
+ assign T_341 = $unsigned(GEN_7);
+ assign T_344 = 1'h1 << io_inner_acquire_bits_client_id;
+ assign T_345 = T_341 | T_344;
+ assign T_346 = ~ T_341;
+ assign T_347 = T_346 | T_344;
+ assign T_348 = ~ T_347;
+ assign mask_self = 1'h0 ? T_345 : T_348;
+ assign T_350 = ~ io_incoherent_0;
+ assign mask_incoherent = mask_self & T_350;
+ assign T_356 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_359 = 1'h1 & io_inner_acquire_bits_is_builtin_type;
+ assign T_362_0 = 3'h3;
+ assign T_365 = T_362_0 == io_inner_acquire_bits_a_type;
+ assign T_367 = 1'h0 | T_365;
+ assign T_368 = T_359 & T_367;
+ assign T_369 = T_356 & T_368;
+ assign T_373 = T_371 == 2'h3;
+ assign T_375 = 1'h0 & T_373;
+ assign T_378 = T_371 + 1'h1;
+ assign T_379 = T_378[1:0];
+ assign T_380 = T_375 ? 1'h0 : T_379;
+ assign T_381 = T_369 & T_373;
+ assign T_382 = T_368 ? T_371 : 1'h0;
+ assign iacq_data_done = T_368 ? T_381 : T_356;
+ assign T_384 = io_inner_release_ready & io_inner_release_valid;
+ assign T_388_0 = 1'h0;
+ assign T_388_1 = 1'h1;
+ assign T_388_2 = 2'h2;
+ assign T_393 = T_388_0 == io_inner_release_bits_r_type;
+ assign T_394 = T_388_1 == io_inner_release_bits_r_type;
+ assign T_395 = T_388_2 == io_inner_release_bits_r_type;
+ assign T_397 = 1'h0 | T_393;
+ assign T_398 = T_397 | T_394;
+ assign T_399 = T_398 | T_395;
+ assign T_400 = 1'h1 & T_399;
+ assign T_401 = T_384 & T_400;
+ assign T_405 = T_403 == 2'h3;
+ assign T_407 = 1'h0 & T_405;
+ assign T_410 = T_403 + 1'h1;
+ assign T_411 = T_410[1:0];
+ assign T_412 = T_407 ? 1'h0 : T_411;
+ assign T_413 = T_401 & T_405;
+ assign T_414 = T_400 ? T_403 : 1'h0;
+ assign irel_data_done = T_400 ? T_413 : T_384;
+ assign T_417 = io_inner_grant_ready & io_inner_grant_valid;
+ assign T_421_0 = 3'h5;
+ assign T_424 = T_421_0 == io_inner_grant_bits_g_type;
+ assign T_426 = 1'h0 | T_424;
+ assign T_428_0 = 1'h0;
+ assign T_428_1 = 1'h1;
+ assign T_432 = T_428_0 == io_inner_grant_bits_g_type;
+ assign T_433 = T_428_1 == io_inner_grant_bits_g_type;
+ assign T_435 = 1'h0 | T_432;
+ assign T_436 = T_435 | T_433;
+ assign T_437 = io_inner_grant_bits_is_builtin_type ? T_426 : T_436;
+ assign T_438 = 1'h1 & T_437;
+ assign T_439 = T_417 & T_438;
+ assign T_443 = T_441 == 2'h3;
+ assign T_445 = 1'h0 & T_443;
+ assign T_448 = T_441 + 1'h1;
+ assign T_449 = T_448[1:0];
+ assign T_450 = T_445 ? 1'h0 : T_449;
+ assign T_451 = T_439 & T_443;
+ assign ignt_data_cnt = T_438 ? T_441 : 1'h0;
+ assign ignt_data_done = T_438 ? T_451 : T_417;
+ assign T_455 = io_outer_acquire_ready & io_outer_acquire_valid;
+ assign T_457 = 1'h1 & io_outer_acquire_bits_is_builtin_type;
+ assign T_460_0 = 3'h3;
+ assign T_463 = T_460_0 == io_outer_acquire_bits_a_type;
+ assign T_465 = 1'h0 | T_463;
+ assign T_466 = T_457 & T_465;
+ assign T_467 = T_455 & T_466;
+ assign T_471 = T_469 == 2'h3;
+ assign T_473 = 1'h0 & T_471;
+ assign T_476 = T_469 + 1'h1;
+ assign T_477 = T_476[1:0];
+ assign T_478 = T_473 ? 1'h0 : T_477;
+ assign T_479 = T_467 & T_471;
+ assign oacq_data_cnt = T_466 ? T_469 : 1'h0;
+ assign oacq_data_done = T_466 ? T_479 : T_455;
+ assign T_482 = io_outer_grant_ready & io_outer_grant_valid;
+ assign T_487_0 = 3'h5;
+ assign T_490 = T_487_0 == io_outer_grant_bits_g_type;
+ assign T_492 = 1'h0 | T_490;
+ assign T_494_0 = 1'h0;
+ assign T_497 = T_494_0 == io_outer_grant_bits_g_type;
+ assign T_499 = 1'h0 | T_497;
+ assign T_500 = io_outer_grant_bits_is_builtin_type ? T_492 : T_499;
+ assign T_501 = 1'h1 & T_500;
+ assign T_502 = T_482 & T_501;
+ assign T_506 = T_504 == 2'h3;
+ assign T_508 = 1'h0 & T_506;
+ assign T_511 = T_504 + 1'h1;
+ assign T_512 = T_511[1:0];
+ assign T_513 = T_508 ? 1'h0 : T_512;
+ assign T_514 = T_502 & T_506;
+ assign T_515 = T_501 ? T_504 : 1'h0;
+ assign ognt_data_done = T_501 ? T_514 : T_482;
+ assign T_523_0 = 3'h2;
+ assign T_523_1 = 3'h3;
+ assign T_523_2 = 3'h4;
+ assign T_528 = T_523_0 == xact_a_type;
+ assign T_529 = T_523_1 == xact_a_type;
+ assign T_530 = T_523_2 == xact_a_type;
+ assign T_532 = 1'h0 | T_528;
+ assign T_533 = T_532 | T_529;
+ assign T_534 = T_533 | T_530;
+ assign pending_outer_write = xact_is_builtin_type & T_534;
+ assign T_540_0 = 3'h2;
+ assign T_540_1 = 3'h3;
+ assign T_540_2 = 3'h4;
+ assign T_545 = T_540_0 == io_inner_acquire_bits_a_type;
+ assign T_546 = T_540_1 == io_inner_acquire_bits_a_type;
+ assign T_547 = T_540_2 == io_inner_acquire_bits_a_type;
+ assign T_549 = 1'h0 | T_545;
+ assign T_550 = T_549 | T_546;
+ assign T_551 = T_550 | T_547;
+ assign pending_outer_write_ = io_inner_acquire_bits_is_builtin_type & T_551;
+ assign T_556_0 = 3'h5;
+ assign T_556_1 = 3'h4;
+ assign T_560 = T_556_0 == io_inner_grant_bits_g_type;
+ assign T_561 = T_556_1 == io_inner_grant_bits_g_type;
+ assign T_563 = 1'h0 | T_560;
+ assign T_564 = T_563 | T_561;
+ assign T_566_0 = 1'h0;
+ assign T_566_1 = 1'h1;
+ assign T_570 = T_566_0 == io_inner_grant_bits_g_type;
+ assign T_571 = T_566_1 == io_inner_grant_bits_g_type;
+ assign T_573 = 1'h0 | T_570;
+ assign T_574 = T_573 | T_571;
+ assign pending_outer_read = io_inner_grant_bits_is_builtin_type ? T_564 : T_574;
+ assign T_594 = 3'h6 == io_inner_acquire_bits_a_type;
+ assign T_595 = T_594 ? 3'h1 : 3'h3;
+ assign T_596 = 3'h5 == io_inner_acquire_bits_a_type;
+ assign T_597 = T_596 ? 3'h1 : T_595;
+ assign T_598 = 3'h4 == io_inner_acquire_bits_a_type;
+ assign T_599 = T_598 ? 3'h4 : T_597;
+ assign T_600 = 3'h3 == io_inner_acquire_bits_a_type;
+ assign T_601 = T_600 ? 3'h3 : T_599;
+ assign T_602 = 3'h2 == io_inner_acquire_bits_a_type;
+ assign T_603 = T_602 ? 3'h3 : T_601;
+ assign T_604 = 3'h1 == io_inner_acquire_bits_a_type;
+ assign T_605 = T_604 ? 3'h5 : T_603;
+ assign T_606 = 3'h0 == io_inner_acquire_bits_a_type;
+ assign T_607 = T_606 ? 3'h4 : T_605;
+ assign T_608 = io_inner_acquire_bits_a_type == 1'h0;
+ assign T_611 = 1'h0 == 1'h0;
+ assign T_612 = T_611 ? 1'h0 : 1'h1;
+ assign T_613 = T_608 ? T_612 : 1'h1;
+ assign T_614 = io_inner_acquire_bits_is_builtin_type ? T_607 : T_613;
+ assign T_623_addr_beat = 1'h0;
+ assign T_623_client_xact_id = io_inner_acquire_bits_client_xact_id;
+ assign T_623_manager_xact_id = 3'h5;
+ assign T_623_is_builtin_type = io_inner_acquire_bits_is_builtin_type;
+ assign T_623_g_type = T_614;
+ assign T_623_data = 1'h0;
+ assign T_623_client_id = io_inner_acquire_bits_client_id;
+ assign T_634_0 = 3'h5;
+ assign T_634_1 = 3'h4;
+ assign T_638 = T_634_0 == T_623_g_type;
+ assign T_639 = T_634_1 == T_623_g_type;
+ assign T_641 = 1'h0 | T_638;
+ assign T_642 = T_641 | T_639;
+ assign T_644_0 = 1'h0;
+ assign T_644_1 = 1'h1;
+ assign T_648 = T_644_0 == T_623_g_type;
+ assign T_649 = T_644_1 == T_623_g_type;
+ assign T_651 = 1'h0 | T_648;
+ assign T_652 = T_651 | T_649;
+ assign pending_outer_read_ = T_623_is_builtin_type ? T_642 : T_652;
+ assign T_658_0 = 3'h2;
+ assign T_658_1 = 3'h0;
+ assign T_658_2 = 3'h4;
+ assign T_663 = T_658_0 == xact_a_type;
+ assign T_664 = T_658_1 == xact_a_type;
+ assign T_665 = T_658_2 == xact_a_type;
+ assign T_667 = 1'h0 | T_663;
+ assign T_668 = T_667 | T_664;
+ assign T_669 = T_668 | T_665;
+ assign subblock_type = xact_is_builtin_type & T_669;
+ assign T_671 = xact_addr_block == io_inner_acquire_bits_addr_block;
+ assign T_672 = state != 1'h0;
+ assign T_673 = T_671 & T_672;
+ assign T_675 = collect_iacq_data == 1'h0;
+ assign T_676 = T_673 & T_675;
+ assign T_677 = xact_addr_block == io_inner_acquire_bits_addr_block;
+ assign T_678 = T_677 & collect_iacq_data;
+ assign T_679 = xact_addr_block == io_inner_release_bits_addr_block;
+ assign T_681 = io_inner_release_bits_voluntary == 1'h0;
+ assign T_682 = T_679 & T_681;
+ assign T_683 = state == 1'h1;
+ assign T_684 = T_682 & T_683;
+ assign GEN_8 = $signed(16'hffff);
+ assign T_689 = $unsigned(GEN_8);
+ assign T_695 = {1'h0,3'h7};
+ assign T_696 = {1'h0,1'h1};
+ assign T_697 = {T_695,T_696};
+ assign T_699 = {1'h0,1'h1};
+ assign T_700 = {3'h7,T_699};
+ assign T_702 = {T_689,1'h1};
+ assign T_704 = {T_689,1'h1};
+ assign T_706 = {1'h0,3'h7};
+ assign T_707 = {1'h0,1'h1};
+ assign T_708 = {T_706,T_707};
+ assign T_710 = {5'h0,1'h1};
+ assign T_712 = {5'h1,1'h1};
+ assign T_713 = 3'h6 == 3'h3;
+ assign T_714 = T_713 ? T_712 : 1'h0;
+ assign T_715 = 3'h5 == 3'h3;
+ assign T_716 = T_715 ? T_710 : T_714;
+ assign T_717 = 3'h4 == 3'h3;
+ assign T_718 = T_717 ? T_708 : T_716;
+ assign T_719 = 3'h3 == 3'h3;
+ assign T_720 = T_719 ? T_704 : T_718;
+ assign T_721 = 3'h2 == 3'h3;
+ assign T_722 = T_721 ? T_702 : T_720;
+ assign T_723 = 3'h1 == 3'h3;
+ assign T_724 = T_723 ? T_700 : T_722;
+ assign T_725 = 3'h0 == 3'h3;
+ assign T_726 = T_725 ? T_697 : T_724;
+ assign oacq_probe_addr_block = io_inner_release_bits_addr_block;
+ assign oacq_probe_client_xact_id = 3'h5;
+ assign oacq_probe_addr_beat = io_inner_release_bits_addr_beat;
+ assign oacq_probe_is_builtin_type = 1'h1;
+ assign oacq_probe_a_type = 3'h3;
+ assign oacq_probe_union = T_726;
+ assign oacq_probe_data = io_inner_release_bits_data;
+ assign T_744 = xact_union[12:9];
+ assign T_745 = T_744[3];
+ assign T_747 = 1'h1 << T_745;
+ assign T_749 = xact_a_type == 3'h4;
+ assign T_750 = xact_is_builtin_type & T_749;
+ assign T_751 = T_747[0];
+ assign T_752 = T_747[1];
+ assign T_754_0 = T_751;
+ assign T_754_1 = T_752;
+ assign T_759 = 8'h0 - T_754_0;
+ assign T_760 = T_759[7:0];
+ assign T_762 = 8'h0 - T_754_1;
+ assign T_763 = T_762[7:0];
+ assign T_765_0 = T_760;
+ assign T_765_1 = T_763;
+ assign T_769 = {T_765_1,T_765_0};
+ assign T_771 = xact_a_type == 3'h3;
+ assign T_772 = xact_is_builtin_type & T_771;
+ assign T_774 = xact_a_type == 3'h2;
+ assign T_775 = xact_is_builtin_type & T_774;
+ assign T_776 = T_772 | T_775;
+ assign T_777 = xact_union[16:1];
+ assign T_779 = T_776 ? T_777 : 16'h0;
+ assign T_780 = T_750 ? T_769 : T_779;
+ assign T_788 = {1'h0,3'h7};
+ assign T_789 = {1'h0,1'h1};
+ assign T_790 = {T_788,T_789};
+ assign T_792 = {1'h0,1'h1};
+ assign T_793 = {3'h7,T_792};
+ assign T_795 = {T_780,1'h1};
+ assign T_797 = {T_780,1'h1};
+ assign T_799 = {1'h0,3'h7};
+ assign T_800 = {1'h0,1'h1};
+ assign T_801 = {T_799,T_800};
+ assign T_803 = {5'h0,1'h1};
+ assign T_805 = {5'h1,1'h1};
+ assign T_806 = 3'h6 == 3'h2;
+ assign T_807 = T_806 ? T_805 : 1'h0;
+ assign T_808 = 3'h5 == 3'h2;
+ assign T_809 = T_808 ? T_803 : T_807;
+ assign T_810 = 3'h4 == 3'h2;
+ assign T_811 = T_810 ? T_801 : T_809;
+ assign T_812 = 3'h3 == 3'h2;
+ assign T_813 = T_812 ? T_797 : T_811;
+ assign T_814 = 3'h2 == 3'h2;
+ assign T_815 = T_814 ? T_795 : T_813;
+ assign T_816 = 3'h1 == 3'h2;
+ assign T_817 = T_816 ? T_793 : T_815;
+ assign T_818 = 3'h0 == 3'h2;
+ assign T_819 = T_818 ? T_790 : T_817;
+ assign oacq_write_beat_addr_block = xact_addr_block;
+ assign oacq_write_beat_client_xact_id = 3'h5;
+ assign oacq_write_beat_addr_beat = xact_addr_beat;
+ assign oacq_write_beat_is_builtin_type = 1'h1;
+ assign oacq_write_beat_a_type = 3'h2;
+ assign oacq_write_beat_union = T_819;
+ assign oacq_write_beat_data = xact_data_buffer_0;
+ assign T_846 = {1'h0,3'h7};
+ assign T_847 = {1'h0,1'h1};
+ assign T_848 = {T_846,T_847};
+ assign T_850 = {1'h0,1'h1};
+ assign T_851 = {3'h7,T_850};
+ assign GEN_0 = GEN_45 ? xact_wmask_buffer_3 : GEN_46 ? xact_wmask_buffer_2 : GEN_47 ? xact_wmask_buffer_1 : xact_wmask_buffer_0;
+ assign T_853 = {GEN_0,1'h1};
+ assign GEN_1 = GEN_48 ? xact_wmask_buffer_3 : GEN_49 ? xact_wmask_buffer_2 : GEN_50 ? xact_wmask_buffer_1 : xact_wmask_buffer_0;
+ assign T_855 = {GEN_1,1'h1};
+ assign T_857 = {1'h0,3'h7};
+ assign T_858 = {1'h0,1'h1};
+ assign T_859 = {T_857,T_858};
+ assign T_861 = {5'h0,1'h1};
+ assign T_863 = {5'h1,1'h1};
+ assign T_864 = 3'h6 == 3'h3;
+ assign T_865 = T_864 ? T_863 : 1'h0;
+ assign T_866 = 3'h5 == 3'h3;
+ assign T_867 = T_866 ? T_861 : T_865;
+ assign T_868 = 3'h4 == 3'h3;
+ assign T_869 = T_868 ? T_859 : T_867;
+ assign T_870 = 3'h3 == 3'h3;
+ assign T_871 = T_870 ? T_855 : T_869;
+ assign T_872 = 3'h2 == 3'h3;
+ assign T_873 = T_872 ? T_853 : T_871;
+ assign T_874 = 3'h1 == 3'h3;
+ assign T_875 = T_874 ? T_851 : T_873;
+ assign T_876 = 3'h0 == 3'h3;
+ assign T_877 = T_876 ? T_848 : T_875;
+ assign oacq_write_block_addr_block = xact_addr_block;
+ assign oacq_write_block_client_xact_id = 3'h5;
+ assign oacq_write_block_addr_beat = oacq_data_cnt;
+ assign oacq_write_block_is_builtin_type = 1'h1;
+ assign oacq_write_block_a_type = 3'h3;
+ assign oacq_write_block_union = T_877;
+ assign oacq_write_block_data = GEN_2;
+ assign GEN_2 = GEN_51 ? xact_data_buffer_3 : GEN_52 ? xact_data_buffer_2 : GEN_53 ? xact_data_buffer_1 : xact_data_buffer_0;
+ assign T_895 = xact_union[12:9];
+ assign T_896 = xact_union[8:6];
+ assign T_904 = {T_895,T_896};
+ assign T_905 = {5'h0,1'h0};
+ assign T_906 = {T_904,T_905};
+ assign T_908 = {5'h0,1'h0};
+ assign T_909 = {T_896,T_908};
+ assign T_911 = {1'h0,1'h0};
+ assign T_913 = {1'h0,1'h0};
+ assign T_915 = {T_895,T_896};
+ assign T_916 = {5'h0,1'h0};
+ assign T_917 = {T_915,T_916};
+ assign T_919 = {5'h0,1'h0};
+ assign T_921 = {5'h1,1'h0};
+ assign T_922 = 3'h6 == 3'h0;
+ assign T_923 = T_922 ? T_921 : 1'h0;
+ assign T_924 = 3'h5 == 3'h0;
+ assign T_925 = T_924 ? T_919 : T_923;
+ assign T_926 = 3'h4 == 3'h0;
+ assign T_927 = T_926 ? T_917 : T_925;
+ assign T_928 = 3'h3 == 3'h0;
+ assign T_929 = T_928 ? T_913 : T_927;
+ assign T_930 = 3'h2 == 3'h0;
+ assign T_931 = T_930 ? T_911 : T_929;
+ assign T_932 = 3'h1 == 3'h0;
+ assign T_933 = T_932 ? T_909 : T_931;
+ assign T_934 = 3'h0 == 3'h0;
+ assign T_935 = T_934 ? T_906 : T_933;
+ assign oacq_read_beat_addr_block = xact_addr_block;
+ assign oacq_read_beat_client_xact_id = 3'h5;
+ assign oacq_read_beat_addr_beat = xact_addr_beat;
+ assign oacq_read_beat_is_builtin_type = 1'h1;
+ assign oacq_read_beat_a_type = 3'h0;
+ assign oacq_read_beat_union = T_935;
+ assign oacq_read_beat_data = 1'h0;
+ assign T_962 = {1'h0,3'h7};
+ assign T_963 = {5'h0,1'h1};
+ assign T_964 = {T_962,T_963};
+ assign T_966 = {5'h0,1'h1};
+ assign T_967 = {3'h7,T_966};
+ assign T_969 = {1'h0,1'h1};
+ assign T_971 = {1'h0,1'h1};
+ assign T_973 = {1'h0,3'h7};
+ assign T_974 = {5'h0,1'h1};
+ assign T_975 = {T_973,T_974};
+ assign T_977 = {5'h0,1'h1};
+ assign T_979 = {5'h1,1'h1};
+ assign T_980 = 3'h6 == 3'h1;
+ assign T_981 = T_980 ? T_979 : 1'h0;
+ assign T_982 = 3'h5 == 3'h1;
+ assign T_983 = T_982 ? T_977 : T_981;
+ assign T_984 = 3'h4 == 3'h1;
+ assign T_985 = T_984 ? T_975 : T_983;
+ assign T_986 = 3'h3 == 3'h1;
+ assign T_987 = T_986 ? T_971 : T_985;
+ assign T_988 = 3'h2 == 3'h1;
+ assign T_989 = T_988 ? T_969 : T_987;
+ assign T_990 = 3'h1 == 3'h1;
+ assign T_991 = T_990 ? T_967 : T_989;
+ assign T_992 = 3'h0 == 3'h1;
+ assign T_993 = T_992 ? T_964 : T_991;
+ assign oacq_read_block_addr_block = xact_addr_block;
+ assign oacq_read_block_client_xact_id = 3'h5;
+ assign oacq_read_block_addr_beat = 1'h0;
+ assign oacq_read_block_is_builtin_type = 1'h1;
+ assign oacq_read_block_a_type = 3'h1;
+ assign oacq_read_block_union = T_993;
+ assign oacq_read_block_data = 1'h0;
+ assign T_1011 = state == 1'h1;
+ assign T_1012 = state == 2'h3;
+ assign T_1013_addr_block = subblock_type ? oacq_write_beat_addr_block : oacq_write_block_addr_block;
+ assign T_1013_client_xact_id = subblock_type ? oacq_write_beat_client_xact_id : oacq_write_block_client_xact_id;
+ assign T_1013_addr_beat = subblock_type ? oacq_write_beat_addr_beat : oacq_write_block_addr_beat;
+ assign T_1013_is_builtin_type = subblock_type ? oacq_write_beat_is_builtin_type : oacq_write_block_is_builtin_type;
+ assign T_1013_a_type = subblock_type ? oacq_write_beat_a_type : oacq_write_block_a_type;
+ assign T_1013_union = subblock_type ? oacq_write_beat_union : oacq_write_block_union;
+ assign T_1013_data = subblock_type ? oacq_write_beat_data : oacq_write_block_data;
+ assign T_1021_addr_block = subblock_type ? oacq_read_beat_addr_block : oacq_read_block_addr_block;
+ assign T_1021_client_xact_id = subblock_type ? oacq_read_beat_client_xact_id : oacq_read_block_client_xact_id;
+ assign T_1021_addr_beat = subblock_type ? oacq_read_beat_addr_beat : oacq_read_block_addr_beat;
+ assign T_1021_is_builtin_type = subblock_type ? oacq_read_beat_is_builtin_type : oacq_read_block_is_builtin_type;
+ assign T_1021_a_type = subblock_type ? oacq_read_beat_a_type : oacq_read_block_a_type;
+ assign T_1021_union = subblock_type ? oacq_read_beat_union : oacq_read_block_union;
+ assign T_1021_data = subblock_type ? oacq_read_beat_data : oacq_read_block_data;
+ assign T_1029_addr_block = T_1012 ? T_1013_addr_block : T_1021_addr_block;
+ assign T_1029_client_xact_id = T_1012 ? T_1013_client_xact_id : T_1021_client_xact_id;
+ assign T_1029_addr_beat = T_1012 ? T_1013_addr_beat : T_1021_addr_beat;
+ assign T_1029_is_builtin_type = T_1012 ? T_1013_is_builtin_type : T_1021_is_builtin_type;
+ assign T_1029_a_type = T_1012 ? T_1013_a_type : T_1021_a_type;
+ assign T_1029_union = T_1012 ? T_1013_union : T_1021_union;
+ assign T_1029_data = T_1012 ? T_1013_data : T_1021_data;
+ assign T_1037_addr_block = T_1011 ? oacq_probe_addr_block : T_1029_addr_block;
+ assign T_1037_client_xact_id = T_1011 ? oacq_probe_client_xact_id : T_1029_client_xact_id;
+ assign T_1037_addr_beat = T_1011 ? oacq_probe_addr_beat : T_1029_addr_beat;
+ assign T_1037_is_builtin_type = T_1011 ? oacq_probe_is_builtin_type : T_1029_is_builtin_type;
+ assign T_1037_a_type = T_1011 ? oacq_probe_a_type : T_1029_a_type;
+ assign T_1037_union = T_1011 ? oacq_probe_union : T_1029_union;
+ assign T_1037_data = T_1011 ? oacq_probe_data : T_1029_data;
+ assign T_1054 = 3'h4 == xact_a_type;
+ assign T_1055 = T_1054 ? 1'h0 : 2'h2;
+ assign T_1056 = 3'h6 == xact_a_type;
+ assign T_1057 = T_1056 ? 1'h0 : T_1055;
+ assign T_1058 = 3'h5 == xact_a_type;
+ assign T_1059 = T_1058 ? 2'h2 : T_1057;
+ assign T_1060 = 3'h2 == xact_a_type;
+ assign T_1061 = T_1060 ? 1'h0 : T_1059;
+ assign T_1062 = 3'h0 == xact_a_type;
+ assign T_1063 = T_1062 ? 2'h2 : T_1061;
+ assign T_1064 = 3'h3 == xact_a_type;
+ assign T_1065 = T_1064 ? 1'h0 : T_1063;
+ assign T_1066 = 3'h1 == xact_a_type;
+ assign T_1067 = T_1066 ? 2'h2 : T_1065;
+ assign T_1068 = 1'h1 == xact_a_type;
+ assign T_1069 = T_1068 ? 1'h0 : 2'h2;
+ assign T_1070 = 1'h0 == xact_a_type;
+ assign T_1071 = T_1070 ? 1'h1 : T_1069;
+ assign T_1072 = xact_is_builtin_type ? T_1067 : T_1071;
+ assign T_1077_addr_block = xact_addr_block;
+ assign T_1077_p_type = T_1072;
+ assign T_1077_client_id = 1'h0;
+ assign T_1100 = 3'h6 == xact_a_type;
+ assign T_1101 = T_1100 ? 3'h1 : 3'h3;
+ assign T_1102 = 3'h5 == xact_a_type;
+ assign T_1103 = T_1102 ? 3'h1 : T_1101;
+ assign T_1104 = 3'h4 == xact_a_type;
+ assign T_1105 = T_1104 ? 3'h4 : T_1103;
+ assign T_1106 = 3'h3 == xact_a_type;
+ assign T_1107 = T_1106 ? 3'h3 : T_1105;
+ assign T_1108 = 3'h2 == xact_a_type;
+ assign T_1109 = T_1108 ? 3'h3 : T_1107;
+ assign T_1110 = 3'h1 == xact_a_type;
+ assign T_1111 = T_1110 ? 3'h5 : T_1109;
+ assign T_1112 = 3'h0 == xact_a_type;
+ assign T_1113 = T_1112 ? 3'h4 : T_1111;
+ assign T_1114 = xact_a_type == 1'h0;
+ assign T_1117 = 1'h0 == 1'h0;
+ assign T_1118 = T_1117 ? 1'h0 : 1'h1;
+ assign T_1119 = T_1114 ? T_1118 : 1'h1;
+ assign T_1120 = xact_is_builtin_type ? T_1113 : T_1119;
+ assign T_1129_addr_beat = 1'h0;
+ assign T_1129_client_xact_id = xact_client_xact_id;
+ assign T_1129_manager_xact_id = 3'h5;
+ assign T_1129_is_builtin_type = xact_is_builtin_type;
+ assign T_1129_g_type = T_1120;
+ assign T_1129_data = 1'h0;
+ assign T_1129_client_id = xact_client_id;
+ assign T_1140 = state != 1'h0;
+ assign T_1141 = T_1140 & collect_iacq_data;
+ assign T_1142 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_1143 = T_1141 & T_1142;
+ assign T_1144 = io_inner_acquire_bits_client_id != xact_client_id;
+ assign T_1145 = T_1143 & T_1144;
+ assign T_1147 = T_1145 == 1'h0;
+ assign T_1149 = reset == 1'h0;
+ assign T_1151 = T_1147 == 1'h0;
+ assign T_1153 = reset == 1'h0;
+ assign T_1154 = state != 1'h0;
+ assign T_1155 = T_1154 & collect_iacq_data;
+ assign T_1156 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_1157 = T_1155 & T_1156;
+ assign T_1158 = io_inner_acquire_bits_client_xact_id != xact_client_xact_id;
+ assign T_1159 = T_1157 & T_1158;
+ assign T_1161 = T_1159 == 1'h0;
+ assign T_1163 = reset == 1'h0;
+ assign T_1165 = T_1161 == 1'h0;
+ assign T_1167 = reset == 1'h0;
+ assign T_1168 = state == 1'h0;
+ assign T_1169 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_1170 = T_1168 & T_1169;
+ assign T_1172 = 1'h1 & io_inner_acquire_bits_is_builtin_type;
+ assign T_1175_0 = 3'h3;
+ assign T_1178 = T_1175_0 == io_inner_acquire_bits_a_type;
+ assign T_1180 = 1'h0 | T_1178;
+ assign T_1181 = T_1172 & T_1180;
+ assign T_1182 = T_1170 & T_1181;
+ assign T_1184 = io_inner_acquire_bits_addr_beat != 1'h0;
+ assign T_1185 = T_1182 & T_1184;
+ assign T_1187 = T_1185 == 1'h0;
+ assign T_1189 = reset == 1'h0;
+ assign T_1191 = T_1187 == 1'h0;
+ assign T_1193 = reset == 1'h0;
+ assign GEN_3 = io_inner_acquire_bits_data;
+ assign T_1197 = io_inner_acquire_bits_union[12:9];
+ assign T_1198 = T_1197[3];
+ assign T_1200 = 1'h1 << T_1198;
+ assign T_1202 = io_inner_acquire_bits_a_type == 3'h4;
+ assign T_1203 = io_inner_acquire_bits_is_builtin_type & T_1202;
+ assign T_1204 = T_1200[0];
+ assign T_1205 = T_1200[1];
+ assign T_1207_0 = T_1204;
+ assign T_1207_1 = T_1205;
+ assign T_1212 = 8'h0 - T_1207_0;
+ assign T_1213 = T_1212[7:0];
+ assign T_1215 = 8'h0 - T_1207_1;
+ assign T_1216 = T_1215[7:0];
+ assign T_1218_0 = T_1213;
+ assign T_1218_1 = T_1216;
+ assign T_1222 = {T_1218_1,T_1218_0};
+ assign T_1224 = io_inner_acquire_bits_a_type == 3'h3;
+ assign T_1225 = io_inner_acquire_bits_is_builtin_type & T_1224;
+ assign T_1227 = io_inner_acquire_bits_a_type == 3'h2;
+ assign T_1228 = io_inner_acquire_bits_is_builtin_type & T_1227;
+ assign T_1229 = T_1225 | T_1228;
+ assign T_1230 = io_inner_acquire_bits_union[16:1];
+ assign T_1232 = T_1229 ? T_1230 : 16'h0;
+ assign T_1233 = T_1203 ? T_1222 : T_1232;
+ assign GEN_4 = T_1233;
+ assign T_1236 = 1'h1 << io_inner_acquire_bits_addr_beat;
+ assign T_1237 = iacq_data_valid | T_1236;
+ assign T_1238 = ~ iacq_data_valid;
+ assign T_1239 = T_1238 | T_1236;
+ assign T_1240 = ~ T_1239;
+ assign T_1241 = 1'h1 ? T_1237 : T_1240;
+ assign T_1245 = 1'h0 == state;
+ assign GEN_5 = io_inner_acquire_bits_data;
+ assign T_1251 = io_inner_acquire_bits_union[12:9];
+ assign T_1252 = T_1251[3];
+ assign T_1254 = 1'h1 << T_1252;
+ assign T_1256 = io_inner_acquire_bits_a_type == 3'h4;
+ assign T_1257 = io_inner_acquire_bits_is_builtin_type & T_1256;
+ assign T_1258 = T_1254[0];
+ assign T_1259 = T_1254[1];
+ assign T_1261_0 = T_1258;
+ assign T_1261_1 = T_1259;
+ assign T_1266 = 8'h0 - T_1261_0;
+ assign T_1267 = T_1266[7:0];
+ assign T_1269 = 8'h0 - T_1261_1;
+ assign T_1270 = T_1269[7:0];
+ assign T_1272_0 = T_1267;
+ assign T_1272_1 = T_1270;
+ assign T_1276 = {T_1272_1,T_1272_0};
+ assign T_1278 = io_inner_acquire_bits_a_type == 3'h3;
+ assign T_1279 = io_inner_acquire_bits_is_builtin_type & T_1278;
+ assign T_1281 = io_inner_acquire_bits_a_type == 3'h2;
+ assign T_1282 = io_inner_acquire_bits_is_builtin_type & T_1281;
+ assign T_1283 = T_1279 | T_1282;
+ assign T_1284 = io_inner_acquire_bits_union[16:1];
+ assign T_1286 = T_1283 ? T_1284 : 16'h0;
+ assign T_1287 = T_1257 ? T_1276 : T_1286;
+ assign GEN_6 = T_1287;
+ assign T_1289 = 1'h1 & io_inner_acquire_bits_is_builtin_type;
+ assign T_1292_0 = 3'h3;
+ assign T_1295 = T_1292_0 == io_inner_acquire_bits_a_type;
+ assign T_1297 = 1'h0 | T_1295;
+ assign T_1298 = T_1289 & T_1297;
+ assign T_1303_0 = 3'h2;
+ assign T_1303_1 = 3'h3;
+ assign T_1303_2 = 3'h4;
+ assign T_1308 = T_1303_0 == io_inner_acquire_bits_a_type;
+ assign T_1309 = T_1303_1 == io_inner_acquire_bits_a_type;
+ assign T_1310 = T_1303_2 == io_inner_acquire_bits_a_type;
+ assign T_1312 = 1'h0 | T_1308;
+ assign T_1313 = T_1312 | T_1309;
+ assign T_1314 = T_1313 | T_1310;
+ assign T_1315 = io_inner_acquire_bits_is_builtin_type & T_1314;
+ assign T_1316 = T_1315 << io_inner_acquire_bits_addr_beat;
+ assign T_1318 = mask_incoherent != 1'h0;
+ assign T_1319 = mask_incoherent[0];
+ assign T_1320 = mask_incoherent[1];
+ assign T_1321 = mask_incoherent[2];
+ assign T_1322 = mask_incoherent[3];
+ assign T_1324 = {1'h0,T_1320};
+ assign T_1325 = T_1319 + T_1324;
+ assign T_1326 = T_1325[1:0];
+ assign T_1329 = {1'h0,T_1322};
+ assign T_1330 = T_1321 + T_1329;
+ assign T_1331 = T_1330[1:0];
+ assign T_1332 = {1'h0,T_1331};
+ assign T_1333 = T_1326 + T_1332;
+ assign T_1334 = T_1333[2:0];
+ assign T_1335 = pending_outer_read_ ? 2'h2 : 3'h4;
+ assign T_1336 = pending_outer_write_ ? 2'h3 : T_1335;
+ assign T_1337 = T_1318 ? 1'h1 : T_1336;
+ assign T_1338 = 1'h1 == state;
+ assign T_1340 = pending_probes != 1'h0;
+ assign T_1342 = 1'h1 << 1'h0;
+ assign T_1343 = ~ T_1342;
+ assign T_1344 = pending_probes & T_1343;
+ assign T_1346_0 = 1'h0;
+ assign T_1346_1 = 1'h1;
+ assign T_1346_2 = 2'h2;
+ assign T_1351 = T_1346_0 == io_inner_release_bits_r_type;
+ assign T_1352 = T_1346_1 == io_inner_release_bits_r_type;
+ assign T_1353 = T_1346_2 == io_inner_release_bits_r_type;
+ assign T_1355 = 1'h0 | T_1351;
+ assign T_1356 = T_1355 | T_1352;
+ assign T_1357 = T_1356 | T_1353;
+ assign T_1359 = T_1357 == 1'h0;
+ assign T_1360 = T_1359 | io_outer_acquire_ready;
+ assign T_1362_0 = 1'h0;
+ assign T_1362_1 = 1'h1;
+ assign T_1362_2 = 2'h2;
+ assign T_1367 = T_1362_0 == io_inner_release_bits_r_type;
+ assign T_1368 = T_1362_1 == io_inner_release_bits_r_type;
+ assign T_1369 = T_1362_2 == io_inner_release_bits_r_type;
+ assign T_1371 = 1'h0 | T_1367;
+ assign T_1372 = T_1371 | T_1368;
+ assign T_1373 = T_1372 | T_1369;
+ assign T_1377 = release_count - 1'h1;
+ assign T_1378 = T_1377[0:0];
+ assign T_1380 = release_count == 1'h1;
+ assign T_1381 = pending_outer_read ? 2'h2 : 3'h4;
+ assign T_1382 = pending_outer_write ? 2'h3 : T_1381;
+ assign T_1384 = T_1373 == 1'h0;
+ assign T_1386 = release_count - 1'h1;
+ assign T_1387 = T_1386[0:0];
+ assign T_1389 = release_count == 1'h1;
+ assign T_1390 = pending_outer_read ? 2'h2 : 3'h4;
+ assign T_1391 = pending_outer_write ? 2'h3 : T_1390;
+ assign T_1392 = 2'h3 == state;
+ assign T_1394 = pending_ognt_ack == 1'h0;
+ assign T_1396 = collect_iacq_data == 1'h0;
+ assign T_1397 = iacq_data_valid >> oacq_data_cnt;
+ assign T_1398 = T_1397[0];
+ assign T_1399 = T_1396 | T_1398;
+ assign T_1400 = T_1394 & T_1399;
+ assign T_1402 = pending_outer_read ? 2'h2 : 3'h5;
+ assign T_1403 = 2'h2 == state;
+ assign T_1405 = pending_ognt_ack == 1'h0;
+ assign T_1406 = io_outer_acquire_ready & io_outer_acquire_valid;
+ assign T_1407 = 3'h5 == state;
+ assign T_1410 = 1'h0 == 1'h0;
+ assign T_1412 = io_inner_grant_bits_g_type == 3'h0;
+ assign T_1413 = io_inner_grant_bits_is_builtin_type & T_1412;
+ assign T_1415 = T_1413 == 1'h0;
+ assign T_1416 = T_1410 & T_1415;
+ assign T_1417 = T_1416 ? 3'h6 : 1'h0;
+ assign T_1418 = 3'h4 == state;
+ assign T_1422 = 1'h0 == 1'h0;
+ assign T_1424 = io_inner_grant_bits_g_type == 3'h0;
+ assign T_1425 = io_inner_grant_bits_is_builtin_type & T_1424;
+ assign T_1427 = T_1425 == 1'h0;
+ assign T_1428 = T_1422 & T_1427;
+ assign T_1429 = T_1428 ? 3'h6 : 1'h0;
+ assign T_1430 = 3'h6 == state;
+ assign GEN_9 = T_325 & T_327;
+ assign GEN_10 = T_1149 & T_1151;
+ assign GEN_11 = T_1163 & T_1165;
+ assign GEN_12 = T_1189 & T_1191;
+ assign GEN_13 = 1'h0 == 1'h0;
+ assign GEN_14 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_15 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_16 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_17 = 1'h1 == 1'h0;
+ assign GEN_18 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_19 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_20 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_21 = 2'h2 == 1'h0;
+ assign GEN_22 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_23 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_24 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_25 = 2'h3 == 1'h0;
+ assign GEN_26 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_27 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_28 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_29 = 1'h0 == 1'h0;
+ assign GEN_30 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_31 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_32 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_33 = 1'h1 == 1'h0;
+ assign GEN_34 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_35 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_36 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_37 = 2'h2 == 1'h0;
+ assign GEN_38 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_39 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_40 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_41 = 2'h3 == 1'h0;
+ assign GEN_42 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_43 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_44 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_45 = 2'h3 == oacq_data_cnt;
+ assign GEN_46 = 2'h2 == oacq_data_cnt;
+ assign GEN_47 = 1'h1 == oacq_data_cnt;
+ assign GEN_48 = 2'h3 == oacq_data_cnt;
+ assign GEN_49 = 2'h2 == oacq_data_cnt;
+ assign GEN_50 = 1'h1 == oacq_data_cnt;
+ assign GEN_51 = 2'h3 == oacq_data_cnt;
+ assign GEN_52 = 2'h2 == oacq_data_cnt;
+ assign GEN_53 = 1'h1 == oacq_data_cnt;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ state = {1{$random}};
+ xact_addr_block = {1{$random}};
+ xact_client_xact_id = {1{$random}};
+ xact_addr_beat = {1{$random}};
+ xact_is_builtin_type = {1{$random}};
+ xact_a_type = {1{$random}};
+ xact_union = {1{$random}};
+ xact_data_buffer_0 = {1{$random}};
+ xact_data_buffer_1 = {1{$random}};
+ xact_data_buffer_2 = {1{$random}};
+ xact_data_buffer_3 = {1{$random}};
+ xact_wmask_buffer_0 = {1{$random}};
+ xact_wmask_buffer_1 = {1{$random}};
+ xact_wmask_buffer_2 = {1{$random}};
+ xact_wmask_buffer_3 = {1{$random}};
+ xact_client_id = {1{$random}};
+ release_count = {1{$random}};
+ pending_probes = {1{$random}};
+ collect_iacq_data = {1{$random}};
+ iacq_data_valid = {1{$random}};
+ T_371 = {1{$random}};
+ T_403 = {1{$random}};
+ T_441 = {1{$random}};
+ T_469 = {1{$random}};
+ T_504 = {1{$random}};
+ pending_ognt_ack = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1430) begin
+ if(io_inner_finish_valid) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1418) begin
+ if(io_inner_grant_ready) begin
+ state <= T_1429;
+ end else begin
+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
+ end else begin
+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end
+ end else begin
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+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end else begin
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+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
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+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
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+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
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+ end
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+ end
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+ state <= T_1402;
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ end else begin
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
+ end else begin
+ ;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ end else begin
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end
+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1418) begin
+ if(io_inner_grant_ready) begin
+ state <= T_1429;
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+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
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+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
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+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end
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+ end
+ end else begin
+ if(T_1392) begin
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+ state <= T_1402;
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ if(T_1380) begin
+ state <= T_1382;
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ end
+ end else begin
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
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+ end
+ end else begin
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+ if(T_1406) begin
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ state <= T_1337;
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+ end
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ state <= T_1337;
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+ end
+ end else begin
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
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+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
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+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1382;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_addr_block <= io_inner_acquire_bits_addr_block;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_client_xact_id <= io_inner_acquire_bits_client_xact_id;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_addr_beat <= io_inner_acquire_bits_addr_beat;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_is_builtin_type <= io_inner_acquire_bits_is_builtin_type;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_a_type <= io_inner_acquire_bits_a_type;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_union <= io_inner_acquire_bits_union;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_13) begin
+ xact_data_buffer_0 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_14) begin
+ xact_data_buffer_0 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_15) begin
+ xact_data_buffer_0 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_16) begin
+ xact_data_buffer_0 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_17) begin
+ xact_data_buffer_1 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_18) begin
+ xact_data_buffer_1 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_19) begin
+ xact_data_buffer_1 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_20) begin
+ xact_data_buffer_1 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_21) begin
+ xact_data_buffer_2 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_22) begin
+ xact_data_buffer_2 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_23) begin
+ xact_data_buffer_2 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_24) begin
+ xact_data_buffer_2 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_25) begin
+ xact_data_buffer_3 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_26) begin
+ xact_data_buffer_3 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_27) begin
+ xact_data_buffer_3 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_28) begin
+ xact_data_buffer_3 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_29) begin
+ xact_wmask_buffer_0 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_30) begin
+ xact_wmask_buffer_0 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_31) begin
+ xact_wmask_buffer_0 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_32) begin
+ xact_wmask_buffer_0 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_33) begin
+ xact_wmask_buffer_1 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_34) begin
+ xact_wmask_buffer_1 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_35) begin
+ xact_wmask_buffer_1 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_36) begin
+ xact_wmask_buffer_1 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_37) begin
+ xact_wmask_buffer_2 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_38) begin
+ xact_wmask_buffer_2 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_39) begin
+ xact_wmask_buffer_2 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_40) begin
+ xact_wmask_buffer_2 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_41) begin
+ xact_wmask_buffer_3 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_42) begin
+ xact_wmask_buffer_3 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_43) begin
+ xact_wmask_buffer_3 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_44) begin
+ xact_wmask_buffer_3 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_client_id <= io_inner_acquire_bits_client_id;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ release_count <= 1'h0;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ release_count <= T_1387;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ release_count <= T_1378;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ pending_probes <= 1'h0;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_probe_ready) begin
+ pending_probes <= T_1344;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ pending_probes <= mask_incoherent;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ pending_probes <= mask_incoherent;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ collect_iacq_data <= 1'h0;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ collect_iacq_data <= T_1298;
+ end else begin
+ if(collect_iacq_data) begin
+ if(iacq_data_done) begin
+ collect_iacq_data <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(iacq_data_done) begin
+ collect_iacq_data <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ iacq_data_valid <= 4'h0;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ iacq_data_valid <= T_1316;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ iacq_data_valid <= T_1241;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ iacq_data_valid <= T_1241;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ T_371 <= 2'h0;
+ end else begin
+ if(T_369) begin
+ T_371 <= T_380;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_403 <= 2'h0;
+ end else begin
+ if(T_401) begin
+ T_403 <= T_412;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_441 <= 2'h0;
+ end else begin
+ if(T_439) begin
+ T_441 <= T_450;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_469 <= 2'h0;
+ end else begin
+ if(T_467) begin
+ T_469 <= T_478;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_504 <= 2'h0;
+ end else begin
+ if(T_502) begin
+ T_504 <= T_513;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ pending_ognt_ack <= 1'h1;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ pending_ognt_ack <= 1'h1;
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ pending_ognt_ack <= 1'h1;
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ `ifndef SYNTHESIS
+ if(GEN_9 & T_329) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_325 & T_327) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_10 & T_1153) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_1149 & T_1151) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_11 & T_1167) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_1163 & T_1165) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_12 & T_1193) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_1189 & T_1191) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ end
+endmodule
+module BroadcastAcquireTracker_31(
+ input clk,
+ input reset,
+ output io_inner_acquire_ready,
+ input io_inner_acquire_valid,
+ input [25:0] io_inner_acquire_bits_addr_block,
+ input [1:0] io_inner_acquire_bits_client_xact_id,
+ input [1:0] io_inner_acquire_bits_addr_beat,
+ input io_inner_acquire_bits_is_builtin_type,
+ input [2:0] io_inner_acquire_bits_a_type,
+ input [16:0] io_inner_acquire_bits_union,
+ input [3:0] io_inner_acquire_bits_data,
+ input [1:0] io_inner_acquire_bits_client_id,
+ input io_inner_grant_ready,
+ output io_inner_grant_valid,
+ output [1:0] io_inner_grant_bits_addr_beat,
+ output [1:0] io_inner_grant_bits_client_xact_id,
+ output [3:0] io_inner_grant_bits_manager_xact_id,
+ output io_inner_grant_bits_is_builtin_type,
+ output [3:0] io_inner_grant_bits_g_type,
+ output [3:0] io_inner_grant_bits_data,
+ output [1:0] io_inner_grant_bits_client_id,
+ output io_inner_finish_ready,
+ input io_inner_finish_valid,
+ input [3:0] io_inner_finish_bits_manager_xact_id,
+ input io_inner_probe_ready,
+ output io_inner_probe_valid,
+ output [25:0] io_inner_probe_bits_addr_block,
+ output [1:0] io_inner_probe_bits_p_type,
+ output [1:0] io_inner_probe_bits_client_id,
+ output io_inner_release_ready,
+ input io_inner_release_valid,
+ input [1:0] io_inner_release_bits_addr_beat,
+ input [25:0] io_inner_release_bits_addr_block,
+ input [1:0] io_inner_release_bits_client_xact_id,
+ input io_inner_release_bits_voluntary,
+ input [2:0] io_inner_release_bits_r_type,
+ input [3:0] io_inner_release_bits_data,
+ input [1:0] io_inner_release_bits_client_id,
+ input io_incoherent_0,
+ input io_outer_acquire_ready,
+ output io_outer_acquire_valid,
+ output [25:0] io_outer_acquire_bits_addr_block,
+ output [3:0] io_outer_acquire_bits_client_xact_id,
+ output [1:0] io_outer_acquire_bits_addr_beat,
+ output io_outer_acquire_bits_is_builtin_type,
+ output [2:0] io_outer_acquire_bits_a_type,
+ output [16:0] io_outer_acquire_bits_union,
+ output [3:0] io_outer_acquire_bits_data,
+ output io_outer_grant_ready,
+ input io_outer_grant_valid,
+ input [1:0] io_outer_grant_bits_addr_beat,
+ input [3:0] io_outer_grant_bits_client_xact_id,
+ input io_outer_grant_bits_manager_xact_id,
+ input io_outer_grant_bits_is_builtin_type,
+ input [3:0] io_outer_grant_bits_g_type,
+ input [3:0] io_outer_grant_bits_data,
+ output io_has_acquire_conflict,
+ output io_has_acquire_match,
+ output io_has_release_match
+);
+ reg [2:0] state;
+ reg [25:0] xact_addr_block;
+ reg [1:0] xact_client_xact_id;
+ reg [1:0] xact_addr_beat;
+ reg xact_is_builtin_type;
+ reg [2:0] xact_a_type;
+ reg [16:0] xact_union;
+ reg [3:0] xact_data_buffer_0;
+ reg [3:0] xact_data_buffer_1;
+ reg [3:0] xact_data_buffer_2;
+ reg [3:0] xact_data_buffer_3;
+ reg [15:0] xact_wmask_buffer_0;
+ reg [15:0] xact_wmask_buffer_1;
+ reg [15:0] xact_wmask_buffer_2;
+ reg [15:0] xact_wmask_buffer_3;
+ reg [1:0] xact_client_id;
+ wire coh_sharers;
+ wire T_303;
+ wire T_304;
+ wire [2:0] T_309_0;
+ wire [2:0] T_309_1;
+ wire [2:0] T_309_2;
+ wire T_314;
+ wire T_315;
+ wire T_316;
+ wire T_318;
+ wire T_319;
+ wire T_320;
+ wire T_321;
+ wire T_323;
+ wire T_325;
+ wire T_327;
+ wire T_329;
+ reg release_count;
+ reg pending_probes;
+ wire T_334;
+ wire T_336_0;
+ wire GEN_7;
+ wire T_341;
+ wire [3:0] T_344;
+ wire [3:0] T_345;
+ wire T_346;
+ wire [3:0] T_347;
+ wire [3:0] T_348;
+ wire [3:0] mask_self;
+ wire T_350;
+ wire [3:0] mask_incoherent;
+ reg collect_iacq_data;
+ reg [3:0] iacq_data_valid;
+ wire T_356;
+ wire T_359;
+ wire [2:0] T_362_0;
+ wire T_365;
+ wire T_367;
+ wire T_368;
+ wire T_369;
+ reg [1:0] T_371;
+ wire T_373;
+ wire T_375;
+ wire [2:0] T_378;
+ wire [1:0] T_379;
+ wire [1:0] T_380;
+ wire T_381;
+ wire [1:0] T_382;
+ wire iacq_data_done;
+ wire T_384;
+ wire [1:0] T_388_0;
+ wire [1:0] T_388_1;
+ wire [1:0] T_388_2;
+ wire T_393;
+ wire T_394;
+ wire T_395;
+ wire T_397;
+ wire T_398;
+ wire T_399;
+ wire T_400;
+ wire T_401;
+ reg [1:0] T_403;
+ wire T_405;
+ wire T_407;
+ wire [2:0] T_410;
+ wire [1:0] T_411;
+ wire [1:0] T_412;
+ wire T_413;
+ wire [1:0] T_414;
+ wire irel_data_done;
+ wire T_417;
+ wire [2:0] T_421_0;
+ wire T_424;
+ wire T_426;
+ wire T_428_0;
+ wire T_428_1;
+ wire T_432;
+ wire T_433;
+ wire T_435;
+ wire T_436;
+ wire T_437;
+ wire T_438;
+ wire T_439;
+ reg [1:0] T_441;
+ wire T_443;
+ wire T_445;
+ wire [2:0] T_448;
+ wire [1:0] T_449;
+ wire [1:0] T_450;
+ wire T_451;
+ wire [1:0] ignt_data_cnt;
+ wire ignt_data_done;
+ wire T_455;
+ wire T_457;
+ wire [2:0] T_460_0;
+ wire T_463;
+ wire T_465;
+ wire T_466;
+ wire T_467;
+ reg [1:0] T_469;
+ wire T_471;
+ wire T_473;
+ wire [2:0] T_476;
+ wire [1:0] T_477;
+ wire [1:0] T_478;
+ wire T_479;
+ wire [1:0] oacq_data_cnt;
+ wire oacq_data_done;
+ wire T_482;
+ wire [2:0] T_487_0;
+ wire T_490;
+ wire T_492;
+ wire T_494_0;
+ wire T_497;
+ wire T_499;
+ wire T_500;
+ wire T_501;
+ wire T_502;
+ reg [1:0] T_504;
+ wire T_506;
+ wire T_508;
+ wire [2:0] T_511;
+ wire [1:0] T_512;
+ wire [1:0] T_513;
+ wire T_514;
+ wire [1:0] T_515;
+ wire ognt_data_done;
+ reg pending_ognt_ack;
+ wire [2:0] T_523_0;
+ wire [2:0] T_523_1;
+ wire [2:0] T_523_2;
+ wire T_528;
+ wire T_529;
+ wire T_530;
+ wire T_532;
+ wire T_533;
+ wire T_534;
+ wire pending_outer_write;
+ wire [2:0] T_540_0;
+ wire [2:0] T_540_1;
+ wire [2:0] T_540_2;
+ wire T_545;
+ wire T_546;
+ wire T_547;
+ wire T_549;
+ wire T_550;
+ wire T_551;
+ wire pending_outer_write_;
+ wire [2:0] T_556_0;
+ wire [2:0] T_556_1;
+ wire T_560;
+ wire T_561;
+ wire T_563;
+ wire T_564;
+ wire T_566_0;
+ wire T_566_1;
+ wire T_570;
+ wire T_571;
+ wire T_573;
+ wire T_574;
+ wire pending_outer_read;
+ wire T_594;
+ wire [2:0] T_595;
+ wire T_596;
+ wire [2:0] T_597;
+ wire T_598;
+ wire [2:0] T_599;
+ wire T_600;
+ wire [2:0] T_601;
+ wire T_602;
+ wire [2:0] T_603;
+ wire T_604;
+ wire [2:0] T_605;
+ wire T_606;
+ wire [2:0] T_607;
+ wire T_608;
+ wire T_611;
+ wire T_612;
+ wire T_613;
+ wire [2:0] T_614;
+ wire [1:0] T_623_addr_beat;
+ wire [1:0] T_623_client_xact_id;
+ wire [3:0] T_623_manager_xact_id;
+ wire T_623_is_builtin_type;
+ wire [3:0] T_623_g_type;
+ wire [3:0] T_623_data;
+ wire [1:0] T_623_client_id;
+ wire [2:0] T_634_0;
+ wire [2:0] T_634_1;
+ wire T_638;
+ wire T_639;
+ wire T_641;
+ wire T_642;
+ wire T_644_0;
+ wire T_644_1;
+ wire T_648;
+ wire T_649;
+ wire T_651;
+ wire T_652;
+ wire pending_outer_read_;
+ wire [2:0] T_658_0;
+ wire [2:0] T_658_1;
+ wire [2:0] T_658_2;
+ wire T_663;
+ wire T_664;
+ wire T_665;
+ wire T_667;
+ wire T_668;
+ wire T_669;
+ wire subblock_type;
+ wire T_671;
+ wire T_672;
+ wire T_673;
+ wire T_675;
+ wire T_676;
+ wire T_677;
+ wire T_678;
+ wire T_679;
+ wire T_681;
+ wire T_682;
+ wire T_683;
+ wire T_684;
+ wire [15:0] GEN_8;
+ wire [15:0] T_689;
+ wire [3:0] T_695;
+ wire [1:0] T_696;
+ wire [5:0] T_697;
+ wire [1:0] T_699;
+ wire [4:0] T_700;
+ wire [16:0] T_702;
+ wire [16:0] T_704;
+ wire [3:0] T_706;
+ wire [1:0] T_707;
+ wire [5:0] T_708;
+ wire [5:0] T_710;
+ wire [5:0] T_712;
+ wire T_713;
+ wire [5:0] T_714;
+ wire T_715;
+ wire [5:0] T_716;
+ wire T_717;
+ wire [5:0] T_718;
+ wire T_719;
+ wire [16:0] T_720;
+ wire T_721;
+ wire [16:0] T_722;
+ wire T_723;
+ wire [16:0] T_724;
+ wire T_725;
+ wire [16:0] T_726;
+ wire [25:0] oacq_probe_addr_block;
+ wire [3:0] oacq_probe_client_xact_id;
+ wire [1:0] oacq_probe_addr_beat;
+ wire oacq_probe_is_builtin_type;
+ wire [2:0] oacq_probe_a_type;
+ wire [16:0] oacq_probe_union;
+ wire [3:0] oacq_probe_data;
+ wire [3:0] T_744;
+ wire T_745;
+ wire [1:0] T_747;
+ wire T_749;
+ wire T_750;
+ wire T_751;
+ wire T_752;
+ wire T_754_0;
+ wire T_754_1;
+ wire [8:0] T_759;
+ wire [7:0] T_760;
+ wire [8:0] T_762;
+ wire [7:0] T_763;
+ wire [7:0] T_765_0;
+ wire [7:0] T_765_1;
+ wire [15:0] T_769;
+ wire T_771;
+ wire T_772;
+ wire T_774;
+ wire T_775;
+ wire T_776;
+ wire [15:0] T_777;
+ wire [15:0] T_779;
+ wire [15:0] T_780;
+ wire [3:0] T_788;
+ wire [1:0] T_789;
+ wire [5:0] T_790;
+ wire [1:0] T_792;
+ wire [4:0] T_793;
+ wire [16:0] T_795;
+ wire [16:0] T_797;
+ wire [3:0] T_799;
+ wire [1:0] T_800;
+ wire [5:0] T_801;
+ wire [5:0] T_803;
+ wire [5:0] T_805;
+ wire T_806;
+ wire [5:0] T_807;
+ wire T_808;
+ wire [5:0] T_809;
+ wire T_810;
+ wire [5:0] T_811;
+ wire T_812;
+ wire [16:0] T_813;
+ wire T_814;
+ wire [16:0] T_815;
+ wire T_816;
+ wire [16:0] T_817;
+ wire T_818;
+ wire [16:0] T_819;
+ wire [25:0] oacq_write_beat_addr_block;
+ wire [3:0] oacq_write_beat_client_xact_id;
+ wire [1:0] oacq_write_beat_addr_beat;
+ wire oacq_write_beat_is_builtin_type;
+ wire [2:0] oacq_write_beat_a_type;
+ wire [16:0] oacq_write_beat_union;
+ wire [3:0] oacq_write_beat_data;
+ wire [3:0] T_846;
+ wire [1:0] T_847;
+ wire [5:0] T_848;
+ wire [1:0] T_850;
+ wire [4:0] T_851;
+ wire [15:0] GEN_0;
+ wire [16:0] T_853;
+ wire [15:0] GEN_1;
+ wire [16:0] T_855;
+ wire [3:0] T_857;
+ wire [1:0] T_858;
+ wire [5:0] T_859;
+ wire [5:0] T_861;
+ wire [5:0] T_863;
+ wire T_864;
+ wire [5:0] T_865;
+ wire T_866;
+ wire [5:0] T_867;
+ wire T_868;
+ wire [5:0] T_869;
+ wire T_870;
+ wire [16:0] T_871;
+ wire T_872;
+ wire [16:0] T_873;
+ wire T_874;
+ wire [16:0] T_875;
+ wire T_876;
+ wire [16:0] T_877;
+ wire [25:0] oacq_write_block_addr_block;
+ wire [3:0] oacq_write_block_client_xact_id;
+ wire [1:0] oacq_write_block_addr_beat;
+ wire oacq_write_block_is_builtin_type;
+ wire [2:0] oacq_write_block_a_type;
+ wire [16:0] oacq_write_block_union;
+ wire [3:0] oacq_write_block_data;
+ wire [3:0] GEN_2;
+ wire [3:0] T_895;
+ wire [2:0] T_896;
+ wire [6:0] T_904;
+ wire [5:0] T_905;
+ wire [12:0] T_906;
+ wire [5:0] T_908;
+ wire [8:0] T_909;
+ wire [1:0] T_911;
+ wire [1:0] T_913;
+ wire [6:0] T_915;
+ wire [5:0] T_916;
+ wire [12:0] T_917;
+ wire [5:0] T_919;
+ wire [5:0] T_921;
+ wire T_922;
+ wire [5:0] T_923;
+ wire T_924;
+ wire [5:0] T_925;
+ wire T_926;
+ wire [12:0] T_927;
+ wire T_928;
+ wire [12:0] T_929;
+ wire T_930;
+ wire [12:0] T_931;
+ wire T_932;
+ wire [12:0] T_933;
+ wire T_934;
+ wire [12:0] T_935;
+ wire [25:0] oacq_read_beat_addr_block;
+ wire [3:0] oacq_read_beat_client_xact_id;
+ wire [1:0] oacq_read_beat_addr_beat;
+ wire oacq_read_beat_is_builtin_type;
+ wire [2:0] oacq_read_beat_a_type;
+ wire [16:0] oacq_read_beat_union;
+ wire [3:0] oacq_read_beat_data;
+ wire [3:0] T_962;
+ wire [5:0] T_963;
+ wire [9:0] T_964;
+ wire [5:0] T_966;
+ wire [8:0] T_967;
+ wire [1:0] T_969;
+ wire [1:0] T_971;
+ wire [3:0] T_973;
+ wire [5:0] T_974;
+ wire [9:0] T_975;
+ wire [5:0] T_977;
+ wire [5:0] T_979;
+ wire T_980;
+ wire [5:0] T_981;
+ wire T_982;
+ wire [5:0] T_983;
+ wire T_984;
+ wire [9:0] T_985;
+ wire T_986;
+ wire [9:0] T_987;
+ wire T_988;
+ wire [9:0] T_989;
+ wire T_990;
+ wire [9:0] T_991;
+ wire T_992;
+ wire [9:0] T_993;
+ wire [25:0] oacq_read_block_addr_block;
+ wire [3:0] oacq_read_block_client_xact_id;
+ wire [1:0] oacq_read_block_addr_beat;
+ wire oacq_read_block_is_builtin_type;
+ wire [2:0] oacq_read_block_a_type;
+ wire [16:0] oacq_read_block_union;
+ wire [3:0] oacq_read_block_data;
+ wire T_1011;
+ wire T_1012;
+ wire [25:0] T_1013_addr_block;
+ wire [3:0] T_1013_client_xact_id;
+ wire [1:0] T_1013_addr_beat;
+ wire T_1013_is_builtin_type;
+ wire [2:0] T_1013_a_type;
+ wire [16:0] T_1013_union;
+ wire [3:0] T_1013_data;
+ wire [25:0] T_1021_addr_block;
+ wire [3:0] T_1021_client_xact_id;
+ wire [1:0] T_1021_addr_beat;
+ wire T_1021_is_builtin_type;
+ wire [2:0] T_1021_a_type;
+ wire [16:0] T_1021_union;
+ wire [3:0] T_1021_data;
+ wire [25:0] T_1029_addr_block;
+ wire [3:0] T_1029_client_xact_id;
+ wire [1:0] T_1029_addr_beat;
+ wire T_1029_is_builtin_type;
+ wire [2:0] T_1029_a_type;
+ wire [16:0] T_1029_union;
+ wire [3:0] T_1029_data;
+ wire [25:0] T_1037_addr_block;
+ wire [3:0] T_1037_client_xact_id;
+ wire [1:0] T_1037_addr_beat;
+ wire T_1037_is_builtin_type;
+ wire [2:0] T_1037_a_type;
+ wire [16:0] T_1037_union;
+ wire [3:0] T_1037_data;
+ wire T_1054;
+ wire [1:0] T_1055;
+ wire T_1056;
+ wire [1:0] T_1057;
+ wire T_1058;
+ wire [1:0] T_1059;
+ wire T_1060;
+ wire [1:0] T_1061;
+ wire T_1062;
+ wire [1:0] T_1063;
+ wire T_1064;
+ wire [1:0] T_1065;
+ wire T_1066;
+ wire [1:0] T_1067;
+ wire T_1068;
+ wire [1:0] T_1069;
+ wire T_1070;
+ wire [1:0] T_1071;
+ wire [1:0] T_1072;
+ wire [25:0] T_1077_addr_block;
+ wire [1:0] T_1077_p_type;
+ wire [1:0] T_1077_client_id;
+ wire T_1100;
+ wire [2:0] T_1101;
+ wire T_1102;
+ wire [2:0] T_1103;
+ wire T_1104;
+ wire [2:0] T_1105;
+ wire T_1106;
+ wire [2:0] T_1107;
+ wire T_1108;
+ wire [2:0] T_1109;
+ wire T_1110;
+ wire [2:0] T_1111;
+ wire T_1112;
+ wire [2:0] T_1113;
+ wire T_1114;
+ wire T_1117;
+ wire T_1118;
+ wire T_1119;
+ wire [2:0] T_1120;
+ wire [1:0] T_1129_addr_beat;
+ wire [1:0] T_1129_client_xact_id;
+ wire [3:0] T_1129_manager_xact_id;
+ wire T_1129_is_builtin_type;
+ wire [3:0] T_1129_g_type;
+ wire [3:0] T_1129_data;
+ wire [1:0] T_1129_client_id;
+ wire T_1140;
+ wire T_1141;
+ wire T_1142;
+ wire T_1143;
+ wire T_1144;
+ wire T_1145;
+ wire T_1147;
+ wire T_1149;
+ wire T_1151;
+ wire T_1153;
+ wire T_1154;
+ wire T_1155;
+ wire T_1156;
+ wire T_1157;
+ wire T_1158;
+ wire T_1159;
+ wire T_1161;
+ wire T_1163;
+ wire T_1165;
+ wire T_1167;
+ wire T_1168;
+ wire T_1169;
+ wire T_1170;
+ wire T_1172;
+ wire [2:0] T_1175_0;
+ wire T_1178;
+ wire T_1180;
+ wire T_1181;
+ wire T_1182;
+ wire T_1184;
+ wire T_1185;
+ wire T_1187;
+ wire T_1189;
+ wire T_1191;
+ wire T_1193;
+ wire [3:0] GEN_3;
+ wire [3:0] T_1197;
+ wire T_1198;
+ wire [1:0] T_1200;
+ wire T_1202;
+ wire T_1203;
+ wire T_1204;
+ wire T_1205;
+ wire T_1207_0;
+ wire T_1207_1;
+ wire [8:0] T_1212;
+ wire [7:0] T_1213;
+ wire [8:0] T_1215;
+ wire [7:0] T_1216;
+ wire [7:0] T_1218_0;
+ wire [7:0] T_1218_1;
+ wire [15:0] T_1222;
+ wire T_1224;
+ wire T_1225;
+ wire T_1227;
+ wire T_1228;
+ wire T_1229;
+ wire [15:0] T_1230;
+ wire [15:0] T_1232;
+ wire [15:0] T_1233;
+ wire [15:0] GEN_4;
+ wire [3:0] T_1236;
+ wire [3:0] T_1237;
+ wire [3:0] T_1238;
+ wire [3:0] T_1239;
+ wire [3:0] T_1240;
+ wire [3:0] T_1241;
+ wire T_1245;
+ wire [3:0] GEN_5;
+ wire [3:0] T_1251;
+ wire T_1252;
+ wire [1:0] T_1254;
+ wire T_1256;
+ wire T_1257;
+ wire T_1258;
+ wire T_1259;
+ wire T_1261_0;
+ wire T_1261_1;
+ wire [8:0] T_1266;
+ wire [7:0] T_1267;
+ wire [8:0] T_1269;
+ wire [7:0] T_1270;
+ wire [7:0] T_1272_0;
+ wire [7:0] T_1272_1;
+ wire [15:0] T_1276;
+ wire T_1278;
+ wire T_1279;
+ wire T_1281;
+ wire T_1282;
+ wire T_1283;
+ wire [15:0] T_1284;
+ wire [15:0] T_1286;
+ wire [15:0] T_1287;
+ wire [15:0] GEN_6;
+ wire T_1289;
+ wire [2:0] T_1292_0;
+ wire T_1295;
+ wire T_1297;
+ wire T_1298;
+ wire [2:0] T_1303_0;
+ wire [2:0] T_1303_1;
+ wire [2:0] T_1303_2;
+ wire T_1308;
+ wire T_1309;
+ wire T_1310;
+ wire T_1312;
+ wire T_1313;
+ wire T_1314;
+ wire T_1315;
+ wire [3:0] T_1316;
+ wire T_1318;
+ wire T_1319;
+ wire T_1320;
+ wire T_1321;
+ wire T_1322;
+ wire [1:0] T_1324;
+ wire [2:0] T_1325;
+ wire [1:0] T_1326;
+ wire [1:0] T_1329;
+ wire [2:0] T_1330;
+ wire [1:0] T_1331;
+ wire [2:0] T_1332;
+ wire [3:0] T_1333;
+ wire [2:0] T_1334;
+ wire [2:0] T_1335;
+ wire [2:0] T_1336;
+ wire [2:0] T_1337;
+ wire T_1338;
+ wire T_1340;
+ wire [1:0] T_1342;
+ wire [1:0] T_1343;
+ wire [1:0] T_1344;
+ wire [1:0] T_1346_0;
+ wire [1:0] T_1346_1;
+ wire [1:0] T_1346_2;
+ wire T_1351;
+ wire T_1352;
+ wire T_1353;
+ wire T_1355;
+ wire T_1356;
+ wire T_1357;
+ wire T_1359;
+ wire T_1360;
+ wire [1:0] T_1362_0;
+ wire [1:0] T_1362_1;
+ wire [1:0] T_1362_2;
+ wire T_1367;
+ wire T_1368;
+ wire T_1369;
+ wire T_1371;
+ wire T_1372;
+ wire T_1373;
+ wire [1:0] T_1377;
+ wire T_1378;
+ wire T_1380;
+ wire [2:0] T_1381;
+ wire [2:0] T_1382;
+ wire T_1384;
+ wire [1:0] T_1386;
+ wire T_1387;
+ wire T_1389;
+ wire [2:0] T_1390;
+ wire [2:0] T_1391;
+ wire T_1392;
+ wire T_1394;
+ wire T_1396;
+ wire [3:0] T_1397;
+ wire T_1398;
+ wire T_1399;
+ wire T_1400;
+ wire [2:0] T_1402;
+ wire T_1403;
+ wire T_1405;
+ wire T_1406;
+ wire T_1407;
+ wire T_1410;
+ wire T_1412;
+ wire T_1413;
+ wire T_1415;
+ wire T_1416;
+ wire [2:0] T_1417;
+ wire T_1418;
+ wire T_1422;
+ wire T_1424;
+ wire T_1425;
+ wire T_1427;
+ wire T_1428;
+ wire [2:0] T_1429;
+ wire T_1430;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ wire GEN_17;
+ wire GEN_18;
+ wire GEN_19;
+ wire GEN_20;
+ wire GEN_21;
+ wire GEN_22;
+ wire GEN_23;
+ wire GEN_24;
+ wire GEN_25;
+ wire GEN_26;
+ wire GEN_27;
+ wire GEN_28;
+ wire GEN_29;
+ wire GEN_30;
+ wire GEN_31;
+ wire GEN_32;
+ wire GEN_33;
+ wire GEN_34;
+ wire GEN_35;
+ wire GEN_36;
+ wire GEN_37;
+ wire GEN_38;
+ wire GEN_39;
+ wire GEN_40;
+ wire GEN_41;
+ wire GEN_42;
+ wire GEN_43;
+ wire GEN_44;
+ wire GEN_45;
+ wire GEN_46;
+ wire GEN_47;
+ wire GEN_48;
+ wire GEN_49;
+ wire GEN_50;
+ wire GEN_51;
+ wire GEN_52;
+ wire GEN_53;
+ assign io_inner_acquire_ready = T_1245 ? 1'h1 : collect_iacq_data ? 1'h1 : 1'h0;
+ assign io_inner_grant_valid = T_1418 ? 1'h1 : T_1407 ? io_outer_grant_valid : 1'h0;
+ assign io_inner_grant_bits_addr_beat = T_1129_addr_beat;
+ assign io_inner_grant_bits_client_xact_id = T_1129_client_xact_id;
+ assign io_inner_grant_bits_manager_xact_id = T_1129_manager_xact_id;
+ assign io_inner_grant_bits_is_builtin_type = T_1129_is_builtin_type;
+ assign io_inner_grant_bits_g_type = T_1129_g_type;
+ assign io_inner_grant_bits_data = T_1129_data;
+ assign io_inner_grant_bits_client_id = T_1129_client_id;
+ assign io_inner_finish_ready = T_1430 ? 1'h1 : 1'h0;
+ assign io_inner_probe_valid = T_1338 ? T_1340 : 1'h0;
+ assign io_inner_probe_bits_addr_block = T_1077_addr_block;
+ assign io_inner_probe_bits_p_type = T_1077_p_type;
+ assign io_inner_probe_bits_client_id = T_1077_client_id;
+ assign io_inner_release_ready = T_1338 ? T_1360 : 1'h0;
+ assign io_outer_acquire_valid = T_1403 ? T_1405 : T_1392 ? T_1400 : T_1338 ? io_inner_release_valid ? T_1373 ? 1'h1 : 1'h0 : 1'h0 : 1'h0;
+ assign io_outer_acquire_bits_addr_block = T_1037_addr_block;
+ assign io_outer_acquire_bits_client_xact_id = T_1037_client_xact_id;
+ assign io_outer_acquire_bits_addr_beat = T_1037_addr_beat;
+ assign io_outer_acquire_bits_is_builtin_type = T_1037_is_builtin_type;
+ assign io_outer_acquire_bits_a_type = T_1037_a_type;
+ assign io_outer_acquire_bits_union = T_1037_union;
+ assign io_outer_acquire_bits_data = T_1037_data;
+ assign io_outer_grant_ready = T_1407 ? io_inner_grant_ready : pending_ognt_ack ? 1'h1 : 1'h0;
+ assign io_has_acquire_conflict = T_676;
+ assign io_has_acquire_match = T_678;
+ assign io_has_release_match = T_684;
+ assign coh_sharers = 1'h0;
+ assign T_303 = state != 1'h0;
+ assign T_304 = T_303 & xact_is_builtin_type;
+ assign T_309_0 = 3'h4;
+ assign T_309_1 = 3'h5;
+ assign T_309_2 = 3'h6;
+ assign T_314 = T_309_0 == xact_a_type;
+ assign T_315 = T_309_1 == xact_a_type;
+ assign T_316 = T_309_2 == xact_a_type;
+ assign T_318 = 1'h0 | T_314;
+ assign T_319 = T_318 | T_315;
+ assign T_320 = T_319 | T_316;
+ assign T_321 = T_304 & T_320;
+ assign T_323 = T_321 == 1'h0;
+ assign T_325 = reset == 1'h0;
+ assign T_327 = T_323 == 1'h0;
+ assign T_329 = reset == 1'h0;
+ assign T_334 = pending_probes;
+ assign T_336_0 = T_334;
+ assign GEN_7 = $signed(1'h1);
+ assign T_341 = $unsigned(GEN_7);
+ assign T_344 = 1'h1 << io_inner_acquire_bits_client_id;
+ assign T_345 = T_341 | T_344;
+ assign T_346 = ~ T_341;
+ assign T_347 = T_346 | T_344;
+ assign T_348 = ~ T_347;
+ assign mask_self = 1'h0 ? T_345 : T_348;
+ assign T_350 = ~ io_incoherent_0;
+ assign mask_incoherent = mask_self & T_350;
+ assign T_356 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_359 = 1'h1 & io_inner_acquire_bits_is_builtin_type;
+ assign T_362_0 = 3'h3;
+ assign T_365 = T_362_0 == io_inner_acquire_bits_a_type;
+ assign T_367 = 1'h0 | T_365;
+ assign T_368 = T_359 & T_367;
+ assign T_369 = T_356 & T_368;
+ assign T_373 = T_371 == 2'h3;
+ assign T_375 = 1'h0 & T_373;
+ assign T_378 = T_371 + 1'h1;
+ assign T_379 = T_378[1:0];
+ assign T_380 = T_375 ? 1'h0 : T_379;
+ assign T_381 = T_369 & T_373;
+ assign T_382 = T_368 ? T_371 : 1'h0;
+ assign iacq_data_done = T_368 ? T_381 : T_356;
+ assign T_384 = io_inner_release_ready & io_inner_release_valid;
+ assign T_388_0 = 1'h0;
+ assign T_388_1 = 1'h1;
+ assign T_388_2 = 2'h2;
+ assign T_393 = T_388_0 == io_inner_release_bits_r_type;
+ assign T_394 = T_388_1 == io_inner_release_bits_r_type;
+ assign T_395 = T_388_2 == io_inner_release_bits_r_type;
+ assign T_397 = 1'h0 | T_393;
+ assign T_398 = T_397 | T_394;
+ assign T_399 = T_398 | T_395;
+ assign T_400 = 1'h1 & T_399;
+ assign T_401 = T_384 & T_400;
+ assign T_405 = T_403 == 2'h3;
+ assign T_407 = 1'h0 & T_405;
+ assign T_410 = T_403 + 1'h1;
+ assign T_411 = T_410[1:0];
+ assign T_412 = T_407 ? 1'h0 : T_411;
+ assign T_413 = T_401 & T_405;
+ assign T_414 = T_400 ? T_403 : 1'h0;
+ assign irel_data_done = T_400 ? T_413 : T_384;
+ assign T_417 = io_inner_grant_ready & io_inner_grant_valid;
+ assign T_421_0 = 3'h5;
+ assign T_424 = T_421_0 == io_inner_grant_bits_g_type;
+ assign T_426 = 1'h0 | T_424;
+ assign T_428_0 = 1'h0;
+ assign T_428_1 = 1'h1;
+ assign T_432 = T_428_0 == io_inner_grant_bits_g_type;
+ assign T_433 = T_428_1 == io_inner_grant_bits_g_type;
+ assign T_435 = 1'h0 | T_432;
+ assign T_436 = T_435 | T_433;
+ assign T_437 = io_inner_grant_bits_is_builtin_type ? T_426 : T_436;
+ assign T_438 = 1'h1 & T_437;
+ assign T_439 = T_417 & T_438;
+ assign T_443 = T_441 == 2'h3;
+ assign T_445 = 1'h0 & T_443;
+ assign T_448 = T_441 + 1'h1;
+ assign T_449 = T_448[1:0];
+ assign T_450 = T_445 ? 1'h0 : T_449;
+ assign T_451 = T_439 & T_443;
+ assign ignt_data_cnt = T_438 ? T_441 : 1'h0;
+ assign ignt_data_done = T_438 ? T_451 : T_417;
+ assign T_455 = io_outer_acquire_ready & io_outer_acquire_valid;
+ assign T_457 = 1'h1 & io_outer_acquire_bits_is_builtin_type;
+ assign T_460_0 = 3'h3;
+ assign T_463 = T_460_0 == io_outer_acquire_bits_a_type;
+ assign T_465 = 1'h0 | T_463;
+ assign T_466 = T_457 & T_465;
+ assign T_467 = T_455 & T_466;
+ assign T_471 = T_469 == 2'h3;
+ assign T_473 = 1'h0 & T_471;
+ assign T_476 = T_469 + 1'h1;
+ assign T_477 = T_476[1:0];
+ assign T_478 = T_473 ? 1'h0 : T_477;
+ assign T_479 = T_467 & T_471;
+ assign oacq_data_cnt = T_466 ? T_469 : 1'h0;
+ assign oacq_data_done = T_466 ? T_479 : T_455;
+ assign T_482 = io_outer_grant_ready & io_outer_grant_valid;
+ assign T_487_0 = 3'h5;
+ assign T_490 = T_487_0 == io_outer_grant_bits_g_type;
+ assign T_492 = 1'h0 | T_490;
+ assign T_494_0 = 1'h0;
+ assign T_497 = T_494_0 == io_outer_grant_bits_g_type;
+ assign T_499 = 1'h0 | T_497;
+ assign T_500 = io_outer_grant_bits_is_builtin_type ? T_492 : T_499;
+ assign T_501 = 1'h1 & T_500;
+ assign T_502 = T_482 & T_501;
+ assign T_506 = T_504 == 2'h3;
+ assign T_508 = 1'h0 & T_506;
+ assign T_511 = T_504 + 1'h1;
+ assign T_512 = T_511[1:0];
+ assign T_513 = T_508 ? 1'h0 : T_512;
+ assign T_514 = T_502 & T_506;
+ assign T_515 = T_501 ? T_504 : 1'h0;
+ assign ognt_data_done = T_501 ? T_514 : T_482;
+ assign T_523_0 = 3'h2;
+ assign T_523_1 = 3'h3;
+ assign T_523_2 = 3'h4;
+ assign T_528 = T_523_0 == xact_a_type;
+ assign T_529 = T_523_1 == xact_a_type;
+ assign T_530 = T_523_2 == xact_a_type;
+ assign T_532 = 1'h0 | T_528;
+ assign T_533 = T_532 | T_529;
+ assign T_534 = T_533 | T_530;
+ assign pending_outer_write = xact_is_builtin_type & T_534;
+ assign T_540_0 = 3'h2;
+ assign T_540_1 = 3'h3;
+ assign T_540_2 = 3'h4;
+ assign T_545 = T_540_0 == io_inner_acquire_bits_a_type;
+ assign T_546 = T_540_1 == io_inner_acquire_bits_a_type;
+ assign T_547 = T_540_2 == io_inner_acquire_bits_a_type;
+ assign T_549 = 1'h0 | T_545;
+ assign T_550 = T_549 | T_546;
+ assign T_551 = T_550 | T_547;
+ assign pending_outer_write_ = io_inner_acquire_bits_is_builtin_type & T_551;
+ assign T_556_0 = 3'h5;
+ assign T_556_1 = 3'h4;
+ assign T_560 = T_556_0 == io_inner_grant_bits_g_type;
+ assign T_561 = T_556_1 == io_inner_grant_bits_g_type;
+ assign T_563 = 1'h0 | T_560;
+ assign T_564 = T_563 | T_561;
+ assign T_566_0 = 1'h0;
+ assign T_566_1 = 1'h1;
+ assign T_570 = T_566_0 == io_inner_grant_bits_g_type;
+ assign T_571 = T_566_1 == io_inner_grant_bits_g_type;
+ assign T_573 = 1'h0 | T_570;
+ assign T_574 = T_573 | T_571;
+ assign pending_outer_read = io_inner_grant_bits_is_builtin_type ? T_564 : T_574;
+ assign T_594 = 3'h6 == io_inner_acquire_bits_a_type;
+ assign T_595 = T_594 ? 3'h1 : 3'h3;
+ assign T_596 = 3'h5 == io_inner_acquire_bits_a_type;
+ assign T_597 = T_596 ? 3'h1 : T_595;
+ assign T_598 = 3'h4 == io_inner_acquire_bits_a_type;
+ assign T_599 = T_598 ? 3'h4 : T_597;
+ assign T_600 = 3'h3 == io_inner_acquire_bits_a_type;
+ assign T_601 = T_600 ? 3'h3 : T_599;
+ assign T_602 = 3'h2 == io_inner_acquire_bits_a_type;
+ assign T_603 = T_602 ? 3'h3 : T_601;
+ assign T_604 = 3'h1 == io_inner_acquire_bits_a_type;
+ assign T_605 = T_604 ? 3'h5 : T_603;
+ assign T_606 = 3'h0 == io_inner_acquire_bits_a_type;
+ assign T_607 = T_606 ? 3'h4 : T_605;
+ assign T_608 = io_inner_acquire_bits_a_type == 1'h0;
+ assign T_611 = 1'h0 == 1'h0;
+ assign T_612 = T_611 ? 1'h0 : 1'h1;
+ assign T_613 = T_608 ? T_612 : 1'h1;
+ assign T_614 = io_inner_acquire_bits_is_builtin_type ? T_607 : T_613;
+ assign T_623_addr_beat = 1'h0;
+ assign T_623_client_xact_id = io_inner_acquire_bits_client_xact_id;
+ assign T_623_manager_xact_id = 3'h6;
+ assign T_623_is_builtin_type = io_inner_acquire_bits_is_builtin_type;
+ assign T_623_g_type = T_614;
+ assign T_623_data = 1'h0;
+ assign T_623_client_id = io_inner_acquire_bits_client_id;
+ assign T_634_0 = 3'h5;
+ assign T_634_1 = 3'h4;
+ assign T_638 = T_634_0 == T_623_g_type;
+ assign T_639 = T_634_1 == T_623_g_type;
+ assign T_641 = 1'h0 | T_638;
+ assign T_642 = T_641 | T_639;
+ assign T_644_0 = 1'h0;
+ assign T_644_1 = 1'h1;
+ assign T_648 = T_644_0 == T_623_g_type;
+ assign T_649 = T_644_1 == T_623_g_type;
+ assign T_651 = 1'h0 | T_648;
+ assign T_652 = T_651 | T_649;
+ assign pending_outer_read_ = T_623_is_builtin_type ? T_642 : T_652;
+ assign T_658_0 = 3'h2;
+ assign T_658_1 = 3'h0;
+ assign T_658_2 = 3'h4;
+ assign T_663 = T_658_0 == xact_a_type;
+ assign T_664 = T_658_1 == xact_a_type;
+ assign T_665 = T_658_2 == xact_a_type;
+ assign T_667 = 1'h0 | T_663;
+ assign T_668 = T_667 | T_664;
+ assign T_669 = T_668 | T_665;
+ assign subblock_type = xact_is_builtin_type & T_669;
+ assign T_671 = xact_addr_block == io_inner_acquire_bits_addr_block;
+ assign T_672 = state != 1'h0;
+ assign T_673 = T_671 & T_672;
+ assign T_675 = collect_iacq_data == 1'h0;
+ assign T_676 = T_673 & T_675;
+ assign T_677 = xact_addr_block == io_inner_acquire_bits_addr_block;
+ assign T_678 = T_677 & collect_iacq_data;
+ assign T_679 = xact_addr_block == io_inner_release_bits_addr_block;
+ assign T_681 = io_inner_release_bits_voluntary == 1'h0;
+ assign T_682 = T_679 & T_681;
+ assign T_683 = state == 1'h1;
+ assign T_684 = T_682 & T_683;
+ assign GEN_8 = $signed(16'hffff);
+ assign T_689 = $unsigned(GEN_8);
+ assign T_695 = {1'h0,3'h7};
+ assign T_696 = {1'h0,1'h1};
+ assign T_697 = {T_695,T_696};
+ assign T_699 = {1'h0,1'h1};
+ assign T_700 = {3'h7,T_699};
+ assign T_702 = {T_689,1'h1};
+ assign T_704 = {T_689,1'h1};
+ assign T_706 = {1'h0,3'h7};
+ assign T_707 = {1'h0,1'h1};
+ assign T_708 = {T_706,T_707};
+ assign T_710 = {5'h0,1'h1};
+ assign T_712 = {5'h1,1'h1};
+ assign T_713 = 3'h6 == 3'h3;
+ assign T_714 = T_713 ? T_712 : 1'h0;
+ assign T_715 = 3'h5 == 3'h3;
+ assign T_716 = T_715 ? T_710 : T_714;
+ assign T_717 = 3'h4 == 3'h3;
+ assign T_718 = T_717 ? T_708 : T_716;
+ assign T_719 = 3'h3 == 3'h3;
+ assign T_720 = T_719 ? T_704 : T_718;
+ assign T_721 = 3'h2 == 3'h3;
+ assign T_722 = T_721 ? T_702 : T_720;
+ assign T_723 = 3'h1 == 3'h3;
+ assign T_724 = T_723 ? T_700 : T_722;
+ assign T_725 = 3'h0 == 3'h3;
+ assign T_726 = T_725 ? T_697 : T_724;
+ assign oacq_probe_addr_block = io_inner_release_bits_addr_block;
+ assign oacq_probe_client_xact_id = 3'h6;
+ assign oacq_probe_addr_beat = io_inner_release_bits_addr_beat;
+ assign oacq_probe_is_builtin_type = 1'h1;
+ assign oacq_probe_a_type = 3'h3;
+ assign oacq_probe_union = T_726;
+ assign oacq_probe_data = io_inner_release_bits_data;
+ assign T_744 = xact_union[12:9];
+ assign T_745 = T_744[3];
+ assign T_747 = 1'h1 << T_745;
+ assign T_749 = xact_a_type == 3'h4;
+ assign T_750 = xact_is_builtin_type & T_749;
+ assign T_751 = T_747[0];
+ assign T_752 = T_747[1];
+ assign T_754_0 = T_751;
+ assign T_754_1 = T_752;
+ assign T_759 = 8'h0 - T_754_0;
+ assign T_760 = T_759[7:0];
+ assign T_762 = 8'h0 - T_754_1;
+ assign T_763 = T_762[7:0];
+ assign T_765_0 = T_760;
+ assign T_765_1 = T_763;
+ assign T_769 = {T_765_1,T_765_0};
+ assign T_771 = xact_a_type == 3'h3;
+ assign T_772 = xact_is_builtin_type & T_771;
+ assign T_774 = xact_a_type == 3'h2;
+ assign T_775 = xact_is_builtin_type & T_774;
+ assign T_776 = T_772 | T_775;
+ assign T_777 = xact_union[16:1];
+ assign T_779 = T_776 ? T_777 : 16'h0;
+ assign T_780 = T_750 ? T_769 : T_779;
+ assign T_788 = {1'h0,3'h7};
+ assign T_789 = {1'h0,1'h1};
+ assign T_790 = {T_788,T_789};
+ assign T_792 = {1'h0,1'h1};
+ assign T_793 = {3'h7,T_792};
+ assign T_795 = {T_780,1'h1};
+ assign T_797 = {T_780,1'h1};
+ assign T_799 = {1'h0,3'h7};
+ assign T_800 = {1'h0,1'h1};
+ assign T_801 = {T_799,T_800};
+ assign T_803 = {5'h0,1'h1};
+ assign T_805 = {5'h1,1'h1};
+ assign T_806 = 3'h6 == 3'h2;
+ assign T_807 = T_806 ? T_805 : 1'h0;
+ assign T_808 = 3'h5 == 3'h2;
+ assign T_809 = T_808 ? T_803 : T_807;
+ assign T_810 = 3'h4 == 3'h2;
+ assign T_811 = T_810 ? T_801 : T_809;
+ assign T_812 = 3'h3 == 3'h2;
+ assign T_813 = T_812 ? T_797 : T_811;
+ assign T_814 = 3'h2 == 3'h2;
+ assign T_815 = T_814 ? T_795 : T_813;
+ assign T_816 = 3'h1 == 3'h2;
+ assign T_817 = T_816 ? T_793 : T_815;
+ assign T_818 = 3'h0 == 3'h2;
+ assign T_819 = T_818 ? T_790 : T_817;
+ assign oacq_write_beat_addr_block = xact_addr_block;
+ assign oacq_write_beat_client_xact_id = 3'h6;
+ assign oacq_write_beat_addr_beat = xact_addr_beat;
+ assign oacq_write_beat_is_builtin_type = 1'h1;
+ assign oacq_write_beat_a_type = 3'h2;
+ assign oacq_write_beat_union = T_819;
+ assign oacq_write_beat_data = xact_data_buffer_0;
+ assign T_846 = {1'h0,3'h7};
+ assign T_847 = {1'h0,1'h1};
+ assign T_848 = {T_846,T_847};
+ assign T_850 = {1'h0,1'h1};
+ assign T_851 = {3'h7,T_850};
+ assign GEN_0 = GEN_45 ? xact_wmask_buffer_3 : GEN_46 ? xact_wmask_buffer_2 : GEN_47 ? xact_wmask_buffer_1 : xact_wmask_buffer_0;
+ assign T_853 = {GEN_0,1'h1};
+ assign GEN_1 = GEN_48 ? xact_wmask_buffer_3 : GEN_49 ? xact_wmask_buffer_2 : GEN_50 ? xact_wmask_buffer_1 : xact_wmask_buffer_0;
+ assign T_855 = {GEN_1,1'h1};
+ assign T_857 = {1'h0,3'h7};
+ assign T_858 = {1'h0,1'h1};
+ assign T_859 = {T_857,T_858};
+ assign T_861 = {5'h0,1'h1};
+ assign T_863 = {5'h1,1'h1};
+ assign T_864 = 3'h6 == 3'h3;
+ assign T_865 = T_864 ? T_863 : 1'h0;
+ assign T_866 = 3'h5 == 3'h3;
+ assign T_867 = T_866 ? T_861 : T_865;
+ assign T_868 = 3'h4 == 3'h3;
+ assign T_869 = T_868 ? T_859 : T_867;
+ assign T_870 = 3'h3 == 3'h3;
+ assign T_871 = T_870 ? T_855 : T_869;
+ assign T_872 = 3'h2 == 3'h3;
+ assign T_873 = T_872 ? T_853 : T_871;
+ assign T_874 = 3'h1 == 3'h3;
+ assign T_875 = T_874 ? T_851 : T_873;
+ assign T_876 = 3'h0 == 3'h3;
+ assign T_877 = T_876 ? T_848 : T_875;
+ assign oacq_write_block_addr_block = xact_addr_block;
+ assign oacq_write_block_client_xact_id = 3'h6;
+ assign oacq_write_block_addr_beat = oacq_data_cnt;
+ assign oacq_write_block_is_builtin_type = 1'h1;
+ assign oacq_write_block_a_type = 3'h3;
+ assign oacq_write_block_union = T_877;
+ assign oacq_write_block_data = GEN_2;
+ assign GEN_2 = GEN_51 ? xact_data_buffer_3 : GEN_52 ? xact_data_buffer_2 : GEN_53 ? xact_data_buffer_1 : xact_data_buffer_0;
+ assign T_895 = xact_union[12:9];
+ assign T_896 = xact_union[8:6];
+ assign T_904 = {T_895,T_896};
+ assign T_905 = {5'h0,1'h0};
+ assign T_906 = {T_904,T_905};
+ assign T_908 = {5'h0,1'h0};
+ assign T_909 = {T_896,T_908};
+ assign T_911 = {1'h0,1'h0};
+ assign T_913 = {1'h0,1'h0};
+ assign T_915 = {T_895,T_896};
+ assign T_916 = {5'h0,1'h0};
+ assign T_917 = {T_915,T_916};
+ assign T_919 = {5'h0,1'h0};
+ assign T_921 = {5'h1,1'h0};
+ assign T_922 = 3'h6 == 3'h0;
+ assign T_923 = T_922 ? T_921 : 1'h0;
+ assign T_924 = 3'h5 == 3'h0;
+ assign T_925 = T_924 ? T_919 : T_923;
+ assign T_926 = 3'h4 == 3'h0;
+ assign T_927 = T_926 ? T_917 : T_925;
+ assign T_928 = 3'h3 == 3'h0;
+ assign T_929 = T_928 ? T_913 : T_927;
+ assign T_930 = 3'h2 == 3'h0;
+ assign T_931 = T_930 ? T_911 : T_929;
+ assign T_932 = 3'h1 == 3'h0;
+ assign T_933 = T_932 ? T_909 : T_931;
+ assign T_934 = 3'h0 == 3'h0;
+ assign T_935 = T_934 ? T_906 : T_933;
+ assign oacq_read_beat_addr_block = xact_addr_block;
+ assign oacq_read_beat_client_xact_id = 3'h6;
+ assign oacq_read_beat_addr_beat = xact_addr_beat;
+ assign oacq_read_beat_is_builtin_type = 1'h1;
+ assign oacq_read_beat_a_type = 3'h0;
+ assign oacq_read_beat_union = T_935;
+ assign oacq_read_beat_data = 1'h0;
+ assign T_962 = {1'h0,3'h7};
+ assign T_963 = {5'h0,1'h1};
+ assign T_964 = {T_962,T_963};
+ assign T_966 = {5'h0,1'h1};
+ assign T_967 = {3'h7,T_966};
+ assign T_969 = {1'h0,1'h1};
+ assign T_971 = {1'h0,1'h1};
+ assign T_973 = {1'h0,3'h7};
+ assign T_974 = {5'h0,1'h1};
+ assign T_975 = {T_973,T_974};
+ assign T_977 = {5'h0,1'h1};
+ assign T_979 = {5'h1,1'h1};
+ assign T_980 = 3'h6 == 3'h1;
+ assign T_981 = T_980 ? T_979 : 1'h0;
+ assign T_982 = 3'h5 == 3'h1;
+ assign T_983 = T_982 ? T_977 : T_981;
+ assign T_984 = 3'h4 == 3'h1;
+ assign T_985 = T_984 ? T_975 : T_983;
+ assign T_986 = 3'h3 == 3'h1;
+ assign T_987 = T_986 ? T_971 : T_985;
+ assign T_988 = 3'h2 == 3'h1;
+ assign T_989 = T_988 ? T_969 : T_987;
+ assign T_990 = 3'h1 == 3'h1;
+ assign T_991 = T_990 ? T_967 : T_989;
+ assign T_992 = 3'h0 == 3'h1;
+ assign T_993 = T_992 ? T_964 : T_991;
+ assign oacq_read_block_addr_block = xact_addr_block;
+ assign oacq_read_block_client_xact_id = 3'h6;
+ assign oacq_read_block_addr_beat = 1'h0;
+ assign oacq_read_block_is_builtin_type = 1'h1;
+ assign oacq_read_block_a_type = 3'h1;
+ assign oacq_read_block_union = T_993;
+ assign oacq_read_block_data = 1'h0;
+ assign T_1011 = state == 1'h1;
+ assign T_1012 = state == 2'h3;
+ assign T_1013_addr_block = subblock_type ? oacq_write_beat_addr_block : oacq_write_block_addr_block;
+ assign T_1013_client_xact_id = subblock_type ? oacq_write_beat_client_xact_id : oacq_write_block_client_xact_id;
+ assign T_1013_addr_beat = subblock_type ? oacq_write_beat_addr_beat : oacq_write_block_addr_beat;
+ assign T_1013_is_builtin_type = subblock_type ? oacq_write_beat_is_builtin_type : oacq_write_block_is_builtin_type;
+ assign T_1013_a_type = subblock_type ? oacq_write_beat_a_type : oacq_write_block_a_type;
+ assign T_1013_union = subblock_type ? oacq_write_beat_union : oacq_write_block_union;
+ assign T_1013_data = subblock_type ? oacq_write_beat_data : oacq_write_block_data;
+ assign T_1021_addr_block = subblock_type ? oacq_read_beat_addr_block : oacq_read_block_addr_block;
+ assign T_1021_client_xact_id = subblock_type ? oacq_read_beat_client_xact_id : oacq_read_block_client_xact_id;
+ assign T_1021_addr_beat = subblock_type ? oacq_read_beat_addr_beat : oacq_read_block_addr_beat;
+ assign T_1021_is_builtin_type = subblock_type ? oacq_read_beat_is_builtin_type : oacq_read_block_is_builtin_type;
+ assign T_1021_a_type = subblock_type ? oacq_read_beat_a_type : oacq_read_block_a_type;
+ assign T_1021_union = subblock_type ? oacq_read_beat_union : oacq_read_block_union;
+ assign T_1021_data = subblock_type ? oacq_read_beat_data : oacq_read_block_data;
+ assign T_1029_addr_block = T_1012 ? T_1013_addr_block : T_1021_addr_block;
+ assign T_1029_client_xact_id = T_1012 ? T_1013_client_xact_id : T_1021_client_xact_id;
+ assign T_1029_addr_beat = T_1012 ? T_1013_addr_beat : T_1021_addr_beat;
+ assign T_1029_is_builtin_type = T_1012 ? T_1013_is_builtin_type : T_1021_is_builtin_type;
+ assign T_1029_a_type = T_1012 ? T_1013_a_type : T_1021_a_type;
+ assign T_1029_union = T_1012 ? T_1013_union : T_1021_union;
+ assign T_1029_data = T_1012 ? T_1013_data : T_1021_data;
+ assign T_1037_addr_block = T_1011 ? oacq_probe_addr_block : T_1029_addr_block;
+ assign T_1037_client_xact_id = T_1011 ? oacq_probe_client_xact_id : T_1029_client_xact_id;
+ assign T_1037_addr_beat = T_1011 ? oacq_probe_addr_beat : T_1029_addr_beat;
+ assign T_1037_is_builtin_type = T_1011 ? oacq_probe_is_builtin_type : T_1029_is_builtin_type;
+ assign T_1037_a_type = T_1011 ? oacq_probe_a_type : T_1029_a_type;
+ assign T_1037_union = T_1011 ? oacq_probe_union : T_1029_union;
+ assign T_1037_data = T_1011 ? oacq_probe_data : T_1029_data;
+ assign T_1054 = 3'h4 == xact_a_type;
+ assign T_1055 = T_1054 ? 1'h0 : 2'h2;
+ assign T_1056 = 3'h6 == xact_a_type;
+ assign T_1057 = T_1056 ? 1'h0 : T_1055;
+ assign T_1058 = 3'h5 == xact_a_type;
+ assign T_1059 = T_1058 ? 2'h2 : T_1057;
+ assign T_1060 = 3'h2 == xact_a_type;
+ assign T_1061 = T_1060 ? 1'h0 : T_1059;
+ assign T_1062 = 3'h0 == xact_a_type;
+ assign T_1063 = T_1062 ? 2'h2 : T_1061;
+ assign T_1064 = 3'h3 == xact_a_type;
+ assign T_1065 = T_1064 ? 1'h0 : T_1063;
+ assign T_1066 = 3'h1 == xact_a_type;
+ assign T_1067 = T_1066 ? 2'h2 : T_1065;
+ assign T_1068 = 1'h1 == xact_a_type;
+ assign T_1069 = T_1068 ? 1'h0 : 2'h2;
+ assign T_1070 = 1'h0 == xact_a_type;
+ assign T_1071 = T_1070 ? 1'h1 : T_1069;
+ assign T_1072 = xact_is_builtin_type ? T_1067 : T_1071;
+ assign T_1077_addr_block = xact_addr_block;
+ assign T_1077_p_type = T_1072;
+ assign T_1077_client_id = 1'h0;
+ assign T_1100 = 3'h6 == xact_a_type;
+ assign T_1101 = T_1100 ? 3'h1 : 3'h3;
+ assign T_1102 = 3'h5 == xact_a_type;
+ assign T_1103 = T_1102 ? 3'h1 : T_1101;
+ assign T_1104 = 3'h4 == xact_a_type;
+ assign T_1105 = T_1104 ? 3'h4 : T_1103;
+ assign T_1106 = 3'h3 == xact_a_type;
+ assign T_1107 = T_1106 ? 3'h3 : T_1105;
+ assign T_1108 = 3'h2 == xact_a_type;
+ assign T_1109 = T_1108 ? 3'h3 : T_1107;
+ assign T_1110 = 3'h1 == xact_a_type;
+ assign T_1111 = T_1110 ? 3'h5 : T_1109;
+ assign T_1112 = 3'h0 == xact_a_type;
+ assign T_1113 = T_1112 ? 3'h4 : T_1111;
+ assign T_1114 = xact_a_type == 1'h0;
+ assign T_1117 = 1'h0 == 1'h0;
+ assign T_1118 = T_1117 ? 1'h0 : 1'h1;
+ assign T_1119 = T_1114 ? T_1118 : 1'h1;
+ assign T_1120 = xact_is_builtin_type ? T_1113 : T_1119;
+ assign T_1129_addr_beat = 1'h0;
+ assign T_1129_client_xact_id = xact_client_xact_id;
+ assign T_1129_manager_xact_id = 3'h6;
+ assign T_1129_is_builtin_type = xact_is_builtin_type;
+ assign T_1129_g_type = T_1120;
+ assign T_1129_data = 1'h0;
+ assign T_1129_client_id = xact_client_id;
+ assign T_1140 = state != 1'h0;
+ assign T_1141 = T_1140 & collect_iacq_data;
+ assign T_1142 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_1143 = T_1141 & T_1142;
+ assign T_1144 = io_inner_acquire_bits_client_id != xact_client_id;
+ assign T_1145 = T_1143 & T_1144;
+ assign T_1147 = T_1145 == 1'h0;
+ assign T_1149 = reset == 1'h0;
+ assign T_1151 = T_1147 == 1'h0;
+ assign T_1153 = reset == 1'h0;
+ assign T_1154 = state != 1'h0;
+ assign T_1155 = T_1154 & collect_iacq_data;
+ assign T_1156 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_1157 = T_1155 & T_1156;
+ assign T_1158 = io_inner_acquire_bits_client_xact_id != xact_client_xact_id;
+ assign T_1159 = T_1157 & T_1158;
+ assign T_1161 = T_1159 == 1'h0;
+ assign T_1163 = reset == 1'h0;
+ assign T_1165 = T_1161 == 1'h0;
+ assign T_1167 = reset == 1'h0;
+ assign T_1168 = state == 1'h0;
+ assign T_1169 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_1170 = T_1168 & T_1169;
+ assign T_1172 = 1'h1 & io_inner_acquire_bits_is_builtin_type;
+ assign T_1175_0 = 3'h3;
+ assign T_1178 = T_1175_0 == io_inner_acquire_bits_a_type;
+ assign T_1180 = 1'h0 | T_1178;
+ assign T_1181 = T_1172 & T_1180;
+ assign T_1182 = T_1170 & T_1181;
+ assign T_1184 = io_inner_acquire_bits_addr_beat != 1'h0;
+ assign T_1185 = T_1182 & T_1184;
+ assign T_1187 = T_1185 == 1'h0;
+ assign T_1189 = reset == 1'h0;
+ assign T_1191 = T_1187 == 1'h0;
+ assign T_1193 = reset == 1'h0;
+ assign GEN_3 = io_inner_acquire_bits_data;
+ assign T_1197 = io_inner_acquire_bits_union[12:9];
+ assign T_1198 = T_1197[3];
+ assign T_1200 = 1'h1 << T_1198;
+ assign T_1202 = io_inner_acquire_bits_a_type == 3'h4;
+ assign T_1203 = io_inner_acquire_bits_is_builtin_type & T_1202;
+ assign T_1204 = T_1200[0];
+ assign T_1205 = T_1200[1];
+ assign T_1207_0 = T_1204;
+ assign T_1207_1 = T_1205;
+ assign T_1212 = 8'h0 - T_1207_0;
+ assign T_1213 = T_1212[7:0];
+ assign T_1215 = 8'h0 - T_1207_1;
+ assign T_1216 = T_1215[7:0];
+ assign T_1218_0 = T_1213;
+ assign T_1218_1 = T_1216;
+ assign T_1222 = {T_1218_1,T_1218_0};
+ assign T_1224 = io_inner_acquire_bits_a_type == 3'h3;
+ assign T_1225 = io_inner_acquire_bits_is_builtin_type & T_1224;
+ assign T_1227 = io_inner_acquire_bits_a_type == 3'h2;
+ assign T_1228 = io_inner_acquire_bits_is_builtin_type & T_1227;
+ assign T_1229 = T_1225 | T_1228;
+ assign T_1230 = io_inner_acquire_bits_union[16:1];
+ assign T_1232 = T_1229 ? T_1230 : 16'h0;
+ assign T_1233 = T_1203 ? T_1222 : T_1232;
+ assign GEN_4 = T_1233;
+ assign T_1236 = 1'h1 << io_inner_acquire_bits_addr_beat;
+ assign T_1237 = iacq_data_valid | T_1236;
+ assign T_1238 = ~ iacq_data_valid;
+ assign T_1239 = T_1238 | T_1236;
+ assign T_1240 = ~ T_1239;
+ assign T_1241 = 1'h1 ? T_1237 : T_1240;
+ assign T_1245 = 1'h0 == state;
+ assign GEN_5 = io_inner_acquire_bits_data;
+ assign T_1251 = io_inner_acquire_bits_union[12:9];
+ assign T_1252 = T_1251[3];
+ assign T_1254 = 1'h1 << T_1252;
+ assign T_1256 = io_inner_acquire_bits_a_type == 3'h4;
+ assign T_1257 = io_inner_acquire_bits_is_builtin_type & T_1256;
+ assign T_1258 = T_1254[0];
+ assign T_1259 = T_1254[1];
+ assign T_1261_0 = T_1258;
+ assign T_1261_1 = T_1259;
+ assign T_1266 = 8'h0 - T_1261_0;
+ assign T_1267 = T_1266[7:0];
+ assign T_1269 = 8'h0 - T_1261_1;
+ assign T_1270 = T_1269[7:0];
+ assign T_1272_0 = T_1267;
+ assign T_1272_1 = T_1270;
+ assign T_1276 = {T_1272_1,T_1272_0};
+ assign T_1278 = io_inner_acquire_bits_a_type == 3'h3;
+ assign T_1279 = io_inner_acquire_bits_is_builtin_type & T_1278;
+ assign T_1281 = io_inner_acquire_bits_a_type == 3'h2;
+ assign T_1282 = io_inner_acquire_bits_is_builtin_type & T_1281;
+ assign T_1283 = T_1279 | T_1282;
+ assign T_1284 = io_inner_acquire_bits_union[16:1];
+ assign T_1286 = T_1283 ? T_1284 : 16'h0;
+ assign T_1287 = T_1257 ? T_1276 : T_1286;
+ assign GEN_6 = T_1287;
+ assign T_1289 = 1'h1 & io_inner_acquire_bits_is_builtin_type;
+ assign T_1292_0 = 3'h3;
+ assign T_1295 = T_1292_0 == io_inner_acquire_bits_a_type;
+ assign T_1297 = 1'h0 | T_1295;
+ assign T_1298 = T_1289 & T_1297;
+ assign T_1303_0 = 3'h2;
+ assign T_1303_1 = 3'h3;
+ assign T_1303_2 = 3'h4;
+ assign T_1308 = T_1303_0 == io_inner_acquire_bits_a_type;
+ assign T_1309 = T_1303_1 == io_inner_acquire_bits_a_type;
+ assign T_1310 = T_1303_2 == io_inner_acquire_bits_a_type;
+ assign T_1312 = 1'h0 | T_1308;
+ assign T_1313 = T_1312 | T_1309;
+ assign T_1314 = T_1313 | T_1310;
+ assign T_1315 = io_inner_acquire_bits_is_builtin_type & T_1314;
+ assign T_1316 = T_1315 << io_inner_acquire_bits_addr_beat;
+ assign T_1318 = mask_incoherent != 1'h0;
+ assign T_1319 = mask_incoherent[0];
+ assign T_1320 = mask_incoherent[1];
+ assign T_1321 = mask_incoherent[2];
+ assign T_1322 = mask_incoherent[3];
+ assign T_1324 = {1'h0,T_1320};
+ assign T_1325 = T_1319 + T_1324;
+ assign T_1326 = T_1325[1:0];
+ assign T_1329 = {1'h0,T_1322};
+ assign T_1330 = T_1321 + T_1329;
+ assign T_1331 = T_1330[1:0];
+ assign T_1332 = {1'h0,T_1331};
+ assign T_1333 = T_1326 + T_1332;
+ assign T_1334 = T_1333[2:0];
+ assign T_1335 = pending_outer_read_ ? 2'h2 : 3'h4;
+ assign T_1336 = pending_outer_write_ ? 2'h3 : T_1335;
+ assign T_1337 = T_1318 ? 1'h1 : T_1336;
+ assign T_1338 = 1'h1 == state;
+ assign T_1340 = pending_probes != 1'h0;
+ assign T_1342 = 1'h1 << 1'h0;
+ assign T_1343 = ~ T_1342;
+ assign T_1344 = pending_probes & T_1343;
+ assign T_1346_0 = 1'h0;
+ assign T_1346_1 = 1'h1;
+ assign T_1346_2 = 2'h2;
+ assign T_1351 = T_1346_0 == io_inner_release_bits_r_type;
+ assign T_1352 = T_1346_1 == io_inner_release_bits_r_type;
+ assign T_1353 = T_1346_2 == io_inner_release_bits_r_type;
+ assign T_1355 = 1'h0 | T_1351;
+ assign T_1356 = T_1355 | T_1352;
+ assign T_1357 = T_1356 | T_1353;
+ assign T_1359 = T_1357 == 1'h0;
+ assign T_1360 = T_1359 | io_outer_acquire_ready;
+ assign T_1362_0 = 1'h0;
+ assign T_1362_1 = 1'h1;
+ assign T_1362_2 = 2'h2;
+ assign T_1367 = T_1362_0 == io_inner_release_bits_r_type;
+ assign T_1368 = T_1362_1 == io_inner_release_bits_r_type;
+ assign T_1369 = T_1362_2 == io_inner_release_bits_r_type;
+ assign T_1371 = 1'h0 | T_1367;
+ assign T_1372 = T_1371 | T_1368;
+ assign T_1373 = T_1372 | T_1369;
+ assign T_1377 = release_count - 1'h1;
+ assign T_1378 = T_1377[0:0];
+ assign T_1380 = release_count == 1'h1;
+ assign T_1381 = pending_outer_read ? 2'h2 : 3'h4;
+ assign T_1382 = pending_outer_write ? 2'h3 : T_1381;
+ assign T_1384 = T_1373 == 1'h0;
+ assign T_1386 = release_count - 1'h1;
+ assign T_1387 = T_1386[0:0];
+ assign T_1389 = release_count == 1'h1;
+ assign T_1390 = pending_outer_read ? 2'h2 : 3'h4;
+ assign T_1391 = pending_outer_write ? 2'h3 : T_1390;
+ assign T_1392 = 2'h3 == state;
+ assign T_1394 = pending_ognt_ack == 1'h0;
+ assign T_1396 = collect_iacq_data == 1'h0;
+ assign T_1397 = iacq_data_valid >> oacq_data_cnt;
+ assign T_1398 = T_1397[0];
+ assign T_1399 = T_1396 | T_1398;
+ assign T_1400 = T_1394 & T_1399;
+ assign T_1402 = pending_outer_read ? 2'h2 : 3'h5;
+ assign T_1403 = 2'h2 == state;
+ assign T_1405 = pending_ognt_ack == 1'h0;
+ assign T_1406 = io_outer_acquire_ready & io_outer_acquire_valid;
+ assign T_1407 = 3'h5 == state;
+ assign T_1410 = 1'h0 == 1'h0;
+ assign T_1412 = io_inner_grant_bits_g_type == 3'h0;
+ assign T_1413 = io_inner_grant_bits_is_builtin_type & T_1412;
+ assign T_1415 = T_1413 == 1'h0;
+ assign T_1416 = T_1410 & T_1415;
+ assign T_1417 = T_1416 ? 3'h6 : 1'h0;
+ assign T_1418 = 3'h4 == state;
+ assign T_1422 = 1'h0 == 1'h0;
+ assign T_1424 = io_inner_grant_bits_g_type == 3'h0;
+ assign T_1425 = io_inner_grant_bits_is_builtin_type & T_1424;
+ assign T_1427 = T_1425 == 1'h0;
+ assign T_1428 = T_1422 & T_1427;
+ assign T_1429 = T_1428 ? 3'h6 : 1'h0;
+ assign T_1430 = 3'h6 == state;
+ assign GEN_9 = T_325 & T_327;
+ assign GEN_10 = T_1149 & T_1151;
+ assign GEN_11 = T_1163 & T_1165;
+ assign GEN_12 = T_1189 & T_1191;
+ assign GEN_13 = 1'h0 == 1'h0;
+ assign GEN_14 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_15 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_16 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_17 = 1'h1 == 1'h0;
+ assign GEN_18 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_19 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_20 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_21 = 2'h2 == 1'h0;
+ assign GEN_22 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_23 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_24 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_25 = 2'h3 == 1'h0;
+ assign GEN_26 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_27 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_28 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_29 = 1'h0 == 1'h0;
+ assign GEN_30 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_31 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_32 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_33 = 1'h1 == 1'h0;
+ assign GEN_34 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_35 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_36 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_37 = 2'h2 == 1'h0;
+ assign GEN_38 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_39 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_40 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_41 = 2'h3 == 1'h0;
+ assign GEN_42 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_43 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_44 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_45 = 2'h3 == oacq_data_cnt;
+ assign GEN_46 = 2'h2 == oacq_data_cnt;
+ assign GEN_47 = 1'h1 == oacq_data_cnt;
+ assign GEN_48 = 2'h3 == oacq_data_cnt;
+ assign GEN_49 = 2'h2 == oacq_data_cnt;
+ assign GEN_50 = 1'h1 == oacq_data_cnt;
+ assign GEN_51 = 2'h3 == oacq_data_cnt;
+ assign GEN_52 = 2'h2 == oacq_data_cnt;
+ assign GEN_53 = 1'h1 == oacq_data_cnt;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ state = {1{$random}};
+ xact_addr_block = {1{$random}};
+ xact_client_xact_id = {1{$random}};
+ xact_addr_beat = {1{$random}};
+ xact_is_builtin_type = {1{$random}};
+ xact_a_type = {1{$random}};
+ xact_union = {1{$random}};
+ xact_data_buffer_0 = {1{$random}};
+ xact_data_buffer_1 = {1{$random}};
+ xact_data_buffer_2 = {1{$random}};
+ xact_data_buffer_3 = {1{$random}};
+ xact_wmask_buffer_0 = {1{$random}};
+ xact_wmask_buffer_1 = {1{$random}};
+ xact_wmask_buffer_2 = {1{$random}};
+ xact_wmask_buffer_3 = {1{$random}};
+ xact_client_id = {1{$random}};
+ release_count = {1{$random}};
+ pending_probes = {1{$random}};
+ collect_iacq_data = {1{$random}};
+ iacq_data_valid = {1{$random}};
+ T_371 = {1{$random}};
+ T_403 = {1{$random}};
+ T_441 = {1{$random}};
+ T_469 = {1{$random}};
+ T_504 = {1{$random}};
+ pending_ognt_ack = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1430) begin
+ if(io_inner_finish_valid) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1418) begin
+ if(io_inner_grant_ready) begin
+ state <= T_1429;
+ end else begin
+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
+ end else begin
+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end
+ end else begin
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+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end else begin
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+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
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+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
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+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
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+ end
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+ end
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+ state <= T_1402;
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ end else begin
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
+ end else begin
+ ;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ end else begin
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end
+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1418) begin
+ if(io_inner_grant_ready) begin
+ state <= T_1429;
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+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
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+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
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+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end
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+ end
+ end else begin
+ if(T_1392) begin
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+ state <= T_1402;
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ if(T_1380) begin
+ state <= T_1382;
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ end
+ end else begin
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
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+ end
+ end else begin
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+ if(T_1406) begin
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ state <= T_1337;
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+ end
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ state <= T_1337;
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+ end
+ end else begin
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
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+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
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+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1382;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_addr_block <= io_inner_acquire_bits_addr_block;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_client_xact_id <= io_inner_acquire_bits_client_xact_id;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_addr_beat <= io_inner_acquire_bits_addr_beat;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_is_builtin_type <= io_inner_acquire_bits_is_builtin_type;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_a_type <= io_inner_acquire_bits_a_type;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_union <= io_inner_acquire_bits_union;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_13) begin
+ xact_data_buffer_0 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_14) begin
+ xact_data_buffer_0 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_15) begin
+ xact_data_buffer_0 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_16) begin
+ xact_data_buffer_0 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_17) begin
+ xact_data_buffer_1 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_18) begin
+ xact_data_buffer_1 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_19) begin
+ xact_data_buffer_1 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_20) begin
+ xact_data_buffer_1 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_21) begin
+ xact_data_buffer_2 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_22) begin
+ xact_data_buffer_2 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_23) begin
+ xact_data_buffer_2 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_24) begin
+ xact_data_buffer_2 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_25) begin
+ xact_data_buffer_3 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_26) begin
+ xact_data_buffer_3 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_27) begin
+ xact_data_buffer_3 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_28) begin
+ xact_data_buffer_3 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_29) begin
+ xact_wmask_buffer_0 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_30) begin
+ xact_wmask_buffer_0 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_31) begin
+ xact_wmask_buffer_0 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_32) begin
+ xact_wmask_buffer_0 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_33) begin
+ xact_wmask_buffer_1 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_34) begin
+ xact_wmask_buffer_1 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_35) begin
+ xact_wmask_buffer_1 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_36) begin
+ xact_wmask_buffer_1 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_37) begin
+ xact_wmask_buffer_2 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_38) begin
+ xact_wmask_buffer_2 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_39) begin
+ xact_wmask_buffer_2 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_40) begin
+ xact_wmask_buffer_2 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_41) begin
+ xact_wmask_buffer_3 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_42) begin
+ xact_wmask_buffer_3 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_43) begin
+ xact_wmask_buffer_3 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_44) begin
+ xact_wmask_buffer_3 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_client_id <= io_inner_acquire_bits_client_id;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ release_count <= 1'h0;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ release_count <= T_1387;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ release_count <= T_1378;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ pending_probes <= 1'h0;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_probe_ready) begin
+ pending_probes <= T_1344;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ pending_probes <= mask_incoherent;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ pending_probes <= mask_incoherent;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ collect_iacq_data <= 1'h0;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ collect_iacq_data <= T_1298;
+ end else begin
+ if(collect_iacq_data) begin
+ if(iacq_data_done) begin
+ collect_iacq_data <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(iacq_data_done) begin
+ collect_iacq_data <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ iacq_data_valid <= 4'h0;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ iacq_data_valid <= T_1316;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ iacq_data_valid <= T_1241;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ iacq_data_valid <= T_1241;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ T_371 <= 2'h0;
+ end else begin
+ if(T_369) begin
+ T_371 <= T_380;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_403 <= 2'h0;
+ end else begin
+ if(T_401) begin
+ T_403 <= T_412;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_441 <= 2'h0;
+ end else begin
+ if(T_439) begin
+ T_441 <= T_450;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_469 <= 2'h0;
+ end else begin
+ if(T_467) begin
+ T_469 <= T_478;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_504 <= 2'h0;
+ end else begin
+ if(T_502) begin
+ T_504 <= T_513;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ pending_ognt_ack <= 1'h1;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ pending_ognt_ack <= 1'h1;
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ pending_ognt_ack <= 1'h1;
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ `ifndef SYNTHESIS
+ if(GEN_9 & T_329) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_325 & T_327) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_10 & T_1153) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_1149 & T_1151) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_11 & T_1167) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_1163 & T_1165) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_12 & T_1193) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_1189 & T_1191) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ end
+endmodule
+module BroadcastAcquireTracker_32(
+ input clk,
+ input reset,
+ output io_inner_acquire_ready,
+ input io_inner_acquire_valid,
+ input [25:0] io_inner_acquire_bits_addr_block,
+ input [1:0] io_inner_acquire_bits_client_xact_id,
+ input [1:0] io_inner_acquire_bits_addr_beat,
+ input io_inner_acquire_bits_is_builtin_type,
+ input [2:0] io_inner_acquire_bits_a_type,
+ input [16:0] io_inner_acquire_bits_union,
+ input [3:0] io_inner_acquire_bits_data,
+ input [1:0] io_inner_acquire_bits_client_id,
+ input io_inner_grant_ready,
+ output io_inner_grant_valid,
+ output [1:0] io_inner_grant_bits_addr_beat,
+ output [1:0] io_inner_grant_bits_client_xact_id,
+ output [3:0] io_inner_grant_bits_manager_xact_id,
+ output io_inner_grant_bits_is_builtin_type,
+ output [3:0] io_inner_grant_bits_g_type,
+ output [3:0] io_inner_grant_bits_data,
+ output [1:0] io_inner_grant_bits_client_id,
+ output io_inner_finish_ready,
+ input io_inner_finish_valid,
+ input [3:0] io_inner_finish_bits_manager_xact_id,
+ input io_inner_probe_ready,
+ output io_inner_probe_valid,
+ output [25:0] io_inner_probe_bits_addr_block,
+ output [1:0] io_inner_probe_bits_p_type,
+ output [1:0] io_inner_probe_bits_client_id,
+ output io_inner_release_ready,
+ input io_inner_release_valid,
+ input [1:0] io_inner_release_bits_addr_beat,
+ input [25:0] io_inner_release_bits_addr_block,
+ input [1:0] io_inner_release_bits_client_xact_id,
+ input io_inner_release_bits_voluntary,
+ input [2:0] io_inner_release_bits_r_type,
+ input [3:0] io_inner_release_bits_data,
+ input [1:0] io_inner_release_bits_client_id,
+ input io_incoherent_0,
+ input io_outer_acquire_ready,
+ output io_outer_acquire_valid,
+ output [25:0] io_outer_acquire_bits_addr_block,
+ output [3:0] io_outer_acquire_bits_client_xact_id,
+ output [1:0] io_outer_acquire_bits_addr_beat,
+ output io_outer_acquire_bits_is_builtin_type,
+ output [2:0] io_outer_acquire_bits_a_type,
+ output [16:0] io_outer_acquire_bits_union,
+ output [3:0] io_outer_acquire_bits_data,
+ output io_outer_grant_ready,
+ input io_outer_grant_valid,
+ input [1:0] io_outer_grant_bits_addr_beat,
+ input [3:0] io_outer_grant_bits_client_xact_id,
+ input io_outer_grant_bits_manager_xact_id,
+ input io_outer_grant_bits_is_builtin_type,
+ input [3:0] io_outer_grant_bits_g_type,
+ input [3:0] io_outer_grant_bits_data,
+ output io_has_acquire_conflict,
+ output io_has_acquire_match,
+ output io_has_release_match
+);
+ reg [2:0] state;
+ reg [25:0] xact_addr_block;
+ reg [1:0] xact_client_xact_id;
+ reg [1:0] xact_addr_beat;
+ reg xact_is_builtin_type;
+ reg [2:0] xact_a_type;
+ reg [16:0] xact_union;
+ reg [3:0] xact_data_buffer_0;
+ reg [3:0] xact_data_buffer_1;
+ reg [3:0] xact_data_buffer_2;
+ reg [3:0] xact_data_buffer_3;
+ reg [15:0] xact_wmask_buffer_0;
+ reg [15:0] xact_wmask_buffer_1;
+ reg [15:0] xact_wmask_buffer_2;
+ reg [15:0] xact_wmask_buffer_3;
+ reg [1:0] xact_client_id;
+ wire coh_sharers;
+ wire T_303;
+ wire T_304;
+ wire [2:0] T_309_0;
+ wire [2:0] T_309_1;
+ wire [2:0] T_309_2;
+ wire T_314;
+ wire T_315;
+ wire T_316;
+ wire T_318;
+ wire T_319;
+ wire T_320;
+ wire T_321;
+ wire T_323;
+ wire T_325;
+ wire T_327;
+ wire T_329;
+ reg release_count;
+ reg pending_probes;
+ wire T_334;
+ wire T_336_0;
+ wire GEN_7;
+ wire T_341;
+ wire [3:0] T_344;
+ wire [3:0] T_345;
+ wire T_346;
+ wire [3:0] T_347;
+ wire [3:0] T_348;
+ wire [3:0] mask_self;
+ wire T_350;
+ wire [3:0] mask_incoherent;
+ reg collect_iacq_data;
+ reg [3:0] iacq_data_valid;
+ wire T_356;
+ wire T_359;
+ wire [2:0] T_362_0;
+ wire T_365;
+ wire T_367;
+ wire T_368;
+ wire T_369;
+ reg [1:0] T_371;
+ wire T_373;
+ wire T_375;
+ wire [2:0] T_378;
+ wire [1:0] T_379;
+ wire [1:0] T_380;
+ wire T_381;
+ wire [1:0] T_382;
+ wire iacq_data_done;
+ wire T_384;
+ wire [1:0] T_388_0;
+ wire [1:0] T_388_1;
+ wire [1:0] T_388_2;
+ wire T_393;
+ wire T_394;
+ wire T_395;
+ wire T_397;
+ wire T_398;
+ wire T_399;
+ wire T_400;
+ wire T_401;
+ reg [1:0] T_403;
+ wire T_405;
+ wire T_407;
+ wire [2:0] T_410;
+ wire [1:0] T_411;
+ wire [1:0] T_412;
+ wire T_413;
+ wire [1:0] T_414;
+ wire irel_data_done;
+ wire T_417;
+ wire [2:0] T_421_0;
+ wire T_424;
+ wire T_426;
+ wire T_428_0;
+ wire T_428_1;
+ wire T_432;
+ wire T_433;
+ wire T_435;
+ wire T_436;
+ wire T_437;
+ wire T_438;
+ wire T_439;
+ reg [1:0] T_441;
+ wire T_443;
+ wire T_445;
+ wire [2:0] T_448;
+ wire [1:0] T_449;
+ wire [1:0] T_450;
+ wire T_451;
+ wire [1:0] ignt_data_cnt;
+ wire ignt_data_done;
+ wire T_455;
+ wire T_457;
+ wire [2:0] T_460_0;
+ wire T_463;
+ wire T_465;
+ wire T_466;
+ wire T_467;
+ reg [1:0] T_469;
+ wire T_471;
+ wire T_473;
+ wire [2:0] T_476;
+ wire [1:0] T_477;
+ wire [1:0] T_478;
+ wire T_479;
+ wire [1:0] oacq_data_cnt;
+ wire oacq_data_done;
+ wire T_482;
+ wire [2:0] T_487_0;
+ wire T_490;
+ wire T_492;
+ wire T_494_0;
+ wire T_497;
+ wire T_499;
+ wire T_500;
+ wire T_501;
+ wire T_502;
+ reg [1:0] T_504;
+ wire T_506;
+ wire T_508;
+ wire [2:0] T_511;
+ wire [1:0] T_512;
+ wire [1:0] T_513;
+ wire T_514;
+ wire [1:0] T_515;
+ wire ognt_data_done;
+ reg pending_ognt_ack;
+ wire [2:0] T_523_0;
+ wire [2:0] T_523_1;
+ wire [2:0] T_523_2;
+ wire T_528;
+ wire T_529;
+ wire T_530;
+ wire T_532;
+ wire T_533;
+ wire T_534;
+ wire pending_outer_write;
+ wire [2:0] T_540_0;
+ wire [2:0] T_540_1;
+ wire [2:0] T_540_2;
+ wire T_545;
+ wire T_546;
+ wire T_547;
+ wire T_549;
+ wire T_550;
+ wire T_551;
+ wire pending_outer_write_;
+ wire [2:0] T_556_0;
+ wire [2:0] T_556_1;
+ wire T_560;
+ wire T_561;
+ wire T_563;
+ wire T_564;
+ wire T_566_0;
+ wire T_566_1;
+ wire T_570;
+ wire T_571;
+ wire T_573;
+ wire T_574;
+ wire pending_outer_read;
+ wire T_594;
+ wire [2:0] T_595;
+ wire T_596;
+ wire [2:0] T_597;
+ wire T_598;
+ wire [2:0] T_599;
+ wire T_600;
+ wire [2:0] T_601;
+ wire T_602;
+ wire [2:0] T_603;
+ wire T_604;
+ wire [2:0] T_605;
+ wire T_606;
+ wire [2:0] T_607;
+ wire T_608;
+ wire T_611;
+ wire T_612;
+ wire T_613;
+ wire [2:0] T_614;
+ wire [1:0] T_623_addr_beat;
+ wire [1:0] T_623_client_xact_id;
+ wire [3:0] T_623_manager_xact_id;
+ wire T_623_is_builtin_type;
+ wire [3:0] T_623_g_type;
+ wire [3:0] T_623_data;
+ wire [1:0] T_623_client_id;
+ wire [2:0] T_634_0;
+ wire [2:0] T_634_1;
+ wire T_638;
+ wire T_639;
+ wire T_641;
+ wire T_642;
+ wire T_644_0;
+ wire T_644_1;
+ wire T_648;
+ wire T_649;
+ wire T_651;
+ wire T_652;
+ wire pending_outer_read_;
+ wire [2:0] T_658_0;
+ wire [2:0] T_658_1;
+ wire [2:0] T_658_2;
+ wire T_663;
+ wire T_664;
+ wire T_665;
+ wire T_667;
+ wire T_668;
+ wire T_669;
+ wire subblock_type;
+ wire T_671;
+ wire T_672;
+ wire T_673;
+ wire T_675;
+ wire T_676;
+ wire T_677;
+ wire T_678;
+ wire T_679;
+ wire T_681;
+ wire T_682;
+ wire T_683;
+ wire T_684;
+ wire [15:0] GEN_8;
+ wire [15:0] T_689;
+ wire [3:0] T_695;
+ wire [1:0] T_696;
+ wire [5:0] T_697;
+ wire [1:0] T_699;
+ wire [4:0] T_700;
+ wire [16:0] T_702;
+ wire [16:0] T_704;
+ wire [3:0] T_706;
+ wire [1:0] T_707;
+ wire [5:0] T_708;
+ wire [5:0] T_710;
+ wire [5:0] T_712;
+ wire T_713;
+ wire [5:0] T_714;
+ wire T_715;
+ wire [5:0] T_716;
+ wire T_717;
+ wire [5:0] T_718;
+ wire T_719;
+ wire [16:0] T_720;
+ wire T_721;
+ wire [16:0] T_722;
+ wire T_723;
+ wire [16:0] T_724;
+ wire T_725;
+ wire [16:0] T_726;
+ wire [25:0] oacq_probe_addr_block;
+ wire [3:0] oacq_probe_client_xact_id;
+ wire [1:0] oacq_probe_addr_beat;
+ wire oacq_probe_is_builtin_type;
+ wire [2:0] oacq_probe_a_type;
+ wire [16:0] oacq_probe_union;
+ wire [3:0] oacq_probe_data;
+ wire [3:0] T_744;
+ wire T_745;
+ wire [1:0] T_747;
+ wire T_749;
+ wire T_750;
+ wire T_751;
+ wire T_752;
+ wire T_754_0;
+ wire T_754_1;
+ wire [8:0] T_759;
+ wire [7:0] T_760;
+ wire [8:0] T_762;
+ wire [7:0] T_763;
+ wire [7:0] T_765_0;
+ wire [7:0] T_765_1;
+ wire [15:0] T_769;
+ wire T_771;
+ wire T_772;
+ wire T_774;
+ wire T_775;
+ wire T_776;
+ wire [15:0] T_777;
+ wire [15:0] T_779;
+ wire [15:0] T_780;
+ wire [3:0] T_788;
+ wire [1:0] T_789;
+ wire [5:0] T_790;
+ wire [1:0] T_792;
+ wire [4:0] T_793;
+ wire [16:0] T_795;
+ wire [16:0] T_797;
+ wire [3:0] T_799;
+ wire [1:0] T_800;
+ wire [5:0] T_801;
+ wire [5:0] T_803;
+ wire [5:0] T_805;
+ wire T_806;
+ wire [5:0] T_807;
+ wire T_808;
+ wire [5:0] T_809;
+ wire T_810;
+ wire [5:0] T_811;
+ wire T_812;
+ wire [16:0] T_813;
+ wire T_814;
+ wire [16:0] T_815;
+ wire T_816;
+ wire [16:0] T_817;
+ wire T_818;
+ wire [16:0] T_819;
+ wire [25:0] oacq_write_beat_addr_block;
+ wire [3:0] oacq_write_beat_client_xact_id;
+ wire [1:0] oacq_write_beat_addr_beat;
+ wire oacq_write_beat_is_builtin_type;
+ wire [2:0] oacq_write_beat_a_type;
+ wire [16:0] oacq_write_beat_union;
+ wire [3:0] oacq_write_beat_data;
+ wire [3:0] T_846;
+ wire [1:0] T_847;
+ wire [5:0] T_848;
+ wire [1:0] T_850;
+ wire [4:0] T_851;
+ wire [15:0] GEN_0;
+ wire [16:0] T_853;
+ wire [15:0] GEN_1;
+ wire [16:0] T_855;
+ wire [3:0] T_857;
+ wire [1:0] T_858;
+ wire [5:0] T_859;
+ wire [5:0] T_861;
+ wire [5:0] T_863;
+ wire T_864;
+ wire [5:0] T_865;
+ wire T_866;
+ wire [5:0] T_867;
+ wire T_868;
+ wire [5:0] T_869;
+ wire T_870;
+ wire [16:0] T_871;
+ wire T_872;
+ wire [16:0] T_873;
+ wire T_874;
+ wire [16:0] T_875;
+ wire T_876;
+ wire [16:0] T_877;
+ wire [25:0] oacq_write_block_addr_block;
+ wire [3:0] oacq_write_block_client_xact_id;
+ wire [1:0] oacq_write_block_addr_beat;
+ wire oacq_write_block_is_builtin_type;
+ wire [2:0] oacq_write_block_a_type;
+ wire [16:0] oacq_write_block_union;
+ wire [3:0] oacq_write_block_data;
+ wire [3:0] GEN_2;
+ wire [3:0] T_895;
+ wire [2:0] T_896;
+ wire [6:0] T_904;
+ wire [5:0] T_905;
+ wire [12:0] T_906;
+ wire [5:0] T_908;
+ wire [8:0] T_909;
+ wire [1:0] T_911;
+ wire [1:0] T_913;
+ wire [6:0] T_915;
+ wire [5:0] T_916;
+ wire [12:0] T_917;
+ wire [5:0] T_919;
+ wire [5:0] T_921;
+ wire T_922;
+ wire [5:0] T_923;
+ wire T_924;
+ wire [5:0] T_925;
+ wire T_926;
+ wire [12:0] T_927;
+ wire T_928;
+ wire [12:0] T_929;
+ wire T_930;
+ wire [12:0] T_931;
+ wire T_932;
+ wire [12:0] T_933;
+ wire T_934;
+ wire [12:0] T_935;
+ wire [25:0] oacq_read_beat_addr_block;
+ wire [3:0] oacq_read_beat_client_xact_id;
+ wire [1:0] oacq_read_beat_addr_beat;
+ wire oacq_read_beat_is_builtin_type;
+ wire [2:0] oacq_read_beat_a_type;
+ wire [16:0] oacq_read_beat_union;
+ wire [3:0] oacq_read_beat_data;
+ wire [3:0] T_962;
+ wire [5:0] T_963;
+ wire [9:0] T_964;
+ wire [5:0] T_966;
+ wire [8:0] T_967;
+ wire [1:0] T_969;
+ wire [1:0] T_971;
+ wire [3:0] T_973;
+ wire [5:0] T_974;
+ wire [9:0] T_975;
+ wire [5:0] T_977;
+ wire [5:0] T_979;
+ wire T_980;
+ wire [5:0] T_981;
+ wire T_982;
+ wire [5:0] T_983;
+ wire T_984;
+ wire [9:0] T_985;
+ wire T_986;
+ wire [9:0] T_987;
+ wire T_988;
+ wire [9:0] T_989;
+ wire T_990;
+ wire [9:0] T_991;
+ wire T_992;
+ wire [9:0] T_993;
+ wire [25:0] oacq_read_block_addr_block;
+ wire [3:0] oacq_read_block_client_xact_id;
+ wire [1:0] oacq_read_block_addr_beat;
+ wire oacq_read_block_is_builtin_type;
+ wire [2:0] oacq_read_block_a_type;
+ wire [16:0] oacq_read_block_union;
+ wire [3:0] oacq_read_block_data;
+ wire T_1011;
+ wire T_1012;
+ wire [25:0] T_1013_addr_block;
+ wire [3:0] T_1013_client_xact_id;
+ wire [1:0] T_1013_addr_beat;
+ wire T_1013_is_builtin_type;
+ wire [2:0] T_1013_a_type;
+ wire [16:0] T_1013_union;
+ wire [3:0] T_1013_data;
+ wire [25:0] T_1021_addr_block;
+ wire [3:0] T_1021_client_xact_id;
+ wire [1:0] T_1021_addr_beat;
+ wire T_1021_is_builtin_type;
+ wire [2:0] T_1021_a_type;
+ wire [16:0] T_1021_union;
+ wire [3:0] T_1021_data;
+ wire [25:0] T_1029_addr_block;
+ wire [3:0] T_1029_client_xact_id;
+ wire [1:0] T_1029_addr_beat;
+ wire T_1029_is_builtin_type;
+ wire [2:0] T_1029_a_type;
+ wire [16:0] T_1029_union;
+ wire [3:0] T_1029_data;
+ wire [25:0] T_1037_addr_block;
+ wire [3:0] T_1037_client_xact_id;
+ wire [1:0] T_1037_addr_beat;
+ wire T_1037_is_builtin_type;
+ wire [2:0] T_1037_a_type;
+ wire [16:0] T_1037_union;
+ wire [3:0] T_1037_data;
+ wire T_1054;
+ wire [1:0] T_1055;
+ wire T_1056;
+ wire [1:0] T_1057;
+ wire T_1058;
+ wire [1:0] T_1059;
+ wire T_1060;
+ wire [1:0] T_1061;
+ wire T_1062;
+ wire [1:0] T_1063;
+ wire T_1064;
+ wire [1:0] T_1065;
+ wire T_1066;
+ wire [1:0] T_1067;
+ wire T_1068;
+ wire [1:0] T_1069;
+ wire T_1070;
+ wire [1:0] T_1071;
+ wire [1:0] T_1072;
+ wire [25:0] T_1077_addr_block;
+ wire [1:0] T_1077_p_type;
+ wire [1:0] T_1077_client_id;
+ wire T_1100;
+ wire [2:0] T_1101;
+ wire T_1102;
+ wire [2:0] T_1103;
+ wire T_1104;
+ wire [2:0] T_1105;
+ wire T_1106;
+ wire [2:0] T_1107;
+ wire T_1108;
+ wire [2:0] T_1109;
+ wire T_1110;
+ wire [2:0] T_1111;
+ wire T_1112;
+ wire [2:0] T_1113;
+ wire T_1114;
+ wire T_1117;
+ wire T_1118;
+ wire T_1119;
+ wire [2:0] T_1120;
+ wire [1:0] T_1129_addr_beat;
+ wire [1:0] T_1129_client_xact_id;
+ wire [3:0] T_1129_manager_xact_id;
+ wire T_1129_is_builtin_type;
+ wire [3:0] T_1129_g_type;
+ wire [3:0] T_1129_data;
+ wire [1:0] T_1129_client_id;
+ wire T_1140;
+ wire T_1141;
+ wire T_1142;
+ wire T_1143;
+ wire T_1144;
+ wire T_1145;
+ wire T_1147;
+ wire T_1149;
+ wire T_1151;
+ wire T_1153;
+ wire T_1154;
+ wire T_1155;
+ wire T_1156;
+ wire T_1157;
+ wire T_1158;
+ wire T_1159;
+ wire T_1161;
+ wire T_1163;
+ wire T_1165;
+ wire T_1167;
+ wire T_1168;
+ wire T_1169;
+ wire T_1170;
+ wire T_1172;
+ wire [2:0] T_1175_0;
+ wire T_1178;
+ wire T_1180;
+ wire T_1181;
+ wire T_1182;
+ wire T_1184;
+ wire T_1185;
+ wire T_1187;
+ wire T_1189;
+ wire T_1191;
+ wire T_1193;
+ wire [3:0] GEN_3;
+ wire [3:0] T_1197;
+ wire T_1198;
+ wire [1:0] T_1200;
+ wire T_1202;
+ wire T_1203;
+ wire T_1204;
+ wire T_1205;
+ wire T_1207_0;
+ wire T_1207_1;
+ wire [8:0] T_1212;
+ wire [7:0] T_1213;
+ wire [8:0] T_1215;
+ wire [7:0] T_1216;
+ wire [7:0] T_1218_0;
+ wire [7:0] T_1218_1;
+ wire [15:0] T_1222;
+ wire T_1224;
+ wire T_1225;
+ wire T_1227;
+ wire T_1228;
+ wire T_1229;
+ wire [15:0] T_1230;
+ wire [15:0] T_1232;
+ wire [15:0] T_1233;
+ wire [15:0] GEN_4;
+ wire [3:0] T_1236;
+ wire [3:0] T_1237;
+ wire [3:0] T_1238;
+ wire [3:0] T_1239;
+ wire [3:0] T_1240;
+ wire [3:0] T_1241;
+ wire T_1245;
+ wire [3:0] GEN_5;
+ wire [3:0] T_1251;
+ wire T_1252;
+ wire [1:0] T_1254;
+ wire T_1256;
+ wire T_1257;
+ wire T_1258;
+ wire T_1259;
+ wire T_1261_0;
+ wire T_1261_1;
+ wire [8:0] T_1266;
+ wire [7:0] T_1267;
+ wire [8:0] T_1269;
+ wire [7:0] T_1270;
+ wire [7:0] T_1272_0;
+ wire [7:0] T_1272_1;
+ wire [15:0] T_1276;
+ wire T_1278;
+ wire T_1279;
+ wire T_1281;
+ wire T_1282;
+ wire T_1283;
+ wire [15:0] T_1284;
+ wire [15:0] T_1286;
+ wire [15:0] T_1287;
+ wire [15:0] GEN_6;
+ wire T_1289;
+ wire [2:0] T_1292_0;
+ wire T_1295;
+ wire T_1297;
+ wire T_1298;
+ wire [2:0] T_1303_0;
+ wire [2:0] T_1303_1;
+ wire [2:0] T_1303_2;
+ wire T_1308;
+ wire T_1309;
+ wire T_1310;
+ wire T_1312;
+ wire T_1313;
+ wire T_1314;
+ wire T_1315;
+ wire [3:0] T_1316;
+ wire T_1318;
+ wire T_1319;
+ wire T_1320;
+ wire T_1321;
+ wire T_1322;
+ wire [1:0] T_1324;
+ wire [2:0] T_1325;
+ wire [1:0] T_1326;
+ wire [1:0] T_1329;
+ wire [2:0] T_1330;
+ wire [1:0] T_1331;
+ wire [2:0] T_1332;
+ wire [3:0] T_1333;
+ wire [2:0] T_1334;
+ wire [2:0] T_1335;
+ wire [2:0] T_1336;
+ wire [2:0] T_1337;
+ wire T_1338;
+ wire T_1340;
+ wire [1:0] T_1342;
+ wire [1:0] T_1343;
+ wire [1:0] T_1344;
+ wire [1:0] T_1346_0;
+ wire [1:0] T_1346_1;
+ wire [1:0] T_1346_2;
+ wire T_1351;
+ wire T_1352;
+ wire T_1353;
+ wire T_1355;
+ wire T_1356;
+ wire T_1357;
+ wire T_1359;
+ wire T_1360;
+ wire [1:0] T_1362_0;
+ wire [1:0] T_1362_1;
+ wire [1:0] T_1362_2;
+ wire T_1367;
+ wire T_1368;
+ wire T_1369;
+ wire T_1371;
+ wire T_1372;
+ wire T_1373;
+ wire [1:0] T_1377;
+ wire T_1378;
+ wire T_1380;
+ wire [2:0] T_1381;
+ wire [2:0] T_1382;
+ wire T_1384;
+ wire [1:0] T_1386;
+ wire T_1387;
+ wire T_1389;
+ wire [2:0] T_1390;
+ wire [2:0] T_1391;
+ wire T_1392;
+ wire T_1394;
+ wire T_1396;
+ wire [3:0] T_1397;
+ wire T_1398;
+ wire T_1399;
+ wire T_1400;
+ wire [2:0] T_1402;
+ wire T_1403;
+ wire T_1405;
+ wire T_1406;
+ wire T_1407;
+ wire T_1410;
+ wire T_1412;
+ wire T_1413;
+ wire T_1415;
+ wire T_1416;
+ wire [2:0] T_1417;
+ wire T_1418;
+ wire T_1422;
+ wire T_1424;
+ wire T_1425;
+ wire T_1427;
+ wire T_1428;
+ wire [2:0] T_1429;
+ wire T_1430;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ wire GEN_17;
+ wire GEN_18;
+ wire GEN_19;
+ wire GEN_20;
+ wire GEN_21;
+ wire GEN_22;
+ wire GEN_23;
+ wire GEN_24;
+ wire GEN_25;
+ wire GEN_26;
+ wire GEN_27;
+ wire GEN_28;
+ wire GEN_29;
+ wire GEN_30;
+ wire GEN_31;
+ wire GEN_32;
+ wire GEN_33;
+ wire GEN_34;
+ wire GEN_35;
+ wire GEN_36;
+ wire GEN_37;
+ wire GEN_38;
+ wire GEN_39;
+ wire GEN_40;
+ wire GEN_41;
+ wire GEN_42;
+ wire GEN_43;
+ wire GEN_44;
+ wire GEN_45;
+ wire GEN_46;
+ wire GEN_47;
+ wire GEN_48;
+ wire GEN_49;
+ wire GEN_50;
+ wire GEN_51;
+ wire GEN_52;
+ wire GEN_53;
+ assign io_inner_acquire_ready = T_1245 ? 1'h1 : collect_iacq_data ? 1'h1 : 1'h0;
+ assign io_inner_grant_valid = T_1418 ? 1'h1 : T_1407 ? io_outer_grant_valid : 1'h0;
+ assign io_inner_grant_bits_addr_beat = T_1129_addr_beat;
+ assign io_inner_grant_bits_client_xact_id = T_1129_client_xact_id;
+ assign io_inner_grant_bits_manager_xact_id = T_1129_manager_xact_id;
+ assign io_inner_grant_bits_is_builtin_type = T_1129_is_builtin_type;
+ assign io_inner_grant_bits_g_type = T_1129_g_type;
+ assign io_inner_grant_bits_data = T_1129_data;
+ assign io_inner_grant_bits_client_id = T_1129_client_id;
+ assign io_inner_finish_ready = T_1430 ? 1'h1 : 1'h0;
+ assign io_inner_probe_valid = T_1338 ? T_1340 : 1'h0;
+ assign io_inner_probe_bits_addr_block = T_1077_addr_block;
+ assign io_inner_probe_bits_p_type = T_1077_p_type;
+ assign io_inner_probe_bits_client_id = T_1077_client_id;
+ assign io_inner_release_ready = T_1338 ? T_1360 : 1'h0;
+ assign io_outer_acquire_valid = T_1403 ? T_1405 : T_1392 ? T_1400 : T_1338 ? io_inner_release_valid ? T_1373 ? 1'h1 : 1'h0 : 1'h0 : 1'h0;
+ assign io_outer_acquire_bits_addr_block = T_1037_addr_block;
+ assign io_outer_acquire_bits_client_xact_id = T_1037_client_xact_id;
+ assign io_outer_acquire_bits_addr_beat = T_1037_addr_beat;
+ assign io_outer_acquire_bits_is_builtin_type = T_1037_is_builtin_type;
+ assign io_outer_acquire_bits_a_type = T_1037_a_type;
+ assign io_outer_acquire_bits_union = T_1037_union;
+ assign io_outer_acquire_bits_data = T_1037_data;
+ assign io_outer_grant_ready = T_1407 ? io_inner_grant_ready : pending_ognt_ack ? 1'h1 : 1'h0;
+ assign io_has_acquire_conflict = T_676;
+ assign io_has_acquire_match = T_678;
+ assign io_has_release_match = T_684;
+ assign coh_sharers = 1'h0;
+ assign T_303 = state != 1'h0;
+ assign T_304 = T_303 & xact_is_builtin_type;
+ assign T_309_0 = 3'h4;
+ assign T_309_1 = 3'h5;
+ assign T_309_2 = 3'h6;
+ assign T_314 = T_309_0 == xact_a_type;
+ assign T_315 = T_309_1 == xact_a_type;
+ assign T_316 = T_309_2 == xact_a_type;
+ assign T_318 = 1'h0 | T_314;
+ assign T_319 = T_318 | T_315;
+ assign T_320 = T_319 | T_316;
+ assign T_321 = T_304 & T_320;
+ assign T_323 = T_321 == 1'h0;
+ assign T_325 = reset == 1'h0;
+ assign T_327 = T_323 == 1'h0;
+ assign T_329 = reset == 1'h0;
+ assign T_334 = pending_probes;
+ assign T_336_0 = T_334;
+ assign GEN_7 = $signed(1'h1);
+ assign T_341 = $unsigned(GEN_7);
+ assign T_344 = 1'h1 << io_inner_acquire_bits_client_id;
+ assign T_345 = T_341 | T_344;
+ assign T_346 = ~ T_341;
+ assign T_347 = T_346 | T_344;
+ assign T_348 = ~ T_347;
+ assign mask_self = 1'h0 ? T_345 : T_348;
+ assign T_350 = ~ io_incoherent_0;
+ assign mask_incoherent = mask_self & T_350;
+ assign T_356 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_359 = 1'h1 & io_inner_acquire_bits_is_builtin_type;
+ assign T_362_0 = 3'h3;
+ assign T_365 = T_362_0 == io_inner_acquire_bits_a_type;
+ assign T_367 = 1'h0 | T_365;
+ assign T_368 = T_359 & T_367;
+ assign T_369 = T_356 & T_368;
+ assign T_373 = T_371 == 2'h3;
+ assign T_375 = 1'h0 & T_373;
+ assign T_378 = T_371 + 1'h1;
+ assign T_379 = T_378[1:0];
+ assign T_380 = T_375 ? 1'h0 : T_379;
+ assign T_381 = T_369 & T_373;
+ assign T_382 = T_368 ? T_371 : 1'h0;
+ assign iacq_data_done = T_368 ? T_381 : T_356;
+ assign T_384 = io_inner_release_ready & io_inner_release_valid;
+ assign T_388_0 = 1'h0;
+ assign T_388_1 = 1'h1;
+ assign T_388_2 = 2'h2;
+ assign T_393 = T_388_0 == io_inner_release_bits_r_type;
+ assign T_394 = T_388_1 == io_inner_release_bits_r_type;
+ assign T_395 = T_388_2 == io_inner_release_bits_r_type;
+ assign T_397 = 1'h0 | T_393;
+ assign T_398 = T_397 | T_394;
+ assign T_399 = T_398 | T_395;
+ assign T_400 = 1'h1 & T_399;
+ assign T_401 = T_384 & T_400;
+ assign T_405 = T_403 == 2'h3;
+ assign T_407 = 1'h0 & T_405;
+ assign T_410 = T_403 + 1'h1;
+ assign T_411 = T_410[1:0];
+ assign T_412 = T_407 ? 1'h0 : T_411;
+ assign T_413 = T_401 & T_405;
+ assign T_414 = T_400 ? T_403 : 1'h0;
+ assign irel_data_done = T_400 ? T_413 : T_384;
+ assign T_417 = io_inner_grant_ready & io_inner_grant_valid;
+ assign T_421_0 = 3'h5;
+ assign T_424 = T_421_0 == io_inner_grant_bits_g_type;
+ assign T_426 = 1'h0 | T_424;
+ assign T_428_0 = 1'h0;
+ assign T_428_1 = 1'h1;
+ assign T_432 = T_428_0 == io_inner_grant_bits_g_type;
+ assign T_433 = T_428_1 == io_inner_grant_bits_g_type;
+ assign T_435 = 1'h0 | T_432;
+ assign T_436 = T_435 | T_433;
+ assign T_437 = io_inner_grant_bits_is_builtin_type ? T_426 : T_436;
+ assign T_438 = 1'h1 & T_437;
+ assign T_439 = T_417 & T_438;
+ assign T_443 = T_441 == 2'h3;
+ assign T_445 = 1'h0 & T_443;
+ assign T_448 = T_441 + 1'h1;
+ assign T_449 = T_448[1:0];
+ assign T_450 = T_445 ? 1'h0 : T_449;
+ assign T_451 = T_439 & T_443;
+ assign ignt_data_cnt = T_438 ? T_441 : 1'h0;
+ assign ignt_data_done = T_438 ? T_451 : T_417;
+ assign T_455 = io_outer_acquire_ready & io_outer_acquire_valid;
+ assign T_457 = 1'h1 & io_outer_acquire_bits_is_builtin_type;
+ assign T_460_0 = 3'h3;
+ assign T_463 = T_460_0 == io_outer_acquire_bits_a_type;
+ assign T_465 = 1'h0 | T_463;
+ assign T_466 = T_457 & T_465;
+ assign T_467 = T_455 & T_466;
+ assign T_471 = T_469 == 2'h3;
+ assign T_473 = 1'h0 & T_471;
+ assign T_476 = T_469 + 1'h1;
+ assign T_477 = T_476[1:0];
+ assign T_478 = T_473 ? 1'h0 : T_477;
+ assign T_479 = T_467 & T_471;
+ assign oacq_data_cnt = T_466 ? T_469 : 1'h0;
+ assign oacq_data_done = T_466 ? T_479 : T_455;
+ assign T_482 = io_outer_grant_ready & io_outer_grant_valid;
+ assign T_487_0 = 3'h5;
+ assign T_490 = T_487_0 == io_outer_grant_bits_g_type;
+ assign T_492 = 1'h0 | T_490;
+ assign T_494_0 = 1'h0;
+ assign T_497 = T_494_0 == io_outer_grant_bits_g_type;
+ assign T_499 = 1'h0 | T_497;
+ assign T_500 = io_outer_grant_bits_is_builtin_type ? T_492 : T_499;
+ assign T_501 = 1'h1 & T_500;
+ assign T_502 = T_482 & T_501;
+ assign T_506 = T_504 == 2'h3;
+ assign T_508 = 1'h0 & T_506;
+ assign T_511 = T_504 + 1'h1;
+ assign T_512 = T_511[1:0];
+ assign T_513 = T_508 ? 1'h0 : T_512;
+ assign T_514 = T_502 & T_506;
+ assign T_515 = T_501 ? T_504 : 1'h0;
+ assign ognt_data_done = T_501 ? T_514 : T_482;
+ assign T_523_0 = 3'h2;
+ assign T_523_1 = 3'h3;
+ assign T_523_2 = 3'h4;
+ assign T_528 = T_523_0 == xact_a_type;
+ assign T_529 = T_523_1 == xact_a_type;
+ assign T_530 = T_523_2 == xact_a_type;
+ assign T_532 = 1'h0 | T_528;
+ assign T_533 = T_532 | T_529;
+ assign T_534 = T_533 | T_530;
+ assign pending_outer_write = xact_is_builtin_type & T_534;
+ assign T_540_0 = 3'h2;
+ assign T_540_1 = 3'h3;
+ assign T_540_2 = 3'h4;
+ assign T_545 = T_540_0 == io_inner_acquire_bits_a_type;
+ assign T_546 = T_540_1 == io_inner_acquire_bits_a_type;
+ assign T_547 = T_540_2 == io_inner_acquire_bits_a_type;
+ assign T_549 = 1'h0 | T_545;
+ assign T_550 = T_549 | T_546;
+ assign T_551 = T_550 | T_547;
+ assign pending_outer_write_ = io_inner_acquire_bits_is_builtin_type & T_551;
+ assign T_556_0 = 3'h5;
+ assign T_556_1 = 3'h4;
+ assign T_560 = T_556_0 == io_inner_grant_bits_g_type;
+ assign T_561 = T_556_1 == io_inner_grant_bits_g_type;
+ assign T_563 = 1'h0 | T_560;
+ assign T_564 = T_563 | T_561;
+ assign T_566_0 = 1'h0;
+ assign T_566_1 = 1'h1;
+ assign T_570 = T_566_0 == io_inner_grant_bits_g_type;
+ assign T_571 = T_566_1 == io_inner_grant_bits_g_type;
+ assign T_573 = 1'h0 | T_570;
+ assign T_574 = T_573 | T_571;
+ assign pending_outer_read = io_inner_grant_bits_is_builtin_type ? T_564 : T_574;
+ assign T_594 = 3'h6 == io_inner_acquire_bits_a_type;
+ assign T_595 = T_594 ? 3'h1 : 3'h3;
+ assign T_596 = 3'h5 == io_inner_acquire_bits_a_type;
+ assign T_597 = T_596 ? 3'h1 : T_595;
+ assign T_598 = 3'h4 == io_inner_acquire_bits_a_type;
+ assign T_599 = T_598 ? 3'h4 : T_597;
+ assign T_600 = 3'h3 == io_inner_acquire_bits_a_type;
+ assign T_601 = T_600 ? 3'h3 : T_599;
+ assign T_602 = 3'h2 == io_inner_acquire_bits_a_type;
+ assign T_603 = T_602 ? 3'h3 : T_601;
+ assign T_604 = 3'h1 == io_inner_acquire_bits_a_type;
+ assign T_605 = T_604 ? 3'h5 : T_603;
+ assign T_606 = 3'h0 == io_inner_acquire_bits_a_type;
+ assign T_607 = T_606 ? 3'h4 : T_605;
+ assign T_608 = io_inner_acquire_bits_a_type == 1'h0;
+ assign T_611 = 1'h0 == 1'h0;
+ assign T_612 = T_611 ? 1'h0 : 1'h1;
+ assign T_613 = T_608 ? T_612 : 1'h1;
+ assign T_614 = io_inner_acquire_bits_is_builtin_type ? T_607 : T_613;
+ assign T_623_addr_beat = 1'h0;
+ assign T_623_client_xact_id = io_inner_acquire_bits_client_xact_id;
+ assign T_623_manager_xact_id = 3'h7;
+ assign T_623_is_builtin_type = io_inner_acquire_bits_is_builtin_type;
+ assign T_623_g_type = T_614;
+ assign T_623_data = 1'h0;
+ assign T_623_client_id = io_inner_acquire_bits_client_id;
+ assign T_634_0 = 3'h5;
+ assign T_634_1 = 3'h4;
+ assign T_638 = T_634_0 == T_623_g_type;
+ assign T_639 = T_634_1 == T_623_g_type;
+ assign T_641 = 1'h0 | T_638;
+ assign T_642 = T_641 | T_639;
+ assign T_644_0 = 1'h0;
+ assign T_644_1 = 1'h1;
+ assign T_648 = T_644_0 == T_623_g_type;
+ assign T_649 = T_644_1 == T_623_g_type;
+ assign T_651 = 1'h0 | T_648;
+ assign T_652 = T_651 | T_649;
+ assign pending_outer_read_ = T_623_is_builtin_type ? T_642 : T_652;
+ assign T_658_0 = 3'h2;
+ assign T_658_1 = 3'h0;
+ assign T_658_2 = 3'h4;
+ assign T_663 = T_658_0 == xact_a_type;
+ assign T_664 = T_658_1 == xact_a_type;
+ assign T_665 = T_658_2 == xact_a_type;
+ assign T_667 = 1'h0 | T_663;
+ assign T_668 = T_667 | T_664;
+ assign T_669 = T_668 | T_665;
+ assign subblock_type = xact_is_builtin_type & T_669;
+ assign T_671 = xact_addr_block == io_inner_acquire_bits_addr_block;
+ assign T_672 = state != 1'h0;
+ assign T_673 = T_671 & T_672;
+ assign T_675 = collect_iacq_data == 1'h0;
+ assign T_676 = T_673 & T_675;
+ assign T_677 = xact_addr_block == io_inner_acquire_bits_addr_block;
+ assign T_678 = T_677 & collect_iacq_data;
+ assign T_679 = xact_addr_block == io_inner_release_bits_addr_block;
+ assign T_681 = io_inner_release_bits_voluntary == 1'h0;
+ assign T_682 = T_679 & T_681;
+ assign T_683 = state == 1'h1;
+ assign T_684 = T_682 & T_683;
+ assign GEN_8 = $signed(16'hffff);
+ assign T_689 = $unsigned(GEN_8);
+ assign T_695 = {1'h0,3'h7};
+ assign T_696 = {1'h0,1'h1};
+ assign T_697 = {T_695,T_696};
+ assign T_699 = {1'h0,1'h1};
+ assign T_700 = {3'h7,T_699};
+ assign T_702 = {T_689,1'h1};
+ assign T_704 = {T_689,1'h1};
+ assign T_706 = {1'h0,3'h7};
+ assign T_707 = {1'h0,1'h1};
+ assign T_708 = {T_706,T_707};
+ assign T_710 = {5'h0,1'h1};
+ assign T_712 = {5'h1,1'h1};
+ assign T_713 = 3'h6 == 3'h3;
+ assign T_714 = T_713 ? T_712 : 1'h0;
+ assign T_715 = 3'h5 == 3'h3;
+ assign T_716 = T_715 ? T_710 : T_714;
+ assign T_717 = 3'h4 == 3'h3;
+ assign T_718 = T_717 ? T_708 : T_716;
+ assign T_719 = 3'h3 == 3'h3;
+ assign T_720 = T_719 ? T_704 : T_718;
+ assign T_721 = 3'h2 == 3'h3;
+ assign T_722 = T_721 ? T_702 : T_720;
+ assign T_723 = 3'h1 == 3'h3;
+ assign T_724 = T_723 ? T_700 : T_722;
+ assign T_725 = 3'h0 == 3'h3;
+ assign T_726 = T_725 ? T_697 : T_724;
+ assign oacq_probe_addr_block = io_inner_release_bits_addr_block;
+ assign oacq_probe_client_xact_id = 3'h7;
+ assign oacq_probe_addr_beat = io_inner_release_bits_addr_beat;
+ assign oacq_probe_is_builtin_type = 1'h1;
+ assign oacq_probe_a_type = 3'h3;
+ assign oacq_probe_union = T_726;
+ assign oacq_probe_data = io_inner_release_bits_data;
+ assign T_744 = xact_union[12:9];
+ assign T_745 = T_744[3];
+ assign T_747 = 1'h1 << T_745;
+ assign T_749 = xact_a_type == 3'h4;
+ assign T_750 = xact_is_builtin_type & T_749;
+ assign T_751 = T_747[0];
+ assign T_752 = T_747[1];
+ assign T_754_0 = T_751;
+ assign T_754_1 = T_752;
+ assign T_759 = 8'h0 - T_754_0;
+ assign T_760 = T_759[7:0];
+ assign T_762 = 8'h0 - T_754_1;
+ assign T_763 = T_762[7:0];
+ assign T_765_0 = T_760;
+ assign T_765_1 = T_763;
+ assign T_769 = {T_765_1,T_765_0};
+ assign T_771 = xact_a_type == 3'h3;
+ assign T_772 = xact_is_builtin_type & T_771;
+ assign T_774 = xact_a_type == 3'h2;
+ assign T_775 = xact_is_builtin_type & T_774;
+ assign T_776 = T_772 | T_775;
+ assign T_777 = xact_union[16:1];
+ assign T_779 = T_776 ? T_777 : 16'h0;
+ assign T_780 = T_750 ? T_769 : T_779;
+ assign T_788 = {1'h0,3'h7};
+ assign T_789 = {1'h0,1'h1};
+ assign T_790 = {T_788,T_789};
+ assign T_792 = {1'h0,1'h1};
+ assign T_793 = {3'h7,T_792};
+ assign T_795 = {T_780,1'h1};
+ assign T_797 = {T_780,1'h1};
+ assign T_799 = {1'h0,3'h7};
+ assign T_800 = {1'h0,1'h1};
+ assign T_801 = {T_799,T_800};
+ assign T_803 = {5'h0,1'h1};
+ assign T_805 = {5'h1,1'h1};
+ assign T_806 = 3'h6 == 3'h2;
+ assign T_807 = T_806 ? T_805 : 1'h0;
+ assign T_808 = 3'h5 == 3'h2;
+ assign T_809 = T_808 ? T_803 : T_807;
+ assign T_810 = 3'h4 == 3'h2;
+ assign T_811 = T_810 ? T_801 : T_809;
+ assign T_812 = 3'h3 == 3'h2;
+ assign T_813 = T_812 ? T_797 : T_811;
+ assign T_814 = 3'h2 == 3'h2;
+ assign T_815 = T_814 ? T_795 : T_813;
+ assign T_816 = 3'h1 == 3'h2;
+ assign T_817 = T_816 ? T_793 : T_815;
+ assign T_818 = 3'h0 == 3'h2;
+ assign T_819 = T_818 ? T_790 : T_817;
+ assign oacq_write_beat_addr_block = xact_addr_block;
+ assign oacq_write_beat_client_xact_id = 3'h7;
+ assign oacq_write_beat_addr_beat = xact_addr_beat;
+ assign oacq_write_beat_is_builtin_type = 1'h1;
+ assign oacq_write_beat_a_type = 3'h2;
+ assign oacq_write_beat_union = T_819;
+ assign oacq_write_beat_data = xact_data_buffer_0;
+ assign T_846 = {1'h0,3'h7};
+ assign T_847 = {1'h0,1'h1};
+ assign T_848 = {T_846,T_847};
+ assign T_850 = {1'h0,1'h1};
+ assign T_851 = {3'h7,T_850};
+ assign GEN_0 = GEN_45 ? xact_wmask_buffer_3 : GEN_46 ? xact_wmask_buffer_2 : GEN_47 ? xact_wmask_buffer_1 : xact_wmask_buffer_0;
+ assign T_853 = {GEN_0,1'h1};
+ assign GEN_1 = GEN_48 ? xact_wmask_buffer_3 : GEN_49 ? xact_wmask_buffer_2 : GEN_50 ? xact_wmask_buffer_1 : xact_wmask_buffer_0;
+ assign T_855 = {GEN_1,1'h1};
+ assign T_857 = {1'h0,3'h7};
+ assign T_858 = {1'h0,1'h1};
+ assign T_859 = {T_857,T_858};
+ assign T_861 = {5'h0,1'h1};
+ assign T_863 = {5'h1,1'h1};
+ assign T_864 = 3'h6 == 3'h3;
+ assign T_865 = T_864 ? T_863 : 1'h0;
+ assign T_866 = 3'h5 == 3'h3;
+ assign T_867 = T_866 ? T_861 : T_865;
+ assign T_868 = 3'h4 == 3'h3;
+ assign T_869 = T_868 ? T_859 : T_867;
+ assign T_870 = 3'h3 == 3'h3;
+ assign T_871 = T_870 ? T_855 : T_869;
+ assign T_872 = 3'h2 == 3'h3;
+ assign T_873 = T_872 ? T_853 : T_871;
+ assign T_874 = 3'h1 == 3'h3;
+ assign T_875 = T_874 ? T_851 : T_873;
+ assign T_876 = 3'h0 == 3'h3;
+ assign T_877 = T_876 ? T_848 : T_875;
+ assign oacq_write_block_addr_block = xact_addr_block;
+ assign oacq_write_block_client_xact_id = 3'h7;
+ assign oacq_write_block_addr_beat = oacq_data_cnt;
+ assign oacq_write_block_is_builtin_type = 1'h1;
+ assign oacq_write_block_a_type = 3'h3;
+ assign oacq_write_block_union = T_877;
+ assign oacq_write_block_data = GEN_2;
+ assign GEN_2 = GEN_51 ? xact_data_buffer_3 : GEN_52 ? xact_data_buffer_2 : GEN_53 ? xact_data_buffer_1 : xact_data_buffer_0;
+ assign T_895 = xact_union[12:9];
+ assign T_896 = xact_union[8:6];
+ assign T_904 = {T_895,T_896};
+ assign T_905 = {5'h0,1'h0};
+ assign T_906 = {T_904,T_905};
+ assign T_908 = {5'h0,1'h0};
+ assign T_909 = {T_896,T_908};
+ assign T_911 = {1'h0,1'h0};
+ assign T_913 = {1'h0,1'h0};
+ assign T_915 = {T_895,T_896};
+ assign T_916 = {5'h0,1'h0};
+ assign T_917 = {T_915,T_916};
+ assign T_919 = {5'h0,1'h0};
+ assign T_921 = {5'h1,1'h0};
+ assign T_922 = 3'h6 == 3'h0;
+ assign T_923 = T_922 ? T_921 : 1'h0;
+ assign T_924 = 3'h5 == 3'h0;
+ assign T_925 = T_924 ? T_919 : T_923;
+ assign T_926 = 3'h4 == 3'h0;
+ assign T_927 = T_926 ? T_917 : T_925;
+ assign T_928 = 3'h3 == 3'h0;
+ assign T_929 = T_928 ? T_913 : T_927;
+ assign T_930 = 3'h2 == 3'h0;
+ assign T_931 = T_930 ? T_911 : T_929;
+ assign T_932 = 3'h1 == 3'h0;
+ assign T_933 = T_932 ? T_909 : T_931;
+ assign T_934 = 3'h0 == 3'h0;
+ assign T_935 = T_934 ? T_906 : T_933;
+ assign oacq_read_beat_addr_block = xact_addr_block;
+ assign oacq_read_beat_client_xact_id = 3'h7;
+ assign oacq_read_beat_addr_beat = xact_addr_beat;
+ assign oacq_read_beat_is_builtin_type = 1'h1;
+ assign oacq_read_beat_a_type = 3'h0;
+ assign oacq_read_beat_union = T_935;
+ assign oacq_read_beat_data = 1'h0;
+ assign T_962 = {1'h0,3'h7};
+ assign T_963 = {5'h0,1'h1};
+ assign T_964 = {T_962,T_963};
+ assign T_966 = {5'h0,1'h1};
+ assign T_967 = {3'h7,T_966};
+ assign T_969 = {1'h0,1'h1};
+ assign T_971 = {1'h0,1'h1};
+ assign T_973 = {1'h0,3'h7};
+ assign T_974 = {5'h0,1'h1};
+ assign T_975 = {T_973,T_974};
+ assign T_977 = {5'h0,1'h1};
+ assign T_979 = {5'h1,1'h1};
+ assign T_980 = 3'h6 == 3'h1;
+ assign T_981 = T_980 ? T_979 : 1'h0;
+ assign T_982 = 3'h5 == 3'h1;
+ assign T_983 = T_982 ? T_977 : T_981;
+ assign T_984 = 3'h4 == 3'h1;
+ assign T_985 = T_984 ? T_975 : T_983;
+ assign T_986 = 3'h3 == 3'h1;
+ assign T_987 = T_986 ? T_971 : T_985;
+ assign T_988 = 3'h2 == 3'h1;
+ assign T_989 = T_988 ? T_969 : T_987;
+ assign T_990 = 3'h1 == 3'h1;
+ assign T_991 = T_990 ? T_967 : T_989;
+ assign T_992 = 3'h0 == 3'h1;
+ assign T_993 = T_992 ? T_964 : T_991;
+ assign oacq_read_block_addr_block = xact_addr_block;
+ assign oacq_read_block_client_xact_id = 3'h7;
+ assign oacq_read_block_addr_beat = 1'h0;
+ assign oacq_read_block_is_builtin_type = 1'h1;
+ assign oacq_read_block_a_type = 3'h1;
+ assign oacq_read_block_union = T_993;
+ assign oacq_read_block_data = 1'h0;
+ assign T_1011 = state == 1'h1;
+ assign T_1012 = state == 2'h3;
+ assign T_1013_addr_block = subblock_type ? oacq_write_beat_addr_block : oacq_write_block_addr_block;
+ assign T_1013_client_xact_id = subblock_type ? oacq_write_beat_client_xact_id : oacq_write_block_client_xact_id;
+ assign T_1013_addr_beat = subblock_type ? oacq_write_beat_addr_beat : oacq_write_block_addr_beat;
+ assign T_1013_is_builtin_type = subblock_type ? oacq_write_beat_is_builtin_type : oacq_write_block_is_builtin_type;
+ assign T_1013_a_type = subblock_type ? oacq_write_beat_a_type : oacq_write_block_a_type;
+ assign T_1013_union = subblock_type ? oacq_write_beat_union : oacq_write_block_union;
+ assign T_1013_data = subblock_type ? oacq_write_beat_data : oacq_write_block_data;
+ assign T_1021_addr_block = subblock_type ? oacq_read_beat_addr_block : oacq_read_block_addr_block;
+ assign T_1021_client_xact_id = subblock_type ? oacq_read_beat_client_xact_id : oacq_read_block_client_xact_id;
+ assign T_1021_addr_beat = subblock_type ? oacq_read_beat_addr_beat : oacq_read_block_addr_beat;
+ assign T_1021_is_builtin_type = subblock_type ? oacq_read_beat_is_builtin_type : oacq_read_block_is_builtin_type;
+ assign T_1021_a_type = subblock_type ? oacq_read_beat_a_type : oacq_read_block_a_type;
+ assign T_1021_union = subblock_type ? oacq_read_beat_union : oacq_read_block_union;
+ assign T_1021_data = subblock_type ? oacq_read_beat_data : oacq_read_block_data;
+ assign T_1029_addr_block = T_1012 ? T_1013_addr_block : T_1021_addr_block;
+ assign T_1029_client_xact_id = T_1012 ? T_1013_client_xact_id : T_1021_client_xact_id;
+ assign T_1029_addr_beat = T_1012 ? T_1013_addr_beat : T_1021_addr_beat;
+ assign T_1029_is_builtin_type = T_1012 ? T_1013_is_builtin_type : T_1021_is_builtin_type;
+ assign T_1029_a_type = T_1012 ? T_1013_a_type : T_1021_a_type;
+ assign T_1029_union = T_1012 ? T_1013_union : T_1021_union;
+ assign T_1029_data = T_1012 ? T_1013_data : T_1021_data;
+ assign T_1037_addr_block = T_1011 ? oacq_probe_addr_block : T_1029_addr_block;
+ assign T_1037_client_xact_id = T_1011 ? oacq_probe_client_xact_id : T_1029_client_xact_id;
+ assign T_1037_addr_beat = T_1011 ? oacq_probe_addr_beat : T_1029_addr_beat;
+ assign T_1037_is_builtin_type = T_1011 ? oacq_probe_is_builtin_type : T_1029_is_builtin_type;
+ assign T_1037_a_type = T_1011 ? oacq_probe_a_type : T_1029_a_type;
+ assign T_1037_union = T_1011 ? oacq_probe_union : T_1029_union;
+ assign T_1037_data = T_1011 ? oacq_probe_data : T_1029_data;
+ assign T_1054 = 3'h4 == xact_a_type;
+ assign T_1055 = T_1054 ? 1'h0 : 2'h2;
+ assign T_1056 = 3'h6 == xact_a_type;
+ assign T_1057 = T_1056 ? 1'h0 : T_1055;
+ assign T_1058 = 3'h5 == xact_a_type;
+ assign T_1059 = T_1058 ? 2'h2 : T_1057;
+ assign T_1060 = 3'h2 == xact_a_type;
+ assign T_1061 = T_1060 ? 1'h0 : T_1059;
+ assign T_1062 = 3'h0 == xact_a_type;
+ assign T_1063 = T_1062 ? 2'h2 : T_1061;
+ assign T_1064 = 3'h3 == xact_a_type;
+ assign T_1065 = T_1064 ? 1'h0 : T_1063;
+ assign T_1066 = 3'h1 == xact_a_type;
+ assign T_1067 = T_1066 ? 2'h2 : T_1065;
+ assign T_1068 = 1'h1 == xact_a_type;
+ assign T_1069 = T_1068 ? 1'h0 : 2'h2;
+ assign T_1070 = 1'h0 == xact_a_type;
+ assign T_1071 = T_1070 ? 1'h1 : T_1069;
+ assign T_1072 = xact_is_builtin_type ? T_1067 : T_1071;
+ assign T_1077_addr_block = xact_addr_block;
+ assign T_1077_p_type = T_1072;
+ assign T_1077_client_id = 1'h0;
+ assign T_1100 = 3'h6 == xact_a_type;
+ assign T_1101 = T_1100 ? 3'h1 : 3'h3;
+ assign T_1102 = 3'h5 == xact_a_type;
+ assign T_1103 = T_1102 ? 3'h1 : T_1101;
+ assign T_1104 = 3'h4 == xact_a_type;
+ assign T_1105 = T_1104 ? 3'h4 : T_1103;
+ assign T_1106 = 3'h3 == xact_a_type;
+ assign T_1107 = T_1106 ? 3'h3 : T_1105;
+ assign T_1108 = 3'h2 == xact_a_type;
+ assign T_1109 = T_1108 ? 3'h3 : T_1107;
+ assign T_1110 = 3'h1 == xact_a_type;
+ assign T_1111 = T_1110 ? 3'h5 : T_1109;
+ assign T_1112 = 3'h0 == xact_a_type;
+ assign T_1113 = T_1112 ? 3'h4 : T_1111;
+ assign T_1114 = xact_a_type == 1'h0;
+ assign T_1117 = 1'h0 == 1'h0;
+ assign T_1118 = T_1117 ? 1'h0 : 1'h1;
+ assign T_1119 = T_1114 ? T_1118 : 1'h1;
+ assign T_1120 = xact_is_builtin_type ? T_1113 : T_1119;
+ assign T_1129_addr_beat = 1'h0;
+ assign T_1129_client_xact_id = xact_client_xact_id;
+ assign T_1129_manager_xact_id = 3'h7;
+ assign T_1129_is_builtin_type = xact_is_builtin_type;
+ assign T_1129_g_type = T_1120;
+ assign T_1129_data = 1'h0;
+ assign T_1129_client_id = xact_client_id;
+ assign T_1140 = state != 1'h0;
+ assign T_1141 = T_1140 & collect_iacq_data;
+ assign T_1142 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_1143 = T_1141 & T_1142;
+ assign T_1144 = io_inner_acquire_bits_client_id != xact_client_id;
+ assign T_1145 = T_1143 & T_1144;
+ assign T_1147 = T_1145 == 1'h0;
+ assign T_1149 = reset == 1'h0;
+ assign T_1151 = T_1147 == 1'h0;
+ assign T_1153 = reset == 1'h0;
+ assign T_1154 = state != 1'h0;
+ assign T_1155 = T_1154 & collect_iacq_data;
+ assign T_1156 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_1157 = T_1155 & T_1156;
+ assign T_1158 = io_inner_acquire_bits_client_xact_id != xact_client_xact_id;
+ assign T_1159 = T_1157 & T_1158;
+ assign T_1161 = T_1159 == 1'h0;
+ assign T_1163 = reset == 1'h0;
+ assign T_1165 = T_1161 == 1'h0;
+ assign T_1167 = reset == 1'h0;
+ assign T_1168 = state == 1'h0;
+ assign T_1169 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_1170 = T_1168 & T_1169;
+ assign T_1172 = 1'h1 & io_inner_acquire_bits_is_builtin_type;
+ assign T_1175_0 = 3'h3;
+ assign T_1178 = T_1175_0 == io_inner_acquire_bits_a_type;
+ assign T_1180 = 1'h0 | T_1178;
+ assign T_1181 = T_1172 & T_1180;
+ assign T_1182 = T_1170 & T_1181;
+ assign T_1184 = io_inner_acquire_bits_addr_beat != 1'h0;
+ assign T_1185 = T_1182 & T_1184;
+ assign T_1187 = T_1185 == 1'h0;
+ assign T_1189 = reset == 1'h0;
+ assign T_1191 = T_1187 == 1'h0;
+ assign T_1193 = reset == 1'h0;
+ assign GEN_3 = io_inner_acquire_bits_data;
+ assign T_1197 = io_inner_acquire_bits_union[12:9];
+ assign T_1198 = T_1197[3];
+ assign T_1200 = 1'h1 << T_1198;
+ assign T_1202 = io_inner_acquire_bits_a_type == 3'h4;
+ assign T_1203 = io_inner_acquire_bits_is_builtin_type & T_1202;
+ assign T_1204 = T_1200[0];
+ assign T_1205 = T_1200[1];
+ assign T_1207_0 = T_1204;
+ assign T_1207_1 = T_1205;
+ assign T_1212 = 8'h0 - T_1207_0;
+ assign T_1213 = T_1212[7:0];
+ assign T_1215 = 8'h0 - T_1207_1;
+ assign T_1216 = T_1215[7:0];
+ assign T_1218_0 = T_1213;
+ assign T_1218_1 = T_1216;
+ assign T_1222 = {T_1218_1,T_1218_0};
+ assign T_1224 = io_inner_acquire_bits_a_type == 3'h3;
+ assign T_1225 = io_inner_acquire_bits_is_builtin_type & T_1224;
+ assign T_1227 = io_inner_acquire_bits_a_type == 3'h2;
+ assign T_1228 = io_inner_acquire_bits_is_builtin_type & T_1227;
+ assign T_1229 = T_1225 | T_1228;
+ assign T_1230 = io_inner_acquire_bits_union[16:1];
+ assign T_1232 = T_1229 ? T_1230 : 16'h0;
+ assign T_1233 = T_1203 ? T_1222 : T_1232;
+ assign GEN_4 = T_1233;
+ assign T_1236 = 1'h1 << io_inner_acquire_bits_addr_beat;
+ assign T_1237 = iacq_data_valid | T_1236;
+ assign T_1238 = ~ iacq_data_valid;
+ assign T_1239 = T_1238 | T_1236;
+ assign T_1240 = ~ T_1239;
+ assign T_1241 = 1'h1 ? T_1237 : T_1240;
+ assign T_1245 = 1'h0 == state;
+ assign GEN_5 = io_inner_acquire_bits_data;
+ assign T_1251 = io_inner_acquire_bits_union[12:9];
+ assign T_1252 = T_1251[3];
+ assign T_1254 = 1'h1 << T_1252;
+ assign T_1256 = io_inner_acquire_bits_a_type == 3'h4;
+ assign T_1257 = io_inner_acquire_bits_is_builtin_type & T_1256;
+ assign T_1258 = T_1254[0];
+ assign T_1259 = T_1254[1];
+ assign T_1261_0 = T_1258;
+ assign T_1261_1 = T_1259;
+ assign T_1266 = 8'h0 - T_1261_0;
+ assign T_1267 = T_1266[7:0];
+ assign T_1269 = 8'h0 - T_1261_1;
+ assign T_1270 = T_1269[7:0];
+ assign T_1272_0 = T_1267;
+ assign T_1272_1 = T_1270;
+ assign T_1276 = {T_1272_1,T_1272_0};
+ assign T_1278 = io_inner_acquire_bits_a_type == 3'h3;
+ assign T_1279 = io_inner_acquire_bits_is_builtin_type & T_1278;
+ assign T_1281 = io_inner_acquire_bits_a_type == 3'h2;
+ assign T_1282 = io_inner_acquire_bits_is_builtin_type & T_1281;
+ assign T_1283 = T_1279 | T_1282;
+ assign T_1284 = io_inner_acquire_bits_union[16:1];
+ assign T_1286 = T_1283 ? T_1284 : 16'h0;
+ assign T_1287 = T_1257 ? T_1276 : T_1286;
+ assign GEN_6 = T_1287;
+ assign T_1289 = 1'h1 & io_inner_acquire_bits_is_builtin_type;
+ assign T_1292_0 = 3'h3;
+ assign T_1295 = T_1292_0 == io_inner_acquire_bits_a_type;
+ assign T_1297 = 1'h0 | T_1295;
+ assign T_1298 = T_1289 & T_1297;
+ assign T_1303_0 = 3'h2;
+ assign T_1303_1 = 3'h3;
+ assign T_1303_2 = 3'h4;
+ assign T_1308 = T_1303_0 == io_inner_acquire_bits_a_type;
+ assign T_1309 = T_1303_1 == io_inner_acquire_bits_a_type;
+ assign T_1310 = T_1303_2 == io_inner_acquire_bits_a_type;
+ assign T_1312 = 1'h0 | T_1308;
+ assign T_1313 = T_1312 | T_1309;
+ assign T_1314 = T_1313 | T_1310;
+ assign T_1315 = io_inner_acquire_bits_is_builtin_type & T_1314;
+ assign T_1316 = T_1315 << io_inner_acquire_bits_addr_beat;
+ assign T_1318 = mask_incoherent != 1'h0;
+ assign T_1319 = mask_incoherent[0];
+ assign T_1320 = mask_incoherent[1];
+ assign T_1321 = mask_incoherent[2];
+ assign T_1322 = mask_incoherent[3];
+ assign T_1324 = {1'h0,T_1320};
+ assign T_1325 = T_1319 + T_1324;
+ assign T_1326 = T_1325[1:0];
+ assign T_1329 = {1'h0,T_1322};
+ assign T_1330 = T_1321 + T_1329;
+ assign T_1331 = T_1330[1:0];
+ assign T_1332 = {1'h0,T_1331};
+ assign T_1333 = T_1326 + T_1332;
+ assign T_1334 = T_1333[2:0];
+ assign T_1335 = pending_outer_read_ ? 2'h2 : 3'h4;
+ assign T_1336 = pending_outer_write_ ? 2'h3 : T_1335;
+ assign T_1337 = T_1318 ? 1'h1 : T_1336;
+ assign T_1338 = 1'h1 == state;
+ assign T_1340 = pending_probes != 1'h0;
+ assign T_1342 = 1'h1 << 1'h0;
+ assign T_1343 = ~ T_1342;
+ assign T_1344 = pending_probes & T_1343;
+ assign T_1346_0 = 1'h0;
+ assign T_1346_1 = 1'h1;
+ assign T_1346_2 = 2'h2;
+ assign T_1351 = T_1346_0 == io_inner_release_bits_r_type;
+ assign T_1352 = T_1346_1 == io_inner_release_bits_r_type;
+ assign T_1353 = T_1346_2 == io_inner_release_bits_r_type;
+ assign T_1355 = 1'h0 | T_1351;
+ assign T_1356 = T_1355 | T_1352;
+ assign T_1357 = T_1356 | T_1353;
+ assign T_1359 = T_1357 == 1'h0;
+ assign T_1360 = T_1359 | io_outer_acquire_ready;
+ assign T_1362_0 = 1'h0;
+ assign T_1362_1 = 1'h1;
+ assign T_1362_2 = 2'h2;
+ assign T_1367 = T_1362_0 == io_inner_release_bits_r_type;
+ assign T_1368 = T_1362_1 == io_inner_release_bits_r_type;
+ assign T_1369 = T_1362_2 == io_inner_release_bits_r_type;
+ assign T_1371 = 1'h0 | T_1367;
+ assign T_1372 = T_1371 | T_1368;
+ assign T_1373 = T_1372 | T_1369;
+ assign T_1377 = release_count - 1'h1;
+ assign T_1378 = T_1377[0:0];
+ assign T_1380 = release_count == 1'h1;
+ assign T_1381 = pending_outer_read ? 2'h2 : 3'h4;
+ assign T_1382 = pending_outer_write ? 2'h3 : T_1381;
+ assign T_1384 = T_1373 == 1'h0;
+ assign T_1386 = release_count - 1'h1;
+ assign T_1387 = T_1386[0:0];
+ assign T_1389 = release_count == 1'h1;
+ assign T_1390 = pending_outer_read ? 2'h2 : 3'h4;
+ assign T_1391 = pending_outer_write ? 2'h3 : T_1390;
+ assign T_1392 = 2'h3 == state;
+ assign T_1394 = pending_ognt_ack == 1'h0;
+ assign T_1396 = collect_iacq_data == 1'h0;
+ assign T_1397 = iacq_data_valid >> oacq_data_cnt;
+ assign T_1398 = T_1397[0];
+ assign T_1399 = T_1396 | T_1398;
+ assign T_1400 = T_1394 & T_1399;
+ assign T_1402 = pending_outer_read ? 2'h2 : 3'h5;
+ assign T_1403 = 2'h2 == state;
+ assign T_1405 = pending_ognt_ack == 1'h0;
+ assign T_1406 = io_outer_acquire_ready & io_outer_acquire_valid;
+ assign T_1407 = 3'h5 == state;
+ assign T_1410 = 1'h0 == 1'h0;
+ assign T_1412 = io_inner_grant_bits_g_type == 3'h0;
+ assign T_1413 = io_inner_grant_bits_is_builtin_type & T_1412;
+ assign T_1415 = T_1413 == 1'h0;
+ assign T_1416 = T_1410 & T_1415;
+ assign T_1417 = T_1416 ? 3'h6 : 1'h0;
+ assign T_1418 = 3'h4 == state;
+ assign T_1422 = 1'h0 == 1'h0;
+ assign T_1424 = io_inner_grant_bits_g_type == 3'h0;
+ assign T_1425 = io_inner_grant_bits_is_builtin_type & T_1424;
+ assign T_1427 = T_1425 == 1'h0;
+ assign T_1428 = T_1422 & T_1427;
+ assign T_1429 = T_1428 ? 3'h6 : 1'h0;
+ assign T_1430 = 3'h6 == state;
+ assign GEN_9 = T_325 & T_327;
+ assign GEN_10 = T_1149 & T_1151;
+ assign GEN_11 = T_1163 & T_1165;
+ assign GEN_12 = T_1189 & T_1191;
+ assign GEN_13 = 1'h0 == 1'h0;
+ assign GEN_14 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_15 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_16 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_17 = 1'h1 == 1'h0;
+ assign GEN_18 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_19 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_20 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_21 = 2'h2 == 1'h0;
+ assign GEN_22 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_23 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_24 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_25 = 2'h3 == 1'h0;
+ assign GEN_26 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_27 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_28 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_29 = 1'h0 == 1'h0;
+ assign GEN_30 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_31 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_32 = 1'h0 == io_inner_acquire_bits_addr_beat;
+ assign GEN_33 = 1'h1 == 1'h0;
+ assign GEN_34 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_35 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_36 = 1'h1 == io_inner_acquire_bits_addr_beat;
+ assign GEN_37 = 2'h2 == 1'h0;
+ assign GEN_38 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_39 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_40 = 2'h2 == io_inner_acquire_bits_addr_beat;
+ assign GEN_41 = 2'h3 == 1'h0;
+ assign GEN_42 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_43 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_44 = 2'h3 == io_inner_acquire_bits_addr_beat;
+ assign GEN_45 = 2'h3 == oacq_data_cnt;
+ assign GEN_46 = 2'h2 == oacq_data_cnt;
+ assign GEN_47 = 1'h1 == oacq_data_cnt;
+ assign GEN_48 = 2'h3 == oacq_data_cnt;
+ assign GEN_49 = 2'h2 == oacq_data_cnt;
+ assign GEN_50 = 1'h1 == oacq_data_cnt;
+ assign GEN_51 = 2'h3 == oacq_data_cnt;
+ assign GEN_52 = 2'h2 == oacq_data_cnt;
+ assign GEN_53 = 1'h1 == oacq_data_cnt;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ state = {1{$random}};
+ xact_addr_block = {1{$random}};
+ xact_client_xact_id = {1{$random}};
+ xact_addr_beat = {1{$random}};
+ xact_is_builtin_type = {1{$random}};
+ xact_a_type = {1{$random}};
+ xact_union = {1{$random}};
+ xact_data_buffer_0 = {1{$random}};
+ xact_data_buffer_1 = {1{$random}};
+ xact_data_buffer_2 = {1{$random}};
+ xact_data_buffer_3 = {1{$random}};
+ xact_wmask_buffer_0 = {1{$random}};
+ xact_wmask_buffer_1 = {1{$random}};
+ xact_wmask_buffer_2 = {1{$random}};
+ xact_wmask_buffer_3 = {1{$random}};
+ xact_client_id = {1{$random}};
+ release_count = {1{$random}};
+ pending_probes = {1{$random}};
+ collect_iacq_data = {1{$random}};
+ iacq_data_valid = {1{$random}};
+ T_371 = {1{$random}};
+ T_403 = {1{$random}};
+ T_441 = {1{$random}};
+ T_469 = {1{$random}};
+ T_504 = {1{$random}};
+ pending_ognt_ack = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1430) begin
+ if(io_inner_finish_valid) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1418) begin
+ if(io_inner_grant_ready) begin
+ state <= T_1429;
+ end else begin
+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
+ end else begin
+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end
+ end else begin
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+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end else begin
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+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
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+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
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+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
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+ end
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+ end
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+ state <= T_1402;
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ end else begin
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
+ end else begin
+ ;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ end else begin
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end
+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1418) begin
+ if(io_inner_grant_ready) begin
+ state <= T_1429;
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+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
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+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
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+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ if(T_1380) begin
+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end
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+ end
+ end else begin
+ if(T_1392) begin
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+ state <= T_1402;
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
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+ if(T_1380) begin
+ state <= T_1382;
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ end
+ end else begin
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+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
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+ end
+ end else begin
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+ if(T_1406) begin
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ state <= T_1337;
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+ end
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ state <= T_1337;
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+ end
+ end else begin
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1407) begin
+ if(ignt_data_done) begin
+ state <= T_1417;
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+ if(T_1403) begin
+ if(T_1406) begin
+ state <= 3'h5;
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+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
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+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ end else begin
+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1337;
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+ state <= T_1382;
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+ state <= T_1337;
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ end
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ end else begin
+ ;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ if(T_1245) begin
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+ state <= T_1337;
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+ ;
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+ ;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
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+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
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+ if(T_1389) begin
+ state <= T_1391;
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+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
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+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
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+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
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+ end else begin
+ ;
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+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
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+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ state <= T_1402;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ if(T_1389) begin
+ state <= T_1391;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ if(T_1380) begin
+ state <= T_1382;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ state <= T_1337;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_addr_block <= io_inner_acquire_bits_addr_block;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_client_xact_id <= io_inner_acquire_bits_client_xact_id;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_addr_beat <= io_inner_acquire_bits_addr_beat;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_is_builtin_type <= io_inner_acquire_bits_is_builtin_type;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_a_type <= io_inner_acquire_bits_a_type;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_union <= io_inner_acquire_bits_union;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_13) begin
+ xact_data_buffer_0 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_14) begin
+ xact_data_buffer_0 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_15) begin
+ xact_data_buffer_0 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_16) begin
+ xact_data_buffer_0 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_17) begin
+ xact_data_buffer_1 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_18) begin
+ xact_data_buffer_1 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_19) begin
+ xact_data_buffer_1 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_20) begin
+ xact_data_buffer_1 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_21) begin
+ xact_data_buffer_2 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_22) begin
+ xact_data_buffer_2 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_23) begin
+ xact_data_buffer_2 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_24) begin
+ xact_data_buffer_2 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_25) begin
+ xact_data_buffer_3 <= GEN_5;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_26) begin
+ xact_data_buffer_3 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_27) begin
+ xact_data_buffer_3 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_28) begin
+ xact_data_buffer_3 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_29) begin
+ xact_wmask_buffer_0 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_30) begin
+ xact_wmask_buffer_0 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_31) begin
+ xact_wmask_buffer_0 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_32) begin
+ xact_wmask_buffer_0 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_33) begin
+ xact_wmask_buffer_1 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_34) begin
+ xact_wmask_buffer_1 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_35) begin
+ xact_wmask_buffer_1 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_36) begin
+ xact_wmask_buffer_1 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_37) begin
+ xact_wmask_buffer_2 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_38) begin
+ xact_wmask_buffer_2 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_39) begin
+ xact_wmask_buffer_2 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_40) begin
+ xact_wmask_buffer_2 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_41) begin
+ xact_wmask_buffer_3 <= GEN_6;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_42) begin
+ xact_wmask_buffer_3 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_43) begin
+ xact_wmask_buffer_3 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ if(GEN_44) begin
+ xact_wmask_buffer_3 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ xact_client_id <= io_inner_acquire_bits_client_id;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ release_count <= 1'h0;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1384) begin
+ release_count <= T_1387;
+ end else begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ release_count <= T_1378;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ release_count <= T_1334;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ pending_probes <= 1'h0;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_probe_ready) begin
+ pending_probes <= T_1344;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ pending_probes <= mask_incoherent;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ if(T_1318) begin
+ pending_probes <= mask_incoherent;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ collect_iacq_data <= 1'h0;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ collect_iacq_data <= T_1298;
+ end else begin
+ if(collect_iacq_data) begin
+ if(iacq_data_done) begin
+ collect_iacq_data <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(iacq_data_done) begin
+ collect_iacq_data <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ iacq_data_valid <= 4'h0;
+ end else begin
+ if(T_1245) begin
+ if(io_inner_acquire_valid) begin
+ iacq_data_valid <= T_1316;
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ iacq_data_valid <= T_1241;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(collect_iacq_data) begin
+ if(io_inner_acquire_valid) begin
+ iacq_data_valid <= T_1241;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ T_371 <= 2'h0;
+ end else begin
+ if(T_369) begin
+ T_371 <= T_380;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_403 <= 2'h0;
+ end else begin
+ if(T_401) begin
+ T_403 <= T_412;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_441 <= 2'h0;
+ end else begin
+ if(T_439) begin
+ T_441 <= T_450;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_469 <= 2'h0;
+ end else begin
+ if(T_467) begin
+ T_469 <= T_478;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_504 <= 2'h0;
+ end else begin
+ if(T_502) begin
+ T_504 <= T_513;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ if(T_1392) begin
+ if(oacq_data_done) begin
+ pending_ognt_ack <= 1'h1;
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ pending_ognt_ack <= 1'h1;
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1338) begin
+ if(io_inner_release_valid) begin
+ if(T_1373) begin
+ if(io_outer_acquire_ready) begin
+ if(oacq_data_done) begin
+ pending_ognt_ack <= 1'h1;
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(pending_ognt_ack) begin
+ if(io_outer_grant_valid) begin
+ pending_ognt_ack <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ `ifndef SYNTHESIS
+ if(GEN_9 & T_329) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_325 & T_327) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_10 & T_1153) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_1149 & T_1151) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_11 & T_1167) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_1163 & T_1165) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_12 & T_1193) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_1189 & T_1191) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ end
+endmodule
+module LockingRRArbiter_33(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input [1:0] io_in_0_bits_addr_beat,
+ input [1:0] io_in_0_bits_client_xact_id,
+ input [3:0] io_in_0_bits_manager_xact_id,
+ input io_in_0_bits_is_builtin_type,
+ input [3:0] io_in_0_bits_g_type,
+ input [127:0] io_in_0_bits_data,
+ input [1:0] io_in_0_bits_client_id,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input [1:0] io_in_1_bits_addr_beat,
+ input [1:0] io_in_1_bits_client_xact_id,
+ input [3:0] io_in_1_bits_manager_xact_id,
+ input io_in_1_bits_is_builtin_type,
+ input [3:0] io_in_1_bits_g_type,
+ input [127:0] io_in_1_bits_data,
+ input [1:0] io_in_1_bits_client_id,
+ output io_in_2_ready,
+ input io_in_2_valid,
+ input [1:0] io_in_2_bits_addr_beat,
+ input [1:0] io_in_2_bits_client_xact_id,
+ input [3:0] io_in_2_bits_manager_xact_id,
+ input io_in_2_bits_is_builtin_type,
+ input [3:0] io_in_2_bits_g_type,
+ input [127:0] io_in_2_bits_data,
+ input [1:0] io_in_2_bits_client_id,
+ output io_in_3_ready,
+ input io_in_3_valid,
+ input [1:0] io_in_3_bits_addr_beat,
+ input [1:0] io_in_3_bits_client_xact_id,
+ input [3:0] io_in_3_bits_manager_xact_id,
+ input io_in_3_bits_is_builtin_type,
+ input [3:0] io_in_3_bits_g_type,
+ input [127:0] io_in_3_bits_data,
+ input [1:0] io_in_3_bits_client_id,
+ output io_in_4_ready,
+ input io_in_4_valid,
+ input [1:0] io_in_4_bits_addr_beat,
+ input [1:0] io_in_4_bits_client_xact_id,
+ input [3:0] io_in_4_bits_manager_xact_id,
+ input io_in_4_bits_is_builtin_type,
+ input [3:0] io_in_4_bits_g_type,
+ input [127:0] io_in_4_bits_data,
+ input [1:0] io_in_4_bits_client_id,
+ output io_in_5_ready,
+ input io_in_5_valid,
+ input [1:0] io_in_5_bits_addr_beat,
+ input [1:0] io_in_5_bits_client_xact_id,
+ input [3:0] io_in_5_bits_manager_xact_id,
+ input io_in_5_bits_is_builtin_type,
+ input [3:0] io_in_5_bits_g_type,
+ input [127:0] io_in_5_bits_data,
+ input [1:0] io_in_5_bits_client_id,
+ output io_in_6_ready,
+ input io_in_6_valid,
+ input [1:0] io_in_6_bits_addr_beat,
+ input [1:0] io_in_6_bits_client_xact_id,
+ input [3:0] io_in_6_bits_manager_xact_id,
+ input io_in_6_bits_is_builtin_type,
+ input [3:0] io_in_6_bits_g_type,
+ input [127:0] io_in_6_bits_data,
+ input [1:0] io_in_6_bits_client_id,
+ output io_in_7_ready,
+ input io_in_7_valid,
+ input [1:0] io_in_7_bits_addr_beat,
+ input [1:0] io_in_7_bits_client_xact_id,
+ input [3:0] io_in_7_bits_manager_xact_id,
+ input io_in_7_bits_is_builtin_type,
+ input [3:0] io_in_7_bits_g_type,
+ input [127:0] io_in_7_bits_data,
+ input [1:0] io_in_7_bits_client_id,
+ input io_out_ready,
+ output io_out_valid,
+ output [1:0] io_out_bits_addr_beat,
+ output [1:0] io_out_bits_client_xact_id,
+ output [3:0] io_out_bits_manager_xact_id,
+ output io_out_bits_is_builtin_type,
+ output [3:0] io_out_bits_g_type,
+ output [127:0] io_out_bits_data,
+ output [1:0] io_out_bits_client_id,
+ output [2:0] io_chosen
+);
+ reg T_1502;
+ reg [2:0] T_1504;
+ wire [2:0] T_1506;
+ wire GEN_0;
+ wire [1:0] GEN_1;
+ wire [1:0] GEN_2;
+ wire [3:0] GEN_3;
+ wire GEN_4;
+ wire [3:0] GEN_5;
+ wire [127:0] GEN_6;
+ wire [1:0] GEN_7;
+ wire GEN_8;
+ reg [2:0] last_grant;
+ wire T_1706;
+ wire T_1707;
+ wire T_1709;
+ wire T_1710;
+ wire T_1712;
+ wire T_1713;
+ wire T_1715;
+ wire T_1716;
+ wire T_1718;
+ wire T_1719;
+ wire T_1721;
+ wire T_1722;
+ wire T_1724;
+ wire T_1725;
+ wire T_1727;
+ wire T_1728;
+ wire T_1731;
+ wire T_1733;
+ wire T_1735;
+ wire T_1736;
+ wire T_1738;
+ wire T_1740;
+ wire T_1741;
+ wire T_1742;
+ wire T_1744;
+ wire T_1746;
+ wire T_1747;
+ wire T_1748;
+ wire T_1749;
+ wire T_1751;
+ wire T_1753;
+ wire T_1754;
+ wire T_1755;
+ wire T_1756;
+ wire T_1757;
+ wire T_1759;
+ wire T_1761;
+ wire T_1762;
+ wire T_1763;
+ wire T_1764;
+ wire T_1765;
+ wire T_1766;
+ wire T_1768;
+ wire T_1770;
+ wire T_1771;
+ wire T_1772;
+ wire T_1773;
+ wire T_1774;
+ wire T_1775;
+ wire T_1776;
+ wire T_1778;
+ wire T_1780;
+ wire T_1781;
+ wire T_1782;
+ wire T_1783;
+ wire T_1784;
+ wire T_1785;
+ wire T_1786;
+ wire T_1787;
+ wire T_1789;
+ wire T_1791;
+ wire T_1792;
+ wire T_1793;
+ wire T_1794;
+ wire T_1795;
+ wire T_1796;
+ wire T_1797;
+ wire T_1798;
+ wire T_1799;
+ wire T_1801;
+ wire T_1803;
+ wire T_1804;
+ wire T_1805;
+ wire T_1806;
+ wire T_1807;
+ wire T_1808;
+ wire T_1809;
+ wire T_1810;
+ wire T_1811;
+ wire T_1812;
+ wire T_1814;
+ wire T_1816;
+ wire T_1817;
+ wire T_1818;
+ wire T_1819;
+ wire T_1820;
+ wire T_1821;
+ wire T_1822;
+ wire T_1823;
+ wire T_1824;
+ wire T_1825;
+ wire T_1826;
+ wire T_1828;
+ wire T_1830;
+ wire T_1831;
+ wire T_1832;
+ wire T_1833;
+ wire T_1834;
+ wire T_1835;
+ wire T_1836;
+ wire T_1837;
+ wire T_1838;
+ wire T_1839;
+ wire T_1840;
+ wire T_1841;
+ wire T_1843;
+ wire T_1845;
+ wire T_1846;
+ wire T_1847;
+ wire T_1848;
+ wire T_1849;
+ wire T_1850;
+ wire T_1851;
+ wire T_1852;
+ wire T_1853;
+ wire T_1854;
+ wire T_1855;
+ wire T_1856;
+ wire T_1857;
+ wire T_1859;
+ wire T_1861;
+ wire T_1862;
+ wire T_1863;
+ wire T_1864;
+ wire T_1865;
+ wire T_1866;
+ wire T_1867;
+ wire T_1868;
+ wire T_1869;
+ wire T_1870;
+ wire T_1871;
+ wire T_1872;
+ wire T_1873;
+ wire T_1874;
+ wire T_1876;
+ wire T_1878;
+ wire T_1879;
+ wire T_1880;
+ wire T_1881;
+ wire T_1882;
+ wire T_1883;
+ wire T_1884;
+ wire T_1885;
+ wire T_1886;
+ wire T_1887;
+ wire T_1888;
+ wire T_1889;
+ wire T_1890;
+ wire T_1891;
+ wire T_1892;
+ wire T_1894;
+ wire T_1896;
+ wire T_1897;
+ wire T_1898;
+ wire T_1900;
+ wire T_1901;
+ wire T_1902;
+ wire T_1904;
+ wire T_1905;
+ wire T_1906;
+ wire T_1908;
+ wire T_1909;
+ wire T_1910;
+ wire T_1912;
+ wire T_1913;
+ wire T_1914;
+ wire T_1916;
+ wire T_1917;
+ wire T_1918;
+ wire T_1920;
+ wire T_1921;
+ wire T_1922;
+ wire T_1924;
+ wire T_1925;
+ wire T_1926;
+ wire T_1928;
+ wire T_1929;
+ wire T_1930;
+ wire T_1932;
+ wire T_1933;
+ wire T_1934;
+ wire T_1936;
+ wire T_1937;
+ wire T_1938;
+ wire T_1940;
+ wire T_1941;
+ wire T_1942;
+ wire T_1944;
+ wire T_1945;
+ wire T_1946;
+ wire T_1948;
+ wire T_1949;
+ wire T_1950;
+ wire T_1952;
+ wire T_1953;
+ wire T_1954;
+ wire T_1956;
+ wire T_1957;
+ wire T_1958;
+ reg [1:0] T_1960;
+ wire [2:0] T_1962;
+ wire [1:0] T_1963;
+ wire T_1964;
+ wire [2:0] T_1968_0;
+ wire T_1971;
+ wire T_1973;
+ wire T_1975_0;
+ wire T_1975_1;
+ wire T_1979;
+ wire T_1980;
+ wire T_1982;
+ wire T_1983;
+ wire T_1984;
+ wire T_1985;
+ wire T_1987;
+ wire T_1989;
+ wire T_1990;
+ wire T_1991;
+ wire T_1992;
+ wire T_1993;
+ wire T_1994;
+ wire T_1995;
+ wire T_1996;
+ wire T_1998_0;
+ wire T_1998_1;
+ wire T_1998_2;
+ wire T_1998_3;
+ wire T_1998_4;
+ wire T_1998_5;
+ wire T_1998_6;
+ wire T_1998_7;
+ wire [2:0] T_2016;
+ wire [2:0] T_2017;
+ wire [2:0] T_2018;
+ wire [2:0] T_2019;
+ wire [2:0] T_2020;
+ wire [2:0] T_2021;
+ wire [2:0] T_2022;
+ wire T_2024;
+ wire [2:0] T_2028;
+ wire [2:0] T_2030;
+ wire [2:0] T_2032;
+ wire [2:0] T_2034;
+ wire [2:0] T_2036;
+ wire [2:0] T_2038;
+ wire [2:0] T_2040;
+ wire T_2042;
+ wire T_2043;
+ wire [2:0] T_2045;
+ wire T_2047;
+ wire T_2048;
+ wire [2:0] T_2050;
+ wire T_2052;
+ wire T_2053;
+ wire [2:0] T_2055;
+ wire T_2057;
+ wire T_2058;
+ wire [2:0] T_2060;
+ wire T_2062;
+ wire T_2063;
+ wire [2:0] T_2065;
+ wire T_2067;
+ wire T_2068;
+ wire [2:0] T_2070;
+ wire T_2072;
+ wire T_2073;
+ wire [2:0] choose;
+ wire [2:0] T_2076;
+ wire T_2077;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ wire GEN_17;
+ wire GEN_18;
+ wire GEN_19;
+ wire GEN_20;
+ wire GEN_21;
+ wire GEN_22;
+ wire GEN_23;
+ wire GEN_24;
+ wire GEN_25;
+ wire GEN_26;
+ wire GEN_27;
+ wire GEN_28;
+ wire GEN_29;
+ wire GEN_30;
+ wire GEN_31;
+ wire GEN_32;
+ wire GEN_33;
+ wire GEN_34;
+ wire GEN_35;
+ wire GEN_36;
+ wire GEN_37;
+ wire GEN_38;
+ wire GEN_39;
+ wire GEN_40;
+ wire GEN_41;
+ wire GEN_42;
+ wire GEN_43;
+ wire GEN_44;
+ wire GEN_45;
+ wire GEN_46;
+ wire GEN_47;
+ wire GEN_48;
+ wire GEN_49;
+ wire GEN_50;
+ wire GEN_51;
+ wire GEN_52;
+ wire GEN_53;
+ wire GEN_54;
+ wire GEN_55;
+ wire GEN_56;
+ wire GEN_57;
+ wire GEN_58;
+ wire GEN_59;
+ wire GEN_60;
+ wire GEN_61;
+ wire GEN_62;
+ wire GEN_63;
+ wire GEN_64;
+ assign io_in_0_ready = T_1930;
+ assign io_in_1_ready = T_1934;
+ assign io_in_2_ready = T_1938;
+ assign io_in_3_ready = T_1942;
+ assign io_in_4_ready = T_1946;
+ assign io_in_5_ready = T_1950;
+ assign io_in_6_ready = T_1954;
+ assign io_in_7_ready = T_1958;
+ assign io_out_valid = GEN_0;
+ assign io_out_bits_addr_beat = GEN_1;
+ assign io_out_bits_client_xact_id = GEN_2;
+ assign io_out_bits_manager_xact_id = GEN_3;
+ assign io_out_bits_is_builtin_type = GEN_4;
+ assign io_out_bits_g_type = GEN_5;
+ assign io_out_bits_data = GEN_6;
+ assign io_out_bits_client_id = GEN_7;
+ assign io_chosen = T_1506;
+ assign T_1506 = T_2076;
+ assign GEN_0 = GEN_9 ? io_in_7_valid : GEN_10 ? io_in_6_valid : GEN_11 ? io_in_5_valid : GEN_12 ? io_in_4_valid : GEN_13 ? io_in_3_valid : GEN_14 ? io_in_2_valid : GEN_15 ? io_in_1_valid : io_in_0_valid;
+ assign GEN_1 = GEN_16 ? io_in_7_bits_addr_beat : GEN_17 ? io_in_6_bits_addr_beat : GEN_18 ? io_in_5_bits_addr_beat : GEN_19 ? io_in_4_bits_addr_beat : GEN_20 ? io_in_3_bits_addr_beat : GEN_21 ? io_in_2_bits_addr_beat : GEN_22 ? io_in_1_bits_addr_beat : io_in_0_bits_addr_beat;
+ assign GEN_2 = GEN_23 ? io_in_7_bits_client_xact_id : GEN_24 ? io_in_6_bits_client_xact_id : GEN_25 ? io_in_5_bits_client_xact_id : GEN_26 ? io_in_4_bits_client_xact_id : GEN_27 ? io_in_3_bits_client_xact_id : GEN_28 ? io_in_2_bits_client_xact_id : GEN_29 ? io_in_1_bits_client_xact_id : io_in_0_bits_client_xact_id;
+ assign GEN_3 = GEN_30 ? io_in_7_bits_manager_xact_id : GEN_31 ? io_in_6_bits_manager_xact_id : GEN_32 ? io_in_5_bits_manager_xact_id : GEN_33 ? io_in_4_bits_manager_xact_id : GEN_34 ? io_in_3_bits_manager_xact_id : GEN_35 ? io_in_2_bits_manager_xact_id : GEN_36 ? io_in_1_bits_manager_xact_id : io_in_0_bits_manager_xact_id;
+ assign GEN_4 = GEN_37 ? io_in_7_bits_is_builtin_type : GEN_38 ? io_in_6_bits_is_builtin_type : GEN_39 ? io_in_5_bits_is_builtin_type : GEN_40 ? io_in_4_bits_is_builtin_type : GEN_41 ? io_in_3_bits_is_builtin_type : GEN_42 ? io_in_2_bits_is_builtin_type : GEN_43 ? io_in_1_bits_is_builtin_type : io_in_0_bits_is_builtin_type;
+ assign GEN_5 = GEN_44 ? io_in_7_bits_g_type : GEN_45 ? io_in_6_bits_g_type : GEN_46 ? io_in_5_bits_g_type : GEN_47 ? io_in_4_bits_g_type : GEN_48 ? io_in_3_bits_g_type : GEN_49 ? io_in_2_bits_g_type : GEN_50 ? io_in_1_bits_g_type : io_in_0_bits_g_type;
+ assign GEN_6 = GEN_51 ? io_in_7_bits_data : GEN_52 ? io_in_6_bits_data : GEN_53 ? io_in_5_bits_data : GEN_54 ? io_in_4_bits_data : GEN_55 ? io_in_3_bits_data : GEN_56 ? io_in_2_bits_data : GEN_57 ? io_in_1_bits_data : io_in_0_bits_data;
+ assign GEN_7 = GEN_58 ? io_in_7_bits_client_id : GEN_59 ? io_in_6_bits_client_id : GEN_60 ? io_in_5_bits_client_id : GEN_61 ? io_in_4_bits_client_id : GEN_62 ? io_in_3_bits_client_id : GEN_63 ? io_in_2_bits_client_id : GEN_64 ? io_in_1_bits_client_id : io_in_0_bits_client_id;
+ assign GEN_8 = 1'h0;
+ assign T_1706 = 1'h0 > last_grant;
+ assign T_1707 = io_in_0_valid & T_1706;
+ assign T_1709 = 1'h1 > last_grant;
+ assign T_1710 = io_in_1_valid & T_1709;
+ assign T_1712 = 2'h2 > last_grant;
+ assign T_1713 = io_in_2_valid & T_1712;
+ assign T_1715 = 2'h3 > last_grant;
+ assign T_1716 = io_in_3_valid & T_1715;
+ assign T_1718 = 3'h4 > last_grant;
+ assign T_1719 = io_in_4_valid & T_1718;
+ assign T_1721 = 3'h5 > last_grant;
+ assign T_1722 = io_in_5_valid & T_1721;
+ assign T_1724 = 3'h6 > last_grant;
+ assign T_1725 = io_in_6_valid & T_1724;
+ assign T_1727 = 3'h7 > last_grant;
+ assign T_1728 = io_in_7_valid & T_1727;
+ assign T_1731 = 1'h0 | T_1707;
+ assign T_1733 = T_1731 == 1'h0;
+ assign T_1735 = 1'h0 | T_1707;
+ assign T_1736 = T_1735 | T_1710;
+ assign T_1738 = T_1736 == 1'h0;
+ assign T_1740 = 1'h0 | T_1707;
+ assign T_1741 = T_1740 | T_1710;
+ assign T_1742 = T_1741 | T_1713;
+ assign T_1744 = T_1742 == 1'h0;
+ assign T_1746 = 1'h0 | T_1707;
+ assign T_1747 = T_1746 | T_1710;
+ assign T_1748 = T_1747 | T_1713;
+ assign T_1749 = T_1748 | T_1716;
+ assign T_1751 = T_1749 == 1'h0;
+ assign T_1753 = 1'h0 | T_1707;
+ assign T_1754 = T_1753 | T_1710;
+ assign T_1755 = T_1754 | T_1713;
+ assign T_1756 = T_1755 | T_1716;
+ assign T_1757 = T_1756 | T_1719;
+ assign T_1759 = T_1757 == 1'h0;
+ assign T_1761 = 1'h0 | T_1707;
+ assign T_1762 = T_1761 | T_1710;
+ assign T_1763 = T_1762 | T_1713;
+ assign T_1764 = T_1763 | T_1716;
+ assign T_1765 = T_1764 | T_1719;
+ assign T_1766 = T_1765 | T_1722;
+ assign T_1768 = T_1766 == 1'h0;
+ assign T_1770 = 1'h0 | T_1707;
+ assign T_1771 = T_1770 | T_1710;
+ assign T_1772 = T_1771 | T_1713;
+ assign T_1773 = T_1772 | T_1716;
+ assign T_1774 = T_1773 | T_1719;
+ assign T_1775 = T_1774 | T_1722;
+ assign T_1776 = T_1775 | T_1725;
+ assign T_1778 = T_1776 == 1'h0;
+ assign T_1780 = 1'h0 | T_1707;
+ assign T_1781 = T_1780 | T_1710;
+ assign T_1782 = T_1781 | T_1713;
+ assign T_1783 = T_1782 | T_1716;
+ assign T_1784 = T_1783 | T_1719;
+ assign T_1785 = T_1784 | T_1722;
+ assign T_1786 = T_1785 | T_1725;
+ assign T_1787 = T_1786 | T_1728;
+ assign T_1789 = T_1787 == 1'h0;
+ assign T_1791 = 1'h0 | T_1707;
+ assign T_1792 = T_1791 | T_1710;
+ assign T_1793 = T_1792 | T_1713;
+ assign T_1794 = T_1793 | T_1716;
+ assign T_1795 = T_1794 | T_1719;
+ assign T_1796 = T_1795 | T_1722;
+ assign T_1797 = T_1796 | T_1725;
+ assign T_1798 = T_1797 | T_1728;
+ assign T_1799 = T_1798 | io_in_0_valid;
+ assign T_1801 = T_1799 == 1'h0;
+ assign T_1803 = 1'h0 | T_1707;
+ assign T_1804 = T_1803 | T_1710;
+ assign T_1805 = T_1804 | T_1713;
+ assign T_1806 = T_1805 | T_1716;
+ assign T_1807 = T_1806 | T_1719;
+ assign T_1808 = T_1807 | T_1722;
+ assign T_1809 = T_1808 | T_1725;
+ assign T_1810 = T_1809 | T_1728;
+ assign T_1811 = T_1810 | io_in_0_valid;
+ assign T_1812 = T_1811 | io_in_1_valid;
+ assign T_1814 = T_1812 == 1'h0;
+ assign T_1816 = 1'h0 | T_1707;
+ assign T_1817 = T_1816 | T_1710;
+ assign T_1818 = T_1817 | T_1713;
+ assign T_1819 = T_1818 | T_1716;
+ assign T_1820 = T_1819 | T_1719;
+ assign T_1821 = T_1820 | T_1722;
+ assign T_1822 = T_1821 | T_1725;
+ assign T_1823 = T_1822 | T_1728;
+ assign T_1824 = T_1823 | io_in_0_valid;
+ assign T_1825 = T_1824 | io_in_1_valid;
+ assign T_1826 = T_1825 | io_in_2_valid;
+ assign T_1828 = T_1826 == 1'h0;
+ assign T_1830 = 1'h0 | T_1707;
+ assign T_1831 = T_1830 | T_1710;
+ assign T_1832 = T_1831 | T_1713;
+ assign T_1833 = T_1832 | T_1716;
+ assign T_1834 = T_1833 | T_1719;
+ assign T_1835 = T_1834 | T_1722;
+ assign T_1836 = T_1835 | T_1725;
+ assign T_1837 = T_1836 | T_1728;
+ assign T_1838 = T_1837 | io_in_0_valid;
+ assign T_1839 = T_1838 | io_in_1_valid;
+ assign T_1840 = T_1839 | io_in_2_valid;
+ assign T_1841 = T_1840 | io_in_3_valid;
+ assign T_1843 = T_1841 == 1'h0;
+ assign T_1845 = 1'h0 | T_1707;
+ assign T_1846 = T_1845 | T_1710;
+ assign T_1847 = T_1846 | T_1713;
+ assign T_1848 = T_1847 | T_1716;
+ assign T_1849 = T_1848 | T_1719;
+ assign T_1850 = T_1849 | T_1722;
+ assign T_1851 = T_1850 | T_1725;
+ assign T_1852 = T_1851 | T_1728;
+ assign T_1853 = T_1852 | io_in_0_valid;
+ assign T_1854 = T_1853 | io_in_1_valid;
+ assign T_1855 = T_1854 | io_in_2_valid;
+ assign T_1856 = T_1855 | io_in_3_valid;
+ assign T_1857 = T_1856 | io_in_4_valid;
+ assign T_1859 = T_1857 == 1'h0;
+ assign T_1861 = 1'h0 | T_1707;
+ assign T_1862 = T_1861 | T_1710;
+ assign T_1863 = T_1862 | T_1713;
+ assign T_1864 = T_1863 | T_1716;
+ assign T_1865 = T_1864 | T_1719;
+ assign T_1866 = T_1865 | T_1722;
+ assign T_1867 = T_1866 | T_1725;
+ assign T_1868 = T_1867 | T_1728;
+ assign T_1869 = T_1868 | io_in_0_valid;
+ assign T_1870 = T_1869 | io_in_1_valid;
+ assign T_1871 = T_1870 | io_in_2_valid;
+ assign T_1872 = T_1871 | io_in_3_valid;
+ assign T_1873 = T_1872 | io_in_4_valid;
+ assign T_1874 = T_1873 | io_in_5_valid;
+ assign T_1876 = T_1874 == 1'h0;
+ assign T_1878 = 1'h0 | T_1707;
+ assign T_1879 = T_1878 | T_1710;
+ assign T_1880 = T_1879 | T_1713;
+ assign T_1881 = T_1880 | T_1716;
+ assign T_1882 = T_1881 | T_1719;
+ assign T_1883 = T_1882 | T_1722;
+ assign T_1884 = T_1883 | T_1725;
+ assign T_1885 = T_1884 | T_1728;
+ assign T_1886 = T_1885 | io_in_0_valid;
+ assign T_1887 = T_1886 | io_in_1_valid;
+ assign T_1888 = T_1887 | io_in_2_valid;
+ assign T_1889 = T_1888 | io_in_3_valid;
+ assign T_1890 = T_1889 | io_in_4_valid;
+ assign T_1891 = T_1890 | io_in_5_valid;
+ assign T_1892 = T_1891 | io_in_6_valid;
+ assign T_1894 = T_1892 == 1'h0;
+ assign T_1896 = 1'h0 > last_grant;
+ assign T_1897 = 1'h1 & T_1896;
+ assign T_1898 = T_1897 | T_1789;
+ assign T_1900 = 1'h1 > last_grant;
+ assign T_1901 = T_1733 & T_1900;
+ assign T_1902 = T_1901 | T_1801;
+ assign T_1904 = 2'h2 > last_grant;
+ assign T_1905 = T_1738 & T_1904;
+ assign T_1906 = T_1905 | T_1814;
+ assign T_1908 = 2'h3 > last_grant;
+ assign T_1909 = T_1744 & T_1908;
+ assign T_1910 = T_1909 | T_1828;
+ assign T_1912 = 3'h4 > last_grant;
+ assign T_1913 = T_1751 & T_1912;
+ assign T_1914 = T_1913 | T_1843;
+ assign T_1916 = 3'h5 > last_grant;
+ assign T_1917 = T_1759 & T_1916;
+ assign T_1918 = T_1917 | T_1859;
+ assign T_1920 = 3'h6 > last_grant;
+ assign T_1921 = T_1768 & T_1920;
+ assign T_1922 = T_1921 | T_1876;
+ assign T_1924 = 3'h7 > last_grant;
+ assign T_1925 = T_1778 & T_1924;
+ assign T_1926 = T_1925 | T_1894;
+ assign T_1928 = T_1504 == 1'h0;
+ assign T_1929 = T_1502 ? T_1928 : T_1898;
+ assign T_1930 = T_1929 & io_out_ready;
+ assign T_1932 = T_1504 == 1'h1;
+ assign T_1933 = T_1502 ? T_1932 : T_1902;
+ assign T_1934 = T_1933 & io_out_ready;
+ assign T_1936 = T_1504 == 2'h2;
+ assign T_1937 = T_1502 ? T_1936 : T_1906;
+ assign T_1938 = T_1937 & io_out_ready;
+ assign T_1940 = T_1504 == 2'h3;
+ assign T_1941 = T_1502 ? T_1940 : T_1910;
+ assign T_1942 = T_1941 & io_out_ready;
+ assign T_1944 = T_1504 == 3'h4;
+ assign T_1945 = T_1502 ? T_1944 : T_1914;
+ assign T_1946 = T_1945 & io_out_ready;
+ assign T_1948 = T_1504 == 3'h5;
+ assign T_1949 = T_1502 ? T_1948 : T_1918;
+ assign T_1950 = T_1949 & io_out_ready;
+ assign T_1952 = T_1504 == 3'h6;
+ assign T_1953 = T_1502 ? T_1952 : T_1922;
+ assign T_1954 = T_1953 & io_out_ready;
+ assign T_1956 = T_1504 == 3'h7;
+ assign T_1957 = T_1502 ? T_1956 : T_1926;
+ assign T_1958 = T_1957 & io_out_ready;
+ assign T_1962 = T_1960 + 1'h1;
+ assign T_1963 = T_1962[1:0];
+ assign T_1964 = io_out_ready & io_out_valid;
+ assign T_1968_0 = 3'h5;
+ assign T_1971 = T_1968_0 == io_out_bits_g_type;
+ assign T_1973 = 1'h0 | T_1971;
+ assign T_1975_0 = 1'h0;
+ assign T_1975_1 = 1'h1;
+ assign T_1979 = T_1975_0 == io_out_bits_g_type;
+ assign T_1980 = T_1975_1 == io_out_bits_g_type;
+ assign T_1982 = 1'h0 | T_1979;
+ assign T_1983 = T_1982 | T_1980;
+ assign T_1984 = io_out_bits_is_builtin_type ? T_1973 : T_1983;
+ assign T_1985 = 1'h1 & T_1984;
+ assign T_1987 = T_1502 == 1'h0;
+ assign T_1989 = io_in_0_ready & io_in_0_valid;
+ assign T_1990 = io_in_1_ready & io_in_1_valid;
+ assign T_1991 = io_in_2_ready & io_in_2_valid;
+ assign T_1992 = io_in_3_ready & io_in_3_valid;
+ assign T_1993 = io_in_4_ready & io_in_4_valid;
+ assign T_1994 = io_in_5_ready & io_in_5_valid;
+ assign T_1995 = io_in_6_ready & io_in_6_valid;
+ assign T_1996 = io_in_7_ready & io_in_7_valid;
+ assign T_1998_0 = T_1989;
+ assign T_1998_1 = T_1990;
+ assign T_1998_2 = T_1991;
+ assign T_1998_3 = T_1992;
+ assign T_1998_4 = T_1993;
+ assign T_1998_5 = T_1994;
+ assign T_1998_6 = T_1995;
+ assign T_1998_7 = T_1996;
+ assign T_2016 = T_1998_6 ? 3'h6 : 3'h7;
+ assign T_2017 = T_1998_5 ? 3'h5 : T_2016;
+ assign T_2018 = T_1998_4 ? 3'h4 : T_2017;
+ assign T_2019 = T_1998_3 ? 2'h3 : T_2018;
+ assign T_2020 = T_1998_2 ? 2'h2 : T_2019;
+ assign T_2021 = T_1998_1 ? 1'h1 : T_2020;
+ assign T_2022 = T_1998_0 ? 1'h0 : T_2021;
+ assign T_2024 = T_1963 == 1'h0;
+ assign T_2028 = io_in_6_valid ? 3'h6 : 3'h7;
+ assign T_2030 = io_in_5_valid ? 3'h5 : T_2028;
+ assign T_2032 = io_in_4_valid ? 3'h4 : T_2030;
+ assign T_2034 = io_in_3_valid ? 2'h3 : T_2032;
+ assign T_2036 = io_in_2_valid ? 2'h2 : T_2034;
+ assign T_2038 = io_in_1_valid ? 1'h1 : T_2036;
+ assign T_2040 = io_in_0_valid ? 1'h0 : T_2038;
+ assign T_2042 = 3'h7 > last_grant;
+ assign T_2043 = io_in_7_valid & T_2042;
+ assign T_2045 = T_2043 ? 3'h7 : T_2040;
+ assign T_2047 = 3'h6 > last_grant;
+ assign T_2048 = io_in_6_valid & T_2047;
+ assign T_2050 = T_2048 ? 3'h6 : T_2045;
+ assign T_2052 = 3'h5 > last_grant;
+ assign T_2053 = io_in_5_valid & T_2052;
+ assign T_2055 = T_2053 ? 3'h5 : T_2050;
+ assign T_2057 = 3'h4 > last_grant;
+ assign T_2058 = io_in_4_valid & T_2057;
+ assign T_2060 = T_2058 ? 3'h4 : T_2055;
+ assign T_2062 = 2'h3 > last_grant;
+ assign T_2063 = io_in_3_valid & T_2062;
+ assign T_2065 = T_2063 ? 2'h3 : T_2060;
+ assign T_2067 = 2'h2 > last_grant;
+ assign T_2068 = io_in_2_valid & T_2067;
+ assign T_2070 = T_2068 ? 2'h2 : T_2065;
+ assign T_2072 = 1'h1 > last_grant;
+ assign T_2073 = io_in_1_valid & T_2072;
+ assign choose = T_2073 ? 1'h1 : T_2070;
+ assign T_2076 = T_1502 ? T_1504 : choose;
+ assign T_2077 = io_out_ready & io_out_valid;
+ assign GEN_9 = 3'h7 == T_1506;
+ assign GEN_10 = 3'h6 == T_1506;
+ assign GEN_11 = 3'h5 == T_1506;
+ assign GEN_12 = 3'h4 == T_1506;
+ assign GEN_13 = 2'h3 == T_1506;
+ assign GEN_14 = 2'h2 == T_1506;
+ assign GEN_15 = 1'h1 == T_1506;
+ assign GEN_16 = 3'h7 == T_1506;
+ assign GEN_17 = 3'h6 == T_1506;
+ assign GEN_18 = 3'h5 == T_1506;
+ assign GEN_19 = 3'h4 == T_1506;
+ assign GEN_20 = 2'h3 == T_1506;
+ assign GEN_21 = 2'h2 == T_1506;
+ assign GEN_22 = 1'h1 == T_1506;
+ assign GEN_23 = 3'h7 == T_1506;
+ assign GEN_24 = 3'h6 == T_1506;
+ assign GEN_25 = 3'h5 == T_1506;
+ assign GEN_26 = 3'h4 == T_1506;
+ assign GEN_27 = 2'h3 == T_1506;
+ assign GEN_28 = 2'h2 == T_1506;
+ assign GEN_29 = 1'h1 == T_1506;
+ assign GEN_30 = 3'h7 == T_1506;
+ assign GEN_31 = 3'h6 == T_1506;
+ assign GEN_32 = 3'h5 == T_1506;
+ assign GEN_33 = 3'h4 == T_1506;
+ assign GEN_34 = 2'h3 == T_1506;
+ assign GEN_35 = 2'h2 == T_1506;
+ assign GEN_36 = 1'h1 == T_1506;
+ assign GEN_37 = 3'h7 == T_1506;
+ assign GEN_38 = 3'h6 == T_1506;
+ assign GEN_39 = 3'h5 == T_1506;
+ assign GEN_40 = 3'h4 == T_1506;
+ assign GEN_41 = 2'h3 == T_1506;
+ assign GEN_42 = 2'h2 == T_1506;
+ assign GEN_43 = 1'h1 == T_1506;
+ assign GEN_44 = 3'h7 == T_1506;
+ assign GEN_45 = 3'h6 == T_1506;
+ assign GEN_46 = 3'h5 == T_1506;
+ assign GEN_47 = 3'h4 == T_1506;
+ assign GEN_48 = 2'h3 == T_1506;
+ assign GEN_49 = 2'h2 == T_1506;
+ assign GEN_50 = 1'h1 == T_1506;
+ assign GEN_51 = 3'h7 == T_1506;
+ assign GEN_52 = 3'h6 == T_1506;
+ assign GEN_53 = 3'h5 == T_1506;
+ assign GEN_54 = 3'h4 == T_1506;
+ assign GEN_55 = 2'h3 == T_1506;
+ assign GEN_56 = 2'h2 == T_1506;
+ assign GEN_57 = 1'h1 == T_1506;
+ assign GEN_58 = 3'h7 == T_1506;
+ assign GEN_59 = 3'h6 == T_1506;
+ assign GEN_60 = 3'h5 == T_1506;
+ assign GEN_61 = 3'h4 == T_1506;
+ assign GEN_62 = 2'h3 == T_1506;
+ assign GEN_63 = 2'h2 == T_1506;
+ assign GEN_64 = 1'h1 == T_1506;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_1502 = {1{$random}};
+ T_1504 = {1{$random}};
+ last_grant = {1{$random}};
+ T_1960 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ T_1502 <= 1'h0;
+ end else begin
+ if(T_1964) begin
+ if(T_2024) begin
+ T_1502 <= 1'h0;
+ end else begin
+ if(T_1985) begin
+ if(T_1987) begin
+ T_1502 <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_1504 <= 3'h7;
+ end else begin
+ if(T_1964) begin
+ if(T_1985) begin
+ if(T_1987) begin
+ T_1504 <= T_2022;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ last_grant <= 3'h0;
+ end else begin
+ if(T_2077) begin
+ last_grant <= T_1506;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_1960 <= 2'h0;
+ end else begin
+ if(T_1964) begin
+ if(T_1985) begin
+ T_1960 <= T_1963;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module LockingRRArbiter_34(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input [25:0] io_in_0_bits_addr_block,
+ input [1:0] io_in_0_bits_p_type,
+ input [1:0] io_in_0_bits_client_id,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input [25:0] io_in_1_bits_addr_block,
+ input [1:0] io_in_1_bits_p_type,
+ input [1:0] io_in_1_bits_client_id,
+ output io_in_2_ready,
+ input io_in_2_valid,
+ input [25:0] io_in_2_bits_addr_block,
+ input [1:0] io_in_2_bits_p_type,
+ input [1:0] io_in_2_bits_client_id,
+ output io_in_3_ready,
+ input io_in_3_valid,
+ input [25:0] io_in_3_bits_addr_block,
+ input [1:0] io_in_3_bits_p_type,
+ input [1:0] io_in_3_bits_client_id,
+ output io_in_4_ready,
+ input io_in_4_valid,
+ input [25:0] io_in_4_bits_addr_block,
+ input [1:0] io_in_4_bits_p_type,
+ input [1:0] io_in_4_bits_client_id,
+ output io_in_5_ready,
+ input io_in_5_valid,
+ input [25:0] io_in_5_bits_addr_block,
+ input [1:0] io_in_5_bits_p_type,
+ input [1:0] io_in_5_bits_client_id,
+ output io_in_6_ready,
+ input io_in_6_valid,
+ input [25:0] io_in_6_bits_addr_block,
+ input [1:0] io_in_6_bits_p_type,
+ input [1:0] io_in_6_bits_client_id,
+ output io_in_7_ready,
+ input io_in_7_valid,
+ input [25:0] io_in_7_bits_addr_block,
+ input [1:0] io_in_7_bits_p_type,
+ input [1:0] io_in_7_bits_client_id,
+ input io_out_ready,
+ output io_out_valid,
+ output [25:0] io_out_bits_addr_block,
+ output [1:0] io_out_bits_p_type,
+ output [1:0] io_out_bits_client_id,
+ output [2:0] io_chosen
+);
+ reg T_1318;
+ reg [2:0] T_1320;
+ wire [2:0] T_1322;
+ wire GEN_0;
+ wire [25:0] GEN_1;
+ wire [1:0] GEN_2;
+ wire [1:0] GEN_3;
+ wire GEN_4;
+ reg [2:0] last_grant;
+ wire T_1498;
+ wire T_1499;
+ wire T_1501;
+ wire T_1502;
+ wire T_1504;
+ wire T_1505;
+ wire T_1507;
+ wire T_1508;
+ wire T_1510;
+ wire T_1511;
+ wire T_1513;
+ wire T_1514;
+ wire T_1516;
+ wire T_1517;
+ wire T_1519;
+ wire T_1520;
+ wire T_1523;
+ wire T_1525;
+ wire T_1527;
+ wire T_1528;
+ wire T_1530;
+ wire T_1532;
+ wire T_1533;
+ wire T_1534;
+ wire T_1536;
+ wire T_1538;
+ wire T_1539;
+ wire T_1540;
+ wire T_1541;
+ wire T_1543;
+ wire T_1545;
+ wire T_1546;
+ wire T_1547;
+ wire T_1548;
+ wire T_1549;
+ wire T_1551;
+ wire T_1553;
+ wire T_1554;
+ wire T_1555;
+ wire T_1556;
+ wire T_1557;
+ wire T_1558;
+ wire T_1560;
+ wire T_1562;
+ wire T_1563;
+ wire T_1564;
+ wire T_1565;
+ wire T_1566;
+ wire T_1567;
+ wire T_1568;
+ wire T_1570;
+ wire T_1572;
+ wire T_1573;
+ wire T_1574;
+ wire T_1575;
+ wire T_1576;
+ wire T_1577;
+ wire T_1578;
+ wire T_1579;
+ wire T_1581;
+ wire T_1583;
+ wire T_1584;
+ wire T_1585;
+ wire T_1586;
+ wire T_1587;
+ wire T_1588;
+ wire T_1589;
+ wire T_1590;
+ wire T_1591;
+ wire T_1593;
+ wire T_1595;
+ wire T_1596;
+ wire T_1597;
+ wire T_1598;
+ wire T_1599;
+ wire T_1600;
+ wire T_1601;
+ wire T_1602;
+ wire T_1603;
+ wire T_1604;
+ wire T_1606;
+ wire T_1608;
+ wire T_1609;
+ wire T_1610;
+ wire T_1611;
+ wire T_1612;
+ wire T_1613;
+ wire T_1614;
+ wire T_1615;
+ wire T_1616;
+ wire T_1617;
+ wire T_1618;
+ wire T_1620;
+ wire T_1622;
+ wire T_1623;
+ wire T_1624;
+ wire T_1625;
+ wire T_1626;
+ wire T_1627;
+ wire T_1628;
+ wire T_1629;
+ wire T_1630;
+ wire T_1631;
+ wire T_1632;
+ wire T_1633;
+ wire T_1635;
+ wire T_1637;
+ wire T_1638;
+ wire T_1639;
+ wire T_1640;
+ wire T_1641;
+ wire T_1642;
+ wire T_1643;
+ wire T_1644;
+ wire T_1645;
+ wire T_1646;
+ wire T_1647;
+ wire T_1648;
+ wire T_1649;
+ wire T_1651;
+ wire T_1653;
+ wire T_1654;
+ wire T_1655;
+ wire T_1656;
+ wire T_1657;
+ wire T_1658;
+ wire T_1659;
+ wire T_1660;
+ wire T_1661;
+ wire T_1662;
+ wire T_1663;
+ wire T_1664;
+ wire T_1665;
+ wire T_1666;
+ wire T_1668;
+ wire T_1670;
+ wire T_1671;
+ wire T_1672;
+ wire T_1673;
+ wire T_1674;
+ wire T_1675;
+ wire T_1676;
+ wire T_1677;
+ wire T_1678;
+ wire T_1679;
+ wire T_1680;
+ wire T_1681;
+ wire T_1682;
+ wire T_1683;
+ wire T_1684;
+ wire T_1686;
+ wire T_1688;
+ wire T_1689;
+ wire T_1690;
+ wire T_1692;
+ wire T_1693;
+ wire T_1694;
+ wire T_1696;
+ wire T_1697;
+ wire T_1698;
+ wire T_1700;
+ wire T_1701;
+ wire T_1702;
+ wire T_1704;
+ wire T_1705;
+ wire T_1706;
+ wire T_1708;
+ wire T_1709;
+ wire T_1710;
+ wire T_1712;
+ wire T_1713;
+ wire T_1714;
+ wire T_1716;
+ wire T_1717;
+ wire T_1718;
+ wire T_1720;
+ wire T_1721;
+ wire T_1722;
+ wire T_1724;
+ wire T_1725;
+ wire T_1726;
+ wire T_1728;
+ wire T_1729;
+ wire T_1730;
+ wire T_1732;
+ wire T_1733;
+ wire T_1734;
+ wire T_1736;
+ wire T_1737;
+ wire T_1738;
+ wire T_1740;
+ wire T_1741;
+ wire T_1742;
+ wire T_1744;
+ wire T_1745;
+ wire T_1746;
+ wire T_1748;
+ wire T_1749;
+ wire T_1750;
+ reg [1:0] T_1752;
+ wire [2:0] T_1754;
+ wire [1:0] T_1755;
+ wire T_1756;
+ wire T_1759;
+ wire T_1761;
+ wire T_1762;
+ wire T_1763;
+ wire T_1764;
+ wire T_1765;
+ wire T_1766;
+ wire T_1767;
+ wire T_1768;
+ wire T_1770_0;
+ wire T_1770_1;
+ wire T_1770_2;
+ wire T_1770_3;
+ wire T_1770_4;
+ wire T_1770_5;
+ wire T_1770_6;
+ wire T_1770_7;
+ wire [2:0] T_1788;
+ wire [2:0] T_1789;
+ wire [2:0] T_1790;
+ wire [2:0] T_1791;
+ wire [2:0] T_1792;
+ wire [2:0] T_1793;
+ wire [2:0] T_1794;
+ wire T_1796;
+ wire [2:0] T_1800;
+ wire [2:0] T_1802;
+ wire [2:0] T_1804;
+ wire [2:0] T_1806;
+ wire [2:0] T_1808;
+ wire [2:0] T_1810;
+ wire [2:0] T_1812;
+ wire T_1814;
+ wire T_1815;
+ wire [2:0] T_1817;
+ wire T_1819;
+ wire T_1820;
+ wire [2:0] T_1822;
+ wire T_1824;
+ wire T_1825;
+ wire [2:0] T_1827;
+ wire T_1829;
+ wire T_1830;
+ wire [2:0] T_1832;
+ wire T_1834;
+ wire T_1835;
+ wire [2:0] T_1837;
+ wire T_1839;
+ wire T_1840;
+ wire [2:0] T_1842;
+ wire T_1844;
+ wire T_1845;
+ wire [2:0] choose;
+ wire [2:0] T_1848;
+ wire T_1849;
+ wire GEN_5;
+ wire GEN_6;
+ wire GEN_7;
+ wire GEN_8;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ wire GEN_17;
+ wire GEN_18;
+ wire GEN_19;
+ wire GEN_20;
+ wire GEN_21;
+ wire GEN_22;
+ wire GEN_23;
+ wire GEN_24;
+ wire GEN_25;
+ wire GEN_26;
+ wire GEN_27;
+ wire GEN_28;
+ wire GEN_29;
+ wire GEN_30;
+ wire GEN_31;
+ wire GEN_32;
+ assign io_in_0_ready = T_1722;
+ assign io_in_1_ready = T_1726;
+ assign io_in_2_ready = T_1730;
+ assign io_in_3_ready = T_1734;
+ assign io_in_4_ready = T_1738;
+ assign io_in_5_ready = T_1742;
+ assign io_in_6_ready = T_1746;
+ assign io_in_7_ready = T_1750;
+ assign io_out_valid = GEN_0;
+ assign io_out_bits_addr_block = GEN_1;
+ assign io_out_bits_p_type = GEN_2;
+ assign io_out_bits_client_id = GEN_3;
+ assign io_chosen = T_1322;
+ assign T_1322 = T_1848;
+ assign GEN_0 = GEN_5 ? io_in_7_valid : GEN_6 ? io_in_6_valid : GEN_7 ? io_in_5_valid : GEN_8 ? io_in_4_valid : GEN_9 ? io_in_3_valid : GEN_10 ? io_in_2_valid : GEN_11 ? io_in_1_valid : io_in_0_valid;
+ assign GEN_1 = GEN_12 ? io_in_7_bits_addr_block : GEN_13 ? io_in_6_bits_addr_block : GEN_14 ? io_in_5_bits_addr_block : GEN_15 ? io_in_4_bits_addr_block : GEN_16 ? io_in_3_bits_addr_block : GEN_17 ? io_in_2_bits_addr_block : GEN_18 ? io_in_1_bits_addr_block : io_in_0_bits_addr_block;
+ assign GEN_2 = GEN_19 ? io_in_7_bits_p_type : GEN_20 ? io_in_6_bits_p_type : GEN_21 ? io_in_5_bits_p_type : GEN_22 ? io_in_4_bits_p_type : GEN_23 ? io_in_3_bits_p_type : GEN_24 ? io_in_2_bits_p_type : GEN_25 ? io_in_1_bits_p_type : io_in_0_bits_p_type;
+ assign GEN_3 = GEN_26 ? io_in_7_bits_client_id : GEN_27 ? io_in_6_bits_client_id : GEN_28 ? io_in_5_bits_client_id : GEN_29 ? io_in_4_bits_client_id : GEN_30 ? io_in_3_bits_client_id : GEN_31 ? io_in_2_bits_client_id : GEN_32 ? io_in_1_bits_client_id : io_in_0_bits_client_id;
+ assign GEN_4 = 1'h0;
+ assign T_1498 = 1'h0 > last_grant;
+ assign T_1499 = io_in_0_valid & T_1498;
+ assign T_1501 = 1'h1 > last_grant;
+ assign T_1502 = io_in_1_valid & T_1501;
+ assign T_1504 = 2'h2 > last_grant;
+ assign T_1505 = io_in_2_valid & T_1504;
+ assign T_1507 = 2'h3 > last_grant;
+ assign T_1508 = io_in_3_valid & T_1507;
+ assign T_1510 = 3'h4 > last_grant;
+ assign T_1511 = io_in_4_valid & T_1510;
+ assign T_1513 = 3'h5 > last_grant;
+ assign T_1514 = io_in_5_valid & T_1513;
+ assign T_1516 = 3'h6 > last_grant;
+ assign T_1517 = io_in_6_valid & T_1516;
+ assign T_1519 = 3'h7 > last_grant;
+ assign T_1520 = io_in_7_valid & T_1519;
+ assign T_1523 = 1'h0 | T_1499;
+ assign T_1525 = T_1523 == 1'h0;
+ assign T_1527 = 1'h0 | T_1499;
+ assign T_1528 = T_1527 | T_1502;
+ assign T_1530 = T_1528 == 1'h0;
+ assign T_1532 = 1'h0 | T_1499;
+ assign T_1533 = T_1532 | T_1502;
+ assign T_1534 = T_1533 | T_1505;
+ assign T_1536 = T_1534 == 1'h0;
+ assign T_1538 = 1'h0 | T_1499;
+ assign T_1539 = T_1538 | T_1502;
+ assign T_1540 = T_1539 | T_1505;
+ assign T_1541 = T_1540 | T_1508;
+ assign T_1543 = T_1541 == 1'h0;
+ assign T_1545 = 1'h0 | T_1499;
+ assign T_1546 = T_1545 | T_1502;
+ assign T_1547 = T_1546 | T_1505;
+ assign T_1548 = T_1547 | T_1508;
+ assign T_1549 = T_1548 | T_1511;
+ assign T_1551 = T_1549 == 1'h0;
+ assign T_1553 = 1'h0 | T_1499;
+ assign T_1554 = T_1553 | T_1502;
+ assign T_1555 = T_1554 | T_1505;
+ assign T_1556 = T_1555 | T_1508;
+ assign T_1557 = T_1556 | T_1511;
+ assign T_1558 = T_1557 | T_1514;
+ assign T_1560 = T_1558 == 1'h0;
+ assign T_1562 = 1'h0 | T_1499;
+ assign T_1563 = T_1562 | T_1502;
+ assign T_1564 = T_1563 | T_1505;
+ assign T_1565 = T_1564 | T_1508;
+ assign T_1566 = T_1565 | T_1511;
+ assign T_1567 = T_1566 | T_1514;
+ assign T_1568 = T_1567 | T_1517;
+ assign T_1570 = T_1568 == 1'h0;
+ assign T_1572 = 1'h0 | T_1499;
+ assign T_1573 = T_1572 | T_1502;
+ assign T_1574 = T_1573 | T_1505;
+ assign T_1575 = T_1574 | T_1508;
+ assign T_1576 = T_1575 | T_1511;
+ assign T_1577 = T_1576 | T_1514;
+ assign T_1578 = T_1577 | T_1517;
+ assign T_1579 = T_1578 | T_1520;
+ assign T_1581 = T_1579 == 1'h0;
+ assign T_1583 = 1'h0 | T_1499;
+ assign T_1584 = T_1583 | T_1502;
+ assign T_1585 = T_1584 | T_1505;
+ assign T_1586 = T_1585 | T_1508;
+ assign T_1587 = T_1586 | T_1511;
+ assign T_1588 = T_1587 | T_1514;
+ assign T_1589 = T_1588 | T_1517;
+ assign T_1590 = T_1589 | T_1520;
+ assign T_1591 = T_1590 | io_in_0_valid;
+ assign T_1593 = T_1591 == 1'h0;
+ assign T_1595 = 1'h0 | T_1499;
+ assign T_1596 = T_1595 | T_1502;
+ assign T_1597 = T_1596 | T_1505;
+ assign T_1598 = T_1597 | T_1508;
+ assign T_1599 = T_1598 | T_1511;
+ assign T_1600 = T_1599 | T_1514;
+ assign T_1601 = T_1600 | T_1517;
+ assign T_1602 = T_1601 | T_1520;
+ assign T_1603 = T_1602 | io_in_0_valid;
+ assign T_1604 = T_1603 | io_in_1_valid;
+ assign T_1606 = T_1604 == 1'h0;
+ assign T_1608 = 1'h0 | T_1499;
+ assign T_1609 = T_1608 | T_1502;
+ assign T_1610 = T_1609 | T_1505;
+ assign T_1611 = T_1610 | T_1508;
+ assign T_1612 = T_1611 | T_1511;
+ assign T_1613 = T_1612 | T_1514;
+ assign T_1614 = T_1613 | T_1517;
+ assign T_1615 = T_1614 | T_1520;
+ assign T_1616 = T_1615 | io_in_0_valid;
+ assign T_1617 = T_1616 | io_in_1_valid;
+ assign T_1618 = T_1617 | io_in_2_valid;
+ assign T_1620 = T_1618 == 1'h0;
+ assign T_1622 = 1'h0 | T_1499;
+ assign T_1623 = T_1622 | T_1502;
+ assign T_1624 = T_1623 | T_1505;
+ assign T_1625 = T_1624 | T_1508;
+ assign T_1626 = T_1625 | T_1511;
+ assign T_1627 = T_1626 | T_1514;
+ assign T_1628 = T_1627 | T_1517;
+ assign T_1629 = T_1628 | T_1520;
+ assign T_1630 = T_1629 | io_in_0_valid;
+ assign T_1631 = T_1630 | io_in_1_valid;
+ assign T_1632 = T_1631 | io_in_2_valid;
+ assign T_1633 = T_1632 | io_in_3_valid;
+ assign T_1635 = T_1633 == 1'h0;
+ assign T_1637 = 1'h0 | T_1499;
+ assign T_1638 = T_1637 | T_1502;
+ assign T_1639 = T_1638 | T_1505;
+ assign T_1640 = T_1639 | T_1508;
+ assign T_1641 = T_1640 | T_1511;
+ assign T_1642 = T_1641 | T_1514;
+ assign T_1643 = T_1642 | T_1517;
+ assign T_1644 = T_1643 | T_1520;
+ assign T_1645 = T_1644 | io_in_0_valid;
+ assign T_1646 = T_1645 | io_in_1_valid;
+ assign T_1647 = T_1646 | io_in_2_valid;
+ assign T_1648 = T_1647 | io_in_3_valid;
+ assign T_1649 = T_1648 | io_in_4_valid;
+ assign T_1651 = T_1649 == 1'h0;
+ assign T_1653 = 1'h0 | T_1499;
+ assign T_1654 = T_1653 | T_1502;
+ assign T_1655 = T_1654 | T_1505;
+ assign T_1656 = T_1655 | T_1508;
+ assign T_1657 = T_1656 | T_1511;
+ assign T_1658 = T_1657 | T_1514;
+ assign T_1659 = T_1658 | T_1517;
+ assign T_1660 = T_1659 | T_1520;
+ assign T_1661 = T_1660 | io_in_0_valid;
+ assign T_1662 = T_1661 | io_in_1_valid;
+ assign T_1663 = T_1662 | io_in_2_valid;
+ assign T_1664 = T_1663 | io_in_3_valid;
+ assign T_1665 = T_1664 | io_in_4_valid;
+ assign T_1666 = T_1665 | io_in_5_valid;
+ assign T_1668 = T_1666 == 1'h0;
+ assign T_1670 = 1'h0 | T_1499;
+ assign T_1671 = T_1670 | T_1502;
+ assign T_1672 = T_1671 | T_1505;
+ assign T_1673 = T_1672 | T_1508;
+ assign T_1674 = T_1673 | T_1511;
+ assign T_1675 = T_1674 | T_1514;
+ assign T_1676 = T_1675 | T_1517;
+ assign T_1677 = T_1676 | T_1520;
+ assign T_1678 = T_1677 | io_in_0_valid;
+ assign T_1679 = T_1678 | io_in_1_valid;
+ assign T_1680 = T_1679 | io_in_2_valid;
+ assign T_1681 = T_1680 | io_in_3_valid;
+ assign T_1682 = T_1681 | io_in_4_valid;
+ assign T_1683 = T_1682 | io_in_5_valid;
+ assign T_1684 = T_1683 | io_in_6_valid;
+ assign T_1686 = T_1684 == 1'h0;
+ assign T_1688 = 1'h0 > last_grant;
+ assign T_1689 = 1'h1 & T_1688;
+ assign T_1690 = T_1689 | T_1581;
+ assign T_1692 = 1'h1 > last_grant;
+ assign T_1693 = T_1525 & T_1692;
+ assign T_1694 = T_1693 | T_1593;
+ assign T_1696 = 2'h2 > last_grant;
+ assign T_1697 = T_1530 & T_1696;
+ assign T_1698 = T_1697 | T_1606;
+ assign T_1700 = 2'h3 > last_grant;
+ assign T_1701 = T_1536 & T_1700;
+ assign T_1702 = T_1701 | T_1620;
+ assign T_1704 = 3'h4 > last_grant;
+ assign T_1705 = T_1543 & T_1704;
+ assign T_1706 = T_1705 | T_1635;
+ assign T_1708 = 3'h5 > last_grant;
+ assign T_1709 = T_1551 & T_1708;
+ assign T_1710 = T_1709 | T_1651;
+ assign T_1712 = 3'h6 > last_grant;
+ assign T_1713 = T_1560 & T_1712;
+ assign T_1714 = T_1713 | T_1668;
+ assign T_1716 = 3'h7 > last_grant;
+ assign T_1717 = T_1570 & T_1716;
+ assign T_1718 = T_1717 | T_1686;
+ assign T_1720 = T_1320 == 1'h0;
+ assign T_1721 = T_1318 ? T_1720 : T_1690;
+ assign T_1722 = T_1721 & io_out_ready;
+ assign T_1724 = T_1320 == 1'h1;
+ assign T_1725 = T_1318 ? T_1724 : T_1694;
+ assign T_1726 = T_1725 & io_out_ready;
+ assign T_1728 = T_1320 == 2'h2;
+ assign T_1729 = T_1318 ? T_1728 : T_1698;
+ assign T_1730 = T_1729 & io_out_ready;
+ assign T_1732 = T_1320 == 2'h3;
+ assign T_1733 = T_1318 ? T_1732 : T_1702;
+ assign T_1734 = T_1733 & io_out_ready;
+ assign T_1736 = T_1320 == 3'h4;
+ assign T_1737 = T_1318 ? T_1736 : T_1706;
+ assign T_1738 = T_1737 & io_out_ready;
+ assign T_1740 = T_1320 == 3'h5;
+ assign T_1741 = T_1318 ? T_1740 : T_1710;
+ assign T_1742 = T_1741 & io_out_ready;
+ assign T_1744 = T_1320 == 3'h6;
+ assign T_1745 = T_1318 ? T_1744 : T_1714;
+ assign T_1746 = T_1745 & io_out_ready;
+ assign T_1748 = T_1320 == 3'h7;
+ assign T_1749 = T_1318 ? T_1748 : T_1718;
+ assign T_1750 = T_1749 & io_out_ready;
+ assign T_1754 = T_1752 + 1'h1;
+ assign T_1755 = T_1754[1:0];
+ assign T_1756 = io_out_ready & io_out_valid;
+ assign T_1759 = T_1318 == 1'h0;
+ assign T_1761 = io_in_0_ready & io_in_0_valid;
+ assign T_1762 = io_in_1_ready & io_in_1_valid;
+ assign T_1763 = io_in_2_ready & io_in_2_valid;
+ assign T_1764 = io_in_3_ready & io_in_3_valid;
+ assign T_1765 = io_in_4_ready & io_in_4_valid;
+ assign T_1766 = io_in_5_ready & io_in_5_valid;
+ assign T_1767 = io_in_6_ready & io_in_6_valid;
+ assign T_1768 = io_in_7_ready & io_in_7_valid;
+ assign T_1770_0 = T_1761;
+ assign T_1770_1 = T_1762;
+ assign T_1770_2 = T_1763;
+ assign T_1770_3 = T_1764;
+ assign T_1770_4 = T_1765;
+ assign T_1770_5 = T_1766;
+ assign T_1770_6 = T_1767;
+ assign T_1770_7 = T_1768;
+ assign T_1788 = T_1770_6 ? 3'h6 : 3'h7;
+ assign T_1789 = T_1770_5 ? 3'h5 : T_1788;
+ assign T_1790 = T_1770_4 ? 3'h4 : T_1789;
+ assign T_1791 = T_1770_3 ? 2'h3 : T_1790;
+ assign T_1792 = T_1770_2 ? 2'h2 : T_1791;
+ assign T_1793 = T_1770_1 ? 1'h1 : T_1792;
+ assign T_1794 = T_1770_0 ? 1'h0 : T_1793;
+ assign T_1796 = T_1755 == 1'h0;
+ assign T_1800 = io_in_6_valid ? 3'h6 : 3'h7;
+ assign T_1802 = io_in_5_valid ? 3'h5 : T_1800;
+ assign T_1804 = io_in_4_valid ? 3'h4 : T_1802;
+ assign T_1806 = io_in_3_valid ? 2'h3 : T_1804;
+ assign T_1808 = io_in_2_valid ? 2'h2 : T_1806;
+ assign T_1810 = io_in_1_valid ? 1'h1 : T_1808;
+ assign T_1812 = io_in_0_valid ? 1'h0 : T_1810;
+ assign T_1814 = 3'h7 > last_grant;
+ assign T_1815 = io_in_7_valid & T_1814;
+ assign T_1817 = T_1815 ? 3'h7 : T_1812;
+ assign T_1819 = 3'h6 > last_grant;
+ assign T_1820 = io_in_6_valid & T_1819;
+ assign T_1822 = T_1820 ? 3'h6 : T_1817;
+ assign T_1824 = 3'h5 > last_grant;
+ assign T_1825 = io_in_5_valid & T_1824;
+ assign T_1827 = T_1825 ? 3'h5 : T_1822;
+ assign T_1829 = 3'h4 > last_grant;
+ assign T_1830 = io_in_4_valid & T_1829;
+ assign T_1832 = T_1830 ? 3'h4 : T_1827;
+ assign T_1834 = 2'h3 > last_grant;
+ assign T_1835 = io_in_3_valid & T_1834;
+ assign T_1837 = T_1835 ? 2'h3 : T_1832;
+ assign T_1839 = 2'h2 > last_grant;
+ assign T_1840 = io_in_2_valid & T_1839;
+ assign T_1842 = T_1840 ? 2'h2 : T_1837;
+ assign T_1844 = 1'h1 > last_grant;
+ assign T_1845 = io_in_1_valid & T_1844;
+ assign choose = T_1845 ? 1'h1 : T_1842;
+ assign T_1848 = T_1318 ? T_1320 : choose;
+ assign T_1849 = io_out_ready & io_out_valid;
+ assign GEN_5 = 3'h7 == T_1322;
+ assign GEN_6 = 3'h6 == T_1322;
+ assign GEN_7 = 3'h5 == T_1322;
+ assign GEN_8 = 3'h4 == T_1322;
+ assign GEN_9 = 2'h3 == T_1322;
+ assign GEN_10 = 2'h2 == T_1322;
+ assign GEN_11 = 1'h1 == T_1322;
+ assign GEN_12 = 3'h7 == T_1322;
+ assign GEN_13 = 3'h6 == T_1322;
+ assign GEN_14 = 3'h5 == T_1322;
+ assign GEN_15 = 3'h4 == T_1322;
+ assign GEN_16 = 2'h3 == T_1322;
+ assign GEN_17 = 2'h2 == T_1322;
+ assign GEN_18 = 1'h1 == T_1322;
+ assign GEN_19 = 3'h7 == T_1322;
+ assign GEN_20 = 3'h6 == T_1322;
+ assign GEN_21 = 3'h5 == T_1322;
+ assign GEN_22 = 3'h4 == T_1322;
+ assign GEN_23 = 2'h3 == T_1322;
+ assign GEN_24 = 2'h2 == T_1322;
+ assign GEN_25 = 1'h1 == T_1322;
+ assign GEN_26 = 3'h7 == T_1322;
+ assign GEN_27 = 3'h6 == T_1322;
+ assign GEN_28 = 3'h5 == T_1322;
+ assign GEN_29 = 3'h4 == T_1322;
+ assign GEN_30 = 2'h3 == T_1322;
+ assign GEN_31 = 2'h2 == T_1322;
+ assign GEN_32 = 1'h1 == T_1322;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_1318 = {1{$random}};
+ T_1320 = {1{$random}};
+ last_grant = {1{$random}};
+ T_1752 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ T_1318 <= 1'h0;
+ end else begin
+ if(T_1756) begin
+ if(T_1796) begin
+ T_1318 <= 1'h0;
+ end else begin
+ if(1'h0) begin
+ if(T_1759) begin
+ T_1318 <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_1320 <= 3'h7;
+ end else begin
+ if(T_1756) begin
+ if(1'h0) begin
+ if(T_1759) begin
+ T_1320 <= T_1794;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ last_grant <= 3'h0;
+ end else begin
+ if(T_1849) begin
+ last_grant <= T_1322;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_1752 <= 2'h0;
+ end else begin
+ if(T_1756) begin
+ if(1'h0) begin
+ T_1752 <= T_1755;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module LockingRRArbiter_35(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input [25:0] io_in_0_bits_addr_block,
+ input [3:0] io_in_0_bits_client_xact_id,
+ input [1:0] io_in_0_bits_addr_beat,
+ input io_in_0_bits_is_builtin_type,
+ input [2:0] io_in_0_bits_a_type,
+ input [16:0] io_in_0_bits_union,
+ input [3:0] io_in_0_bits_data,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input [25:0] io_in_1_bits_addr_block,
+ input [3:0] io_in_1_bits_client_xact_id,
+ input [1:0] io_in_1_bits_addr_beat,
+ input io_in_1_bits_is_builtin_type,
+ input [2:0] io_in_1_bits_a_type,
+ input [16:0] io_in_1_bits_union,
+ input [3:0] io_in_1_bits_data,
+ output io_in_2_ready,
+ input io_in_2_valid,
+ input [25:0] io_in_2_bits_addr_block,
+ input [3:0] io_in_2_bits_client_xact_id,
+ input [1:0] io_in_2_bits_addr_beat,
+ input io_in_2_bits_is_builtin_type,
+ input [2:0] io_in_2_bits_a_type,
+ input [16:0] io_in_2_bits_union,
+ input [3:0] io_in_2_bits_data,
+ output io_in_3_ready,
+ input io_in_3_valid,
+ input [25:0] io_in_3_bits_addr_block,
+ input [3:0] io_in_3_bits_client_xact_id,
+ input [1:0] io_in_3_bits_addr_beat,
+ input io_in_3_bits_is_builtin_type,
+ input [2:0] io_in_3_bits_a_type,
+ input [16:0] io_in_3_bits_union,
+ input [3:0] io_in_3_bits_data,
+ output io_in_4_ready,
+ input io_in_4_valid,
+ input [25:0] io_in_4_bits_addr_block,
+ input [3:0] io_in_4_bits_client_xact_id,
+ input [1:0] io_in_4_bits_addr_beat,
+ input io_in_4_bits_is_builtin_type,
+ input [2:0] io_in_4_bits_a_type,
+ input [16:0] io_in_4_bits_union,
+ input [3:0] io_in_4_bits_data,
+ output io_in_5_ready,
+ input io_in_5_valid,
+ input [25:0] io_in_5_bits_addr_block,
+ input [3:0] io_in_5_bits_client_xact_id,
+ input [1:0] io_in_5_bits_addr_beat,
+ input io_in_5_bits_is_builtin_type,
+ input [2:0] io_in_5_bits_a_type,
+ input [16:0] io_in_5_bits_union,
+ input [3:0] io_in_5_bits_data,
+ output io_in_6_ready,
+ input io_in_6_valid,
+ input [25:0] io_in_6_bits_addr_block,
+ input [3:0] io_in_6_bits_client_xact_id,
+ input [1:0] io_in_6_bits_addr_beat,
+ input io_in_6_bits_is_builtin_type,
+ input [2:0] io_in_6_bits_a_type,
+ input [16:0] io_in_6_bits_union,
+ input [3:0] io_in_6_bits_data,
+ output io_in_7_ready,
+ input io_in_7_valid,
+ input [25:0] io_in_7_bits_addr_block,
+ input [3:0] io_in_7_bits_client_xact_id,
+ input [1:0] io_in_7_bits_addr_beat,
+ input io_in_7_bits_is_builtin_type,
+ input [2:0] io_in_7_bits_a_type,
+ input [16:0] io_in_7_bits_union,
+ input [3:0] io_in_7_bits_data,
+ input io_out_ready,
+ output io_out_valid,
+ output [25:0] io_out_bits_addr_block,
+ output [3:0] io_out_bits_client_xact_id,
+ output [1:0] io_out_bits_addr_beat,
+ output io_out_bits_is_builtin_type,
+ output [2:0] io_out_bits_a_type,
+ output [16:0] io_out_bits_union,
+ output [3:0] io_out_bits_data,
+ output [2:0] io_chosen
+);
+ reg T_444;
+ reg [2:0] T_446;
+ wire [2:0] T_448;
+ wire GEN_0;
+ wire [25:0] GEN_1;
+ wire [3:0] GEN_2;
+ wire [1:0] GEN_3;
+ wire GEN_4;
+ wire [2:0] GEN_5;
+ wire [16:0] GEN_6;
+ wire [3:0] GEN_7;
+ wire GEN_8;
+ reg [2:0] last_grant;
+ wire T_510;
+ wire T_511;
+ wire T_513;
+ wire T_514;
+ wire T_516;
+ wire T_517;
+ wire T_519;
+ wire T_520;
+ wire T_522;
+ wire T_523;
+ wire T_525;
+ wire T_526;
+ wire T_528;
+ wire T_529;
+ wire T_531;
+ wire T_532;
+ wire T_535;
+ wire T_537;
+ wire T_539;
+ wire T_540;
+ wire T_542;
+ wire T_544;
+ wire T_545;
+ wire T_546;
+ wire T_548;
+ wire T_550;
+ wire T_551;
+ wire T_552;
+ wire T_553;
+ wire T_555;
+ wire T_557;
+ wire T_558;
+ wire T_559;
+ wire T_560;
+ wire T_561;
+ wire T_563;
+ wire T_565;
+ wire T_566;
+ wire T_567;
+ wire T_568;
+ wire T_569;
+ wire T_570;
+ wire T_572;
+ wire T_574;
+ wire T_575;
+ wire T_576;
+ wire T_577;
+ wire T_578;
+ wire T_579;
+ wire T_580;
+ wire T_582;
+ wire T_584;
+ wire T_585;
+ wire T_586;
+ wire T_587;
+ wire T_588;
+ wire T_589;
+ wire T_590;
+ wire T_591;
+ wire T_593;
+ wire T_595;
+ wire T_596;
+ wire T_597;
+ wire T_598;
+ wire T_599;
+ wire T_600;
+ wire T_601;
+ wire T_602;
+ wire T_603;
+ wire T_605;
+ wire T_607;
+ wire T_608;
+ wire T_609;
+ wire T_610;
+ wire T_611;
+ wire T_612;
+ wire T_613;
+ wire T_614;
+ wire T_615;
+ wire T_616;
+ wire T_618;
+ wire T_620;
+ wire T_621;
+ wire T_622;
+ wire T_623;
+ wire T_624;
+ wire T_625;
+ wire T_626;
+ wire T_627;
+ wire T_628;
+ wire T_629;
+ wire T_630;
+ wire T_632;
+ wire T_634;
+ wire T_635;
+ wire T_636;
+ wire T_637;
+ wire T_638;
+ wire T_639;
+ wire T_640;
+ wire T_641;
+ wire T_642;
+ wire T_643;
+ wire T_644;
+ wire T_645;
+ wire T_647;
+ wire T_649;
+ wire T_650;
+ wire T_651;
+ wire T_652;
+ wire T_653;
+ wire T_654;
+ wire T_655;
+ wire T_656;
+ wire T_657;
+ wire T_658;
+ wire T_659;
+ wire T_660;
+ wire T_661;
+ wire T_663;
+ wire T_665;
+ wire T_666;
+ wire T_667;
+ wire T_668;
+ wire T_669;
+ wire T_670;
+ wire T_671;
+ wire T_672;
+ wire T_673;
+ wire T_674;
+ wire T_675;
+ wire T_676;
+ wire T_677;
+ wire T_678;
+ wire T_680;
+ wire T_682;
+ wire T_683;
+ wire T_684;
+ wire T_685;
+ wire T_686;
+ wire T_687;
+ wire T_688;
+ wire T_689;
+ wire T_690;
+ wire T_691;
+ wire T_692;
+ wire T_693;
+ wire T_694;
+ wire T_695;
+ wire T_696;
+ wire T_698;
+ wire T_700;
+ wire T_701;
+ wire T_702;
+ wire T_704;
+ wire T_705;
+ wire T_706;
+ wire T_708;
+ wire T_709;
+ wire T_710;
+ wire T_712;
+ wire T_713;
+ wire T_714;
+ wire T_716;
+ wire T_717;
+ wire T_718;
+ wire T_720;
+ wire T_721;
+ wire T_722;
+ wire T_724;
+ wire T_725;
+ wire T_726;
+ wire T_728;
+ wire T_729;
+ wire T_730;
+ wire T_732;
+ wire T_733;
+ wire T_734;
+ wire T_736;
+ wire T_737;
+ wire T_738;
+ wire T_740;
+ wire T_741;
+ wire T_742;
+ wire T_744;
+ wire T_745;
+ wire T_746;
+ wire T_748;
+ wire T_749;
+ wire T_750;
+ wire T_752;
+ wire T_753;
+ wire T_754;
+ wire T_756;
+ wire T_757;
+ wire T_758;
+ wire T_760;
+ wire T_761;
+ wire T_762;
+ reg [1:0] T_764;
+ wire [2:0] T_766;
+ wire [1:0] T_767;
+ wire T_768;
+ wire T_770;
+ wire [2:0] T_773_0;
+ wire T_776;
+ wire T_778;
+ wire T_779;
+ wire T_781;
+ wire T_783;
+ wire T_784;
+ wire T_785;
+ wire T_786;
+ wire T_787;
+ wire T_788;
+ wire T_789;
+ wire T_790;
+ wire T_792_0;
+ wire T_792_1;
+ wire T_792_2;
+ wire T_792_3;
+ wire T_792_4;
+ wire T_792_5;
+ wire T_792_6;
+ wire T_792_7;
+ wire [2:0] T_810;
+ wire [2:0] T_811;
+ wire [2:0] T_812;
+ wire [2:0] T_813;
+ wire [2:0] T_814;
+ wire [2:0] T_815;
+ wire [2:0] T_816;
+ wire T_818;
+ wire [2:0] T_822;
+ wire [2:0] T_824;
+ wire [2:0] T_826;
+ wire [2:0] T_828;
+ wire [2:0] T_830;
+ wire [2:0] T_832;
+ wire [2:0] T_834;
+ wire T_836;
+ wire T_837;
+ wire [2:0] T_839;
+ wire T_841;
+ wire T_842;
+ wire [2:0] T_844;
+ wire T_846;
+ wire T_847;
+ wire [2:0] T_849;
+ wire T_851;
+ wire T_852;
+ wire [2:0] T_854;
+ wire T_856;
+ wire T_857;
+ wire [2:0] T_859;
+ wire T_861;
+ wire T_862;
+ wire [2:0] T_864;
+ wire T_866;
+ wire T_867;
+ wire [2:0] choose;
+ wire [2:0] T_870;
+ wire T_871;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ wire GEN_17;
+ wire GEN_18;
+ wire GEN_19;
+ wire GEN_20;
+ wire GEN_21;
+ wire GEN_22;
+ wire GEN_23;
+ wire GEN_24;
+ wire GEN_25;
+ wire GEN_26;
+ wire GEN_27;
+ wire GEN_28;
+ wire GEN_29;
+ wire GEN_30;
+ wire GEN_31;
+ wire GEN_32;
+ wire GEN_33;
+ wire GEN_34;
+ wire GEN_35;
+ wire GEN_36;
+ wire GEN_37;
+ wire GEN_38;
+ wire GEN_39;
+ wire GEN_40;
+ wire GEN_41;
+ wire GEN_42;
+ wire GEN_43;
+ wire GEN_44;
+ wire GEN_45;
+ wire GEN_46;
+ wire GEN_47;
+ wire GEN_48;
+ wire GEN_49;
+ wire GEN_50;
+ wire GEN_51;
+ wire GEN_52;
+ wire GEN_53;
+ wire GEN_54;
+ wire GEN_55;
+ wire GEN_56;
+ wire GEN_57;
+ wire GEN_58;
+ wire GEN_59;
+ wire GEN_60;
+ wire GEN_61;
+ wire GEN_62;
+ wire GEN_63;
+ wire GEN_64;
+ assign io_in_0_ready = T_734;
+ assign io_in_1_ready = T_738;
+ assign io_in_2_ready = T_742;
+ assign io_in_3_ready = T_746;
+ assign io_in_4_ready = T_750;
+ assign io_in_5_ready = T_754;
+ assign io_in_6_ready = T_758;
+ assign io_in_7_ready = T_762;
+ assign io_out_valid = GEN_0;
+ assign io_out_bits_addr_block = GEN_1;
+ assign io_out_bits_client_xact_id = GEN_2;
+ assign io_out_bits_addr_beat = GEN_3;
+ assign io_out_bits_is_builtin_type = GEN_4;
+ assign io_out_bits_a_type = GEN_5;
+ assign io_out_bits_union = GEN_6;
+ assign io_out_bits_data = GEN_7;
+ assign io_chosen = T_448;
+ assign T_448 = T_870;
+ assign GEN_0 = GEN_9 ? io_in_7_valid : GEN_10 ? io_in_6_valid : GEN_11 ? io_in_5_valid : GEN_12 ? io_in_4_valid : GEN_13 ? io_in_3_valid : GEN_14 ? io_in_2_valid : GEN_15 ? io_in_1_valid : io_in_0_valid;
+ assign GEN_1 = GEN_16 ? io_in_7_bits_addr_block : GEN_17 ? io_in_6_bits_addr_block : GEN_18 ? io_in_5_bits_addr_block : GEN_19 ? io_in_4_bits_addr_block : GEN_20 ? io_in_3_bits_addr_block : GEN_21 ? io_in_2_bits_addr_block : GEN_22 ? io_in_1_bits_addr_block : io_in_0_bits_addr_block;
+ assign GEN_2 = GEN_23 ? io_in_7_bits_client_xact_id : GEN_24 ? io_in_6_bits_client_xact_id : GEN_25 ? io_in_5_bits_client_xact_id : GEN_26 ? io_in_4_bits_client_xact_id : GEN_27 ? io_in_3_bits_client_xact_id : GEN_28 ? io_in_2_bits_client_xact_id : GEN_29 ? io_in_1_bits_client_xact_id : io_in_0_bits_client_xact_id;
+ assign GEN_3 = GEN_30 ? io_in_7_bits_addr_beat : GEN_31 ? io_in_6_bits_addr_beat : GEN_32 ? io_in_5_bits_addr_beat : GEN_33 ? io_in_4_bits_addr_beat : GEN_34 ? io_in_3_bits_addr_beat : GEN_35 ? io_in_2_bits_addr_beat : GEN_36 ? io_in_1_bits_addr_beat : io_in_0_bits_addr_beat;
+ assign GEN_4 = GEN_37 ? io_in_7_bits_is_builtin_type : GEN_38 ? io_in_6_bits_is_builtin_type : GEN_39 ? io_in_5_bits_is_builtin_type : GEN_40 ? io_in_4_bits_is_builtin_type : GEN_41 ? io_in_3_bits_is_builtin_type : GEN_42 ? io_in_2_bits_is_builtin_type : GEN_43 ? io_in_1_bits_is_builtin_type : io_in_0_bits_is_builtin_type;
+ assign GEN_5 = GEN_44 ? io_in_7_bits_a_type : GEN_45 ? io_in_6_bits_a_type : GEN_46 ? io_in_5_bits_a_type : GEN_47 ? io_in_4_bits_a_type : GEN_48 ? io_in_3_bits_a_type : GEN_49 ? io_in_2_bits_a_type : GEN_50 ? io_in_1_bits_a_type : io_in_0_bits_a_type;
+ assign GEN_6 = GEN_51 ? io_in_7_bits_union : GEN_52 ? io_in_6_bits_union : GEN_53 ? io_in_5_bits_union : GEN_54 ? io_in_4_bits_union : GEN_55 ? io_in_3_bits_union : GEN_56 ? io_in_2_bits_union : GEN_57 ? io_in_1_bits_union : io_in_0_bits_union;
+ assign GEN_7 = GEN_58 ? io_in_7_bits_data : GEN_59 ? io_in_6_bits_data : GEN_60 ? io_in_5_bits_data : GEN_61 ? io_in_4_bits_data : GEN_62 ? io_in_3_bits_data : GEN_63 ? io_in_2_bits_data : GEN_64 ? io_in_1_bits_data : io_in_0_bits_data;
+ assign GEN_8 = 1'h0;
+ assign T_510 = 1'h0 > last_grant;
+ assign T_511 = io_in_0_valid & T_510;
+ assign T_513 = 1'h1 > last_grant;
+ assign T_514 = io_in_1_valid & T_513;
+ assign T_516 = 2'h2 > last_grant;
+ assign T_517 = io_in_2_valid & T_516;
+ assign T_519 = 2'h3 > last_grant;
+ assign T_520 = io_in_3_valid & T_519;
+ assign T_522 = 3'h4 > last_grant;
+ assign T_523 = io_in_4_valid & T_522;
+ assign T_525 = 3'h5 > last_grant;
+ assign T_526 = io_in_5_valid & T_525;
+ assign T_528 = 3'h6 > last_grant;
+ assign T_529 = io_in_6_valid & T_528;
+ assign T_531 = 3'h7 > last_grant;
+ assign T_532 = io_in_7_valid & T_531;
+ assign T_535 = 1'h0 | T_511;
+ assign T_537 = T_535 == 1'h0;
+ assign T_539 = 1'h0 | T_511;
+ assign T_540 = T_539 | T_514;
+ assign T_542 = T_540 == 1'h0;
+ assign T_544 = 1'h0 | T_511;
+ assign T_545 = T_544 | T_514;
+ assign T_546 = T_545 | T_517;
+ assign T_548 = T_546 == 1'h0;
+ assign T_550 = 1'h0 | T_511;
+ assign T_551 = T_550 | T_514;
+ assign T_552 = T_551 | T_517;
+ assign T_553 = T_552 | T_520;
+ assign T_555 = T_553 == 1'h0;
+ assign T_557 = 1'h0 | T_511;
+ assign T_558 = T_557 | T_514;
+ assign T_559 = T_558 | T_517;
+ assign T_560 = T_559 | T_520;
+ assign T_561 = T_560 | T_523;
+ assign T_563 = T_561 == 1'h0;
+ assign T_565 = 1'h0 | T_511;
+ assign T_566 = T_565 | T_514;
+ assign T_567 = T_566 | T_517;
+ assign T_568 = T_567 | T_520;
+ assign T_569 = T_568 | T_523;
+ assign T_570 = T_569 | T_526;
+ assign T_572 = T_570 == 1'h0;
+ assign T_574 = 1'h0 | T_511;
+ assign T_575 = T_574 | T_514;
+ assign T_576 = T_575 | T_517;
+ assign T_577 = T_576 | T_520;
+ assign T_578 = T_577 | T_523;
+ assign T_579 = T_578 | T_526;
+ assign T_580 = T_579 | T_529;
+ assign T_582 = T_580 == 1'h0;
+ assign T_584 = 1'h0 | T_511;
+ assign T_585 = T_584 | T_514;
+ assign T_586 = T_585 | T_517;
+ assign T_587 = T_586 | T_520;
+ assign T_588 = T_587 | T_523;
+ assign T_589 = T_588 | T_526;
+ assign T_590 = T_589 | T_529;
+ assign T_591 = T_590 | T_532;
+ assign T_593 = T_591 == 1'h0;
+ assign T_595 = 1'h0 | T_511;
+ assign T_596 = T_595 | T_514;
+ assign T_597 = T_596 | T_517;
+ assign T_598 = T_597 | T_520;
+ assign T_599 = T_598 | T_523;
+ assign T_600 = T_599 | T_526;
+ assign T_601 = T_600 | T_529;
+ assign T_602 = T_601 | T_532;
+ assign T_603 = T_602 | io_in_0_valid;
+ assign T_605 = T_603 == 1'h0;
+ assign T_607 = 1'h0 | T_511;
+ assign T_608 = T_607 | T_514;
+ assign T_609 = T_608 | T_517;
+ assign T_610 = T_609 | T_520;
+ assign T_611 = T_610 | T_523;
+ assign T_612 = T_611 | T_526;
+ assign T_613 = T_612 | T_529;
+ assign T_614 = T_613 | T_532;
+ assign T_615 = T_614 | io_in_0_valid;
+ assign T_616 = T_615 | io_in_1_valid;
+ assign T_618 = T_616 == 1'h0;
+ assign T_620 = 1'h0 | T_511;
+ assign T_621 = T_620 | T_514;
+ assign T_622 = T_621 | T_517;
+ assign T_623 = T_622 | T_520;
+ assign T_624 = T_623 | T_523;
+ assign T_625 = T_624 | T_526;
+ assign T_626 = T_625 | T_529;
+ assign T_627 = T_626 | T_532;
+ assign T_628 = T_627 | io_in_0_valid;
+ assign T_629 = T_628 | io_in_1_valid;
+ assign T_630 = T_629 | io_in_2_valid;
+ assign T_632 = T_630 == 1'h0;
+ assign T_634 = 1'h0 | T_511;
+ assign T_635 = T_634 | T_514;
+ assign T_636 = T_635 | T_517;
+ assign T_637 = T_636 | T_520;
+ assign T_638 = T_637 | T_523;
+ assign T_639 = T_638 | T_526;
+ assign T_640 = T_639 | T_529;
+ assign T_641 = T_640 | T_532;
+ assign T_642 = T_641 | io_in_0_valid;
+ assign T_643 = T_642 | io_in_1_valid;
+ assign T_644 = T_643 | io_in_2_valid;
+ assign T_645 = T_644 | io_in_3_valid;
+ assign T_647 = T_645 == 1'h0;
+ assign T_649 = 1'h0 | T_511;
+ assign T_650 = T_649 | T_514;
+ assign T_651 = T_650 | T_517;
+ assign T_652 = T_651 | T_520;
+ assign T_653 = T_652 | T_523;
+ assign T_654 = T_653 | T_526;
+ assign T_655 = T_654 | T_529;
+ assign T_656 = T_655 | T_532;
+ assign T_657 = T_656 | io_in_0_valid;
+ assign T_658 = T_657 | io_in_1_valid;
+ assign T_659 = T_658 | io_in_2_valid;
+ assign T_660 = T_659 | io_in_3_valid;
+ assign T_661 = T_660 | io_in_4_valid;
+ assign T_663 = T_661 == 1'h0;
+ assign T_665 = 1'h0 | T_511;
+ assign T_666 = T_665 | T_514;
+ assign T_667 = T_666 | T_517;
+ assign T_668 = T_667 | T_520;
+ assign T_669 = T_668 | T_523;
+ assign T_670 = T_669 | T_526;
+ assign T_671 = T_670 | T_529;
+ assign T_672 = T_671 | T_532;
+ assign T_673 = T_672 | io_in_0_valid;
+ assign T_674 = T_673 | io_in_1_valid;
+ assign T_675 = T_674 | io_in_2_valid;
+ assign T_676 = T_675 | io_in_3_valid;
+ assign T_677 = T_676 | io_in_4_valid;
+ assign T_678 = T_677 | io_in_5_valid;
+ assign T_680 = T_678 == 1'h0;
+ assign T_682 = 1'h0 | T_511;
+ assign T_683 = T_682 | T_514;
+ assign T_684 = T_683 | T_517;
+ assign T_685 = T_684 | T_520;
+ assign T_686 = T_685 | T_523;
+ assign T_687 = T_686 | T_526;
+ assign T_688 = T_687 | T_529;
+ assign T_689 = T_688 | T_532;
+ assign T_690 = T_689 | io_in_0_valid;
+ assign T_691 = T_690 | io_in_1_valid;
+ assign T_692 = T_691 | io_in_2_valid;
+ assign T_693 = T_692 | io_in_3_valid;
+ assign T_694 = T_693 | io_in_4_valid;
+ assign T_695 = T_694 | io_in_5_valid;
+ assign T_696 = T_695 | io_in_6_valid;
+ assign T_698 = T_696 == 1'h0;
+ assign T_700 = 1'h0 > last_grant;
+ assign T_701 = 1'h1 & T_700;
+ assign T_702 = T_701 | T_593;
+ assign T_704 = 1'h1 > last_grant;
+ assign T_705 = T_537 & T_704;
+ assign T_706 = T_705 | T_605;
+ assign T_708 = 2'h2 > last_grant;
+ assign T_709 = T_542 & T_708;
+ assign T_710 = T_709 | T_618;
+ assign T_712 = 2'h3 > last_grant;
+ assign T_713 = T_548 & T_712;
+ assign T_714 = T_713 | T_632;
+ assign T_716 = 3'h4 > last_grant;
+ assign T_717 = T_555 & T_716;
+ assign T_718 = T_717 | T_647;
+ assign T_720 = 3'h5 > last_grant;
+ assign T_721 = T_563 & T_720;
+ assign T_722 = T_721 | T_663;
+ assign T_724 = 3'h6 > last_grant;
+ assign T_725 = T_572 & T_724;
+ assign T_726 = T_725 | T_680;
+ assign T_728 = 3'h7 > last_grant;
+ assign T_729 = T_582 & T_728;
+ assign T_730 = T_729 | T_698;
+ assign T_732 = T_446 == 1'h0;
+ assign T_733 = T_444 ? T_732 : T_702;
+ assign T_734 = T_733 & io_out_ready;
+ assign T_736 = T_446 == 1'h1;
+ assign T_737 = T_444 ? T_736 : T_706;
+ assign T_738 = T_737 & io_out_ready;
+ assign T_740 = T_446 == 2'h2;
+ assign T_741 = T_444 ? T_740 : T_710;
+ assign T_742 = T_741 & io_out_ready;
+ assign T_744 = T_446 == 2'h3;
+ assign T_745 = T_444 ? T_744 : T_714;
+ assign T_746 = T_745 & io_out_ready;
+ assign T_748 = T_446 == 3'h4;
+ assign T_749 = T_444 ? T_748 : T_718;
+ assign T_750 = T_749 & io_out_ready;
+ assign T_752 = T_446 == 3'h5;
+ assign T_753 = T_444 ? T_752 : T_722;
+ assign T_754 = T_753 & io_out_ready;
+ assign T_756 = T_446 == 3'h6;
+ assign T_757 = T_444 ? T_756 : T_726;
+ assign T_758 = T_757 & io_out_ready;
+ assign T_760 = T_446 == 3'h7;
+ assign T_761 = T_444 ? T_760 : T_730;
+ assign T_762 = T_761 & io_out_ready;
+ assign T_766 = T_764 + 1'h1;
+ assign T_767 = T_766[1:0];
+ assign T_768 = io_out_ready & io_out_valid;
+ assign T_770 = 1'h1 & io_out_bits_is_builtin_type;
+ assign T_773_0 = 3'h3;
+ assign T_776 = T_773_0 == io_out_bits_a_type;
+ assign T_778 = 1'h0 | T_776;
+ assign T_779 = T_770 & T_778;
+ assign T_781 = T_444 == 1'h0;
+ assign T_783 = io_in_0_ready & io_in_0_valid;
+ assign T_784 = io_in_1_ready & io_in_1_valid;
+ assign T_785 = io_in_2_ready & io_in_2_valid;
+ assign T_786 = io_in_3_ready & io_in_3_valid;
+ assign T_787 = io_in_4_ready & io_in_4_valid;
+ assign T_788 = io_in_5_ready & io_in_5_valid;
+ assign T_789 = io_in_6_ready & io_in_6_valid;
+ assign T_790 = io_in_7_ready & io_in_7_valid;
+ assign T_792_0 = T_783;
+ assign T_792_1 = T_784;
+ assign T_792_2 = T_785;
+ assign T_792_3 = T_786;
+ assign T_792_4 = T_787;
+ assign T_792_5 = T_788;
+ assign T_792_6 = T_789;
+ assign T_792_7 = T_790;
+ assign T_810 = T_792_6 ? 3'h6 : 3'h7;
+ assign T_811 = T_792_5 ? 3'h5 : T_810;
+ assign T_812 = T_792_4 ? 3'h4 : T_811;
+ assign T_813 = T_792_3 ? 2'h3 : T_812;
+ assign T_814 = T_792_2 ? 2'h2 : T_813;
+ assign T_815 = T_792_1 ? 1'h1 : T_814;
+ assign T_816 = T_792_0 ? 1'h0 : T_815;
+ assign T_818 = T_767 == 1'h0;
+ assign T_822 = io_in_6_valid ? 3'h6 : 3'h7;
+ assign T_824 = io_in_5_valid ? 3'h5 : T_822;
+ assign T_826 = io_in_4_valid ? 3'h4 : T_824;
+ assign T_828 = io_in_3_valid ? 2'h3 : T_826;
+ assign T_830 = io_in_2_valid ? 2'h2 : T_828;
+ assign T_832 = io_in_1_valid ? 1'h1 : T_830;
+ assign T_834 = io_in_0_valid ? 1'h0 : T_832;
+ assign T_836 = 3'h7 > last_grant;
+ assign T_837 = io_in_7_valid & T_836;
+ assign T_839 = T_837 ? 3'h7 : T_834;
+ assign T_841 = 3'h6 > last_grant;
+ assign T_842 = io_in_6_valid & T_841;
+ assign T_844 = T_842 ? 3'h6 : T_839;
+ assign T_846 = 3'h5 > last_grant;
+ assign T_847 = io_in_5_valid & T_846;
+ assign T_849 = T_847 ? 3'h5 : T_844;
+ assign T_851 = 3'h4 > last_grant;
+ assign T_852 = io_in_4_valid & T_851;
+ assign T_854 = T_852 ? 3'h4 : T_849;
+ assign T_856 = 2'h3 > last_grant;
+ assign T_857 = io_in_3_valid & T_856;
+ assign T_859 = T_857 ? 2'h3 : T_854;
+ assign T_861 = 2'h2 > last_grant;
+ assign T_862 = io_in_2_valid & T_861;
+ assign T_864 = T_862 ? 2'h2 : T_859;
+ assign T_866 = 1'h1 > last_grant;
+ assign T_867 = io_in_1_valid & T_866;
+ assign choose = T_867 ? 1'h1 : T_864;
+ assign T_870 = T_444 ? T_446 : choose;
+ assign T_871 = io_out_ready & io_out_valid;
+ assign GEN_9 = 3'h7 == T_448;
+ assign GEN_10 = 3'h6 == T_448;
+ assign GEN_11 = 3'h5 == T_448;
+ assign GEN_12 = 3'h4 == T_448;
+ assign GEN_13 = 2'h3 == T_448;
+ assign GEN_14 = 2'h2 == T_448;
+ assign GEN_15 = 1'h1 == T_448;
+ assign GEN_16 = 3'h7 == T_448;
+ assign GEN_17 = 3'h6 == T_448;
+ assign GEN_18 = 3'h5 == T_448;
+ assign GEN_19 = 3'h4 == T_448;
+ assign GEN_20 = 2'h3 == T_448;
+ assign GEN_21 = 2'h2 == T_448;
+ assign GEN_22 = 1'h1 == T_448;
+ assign GEN_23 = 3'h7 == T_448;
+ assign GEN_24 = 3'h6 == T_448;
+ assign GEN_25 = 3'h5 == T_448;
+ assign GEN_26 = 3'h4 == T_448;
+ assign GEN_27 = 2'h3 == T_448;
+ assign GEN_28 = 2'h2 == T_448;
+ assign GEN_29 = 1'h1 == T_448;
+ assign GEN_30 = 3'h7 == T_448;
+ assign GEN_31 = 3'h6 == T_448;
+ assign GEN_32 = 3'h5 == T_448;
+ assign GEN_33 = 3'h4 == T_448;
+ assign GEN_34 = 2'h3 == T_448;
+ assign GEN_35 = 2'h2 == T_448;
+ assign GEN_36 = 1'h1 == T_448;
+ assign GEN_37 = 3'h7 == T_448;
+ assign GEN_38 = 3'h6 == T_448;
+ assign GEN_39 = 3'h5 == T_448;
+ assign GEN_40 = 3'h4 == T_448;
+ assign GEN_41 = 2'h3 == T_448;
+ assign GEN_42 = 2'h2 == T_448;
+ assign GEN_43 = 1'h1 == T_448;
+ assign GEN_44 = 3'h7 == T_448;
+ assign GEN_45 = 3'h6 == T_448;
+ assign GEN_46 = 3'h5 == T_448;
+ assign GEN_47 = 3'h4 == T_448;
+ assign GEN_48 = 2'h3 == T_448;
+ assign GEN_49 = 2'h2 == T_448;
+ assign GEN_50 = 1'h1 == T_448;
+ assign GEN_51 = 3'h7 == T_448;
+ assign GEN_52 = 3'h6 == T_448;
+ assign GEN_53 = 3'h5 == T_448;
+ assign GEN_54 = 3'h4 == T_448;
+ assign GEN_55 = 2'h3 == T_448;
+ assign GEN_56 = 2'h2 == T_448;
+ assign GEN_57 = 1'h1 == T_448;
+ assign GEN_58 = 3'h7 == T_448;
+ assign GEN_59 = 3'h6 == T_448;
+ assign GEN_60 = 3'h5 == T_448;
+ assign GEN_61 = 3'h4 == T_448;
+ assign GEN_62 = 2'h3 == T_448;
+ assign GEN_63 = 2'h2 == T_448;
+ assign GEN_64 = 1'h1 == T_448;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_444 = {1{$random}};
+ T_446 = {1{$random}};
+ last_grant = {1{$random}};
+ T_764 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ T_444 <= 1'h0;
+ end else begin
+ if(T_768) begin
+ if(T_818) begin
+ T_444 <= 1'h0;
+ end else begin
+ if(T_779) begin
+ if(T_781) begin
+ T_444 <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_446 <= 3'h7;
+ end else begin
+ if(T_768) begin
+ if(T_779) begin
+ if(T_781) begin
+ T_446 <= T_816;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ last_grant <= 3'h0;
+ end else begin
+ if(T_871) begin
+ last_grant <= T_448;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_764 <= 2'h0;
+ end else begin
+ if(T_768) begin
+ if(T_779) begin
+ T_764 <= T_767;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module ClientUncachedTileLinkIOArbiter(
+ input clk,
+ input reset,
+ output io_in_0_acquire_ready,
+ input io_in_0_acquire_valid,
+ input [25:0] io_in_0_acquire_bits_addr_block,
+ input [3:0] io_in_0_acquire_bits_client_xact_id,
+ input [1:0] io_in_0_acquire_bits_addr_beat,
+ input io_in_0_acquire_bits_is_builtin_type,
+ input [2:0] io_in_0_acquire_bits_a_type,
+ input [16:0] io_in_0_acquire_bits_union,
+ input [3:0] io_in_0_acquire_bits_data,
+ input io_in_0_grant_ready,
+ output io_in_0_grant_valid,
+ output [1:0] io_in_0_grant_bits_addr_beat,
+ output [3:0] io_in_0_grant_bits_client_xact_id,
+ output io_in_0_grant_bits_manager_xact_id,
+ output io_in_0_grant_bits_is_builtin_type,
+ output [3:0] io_in_0_grant_bits_g_type,
+ output [3:0] io_in_0_grant_bits_data,
+ output io_in_1_acquire_ready,
+ input io_in_1_acquire_valid,
+ input [25:0] io_in_1_acquire_bits_addr_block,
+ input [3:0] io_in_1_acquire_bits_client_xact_id,
+ input [1:0] io_in_1_acquire_bits_addr_beat,
+ input io_in_1_acquire_bits_is_builtin_type,
+ input [2:0] io_in_1_acquire_bits_a_type,
+ input [16:0] io_in_1_acquire_bits_union,
+ input [3:0] io_in_1_acquire_bits_data,
+ input io_in_1_grant_ready,
+ output io_in_1_grant_valid,
+ output [1:0] io_in_1_grant_bits_addr_beat,
+ output [3:0] io_in_1_grant_bits_client_xact_id,
+ output io_in_1_grant_bits_manager_xact_id,
+ output io_in_1_grant_bits_is_builtin_type,
+ output [3:0] io_in_1_grant_bits_g_type,
+ output [3:0] io_in_1_grant_bits_data,
+ output io_in_2_acquire_ready,
+ input io_in_2_acquire_valid,
+ input [25:0] io_in_2_acquire_bits_addr_block,
+ input [3:0] io_in_2_acquire_bits_client_xact_id,
+ input [1:0] io_in_2_acquire_bits_addr_beat,
+ input io_in_2_acquire_bits_is_builtin_type,
+ input [2:0] io_in_2_acquire_bits_a_type,
+ input [16:0] io_in_2_acquire_bits_union,
+ input [3:0] io_in_2_acquire_bits_data,
+ input io_in_2_grant_ready,
+ output io_in_2_grant_valid,
+ output [1:0] io_in_2_grant_bits_addr_beat,
+ output [3:0] io_in_2_grant_bits_client_xact_id,
+ output io_in_2_grant_bits_manager_xact_id,
+ output io_in_2_grant_bits_is_builtin_type,
+ output [3:0] io_in_2_grant_bits_g_type,
+ output [3:0] io_in_2_grant_bits_data,
+ output io_in_3_acquire_ready,
+ input io_in_3_acquire_valid,
+ input [25:0] io_in_3_acquire_bits_addr_block,
+ input [3:0] io_in_3_acquire_bits_client_xact_id,
+ input [1:0] io_in_3_acquire_bits_addr_beat,
+ input io_in_3_acquire_bits_is_builtin_type,
+ input [2:0] io_in_3_acquire_bits_a_type,
+ input [16:0] io_in_3_acquire_bits_union,
+ input [3:0] io_in_3_acquire_bits_data,
+ input io_in_3_grant_ready,
+ output io_in_3_grant_valid,
+ output [1:0] io_in_3_grant_bits_addr_beat,
+ output [3:0] io_in_3_grant_bits_client_xact_id,
+ output io_in_3_grant_bits_manager_xact_id,
+ output io_in_3_grant_bits_is_builtin_type,
+ output [3:0] io_in_3_grant_bits_g_type,
+ output [3:0] io_in_3_grant_bits_data,
+ output io_in_4_acquire_ready,
+ input io_in_4_acquire_valid,
+ input [25:0] io_in_4_acquire_bits_addr_block,
+ input [3:0] io_in_4_acquire_bits_client_xact_id,
+ input [1:0] io_in_4_acquire_bits_addr_beat,
+ input io_in_4_acquire_bits_is_builtin_type,
+ input [2:0] io_in_4_acquire_bits_a_type,
+ input [16:0] io_in_4_acquire_bits_union,
+ input [3:0] io_in_4_acquire_bits_data,
+ input io_in_4_grant_ready,
+ output io_in_4_grant_valid,
+ output [1:0] io_in_4_grant_bits_addr_beat,
+ output [3:0] io_in_4_grant_bits_client_xact_id,
+ output io_in_4_grant_bits_manager_xact_id,
+ output io_in_4_grant_bits_is_builtin_type,
+ output [3:0] io_in_4_grant_bits_g_type,
+ output [3:0] io_in_4_grant_bits_data,
+ output io_in_5_acquire_ready,
+ input io_in_5_acquire_valid,
+ input [25:0] io_in_5_acquire_bits_addr_block,
+ input [3:0] io_in_5_acquire_bits_client_xact_id,
+ input [1:0] io_in_5_acquire_bits_addr_beat,
+ input io_in_5_acquire_bits_is_builtin_type,
+ input [2:0] io_in_5_acquire_bits_a_type,
+ input [16:0] io_in_5_acquire_bits_union,
+ input [3:0] io_in_5_acquire_bits_data,
+ input io_in_5_grant_ready,
+ output io_in_5_grant_valid,
+ output [1:0] io_in_5_grant_bits_addr_beat,
+ output [3:0] io_in_5_grant_bits_client_xact_id,
+ output io_in_5_grant_bits_manager_xact_id,
+ output io_in_5_grant_bits_is_builtin_type,
+ output [3:0] io_in_5_grant_bits_g_type,
+ output [3:0] io_in_5_grant_bits_data,
+ output io_in_6_acquire_ready,
+ input io_in_6_acquire_valid,
+ input [25:0] io_in_6_acquire_bits_addr_block,
+ input [3:0] io_in_6_acquire_bits_client_xact_id,
+ input [1:0] io_in_6_acquire_bits_addr_beat,
+ input io_in_6_acquire_bits_is_builtin_type,
+ input [2:0] io_in_6_acquire_bits_a_type,
+ input [16:0] io_in_6_acquire_bits_union,
+ input [3:0] io_in_6_acquire_bits_data,
+ input io_in_6_grant_ready,
+ output io_in_6_grant_valid,
+ output [1:0] io_in_6_grant_bits_addr_beat,
+ output [3:0] io_in_6_grant_bits_client_xact_id,
+ output io_in_6_grant_bits_manager_xact_id,
+ output io_in_6_grant_bits_is_builtin_type,
+ output [3:0] io_in_6_grant_bits_g_type,
+ output [3:0] io_in_6_grant_bits_data,
+ output io_in_7_acquire_ready,
+ input io_in_7_acquire_valid,
+ input [25:0] io_in_7_acquire_bits_addr_block,
+ input [3:0] io_in_7_acquire_bits_client_xact_id,
+ input [1:0] io_in_7_acquire_bits_addr_beat,
+ input io_in_7_acquire_bits_is_builtin_type,
+ input [2:0] io_in_7_acquire_bits_a_type,
+ input [16:0] io_in_7_acquire_bits_union,
+ input [3:0] io_in_7_acquire_bits_data,
+ input io_in_7_grant_ready,
+ output io_in_7_grant_valid,
+ output [1:0] io_in_7_grant_bits_addr_beat,
+ output [3:0] io_in_7_grant_bits_client_xact_id,
+ output io_in_7_grant_bits_manager_xact_id,
+ output io_in_7_grant_bits_is_builtin_type,
+ output [3:0] io_in_7_grant_bits_g_type,
+ output [3:0] io_in_7_grant_bits_data,
+ input io_out_acquire_ready,
+ output io_out_acquire_valid,
+ output [25:0] io_out_acquire_bits_addr_block,
+ output [3:0] io_out_acquire_bits_client_xact_id,
+ output [1:0] io_out_acquire_bits_addr_beat,
+ output io_out_acquire_bits_is_builtin_type,
+ output [2:0] io_out_acquire_bits_a_type,
+ output [16:0] io_out_acquire_bits_union,
+ output [3:0] io_out_acquire_bits_data,
+ output io_out_grant_ready,
+ input io_out_grant_valid,
+ input [1:0] io_out_grant_bits_addr_beat,
+ input [3:0] io_out_grant_bits_client_xact_id,
+ input io_out_grant_bits_manager_xact_id,
+ input io_out_grant_bits_is_builtin_type,
+ input [3:0] io_out_grant_bits_g_type,
+ input [3:0] io_out_grant_bits_data
+);
+ wire T_1593_clk;
+ wire T_1593_reset;
+ wire T_1593_io_in_0_ready;
+ wire T_1593_io_in_0_valid;
+ wire [25:0] T_1593_io_in_0_bits_addr_block;
+ wire [3:0] T_1593_io_in_0_bits_client_xact_id;
+ wire [1:0] T_1593_io_in_0_bits_addr_beat;
+ wire T_1593_io_in_0_bits_is_builtin_type;
+ wire [2:0] T_1593_io_in_0_bits_a_type;
+ wire [16:0] T_1593_io_in_0_bits_union;
+ wire [3:0] T_1593_io_in_0_bits_data;
+ wire T_1593_io_in_1_ready;
+ wire T_1593_io_in_1_valid;
+ wire [25:0] T_1593_io_in_1_bits_addr_block;
+ wire [3:0] T_1593_io_in_1_bits_client_xact_id;
+ wire [1:0] T_1593_io_in_1_bits_addr_beat;
+ wire T_1593_io_in_1_bits_is_builtin_type;
+ wire [2:0] T_1593_io_in_1_bits_a_type;
+ wire [16:0] T_1593_io_in_1_bits_union;
+ wire [3:0] T_1593_io_in_1_bits_data;
+ wire T_1593_io_in_2_ready;
+ wire T_1593_io_in_2_valid;
+ wire [25:0] T_1593_io_in_2_bits_addr_block;
+ wire [3:0] T_1593_io_in_2_bits_client_xact_id;
+ wire [1:0] T_1593_io_in_2_bits_addr_beat;
+ wire T_1593_io_in_2_bits_is_builtin_type;
+ wire [2:0] T_1593_io_in_2_bits_a_type;
+ wire [16:0] T_1593_io_in_2_bits_union;
+ wire [3:0] T_1593_io_in_2_bits_data;
+ wire T_1593_io_in_3_ready;
+ wire T_1593_io_in_3_valid;
+ wire [25:0] T_1593_io_in_3_bits_addr_block;
+ wire [3:0] T_1593_io_in_3_bits_client_xact_id;
+ wire [1:0] T_1593_io_in_3_bits_addr_beat;
+ wire T_1593_io_in_3_bits_is_builtin_type;
+ wire [2:0] T_1593_io_in_3_bits_a_type;
+ wire [16:0] T_1593_io_in_3_bits_union;
+ wire [3:0] T_1593_io_in_3_bits_data;
+ wire T_1593_io_in_4_ready;
+ wire T_1593_io_in_4_valid;
+ wire [25:0] T_1593_io_in_4_bits_addr_block;
+ wire [3:0] T_1593_io_in_4_bits_client_xact_id;
+ wire [1:0] T_1593_io_in_4_bits_addr_beat;
+ wire T_1593_io_in_4_bits_is_builtin_type;
+ wire [2:0] T_1593_io_in_4_bits_a_type;
+ wire [16:0] T_1593_io_in_4_bits_union;
+ wire [3:0] T_1593_io_in_4_bits_data;
+ wire T_1593_io_in_5_ready;
+ wire T_1593_io_in_5_valid;
+ wire [25:0] T_1593_io_in_5_bits_addr_block;
+ wire [3:0] T_1593_io_in_5_bits_client_xact_id;
+ wire [1:0] T_1593_io_in_5_bits_addr_beat;
+ wire T_1593_io_in_5_bits_is_builtin_type;
+ wire [2:0] T_1593_io_in_5_bits_a_type;
+ wire [16:0] T_1593_io_in_5_bits_union;
+ wire [3:0] T_1593_io_in_5_bits_data;
+ wire T_1593_io_in_6_ready;
+ wire T_1593_io_in_6_valid;
+ wire [25:0] T_1593_io_in_6_bits_addr_block;
+ wire [3:0] T_1593_io_in_6_bits_client_xact_id;
+ wire [1:0] T_1593_io_in_6_bits_addr_beat;
+ wire T_1593_io_in_6_bits_is_builtin_type;
+ wire [2:0] T_1593_io_in_6_bits_a_type;
+ wire [16:0] T_1593_io_in_6_bits_union;
+ wire [3:0] T_1593_io_in_6_bits_data;
+ wire T_1593_io_in_7_ready;
+ wire T_1593_io_in_7_valid;
+ wire [25:0] T_1593_io_in_7_bits_addr_block;
+ wire [3:0] T_1593_io_in_7_bits_client_xact_id;
+ wire [1:0] T_1593_io_in_7_bits_addr_beat;
+ wire T_1593_io_in_7_bits_is_builtin_type;
+ wire [2:0] T_1593_io_in_7_bits_a_type;
+ wire [16:0] T_1593_io_in_7_bits_union;
+ wire [3:0] T_1593_io_in_7_bits_data;
+ wire T_1593_io_out_ready;
+ wire T_1593_io_out_valid;
+ wire [25:0] T_1593_io_out_bits_addr_block;
+ wire [3:0] T_1593_io_out_bits_client_xact_id;
+ wire [1:0] T_1593_io_out_bits_addr_beat;
+ wire T_1593_io_out_bits_is_builtin_type;
+ wire [2:0] T_1593_io_out_bits_a_type;
+ wire [16:0] T_1593_io_out_bits_union;
+ wire [3:0] T_1593_io_out_bits_data;
+ wire [2:0] T_1593_io_chosen;
+ wire [6:0] T_1595;
+ wire [6:0] T_1597;
+ wire [6:0] T_1599;
+ wire [6:0] T_1601;
+ wire [6:0] T_1603;
+ wire [6:0] T_1605;
+ wire [6:0] T_1607;
+ wire [6:0] T_1609;
+ wire [2:0] T_1612;
+ wire T_1614;
+ wire T_1615;
+ wire [2:0] T_1617;
+ wire T_1619;
+ wire T_1620;
+ wire [2:0] T_1622;
+ wire T_1624;
+ wire T_1625;
+ wire [2:0] T_1627;
+ wire T_1629;
+ wire T_1630;
+ wire [2:0] T_1632;
+ wire T_1634;
+ wire T_1635;
+ wire [2:0] T_1637;
+ wire T_1639;
+ wire T_1640;
+ wire [2:0] T_1642;
+ wire T_1644;
+ wire T_1645;
+ wire [2:0] T_1647;
+ wire T_1649;
+ wire T_1650;
+ LockingRRArbiter_35 T_1593 (
+ .clk(T_1593_clk),
+ .reset(T_1593_reset),
+ .io_in_0_ready(T_1593_io_in_0_ready),
+ .io_in_0_valid(T_1593_io_in_0_valid),
+ .io_in_0_bits_addr_block(T_1593_io_in_0_bits_addr_block),
+ .io_in_0_bits_client_xact_id(T_1593_io_in_0_bits_client_xact_id),
+ .io_in_0_bits_addr_beat(T_1593_io_in_0_bits_addr_beat),
+ .io_in_0_bits_is_builtin_type(T_1593_io_in_0_bits_is_builtin_type),
+ .io_in_0_bits_a_type(T_1593_io_in_0_bits_a_type),
+ .io_in_0_bits_union(T_1593_io_in_0_bits_union),
+ .io_in_0_bits_data(T_1593_io_in_0_bits_data),
+ .io_in_1_ready(T_1593_io_in_1_ready),
+ .io_in_1_valid(T_1593_io_in_1_valid),
+ .io_in_1_bits_addr_block(T_1593_io_in_1_bits_addr_block),
+ .io_in_1_bits_client_xact_id(T_1593_io_in_1_bits_client_xact_id),
+ .io_in_1_bits_addr_beat(T_1593_io_in_1_bits_addr_beat),
+ .io_in_1_bits_is_builtin_type(T_1593_io_in_1_bits_is_builtin_type),
+ .io_in_1_bits_a_type(T_1593_io_in_1_bits_a_type),
+ .io_in_1_bits_union(T_1593_io_in_1_bits_union),
+ .io_in_1_bits_data(T_1593_io_in_1_bits_data),
+ .io_in_2_ready(T_1593_io_in_2_ready),
+ .io_in_2_valid(T_1593_io_in_2_valid),
+ .io_in_2_bits_addr_block(T_1593_io_in_2_bits_addr_block),
+ .io_in_2_bits_client_xact_id(T_1593_io_in_2_bits_client_xact_id),
+ .io_in_2_bits_addr_beat(T_1593_io_in_2_bits_addr_beat),
+ .io_in_2_bits_is_builtin_type(T_1593_io_in_2_bits_is_builtin_type),
+ .io_in_2_bits_a_type(T_1593_io_in_2_bits_a_type),
+ .io_in_2_bits_union(T_1593_io_in_2_bits_union),
+ .io_in_2_bits_data(T_1593_io_in_2_bits_data),
+ .io_in_3_ready(T_1593_io_in_3_ready),
+ .io_in_3_valid(T_1593_io_in_3_valid),
+ .io_in_3_bits_addr_block(T_1593_io_in_3_bits_addr_block),
+ .io_in_3_bits_client_xact_id(T_1593_io_in_3_bits_client_xact_id),
+ .io_in_3_bits_addr_beat(T_1593_io_in_3_bits_addr_beat),
+ .io_in_3_bits_is_builtin_type(T_1593_io_in_3_bits_is_builtin_type),
+ .io_in_3_bits_a_type(T_1593_io_in_3_bits_a_type),
+ .io_in_3_bits_union(T_1593_io_in_3_bits_union),
+ .io_in_3_bits_data(T_1593_io_in_3_bits_data),
+ .io_in_4_ready(T_1593_io_in_4_ready),
+ .io_in_4_valid(T_1593_io_in_4_valid),
+ .io_in_4_bits_addr_block(T_1593_io_in_4_bits_addr_block),
+ .io_in_4_bits_client_xact_id(T_1593_io_in_4_bits_client_xact_id),
+ .io_in_4_bits_addr_beat(T_1593_io_in_4_bits_addr_beat),
+ .io_in_4_bits_is_builtin_type(T_1593_io_in_4_bits_is_builtin_type),
+ .io_in_4_bits_a_type(T_1593_io_in_4_bits_a_type),
+ .io_in_4_bits_union(T_1593_io_in_4_bits_union),
+ .io_in_4_bits_data(T_1593_io_in_4_bits_data),
+ .io_in_5_ready(T_1593_io_in_5_ready),
+ .io_in_5_valid(T_1593_io_in_5_valid),
+ .io_in_5_bits_addr_block(T_1593_io_in_5_bits_addr_block),
+ .io_in_5_bits_client_xact_id(T_1593_io_in_5_bits_client_xact_id),
+ .io_in_5_bits_addr_beat(T_1593_io_in_5_bits_addr_beat),
+ .io_in_5_bits_is_builtin_type(T_1593_io_in_5_bits_is_builtin_type),
+ .io_in_5_bits_a_type(T_1593_io_in_5_bits_a_type),
+ .io_in_5_bits_union(T_1593_io_in_5_bits_union),
+ .io_in_5_bits_data(T_1593_io_in_5_bits_data),
+ .io_in_6_ready(T_1593_io_in_6_ready),
+ .io_in_6_valid(T_1593_io_in_6_valid),
+ .io_in_6_bits_addr_block(T_1593_io_in_6_bits_addr_block),
+ .io_in_6_bits_client_xact_id(T_1593_io_in_6_bits_client_xact_id),
+ .io_in_6_bits_addr_beat(T_1593_io_in_6_bits_addr_beat),
+ .io_in_6_bits_is_builtin_type(T_1593_io_in_6_bits_is_builtin_type),
+ .io_in_6_bits_a_type(T_1593_io_in_6_bits_a_type),
+ .io_in_6_bits_union(T_1593_io_in_6_bits_union),
+ .io_in_6_bits_data(T_1593_io_in_6_bits_data),
+ .io_in_7_ready(T_1593_io_in_7_ready),
+ .io_in_7_valid(T_1593_io_in_7_valid),
+ .io_in_7_bits_addr_block(T_1593_io_in_7_bits_addr_block),
+ .io_in_7_bits_client_xact_id(T_1593_io_in_7_bits_client_xact_id),
+ .io_in_7_bits_addr_beat(T_1593_io_in_7_bits_addr_beat),
+ .io_in_7_bits_is_builtin_type(T_1593_io_in_7_bits_is_builtin_type),
+ .io_in_7_bits_a_type(T_1593_io_in_7_bits_a_type),
+ .io_in_7_bits_union(T_1593_io_in_7_bits_union),
+ .io_in_7_bits_data(T_1593_io_in_7_bits_data),
+ .io_out_ready(T_1593_io_out_ready),
+ .io_out_valid(T_1593_io_out_valid),
+ .io_out_bits_addr_block(T_1593_io_out_bits_addr_block),
+ .io_out_bits_client_xact_id(T_1593_io_out_bits_client_xact_id),
+ .io_out_bits_addr_beat(T_1593_io_out_bits_addr_beat),
+ .io_out_bits_is_builtin_type(T_1593_io_out_bits_is_builtin_type),
+ .io_out_bits_a_type(T_1593_io_out_bits_a_type),
+ .io_out_bits_union(T_1593_io_out_bits_union),
+ .io_out_bits_data(T_1593_io_out_bits_data),
+ .io_chosen(T_1593_io_chosen)
+ );
+ assign io_in_0_acquire_ready = T_1593_io_in_0_ready;
+ assign io_in_0_grant_valid = T_1614 ? io_out_grant_valid : 1'h0;
+ assign io_in_0_grant_bits_addr_beat = io_out_grant_bits_addr_beat;
+ assign io_in_0_grant_bits_client_xact_id = T_1615;
+ assign io_in_0_grant_bits_manager_xact_id = io_out_grant_bits_manager_xact_id;
+ assign io_in_0_grant_bits_is_builtin_type = io_out_grant_bits_is_builtin_type;
+ assign io_in_0_grant_bits_g_type = io_out_grant_bits_g_type;
+ assign io_in_0_grant_bits_data = io_out_grant_bits_data;
+ assign io_in_1_acquire_ready = T_1593_io_in_1_ready;
+ assign io_in_1_grant_valid = T_1619 ? io_out_grant_valid : 1'h0;
+ assign io_in_1_grant_bits_addr_beat = io_out_grant_bits_addr_beat;
+ assign io_in_1_grant_bits_client_xact_id = T_1620;
+ assign io_in_1_grant_bits_manager_xact_id = io_out_grant_bits_manager_xact_id;
+ assign io_in_1_grant_bits_is_builtin_type = io_out_grant_bits_is_builtin_type;
+ assign io_in_1_grant_bits_g_type = io_out_grant_bits_g_type;
+ assign io_in_1_grant_bits_data = io_out_grant_bits_data;
+ assign io_in_2_acquire_ready = T_1593_io_in_2_ready;
+ assign io_in_2_grant_valid = T_1624 ? io_out_grant_valid : 1'h0;
+ assign io_in_2_grant_bits_addr_beat = io_out_grant_bits_addr_beat;
+ assign io_in_2_grant_bits_client_xact_id = T_1625;
+ assign io_in_2_grant_bits_manager_xact_id = io_out_grant_bits_manager_xact_id;
+ assign io_in_2_grant_bits_is_builtin_type = io_out_grant_bits_is_builtin_type;
+ assign io_in_2_grant_bits_g_type = io_out_grant_bits_g_type;
+ assign io_in_2_grant_bits_data = io_out_grant_bits_data;
+ assign io_in_3_acquire_ready = T_1593_io_in_3_ready;
+ assign io_in_3_grant_valid = T_1629 ? io_out_grant_valid : 1'h0;
+ assign io_in_3_grant_bits_addr_beat = io_out_grant_bits_addr_beat;
+ assign io_in_3_grant_bits_client_xact_id = T_1630;
+ assign io_in_3_grant_bits_manager_xact_id = io_out_grant_bits_manager_xact_id;
+ assign io_in_3_grant_bits_is_builtin_type = io_out_grant_bits_is_builtin_type;
+ assign io_in_3_grant_bits_g_type = io_out_grant_bits_g_type;
+ assign io_in_3_grant_bits_data = io_out_grant_bits_data;
+ assign io_in_4_acquire_ready = T_1593_io_in_4_ready;
+ assign io_in_4_grant_valid = T_1634 ? io_out_grant_valid : 1'h0;
+ assign io_in_4_grant_bits_addr_beat = io_out_grant_bits_addr_beat;
+ assign io_in_4_grant_bits_client_xact_id = T_1635;
+ assign io_in_4_grant_bits_manager_xact_id = io_out_grant_bits_manager_xact_id;
+ assign io_in_4_grant_bits_is_builtin_type = io_out_grant_bits_is_builtin_type;
+ assign io_in_4_grant_bits_g_type = io_out_grant_bits_g_type;
+ assign io_in_4_grant_bits_data = io_out_grant_bits_data;
+ assign io_in_5_acquire_ready = T_1593_io_in_5_ready;
+ assign io_in_5_grant_valid = T_1639 ? io_out_grant_valid : 1'h0;
+ assign io_in_5_grant_bits_addr_beat = io_out_grant_bits_addr_beat;
+ assign io_in_5_grant_bits_client_xact_id = T_1640;
+ assign io_in_5_grant_bits_manager_xact_id = io_out_grant_bits_manager_xact_id;
+ assign io_in_5_grant_bits_is_builtin_type = io_out_grant_bits_is_builtin_type;
+ assign io_in_5_grant_bits_g_type = io_out_grant_bits_g_type;
+ assign io_in_5_grant_bits_data = io_out_grant_bits_data;
+ assign io_in_6_acquire_ready = T_1593_io_in_6_ready;
+ assign io_in_6_grant_valid = T_1644 ? io_out_grant_valid : 1'h0;
+ assign io_in_6_grant_bits_addr_beat = io_out_grant_bits_addr_beat;
+ assign io_in_6_grant_bits_client_xact_id = T_1645;
+ assign io_in_6_grant_bits_manager_xact_id = io_out_grant_bits_manager_xact_id;
+ assign io_in_6_grant_bits_is_builtin_type = io_out_grant_bits_is_builtin_type;
+ assign io_in_6_grant_bits_g_type = io_out_grant_bits_g_type;
+ assign io_in_6_grant_bits_data = io_out_grant_bits_data;
+ assign io_in_7_acquire_ready = T_1593_io_in_7_ready;
+ assign io_in_7_grant_valid = T_1649 ? io_out_grant_valid : 1'h0;
+ assign io_in_7_grant_bits_addr_beat = io_out_grant_bits_addr_beat;
+ assign io_in_7_grant_bits_client_xact_id = T_1650;
+ assign io_in_7_grant_bits_manager_xact_id = io_out_grant_bits_manager_xact_id;
+ assign io_in_7_grant_bits_is_builtin_type = io_out_grant_bits_is_builtin_type;
+ assign io_in_7_grant_bits_g_type = io_out_grant_bits_g_type;
+ assign io_in_7_grant_bits_data = io_out_grant_bits_data;
+ assign io_out_acquire_valid = T_1593_io_out_valid;
+ assign io_out_acquire_bits_addr_block = T_1593_io_out_bits_addr_block;
+ assign io_out_acquire_bits_client_xact_id = T_1593_io_out_bits_client_xact_id;
+ assign io_out_acquire_bits_addr_beat = T_1593_io_out_bits_addr_beat;
+ assign io_out_acquire_bits_is_builtin_type = T_1593_io_out_bits_is_builtin_type;
+ assign io_out_acquire_bits_a_type = T_1593_io_out_bits_a_type;
+ assign io_out_acquire_bits_union = T_1593_io_out_bits_union;
+ assign io_out_acquire_bits_data = T_1593_io_out_bits_data;
+ assign io_out_grant_ready = T_1649 ? io_in_7_grant_ready : T_1644 ? io_in_6_grant_ready : T_1639 ? io_in_5_grant_ready : T_1634 ? io_in_4_grant_ready : T_1629 ? io_in_3_grant_ready : T_1624 ? io_in_2_grant_ready : T_1619 ? io_in_1_grant_ready : T_1614 ? io_in_0_grant_ready : 1'h0;
+ assign T_1593_clk = clk;
+ assign T_1593_reset = reset;
+ assign T_1593_io_in_0_valid = io_in_0_acquire_valid;
+ assign T_1593_io_in_0_bits_addr_block = io_in_0_acquire_bits_addr_block;
+ assign T_1593_io_in_0_bits_client_xact_id = T_1595;
+ assign T_1593_io_in_0_bits_addr_beat = io_in_0_acquire_bits_addr_beat;
+ assign T_1593_io_in_0_bits_is_builtin_type = io_in_0_acquire_bits_is_builtin_type;
+ assign T_1593_io_in_0_bits_a_type = io_in_0_acquire_bits_a_type;
+ assign T_1593_io_in_0_bits_union = io_in_0_acquire_bits_union;
+ assign T_1593_io_in_0_bits_data = io_in_0_acquire_bits_data;
+ assign T_1593_io_in_1_valid = io_in_1_acquire_valid;
+ assign T_1593_io_in_1_bits_addr_block = io_in_1_acquire_bits_addr_block;
+ assign T_1593_io_in_1_bits_client_xact_id = T_1597;
+ assign T_1593_io_in_1_bits_addr_beat = io_in_1_acquire_bits_addr_beat;
+ assign T_1593_io_in_1_bits_is_builtin_type = io_in_1_acquire_bits_is_builtin_type;
+ assign T_1593_io_in_1_bits_a_type = io_in_1_acquire_bits_a_type;
+ assign T_1593_io_in_1_bits_union = io_in_1_acquire_bits_union;
+ assign T_1593_io_in_1_bits_data = io_in_1_acquire_bits_data;
+ assign T_1593_io_in_2_valid = io_in_2_acquire_valid;
+ assign T_1593_io_in_2_bits_addr_block = io_in_2_acquire_bits_addr_block;
+ assign T_1593_io_in_2_bits_client_xact_id = T_1599;
+ assign T_1593_io_in_2_bits_addr_beat = io_in_2_acquire_bits_addr_beat;
+ assign T_1593_io_in_2_bits_is_builtin_type = io_in_2_acquire_bits_is_builtin_type;
+ assign T_1593_io_in_2_bits_a_type = io_in_2_acquire_bits_a_type;
+ assign T_1593_io_in_2_bits_union = io_in_2_acquire_bits_union;
+ assign T_1593_io_in_2_bits_data = io_in_2_acquire_bits_data;
+ assign T_1593_io_in_3_valid = io_in_3_acquire_valid;
+ assign T_1593_io_in_3_bits_addr_block = io_in_3_acquire_bits_addr_block;
+ assign T_1593_io_in_3_bits_client_xact_id = T_1601;
+ assign T_1593_io_in_3_bits_addr_beat = io_in_3_acquire_bits_addr_beat;
+ assign T_1593_io_in_3_bits_is_builtin_type = io_in_3_acquire_bits_is_builtin_type;
+ assign T_1593_io_in_3_bits_a_type = io_in_3_acquire_bits_a_type;
+ assign T_1593_io_in_3_bits_union = io_in_3_acquire_bits_union;
+ assign T_1593_io_in_3_bits_data = io_in_3_acquire_bits_data;
+ assign T_1593_io_in_4_valid = io_in_4_acquire_valid;
+ assign T_1593_io_in_4_bits_addr_block = io_in_4_acquire_bits_addr_block;
+ assign T_1593_io_in_4_bits_client_xact_id = T_1603;
+ assign T_1593_io_in_4_bits_addr_beat = io_in_4_acquire_bits_addr_beat;
+ assign T_1593_io_in_4_bits_is_builtin_type = io_in_4_acquire_bits_is_builtin_type;
+ assign T_1593_io_in_4_bits_a_type = io_in_4_acquire_bits_a_type;
+ assign T_1593_io_in_4_bits_union = io_in_4_acquire_bits_union;
+ assign T_1593_io_in_4_bits_data = io_in_4_acquire_bits_data;
+ assign T_1593_io_in_5_valid = io_in_5_acquire_valid;
+ assign T_1593_io_in_5_bits_addr_block = io_in_5_acquire_bits_addr_block;
+ assign T_1593_io_in_5_bits_client_xact_id = T_1605;
+ assign T_1593_io_in_5_bits_addr_beat = io_in_5_acquire_bits_addr_beat;
+ assign T_1593_io_in_5_bits_is_builtin_type = io_in_5_acquire_bits_is_builtin_type;
+ assign T_1593_io_in_5_bits_a_type = io_in_5_acquire_bits_a_type;
+ assign T_1593_io_in_5_bits_union = io_in_5_acquire_bits_union;
+ assign T_1593_io_in_5_bits_data = io_in_5_acquire_bits_data;
+ assign T_1593_io_in_6_valid = io_in_6_acquire_valid;
+ assign T_1593_io_in_6_bits_addr_block = io_in_6_acquire_bits_addr_block;
+ assign T_1593_io_in_6_bits_client_xact_id = T_1607;
+ assign T_1593_io_in_6_bits_addr_beat = io_in_6_acquire_bits_addr_beat;
+ assign T_1593_io_in_6_bits_is_builtin_type = io_in_6_acquire_bits_is_builtin_type;
+ assign T_1593_io_in_6_bits_a_type = io_in_6_acquire_bits_a_type;
+ assign T_1593_io_in_6_bits_union = io_in_6_acquire_bits_union;
+ assign T_1593_io_in_6_bits_data = io_in_6_acquire_bits_data;
+ assign T_1593_io_in_7_valid = io_in_7_acquire_valid;
+ assign T_1593_io_in_7_bits_addr_block = io_in_7_acquire_bits_addr_block;
+ assign T_1593_io_in_7_bits_client_xact_id = T_1609;
+ assign T_1593_io_in_7_bits_addr_beat = io_in_7_acquire_bits_addr_beat;
+ assign T_1593_io_in_7_bits_is_builtin_type = io_in_7_acquire_bits_is_builtin_type;
+ assign T_1593_io_in_7_bits_a_type = io_in_7_acquire_bits_a_type;
+ assign T_1593_io_in_7_bits_union = io_in_7_acquire_bits_union;
+ assign T_1593_io_in_7_bits_data = io_in_7_acquire_bits_data;
+ assign T_1593_io_out_ready = io_out_acquire_ready;
+ assign T_1595 = {io_in_0_acquire_bits_client_xact_id,3'h0};
+ assign T_1597 = {io_in_1_acquire_bits_client_xact_id,3'h1};
+ assign T_1599 = {io_in_2_acquire_bits_client_xact_id,3'h2};
+ assign T_1601 = {io_in_3_acquire_bits_client_xact_id,3'h3};
+ assign T_1603 = {io_in_4_acquire_bits_client_xact_id,3'h4};
+ assign T_1605 = {io_in_5_acquire_bits_client_xact_id,3'h5};
+ assign T_1607 = {io_in_6_acquire_bits_client_xact_id,3'h6};
+ assign T_1609 = {io_in_7_acquire_bits_client_xact_id,3'h7};
+ assign T_1612 = io_out_grant_bits_client_xact_id[2:0];
+ assign T_1614 = T_1612 == 1'h0;
+ assign T_1615 = io_out_grant_bits_client_xact_id[3:3];
+ assign T_1617 = io_out_grant_bits_client_xact_id[2:0];
+ assign T_1619 = T_1617 == 1'h1;
+ assign T_1620 = io_out_grant_bits_client_xact_id[3:3];
+ assign T_1622 = io_out_grant_bits_client_xact_id[2:0];
+ assign T_1624 = T_1622 == 2'h2;
+ assign T_1625 = io_out_grant_bits_client_xact_id[3:3];
+ assign T_1627 = io_out_grant_bits_client_xact_id[2:0];
+ assign T_1629 = T_1627 == 2'h3;
+ assign T_1630 = io_out_grant_bits_client_xact_id[3:3];
+ assign T_1632 = io_out_grant_bits_client_xact_id[2:0];
+ assign T_1634 = T_1632 == 3'h4;
+ assign T_1635 = io_out_grant_bits_client_xact_id[3:3];
+ assign T_1637 = io_out_grant_bits_client_xact_id[2:0];
+ assign T_1639 = T_1637 == 3'h5;
+ assign T_1640 = io_out_grant_bits_client_xact_id[3:3];
+ assign T_1642 = io_out_grant_bits_client_xact_id[2:0];
+ assign T_1644 = T_1642 == 3'h6;
+ assign T_1645 = io_out_grant_bits_client_xact_id[3:3];
+ assign T_1647 = io_out_grant_bits_client_xact_id[2:0];
+ assign T_1649 = T_1647 == 3'h7;
+ assign T_1650 = io_out_grant_bits_client_xact_id[3:3];
+endmodule
+module L2BroadcastHub(
+ input clk,
+ input reset,
+ output io_inner_acquire_ready,
+ input io_inner_acquire_valid,
+ input [25:0] io_inner_acquire_bits_addr_block,
+ input [1:0] io_inner_acquire_bits_client_xact_id,
+ input [1:0] io_inner_acquire_bits_addr_beat,
+ input io_inner_acquire_bits_is_builtin_type,
+ input [2:0] io_inner_acquire_bits_a_type,
+ input [16:0] io_inner_acquire_bits_union,
+ input [127:0] io_inner_acquire_bits_data,
+ input [1:0] io_inner_acquire_bits_client_id,
+ input io_inner_grant_ready,
+ output io_inner_grant_valid,
+ output [1:0] io_inner_grant_bits_addr_beat,
+ output [1:0] io_inner_grant_bits_client_xact_id,
+ output [3:0] io_inner_grant_bits_manager_xact_id,
+ output io_inner_grant_bits_is_builtin_type,
+ output [3:0] io_inner_grant_bits_g_type,
+ output [127:0] io_inner_grant_bits_data,
+ output [1:0] io_inner_grant_bits_client_id,
+ output io_inner_finish_ready,
+ input io_inner_finish_valid,
+ input [3:0] io_inner_finish_bits_manager_xact_id,
+ input io_inner_probe_ready,
+ output io_inner_probe_valid,
+ output [25:0] io_inner_probe_bits_addr_block,
+ output [1:0] io_inner_probe_bits_p_type,
+ output [1:0] io_inner_probe_bits_client_id,
+ output io_inner_release_ready,
+ input io_inner_release_valid,
+ input [1:0] io_inner_release_bits_addr_beat,
+ input [25:0] io_inner_release_bits_addr_block,
+ input [1:0] io_inner_release_bits_client_xact_id,
+ input io_inner_release_bits_voluntary,
+ input [2:0] io_inner_release_bits_r_type,
+ input [127:0] io_inner_release_bits_data,
+ input [1:0] io_inner_release_bits_client_id,
+ input io_incoherent_0,
+ input io_outer_acquire_ready,
+ output io_outer_acquire_valid,
+ output [25:0] io_outer_acquire_bits_addr_block,
+ output [3:0] io_outer_acquire_bits_client_xact_id,
+ output [1:0] io_outer_acquire_bits_addr_beat,
+ output io_outer_acquire_bits_is_builtin_type,
+ output [2:0] io_outer_acquire_bits_a_type,
+ output [16:0] io_outer_acquire_bits_union,
+ output [127:0] io_outer_acquire_bits_data,
+ output io_outer_grant_ready,
+ input io_outer_grant_valid,
+ input [1:0] io_outer_grant_bits_addr_beat,
+ input [3:0] io_outer_grant_bits_client_xact_id,
+ input io_outer_grant_bits_manager_xact_id,
+ input io_outer_grant_bits_is_builtin_type,
+ input [3:0] io_outer_grant_bits_g_type,
+ input [127:0] io_outer_grant_bits_data
+);
+ wire T_1060_clk;
+ wire T_1060_reset;
+ wire T_1060_io_inner_acquire_ready;
+ wire T_1060_io_inner_acquire_valid;
+ wire [25:0] T_1060_io_inner_acquire_bits_addr_block;
+ wire [1:0] T_1060_io_inner_acquire_bits_client_xact_id;
+ wire [1:0] T_1060_io_inner_acquire_bits_addr_beat;
+ wire T_1060_io_inner_acquire_bits_is_builtin_type;
+ wire [2:0] T_1060_io_inner_acquire_bits_a_type;
+ wire [16:0] T_1060_io_inner_acquire_bits_union;
+ wire [3:0] T_1060_io_inner_acquire_bits_data;
+ wire [1:0] T_1060_io_inner_acquire_bits_client_id;
+ wire T_1060_io_inner_grant_ready;
+ wire T_1060_io_inner_grant_valid;
+ wire [1:0] T_1060_io_inner_grant_bits_addr_beat;
+ wire [1:0] T_1060_io_inner_grant_bits_client_xact_id;
+ wire [3:0] T_1060_io_inner_grant_bits_manager_xact_id;
+ wire T_1060_io_inner_grant_bits_is_builtin_type;
+ wire [3:0] T_1060_io_inner_grant_bits_g_type;
+ wire [3:0] T_1060_io_inner_grant_bits_data;
+ wire [1:0] T_1060_io_inner_grant_bits_client_id;
+ wire T_1060_io_inner_finish_ready;
+ wire T_1060_io_inner_finish_valid;
+ wire [3:0] T_1060_io_inner_finish_bits_manager_xact_id;
+ wire T_1060_io_inner_probe_ready;
+ wire T_1060_io_inner_probe_valid;
+ wire [25:0] T_1060_io_inner_probe_bits_addr_block;
+ wire [1:0] T_1060_io_inner_probe_bits_p_type;
+ wire [1:0] T_1060_io_inner_probe_bits_client_id;
+ wire T_1060_io_inner_release_ready;
+ wire T_1060_io_inner_release_valid;
+ wire [1:0] T_1060_io_inner_release_bits_addr_beat;
+ wire [25:0] T_1060_io_inner_release_bits_addr_block;
+ wire [1:0] T_1060_io_inner_release_bits_client_xact_id;
+ wire T_1060_io_inner_release_bits_voluntary;
+ wire [2:0] T_1060_io_inner_release_bits_r_type;
+ wire [3:0] T_1060_io_inner_release_bits_data;
+ wire [1:0] T_1060_io_inner_release_bits_client_id;
+ wire T_1060_io_incoherent_0;
+ wire T_1060_io_outer_acquire_ready;
+ wire T_1060_io_outer_acquire_valid;
+ wire [25:0] T_1060_io_outer_acquire_bits_addr_block;
+ wire [3:0] T_1060_io_outer_acquire_bits_client_xact_id;
+ wire [1:0] T_1060_io_outer_acquire_bits_addr_beat;
+ wire T_1060_io_outer_acquire_bits_is_builtin_type;
+ wire [2:0] T_1060_io_outer_acquire_bits_a_type;
+ wire [16:0] T_1060_io_outer_acquire_bits_union;
+ wire [3:0] T_1060_io_outer_acquire_bits_data;
+ wire T_1060_io_outer_grant_ready;
+ wire T_1060_io_outer_grant_valid;
+ wire [1:0] T_1060_io_outer_grant_bits_addr_beat;
+ wire [3:0] T_1060_io_outer_grant_bits_client_xact_id;
+ wire T_1060_io_outer_grant_bits_manager_xact_id;
+ wire T_1060_io_outer_grant_bits_is_builtin_type;
+ wire [3:0] T_1060_io_outer_grant_bits_g_type;
+ wire [3:0] T_1060_io_outer_grant_bits_data;
+ wire T_1060_io_has_acquire_conflict;
+ wire T_1060_io_has_acquire_match;
+ wire T_1060_io_has_release_match;
+ wire T_1061_clk;
+ wire T_1061_reset;
+ wire T_1061_io_inner_acquire_ready;
+ wire T_1061_io_inner_acquire_valid;
+ wire [25:0] T_1061_io_inner_acquire_bits_addr_block;
+ wire [1:0] T_1061_io_inner_acquire_bits_client_xact_id;
+ wire [1:0] T_1061_io_inner_acquire_bits_addr_beat;
+ wire T_1061_io_inner_acquire_bits_is_builtin_type;
+ wire [2:0] T_1061_io_inner_acquire_bits_a_type;
+ wire [16:0] T_1061_io_inner_acquire_bits_union;
+ wire [3:0] T_1061_io_inner_acquire_bits_data;
+ wire [1:0] T_1061_io_inner_acquire_bits_client_id;
+ wire T_1061_io_inner_grant_ready;
+ wire T_1061_io_inner_grant_valid;
+ wire [1:0] T_1061_io_inner_grant_bits_addr_beat;
+ wire [1:0] T_1061_io_inner_grant_bits_client_xact_id;
+ wire [3:0] T_1061_io_inner_grant_bits_manager_xact_id;
+ wire T_1061_io_inner_grant_bits_is_builtin_type;
+ wire [3:0] T_1061_io_inner_grant_bits_g_type;
+ wire [3:0] T_1061_io_inner_grant_bits_data;
+ wire [1:0] T_1061_io_inner_grant_bits_client_id;
+ wire T_1061_io_inner_finish_ready;
+ wire T_1061_io_inner_finish_valid;
+ wire [3:0] T_1061_io_inner_finish_bits_manager_xact_id;
+ wire T_1061_io_inner_probe_ready;
+ wire T_1061_io_inner_probe_valid;
+ wire [25:0] T_1061_io_inner_probe_bits_addr_block;
+ wire [1:0] T_1061_io_inner_probe_bits_p_type;
+ wire [1:0] T_1061_io_inner_probe_bits_client_id;
+ wire T_1061_io_inner_release_ready;
+ wire T_1061_io_inner_release_valid;
+ wire [1:0] T_1061_io_inner_release_bits_addr_beat;
+ wire [25:0] T_1061_io_inner_release_bits_addr_block;
+ wire [1:0] T_1061_io_inner_release_bits_client_xact_id;
+ wire T_1061_io_inner_release_bits_voluntary;
+ wire [2:0] T_1061_io_inner_release_bits_r_type;
+ wire [3:0] T_1061_io_inner_release_bits_data;
+ wire [1:0] T_1061_io_inner_release_bits_client_id;
+ wire T_1061_io_incoherent_0;
+ wire T_1061_io_outer_acquire_ready;
+ wire T_1061_io_outer_acquire_valid;
+ wire [25:0] T_1061_io_outer_acquire_bits_addr_block;
+ wire [3:0] T_1061_io_outer_acquire_bits_client_xact_id;
+ wire [1:0] T_1061_io_outer_acquire_bits_addr_beat;
+ wire T_1061_io_outer_acquire_bits_is_builtin_type;
+ wire [2:0] T_1061_io_outer_acquire_bits_a_type;
+ wire [16:0] T_1061_io_outer_acquire_bits_union;
+ wire [3:0] T_1061_io_outer_acquire_bits_data;
+ wire T_1061_io_outer_grant_ready;
+ wire T_1061_io_outer_grant_valid;
+ wire [1:0] T_1061_io_outer_grant_bits_addr_beat;
+ wire [3:0] T_1061_io_outer_grant_bits_client_xact_id;
+ wire T_1061_io_outer_grant_bits_manager_xact_id;
+ wire T_1061_io_outer_grant_bits_is_builtin_type;
+ wire [3:0] T_1061_io_outer_grant_bits_g_type;
+ wire [3:0] T_1061_io_outer_grant_bits_data;
+ wire T_1061_io_has_acquire_conflict;
+ wire T_1061_io_has_acquire_match;
+ wire T_1061_io_has_release_match;
+ wire T_1062_clk;
+ wire T_1062_reset;
+ wire T_1062_io_inner_acquire_ready;
+ wire T_1062_io_inner_acquire_valid;
+ wire [25:0] T_1062_io_inner_acquire_bits_addr_block;
+ wire [1:0] T_1062_io_inner_acquire_bits_client_xact_id;
+ wire [1:0] T_1062_io_inner_acquire_bits_addr_beat;
+ wire T_1062_io_inner_acquire_bits_is_builtin_type;
+ wire [2:0] T_1062_io_inner_acquire_bits_a_type;
+ wire [16:0] T_1062_io_inner_acquire_bits_union;
+ wire [3:0] T_1062_io_inner_acquire_bits_data;
+ wire [1:0] T_1062_io_inner_acquire_bits_client_id;
+ wire T_1062_io_inner_grant_ready;
+ wire T_1062_io_inner_grant_valid;
+ wire [1:0] T_1062_io_inner_grant_bits_addr_beat;
+ wire [1:0] T_1062_io_inner_grant_bits_client_xact_id;
+ wire [3:0] T_1062_io_inner_grant_bits_manager_xact_id;
+ wire T_1062_io_inner_grant_bits_is_builtin_type;
+ wire [3:0] T_1062_io_inner_grant_bits_g_type;
+ wire [3:0] T_1062_io_inner_grant_bits_data;
+ wire [1:0] T_1062_io_inner_grant_bits_client_id;
+ wire T_1062_io_inner_finish_ready;
+ wire T_1062_io_inner_finish_valid;
+ wire [3:0] T_1062_io_inner_finish_bits_manager_xact_id;
+ wire T_1062_io_inner_probe_ready;
+ wire T_1062_io_inner_probe_valid;
+ wire [25:0] T_1062_io_inner_probe_bits_addr_block;
+ wire [1:0] T_1062_io_inner_probe_bits_p_type;
+ wire [1:0] T_1062_io_inner_probe_bits_client_id;
+ wire T_1062_io_inner_release_ready;
+ wire T_1062_io_inner_release_valid;
+ wire [1:0] T_1062_io_inner_release_bits_addr_beat;
+ wire [25:0] T_1062_io_inner_release_bits_addr_block;
+ wire [1:0] T_1062_io_inner_release_bits_client_xact_id;
+ wire T_1062_io_inner_release_bits_voluntary;
+ wire [2:0] T_1062_io_inner_release_bits_r_type;
+ wire [3:0] T_1062_io_inner_release_bits_data;
+ wire [1:0] T_1062_io_inner_release_bits_client_id;
+ wire T_1062_io_incoherent_0;
+ wire T_1062_io_outer_acquire_ready;
+ wire T_1062_io_outer_acquire_valid;
+ wire [25:0] T_1062_io_outer_acquire_bits_addr_block;
+ wire [3:0] T_1062_io_outer_acquire_bits_client_xact_id;
+ wire [1:0] T_1062_io_outer_acquire_bits_addr_beat;
+ wire T_1062_io_outer_acquire_bits_is_builtin_type;
+ wire [2:0] T_1062_io_outer_acquire_bits_a_type;
+ wire [16:0] T_1062_io_outer_acquire_bits_union;
+ wire [3:0] T_1062_io_outer_acquire_bits_data;
+ wire T_1062_io_outer_grant_ready;
+ wire T_1062_io_outer_grant_valid;
+ wire [1:0] T_1062_io_outer_grant_bits_addr_beat;
+ wire [3:0] T_1062_io_outer_grant_bits_client_xact_id;
+ wire T_1062_io_outer_grant_bits_manager_xact_id;
+ wire T_1062_io_outer_grant_bits_is_builtin_type;
+ wire [3:0] T_1062_io_outer_grant_bits_g_type;
+ wire [3:0] T_1062_io_outer_grant_bits_data;
+ wire T_1062_io_has_acquire_conflict;
+ wire T_1062_io_has_acquire_match;
+ wire T_1062_io_has_release_match;
+ wire T_1063_clk;
+ wire T_1063_reset;
+ wire T_1063_io_inner_acquire_ready;
+ wire T_1063_io_inner_acquire_valid;
+ wire [25:0] T_1063_io_inner_acquire_bits_addr_block;
+ wire [1:0] T_1063_io_inner_acquire_bits_client_xact_id;
+ wire [1:0] T_1063_io_inner_acquire_bits_addr_beat;
+ wire T_1063_io_inner_acquire_bits_is_builtin_type;
+ wire [2:0] T_1063_io_inner_acquire_bits_a_type;
+ wire [16:0] T_1063_io_inner_acquire_bits_union;
+ wire [3:0] T_1063_io_inner_acquire_bits_data;
+ wire [1:0] T_1063_io_inner_acquire_bits_client_id;
+ wire T_1063_io_inner_grant_ready;
+ wire T_1063_io_inner_grant_valid;
+ wire [1:0] T_1063_io_inner_grant_bits_addr_beat;
+ wire [1:0] T_1063_io_inner_grant_bits_client_xact_id;
+ wire [3:0] T_1063_io_inner_grant_bits_manager_xact_id;
+ wire T_1063_io_inner_grant_bits_is_builtin_type;
+ wire [3:0] T_1063_io_inner_grant_bits_g_type;
+ wire [3:0] T_1063_io_inner_grant_bits_data;
+ wire [1:0] T_1063_io_inner_grant_bits_client_id;
+ wire T_1063_io_inner_finish_ready;
+ wire T_1063_io_inner_finish_valid;
+ wire [3:0] T_1063_io_inner_finish_bits_manager_xact_id;
+ wire T_1063_io_inner_probe_ready;
+ wire T_1063_io_inner_probe_valid;
+ wire [25:0] T_1063_io_inner_probe_bits_addr_block;
+ wire [1:0] T_1063_io_inner_probe_bits_p_type;
+ wire [1:0] T_1063_io_inner_probe_bits_client_id;
+ wire T_1063_io_inner_release_ready;
+ wire T_1063_io_inner_release_valid;
+ wire [1:0] T_1063_io_inner_release_bits_addr_beat;
+ wire [25:0] T_1063_io_inner_release_bits_addr_block;
+ wire [1:0] T_1063_io_inner_release_bits_client_xact_id;
+ wire T_1063_io_inner_release_bits_voluntary;
+ wire [2:0] T_1063_io_inner_release_bits_r_type;
+ wire [3:0] T_1063_io_inner_release_bits_data;
+ wire [1:0] T_1063_io_inner_release_bits_client_id;
+ wire T_1063_io_incoherent_0;
+ wire T_1063_io_outer_acquire_ready;
+ wire T_1063_io_outer_acquire_valid;
+ wire [25:0] T_1063_io_outer_acquire_bits_addr_block;
+ wire [3:0] T_1063_io_outer_acquire_bits_client_xact_id;
+ wire [1:0] T_1063_io_outer_acquire_bits_addr_beat;
+ wire T_1063_io_outer_acquire_bits_is_builtin_type;
+ wire [2:0] T_1063_io_outer_acquire_bits_a_type;
+ wire [16:0] T_1063_io_outer_acquire_bits_union;
+ wire [3:0] T_1063_io_outer_acquire_bits_data;
+ wire T_1063_io_outer_grant_ready;
+ wire T_1063_io_outer_grant_valid;
+ wire [1:0] T_1063_io_outer_grant_bits_addr_beat;
+ wire [3:0] T_1063_io_outer_grant_bits_client_xact_id;
+ wire T_1063_io_outer_grant_bits_manager_xact_id;
+ wire T_1063_io_outer_grant_bits_is_builtin_type;
+ wire [3:0] T_1063_io_outer_grant_bits_g_type;
+ wire [3:0] T_1063_io_outer_grant_bits_data;
+ wire T_1063_io_has_acquire_conflict;
+ wire T_1063_io_has_acquire_match;
+ wire T_1063_io_has_release_match;
+ wire T_1064_clk;
+ wire T_1064_reset;
+ wire T_1064_io_inner_acquire_ready;
+ wire T_1064_io_inner_acquire_valid;
+ wire [25:0] T_1064_io_inner_acquire_bits_addr_block;
+ wire [1:0] T_1064_io_inner_acquire_bits_client_xact_id;
+ wire [1:0] T_1064_io_inner_acquire_bits_addr_beat;
+ wire T_1064_io_inner_acquire_bits_is_builtin_type;
+ wire [2:0] T_1064_io_inner_acquire_bits_a_type;
+ wire [16:0] T_1064_io_inner_acquire_bits_union;
+ wire [3:0] T_1064_io_inner_acquire_bits_data;
+ wire [1:0] T_1064_io_inner_acquire_bits_client_id;
+ wire T_1064_io_inner_grant_ready;
+ wire T_1064_io_inner_grant_valid;
+ wire [1:0] T_1064_io_inner_grant_bits_addr_beat;
+ wire [1:0] T_1064_io_inner_grant_bits_client_xact_id;
+ wire [3:0] T_1064_io_inner_grant_bits_manager_xact_id;
+ wire T_1064_io_inner_grant_bits_is_builtin_type;
+ wire [3:0] T_1064_io_inner_grant_bits_g_type;
+ wire [3:0] T_1064_io_inner_grant_bits_data;
+ wire [1:0] T_1064_io_inner_grant_bits_client_id;
+ wire T_1064_io_inner_finish_ready;
+ wire T_1064_io_inner_finish_valid;
+ wire [3:0] T_1064_io_inner_finish_bits_manager_xact_id;
+ wire T_1064_io_inner_probe_ready;
+ wire T_1064_io_inner_probe_valid;
+ wire [25:0] T_1064_io_inner_probe_bits_addr_block;
+ wire [1:0] T_1064_io_inner_probe_bits_p_type;
+ wire [1:0] T_1064_io_inner_probe_bits_client_id;
+ wire T_1064_io_inner_release_ready;
+ wire T_1064_io_inner_release_valid;
+ wire [1:0] T_1064_io_inner_release_bits_addr_beat;
+ wire [25:0] T_1064_io_inner_release_bits_addr_block;
+ wire [1:0] T_1064_io_inner_release_bits_client_xact_id;
+ wire T_1064_io_inner_release_bits_voluntary;
+ wire [2:0] T_1064_io_inner_release_bits_r_type;
+ wire [3:0] T_1064_io_inner_release_bits_data;
+ wire [1:0] T_1064_io_inner_release_bits_client_id;
+ wire T_1064_io_incoherent_0;
+ wire T_1064_io_outer_acquire_ready;
+ wire T_1064_io_outer_acquire_valid;
+ wire [25:0] T_1064_io_outer_acquire_bits_addr_block;
+ wire [3:0] T_1064_io_outer_acquire_bits_client_xact_id;
+ wire [1:0] T_1064_io_outer_acquire_bits_addr_beat;
+ wire T_1064_io_outer_acquire_bits_is_builtin_type;
+ wire [2:0] T_1064_io_outer_acquire_bits_a_type;
+ wire [16:0] T_1064_io_outer_acquire_bits_union;
+ wire [3:0] T_1064_io_outer_acquire_bits_data;
+ wire T_1064_io_outer_grant_ready;
+ wire T_1064_io_outer_grant_valid;
+ wire [1:0] T_1064_io_outer_grant_bits_addr_beat;
+ wire [3:0] T_1064_io_outer_grant_bits_client_xact_id;
+ wire T_1064_io_outer_grant_bits_manager_xact_id;
+ wire T_1064_io_outer_grant_bits_is_builtin_type;
+ wire [3:0] T_1064_io_outer_grant_bits_g_type;
+ wire [3:0] T_1064_io_outer_grant_bits_data;
+ wire T_1064_io_has_acquire_conflict;
+ wire T_1064_io_has_acquire_match;
+ wire T_1064_io_has_release_match;
+ wire T_1065_clk;
+ wire T_1065_reset;
+ wire T_1065_io_inner_acquire_ready;
+ wire T_1065_io_inner_acquire_valid;
+ wire [25:0] T_1065_io_inner_acquire_bits_addr_block;
+ wire [1:0] T_1065_io_inner_acquire_bits_client_xact_id;
+ wire [1:0] T_1065_io_inner_acquire_bits_addr_beat;
+ wire T_1065_io_inner_acquire_bits_is_builtin_type;
+ wire [2:0] T_1065_io_inner_acquire_bits_a_type;
+ wire [16:0] T_1065_io_inner_acquire_bits_union;
+ wire [3:0] T_1065_io_inner_acquire_bits_data;
+ wire [1:0] T_1065_io_inner_acquire_bits_client_id;
+ wire T_1065_io_inner_grant_ready;
+ wire T_1065_io_inner_grant_valid;
+ wire [1:0] T_1065_io_inner_grant_bits_addr_beat;
+ wire [1:0] T_1065_io_inner_grant_bits_client_xact_id;
+ wire [3:0] T_1065_io_inner_grant_bits_manager_xact_id;
+ wire T_1065_io_inner_grant_bits_is_builtin_type;
+ wire [3:0] T_1065_io_inner_grant_bits_g_type;
+ wire [3:0] T_1065_io_inner_grant_bits_data;
+ wire [1:0] T_1065_io_inner_grant_bits_client_id;
+ wire T_1065_io_inner_finish_ready;
+ wire T_1065_io_inner_finish_valid;
+ wire [3:0] T_1065_io_inner_finish_bits_manager_xact_id;
+ wire T_1065_io_inner_probe_ready;
+ wire T_1065_io_inner_probe_valid;
+ wire [25:0] T_1065_io_inner_probe_bits_addr_block;
+ wire [1:0] T_1065_io_inner_probe_bits_p_type;
+ wire [1:0] T_1065_io_inner_probe_bits_client_id;
+ wire T_1065_io_inner_release_ready;
+ wire T_1065_io_inner_release_valid;
+ wire [1:0] T_1065_io_inner_release_bits_addr_beat;
+ wire [25:0] T_1065_io_inner_release_bits_addr_block;
+ wire [1:0] T_1065_io_inner_release_bits_client_xact_id;
+ wire T_1065_io_inner_release_bits_voluntary;
+ wire [2:0] T_1065_io_inner_release_bits_r_type;
+ wire [3:0] T_1065_io_inner_release_bits_data;
+ wire [1:0] T_1065_io_inner_release_bits_client_id;
+ wire T_1065_io_incoherent_0;
+ wire T_1065_io_outer_acquire_ready;
+ wire T_1065_io_outer_acquire_valid;
+ wire [25:0] T_1065_io_outer_acquire_bits_addr_block;
+ wire [3:0] T_1065_io_outer_acquire_bits_client_xact_id;
+ wire [1:0] T_1065_io_outer_acquire_bits_addr_beat;
+ wire T_1065_io_outer_acquire_bits_is_builtin_type;
+ wire [2:0] T_1065_io_outer_acquire_bits_a_type;
+ wire [16:0] T_1065_io_outer_acquire_bits_union;
+ wire [3:0] T_1065_io_outer_acquire_bits_data;
+ wire T_1065_io_outer_grant_ready;
+ wire T_1065_io_outer_grant_valid;
+ wire [1:0] T_1065_io_outer_grant_bits_addr_beat;
+ wire [3:0] T_1065_io_outer_grant_bits_client_xact_id;
+ wire T_1065_io_outer_grant_bits_manager_xact_id;
+ wire T_1065_io_outer_grant_bits_is_builtin_type;
+ wire [3:0] T_1065_io_outer_grant_bits_g_type;
+ wire [3:0] T_1065_io_outer_grant_bits_data;
+ wire T_1065_io_has_acquire_conflict;
+ wire T_1065_io_has_acquire_match;
+ wire T_1065_io_has_release_match;
+ wire T_1066_clk;
+ wire T_1066_reset;
+ wire T_1066_io_inner_acquire_ready;
+ wire T_1066_io_inner_acquire_valid;
+ wire [25:0] T_1066_io_inner_acquire_bits_addr_block;
+ wire [1:0] T_1066_io_inner_acquire_bits_client_xact_id;
+ wire [1:0] T_1066_io_inner_acquire_bits_addr_beat;
+ wire T_1066_io_inner_acquire_bits_is_builtin_type;
+ wire [2:0] T_1066_io_inner_acquire_bits_a_type;
+ wire [16:0] T_1066_io_inner_acquire_bits_union;
+ wire [3:0] T_1066_io_inner_acquire_bits_data;
+ wire [1:0] T_1066_io_inner_acquire_bits_client_id;
+ wire T_1066_io_inner_grant_ready;
+ wire T_1066_io_inner_grant_valid;
+ wire [1:0] T_1066_io_inner_grant_bits_addr_beat;
+ wire [1:0] T_1066_io_inner_grant_bits_client_xact_id;
+ wire [3:0] T_1066_io_inner_grant_bits_manager_xact_id;
+ wire T_1066_io_inner_grant_bits_is_builtin_type;
+ wire [3:0] T_1066_io_inner_grant_bits_g_type;
+ wire [3:0] T_1066_io_inner_grant_bits_data;
+ wire [1:0] T_1066_io_inner_grant_bits_client_id;
+ wire T_1066_io_inner_finish_ready;
+ wire T_1066_io_inner_finish_valid;
+ wire [3:0] T_1066_io_inner_finish_bits_manager_xact_id;
+ wire T_1066_io_inner_probe_ready;
+ wire T_1066_io_inner_probe_valid;
+ wire [25:0] T_1066_io_inner_probe_bits_addr_block;
+ wire [1:0] T_1066_io_inner_probe_bits_p_type;
+ wire [1:0] T_1066_io_inner_probe_bits_client_id;
+ wire T_1066_io_inner_release_ready;
+ wire T_1066_io_inner_release_valid;
+ wire [1:0] T_1066_io_inner_release_bits_addr_beat;
+ wire [25:0] T_1066_io_inner_release_bits_addr_block;
+ wire [1:0] T_1066_io_inner_release_bits_client_xact_id;
+ wire T_1066_io_inner_release_bits_voluntary;
+ wire [2:0] T_1066_io_inner_release_bits_r_type;
+ wire [3:0] T_1066_io_inner_release_bits_data;
+ wire [1:0] T_1066_io_inner_release_bits_client_id;
+ wire T_1066_io_incoherent_0;
+ wire T_1066_io_outer_acquire_ready;
+ wire T_1066_io_outer_acquire_valid;
+ wire [25:0] T_1066_io_outer_acquire_bits_addr_block;
+ wire [3:0] T_1066_io_outer_acquire_bits_client_xact_id;
+ wire [1:0] T_1066_io_outer_acquire_bits_addr_beat;
+ wire T_1066_io_outer_acquire_bits_is_builtin_type;
+ wire [2:0] T_1066_io_outer_acquire_bits_a_type;
+ wire [16:0] T_1066_io_outer_acquire_bits_union;
+ wire [3:0] T_1066_io_outer_acquire_bits_data;
+ wire T_1066_io_outer_grant_ready;
+ wire T_1066_io_outer_grant_valid;
+ wire [1:0] T_1066_io_outer_grant_bits_addr_beat;
+ wire [3:0] T_1066_io_outer_grant_bits_client_xact_id;
+ wire T_1066_io_outer_grant_bits_manager_xact_id;
+ wire T_1066_io_outer_grant_bits_is_builtin_type;
+ wire [3:0] T_1066_io_outer_grant_bits_g_type;
+ wire [3:0] T_1066_io_outer_grant_bits_data;
+ wire T_1066_io_has_acquire_conflict;
+ wire T_1066_io_has_acquire_match;
+ wire T_1066_io_has_release_match;
+ wire T_1067_clk;
+ wire T_1067_reset;
+ wire T_1067_io_inner_acquire_ready;
+ wire T_1067_io_inner_acquire_valid;
+ wire [25:0] T_1067_io_inner_acquire_bits_addr_block;
+ wire [1:0] T_1067_io_inner_acquire_bits_client_xact_id;
+ wire [1:0] T_1067_io_inner_acquire_bits_addr_beat;
+ wire T_1067_io_inner_acquire_bits_is_builtin_type;
+ wire [2:0] T_1067_io_inner_acquire_bits_a_type;
+ wire [16:0] T_1067_io_inner_acquire_bits_union;
+ wire [3:0] T_1067_io_inner_acquire_bits_data;
+ wire [1:0] T_1067_io_inner_acquire_bits_client_id;
+ wire T_1067_io_inner_grant_ready;
+ wire T_1067_io_inner_grant_valid;
+ wire [1:0] T_1067_io_inner_grant_bits_addr_beat;
+ wire [1:0] T_1067_io_inner_grant_bits_client_xact_id;
+ wire [3:0] T_1067_io_inner_grant_bits_manager_xact_id;
+ wire T_1067_io_inner_grant_bits_is_builtin_type;
+ wire [3:0] T_1067_io_inner_grant_bits_g_type;
+ wire [3:0] T_1067_io_inner_grant_bits_data;
+ wire [1:0] T_1067_io_inner_grant_bits_client_id;
+ wire T_1067_io_inner_finish_ready;
+ wire T_1067_io_inner_finish_valid;
+ wire [3:0] T_1067_io_inner_finish_bits_manager_xact_id;
+ wire T_1067_io_inner_probe_ready;
+ wire T_1067_io_inner_probe_valid;
+ wire [25:0] T_1067_io_inner_probe_bits_addr_block;
+ wire [1:0] T_1067_io_inner_probe_bits_p_type;
+ wire [1:0] T_1067_io_inner_probe_bits_client_id;
+ wire T_1067_io_inner_release_ready;
+ wire T_1067_io_inner_release_valid;
+ wire [1:0] T_1067_io_inner_release_bits_addr_beat;
+ wire [25:0] T_1067_io_inner_release_bits_addr_block;
+ wire [1:0] T_1067_io_inner_release_bits_client_xact_id;
+ wire T_1067_io_inner_release_bits_voluntary;
+ wire [2:0] T_1067_io_inner_release_bits_r_type;
+ wire [3:0] T_1067_io_inner_release_bits_data;
+ wire [1:0] T_1067_io_inner_release_bits_client_id;
+ wire T_1067_io_incoherent_0;
+ wire T_1067_io_outer_acquire_ready;
+ wire T_1067_io_outer_acquire_valid;
+ wire [25:0] T_1067_io_outer_acquire_bits_addr_block;
+ wire [3:0] T_1067_io_outer_acquire_bits_client_xact_id;
+ wire [1:0] T_1067_io_outer_acquire_bits_addr_beat;
+ wire T_1067_io_outer_acquire_bits_is_builtin_type;
+ wire [2:0] T_1067_io_outer_acquire_bits_a_type;
+ wire [16:0] T_1067_io_outer_acquire_bits_union;
+ wire [3:0] T_1067_io_outer_acquire_bits_data;
+ wire T_1067_io_outer_grant_ready;
+ wire T_1067_io_outer_grant_valid;
+ wire [1:0] T_1067_io_outer_grant_bits_addr_beat;
+ wire [3:0] T_1067_io_outer_grant_bits_client_xact_id;
+ wire T_1067_io_outer_grant_bits_manager_xact_id;
+ wire T_1067_io_outer_grant_bits_is_builtin_type;
+ wire [3:0] T_1067_io_outer_grant_bits_g_type;
+ wire [3:0] T_1067_io_outer_grant_bits_data;
+ wire T_1067_io_has_acquire_conflict;
+ wire T_1067_io_has_acquire_match;
+ wire T_1067_io_has_release_match;
+ reg [127:0] sdq_0;
+ reg [127:0] sdq_1;
+ reg [127:0] sdq_2;
+ reg [127:0] sdq_3;
+ reg [3:0] sdq_val;
+ wire [3:0] T_1085;
+ wire T_1086;
+ wire T_1087;
+ wire T_1088;
+ wire T_1089;
+ wire T_1091_0;
+ wire T_1091_1;
+ wire T_1091_2;
+ wire T_1091_3;
+ wire [1:0] T_1101;
+ wire [1:0] T_1102;
+ wire [1:0] sdq_alloc_id;
+ wire [3:0] T_1104;
+ wire T_1106;
+ wire sdq_rdy;
+ wire T_1109;
+ wire [2:0] T_1114_0;
+ wire [2:0] T_1114_1;
+ wire [2:0] T_1114_2;
+ wire T_1119;
+ wire T_1120;
+ wire T_1121;
+ wire T_1123;
+ wire T_1124;
+ wire T_1125;
+ wire T_1126;
+ wire sdq_enq;
+ wire [127:0] GEN_0;
+ wire T_1130_0;
+ wire T_1130_1;
+ wire T_1130_2;
+ wire T_1130_3;
+ wire T_1130_4;
+ wire T_1130_5;
+ wire T_1130_6;
+ wire T_1130_7;
+ wire [1:0] T_1140;
+ wire [1:0] T_1141;
+ wire [3:0] T_1142;
+ wire [1:0] T_1143;
+ wire [1:0] T_1144;
+ wire [3:0] T_1145;
+ wire [7:0] acquireConflicts;
+ wire T_1148_0;
+ wire T_1148_1;
+ wire T_1148_2;
+ wire T_1148_3;
+ wire T_1148_4;
+ wire T_1148_5;
+ wire T_1148_6;
+ wire T_1148_7;
+ wire [1:0] T_1158;
+ wire [1:0] T_1159;
+ wire [3:0] T_1160;
+ wire [1:0] T_1161;
+ wire [1:0] T_1162;
+ wire [3:0] T_1163;
+ wire [7:0] acquireMatches;
+ wire T_1166_0;
+ wire T_1166_1;
+ wire T_1166_2;
+ wire T_1166_3;
+ wire T_1166_4;
+ wire T_1166_5;
+ wire T_1166_6;
+ wire T_1166_7;
+ wire [1:0] T_1176;
+ wire [1:0] T_1177;
+ wire [3:0] T_1178;
+ wire [1:0] T_1179;
+ wire [1:0] T_1180;
+ wire [3:0] T_1181;
+ wire [7:0] acquireReadys;
+ wire T_1184;
+ wire T_1185;
+ wire T_1186;
+ wire T_1187;
+ wire T_1188;
+ wire T_1189;
+ wire T_1190;
+ wire T_1191;
+ wire T_1192;
+ wire T_1194_0;
+ wire T_1194_1;
+ wire T_1194_2;
+ wire T_1194_3;
+ wire T_1194_4;
+ wire T_1194_5;
+ wire T_1194_6;
+ wire T_1194_7;
+ wire [2:0] T_1212;
+ wire [2:0] T_1213;
+ wire [2:0] T_1214;
+ wire [2:0] T_1215;
+ wire [2:0] T_1216;
+ wire [2:0] T_1217;
+ wire [2:0] T_1218;
+ wire T_1219;
+ wire T_1220;
+ wire T_1221;
+ wire T_1222;
+ wire T_1223;
+ wire T_1224;
+ wire T_1225;
+ wire T_1226;
+ wire T_1228_0;
+ wire T_1228_1;
+ wire T_1228_2;
+ wire T_1228_3;
+ wire T_1228_4;
+ wire T_1228_5;
+ wire T_1228_6;
+ wire T_1228_7;
+ wire [2:0] T_1246;
+ wire [2:0] T_1247;
+ wire [2:0] T_1248;
+ wire [2:0] T_1249;
+ wire [2:0] T_1250;
+ wire [2:0] T_1251;
+ wire [2:0] T_1252;
+ wire [2:0] acquire_idx;
+ wire T_1255;
+ wire T_1257;
+ wire block_acquires;
+ wire T_1260;
+ wire T_1262;
+ wire T_1263;
+ wire [1:0] T_1310_idx;
+ wire [1:0] T_1310_loc;
+ wire [3:0] T_1356;
+ wire T_1358;
+ wire T_1359;
+ wire T_1361;
+ wire T_1362;
+ wire [1:0] T_1409_idx;
+ wire [1:0] T_1409_loc;
+ wire [3:0] T_1455;
+ wire T_1457;
+ wire T_1458;
+ wire T_1460;
+ wire T_1461;
+ wire [1:0] T_1508_idx;
+ wire [1:0] T_1508_loc;
+ wire [3:0] T_1554;
+ wire T_1556;
+ wire T_1557;
+ wire T_1559;
+ wire T_1560;
+ wire [1:0] T_1607_idx;
+ wire [1:0] T_1607_loc;
+ wire [3:0] T_1653;
+ wire T_1655;
+ wire T_1656;
+ wire T_1658;
+ wire T_1659;
+ wire [1:0] T_1706_idx;
+ wire [1:0] T_1706_loc;
+ wire [3:0] T_1752;
+ wire T_1754;
+ wire T_1755;
+ wire T_1757;
+ wire T_1758;
+ wire [1:0] T_1805_idx;
+ wire [1:0] T_1805_loc;
+ wire [3:0] T_1851;
+ wire T_1853;
+ wire T_1854;
+ wire T_1856;
+ wire T_1857;
+ wire [1:0] T_1904_idx;
+ wire [1:0] T_1904_loc;
+ wire [3:0] T_1950;
+ wire T_1952;
+ wire T_1953;
+ wire T_1955;
+ wire T_1956;
+ wire [1:0] T_2003_idx;
+ wire [1:0] T_2003_loc;
+ wire [3:0] T_2049;
+ wire T_2051;
+ wire T_2052;
+ wire T_2054;
+ wire T_2055;
+ wire T_2056;
+ wire T_2057;
+ wire [1:0] T_2059_0;
+ wire [1:0] T_2059_1;
+ wire [1:0] T_2059_2;
+ wire T_2064;
+ wire T_2065;
+ wire T_2066;
+ wire T_2068;
+ wire T_2069;
+ wire T_2070;
+ wire vwbdq_enq;
+ reg [1:0] rel_data_cnt;
+ wire T_2075;
+ wire T_2077;
+ wire [2:0] T_2080;
+ wire [1:0] T_2081;
+ wire [1:0] T_2082;
+ wire rel_data_done;
+ reg [127:0] vwbdq_0;
+ reg [127:0] vwbdq_1;
+ reg [127:0] vwbdq_2;
+ reg [127:0] vwbdq_3;
+ wire [127:0] GEN_1;
+ wire T_2101_0;
+ wire T_2101_1;
+ wire T_2101_2;
+ wire T_2101_3;
+ wire T_2101_4;
+ wire T_2101_5;
+ wire T_2101_6;
+ wire T_2101_7;
+ wire [1:0] T_2111;
+ wire [1:0] T_2112;
+ wire [3:0] T_2113;
+ wire [1:0] T_2114;
+ wire [1:0] T_2115;
+ wire [3:0] T_2116;
+ wire [7:0] releaseReadys;
+ wire T_2119_0;
+ wire T_2119_1;
+ wire T_2119_2;
+ wire T_2119_3;
+ wire T_2119_4;
+ wire T_2119_5;
+ wire T_2119_6;
+ wire T_2119_7;
+ wire [1:0] T_2129;
+ wire [1:0] T_2130;
+ wire [3:0] T_2131;
+ wire [1:0] T_2132;
+ wire [1:0] T_2133;
+ wire [3:0] T_2134;
+ wire [7:0] releaseMatches;
+ wire T_2136;
+ wire T_2137;
+ wire T_2138;
+ wire T_2139;
+ wire T_2140;
+ wire T_2141;
+ wire T_2142;
+ wire T_2143;
+ wire T_2145_0;
+ wire T_2145_1;
+ wire T_2145_2;
+ wire T_2145_3;
+ wire T_2145_4;
+ wire T_2145_5;
+ wire T_2145_6;
+ wire T_2145_7;
+ wire [2:0] T_2163;
+ wire [2:0] T_2164;
+ wire [2:0] T_2165;
+ wire [2:0] T_2166;
+ wire [2:0] T_2167;
+ wire [2:0] T_2168;
+ wire [2:0] release_idx;
+ wire [7:0] T_2170;
+ wire T_2171;
+ wire T_2173;
+ wire T_2174;
+ wire [1:0] T_2221_idx;
+ wire [1:0] T_2221_loc;
+ wire [3:0] T_2267;
+ wire T_2269;
+ wire T_2270;
+ wire [1:0] T_2317_idx;
+ wire [1:0] T_2317_loc;
+ wire [3:0] T_2363;
+ wire T_2365;
+ wire T_2366;
+ wire [1:0] T_2413_idx;
+ wire [1:0] T_2413_loc;
+ wire [3:0] T_2459;
+ wire T_2461;
+ wire T_2462;
+ wire [1:0] T_2509_idx;
+ wire [1:0] T_2509_loc;
+ wire [3:0] T_2555;
+ wire T_2557;
+ wire T_2558;
+ wire [1:0] T_2605_idx;
+ wire [1:0] T_2605_loc;
+ wire [3:0] T_2651;
+ wire T_2653;
+ wire T_2654;
+ wire [1:0] T_2701_idx;
+ wire [1:0] T_2701_loc;
+ wire [3:0] T_2747;
+ wire T_2749;
+ wire T_2750;
+ wire [1:0] T_2797_idx;
+ wire [1:0] T_2797_loc;
+ wire [3:0] T_2843;
+ wire T_2845;
+ wire T_2846;
+ wire [1:0] T_2893_idx;
+ wire [1:0] T_2893_loc;
+ wire [3:0] T_2939;
+ wire T_2941;
+ wire T_2943;
+ wire T_2944;
+ wire T_2946;
+ wire T_2948;
+ wire T_2950;
+ wire T_2952;
+ wire T_2953_clk;
+ wire T_2953_reset;
+ wire T_2953_io_in_0_ready;
+ wire T_2953_io_in_0_valid;
+ wire [1:0] T_2953_io_in_0_bits_addr_beat;
+ wire [1:0] T_2953_io_in_0_bits_client_xact_id;
+ wire [3:0] T_2953_io_in_0_bits_manager_xact_id;
+ wire T_2953_io_in_0_bits_is_builtin_type;
+ wire [3:0] T_2953_io_in_0_bits_g_type;
+ wire [127:0] T_2953_io_in_0_bits_data;
+ wire [1:0] T_2953_io_in_0_bits_client_id;
+ wire T_2953_io_in_1_ready;
+ wire T_2953_io_in_1_valid;
+ wire [1:0] T_2953_io_in_1_bits_addr_beat;
+ wire [1:0] T_2953_io_in_1_bits_client_xact_id;
+ wire [3:0] T_2953_io_in_1_bits_manager_xact_id;
+ wire T_2953_io_in_1_bits_is_builtin_type;
+ wire [3:0] T_2953_io_in_1_bits_g_type;
+ wire [127:0] T_2953_io_in_1_bits_data;
+ wire [1:0] T_2953_io_in_1_bits_client_id;
+ wire T_2953_io_in_2_ready;
+ wire T_2953_io_in_2_valid;
+ wire [1:0] T_2953_io_in_2_bits_addr_beat;
+ wire [1:0] T_2953_io_in_2_bits_client_xact_id;
+ wire [3:0] T_2953_io_in_2_bits_manager_xact_id;
+ wire T_2953_io_in_2_bits_is_builtin_type;
+ wire [3:0] T_2953_io_in_2_bits_g_type;
+ wire [127:0] T_2953_io_in_2_bits_data;
+ wire [1:0] T_2953_io_in_2_bits_client_id;
+ wire T_2953_io_in_3_ready;
+ wire T_2953_io_in_3_valid;
+ wire [1:0] T_2953_io_in_3_bits_addr_beat;
+ wire [1:0] T_2953_io_in_3_bits_client_xact_id;
+ wire [3:0] T_2953_io_in_3_bits_manager_xact_id;
+ wire T_2953_io_in_3_bits_is_builtin_type;
+ wire [3:0] T_2953_io_in_3_bits_g_type;
+ wire [127:0] T_2953_io_in_3_bits_data;
+ wire [1:0] T_2953_io_in_3_bits_client_id;
+ wire T_2953_io_in_4_ready;
+ wire T_2953_io_in_4_valid;
+ wire [1:0] T_2953_io_in_4_bits_addr_beat;
+ wire [1:0] T_2953_io_in_4_bits_client_xact_id;
+ wire [3:0] T_2953_io_in_4_bits_manager_xact_id;
+ wire T_2953_io_in_4_bits_is_builtin_type;
+ wire [3:0] T_2953_io_in_4_bits_g_type;
+ wire [127:0] T_2953_io_in_4_bits_data;
+ wire [1:0] T_2953_io_in_4_bits_client_id;
+ wire T_2953_io_in_5_ready;
+ wire T_2953_io_in_5_valid;
+ wire [1:0] T_2953_io_in_5_bits_addr_beat;
+ wire [1:0] T_2953_io_in_5_bits_client_xact_id;
+ wire [3:0] T_2953_io_in_5_bits_manager_xact_id;
+ wire T_2953_io_in_5_bits_is_builtin_type;
+ wire [3:0] T_2953_io_in_5_bits_g_type;
+ wire [127:0] T_2953_io_in_5_bits_data;
+ wire [1:0] T_2953_io_in_5_bits_client_id;
+ wire T_2953_io_in_6_ready;
+ wire T_2953_io_in_6_valid;
+ wire [1:0] T_2953_io_in_6_bits_addr_beat;
+ wire [1:0] T_2953_io_in_6_bits_client_xact_id;
+ wire [3:0] T_2953_io_in_6_bits_manager_xact_id;
+ wire T_2953_io_in_6_bits_is_builtin_type;
+ wire [3:0] T_2953_io_in_6_bits_g_type;
+ wire [127:0] T_2953_io_in_6_bits_data;
+ wire [1:0] T_2953_io_in_6_bits_client_id;
+ wire T_2953_io_in_7_ready;
+ wire T_2953_io_in_7_valid;
+ wire [1:0] T_2953_io_in_7_bits_addr_beat;
+ wire [1:0] T_2953_io_in_7_bits_client_xact_id;
+ wire [3:0] T_2953_io_in_7_bits_manager_xact_id;
+ wire T_2953_io_in_7_bits_is_builtin_type;
+ wire [3:0] T_2953_io_in_7_bits_g_type;
+ wire [127:0] T_2953_io_in_7_bits_data;
+ wire [1:0] T_2953_io_in_7_bits_client_id;
+ wire T_2953_io_out_ready;
+ wire T_2953_io_out_valid;
+ wire [1:0] T_2953_io_out_bits_addr_beat;
+ wire [1:0] T_2953_io_out_bits_client_xact_id;
+ wire [3:0] T_2953_io_out_bits_manager_xact_id;
+ wire T_2953_io_out_bits_is_builtin_type;
+ wire [3:0] T_2953_io_out_bits_g_type;
+ wire [127:0] T_2953_io_out_bits_data;
+ wire [1:0] T_2953_io_out_bits_client_id;
+ wire [2:0] T_2953_io_chosen;
+ wire T_2954_clk;
+ wire T_2954_reset;
+ wire T_2954_io_in_0_ready;
+ wire T_2954_io_in_0_valid;
+ wire [25:0] T_2954_io_in_0_bits_addr_block;
+ wire [1:0] T_2954_io_in_0_bits_p_type;
+ wire [1:0] T_2954_io_in_0_bits_client_id;
+ wire T_2954_io_in_1_ready;
+ wire T_2954_io_in_1_valid;
+ wire [25:0] T_2954_io_in_1_bits_addr_block;
+ wire [1:0] T_2954_io_in_1_bits_p_type;
+ wire [1:0] T_2954_io_in_1_bits_client_id;
+ wire T_2954_io_in_2_ready;
+ wire T_2954_io_in_2_valid;
+ wire [25:0] T_2954_io_in_2_bits_addr_block;
+ wire [1:0] T_2954_io_in_2_bits_p_type;
+ wire [1:0] T_2954_io_in_2_bits_client_id;
+ wire T_2954_io_in_3_ready;
+ wire T_2954_io_in_3_valid;
+ wire [25:0] T_2954_io_in_3_bits_addr_block;
+ wire [1:0] T_2954_io_in_3_bits_p_type;
+ wire [1:0] T_2954_io_in_3_bits_client_id;
+ wire T_2954_io_in_4_ready;
+ wire T_2954_io_in_4_valid;
+ wire [25:0] T_2954_io_in_4_bits_addr_block;
+ wire [1:0] T_2954_io_in_4_bits_p_type;
+ wire [1:0] T_2954_io_in_4_bits_client_id;
+ wire T_2954_io_in_5_ready;
+ wire T_2954_io_in_5_valid;
+ wire [25:0] T_2954_io_in_5_bits_addr_block;
+ wire [1:0] T_2954_io_in_5_bits_p_type;
+ wire [1:0] T_2954_io_in_5_bits_client_id;
+ wire T_2954_io_in_6_ready;
+ wire T_2954_io_in_6_valid;
+ wire [25:0] T_2954_io_in_6_bits_addr_block;
+ wire [1:0] T_2954_io_in_6_bits_p_type;
+ wire [1:0] T_2954_io_in_6_bits_client_id;
+ wire T_2954_io_in_7_ready;
+ wire T_2954_io_in_7_valid;
+ wire [25:0] T_2954_io_in_7_bits_addr_block;
+ wire [1:0] T_2954_io_in_7_bits_p_type;
+ wire [1:0] T_2954_io_in_7_bits_client_id;
+ wire T_2954_io_out_ready;
+ wire T_2954_io_out_valid;
+ wire [25:0] T_2954_io_out_bits_addr_block;
+ wire [1:0] T_2954_io_out_bits_p_type;
+ wire [1:0] T_2954_io_out_bits_client_id;
+ wire [2:0] T_2954_io_chosen;
+ wire T_2956;
+ wire T_2957;
+ wire T_2959;
+ wire T_2960;
+ wire T_2962;
+ wire T_2963;
+ wire T_2965;
+ wire T_2966;
+ wire T_2968;
+ wire T_2969;
+ wire T_2971;
+ wire T_2972;
+ wire T_2974;
+ wire T_2975;
+ wire T_2977;
+ wire T_2978;
+ wire T_2980_0;
+ wire T_2980_1;
+ wire T_2980_2;
+ wire T_2980_3;
+ wire T_2980_4;
+ wire T_2980_5;
+ wire T_2980_6;
+ wire T_2980_7;
+ wire GEN_2;
+ wire outer_arb_clk;
+ wire outer_arb_reset;
+ wire outer_arb_io_in_0_acquire_ready;
+ wire outer_arb_io_in_0_acquire_valid;
+ wire [25:0] outer_arb_io_in_0_acquire_bits_addr_block;
+ wire [3:0] outer_arb_io_in_0_acquire_bits_client_xact_id;
+ wire [1:0] outer_arb_io_in_0_acquire_bits_addr_beat;
+ wire outer_arb_io_in_0_acquire_bits_is_builtin_type;
+ wire [2:0] outer_arb_io_in_0_acquire_bits_a_type;
+ wire [16:0] outer_arb_io_in_0_acquire_bits_union;
+ wire [3:0] outer_arb_io_in_0_acquire_bits_data;
+ wire outer_arb_io_in_0_grant_ready;
+ wire outer_arb_io_in_0_grant_valid;
+ wire [1:0] outer_arb_io_in_0_grant_bits_addr_beat;
+ wire [3:0] outer_arb_io_in_0_grant_bits_client_xact_id;
+ wire outer_arb_io_in_0_grant_bits_manager_xact_id;
+ wire outer_arb_io_in_0_grant_bits_is_builtin_type;
+ wire [3:0] outer_arb_io_in_0_grant_bits_g_type;
+ wire [3:0] outer_arb_io_in_0_grant_bits_data;
+ wire outer_arb_io_in_1_acquire_ready;
+ wire outer_arb_io_in_1_acquire_valid;
+ wire [25:0] outer_arb_io_in_1_acquire_bits_addr_block;
+ wire [3:0] outer_arb_io_in_1_acquire_bits_client_xact_id;
+ wire [1:0] outer_arb_io_in_1_acquire_bits_addr_beat;
+ wire outer_arb_io_in_1_acquire_bits_is_builtin_type;
+ wire [2:0] outer_arb_io_in_1_acquire_bits_a_type;
+ wire [16:0] outer_arb_io_in_1_acquire_bits_union;
+ wire [3:0] outer_arb_io_in_1_acquire_bits_data;
+ wire outer_arb_io_in_1_grant_ready;
+ wire outer_arb_io_in_1_grant_valid;
+ wire [1:0] outer_arb_io_in_1_grant_bits_addr_beat;
+ wire [3:0] outer_arb_io_in_1_grant_bits_client_xact_id;
+ wire outer_arb_io_in_1_grant_bits_manager_xact_id;
+ wire outer_arb_io_in_1_grant_bits_is_builtin_type;
+ wire [3:0] outer_arb_io_in_1_grant_bits_g_type;
+ wire [3:0] outer_arb_io_in_1_grant_bits_data;
+ wire outer_arb_io_in_2_acquire_ready;
+ wire outer_arb_io_in_2_acquire_valid;
+ wire [25:0] outer_arb_io_in_2_acquire_bits_addr_block;
+ wire [3:0] outer_arb_io_in_2_acquire_bits_client_xact_id;
+ wire [1:0] outer_arb_io_in_2_acquire_bits_addr_beat;
+ wire outer_arb_io_in_2_acquire_bits_is_builtin_type;
+ wire [2:0] outer_arb_io_in_2_acquire_bits_a_type;
+ wire [16:0] outer_arb_io_in_2_acquire_bits_union;
+ wire [3:0] outer_arb_io_in_2_acquire_bits_data;
+ wire outer_arb_io_in_2_grant_ready;
+ wire outer_arb_io_in_2_grant_valid;
+ wire [1:0] outer_arb_io_in_2_grant_bits_addr_beat;
+ wire [3:0] outer_arb_io_in_2_grant_bits_client_xact_id;
+ wire outer_arb_io_in_2_grant_bits_manager_xact_id;
+ wire outer_arb_io_in_2_grant_bits_is_builtin_type;
+ wire [3:0] outer_arb_io_in_2_grant_bits_g_type;
+ wire [3:0] outer_arb_io_in_2_grant_bits_data;
+ wire outer_arb_io_in_3_acquire_ready;
+ wire outer_arb_io_in_3_acquire_valid;
+ wire [25:0] outer_arb_io_in_3_acquire_bits_addr_block;
+ wire [3:0] outer_arb_io_in_3_acquire_bits_client_xact_id;
+ wire [1:0] outer_arb_io_in_3_acquire_bits_addr_beat;
+ wire outer_arb_io_in_3_acquire_bits_is_builtin_type;
+ wire [2:0] outer_arb_io_in_3_acquire_bits_a_type;
+ wire [16:0] outer_arb_io_in_3_acquire_bits_union;
+ wire [3:0] outer_arb_io_in_3_acquire_bits_data;
+ wire outer_arb_io_in_3_grant_ready;
+ wire outer_arb_io_in_3_grant_valid;
+ wire [1:0] outer_arb_io_in_3_grant_bits_addr_beat;
+ wire [3:0] outer_arb_io_in_3_grant_bits_client_xact_id;
+ wire outer_arb_io_in_3_grant_bits_manager_xact_id;
+ wire outer_arb_io_in_3_grant_bits_is_builtin_type;
+ wire [3:0] outer_arb_io_in_3_grant_bits_g_type;
+ wire [3:0] outer_arb_io_in_3_grant_bits_data;
+ wire outer_arb_io_in_4_acquire_ready;
+ wire outer_arb_io_in_4_acquire_valid;
+ wire [25:0] outer_arb_io_in_4_acquire_bits_addr_block;
+ wire [3:0] outer_arb_io_in_4_acquire_bits_client_xact_id;
+ wire [1:0] outer_arb_io_in_4_acquire_bits_addr_beat;
+ wire outer_arb_io_in_4_acquire_bits_is_builtin_type;
+ wire [2:0] outer_arb_io_in_4_acquire_bits_a_type;
+ wire [16:0] outer_arb_io_in_4_acquire_bits_union;
+ wire [3:0] outer_arb_io_in_4_acquire_bits_data;
+ wire outer_arb_io_in_4_grant_ready;
+ wire outer_arb_io_in_4_grant_valid;
+ wire [1:0] outer_arb_io_in_4_grant_bits_addr_beat;
+ wire [3:0] outer_arb_io_in_4_grant_bits_client_xact_id;
+ wire outer_arb_io_in_4_grant_bits_manager_xact_id;
+ wire outer_arb_io_in_4_grant_bits_is_builtin_type;
+ wire [3:0] outer_arb_io_in_4_grant_bits_g_type;
+ wire [3:0] outer_arb_io_in_4_grant_bits_data;
+ wire outer_arb_io_in_5_acquire_ready;
+ wire outer_arb_io_in_5_acquire_valid;
+ wire [25:0] outer_arb_io_in_5_acquire_bits_addr_block;
+ wire [3:0] outer_arb_io_in_5_acquire_bits_client_xact_id;
+ wire [1:0] outer_arb_io_in_5_acquire_bits_addr_beat;
+ wire outer_arb_io_in_5_acquire_bits_is_builtin_type;
+ wire [2:0] outer_arb_io_in_5_acquire_bits_a_type;
+ wire [16:0] outer_arb_io_in_5_acquire_bits_union;
+ wire [3:0] outer_arb_io_in_5_acquire_bits_data;
+ wire outer_arb_io_in_5_grant_ready;
+ wire outer_arb_io_in_5_grant_valid;
+ wire [1:0] outer_arb_io_in_5_grant_bits_addr_beat;
+ wire [3:0] outer_arb_io_in_5_grant_bits_client_xact_id;
+ wire outer_arb_io_in_5_grant_bits_manager_xact_id;
+ wire outer_arb_io_in_5_grant_bits_is_builtin_type;
+ wire [3:0] outer_arb_io_in_5_grant_bits_g_type;
+ wire [3:0] outer_arb_io_in_5_grant_bits_data;
+ wire outer_arb_io_in_6_acquire_ready;
+ wire outer_arb_io_in_6_acquire_valid;
+ wire [25:0] outer_arb_io_in_6_acquire_bits_addr_block;
+ wire [3:0] outer_arb_io_in_6_acquire_bits_client_xact_id;
+ wire [1:0] outer_arb_io_in_6_acquire_bits_addr_beat;
+ wire outer_arb_io_in_6_acquire_bits_is_builtin_type;
+ wire [2:0] outer_arb_io_in_6_acquire_bits_a_type;
+ wire [16:0] outer_arb_io_in_6_acquire_bits_union;
+ wire [3:0] outer_arb_io_in_6_acquire_bits_data;
+ wire outer_arb_io_in_6_grant_ready;
+ wire outer_arb_io_in_6_grant_valid;
+ wire [1:0] outer_arb_io_in_6_grant_bits_addr_beat;
+ wire [3:0] outer_arb_io_in_6_grant_bits_client_xact_id;
+ wire outer_arb_io_in_6_grant_bits_manager_xact_id;
+ wire outer_arb_io_in_6_grant_bits_is_builtin_type;
+ wire [3:0] outer_arb_io_in_6_grant_bits_g_type;
+ wire [3:0] outer_arb_io_in_6_grant_bits_data;
+ wire outer_arb_io_in_7_acquire_ready;
+ wire outer_arb_io_in_7_acquire_valid;
+ wire [25:0] outer_arb_io_in_7_acquire_bits_addr_block;
+ wire [3:0] outer_arb_io_in_7_acquire_bits_client_xact_id;
+ wire [1:0] outer_arb_io_in_7_acquire_bits_addr_beat;
+ wire outer_arb_io_in_7_acquire_bits_is_builtin_type;
+ wire [2:0] outer_arb_io_in_7_acquire_bits_a_type;
+ wire [16:0] outer_arb_io_in_7_acquire_bits_union;
+ wire [3:0] outer_arb_io_in_7_acquire_bits_data;
+ wire outer_arb_io_in_7_grant_ready;
+ wire outer_arb_io_in_7_grant_valid;
+ wire [1:0] outer_arb_io_in_7_grant_bits_addr_beat;
+ wire [3:0] outer_arb_io_in_7_grant_bits_client_xact_id;
+ wire outer_arb_io_in_7_grant_bits_manager_xact_id;
+ wire outer_arb_io_in_7_grant_bits_is_builtin_type;
+ wire [3:0] outer_arb_io_in_7_grant_bits_g_type;
+ wire [3:0] outer_arb_io_in_7_grant_bits_data;
+ wire outer_arb_io_out_acquire_ready;
+ wire outer_arb_io_out_acquire_valid;
+ wire [25:0] outer_arb_io_out_acquire_bits_addr_block;
+ wire [3:0] outer_arb_io_out_acquire_bits_client_xact_id;
+ wire [1:0] outer_arb_io_out_acquire_bits_addr_beat;
+ wire outer_arb_io_out_acquire_bits_is_builtin_type;
+ wire [2:0] outer_arb_io_out_acquire_bits_a_type;
+ wire [16:0] outer_arb_io_out_acquire_bits_union;
+ wire [3:0] outer_arb_io_out_acquire_bits_data;
+ wire outer_arb_io_out_grant_ready;
+ wire outer_arb_io_out_grant_valid;
+ wire [1:0] outer_arb_io_out_grant_bits_addr_beat;
+ wire [3:0] outer_arb_io_out_grant_bits_client_xact_id;
+ wire outer_arb_io_out_grant_bits_manager_xact_id;
+ wire outer_arb_io_out_grant_bits_is_builtin_type;
+ wire [3:0] outer_arb_io_out_grant_bits_g_type;
+ wire [3:0] outer_arb_io_out_grant_bits_data;
+ wire [1:0] outer_data_ptr_idx;
+ wire [1:0] outer_data_ptr_loc;
+ wire [1:0] T_3130;
+ wire [1:0] T_3131;
+ wire is_in_sdq;
+ wire T_3133;
+ wire [2:0] T_3138_0;
+ wire [2:0] T_3138_1;
+ wire [2:0] T_3138_2;
+ wire T_3143;
+ wire T_3144;
+ wire T_3145;
+ wire T_3147;
+ wire T_3148;
+ wire T_3149;
+ wire T_3150;
+ wire T_3151;
+ wire T_3152;
+ wire free_sdq;
+ wire T_3156;
+ wire [127:0] GEN_3;
+ wire [127:0] T_3157;
+ wire T_3158;
+ wire [127:0] GEN_4;
+ wire [127:0] T_3159;
+ wire T_3160;
+ wire [3:0] T_3162;
+ wire [4:0] T_3164;
+ wire [3:0] T_3165;
+ wire [3:0] T_3166;
+ wire [3:0] T_3167;
+ wire [3:0] T_3168;
+ wire [3:0] T_3169;
+ wire [3:0] T_3170;
+ wire T_3171;
+ wire T_3172;
+ wire T_3173;
+ wire T_3174;
+ wire [3:0] T_3180_0;
+ wire [3:0] T_3180_1;
+ wire [3:0] T_3180_2;
+ wire [3:0] T_3180_3;
+ wire [3:0] T_3188;
+ wire [3:0] T_3189;
+ wire [3:0] T_3190;
+ wire [3:0] T_3191;
+ wire [4:0] T_3193;
+ wire [3:0] T_3194;
+ wire [3:0] T_3195;
+ wire [3:0] T_3196;
+ wire GEN_5;
+ wire GEN_6;
+ wire GEN_7;
+ wire GEN_8;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ wire GEN_17;
+ wire GEN_18;
+ wire GEN_19;
+ wire GEN_20;
+ wire GEN_21;
+ wire GEN_22;
+ wire GEN_23;
+ wire GEN_24;
+ wire GEN_25;
+ wire GEN_26;
+ BroadcastVoluntaryReleaseTracker T_1060 (
+ .clk(T_1060_clk),
+ .reset(T_1060_reset),
+ .io_inner_acquire_ready(T_1060_io_inner_acquire_ready),
+ .io_inner_acquire_valid(T_1060_io_inner_acquire_valid),
+ .io_inner_acquire_bits_addr_block(T_1060_io_inner_acquire_bits_addr_block),
+ .io_inner_acquire_bits_client_xact_id(T_1060_io_inner_acquire_bits_client_xact_id),
+ .io_inner_acquire_bits_addr_beat(T_1060_io_inner_acquire_bits_addr_beat),
+ .io_inner_acquire_bits_is_builtin_type(T_1060_io_inner_acquire_bits_is_builtin_type),
+ .io_inner_acquire_bits_a_type(T_1060_io_inner_acquire_bits_a_type),
+ .io_inner_acquire_bits_union(T_1060_io_inner_acquire_bits_union),
+ .io_inner_acquire_bits_data(T_1060_io_inner_acquire_bits_data),
+ .io_inner_acquire_bits_client_id(T_1060_io_inner_acquire_bits_client_id),
+ .io_inner_grant_ready(T_1060_io_inner_grant_ready),
+ .io_inner_grant_valid(T_1060_io_inner_grant_valid),
+ .io_inner_grant_bits_addr_beat(T_1060_io_inner_grant_bits_addr_beat),
+ .io_inner_grant_bits_client_xact_id(T_1060_io_inner_grant_bits_client_xact_id),
+ .io_inner_grant_bits_manager_xact_id(T_1060_io_inner_grant_bits_manager_xact_id),
+ .io_inner_grant_bits_is_builtin_type(T_1060_io_inner_grant_bits_is_builtin_type),
+ .io_inner_grant_bits_g_type(T_1060_io_inner_grant_bits_g_type),
+ .io_inner_grant_bits_data(T_1060_io_inner_grant_bits_data),
+ .io_inner_grant_bits_client_id(T_1060_io_inner_grant_bits_client_id),
+ .io_inner_finish_ready(T_1060_io_inner_finish_ready),
+ .io_inner_finish_valid(T_1060_io_inner_finish_valid),
+ .io_inner_finish_bits_manager_xact_id(T_1060_io_inner_finish_bits_manager_xact_id),
+ .io_inner_probe_ready(T_1060_io_inner_probe_ready),
+ .io_inner_probe_valid(T_1060_io_inner_probe_valid),
+ .io_inner_probe_bits_addr_block(T_1060_io_inner_probe_bits_addr_block),
+ .io_inner_probe_bits_p_type(T_1060_io_inner_probe_bits_p_type),
+ .io_inner_probe_bits_client_id(T_1060_io_inner_probe_bits_client_id),
+ .io_inner_release_ready(T_1060_io_inner_release_ready),
+ .io_inner_release_valid(T_1060_io_inner_release_valid),
+ .io_inner_release_bits_addr_beat(T_1060_io_inner_release_bits_addr_beat),
+ .io_inner_release_bits_addr_block(T_1060_io_inner_release_bits_addr_block),
+ .io_inner_release_bits_client_xact_id(T_1060_io_inner_release_bits_client_xact_id),
+ .io_inner_release_bits_voluntary(T_1060_io_inner_release_bits_voluntary),
+ .io_inner_release_bits_r_type(T_1060_io_inner_release_bits_r_type),
+ .io_inner_release_bits_data(T_1060_io_inner_release_bits_data),
+ .io_inner_release_bits_client_id(T_1060_io_inner_release_bits_client_id),
+ .io_incoherent_0(T_1060_io_incoherent_0),
+ .io_outer_acquire_ready(T_1060_io_outer_acquire_ready),
+ .io_outer_acquire_valid(T_1060_io_outer_acquire_valid),
+ .io_outer_acquire_bits_addr_block(T_1060_io_outer_acquire_bits_addr_block),
+ .io_outer_acquire_bits_client_xact_id(T_1060_io_outer_acquire_bits_client_xact_id),
+ .io_outer_acquire_bits_addr_beat(T_1060_io_outer_acquire_bits_addr_beat),
+ .io_outer_acquire_bits_is_builtin_type(T_1060_io_outer_acquire_bits_is_builtin_type),
+ .io_outer_acquire_bits_a_type(T_1060_io_outer_acquire_bits_a_type),
+ .io_outer_acquire_bits_union(T_1060_io_outer_acquire_bits_union),
+ .io_outer_acquire_bits_data(T_1060_io_outer_acquire_bits_data),
+ .io_outer_grant_ready(T_1060_io_outer_grant_ready),
+ .io_outer_grant_valid(T_1060_io_outer_grant_valid),
+ .io_outer_grant_bits_addr_beat(T_1060_io_outer_grant_bits_addr_beat),
+ .io_outer_grant_bits_client_xact_id(T_1060_io_outer_grant_bits_client_xact_id),
+ .io_outer_grant_bits_manager_xact_id(T_1060_io_outer_grant_bits_manager_xact_id),
+ .io_outer_grant_bits_is_builtin_type(T_1060_io_outer_grant_bits_is_builtin_type),
+ .io_outer_grant_bits_g_type(T_1060_io_outer_grant_bits_g_type),
+ .io_outer_grant_bits_data(T_1060_io_outer_grant_bits_data),
+ .io_has_acquire_conflict(T_1060_io_has_acquire_conflict),
+ .io_has_acquire_match(T_1060_io_has_acquire_match),
+ .io_has_release_match(T_1060_io_has_release_match)
+ );
+ BroadcastAcquireTracker T_1061 (
+ .clk(T_1061_clk),
+ .reset(T_1061_reset),
+ .io_inner_acquire_ready(T_1061_io_inner_acquire_ready),
+ .io_inner_acquire_valid(T_1061_io_inner_acquire_valid),
+ .io_inner_acquire_bits_addr_block(T_1061_io_inner_acquire_bits_addr_block),
+ .io_inner_acquire_bits_client_xact_id(T_1061_io_inner_acquire_bits_client_xact_id),
+ .io_inner_acquire_bits_addr_beat(T_1061_io_inner_acquire_bits_addr_beat),
+ .io_inner_acquire_bits_is_builtin_type(T_1061_io_inner_acquire_bits_is_builtin_type),
+ .io_inner_acquire_bits_a_type(T_1061_io_inner_acquire_bits_a_type),
+ .io_inner_acquire_bits_union(T_1061_io_inner_acquire_bits_union),
+ .io_inner_acquire_bits_data(T_1061_io_inner_acquire_bits_data),
+ .io_inner_acquire_bits_client_id(T_1061_io_inner_acquire_bits_client_id),
+ .io_inner_grant_ready(T_1061_io_inner_grant_ready),
+ .io_inner_grant_valid(T_1061_io_inner_grant_valid),
+ .io_inner_grant_bits_addr_beat(T_1061_io_inner_grant_bits_addr_beat),
+ .io_inner_grant_bits_client_xact_id(T_1061_io_inner_grant_bits_client_xact_id),
+ .io_inner_grant_bits_manager_xact_id(T_1061_io_inner_grant_bits_manager_xact_id),
+ .io_inner_grant_bits_is_builtin_type(T_1061_io_inner_grant_bits_is_builtin_type),
+ .io_inner_grant_bits_g_type(T_1061_io_inner_grant_bits_g_type),
+ .io_inner_grant_bits_data(T_1061_io_inner_grant_bits_data),
+ .io_inner_grant_bits_client_id(T_1061_io_inner_grant_bits_client_id),
+ .io_inner_finish_ready(T_1061_io_inner_finish_ready),
+ .io_inner_finish_valid(T_1061_io_inner_finish_valid),
+ .io_inner_finish_bits_manager_xact_id(T_1061_io_inner_finish_bits_manager_xact_id),
+ .io_inner_probe_ready(T_1061_io_inner_probe_ready),
+ .io_inner_probe_valid(T_1061_io_inner_probe_valid),
+ .io_inner_probe_bits_addr_block(T_1061_io_inner_probe_bits_addr_block),
+ .io_inner_probe_bits_p_type(T_1061_io_inner_probe_bits_p_type),
+ .io_inner_probe_bits_client_id(T_1061_io_inner_probe_bits_client_id),
+ .io_inner_release_ready(T_1061_io_inner_release_ready),
+ .io_inner_release_valid(T_1061_io_inner_release_valid),
+ .io_inner_release_bits_addr_beat(T_1061_io_inner_release_bits_addr_beat),
+ .io_inner_release_bits_addr_block(T_1061_io_inner_release_bits_addr_block),
+ .io_inner_release_bits_client_xact_id(T_1061_io_inner_release_bits_client_xact_id),
+ .io_inner_release_bits_voluntary(T_1061_io_inner_release_bits_voluntary),
+ .io_inner_release_bits_r_type(T_1061_io_inner_release_bits_r_type),
+ .io_inner_release_bits_data(T_1061_io_inner_release_bits_data),
+ .io_inner_release_bits_client_id(T_1061_io_inner_release_bits_client_id),
+ .io_incoherent_0(T_1061_io_incoherent_0),
+ .io_outer_acquire_ready(T_1061_io_outer_acquire_ready),
+ .io_outer_acquire_valid(T_1061_io_outer_acquire_valid),
+ .io_outer_acquire_bits_addr_block(T_1061_io_outer_acquire_bits_addr_block),
+ .io_outer_acquire_bits_client_xact_id(T_1061_io_outer_acquire_bits_client_xact_id),
+ .io_outer_acquire_bits_addr_beat(T_1061_io_outer_acquire_bits_addr_beat),
+ .io_outer_acquire_bits_is_builtin_type(T_1061_io_outer_acquire_bits_is_builtin_type),
+ .io_outer_acquire_bits_a_type(T_1061_io_outer_acquire_bits_a_type),
+ .io_outer_acquire_bits_union(T_1061_io_outer_acquire_bits_union),
+ .io_outer_acquire_bits_data(T_1061_io_outer_acquire_bits_data),
+ .io_outer_grant_ready(T_1061_io_outer_grant_ready),
+ .io_outer_grant_valid(T_1061_io_outer_grant_valid),
+ .io_outer_grant_bits_addr_beat(T_1061_io_outer_grant_bits_addr_beat),
+ .io_outer_grant_bits_client_xact_id(T_1061_io_outer_grant_bits_client_xact_id),
+ .io_outer_grant_bits_manager_xact_id(T_1061_io_outer_grant_bits_manager_xact_id),
+ .io_outer_grant_bits_is_builtin_type(T_1061_io_outer_grant_bits_is_builtin_type),
+ .io_outer_grant_bits_g_type(T_1061_io_outer_grant_bits_g_type),
+ .io_outer_grant_bits_data(T_1061_io_outer_grant_bits_data),
+ .io_has_acquire_conflict(T_1061_io_has_acquire_conflict),
+ .io_has_acquire_match(T_1061_io_has_acquire_match),
+ .io_has_release_match(T_1061_io_has_release_match)
+ );
+ BroadcastAcquireTracker_27 T_1062 (
+ .clk(T_1062_clk),
+ .reset(T_1062_reset),
+ .io_inner_acquire_ready(T_1062_io_inner_acquire_ready),
+ .io_inner_acquire_valid(T_1062_io_inner_acquire_valid),
+ .io_inner_acquire_bits_addr_block(T_1062_io_inner_acquire_bits_addr_block),
+ .io_inner_acquire_bits_client_xact_id(T_1062_io_inner_acquire_bits_client_xact_id),
+ .io_inner_acquire_bits_addr_beat(T_1062_io_inner_acquire_bits_addr_beat),
+ .io_inner_acquire_bits_is_builtin_type(T_1062_io_inner_acquire_bits_is_builtin_type),
+ .io_inner_acquire_bits_a_type(T_1062_io_inner_acquire_bits_a_type),
+ .io_inner_acquire_bits_union(T_1062_io_inner_acquire_bits_union),
+ .io_inner_acquire_bits_data(T_1062_io_inner_acquire_bits_data),
+ .io_inner_acquire_bits_client_id(T_1062_io_inner_acquire_bits_client_id),
+ .io_inner_grant_ready(T_1062_io_inner_grant_ready),
+ .io_inner_grant_valid(T_1062_io_inner_grant_valid),
+ .io_inner_grant_bits_addr_beat(T_1062_io_inner_grant_bits_addr_beat),
+ .io_inner_grant_bits_client_xact_id(T_1062_io_inner_grant_bits_client_xact_id),
+ .io_inner_grant_bits_manager_xact_id(T_1062_io_inner_grant_bits_manager_xact_id),
+ .io_inner_grant_bits_is_builtin_type(T_1062_io_inner_grant_bits_is_builtin_type),
+ .io_inner_grant_bits_g_type(T_1062_io_inner_grant_bits_g_type),
+ .io_inner_grant_bits_data(T_1062_io_inner_grant_bits_data),
+ .io_inner_grant_bits_client_id(T_1062_io_inner_grant_bits_client_id),
+ .io_inner_finish_ready(T_1062_io_inner_finish_ready),
+ .io_inner_finish_valid(T_1062_io_inner_finish_valid),
+ .io_inner_finish_bits_manager_xact_id(T_1062_io_inner_finish_bits_manager_xact_id),
+ .io_inner_probe_ready(T_1062_io_inner_probe_ready),
+ .io_inner_probe_valid(T_1062_io_inner_probe_valid),
+ .io_inner_probe_bits_addr_block(T_1062_io_inner_probe_bits_addr_block),
+ .io_inner_probe_bits_p_type(T_1062_io_inner_probe_bits_p_type),
+ .io_inner_probe_bits_client_id(T_1062_io_inner_probe_bits_client_id),
+ .io_inner_release_ready(T_1062_io_inner_release_ready),
+ .io_inner_release_valid(T_1062_io_inner_release_valid),
+ .io_inner_release_bits_addr_beat(T_1062_io_inner_release_bits_addr_beat),
+ .io_inner_release_bits_addr_block(T_1062_io_inner_release_bits_addr_block),
+ .io_inner_release_bits_client_xact_id(T_1062_io_inner_release_bits_client_xact_id),
+ .io_inner_release_bits_voluntary(T_1062_io_inner_release_bits_voluntary),
+ .io_inner_release_bits_r_type(T_1062_io_inner_release_bits_r_type),
+ .io_inner_release_bits_data(T_1062_io_inner_release_bits_data),
+ .io_inner_release_bits_client_id(T_1062_io_inner_release_bits_client_id),
+ .io_incoherent_0(T_1062_io_incoherent_0),
+ .io_outer_acquire_ready(T_1062_io_outer_acquire_ready),
+ .io_outer_acquire_valid(T_1062_io_outer_acquire_valid),
+ .io_outer_acquire_bits_addr_block(T_1062_io_outer_acquire_bits_addr_block),
+ .io_outer_acquire_bits_client_xact_id(T_1062_io_outer_acquire_bits_client_xact_id),
+ .io_outer_acquire_bits_addr_beat(T_1062_io_outer_acquire_bits_addr_beat),
+ .io_outer_acquire_bits_is_builtin_type(T_1062_io_outer_acquire_bits_is_builtin_type),
+ .io_outer_acquire_bits_a_type(T_1062_io_outer_acquire_bits_a_type),
+ .io_outer_acquire_bits_union(T_1062_io_outer_acquire_bits_union),
+ .io_outer_acquire_bits_data(T_1062_io_outer_acquire_bits_data),
+ .io_outer_grant_ready(T_1062_io_outer_grant_ready),
+ .io_outer_grant_valid(T_1062_io_outer_grant_valid),
+ .io_outer_grant_bits_addr_beat(T_1062_io_outer_grant_bits_addr_beat),
+ .io_outer_grant_bits_client_xact_id(T_1062_io_outer_grant_bits_client_xact_id),
+ .io_outer_grant_bits_manager_xact_id(T_1062_io_outer_grant_bits_manager_xact_id),
+ .io_outer_grant_bits_is_builtin_type(T_1062_io_outer_grant_bits_is_builtin_type),
+ .io_outer_grant_bits_g_type(T_1062_io_outer_grant_bits_g_type),
+ .io_outer_grant_bits_data(T_1062_io_outer_grant_bits_data),
+ .io_has_acquire_conflict(T_1062_io_has_acquire_conflict),
+ .io_has_acquire_match(T_1062_io_has_acquire_match),
+ .io_has_release_match(T_1062_io_has_release_match)
+ );
+ BroadcastAcquireTracker_28 T_1063 (
+ .clk(T_1063_clk),
+ .reset(T_1063_reset),
+ .io_inner_acquire_ready(T_1063_io_inner_acquire_ready),
+ .io_inner_acquire_valid(T_1063_io_inner_acquire_valid),
+ .io_inner_acquire_bits_addr_block(T_1063_io_inner_acquire_bits_addr_block),
+ .io_inner_acquire_bits_client_xact_id(T_1063_io_inner_acquire_bits_client_xact_id),
+ .io_inner_acquire_bits_addr_beat(T_1063_io_inner_acquire_bits_addr_beat),
+ .io_inner_acquire_bits_is_builtin_type(T_1063_io_inner_acquire_bits_is_builtin_type),
+ .io_inner_acquire_bits_a_type(T_1063_io_inner_acquire_bits_a_type),
+ .io_inner_acquire_bits_union(T_1063_io_inner_acquire_bits_union),
+ .io_inner_acquire_bits_data(T_1063_io_inner_acquire_bits_data),
+ .io_inner_acquire_bits_client_id(T_1063_io_inner_acquire_bits_client_id),
+ .io_inner_grant_ready(T_1063_io_inner_grant_ready),
+ .io_inner_grant_valid(T_1063_io_inner_grant_valid),
+ .io_inner_grant_bits_addr_beat(T_1063_io_inner_grant_bits_addr_beat),
+ .io_inner_grant_bits_client_xact_id(T_1063_io_inner_grant_bits_client_xact_id),
+ .io_inner_grant_bits_manager_xact_id(T_1063_io_inner_grant_bits_manager_xact_id),
+ .io_inner_grant_bits_is_builtin_type(T_1063_io_inner_grant_bits_is_builtin_type),
+ .io_inner_grant_bits_g_type(T_1063_io_inner_grant_bits_g_type),
+ .io_inner_grant_bits_data(T_1063_io_inner_grant_bits_data),
+ .io_inner_grant_bits_client_id(T_1063_io_inner_grant_bits_client_id),
+ .io_inner_finish_ready(T_1063_io_inner_finish_ready),
+ .io_inner_finish_valid(T_1063_io_inner_finish_valid),
+ .io_inner_finish_bits_manager_xact_id(T_1063_io_inner_finish_bits_manager_xact_id),
+ .io_inner_probe_ready(T_1063_io_inner_probe_ready),
+ .io_inner_probe_valid(T_1063_io_inner_probe_valid),
+ .io_inner_probe_bits_addr_block(T_1063_io_inner_probe_bits_addr_block),
+ .io_inner_probe_bits_p_type(T_1063_io_inner_probe_bits_p_type),
+ .io_inner_probe_bits_client_id(T_1063_io_inner_probe_bits_client_id),
+ .io_inner_release_ready(T_1063_io_inner_release_ready),
+ .io_inner_release_valid(T_1063_io_inner_release_valid),
+ .io_inner_release_bits_addr_beat(T_1063_io_inner_release_bits_addr_beat),
+ .io_inner_release_bits_addr_block(T_1063_io_inner_release_bits_addr_block),
+ .io_inner_release_bits_client_xact_id(T_1063_io_inner_release_bits_client_xact_id),
+ .io_inner_release_bits_voluntary(T_1063_io_inner_release_bits_voluntary),
+ .io_inner_release_bits_r_type(T_1063_io_inner_release_bits_r_type),
+ .io_inner_release_bits_data(T_1063_io_inner_release_bits_data),
+ .io_inner_release_bits_client_id(T_1063_io_inner_release_bits_client_id),
+ .io_incoherent_0(T_1063_io_incoherent_0),
+ .io_outer_acquire_ready(T_1063_io_outer_acquire_ready),
+ .io_outer_acquire_valid(T_1063_io_outer_acquire_valid),
+ .io_outer_acquire_bits_addr_block(T_1063_io_outer_acquire_bits_addr_block),
+ .io_outer_acquire_bits_client_xact_id(T_1063_io_outer_acquire_bits_client_xact_id),
+ .io_outer_acquire_bits_addr_beat(T_1063_io_outer_acquire_bits_addr_beat),
+ .io_outer_acquire_bits_is_builtin_type(T_1063_io_outer_acquire_bits_is_builtin_type),
+ .io_outer_acquire_bits_a_type(T_1063_io_outer_acquire_bits_a_type),
+ .io_outer_acquire_bits_union(T_1063_io_outer_acquire_bits_union),
+ .io_outer_acquire_bits_data(T_1063_io_outer_acquire_bits_data),
+ .io_outer_grant_ready(T_1063_io_outer_grant_ready),
+ .io_outer_grant_valid(T_1063_io_outer_grant_valid),
+ .io_outer_grant_bits_addr_beat(T_1063_io_outer_grant_bits_addr_beat),
+ .io_outer_grant_bits_client_xact_id(T_1063_io_outer_grant_bits_client_xact_id),
+ .io_outer_grant_bits_manager_xact_id(T_1063_io_outer_grant_bits_manager_xact_id),
+ .io_outer_grant_bits_is_builtin_type(T_1063_io_outer_grant_bits_is_builtin_type),
+ .io_outer_grant_bits_g_type(T_1063_io_outer_grant_bits_g_type),
+ .io_outer_grant_bits_data(T_1063_io_outer_grant_bits_data),
+ .io_has_acquire_conflict(T_1063_io_has_acquire_conflict),
+ .io_has_acquire_match(T_1063_io_has_acquire_match),
+ .io_has_release_match(T_1063_io_has_release_match)
+ );
+ BroadcastAcquireTracker_29 T_1064 (
+ .clk(T_1064_clk),
+ .reset(T_1064_reset),
+ .io_inner_acquire_ready(T_1064_io_inner_acquire_ready),
+ .io_inner_acquire_valid(T_1064_io_inner_acquire_valid),
+ .io_inner_acquire_bits_addr_block(T_1064_io_inner_acquire_bits_addr_block),
+ .io_inner_acquire_bits_client_xact_id(T_1064_io_inner_acquire_bits_client_xact_id),
+ .io_inner_acquire_bits_addr_beat(T_1064_io_inner_acquire_bits_addr_beat),
+ .io_inner_acquire_bits_is_builtin_type(T_1064_io_inner_acquire_bits_is_builtin_type),
+ .io_inner_acquire_bits_a_type(T_1064_io_inner_acquire_bits_a_type),
+ .io_inner_acquire_bits_union(T_1064_io_inner_acquire_bits_union),
+ .io_inner_acquire_bits_data(T_1064_io_inner_acquire_bits_data),
+ .io_inner_acquire_bits_client_id(T_1064_io_inner_acquire_bits_client_id),
+ .io_inner_grant_ready(T_1064_io_inner_grant_ready),
+ .io_inner_grant_valid(T_1064_io_inner_grant_valid),
+ .io_inner_grant_bits_addr_beat(T_1064_io_inner_grant_bits_addr_beat),
+ .io_inner_grant_bits_client_xact_id(T_1064_io_inner_grant_bits_client_xact_id),
+ .io_inner_grant_bits_manager_xact_id(T_1064_io_inner_grant_bits_manager_xact_id),
+ .io_inner_grant_bits_is_builtin_type(T_1064_io_inner_grant_bits_is_builtin_type),
+ .io_inner_grant_bits_g_type(T_1064_io_inner_grant_bits_g_type),
+ .io_inner_grant_bits_data(T_1064_io_inner_grant_bits_data),
+ .io_inner_grant_bits_client_id(T_1064_io_inner_grant_bits_client_id),
+ .io_inner_finish_ready(T_1064_io_inner_finish_ready),
+ .io_inner_finish_valid(T_1064_io_inner_finish_valid),
+ .io_inner_finish_bits_manager_xact_id(T_1064_io_inner_finish_bits_manager_xact_id),
+ .io_inner_probe_ready(T_1064_io_inner_probe_ready),
+ .io_inner_probe_valid(T_1064_io_inner_probe_valid),
+ .io_inner_probe_bits_addr_block(T_1064_io_inner_probe_bits_addr_block),
+ .io_inner_probe_bits_p_type(T_1064_io_inner_probe_bits_p_type),
+ .io_inner_probe_bits_client_id(T_1064_io_inner_probe_bits_client_id),
+ .io_inner_release_ready(T_1064_io_inner_release_ready),
+ .io_inner_release_valid(T_1064_io_inner_release_valid),
+ .io_inner_release_bits_addr_beat(T_1064_io_inner_release_bits_addr_beat),
+ .io_inner_release_bits_addr_block(T_1064_io_inner_release_bits_addr_block),
+ .io_inner_release_bits_client_xact_id(T_1064_io_inner_release_bits_client_xact_id),
+ .io_inner_release_bits_voluntary(T_1064_io_inner_release_bits_voluntary),
+ .io_inner_release_bits_r_type(T_1064_io_inner_release_bits_r_type),
+ .io_inner_release_bits_data(T_1064_io_inner_release_bits_data),
+ .io_inner_release_bits_client_id(T_1064_io_inner_release_bits_client_id),
+ .io_incoherent_0(T_1064_io_incoherent_0),
+ .io_outer_acquire_ready(T_1064_io_outer_acquire_ready),
+ .io_outer_acquire_valid(T_1064_io_outer_acquire_valid),
+ .io_outer_acquire_bits_addr_block(T_1064_io_outer_acquire_bits_addr_block),
+ .io_outer_acquire_bits_client_xact_id(T_1064_io_outer_acquire_bits_client_xact_id),
+ .io_outer_acquire_bits_addr_beat(T_1064_io_outer_acquire_bits_addr_beat),
+ .io_outer_acquire_bits_is_builtin_type(T_1064_io_outer_acquire_bits_is_builtin_type),
+ .io_outer_acquire_bits_a_type(T_1064_io_outer_acquire_bits_a_type),
+ .io_outer_acquire_bits_union(T_1064_io_outer_acquire_bits_union),
+ .io_outer_acquire_bits_data(T_1064_io_outer_acquire_bits_data),
+ .io_outer_grant_ready(T_1064_io_outer_grant_ready),
+ .io_outer_grant_valid(T_1064_io_outer_grant_valid),
+ .io_outer_grant_bits_addr_beat(T_1064_io_outer_grant_bits_addr_beat),
+ .io_outer_grant_bits_client_xact_id(T_1064_io_outer_grant_bits_client_xact_id),
+ .io_outer_grant_bits_manager_xact_id(T_1064_io_outer_grant_bits_manager_xact_id),
+ .io_outer_grant_bits_is_builtin_type(T_1064_io_outer_grant_bits_is_builtin_type),
+ .io_outer_grant_bits_g_type(T_1064_io_outer_grant_bits_g_type),
+ .io_outer_grant_bits_data(T_1064_io_outer_grant_bits_data),
+ .io_has_acquire_conflict(T_1064_io_has_acquire_conflict),
+ .io_has_acquire_match(T_1064_io_has_acquire_match),
+ .io_has_release_match(T_1064_io_has_release_match)
+ );
+ BroadcastAcquireTracker_30 T_1065 (
+ .clk(T_1065_clk),
+ .reset(T_1065_reset),
+ .io_inner_acquire_ready(T_1065_io_inner_acquire_ready),
+ .io_inner_acquire_valid(T_1065_io_inner_acquire_valid),
+ .io_inner_acquire_bits_addr_block(T_1065_io_inner_acquire_bits_addr_block),
+ .io_inner_acquire_bits_client_xact_id(T_1065_io_inner_acquire_bits_client_xact_id),
+ .io_inner_acquire_bits_addr_beat(T_1065_io_inner_acquire_bits_addr_beat),
+ .io_inner_acquire_bits_is_builtin_type(T_1065_io_inner_acquire_bits_is_builtin_type),
+ .io_inner_acquire_bits_a_type(T_1065_io_inner_acquire_bits_a_type),
+ .io_inner_acquire_bits_union(T_1065_io_inner_acquire_bits_union),
+ .io_inner_acquire_bits_data(T_1065_io_inner_acquire_bits_data),
+ .io_inner_acquire_bits_client_id(T_1065_io_inner_acquire_bits_client_id),
+ .io_inner_grant_ready(T_1065_io_inner_grant_ready),
+ .io_inner_grant_valid(T_1065_io_inner_grant_valid),
+ .io_inner_grant_bits_addr_beat(T_1065_io_inner_grant_bits_addr_beat),
+ .io_inner_grant_bits_client_xact_id(T_1065_io_inner_grant_bits_client_xact_id),
+ .io_inner_grant_bits_manager_xact_id(T_1065_io_inner_grant_bits_manager_xact_id),
+ .io_inner_grant_bits_is_builtin_type(T_1065_io_inner_grant_bits_is_builtin_type),
+ .io_inner_grant_bits_g_type(T_1065_io_inner_grant_bits_g_type),
+ .io_inner_grant_bits_data(T_1065_io_inner_grant_bits_data),
+ .io_inner_grant_bits_client_id(T_1065_io_inner_grant_bits_client_id),
+ .io_inner_finish_ready(T_1065_io_inner_finish_ready),
+ .io_inner_finish_valid(T_1065_io_inner_finish_valid),
+ .io_inner_finish_bits_manager_xact_id(T_1065_io_inner_finish_bits_manager_xact_id),
+ .io_inner_probe_ready(T_1065_io_inner_probe_ready),
+ .io_inner_probe_valid(T_1065_io_inner_probe_valid),
+ .io_inner_probe_bits_addr_block(T_1065_io_inner_probe_bits_addr_block),
+ .io_inner_probe_bits_p_type(T_1065_io_inner_probe_bits_p_type),
+ .io_inner_probe_bits_client_id(T_1065_io_inner_probe_bits_client_id),
+ .io_inner_release_ready(T_1065_io_inner_release_ready),
+ .io_inner_release_valid(T_1065_io_inner_release_valid),
+ .io_inner_release_bits_addr_beat(T_1065_io_inner_release_bits_addr_beat),
+ .io_inner_release_bits_addr_block(T_1065_io_inner_release_bits_addr_block),
+ .io_inner_release_bits_client_xact_id(T_1065_io_inner_release_bits_client_xact_id),
+ .io_inner_release_bits_voluntary(T_1065_io_inner_release_bits_voluntary),
+ .io_inner_release_bits_r_type(T_1065_io_inner_release_bits_r_type),
+ .io_inner_release_bits_data(T_1065_io_inner_release_bits_data),
+ .io_inner_release_bits_client_id(T_1065_io_inner_release_bits_client_id),
+ .io_incoherent_0(T_1065_io_incoherent_0),
+ .io_outer_acquire_ready(T_1065_io_outer_acquire_ready),
+ .io_outer_acquire_valid(T_1065_io_outer_acquire_valid),
+ .io_outer_acquire_bits_addr_block(T_1065_io_outer_acquire_bits_addr_block),
+ .io_outer_acquire_bits_client_xact_id(T_1065_io_outer_acquire_bits_client_xact_id),
+ .io_outer_acquire_bits_addr_beat(T_1065_io_outer_acquire_bits_addr_beat),
+ .io_outer_acquire_bits_is_builtin_type(T_1065_io_outer_acquire_bits_is_builtin_type),
+ .io_outer_acquire_bits_a_type(T_1065_io_outer_acquire_bits_a_type),
+ .io_outer_acquire_bits_union(T_1065_io_outer_acquire_bits_union),
+ .io_outer_acquire_bits_data(T_1065_io_outer_acquire_bits_data),
+ .io_outer_grant_ready(T_1065_io_outer_grant_ready),
+ .io_outer_grant_valid(T_1065_io_outer_grant_valid),
+ .io_outer_grant_bits_addr_beat(T_1065_io_outer_grant_bits_addr_beat),
+ .io_outer_grant_bits_client_xact_id(T_1065_io_outer_grant_bits_client_xact_id),
+ .io_outer_grant_bits_manager_xact_id(T_1065_io_outer_grant_bits_manager_xact_id),
+ .io_outer_grant_bits_is_builtin_type(T_1065_io_outer_grant_bits_is_builtin_type),
+ .io_outer_grant_bits_g_type(T_1065_io_outer_grant_bits_g_type),
+ .io_outer_grant_bits_data(T_1065_io_outer_grant_bits_data),
+ .io_has_acquire_conflict(T_1065_io_has_acquire_conflict),
+ .io_has_acquire_match(T_1065_io_has_acquire_match),
+ .io_has_release_match(T_1065_io_has_release_match)
+ );
+ BroadcastAcquireTracker_31 T_1066 (
+ .clk(T_1066_clk),
+ .reset(T_1066_reset),
+ .io_inner_acquire_ready(T_1066_io_inner_acquire_ready),
+ .io_inner_acquire_valid(T_1066_io_inner_acquire_valid),
+ .io_inner_acquire_bits_addr_block(T_1066_io_inner_acquire_bits_addr_block),
+ .io_inner_acquire_bits_client_xact_id(T_1066_io_inner_acquire_bits_client_xact_id),
+ .io_inner_acquire_bits_addr_beat(T_1066_io_inner_acquire_bits_addr_beat),
+ .io_inner_acquire_bits_is_builtin_type(T_1066_io_inner_acquire_bits_is_builtin_type),
+ .io_inner_acquire_bits_a_type(T_1066_io_inner_acquire_bits_a_type),
+ .io_inner_acquire_bits_union(T_1066_io_inner_acquire_bits_union),
+ .io_inner_acquire_bits_data(T_1066_io_inner_acquire_bits_data),
+ .io_inner_acquire_bits_client_id(T_1066_io_inner_acquire_bits_client_id),
+ .io_inner_grant_ready(T_1066_io_inner_grant_ready),
+ .io_inner_grant_valid(T_1066_io_inner_grant_valid),
+ .io_inner_grant_bits_addr_beat(T_1066_io_inner_grant_bits_addr_beat),
+ .io_inner_grant_bits_client_xact_id(T_1066_io_inner_grant_bits_client_xact_id),
+ .io_inner_grant_bits_manager_xact_id(T_1066_io_inner_grant_bits_manager_xact_id),
+ .io_inner_grant_bits_is_builtin_type(T_1066_io_inner_grant_bits_is_builtin_type),
+ .io_inner_grant_bits_g_type(T_1066_io_inner_grant_bits_g_type),
+ .io_inner_grant_bits_data(T_1066_io_inner_grant_bits_data),
+ .io_inner_grant_bits_client_id(T_1066_io_inner_grant_bits_client_id),
+ .io_inner_finish_ready(T_1066_io_inner_finish_ready),
+ .io_inner_finish_valid(T_1066_io_inner_finish_valid),
+ .io_inner_finish_bits_manager_xact_id(T_1066_io_inner_finish_bits_manager_xact_id),
+ .io_inner_probe_ready(T_1066_io_inner_probe_ready),
+ .io_inner_probe_valid(T_1066_io_inner_probe_valid),
+ .io_inner_probe_bits_addr_block(T_1066_io_inner_probe_bits_addr_block),
+ .io_inner_probe_bits_p_type(T_1066_io_inner_probe_bits_p_type),
+ .io_inner_probe_bits_client_id(T_1066_io_inner_probe_bits_client_id),
+ .io_inner_release_ready(T_1066_io_inner_release_ready),
+ .io_inner_release_valid(T_1066_io_inner_release_valid),
+ .io_inner_release_bits_addr_beat(T_1066_io_inner_release_bits_addr_beat),
+ .io_inner_release_bits_addr_block(T_1066_io_inner_release_bits_addr_block),
+ .io_inner_release_bits_client_xact_id(T_1066_io_inner_release_bits_client_xact_id),
+ .io_inner_release_bits_voluntary(T_1066_io_inner_release_bits_voluntary),
+ .io_inner_release_bits_r_type(T_1066_io_inner_release_bits_r_type),
+ .io_inner_release_bits_data(T_1066_io_inner_release_bits_data),
+ .io_inner_release_bits_client_id(T_1066_io_inner_release_bits_client_id),
+ .io_incoherent_0(T_1066_io_incoherent_0),
+ .io_outer_acquire_ready(T_1066_io_outer_acquire_ready),
+ .io_outer_acquire_valid(T_1066_io_outer_acquire_valid),
+ .io_outer_acquire_bits_addr_block(T_1066_io_outer_acquire_bits_addr_block),
+ .io_outer_acquire_bits_client_xact_id(T_1066_io_outer_acquire_bits_client_xact_id),
+ .io_outer_acquire_bits_addr_beat(T_1066_io_outer_acquire_bits_addr_beat),
+ .io_outer_acquire_bits_is_builtin_type(T_1066_io_outer_acquire_bits_is_builtin_type),
+ .io_outer_acquire_bits_a_type(T_1066_io_outer_acquire_bits_a_type),
+ .io_outer_acquire_bits_union(T_1066_io_outer_acquire_bits_union),
+ .io_outer_acquire_bits_data(T_1066_io_outer_acquire_bits_data),
+ .io_outer_grant_ready(T_1066_io_outer_grant_ready),
+ .io_outer_grant_valid(T_1066_io_outer_grant_valid),
+ .io_outer_grant_bits_addr_beat(T_1066_io_outer_grant_bits_addr_beat),
+ .io_outer_grant_bits_client_xact_id(T_1066_io_outer_grant_bits_client_xact_id),
+ .io_outer_grant_bits_manager_xact_id(T_1066_io_outer_grant_bits_manager_xact_id),
+ .io_outer_grant_bits_is_builtin_type(T_1066_io_outer_grant_bits_is_builtin_type),
+ .io_outer_grant_bits_g_type(T_1066_io_outer_grant_bits_g_type),
+ .io_outer_grant_bits_data(T_1066_io_outer_grant_bits_data),
+ .io_has_acquire_conflict(T_1066_io_has_acquire_conflict),
+ .io_has_acquire_match(T_1066_io_has_acquire_match),
+ .io_has_release_match(T_1066_io_has_release_match)
+ );
+ BroadcastAcquireTracker_32 T_1067 (
+ .clk(T_1067_clk),
+ .reset(T_1067_reset),
+ .io_inner_acquire_ready(T_1067_io_inner_acquire_ready),
+ .io_inner_acquire_valid(T_1067_io_inner_acquire_valid),
+ .io_inner_acquire_bits_addr_block(T_1067_io_inner_acquire_bits_addr_block),
+ .io_inner_acquire_bits_client_xact_id(T_1067_io_inner_acquire_bits_client_xact_id),
+ .io_inner_acquire_bits_addr_beat(T_1067_io_inner_acquire_bits_addr_beat),
+ .io_inner_acquire_bits_is_builtin_type(T_1067_io_inner_acquire_bits_is_builtin_type),
+ .io_inner_acquire_bits_a_type(T_1067_io_inner_acquire_bits_a_type),
+ .io_inner_acquire_bits_union(T_1067_io_inner_acquire_bits_union),
+ .io_inner_acquire_bits_data(T_1067_io_inner_acquire_bits_data),
+ .io_inner_acquire_bits_client_id(T_1067_io_inner_acquire_bits_client_id),
+ .io_inner_grant_ready(T_1067_io_inner_grant_ready),
+ .io_inner_grant_valid(T_1067_io_inner_grant_valid),
+ .io_inner_grant_bits_addr_beat(T_1067_io_inner_grant_bits_addr_beat),
+ .io_inner_grant_bits_client_xact_id(T_1067_io_inner_grant_bits_client_xact_id),
+ .io_inner_grant_bits_manager_xact_id(T_1067_io_inner_grant_bits_manager_xact_id),
+ .io_inner_grant_bits_is_builtin_type(T_1067_io_inner_grant_bits_is_builtin_type),
+ .io_inner_grant_bits_g_type(T_1067_io_inner_grant_bits_g_type),
+ .io_inner_grant_bits_data(T_1067_io_inner_grant_bits_data),
+ .io_inner_grant_bits_client_id(T_1067_io_inner_grant_bits_client_id),
+ .io_inner_finish_ready(T_1067_io_inner_finish_ready),
+ .io_inner_finish_valid(T_1067_io_inner_finish_valid),
+ .io_inner_finish_bits_manager_xact_id(T_1067_io_inner_finish_bits_manager_xact_id),
+ .io_inner_probe_ready(T_1067_io_inner_probe_ready),
+ .io_inner_probe_valid(T_1067_io_inner_probe_valid),
+ .io_inner_probe_bits_addr_block(T_1067_io_inner_probe_bits_addr_block),
+ .io_inner_probe_bits_p_type(T_1067_io_inner_probe_bits_p_type),
+ .io_inner_probe_bits_client_id(T_1067_io_inner_probe_bits_client_id),
+ .io_inner_release_ready(T_1067_io_inner_release_ready),
+ .io_inner_release_valid(T_1067_io_inner_release_valid),
+ .io_inner_release_bits_addr_beat(T_1067_io_inner_release_bits_addr_beat),
+ .io_inner_release_bits_addr_block(T_1067_io_inner_release_bits_addr_block),
+ .io_inner_release_bits_client_xact_id(T_1067_io_inner_release_bits_client_xact_id),
+ .io_inner_release_bits_voluntary(T_1067_io_inner_release_bits_voluntary),
+ .io_inner_release_bits_r_type(T_1067_io_inner_release_bits_r_type),
+ .io_inner_release_bits_data(T_1067_io_inner_release_bits_data),
+ .io_inner_release_bits_client_id(T_1067_io_inner_release_bits_client_id),
+ .io_incoherent_0(T_1067_io_incoherent_0),
+ .io_outer_acquire_ready(T_1067_io_outer_acquire_ready),
+ .io_outer_acquire_valid(T_1067_io_outer_acquire_valid),
+ .io_outer_acquire_bits_addr_block(T_1067_io_outer_acquire_bits_addr_block),
+ .io_outer_acquire_bits_client_xact_id(T_1067_io_outer_acquire_bits_client_xact_id),
+ .io_outer_acquire_bits_addr_beat(T_1067_io_outer_acquire_bits_addr_beat),
+ .io_outer_acquire_bits_is_builtin_type(T_1067_io_outer_acquire_bits_is_builtin_type),
+ .io_outer_acquire_bits_a_type(T_1067_io_outer_acquire_bits_a_type),
+ .io_outer_acquire_bits_union(T_1067_io_outer_acquire_bits_union),
+ .io_outer_acquire_bits_data(T_1067_io_outer_acquire_bits_data),
+ .io_outer_grant_ready(T_1067_io_outer_grant_ready),
+ .io_outer_grant_valid(T_1067_io_outer_grant_valid),
+ .io_outer_grant_bits_addr_beat(T_1067_io_outer_grant_bits_addr_beat),
+ .io_outer_grant_bits_client_xact_id(T_1067_io_outer_grant_bits_client_xact_id),
+ .io_outer_grant_bits_manager_xact_id(T_1067_io_outer_grant_bits_manager_xact_id),
+ .io_outer_grant_bits_is_builtin_type(T_1067_io_outer_grant_bits_is_builtin_type),
+ .io_outer_grant_bits_g_type(T_1067_io_outer_grant_bits_g_type),
+ .io_outer_grant_bits_data(T_1067_io_outer_grant_bits_data),
+ .io_has_acquire_conflict(T_1067_io_has_acquire_conflict),
+ .io_has_acquire_match(T_1067_io_has_acquire_match),
+ .io_has_release_match(T_1067_io_has_release_match)
+ );
+ LockingRRArbiter_33 T_2953 (
+ .clk(T_2953_clk),
+ .reset(T_2953_reset),
+ .io_in_0_ready(T_2953_io_in_0_ready),
+ .io_in_0_valid(T_2953_io_in_0_valid),
+ .io_in_0_bits_addr_beat(T_2953_io_in_0_bits_addr_beat),
+ .io_in_0_bits_client_xact_id(T_2953_io_in_0_bits_client_xact_id),
+ .io_in_0_bits_manager_xact_id(T_2953_io_in_0_bits_manager_xact_id),
+ .io_in_0_bits_is_builtin_type(T_2953_io_in_0_bits_is_builtin_type),
+ .io_in_0_bits_g_type(T_2953_io_in_0_bits_g_type),
+ .io_in_0_bits_data(T_2953_io_in_0_bits_data),
+ .io_in_0_bits_client_id(T_2953_io_in_0_bits_client_id),
+ .io_in_1_ready(T_2953_io_in_1_ready),
+ .io_in_1_valid(T_2953_io_in_1_valid),
+ .io_in_1_bits_addr_beat(T_2953_io_in_1_bits_addr_beat),
+ .io_in_1_bits_client_xact_id(T_2953_io_in_1_bits_client_xact_id),
+ .io_in_1_bits_manager_xact_id(T_2953_io_in_1_bits_manager_xact_id),
+ .io_in_1_bits_is_builtin_type(T_2953_io_in_1_bits_is_builtin_type),
+ .io_in_1_bits_g_type(T_2953_io_in_1_bits_g_type),
+ .io_in_1_bits_data(T_2953_io_in_1_bits_data),
+ .io_in_1_bits_client_id(T_2953_io_in_1_bits_client_id),
+ .io_in_2_ready(T_2953_io_in_2_ready),
+ .io_in_2_valid(T_2953_io_in_2_valid),
+ .io_in_2_bits_addr_beat(T_2953_io_in_2_bits_addr_beat),
+ .io_in_2_bits_client_xact_id(T_2953_io_in_2_bits_client_xact_id),
+ .io_in_2_bits_manager_xact_id(T_2953_io_in_2_bits_manager_xact_id),
+ .io_in_2_bits_is_builtin_type(T_2953_io_in_2_bits_is_builtin_type),
+ .io_in_2_bits_g_type(T_2953_io_in_2_bits_g_type),
+ .io_in_2_bits_data(T_2953_io_in_2_bits_data),
+ .io_in_2_bits_client_id(T_2953_io_in_2_bits_client_id),
+ .io_in_3_ready(T_2953_io_in_3_ready),
+ .io_in_3_valid(T_2953_io_in_3_valid),
+ .io_in_3_bits_addr_beat(T_2953_io_in_3_bits_addr_beat),
+ .io_in_3_bits_client_xact_id(T_2953_io_in_3_bits_client_xact_id),
+ .io_in_3_bits_manager_xact_id(T_2953_io_in_3_bits_manager_xact_id),
+ .io_in_3_bits_is_builtin_type(T_2953_io_in_3_bits_is_builtin_type),
+ .io_in_3_bits_g_type(T_2953_io_in_3_bits_g_type),
+ .io_in_3_bits_data(T_2953_io_in_3_bits_data),
+ .io_in_3_bits_client_id(T_2953_io_in_3_bits_client_id),
+ .io_in_4_ready(T_2953_io_in_4_ready),
+ .io_in_4_valid(T_2953_io_in_4_valid),
+ .io_in_4_bits_addr_beat(T_2953_io_in_4_bits_addr_beat),
+ .io_in_4_bits_client_xact_id(T_2953_io_in_4_bits_client_xact_id),
+ .io_in_4_bits_manager_xact_id(T_2953_io_in_4_bits_manager_xact_id),
+ .io_in_4_bits_is_builtin_type(T_2953_io_in_4_bits_is_builtin_type),
+ .io_in_4_bits_g_type(T_2953_io_in_4_bits_g_type),
+ .io_in_4_bits_data(T_2953_io_in_4_bits_data),
+ .io_in_4_bits_client_id(T_2953_io_in_4_bits_client_id),
+ .io_in_5_ready(T_2953_io_in_5_ready),
+ .io_in_5_valid(T_2953_io_in_5_valid),
+ .io_in_5_bits_addr_beat(T_2953_io_in_5_bits_addr_beat),
+ .io_in_5_bits_client_xact_id(T_2953_io_in_5_bits_client_xact_id),
+ .io_in_5_bits_manager_xact_id(T_2953_io_in_5_bits_manager_xact_id),
+ .io_in_5_bits_is_builtin_type(T_2953_io_in_5_bits_is_builtin_type),
+ .io_in_5_bits_g_type(T_2953_io_in_5_bits_g_type),
+ .io_in_5_bits_data(T_2953_io_in_5_bits_data),
+ .io_in_5_bits_client_id(T_2953_io_in_5_bits_client_id),
+ .io_in_6_ready(T_2953_io_in_6_ready),
+ .io_in_6_valid(T_2953_io_in_6_valid),
+ .io_in_6_bits_addr_beat(T_2953_io_in_6_bits_addr_beat),
+ .io_in_6_bits_client_xact_id(T_2953_io_in_6_bits_client_xact_id),
+ .io_in_6_bits_manager_xact_id(T_2953_io_in_6_bits_manager_xact_id),
+ .io_in_6_bits_is_builtin_type(T_2953_io_in_6_bits_is_builtin_type),
+ .io_in_6_bits_g_type(T_2953_io_in_6_bits_g_type),
+ .io_in_6_bits_data(T_2953_io_in_6_bits_data),
+ .io_in_6_bits_client_id(T_2953_io_in_6_bits_client_id),
+ .io_in_7_ready(T_2953_io_in_7_ready),
+ .io_in_7_valid(T_2953_io_in_7_valid),
+ .io_in_7_bits_addr_beat(T_2953_io_in_7_bits_addr_beat),
+ .io_in_7_bits_client_xact_id(T_2953_io_in_7_bits_client_xact_id),
+ .io_in_7_bits_manager_xact_id(T_2953_io_in_7_bits_manager_xact_id),
+ .io_in_7_bits_is_builtin_type(T_2953_io_in_7_bits_is_builtin_type),
+ .io_in_7_bits_g_type(T_2953_io_in_7_bits_g_type),
+ .io_in_7_bits_data(T_2953_io_in_7_bits_data),
+ .io_in_7_bits_client_id(T_2953_io_in_7_bits_client_id),
+ .io_out_ready(T_2953_io_out_ready),
+ .io_out_valid(T_2953_io_out_valid),
+ .io_out_bits_addr_beat(T_2953_io_out_bits_addr_beat),
+ .io_out_bits_client_xact_id(T_2953_io_out_bits_client_xact_id),
+ .io_out_bits_manager_xact_id(T_2953_io_out_bits_manager_xact_id),
+ .io_out_bits_is_builtin_type(T_2953_io_out_bits_is_builtin_type),
+ .io_out_bits_g_type(T_2953_io_out_bits_g_type),
+ .io_out_bits_data(T_2953_io_out_bits_data),
+ .io_out_bits_client_id(T_2953_io_out_bits_client_id),
+ .io_chosen(T_2953_io_chosen)
+ );
+ LockingRRArbiter_34 T_2954 (
+ .clk(T_2954_clk),
+ .reset(T_2954_reset),
+ .io_in_0_ready(T_2954_io_in_0_ready),
+ .io_in_0_valid(T_2954_io_in_0_valid),
+ .io_in_0_bits_addr_block(T_2954_io_in_0_bits_addr_block),
+ .io_in_0_bits_p_type(T_2954_io_in_0_bits_p_type),
+ .io_in_0_bits_client_id(T_2954_io_in_0_bits_client_id),
+ .io_in_1_ready(T_2954_io_in_1_ready),
+ .io_in_1_valid(T_2954_io_in_1_valid),
+ .io_in_1_bits_addr_block(T_2954_io_in_1_bits_addr_block),
+ .io_in_1_bits_p_type(T_2954_io_in_1_bits_p_type),
+ .io_in_1_bits_client_id(T_2954_io_in_1_bits_client_id),
+ .io_in_2_ready(T_2954_io_in_2_ready),
+ .io_in_2_valid(T_2954_io_in_2_valid),
+ .io_in_2_bits_addr_block(T_2954_io_in_2_bits_addr_block),
+ .io_in_2_bits_p_type(T_2954_io_in_2_bits_p_type),
+ .io_in_2_bits_client_id(T_2954_io_in_2_bits_client_id),
+ .io_in_3_ready(T_2954_io_in_3_ready),
+ .io_in_3_valid(T_2954_io_in_3_valid),
+ .io_in_3_bits_addr_block(T_2954_io_in_3_bits_addr_block),
+ .io_in_3_bits_p_type(T_2954_io_in_3_bits_p_type),
+ .io_in_3_bits_client_id(T_2954_io_in_3_bits_client_id),
+ .io_in_4_ready(T_2954_io_in_4_ready),
+ .io_in_4_valid(T_2954_io_in_4_valid),
+ .io_in_4_bits_addr_block(T_2954_io_in_4_bits_addr_block),
+ .io_in_4_bits_p_type(T_2954_io_in_4_bits_p_type),
+ .io_in_4_bits_client_id(T_2954_io_in_4_bits_client_id),
+ .io_in_5_ready(T_2954_io_in_5_ready),
+ .io_in_5_valid(T_2954_io_in_5_valid),
+ .io_in_5_bits_addr_block(T_2954_io_in_5_bits_addr_block),
+ .io_in_5_bits_p_type(T_2954_io_in_5_bits_p_type),
+ .io_in_5_bits_client_id(T_2954_io_in_5_bits_client_id),
+ .io_in_6_ready(T_2954_io_in_6_ready),
+ .io_in_6_valid(T_2954_io_in_6_valid),
+ .io_in_6_bits_addr_block(T_2954_io_in_6_bits_addr_block),
+ .io_in_6_bits_p_type(T_2954_io_in_6_bits_p_type),
+ .io_in_6_bits_client_id(T_2954_io_in_6_bits_client_id),
+ .io_in_7_ready(T_2954_io_in_7_ready),
+ .io_in_7_valid(T_2954_io_in_7_valid),
+ .io_in_7_bits_addr_block(T_2954_io_in_7_bits_addr_block),
+ .io_in_7_bits_p_type(T_2954_io_in_7_bits_p_type),
+ .io_in_7_bits_client_id(T_2954_io_in_7_bits_client_id),
+ .io_out_ready(T_2954_io_out_ready),
+ .io_out_valid(T_2954_io_out_valid),
+ .io_out_bits_addr_block(T_2954_io_out_bits_addr_block),
+ .io_out_bits_p_type(T_2954_io_out_bits_p_type),
+ .io_out_bits_client_id(T_2954_io_out_bits_client_id),
+ .io_chosen(T_2954_io_chosen)
+ );
+ ClientUncachedTileLinkIOArbiter outer_arb (
+ .clk(outer_arb_clk),
+ .reset(outer_arb_reset),
+ .io_in_0_acquire_ready(outer_arb_io_in_0_acquire_ready),
+ .io_in_0_acquire_valid(outer_arb_io_in_0_acquire_valid),
+ .io_in_0_acquire_bits_addr_block(outer_arb_io_in_0_acquire_bits_addr_block),
+ .io_in_0_acquire_bits_client_xact_id(outer_arb_io_in_0_acquire_bits_client_xact_id),
+ .io_in_0_acquire_bits_addr_beat(outer_arb_io_in_0_acquire_bits_addr_beat),
+ .io_in_0_acquire_bits_is_builtin_type(outer_arb_io_in_0_acquire_bits_is_builtin_type),
+ .io_in_0_acquire_bits_a_type(outer_arb_io_in_0_acquire_bits_a_type),
+ .io_in_0_acquire_bits_union(outer_arb_io_in_0_acquire_bits_union),
+ .io_in_0_acquire_bits_data(outer_arb_io_in_0_acquire_bits_data),
+ .io_in_0_grant_ready(outer_arb_io_in_0_grant_ready),
+ .io_in_0_grant_valid(outer_arb_io_in_0_grant_valid),
+ .io_in_0_grant_bits_addr_beat(outer_arb_io_in_0_grant_bits_addr_beat),
+ .io_in_0_grant_bits_client_xact_id(outer_arb_io_in_0_grant_bits_client_xact_id),
+ .io_in_0_grant_bits_manager_xact_id(outer_arb_io_in_0_grant_bits_manager_xact_id),
+ .io_in_0_grant_bits_is_builtin_type(outer_arb_io_in_0_grant_bits_is_builtin_type),
+ .io_in_0_grant_bits_g_type(outer_arb_io_in_0_grant_bits_g_type),
+ .io_in_0_grant_bits_data(outer_arb_io_in_0_grant_bits_data),
+ .io_in_1_acquire_ready(outer_arb_io_in_1_acquire_ready),
+ .io_in_1_acquire_valid(outer_arb_io_in_1_acquire_valid),
+ .io_in_1_acquire_bits_addr_block(outer_arb_io_in_1_acquire_bits_addr_block),
+ .io_in_1_acquire_bits_client_xact_id(outer_arb_io_in_1_acquire_bits_client_xact_id),
+ .io_in_1_acquire_bits_addr_beat(outer_arb_io_in_1_acquire_bits_addr_beat),
+ .io_in_1_acquire_bits_is_builtin_type(outer_arb_io_in_1_acquire_bits_is_builtin_type),
+ .io_in_1_acquire_bits_a_type(outer_arb_io_in_1_acquire_bits_a_type),
+ .io_in_1_acquire_bits_union(outer_arb_io_in_1_acquire_bits_union),
+ .io_in_1_acquire_bits_data(outer_arb_io_in_1_acquire_bits_data),
+ .io_in_1_grant_ready(outer_arb_io_in_1_grant_ready),
+ .io_in_1_grant_valid(outer_arb_io_in_1_grant_valid),
+ .io_in_1_grant_bits_addr_beat(outer_arb_io_in_1_grant_bits_addr_beat),
+ .io_in_1_grant_bits_client_xact_id(outer_arb_io_in_1_grant_bits_client_xact_id),
+ .io_in_1_grant_bits_manager_xact_id(outer_arb_io_in_1_grant_bits_manager_xact_id),
+ .io_in_1_grant_bits_is_builtin_type(outer_arb_io_in_1_grant_bits_is_builtin_type),
+ .io_in_1_grant_bits_g_type(outer_arb_io_in_1_grant_bits_g_type),
+ .io_in_1_grant_bits_data(outer_arb_io_in_1_grant_bits_data),
+ .io_in_2_acquire_ready(outer_arb_io_in_2_acquire_ready),
+ .io_in_2_acquire_valid(outer_arb_io_in_2_acquire_valid),
+ .io_in_2_acquire_bits_addr_block(outer_arb_io_in_2_acquire_bits_addr_block),
+ .io_in_2_acquire_bits_client_xact_id(outer_arb_io_in_2_acquire_bits_client_xact_id),
+ .io_in_2_acquire_bits_addr_beat(outer_arb_io_in_2_acquire_bits_addr_beat),
+ .io_in_2_acquire_bits_is_builtin_type(outer_arb_io_in_2_acquire_bits_is_builtin_type),
+ .io_in_2_acquire_bits_a_type(outer_arb_io_in_2_acquire_bits_a_type),
+ .io_in_2_acquire_bits_union(outer_arb_io_in_2_acquire_bits_union),
+ .io_in_2_acquire_bits_data(outer_arb_io_in_2_acquire_bits_data),
+ .io_in_2_grant_ready(outer_arb_io_in_2_grant_ready),
+ .io_in_2_grant_valid(outer_arb_io_in_2_grant_valid),
+ .io_in_2_grant_bits_addr_beat(outer_arb_io_in_2_grant_bits_addr_beat),
+ .io_in_2_grant_bits_client_xact_id(outer_arb_io_in_2_grant_bits_client_xact_id),
+ .io_in_2_grant_bits_manager_xact_id(outer_arb_io_in_2_grant_bits_manager_xact_id),
+ .io_in_2_grant_bits_is_builtin_type(outer_arb_io_in_2_grant_bits_is_builtin_type),
+ .io_in_2_grant_bits_g_type(outer_arb_io_in_2_grant_bits_g_type),
+ .io_in_2_grant_bits_data(outer_arb_io_in_2_grant_bits_data),
+ .io_in_3_acquire_ready(outer_arb_io_in_3_acquire_ready),
+ .io_in_3_acquire_valid(outer_arb_io_in_3_acquire_valid),
+ .io_in_3_acquire_bits_addr_block(outer_arb_io_in_3_acquire_bits_addr_block),
+ .io_in_3_acquire_bits_client_xact_id(outer_arb_io_in_3_acquire_bits_client_xact_id),
+ .io_in_3_acquire_bits_addr_beat(outer_arb_io_in_3_acquire_bits_addr_beat),
+ .io_in_3_acquire_bits_is_builtin_type(outer_arb_io_in_3_acquire_bits_is_builtin_type),
+ .io_in_3_acquire_bits_a_type(outer_arb_io_in_3_acquire_bits_a_type),
+ .io_in_3_acquire_bits_union(outer_arb_io_in_3_acquire_bits_union),
+ .io_in_3_acquire_bits_data(outer_arb_io_in_3_acquire_bits_data),
+ .io_in_3_grant_ready(outer_arb_io_in_3_grant_ready),
+ .io_in_3_grant_valid(outer_arb_io_in_3_grant_valid),
+ .io_in_3_grant_bits_addr_beat(outer_arb_io_in_3_grant_bits_addr_beat),
+ .io_in_3_grant_bits_client_xact_id(outer_arb_io_in_3_grant_bits_client_xact_id),
+ .io_in_3_grant_bits_manager_xact_id(outer_arb_io_in_3_grant_bits_manager_xact_id),
+ .io_in_3_grant_bits_is_builtin_type(outer_arb_io_in_3_grant_bits_is_builtin_type),
+ .io_in_3_grant_bits_g_type(outer_arb_io_in_3_grant_bits_g_type),
+ .io_in_3_grant_bits_data(outer_arb_io_in_3_grant_bits_data),
+ .io_in_4_acquire_ready(outer_arb_io_in_4_acquire_ready),
+ .io_in_4_acquire_valid(outer_arb_io_in_4_acquire_valid),
+ .io_in_4_acquire_bits_addr_block(outer_arb_io_in_4_acquire_bits_addr_block),
+ .io_in_4_acquire_bits_client_xact_id(outer_arb_io_in_4_acquire_bits_client_xact_id),
+ .io_in_4_acquire_bits_addr_beat(outer_arb_io_in_4_acquire_bits_addr_beat),
+ .io_in_4_acquire_bits_is_builtin_type(outer_arb_io_in_4_acquire_bits_is_builtin_type),
+ .io_in_4_acquire_bits_a_type(outer_arb_io_in_4_acquire_bits_a_type),
+ .io_in_4_acquire_bits_union(outer_arb_io_in_4_acquire_bits_union),
+ .io_in_4_acquire_bits_data(outer_arb_io_in_4_acquire_bits_data),
+ .io_in_4_grant_ready(outer_arb_io_in_4_grant_ready),
+ .io_in_4_grant_valid(outer_arb_io_in_4_grant_valid),
+ .io_in_4_grant_bits_addr_beat(outer_arb_io_in_4_grant_bits_addr_beat),
+ .io_in_4_grant_bits_client_xact_id(outer_arb_io_in_4_grant_bits_client_xact_id),
+ .io_in_4_grant_bits_manager_xact_id(outer_arb_io_in_4_grant_bits_manager_xact_id),
+ .io_in_4_grant_bits_is_builtin_type(outer_arb_io_in_4_grant_bits_is_builtin_type),
+ .io_in_4_grant_bits_g_type(outer_arb_io_in_4_grant_bits_g_type),
+ .io_in_4_grant_bits_data(outer_arb_io_in_4_grant_bits_data),
+ .io_in_5_acquire_ready(outer_arb_io_in_5_acquire_ready),
+ .io_in_5_acquire_valid(outer_arb_io_in_5_acquire_valid),
+ .io_in_5_acquire_bits_addr_block(outer_arb_io_in_5_acquire_bits_addr_block),
+ .io_in_5_acquire_bits_client_xact_id(outer_arb_io_in_5_acquire_bits_client_xact_id),
+ .io_in_5_acquire_bits_addr_beat(outer_arb_io_in_5_acquire_bits_addr_beat),
+ .io_in_5_acquire_bits_is_builtin_type(outer_arb_io_in_5_acquire_bits_is_builtin_type),
+ .io_in_5_acquire_bits_a_type(outer_arb_io_in_5_acquire_bits_a_type),
+ .io_in_5_acquire_bits_union(outer_arb_io_in_5_acquire_bits_union),
+ .io_in_5_acquire_bits_data(outer_arb_io_in_5_acquire_bits_data),
+ .io_in_5_grant_ready(outer_arb_io_in_5_grant_ready),
+ .io_in_5_grant_valid(outer_arb_io_in_5_grant_valid),
+ .io_in_5_grant_bits_addr_beat(outer_arb_io_in_5_grant_bits_addr_beat),
+ .io_in_5_grant_bits_client_xact_id(outer_arb_io_in_5_grant_bits_client_xact_id),
+ .io_in_5_grant_bits_manager_xact_id(outer_arb_io_in_5_grant_bits_manager_xact_id),
+ .io_in_5_grant_bits_is_builtin_type(outer_arb_io_in_5_grant_bits_is_builtin_type),
+ .io_in_5_grant_bits_g_type(outer_arb_io_in_5_grant_bits_g_type),
+ .io_in_5_grant_bits_data(outer_arb_io_in_5_grant_bits_data),
+ .io_in_6_acquire_ready(outer_arb_io_in_6_acquire_ready),
+ .io_in_6_acquire_valid(outer_arb_io_in_6_acquire_valid),
+ .io_in_6_acquire_bits_addr_block(outer_arb_io_in_6_acquire_bits_addr_block),
+ .io_in_6_acquire_bits_client_xact_id(outer_arb_io_in_6_acquire_bits_client_xact_id),
+ .io_in_6_acquire_bits_addr_beat(outer_arb_io_in_6_acquire_bits_addr_beat),
+ .io_in_6_acquire_bits_is_builtin_type(outer_arb_io_in_6_acquire_bits_is_builtin_type),
+ .io_in_6_acquire_bits_a_type(outer_arb_io_in_6_acquire_bits_a_type),
+ .io_in_6_acquire_bits_union(outer_arb_io_in_6_acquire_bits_union),
+ .io_in_6_acquire_bits_data(outer_arb_io_in_6_acquire_bits_data),
+ .io_in_6_grant_ready(outer_arb_io_in_6_grant_ready),
+ .io_in_6_grant_valid(outer_arb_io_in_6_grant_valid),
+ .io_in_6_grant_bits_addr_beat(outer_arb_io_in_6_grant_bits_addr_beat),
+ .io_in_6_grant_bits_client_xact_id(outer_arb_io_in_6_grant_bits_client_xact_id),
+ .io_in_6_grant_bits_manager_xact_id(outer_arb_io_in_6_grant_bits_manager_xact_id),
+ .io_in_6_grant_bits_is_builtin_type(outer_arb_io_in_6_grant_bits_is_builtin_type),
+ .io_in_6_grant_bits_g_type(outer_arb_io_in_6_grant_bits_g_type),
+ .io_in_6_grant_bits_data(outer_arb_io_in_6_grant_bits_data),
+ .io_in_7_acquire_ready(outer_arb_io_in_7_acquire_ready),
+ .io_in_7_acquire_valid(outer_arb_io_in_7_acquire_valid),
+ .io_in_7_acquire_bits_addr_block(outer_arb_io_in_7_acquire_bits_addr_block),
+ .io_in_7_acquire_bits_client_xact_id(outer_arb_io_in_7_acquire_bits_client_xact_id),
+ .io_in_7_acquire_bits_addr_beat(outer_arb_io_in_7_acquire_bits_addr_beat),
+ .io_in_7_acquire_bits_is_builtin_type(outer_arb_io_in_7_acquire_bits_is_builtin_type),
+ .io_in_7_acquire_bits_a_type(outer_arb_io_in_7_acquire_bits_a_type),
+ .io_in_7_acquire_bits_union(outer_arb_io_in_7_acquire_bits_union),
+ .io_in_7_acquire_bits_data(outer_arb_io_in_7_acquire_bits_data),
+ .io_in_7_grant_ready(outer_arb_io_in_7_grant_ready),
+ .io_in_7_grant_valid(outer_arb_io_in_7_grant_valid),
+ .io_in_7_grant_bits_addr_beat(outer_arb_io_in_7_grant_bits_addr_beat),
+ .io_in_7_grant_bits_client_xact_id(outer_arb_io_in_7_grant_bits_client_xact_id),
+ .io_in_7_grant_bits_manager_xact_id(outer_arb_io_in_7_grant_bits_manager_xact_id),
+ .io_in_7_grant_bits_is_builtin_type(outer_arb_io_in_7_grant_bits_is_builtin_type),
+ .io_in_7_grant_bits_g_type(outer_arb_io_in_7_grant_bits_g_type),
+ .io_in_7_grant_bits_data(outer_arb_io_in_7_grant_bits_data),
+ .io_out_acquire_ready(outer_arb_io_out_acquire_ready),
+ .io_out_acquire_valid(outer_arb_io_out_acquire_valid),
+ .io_out_acquire_bits_addr_block(outer_arb_io_out_acquire_bits_addr_block),
+ .io_out_acquire_bits_client_xact_id(outer_arb_io_out_acquire_bits_client_xact_id),
+ .io_out_acquire_bits_addr_beat(outer_arb_io_out_acquire_bits_addr_beat),
+ .io_out_acquire_bits_is_builtin_type(outer_arb_io_out_acquire_bits_is_builtin_type),
+ .io_out_acquire_bits_a_type(outer_arb_io_out_acquire_bits_a_type),
+ .io_out_acquire_bits_union(outer_arb_io_out_acquire_bits_union),
+ .io_out_acquire_bits_data(outer_arb_io_out_acquire_bits_data),
+ .io_out_grant_ready(outer_arb_io_out_grant_ready),
+ .io_out_grant_valid(outer_arb_io_out_grant_valid),
+ .io_out_grant_bits_addr_beat(outer_arb_io_out_grant_bits_addr_beat),
+ .io_out_grant_bits_client_xact_id(outer_arb_io_out_grant_bits_client_xact_id),
+ .io_out_grant_bits_manager_xact_id(outer_arb_io_out_grant_bits_manager_xact_id),
+ .io_out_grant_bits_is_builtin_type(outer_arb_io_out_grant_bits_is_builtin_type),
+ .io_out_grant_bits_g_type(outer_arb_io_out_grant_bits_g_type),
+ .io_out_grant_bits_data(outer_arb_io_out_grant_bits_data)
+ );
+ assign io_inner_acquire_ready = T_1263;
+ assign io_inner_grant_valid = T_2953_io_out_valid;
+ assign io_inner_grant_bits_addr_beat = io_outer_grant_bits_addr_beat;
+ assign io_inner_grant_bits_client_xact_id = T_2953_io_out_bits_client_xact_id;
+ assign io_inner_grant_bits_manager_xact_id = T_2953_io_out_bits_manager_xact_id;
+ assign io_inner_grant_bits_is_builtin_type = T_2953_io_out_bits_is_builtin_type;
+ assign io_inner_grant_bits_g_type = T_2953_io_out_bits_g_type;
+ assign io_inner_grant_bits_data = io_outer_grant_bits_data;
+ assign io_inner_grant_bits_client_id = T_2953_io_out_bits_client_id;
+ assign io_inner_finish_ready = GEN_2;
+ assign io_inner_probe_valid = T_2954_io_out_valid;
+ assign io_inner_probe_bits_addr_block = T_2954_io_out_bits_addr_block;
+ assign io_inner_probe_bits_p_type = T_2954_io_out_bits_p_type;
+ assign io_inner_probe_bits_client_id = T_2954_io_out_bits_client_id;
+ assign io_inner_release_ready = T_2171;
+ assign io_outer_acquire_valid = outer_arb_io_out_acquire_valid;
+ assign io_outer_acquire_bits_addr_block = outer_arb_io_out_acquire_bits_addr_block;
+ assign io_outer_acquire_bits_client_xact_id = outer_arb_io_out_acquire_bits_client_xact_id;
+ assign io_outer_acquire_bits_addr_beat = outer_arb_io_out_acquire_bits_addr_beat;
+ assign io_outer_acquire_bits_is_builtin_type = outer_arb_io_out_acquire_bits_is_builtin_type;
+ assign io_outer_acquire_bits_a_type = outer_arb_io_out_acquire_bits_a_type;
+ assign io_outer_acquire_bits_union = outer_arb_io_out_acquire_bits_union;
+ assign io_outer_acquire_bits_data = T_3159;
+ assign io_outer_grant_ready = outer_arb_io_out_grant_ready;
+ assign T_1060_clk = clk;
+ assign T_1060_reset = reset;
+ assign T_1060_io_inner_acquire_valid = T_1362;
+ assign T_1060_io_inner_acquire_bits_addr_block = io_inner_acquire_bits_addr_block;
+ assign T_1060_io_inner_acquire_bits_client_xact_id = io_inner_acquire_bits_client_xact_id;
+ assign T_1060_io_inner_acquire_bits_addr_beat = io_inner_acquire_bits_addr_beat;
+ assign T_1060_io_inner_acquire_bits_is_builtin_type = io_inner_acquire_bits_is_builtin_type;
+ assign T_1060_io_inner_acquire_bits_a_type = io_inner_acquire_bits_a_type;
+ assign T_1060_io_inner_acquire_bits_union = io_inner_acquire_bits_union;
+ assign T_1060_io_inner_acquire_bits_data = T_1356;
+ assign T_1060_io_inner_acquire_bits_client_id = io_inner_acquire_bits_client_id;
+ assign T_1060_io_inner_grant_ready = T_2953_io_in_0_ready;
+ assign T_1060_io_inner_finish_valid = T_2957;
+ assign T_1060_io_inner_finish_bits_manager_xact_id = io_inner_finish_bits_manager_xact_id;
+ assign T_1060_io_inner_probe_ready = T_2954_io_in_0_ready;
+ assign T_1060_io_inner_release_valid = T_2174;
+ assign T_1060_io_inner_release_bits_addr_beat = io_inner_release_bits_addr_beat;
+ assign T_1060_io_inner_release_bits_addr_block = io_inner_release_bits_addr_block;
+ assign T_1060_io_inner_release_bits_client_xact_id = io_inner_release_bits_client_xact_id;
+ assign T_1060_io_inner_release_bits_voluntary = io_inner_release_bits_voluntary;
+ assign T_1060_io_inner_release_bits_r_type = io_inner_release_bits_r_type;
+ assign T_1060_io_inner_release_bits_data = T_2267;
+ assign T_1060_io_inner_release_bits_client_id = io_inner_release_bits_client_id;
+ assign T_1060_io_incoherent_0 = io_incoherent_0;
+ assign T_1060_io_outer_acquire_ready = outer_arb_io_in_0_acquire_ready;
+ assign T_1060_io_outer_grant_valid = outer_arb_io_in_0_grant_valid;
+ assign T_1060_io_outer_grant_bits_addr_beat = outer_arb_io_in_0_grant_bits_addr_beat;
+ assign T_1060_io_outer_grant_bits_client_xact_id = outer_arb_io_in_0_grant_bits_client_xact_id;
+ assign T_1060_io_outer_grant_bits_manager_xact_id = outer_arb_io_in_0_grant_bits_manager_xact_id;
+ assign T_1060_io_outer_grant_bits_is_builtin_type = outer_arb_io_in_0_grant_bits_is_builtin_type;
+ assign T_1060_io_outer_grant_bits_g_type = outer_arb_io_in_0_grant_bits_g_type;
+ assign T_1060_io_outer_grant_bits_data = outer_arb_io_in_0_grant_bits_data;
+ assign T_1061_clk = clk;
+ assign T_1061_reset = reset;
+ assign T_1061_io_inner_acquire_valid = T_1461;
+ assign T_1061_io_inner_acquire_bits_addr_block = io_inner_acquire_bits_addr_block;
+ assign T_1061_io_inner_acquire_bits_client_xact_id = io_inner_acquire_bits_client_xact_id;
+ assign T_1061_io_inner_acquire_bits_addr_beat = io_inner_acquire_bits_addr_beat;
+ assign T_1061_io_inner_acquire_bits_is_builtin_type = io_inner_acquire_bits_is_builtin_type;
+ assign T_1061_io_inner_acquire_bits_a_type = io_inner_acquire_bits_a_type;
+ assign T_1061_io_inner_acquire_bits_union = io_inner_acquire_bits_union;
+ assign T_1061_io_inner_acquire_bits_data = T_1455;
+ assign T_1061_io_inner_acquire_bits_client_id = io_inner_acquire_bits_client_id;
+ assign T_1061_io_inner_grant_ready = T_2953_io_in_1_ready;
+ assign T_1061_io_inner_finish_valid = T_2960;
+ assign T_1061_io_inner_finish_bits_manager_xact_id = io_inner_finish_bits_manager_xact_id;
+ assign T_1061_io_inner_probe_ready = T_2954_io_in_1_ready;
+ assign T_1061_io_inner_release_valid = T_2270;
+ assign T_1061_io_inner_release_bits_addr_beat = io_inner_release_bits_addr_beat;
+ assign T_1061_io_inner_release_bits_addr_block = io_inner_release_bits_addr_block;
+ assign T_1061_io_inner_release_bits_client_xact_id = io_inner_release_bits_client_xact_id;
+ assign T_1061_io_inner_release_bits_voluntary = io_inner_release_bits_voluntary;
+ assign T_1061_io_inner_release_bits_r_type = io_inner_release_bits_r_type;
+ assign T_1061_io_inner_release_bits_data = T_2363;
+ assign T_1061_io_inner_release_bits_client_id = io_inner_release_bits_client_id;
+ assign T_1061_io_incoherent_0 = io_incoherent_0;
+ assign T_1061_io_outer_acquire_ready = outer_arb_io_in_1_acquire_ready;
+ assign T_1061_io_outer_grant_valid = outer_arb_io_in_1_grant_valid;
+ assign T_1061_io_outer_grant_bits_addr_beat = outer_arb_io_in_1_grant_bits_addr_beat;
+ assign T_1061_io_outer_grant_bits_client_xact_id = outer_arb_io_in_1_grant_bits_client_xact_id;
+ assign T_1061_io_outer_grant_bits_manager_xact_id = outer_arb_io_in_1_grant_bits_manager_xact_id;
+ assign T_1061_io_outer_grant_bits_is_builtin_type = outer_arb_io_in_1_grant_bits_is_builtin_type;
+ assign T_1061_io_outer_grant_bits_g_type = outer_arb_io_in_1_grant_bits_g_type;
+ assign T_1061_io_outer_grant_bits_data = outer_arb_io_in_1_grant_bits_data;
+ assign T_1062_clk = clk;
+ assign T_1062_reset = reset;
+ assign T_1062_io_inner_acquire_valid = T_1560;
+ assign T_1062_io_inner_acquire_bits_addr_block = io_inner_acquire_bits_addr_block;
+ assign T_1062_io_inner_acquire_bits_client_xact_id = io_inner_acquire_bits_client_xact_id;
+ assign T_1062_io_inner_acquire_bits_addr_beat = io_inner_acquire_bits_addr_beat;
+ assign T_1062_io_inner_acquire_bits_is_builtin_type = io_inner_acquire_bits_is_builtin_type;
+ assign T_1062_io_inner_acquire_bits_a_type = io_inner_acquire_bits_a_type;
+ assign T_1062_io_inner_acquire_bits_union = io_inner_acquire_bits_union;
+ assign T_1062_io_inner_acquire_bits_data = T_1554;
+ assign T_1062_io_inner_acquire_bits_client_id = io_inner_acquire_bits_client_id;
+ assign T_1062_io_inner_grant_ready = T_2953_io_in_2_ready;
+ assign T_1062_io_inner_finish_valid = T_2963;
+ assign T_1062_io_inner_finish_bits_manager_xact_id = io_inner_finish_bits_manager_xact_id;
+ assign T_1062_io_inner_probe_ready = T_2954_io_in_2_ready;
+ assign T_1062_io_inner_release_valid = T_2366;
+ assign T_1062_io_inner_release_bits_addr_beat = io_inner_release_bits_addr_beat;
+ assign T_1062_io_inner_release_bits_addr_block = io_inner_release_bits_addr_block;
+ assign T_1062_io_inner_release_bits_client_xact_id = io_inner_release_bits_client_xact_id;
+ assign T_1062_io_inner_release_bits_voluntary = io_inner_release_bits_voluntary;
+ assign T_1062_io_inner_release_bits_r_type = io_inner_release_bits_r_type;
+ assign T_1062_io_inner_release_bits_data = T_2459;
+ assign T_1062_io_inner_release_bits_client_id = io_inner_release_bits_client_id;
+ assign T_1062_io_incoherent_0 = io_incoherent_0;
+ assign T_1062_io_outer_acquire_ready = outer_arb_io_in_2_acquire_ready;
+ assign T_1062_io_outer_grant_valid = outer_arb_io_in_2_grant_valid;
+ assign T_1062_io_outer_grant_bits_addr_beat = outer_arb_io_in_2_grant_bits_addr_beat;
+ assign T_1062_io_outer_grant_bits_client_xact_id = outer_arb_io_in_2_grant_bits_client_xact_id;
+ assign T_1062_io_outer_grant_bits_manager_xact_id = outer_arb_io_in_2_grant_bits_manager_xact_id;
+ assign T_1062_io_outer_grant_bits_is_builtin_type = outer_arb_io_in_2_grant_bits_is_builtin_type;
+ assign T_1062_io_outer_grant_bits_g_type = outer_arb_io_in_2_grant_bits_g_type;
+ assign T_1062_io_outer_grant_bits_data = outer_arb_io_in_2_grant_bits_data;
+ assign T_1063_clk = clk;
+ assign T_1063_reset = reset;
+ assign T_1063_io_inner_acquire_valid = T_1659;
+ assign T_1063_io_inner_acquire_bits_addr_block = io_inner_acquire_bits_addr_block;
+ assign T_1063_io_inner_acquire_bits_client_xact_id = io_inner_acquire_bits_client_xact_id;
+ assign T_1063_io_inner_acquire_bits_addr_beat = io_inner_acquire_bits_addr_beat;
+ assign T_1063_io_inner_acquire_bits_is_builtin_type = io_inner_acquire_bits_is_builtin_type;
+ assign T_1063_io_inner_acquire_bits_a_type = io_inner_acquire_bits_a_type;
+ assign T_1063_io_inner_acquire_bits_union = io_inner_acquire_bits_union;
+ assign T_1063_io_inner_acquire_bits_data = T_1653;
+ assign T_1063_io_inner_acquire_bits_client_id = io_inner_acquire_bits_client_id;
+ assign T_1063_io_inner_grant_ready = T_2953_io_in_3_ready;
+ assign T_1063_io_inner_finish_valid = T_2966;
+ assign T_1063_io_inner_finish_bits_manager_xact_id = io_inner_finish_bits_manager_xact_id;
+ assign T_1063_io_inner_probe_ready = T_2954_io_in_3_ready;
+ assign T_1063_io_inner_release_valid = T_2462;
+ assign T_1063_io_inner_release_bits_addr_beat = io_inner_release_bits_addr_beat;
+ assign T_1063_io_inner_release_bits_addr_block = io_inner_release_bits_addr_block;
+ assign T_1063_io_inner_release_bits_client_xact_id = io_inner_release_bits_client_xact_id;
+ assign T_1063_io_inner_release_bits_voluntary = io_inner_release_bits_voluntary;
+ assign T_1063_io_inner_release_bits_r_type = io_inner_release_bits_r_type;
+ assign T_1063_io_inner_release_bits_data = T_2555;
+ assign T_1063_io_inner_release_bits_client_id = io_inner_release_bits_client_id;
+ assign T_1063_io_incoherent_0 = io_incoherent_0;
+ assign T_1063_io_outer_acquire_ready = outer_arb_io_in_3_acquire_ready;
+ assign T_1063_io_outer_grant_valid = outer_arb_io_in_3_grant_valid;
+ assign T_1063_io_outer_grant_bits_addr_beat = outer_arb_io_in_3_grant_bits_addr_beat;
+ assign T_1063_io_outer_grant_bits_client_xact_id = outer_arb_io_in_3_grant_bits_client_xact_id;
+ assign T_1063_io_outer_grant_bits_manager_xact_id = outer_arb_io_in_3_grant_bits_manager_xact_id;
+ assign T_1063_io_outer_grant_bits_is_builtin_type = outer_arb_io_in_3_grant_bits_is_builtin_type;
+ assign T_1063_io_outer_grant_bits_g_type = outer_arb_io_in_3_grant_bits_g_type;
+ assign T_1063_io_outer_grant_bits_data = outer_arb_io_in_3_grant_bits_data;
+ assign T_1064_clk = clk;
+ assign T_1064_reset = reset;
+ assign T_1064_io_inner_acquire_valid = T_1758;
+ assign T_1064_io_inner_acquire_bits_addr_block = io_inner_acquire_bits_addr_block;
+ assign T_1064_io_inner_acquire_bits_client_xact_id = io_inner_acquire_bits_client_xact_id;
+ assign T_1064_io_inner_acquire_bits_addr_beat = io_inner_acquire_bits_addr_beat;
+ assign T_1064_io_inner_acquire_bits_is_builtin_type = io_inner_acquire_bits_is_builtin_type;
+ assign T_1064_io_inner_acquire_bits_a_type = io_inner_acquire_bits_a_type;
+ assign T_1064_io_inner_acquire_bits_union = io_inner_acquire_bits_union;
+ assign T_1064_io_inner_acquire_bits_data = T_1752;
+ assign T_1064_io_inner_acquire_bits_client_id = io_inner_acquire_bits_client_id;
+ assign T_1064_io_inner_grant_ready = T_2953_io_in_4_ready;
+ assign T_1064_io_inner_finish_valid = T_2969;
+ assign T_1064_io_inner_finish_bits_manager_xact_id = io_inner_finish_bits_manager_xact_id;
+ assign T_1064_io_inner_probe_ready = T_2954_io_in_4_ready;
+ assign T_1064_io_inner_release_valid = T_2558;
+ assign T_1064_io_inner_release_bits_addr_beat = io_inner_release_bits_addr_beat;
+ assign T_1064_io_inner_release_bits_addr_block = io_inner_release_bits_addr_block;
+ assign T_1064_io_inner_release_bits_client_xact_id = io_inner_release_bits_client_xact_id;
+ assign T_1064_io_inner_release_bits_voluntary = io_inner_release_bits_voluntary;
+ assign T_1064_io_inner_release_bits_r_type = io_inner_release_bits_r_type;
+ assign T_1064_io_inner_release_bits_data = T_2651;
+ assign T_1064_io_inner_release_bits_client_id = io_inner_release_bits_client_id;
+ assign T_1064_io_incoherent_0 = io_incoherent_0;
+ assign T_1064_io_outer_acquire_ready = outer_arb_io_in_4_acquire_ready;
+ assign T_1064_io_outer_grant_valid = outer_arb_io_in_4_grant_valid;
+ assign T_1064_io_outer_grant_bits_addr_beat = outer_arb_io_in_4_grant_bits_addr_beat;
+ assign T_1064_io_outer_grant_bits_client_xact_id = outer_arb_io_in_4_grant_bits_client_xact_id;
+ assign T_1064_io_outer_grant_bits_manager_xact_id = outer_arb_io_in_4_grant_bits_manager_xact_id;
+ assign T_1064_io_outer_grant_bits_is_builtin_type = outer_arb_io_in_4_grant_bits_is_builtin_type;
+ assign T_1064_io_outer_grant_bits_g_type = outer_arb_io_in_4_grant_bits_g_type;
+ assign T_1064_io_outer_grant_bits_data = outer_arb_io_in_4_grant_bits_data;
+ assign T_1065_clk = clk;
+ assign T_1065_reset = reset;
+ assign T_1065_io_inner_acquire_valid = T_1857;
+ assign T_1065_io_inner_acquire_bits_addr_block = io_inner_acquire_bits_addr_block;
+ assign T_1065_io_inner_acquire_bits_client_xact_id = io_inner_acquire_bits_client_xact_id;
+ assign T_1065_io_inner_acquire_bits_addr_beat = io_inner_acquire_bits_addr_beat;
+ assign T_1065_io_inner_acquire_bits_is_builtin_type = io_inner_acquire_bits_is_builtin_type;
+ assign T_1065_io_inner_acquire_bits_a_type = io_inner_acquire_bits_a_type;
+ assign T_1065_io_inner_acquire_bits_union = io_inner_acquire_bits_union;
+ assign T_1065_io_inner_acquire_bits_data = T_1851;
+ assign T_1065_io_inner_acquire_bits_client_id = io_inner_acquire_bits_client_id;
+ assign T_1065_io_inner_grant_ready = T_2953_io_in_5_ready;
+ assign T_1065_io_inner_finish_valid = T_2972;
+ assign T_1065_io_inner_finish_bits_manager_xact_id = io_inner_finish_bits_manager_xact_id;
+ assign T_1065_io_inner_probe_ready = T_2954_io_in_5_ready;
+ assign T_1065_io_inner_release_valid = T_2654;
+ assign T_1065_io_inner_release_bits_addr_beat = io_inner_release_bits_addr_beat;
+ assign T_1065_io_inner_release_bits_addr_block = io_inner_release_bits_addr_block;
+ assign T_1065_io_inner_release_bits_client_xact_id = io_inner_release_bits_client_xact_id;
+ assign T_1065_io_inner_release_bits_voluntary = io_inner_release_bits_voluntary;
+ assign T_1065_io_inner_release_bits_r_type = io_inner_release_bits_r_type;
+ assign T_1065_io_inner_release_bits_data = T_2747;
+ assign T_1065_io_inner_release_bits_client_id = io_inner_release_bits_client_id;
+ assign T_1065_io_incoherent_0 = io_incoherent_0;
+ assign T_1065_io_outer_acquire_ready = outer_arb_io_in_5_acquire_ready;
+ assign T_1065_io_outer_grant_valid = outer_arb_io_in_5_grant_valid;
+ assign T_1065_io_outer_grant_bits_addr_beat = outer_arb_io_in_5_grant_bits_addr_beat;
+ assign T_1065_io_outer_grant_bits_client_xact_id = outer_arb_io_in_5_grant_bits_client_xact_id;
+ assign T_1065_io_outer_grant_bits_manager_xact_id = outer_arb_io_in_5_grant_bits_manager_xact_id;
+ assign T_1065_io_outer_grant_bits_is_builtin_type = outer_arb_io_in_5_grant_bits_is_builtin_type;
+ assign T_1065_io_outer_grant_bits_g_type = outer_arb_io_in_5_grant_bits_g_type;
+ assign T_1065_io_outer_grant_bits_data = outer_arb_io_in_5_grant_bits_data;
+ assign T_1066_clk = clk;
+ assign T_1066_reset = reset;
+ assign T_1066_io_inner_acquire_valid = T_1956;
+ assign T_1066_io_inner_acquire_bits_addr_block = io_inner_acquire_bits_addr_block;
+ assign T_1066_io_inner_acquire_bits_client_xact_id = io_inner_acquire_bits_client_xact_id;
+ assign T_1066_io_inner_acquire_bits_addr_beat = io_inner_acquire_bits_addr_beat;
+ assign T_1066_io_inner_acquire_bits_is_builtin_type = io_inner_acquire_bits_is_builtin_type;
+ assign T_1066_io_inner_acquire_bits_a_type = io_inner_acquire_bits_a_type;
+ assign T_1066_io_inner_acquire_bits_union = io_inner_acquire_bits_union;
+ assign T_1066_io_inner_acquire_bits_data = T_1950;
+ assign T_1066_io_inner_acquire_bits_client_id = io_inner_acquire_bits_client_id;
+ assign T_1066_io_inner_grant_ready = T_2953_io_in_6_ready;
+ assign T_1066_io_inner_finish_valid = T_2975;
+ assign T_1066_io_inner_finish_bits_manager_xact_id = io_inner_finish_bits_manager_xact_id;
+ assign T_1066_io_inner_probe_ready = T_2954_io_in_6_ready;
+ assign T_1066_io_inner_release_valid = T_2750;
+ assign T_1066_io_inner_release_bits_addr_beat = io_inner_release_bits_addr_beat;
+ assign T_1066_io_inner_release_bits_addr_block = io_inner_release_bits_addr_block;
+ assign T_1066_io_inner_release_bits_client_xact_id = io_inner_release_bits_client_xact_id;
+ assign T_1066_io_inner_release_bits_voluntary = io_inner_release_bits_voluntary;
+ assign T_1066_io_inner_release_bits_r_type = io_inner_release_bits_r_type;
+ assign T_1066_io_inner_release_bits_data = T_2843;
+ assign T_1066_io_inner_release_bits_client_id = io_inner_release_bits_client_id;
+ assign T_1066_io_incoherent_0 = io_incoherent_0;
+ assign T_1066_io_outer_acquire_ready = outer_arb_io_in_6_acquire_ready;
+ assign T_1066_io_outer_grant_valid = outer_arb_io_in_6_grant_valid;
+ assign T_1066_io_outer_grant_bits_addr_beat = outer_arb_io_in_6_grant_bits_addr_beat;
+ assign T_1066_io_outer_grant_bits_client_xact_id = outer_arb_io_in_6_grant_bits_client_xact_id;
+ assign T_1066_io_outer_grant_bits_manager_xact_id = outer_arb_io_in_6_grant_bits_manager_xact_id;
+ assign T_1066_io_outer_grant_bits_is_builtin_type = outer_arb_io_in_6_grant_bits_is_builtin_type;
+ assign T_1066_io_outer_grant_bits_g_type = outer_arb_io_in_6_grant_bits_g_type;
+ assign T_1066_io_outer_grant_bits_data = outer_arb_io_in_6_grant_bits_data;
+ assign T_1067_clk = clk;
+ assign T_1067_reset = reset;
+ assign T_1067_io_inner_acquire_valid = T_2055;
+ assign T_1067_io_inner_acquire_bits_addr_block = io_inner_acquire_bits_addr_block;
+ assign T_1067_io_inner_acquire_bits_client_xact_id = io_inner_acquire_bits_client_xact_id;
+ assign T_1067_io_inner_acquire_bits_addr_beat = io_inner_acquire_bits_addr_beat;
+ assign T_1067_io_inner_acquire_bits_is_builtin_type = io_inner_acquire_bits_is_builtin_type;
+ assign T_1067_io_inner_acquire_bits_a_type = io_inner_acquire_bits_a_type;
+ assign T_1067_io_inner_acquire_bits_union = io_inner_acquire_bits_union;
+ assign T_1067_io_inner_acquire_bits_data = T_2049;
+ assign T_1067_io_inner_acquire_bits_client_id = io_inner_acquire_bits_client_id;
+ assign T_1067_io_inner_grant_ready = T_2953_io_in_7_ready;
+ assign T_1067_io_inner_finish_valid = T_2978;
+ assign T_1067_io_inner_finish_bits_manager_xact_id = io_inner_finish_bits_manager_xact_id;
+ assign T_1067_io_inner_probe_ready = T_2954_io_in_7_ready;
+ assign T_1067_io_inner_release_valid = T_2846;
+ assign T_1067_io_inner_release_bits_addr_beat = io_inner_release_bits_addr_beat;
+ assign T_1067_io_inner_release_bits_addr_block = io_inner_release_bits_addr_block;
+ assign T_1067_io_inner_release_bits_client_xact_id = io_inner_release_bits_client_xact_id;
+ assign T_1067_io_inner_release_bits_voluntary = io_inner_release_bits_voluntary;
+ assign T_1067_io_inner_release_bits_r_type = io_inner_release_bits_r_type;
+ assign T_1067_io_inner_release_bits_data = T_2939;
+ assign T_1067_io_inner_release_bits_client_id = io_inner_release_bits_client_id;
+ assign T_1067_io_incoherent_0 = io_incoherent_0;
+ assign T_1067_io_outer_acquire_ready = outer_arb_io_in_7_acquire_ready;
+ assign T_1067_io_outer_grant_valid = outer_arb_io_in_7_grant_valid;
+ assign T_1067_io_outer_grant_bits_addr_beat = outer_arb_io_in_7_grant_bits_addr_beat;
+ assign T_1067_io_outer_grant_bits_client_xact_id = outer_arb_io_in_7_grant_bits_client_xact_id;
+ assign T_1067_io_outer_grant_bits_manager_xact_id = outer_arb_io_in_7_grant_bits_manager_xact_id;
+ assign T_1067_io_outer_grant_bits_is_builtin_type = outer_arb_io_in_7_grant_bits_is_builtin_type;
+ assign T_1067_io_outer_grant_bits_g_type = outer_arb_io_in_7_grant_bits_g_type;
+ assign T_1067_io_outer_grant_bits_data = outer_arb_io_in_7_grant_bits_data;
+ assign T_1085 = ~ sdq_val;
+ assign T_1086 = T_1085[0];
+ assign T_1087 = T_1085[1];
+ assign T_1088 = T_1085[2];
+ assign T_1089 = T_1085[3];
+ assign T_1091_0 = T_1086;
+ assign T_1091_1 = T_1087;
+ assign T_1091_2 = T_1088;
+ assign T_1091_3 = T_1089;
+ assign T_1101 = T_1091_2 ? 2'h2 : 2'h3;
+ assign T_1102 = T_1091_1 ? 1'h1 : T_1101;
+ assign sdq_alloc_id = T_1091_0 ? 1'h0 : T_1102;
+ assign T_1104 = ~ sdq_val;
+ assign T_1106 = T_1104 == 1'h0;
+ assign sdq_rdy = T_1106 == 1'h0;
+ assign T_1109 = io_inner_acquire_ready & io_inner_acquire_valid;
+ assign T_1114_0 = 3'h2;
+ assign T_1114_1 = 3'h3;
+ assign T_1114_2 = 3'h4;
+ assign T_1119 = T_1114_0 == io_inner_acquire_bits_a_type;
+ assign T_1120 = T_1114_1 == io_inner_acquire_bits_a_type;
+ assign T_1121 = T_1114_2 == io_inner_acquire_bits_a_type;
+ assign T_1123 = 1'h0 | T_1119;
+ assign T_1124 = T_1123 | T_1120;
+ assign T_1125 = T_1124 | T_1121;
+ assign T_1126 = io_inner_acquire_bits_is_builtin_type & T_1125;
+ assign sdq_enq = T_1109 & T_1126;
+ assign GEN_0 = io_inner_acquire_bits_data;
+ assign T_1130_0 = T_1060_io_has_acquire_conflict;
+ assign T_1130_1 = T_1061_io_has_acquire_conflict;
+ assign T_1130_2 = T_1062_io_has_acquire_conflict;
+ assign T_1130_3 = T_1063_io_has_acquire_conflict;
+ assign T_1130_4 = T_1064_io_has_acquire_conflict;
+ assign T_1130_5 = T_1065_io_has_acquire_conflict;
+ assign T_1130_6 = T_1066_io_has_acquire_conflict;
+ assign T_1130_7 = T_1067_io_has_acquire_conflict;
+ assign T_1140 = {T_1130_7,T_1130_6};
+ assign T_1141 = {T_1130_5,T_1130_4};
+ assign T_1142 = {T_1140,T_1141};
+ assign T_1143 = {T_1130_3,T_1130_2};
+ assign T_1144 = {T_1130_1,T_1130_0};
+ assign T_1145 = {T_1143,T_1144};
+ assign acquireConflicts = {T_1142,T_1145};
+ assign T_1148_0 = T_1060_io_has_acquire_match;
+ assign T_1148_1 = T_1061_io_has_acquire_match;
+ assign T_1148_2 = T_1062_io_has_acquire_match;
+ assign T_1148_3 = T_1063_io_has_acquire_match;
+ assign T_1148_4 = T_1064_io_has_acquire_match;
+ assign T_1148_5 = T_1065_io_has_acquire_match;
+ assign T_1148_6 = T_1066_io_has_acquire_match;
+ assign T_1148_7 = T_1067_io_has_acquire_match;
+ assign T_1158 = {T_1148_7,T_1148_6};
+ assign T_1159 = {T_1148_5,T_1148_4};
+ assign T_1160 = {T_1158,T_1159};
+ assign T_1161 = {T_1148_3,T_1148_2};
+ assign T_1162 = {T_1148_1,T_1148_0};
+ assign T_1163 = {T_1161,T_1162};
+ assign acquireMatches = {T_1160,T_1163};
+ assign T_1166_0 = T_1060_io_inner_acquire_ready;
+ assign T_1166_1 = T_1061_io_inner_acquire_ready;
+ assign T_1166_2 = T_1062_io_inner_acquire_ready;
+ assign T_1166_3 = T_1063_io_inner_acquire_ready;
+ assign T_1166_4 = T_1064_io_inner_acquire_ready;
+ assign T_1166_5 = T_1065_io_inner_acquire_ready;
+ assign T_1166_6 = T_1066_io_inner_acquire_ready;
+ assign T_1166_7 = T_1067_io_inner_acquire_ready;
+ assign T_1176 = {T_1166_7,T_1166_6};
+ assign T_1177 = {T_1166_5,T_1166_4};
+ assign T_1178 = {T_1176,T_1177};
+ assign T_1179 = {T_1166_3,T_1166_2};
+ assign T_1180 = {T_1166_1,T_1166_0};
+ assign T_1181 = {T_1179,T_1180};
+ assign acquireReadys = {T_1178,T_1181};
+ assign T_1184 = acquireMatches != 1'h0;
+ assign T_1185 = acquireMatches[0];
+ assign T_1186 = acquireMatches[1];
+ assign T_1187 = acquireMatches[2];
+ assign T_1188 = acquireMatches[3];
+ assign T_1189 = acquireMatches[4];
+ assign T_1190 = acquireMatches[5];
+ assign T_1191 = acquireMatches[6];
+ assign T_1192 = acquireMatches[7];
+ assign T_1194_0 = T_1185;
+ assign T_1194_1 = T_1186;
+ assign T_1194_2 = T_1187;
+ assign T_1194_3 = T_1188;
+ assign T_1194_4 = T_1189;
+ assign T_1194_5 = T_1190;
+ assign T_1194_6 = T_1191;
+ assign T_1194_7 = T_1192;
+ assign T_1212 = T_1194_6 ? 3'h6 : 3'h7;
+ assign T_1213 = T_1194_5 ? 3'h5 : T_1212;
+ assign T_1214 = T_1194_4 ? 3'h4 : T_1213;
+ assign T_1215 = T_1194_3 ? 2'h3 : T_1214;
+ assign T_1216 = T_1194_2 ? 2'h2 : T_1215;
+ assign T_1217 = T_1194_1 ? 1'h1 : T_1216;
+ assign T_1218 = T_1194_0 ? 1'h0 : T_1217;
+ assign T_1219 = acquireReadys[0];
+ assign T_1220 = acquireReadys[1];
+ assign T_1221 = acquireReadys[2];
+ assign T_1222 = acquireReadys[3];
+ assign T_1223 = acquireReadys[4];
+ assign T_1224 = acquireReadys[5];
+ assign T_1225 = acquireReadys[6];
+ assign T_1226 = acquireReadys[7];
+ assign T_1228_0 = T_1219;
+ assign T_1228_1 = T_1220;
+ assign T_1228_2 = T_1221;
+ assign T_1228_3 = T_1222;
+ assign T_1228_4 = T_1223;
+ assign T_1228_5 = T_1224;
+ assign T_1228_6 = T_1225;
+ assign T_1228_7 = T_1226;
+ assign T_1246 = T_1228_6 ? 3'h6 : 3'h7;
+ assign T_1247 = T_1228_5 ? 3'h5 : T_1246;
+ assign T_1248 = T_1228_4 ? 3'h4 : T_1247;
+ assign T_1249 = T_1228_3 ? 2'h3 : T_1248;
+ assign T_1250 = T_1228_2 ? 2'h2 : T_1249;
+ assign T_1251 = T_1228_1 ? 1'h1 : T_1250;
+ assign T_1252 = T_1228_0 ? 1'h0 : T_1251;
+ assign acquire_idx = T_1184 ? T_1218 : T_1252;
+ assign T_1255 = acquireConflicts != 1'h0;
+ assign T_1257 = sdq_rdy == 1'h0;
+ assign block_acquires = T_1255 | T_1257;
+ assign T_1260 = acquireReadys != 1'h0;
+ assign T_1262 = block_acquires == 1'h0;
+ assign T_1263 = T_1260 & T_1262;
+ assign T_1310_idx = sdq_alloc_id;
+ assign T_1310_loc = 1'h0;
+ assign T_1356 = {T_1310_idx,T_1310_loc};
+ assign T_1358 = block_acquires == 1'h0;
+ assign T_1359 = io_inner_acquire_valid & T_1358;
+ assign T_1361 = acquire_idx == 1'h0;
+ assign T_1362 = T_1359 & T_1361;
+ assign T_1409_idx = sdq_alloc_id;
+ assign T_1409_loc = 1'h0;
+ assign T_1455 = {T_1409_idx,T_1409_loc};
+ assign T_1457 = block_acquires == 1'h0;
+ assign T_1458 = io_inner_acquire_valid & T_1457;
+ assign T_1460 = acquire_idx == 1'h1;
+ assign T_1461 = T_1458 & T_1460;
+ assign T_1508_idx = sdq_alloc_id;
+ assign T_1508_loc = 1'h0;
+ assign T_1554 = {T_1508_idx,T_1508_loc};
+ assign T_1556 = block_acquires == 1'h0;
+ assign T_1557 = io_inner_acquire_valid & T_1556;
+ assign T_1559 = acquire_idx == 2'h2;
+ assign T_1560 = T_1557 & T_1559;
+ assign T_1607_idx = sdq_alloc_id;
+ assign T_1607_loc = 1'h0;
+ assign T_1653 = {T_1607_idx,T_1607_loc};
+ assign T_1655 = block_acquires == 1'h0;
+ assign T_1656 = io_inner_acquire_valid & T_1655;
+ assign T_1658 = acquire_idx == 2'h3;
+ assign T_1659 = T_1656 & T_1658;
+ assign T_1706_idx = sdq_alloc_id;
+ assign T_1706_loc = 1'h0;
+ assign T_1752 = {T_1706_idx,T_1706_loc};
+ assign T_1754 = block_acquires == 1'h0;
+ assign T_1755 = io_inner_acquire_valid & T_1754;
+ assign T_1757 = acquire_idx == 3'h4;
+ assign T_1758 = T_1755 & T_1757;
+ assign T_1805_idx = sdq_alloc_id;
+ assign T_1805_loc = 1'h0;
+ assign T_1851 = {T_1805_idx,T_1805_loc};
+ assign T_1853 = block_acquires == 1'h0;
+ assign T_1854 = io_inner_acquire_valid & T_1853;
+ assign T_1856 = acquire_idx == 3'h5;
+ assign T_1857 = T_1854 & T_1856;
+ assign T_1904_idx = sdq_alloc_id;
+ assign T_1904_loc = 1'h0;
+ assign T_1950 = {T_1904_idx,T_1904_loc};
+ assign T_1952 = block_acquires == 1'h0;
+ assign T_1953 = io_inner_acquire_valid & T_1952;
+ assign T_1955 = acquire_idx == 3'h6;
+ assign T_1956 = T_1953 & T_1955;
+ assign T_2003_idx = sdq_alloc_id;
+ assign T_2003_loc = 1'h0;
+ assign T_2049 = {T_2003_idx,T_2003_loc};
+ assign T_2051 = block_acquires == 1'h0;
+ assign T_2052 = io_inner_acquire_valid & T_2051;
+ assign T_2054 = acquire_idx == 3'h7;
+ assign T_2055 = T_2052 & T_2054;
+ assign T_2056 = io_inner_release_ready & io_inner_release_valid;
+ assign T_2057 = T_2056 & io_inner_release_bits_voluntary;
+ assign T_2059_0 = 1'h0;
+ assign T_2059_1 = 1'h1;
+ assign T_2059_2 = 2'h2;
+ assign T_2064 = T_2059_0 == io_inner_release_bits_r_type;
+ assign T_2065 = T_2059_1 == io_inner_release_bits_r_type;
+ assign T_2066 = T_2059_2 == io_inner_release_bits_r_type;
+ assign T_2068 = 1'h0 | T_2064;
+ assign T_2069 = T_2068 | T_2065;
+ assign T_2070 = T_2069 | T_2066;
+ assign vwbdq_enq = T_2057 & T_2070;
+ assign T_2075 = rel_data_cnt == 2'h3;
+ assign T_2077 = 1'h0 & T_2075;
+ assign T_2080 = rel_data_cnt + 1'h1;
+ assign T_2081 = T_2080[1:0];
+ assign T_2082 = T_2077 ? 1'h0 : T_2081;
+ assign rel_data_done = vwbdq_enq & T_2075;
+ assign GEN_1 = io_inner_release_bits_data;
+ assign T_2101_0 = T_1060_io_inner_release_ready;
+ assign T_2101_1 = T_1061_io_inner_release_ready;
+ assign T_2101_2 = T_1062_io_inner_release_ready;
+ assign T_2101_3 = T_1063_io_inner_release_ready;
+ assign T_2101_4 = T_1064_io_inner_release_ready;
+ assign T_2101_5 = T_1065_io_inner_release_ready;
+ assign T_2101_6 = T_1066_io_inner_release_ready;
+ assign T_2101_7 = T_1067_io_inner_release_ready;
+ assign T_2111 = {T_2101_7,T_2101_6};
+ assign T_2112 = {T_2101_5,T_2101_4};
+ assign T_2113 = {T_2111,T_2112};
+ assign T_2114 = {T_2101_3,T_2101_2};
+ assign T_2115 = {T_2101_1,T_2101_0};
+ assign T_2116 = {T_2114,T_2115};
+ assign releaseReadys = {T_2113,T_2116};
+ assign T_2119_0 = T_1060_io_has_release_match;
+ assign T_2119_1 = T_1061_io_has_release_match;
+ assign T_2119_2 = T_1062_io_has_release_match;
+ assign T_2119_3 = T_1063_io_has_release_match;
+ assign T_2119_4 = T_1064_io_has_release_match;
+ assign T_2119_5 = T_1065_io_has_release_match;
+ assign T_2119_6 = T_1066_io_has_release_match;
+ assign T_2119_7 = T_1067_io_has_release_match;
+ assign T_2129 = {T_2119_7,T_2119_6};
+ assign T_2130 = {T_2119_5,T_2119_4};
+ assign T_2131 = {T_2129,T_2130};
+ assign T_2132 = {T_2119_3,T_2119_2};
+ assign T_2133 = {T_2119_1,T_2119_0};
+ assign T_2134 = {T_2132,T_2133};
+ assign releaseMatches = {T_2131,T_2134};
+ assign T_2136 = releaseMatches[0];
+ assign T_2137 = releaseMatches[1];
+ assign T_2138 = releaseMatches[2];
+ assign T_2139 = releaseMatches[3];
+ assign T_2140 = releaseMatches[4];
+ assign T_2141 = releaseMatches[5];
+ assign T_2142 = releaseMatches[6];
+ assign T_2143 = releaseMatches[7];
+ assign T_2145_0 = T_2136;
+ assign T_2145_1 = T_2137;
+ assign T_2145_2 = T_2138;
+ assign T_2145_3 = T_2139;
+ assign T_2145_4 = T_2140;
+ assign T_2145_5 = T_2141;
+ assign T_2145_6 = T_2142;
+ assign T_2145_7 = T_2143;
+ assign T_2163 = T_2145_6 ? 3'h6 : 3'h7;
+ assign T_2164 = T_2145_5 ? 3'h5 : T_2163;
+ assign T_2165 = T_2145_4 ? 3'h4 : T_2164;
+ assign T_2166 = T_2145_3 ? 2'h3 : T_2165;
+ assign T_2167 = T_2145_2 ? 2'h2 : T_2166;
+ assign T_2168 = T_2145_1 ? 1'h1 : T_2167;
+ assign release_idx = T_2145_0 ? 1'h0 : T_2168;
+ assign T_2170 = releaseReadys >> release_idx;
+ assign T_2171 = T_2170[0];
+ assign T_2173 = release_idx == 1'h0;
+ assign T_2174 = io_inner_release_valid & T_2173;
+ assign T_2221_idx = rel_data_cnt;
+ assign T_2221_loc = 1'h1;
+ assign T_2267 = {T_2221_idx,T_2221_loc};
+ assign T_2269 = release_idx == 1'h1;
+ assign T_2270 = io_inner_release_valid & T_2269;
+ assign T_2317_idx = rel_data_cnt;
+ assign T_2317_loc = 2'h2;
+ assign T_2363 = {T_2317_idx,T_2317_loc};
+ assign T_2365 = release_idx == 2'h2;
+ assign T_2366 = io_inner_release_valid & T_2365;
+ assign T_2413_idx = rel_data_cnt;
+ assign T_2413_loc = 2'h2;
+ assign T_2459 = {T_2413_idx,T_2413_loc};
+ assign T_2461 = release_idx == 2'h3;
+ assign T_2462 = io_inner_release_valid & T_2461;
+ assign T_2509_idx = rel_data_cnt;
+ assign T_2509_loc = 2'h2;
+ assign T_2555 = {T_2509_idx,T_2509_loc};
+ assign T_2557 = release_idx == 3'h4;
+ assign T_2558 = io_inner_release_valid & T_2557;
+ assign T_2605_idx = rel_data_cnt;
+ assign T_2605_loc = 2'h2;
+ assign T_2651 = {T_2605_idx,T_2605_loc};
+ assign T_2653 = release_idx == 3'h5;
+ assign T_2654 = io_inner_release_valid & T_2653;
+ assign T_2701_idx = rel_data_cnt;
+ assign T_2701_loc = 2'h2;
+ assign T_2747 = {T_2701_idx,T_2701_loc};
+ assign T_2749 = release_idx == 3'h6;
+ assign T_2750 = io_inner_release_valid & T_2749;
+ assign T_2797_idx = rel_data_cnt;
+ assign T_2797_loc = 2'h2;
+ assign T_2843 = {T_2797_idx,T_2797_loc};
+ assign T_2845 = release_idx == 3'h7;
+ assign T_2846 = io_inner_release_valid & T_2845;
+ assign T_2893_idx = rel_data_cnt;
+ assign T_2893_loc = 2'h2;
+ assign T_2939 = {T_2893_idx,T_2893_loc};
+ assign T_2941 = releaseMatches != 1'h0;
+ assign T_2943 = T_2941 == 1'h0;
+ assign T_2944 = io_inner_release_valid & T_2943;
+ assign T_2946 = T_2944 == 1'h0;
+ assign T_2948 = reset == 1'h0;
+ assign T_2950 = T_2946 == 1'h0;
+ assign T_2952 = reset == 1'h0;
+ assign T_2953_clk = clk;
+ assign T_2953_reset = reset;
+ assign T_2953_io_in_0_valid = T_1060_io_inner_grant_valid;
+ assign T_2953_io_in_0_bits_addr_beat = T_1060_io_inner_grant_bits_addr_beat;
+ assign T_2953_io_in_0_bits_client_xact_id = T_1060_io_inner_grant_bits_client_xact_id;
+ assign T_2953_io_in_0_bits_manager_xact_id = T_1060_io_inner_grant_bits_manager_xact_id;
+ assign T_2953_io_in_0_bits_is_builtin_type = T_1060_io_inner_grant_bits_is_builtin_type;
+ assign T_2953_io_in_0_bits_g_type = T_1060_io_inner_grant_bits_g_type;
+ assign T_2953_io_in_0_bits_data = T_1060_io_inner_grant_bits_data;
+ assign T_2953_io_in_0_bits_client_id = T_1060_io_inner_grant_bits_client_id;
+ assign T_2953_io_in_1_valid = T_1061_io_inner_grant_valid;
+ assign T_2953_io_in_1_bits_addr_beat = T_1061_io_inner_grant_bits_addr_beat;
+ assign T_2953_io_in_1_bits_client_xact_id = T_1061_io_inner_grant_bits_client_xact_id;
+ assign T_2953_io_in_1_bits_manager_xact_id = T_1061_io_inner_grant_bits_manager_xact_id;
+ assign T_2953_io_in_1_bits_is_builtin_type = T_1061_io_inner_grant_bits_is_builtin_type;
+ assign T_2953_io_in_1_bits_g_type = T_1061_io_inner_grant_bits_g_type;
+ assign T_2953_io_in_1_bits_data = T_1061_io_inner_grant_bits_data;
+ assign T_2953_io_in_1_bits_client_id = T_1061_io_inner_grant_bits_client_id;
+ assign T_2953_io_in_2_valid = T_1062_io_inner_grant_valid;
+ assign T_2953_io_in_2_bits_addr_beat = T_1062_io_inner_grant_bits_addr_beat;
+ assign T_2953_io_in_2_bits_client_xact_id = T_1062_io_inner_grant_bits_client_xact_id;
+ assign T_2953_io_in_2_bits_manager_xact_id = T_1062_io_inner_grant_bits_manager_xact_id;
+ assign T_2953_io_in_2_bits_is_builtin_type = T_1062_io_inner_grant_bits_is_builtin_type;
+ assign T_2953_io_in_2_bits_g_type = T_1062_io_inner_grant_bits_g_type;
+ assign T_2953_io_in_2_bits_data = T_1062_io_inner_grant_bits_data;
+ assign T_2953_io_in_2_bits_client_id = T_1062_io_inner_grant_bits_client_id;
+ assign T_2953_io_in_3_valid = T_1063_io_inner_grant_valid;
+ assign T_2953_io_in_3_bits_addr_beat = T_1063_io_inner_grant_bits_addr_beat;
+ assign T_2953_io_in_3_bits_client_xact_id = T_1063_io_inner_grant_bits_client_xact_id;
+ assign T_2953_io_in_3_bits_manager_xact_id = T_1063_io_inner_grant_bits_manager_xact_id;
+ assign T_2953_io_in_3_bits_is_builtin_type = T_1063_io_inner_grant_bits_is_builtin_type;
+ assign T_2953_io_in_3_bits_g_type = T_1063_io_inner_grant_bits_g_type;
+ assign T_2953_io_in_3_bits_data = T_1063_io_inner_grant_bits_data;
+ assign T_2953_io_in_3_bits_client_id = T_1063_io_inner_grant_bits_client_id;
+ assign T_2953_io_in_4_valid = T_1064_io_inner_grant_valid;
+ assign T_2953_io_in_4_bits_addr_beat = T_1064_io_inner_grant_bits_addr_beat;
+ assign T_2953_io_in_4_bits_client_xact_id = T_1064_io_inner_grant_bits_client_xact_id;
+ assign T_2953_io_in_4_bits_manager_xact_id = T_1064_io_inner_grant_bits_manager_xact_id;
+ assign T_2953_io_in_4_bits_is_builtin_type = T_1064_io_inner_grant_bits_is_builtin_type;
+ assign T_2953_io_in_4_bits_g_type = T_1064_io_inner_grant_bits_g_type;
+ assign T_2953_io_in_4_bits_data = T_1064_io_inner_grant_bits_data;
+ assign T_2953_io_in_4_bits_client_id = T_1064_io_inner_grant_bits_client_id;
+ assign T_2953_io_in_5_valid = T_1065_io_inner_grant_valid;
+ assign T_2953_io_in_5_bits_addr_beat = T_1065_io_inner_grant_bits_addr_beat;
+ assign T_2953_io_in_5_bits_client_xact_id = T_1065_io_inner_grant_bits_client_xact_id;
+ assign T_2953_io_in_5_bits_manager_xact_id = T_1065_io_inner_grant_bits_manager_xact_id;
+ assign T_2953_io_in_5_bits_is_builtin_type = T_1065_io_inner_grant_bits_is_builtin_type;
+ assign T_2953_io_in_5_bits_g_type = T_1065_io_inner_grant_bits_g_type;
+ assign T_2953_io_in_5_bits_data = T_1065_io_inner_grant_bits_data;
+ assign T_2953_io_in_5_bits_client_id = T_1065_io_inner_grant_bits_client_id;
+ assign T_2953_io_in_6_valid = T_1066_io_inner_grant_valid;
+ assign T_2953_io_in_6_bits_addr_beat = T_1066_io_inner_grant_bits_addr_beat;
+ assign T_2953_io_in_6_bits_client_xact_id = T_1066_io_inner_grant_bits_client_xact_id;
+ assign T_2953_io_in_6_bits_manager_xact_id = T_1066_io_inner_grant_bits_manager_xact_id;
+ assign T_2953_io_in_6_bits_is_builtin_type = T_1066_io_inner_grant_bits_is_builtin_type;
+ assign T_2953_io_in_6_bits_g_type = T_1066_io_inner_grant_bits_g_type;
+ assign T_2953_io_in_6_bits_data = T_1066_io_inner_grant_bits_data;
+ assign T_2953_io_in_6_bits_client_id = T_1066_io_inner_grant_bits_client_id;
+ assign T_2953_io_in_7_valid = T_1067_io_inner_grant_valid;
+ assign T_2953_io_in_7_bits_addr_beat = T_1067_io_inner_grant_bits_addr_beat;
+ assign T_2953_io_in_7_bits_client_xact_id = T_1067_io_inner_grant_bits_client_xact_id;
+ assign T_2953_io_in_7_bits_manager_xact_id = T_1067_io_inner_grant_bits_manager_xact_id;
+ assign T_2953_io_in_7_bits_is_builtin_type = T_1067_io_inner_grant_bits_is_builtin_type;
+ assign T_2953_io_in_7_bits_g_type = T_1067_io_inner_grant_bits_g_type;
+ assign T_2953_io_in_7_bits_data = T_1067_io_inner_grant_bits_data;
+ assign T_2953_io_in_7_bits_client_id = T_1067_io_inner_grant_bits_client_id;
+ assign T_2953_io_out_ready = io_inner_grant_ready;
+ assign T_2954_clk = clk;
+ assign T_2954_reset = reset;
+ assign T_2954_io_in_0_valid = T_1060_io_inner_probe_valid;
+ assign T_2954_io_in_0_bits_addr_block = T_1060_io_inner_probe_bits_addr_block;
+ assign T_2954_io_in_0_bits_p_type = T_1060_io_inner_probe_bits_p_type;
+ assign T_2954_io_in_0_bits_client_id = T_1060_io_inner_probe_bits_client_id;
+ assign T_2954_io_in_1_valid = T_1061_io_inner_probe_valid;
+ assign T_2954_io_in_1_bits_addr_block = T_1061_io_inner_probe_bits_addr_block;
+ assign T_2954_io_in_1_bits_p_type = T_1061_io_inner_probe_bits_p_type;
+ assign T_2954_io_in_1_bits_client_id = T_1061_io_inner_probe_bits_client_id;
+ assign T_2954_io_in_2_valid = T_1062_io_inner_probe_valid;
+ assign T_2954_io_in_2_bits_addr_block = T_1062_io_inner_probe_bits_addr_block;
+ assign T_2954_io_in_2_bits_p_type = T_1062_io_inner_probe_bits_p_type;
+ assign T_2954_io_in_2_bits_client_id = T_1062_io_inner_probe_bits_client_id;
+ assign T_2954_io_in_3_valid = T_1063_io_inner_probe_valid;
+ assign T_2954_io_in_3_bits_addr_block = T_1063_io_inner_probe_bits_addr_block;
+ assign T_2954_io_in_3_bits_p_type = T_1063_io_inner_probe_bits_p_type;
+ assign T_2954_io_in_3_bits_client_id = T_1063_io_inner_probe_bits_client_id;
+ assign T_2954_io_in_4_valid = T_1064_io_inner_probe_valid;
+ assign T_2954_io_in_4_bits_addr_block = T_1064_io_inner_probe_bits_addr_block;
+ assign T_2954_io_in_4_bits_p_type = T_1064_io_inner_probe_bits_p_type;
+ assign T_2954_io_in_4_bits_client_id = T_1064_io_inner_probe_bits_client_id;
+ assign T_2954_io_in_5_valid = T_1065_io_inner_probe_valid;
+ assign T_2954_io_in_5_bits_addr_block = T_1065_io_inner_probe_bits_addr_block;
+ assign T_2954_io_in_5_bits_p_type = T_1065_io_inner_probe_bits_p_type;
+ assign T_2954_io_in_5_bits_client_id = T_1065_io_inner_probe_bits_client_id;
+ assign T_2954_io_in_6_valid = T_1066_io_inner_probe_valid;
+ assign T_2954_io_in_6_bits_addr_block = T_1066_io_inner_probe_bits_addr_block;
+ assign T_2954_io_in_6_bits_p_type = T_1066_io_inner_probe_bits_p_type;
+ assign T_2954_io_in_6_bits_client_id = T_1066_io_inner_probe_bits_client_id;
+ assign T_2954_io_in_7_valid = T_1067_io_inner_probe_valid;
+ assign T_2954_io_in_7_bits_addr_block = T_1067_io_inner_probe_bits_addr_block;
+ assign T_2954_io_in_7_bits_p_type = T_1067_io_inner_probe_bits_p_type;
+ assign T_2954_io_in_7_bits_client_id = T_1067_io_inner_probe_bits_client_id;
+ assign T_2954_io_out_ready = io_inner_probe_ready;
+ assign T_2956 = io_inner_finish_bits_manager_xact_id == 1'h0;
+ assign T_2957 = io_inner_finish_valid & T_2956;
+ assign T_2959 = io_inner_finish_bits_manager_xact_id == 1'h1;
+ assign T_2960 = io_inner_finish_valid & T_2959;
+ assign T_2962 = io_inner_finish_bits_manager_xact_id == 2'h2;
+ assign T_2963 = io_inner_finish_valid & T_2962;
+ assign T_2965 = io_inner_finish_bits_manager_xact_id == 2'h3;
+ assign T_2966 = io_inner_finish_valid & T_2965;
+ assign T_2968 = io_inner_finish_bits_manager_xact_id == 3'h4;
+ assign T_2969 = io_inner_finish_valid & T_2968;
+ assign T_2971 = io_inner_finish_bits_manager_xact_id == 3'h5;
+ assign T_2972 = io_inner_finish_valid & T_2971;
+ assign T_2974 = io_inner_finish_bits_manager_xact_id == 3'h6;
+ assign T_2975 = io_inner_finish_valid & T_2974;
+ assign T_2977 = io_inner_finish_bits_manager_xact_id == 3'h7;
+ assign T_2978 = io_inner_finish_valid & T_2977;
+ assign T_2980_0 = T_1060_io_inner_finish_ready;
+ assign T_2980_1 = T_1061_io_inner_finish_ready;
+ assign T_2980_2 = T_1062_io_inner_finish_ready;
+ assign T_2980_3 = T_1063_io_inner_finish_ready;
+ assign T_2980_4 = T_1064_io_inner_finish_ready;
+ assign T_2980_5 = T_1065_io_inner_finish_ready;
+ assign T_2980_6 = T_1066_io_inner_finish_ready;
+ assign T_2980_7 = T_1067_io_inner_finish_ready;
+ assign GEN_2 = GEN_14 ? T_2980_7 : GEN_15 ? T_2980_6 : GEN_16 ? T_2980_5 : GEN_17 ? T_2980_4 : GEN_18 ? T_2980_3 : GEN_19 ? T_2980_2 : GEN_20 ? T_2980_1 : T_2980_0;
+ assign outer_arb_clk = clk;
+ assign outer_arb_reset = reset;
+ assign outer_arb_io_in_0_acquire_valid = T_1060_io_outer_acquire_valid;
+ assign outer_arb_io_in_0_acquire_bits_addr_block = T_1060_io_outer_acquire_bits_addr_block;
+ assign outer_arb_io_in_0_acquire_bits_client_xact_id = T_1060_io_outer_acquire_bits_client_xact_id;
+ assign outer_arb_io_in_0_acquire_bits_addr_beat = T_1060_io_outer_acquire_bits_addr_beat;
+ assign outer_arb_io_in_0_acquire_bits_is_builtin_type = T_1060_io_outer_acquire_bits_is_builtin_type;
+ assign outer_arb_io_in_0_acquire_bits_a_type = T_1060_io_outer_acquire_bits_a_type;
+ assign outer_arb_io_in_0_acquire_bits_union = T_1060_io_outer_acquire_bits_union;
+ assign outer_arb_io_in_0_acquire_bits_data = T_1060_io_outer_acquire_bits_data;
+ assign outer_arb_io_in_0_grant_ready = T_1060_io_outer_grant_ready;
+ assign outer_arb_io_in_1_acquire_valid = T_1061_io_outer_acquire_valid;
+ assign outer_arb_io_in_1_acquire_bits_addr_block = T_1061_io_outer_acquire_bits_addr_block;
+ assign outer_arb_io_in_1_acquire_bits_client_xact_id = T_1061_io_outer_acquire_bits_client_xact_id;
+ assign outer_arb_io_in_1_acquire_bits_addr_beat = T_1061_io_outer_acquire_bits_addr_beat;
+ assign outer_arb_io_in_1_acquire_bits_is_builtin_type = T_1061_io_outer_acquire_bits_is_builtin_type;
+ assign outer_arb_io_in_1_acquire_bits_a_type = T_1061_io_outer_acquire_bits_a_type;
+ assign outer_arb_io_in_1_acquire_bits_union = T_1061_io_outer_acquire_bits_union;
+ assign outer_arb_io_in_1_acquire_bits_data = T_1061_io_outer_acquire_bits_data;
+ assign outer_arb_io_in_1_grant_ready = T_1061_io_outer_grant_ready;
+ assign outer_arb_io_in_2_acquire_valid = T_1062_io_outer_acquire_valid;
+ assign outer_arb_io_in_2_acquire_bits_addr_block = T_1062_io_outer_acquire_bits_addr_block;
+ assign outer_arb_io_in_2_acquire_bits_client_xact_id = T_1062_io_outer_acquire_bits_client_xact_id;
+ assign outer_arb_io_in_2_acquire_bits_addr_beat = T_1062_io_outer_acquire_bits_addr_beat;
+ assign outer_arb_io_in_2_acquire_bits_is_builtin_type = T_1062_io_outer_acquire_bits_is_builtin_type;
+ assign outer_arb_io_in_2_acquire_bits_a_type = T_1062_io_outer_acquire_bits_a_type;
+ assign outer_arb_io_in_2_acquire_bits_union = T_1062_io_outer_acquire_bits_union;
+ assign outer_arb_io_in_2_acquire_bits_data = T_1062_io_outer_acquire_bits_data;
+ assign outer_arb_io_in_2_grant_ready = T_1062_io_outer_grant_ready;
+ assign outer_arb_io_in_3_acquire_valid = T_1063_io_outer_acquire_valid;
+ assign outer_arb_io_in_3_acquire_bits_addr_block = T_1063_io_outer_acquire_bits_addr_block;
+ assign outer_arb_io_in_3_acquire_bits_client_xact_id = T_1063_io_outer_acquire_bits_client_xact_id;
+ assign outer_arb_io_in_3_acquire_bits_addr_beat = T_1063_io_outer_acquire_bits_addr_beat;
+ assign outer_arb_io_in_3_acquire_bits_is_builtin_type = T_1063_io_outer_acquire_bits_is_builtin_type;
+ assign outer_arb_io_in_3_acquire_bits_a_type = T_1063_io_outer_acquire_bits_a_type;
+ assign outer_arb_io_in_3_acquire_bits_union = T_1063_io_outer_acquire_bits_union;
+ assign outer_arb_io_in_3_acquire_bits_data = T_1063_io_outer_acquire_bits_data;
+ assign outer_arb_io_in_3_grant_ready = T_1063_io_outer_grant_ready;
+ assign outer_arb_io_in_4_acquire_valid = T_1064_io_outer_acquire_valid;
+ assign outer_arb_io_in_4_acquire_bits_addr_block = T_1064_io_outer_acquire_bits_addr_block;
+ assign outer_arb_io_in_4_acquire_bits_client_xact_id = T_1064_io_outer_acquire_bits_client_xact_id;
+ assign outer_arb_io_in_4_acquire_bits_addr_beat = T_1064_io_outer_acquire_bits_addr_beat;
+ assign outer_arb_io_in_4_acquire_bits_is_builtin_type = T_1064_io_outer_acquire_bits_is_builtin_type;
+ assign outer_arb_io_in_4_acquire_bits_a_type = T_1064_io_outer_acquire_bits_a_type;
+ assign outer_arb_io_in_4_acquire_bits_union = T_1064_io_outer_acquire_bits_union;
+ assign outer_arb_io_in_4_acquire_bits_data = T_1064_io_outer_acquire_bits_data;
+ assign outer_arb_io_in_4_grant_ready = T_1064_io_outer_grant_ready;
+ assign outer_arb_io_in_5_acquire_valid = T_1065_io_outer_acquire_valid;
+ assign outer_arb_io_in_5_acquire_bits_addr_block = T_1065_io_outer_acquire_bits_addr_block;
+ assign outer_arb_io_in_5_acquire_bits_client_xact_id = T_1065_io_outer_acquire_bits_client_xact_id;
+ assign outer_arb_io_in_5_acquire_bits_addr_beat = T_1065_io_outer_acquire_bits_addr_beat;
+ assign outer_arb_io_in_5_acquire_bits_is_builtin_type = T_1065_io_outer_acquire_bits_is_builtin_type;
+ assign outer_arb_io_in_5_acquire_bits_a_type = T_1065_io_outer_acquire_bits_a_type;
+ assign outer_arb_io_in_5_acquire_bits_union = T_1065_io_outer_acquire_bits_union;
+ assign outer_arb_io_in_5_acquire_bits_data = T_1065_io_outer_acquire_bits_data;
+ assign outer_arb_io_in_5_grant_ready = T_1065_io_outer_grant_ready;
+ assign outer_arb_io_in_6_acquire_valid = T_1066_io_outer_acquire_valid;
+ assign outer_arb_io_in_6_acquire_bits_addr_block = T_1066_io_outer_acquire_bits_addr_block;
+ assign outer_arb_io_in_6_acquire_bits_client_xact_id = T_1066_io_outer_acquire_bits_client_xact_id;
+ assign outer_arb_io_in_6_acquire_bits_addr_beat = T_1066_io_outer_acquire_bits_addr_beat;
+ assign outer_arb_io_in_6_acquire_bits_is_builtin_type = T_1066_io_outer_acquire_bits_is_builtin_type;
+ assign outer_arb_io_in_6_acquire_bits_a_type = T_1066_io_outer_acquire_bits_a_type;
+ assign outer_arb_io_in_6_acquire_bits_union = T_1066_io_outer_acquire_bits_union;
+ assign outer_arb_io_in_6_acquire_bits_data = T_1066_io_outer_acquire_bits_data;
+ assign outer_arb_io_in_6_grant_ready = T_1066_io_outer_grant_ready;
+ assign outer_arb_io_in_7_acquire_valid = T_1067_io_outer_acquire_valid;
+ assign outer_arb_io_in_7_acquire_bits_addr_block = T_1067_io_outer_acquire_bits_addr_block;
+ assign outer_arb_io_in_7_acquire_bits_client_xact_id = T_1067_io_outer_acquire_bits_client_xact_id;
+ assign outer_arb_io_in_7_acquire_bits_addr_beat = T_1067_io_outer_acquire_bits_addr_beat;
+ assign outer_arb_io_in_7_acquire_bits_is_builtin_type = T_1067_io_outer_acquire_bits_is_builtin_type;
+ assign outer_arb_io_in_7_acquire_bits_a_type = T_1067_io_outer_acquire_bits_a_type;
+ assign outer_arb_io_in_7_acquire_bits_union = T_1067_io_outer_acquire_bits_union;
+ assign outer_arb_io_in_7_acquire_bits_data = T_1067_io_outer_acquire_bits_data;
+ assign outer_arb_io_in_7_grant_ready = T_1067_io_outer_grant_ready;
+ assign outer_arb_io_out_acquire_ready = io_outer_acquire_ready;
+ assign outer_arb_io_out_grant_valid = io_outer_grant_valid;
+ assign outer_arb_io_out_grant_bits_addr_beat = io_outer_grant_bits_addr_beat;
+ assign outer_arb_io_out_grant_bits_client_xact_id = io_outer_grant_bits_client_xact_id;
+ assign outer_arb_io_out_grant_bits_manager_xact_id = io_outer_grant_bits_manager_xact_id;
+ assign outer_arb_io_out_grant_bits_is_builtin_type = io_outer_grant_bits_is_builtin_type;
+ assign outer_arb_io_out_grant_bits_g_type = io_outer_grant_bits_g_type;
+ assign outer_arb_io_out_grant_bits_data = io_outer_grant_bits_data;
+ assign outer_data_ptr_idx = T_3131;
+ assign outer_data_ptr_loc = T_3130;
+ assign T_3130 = outer_arb_io_out_acquire_bits_data[1:0];
+ assign T_3131 = outer_arb_io_out_acquire_bits_data[3:2];
+ assign is_in_sdq = outer_data_ptr_loc == 1'h0;
+ assign T_3133 = io_outer_acquire_ready & io_outer_acquire_valid;
+ assign T_3138_0 = 3'h2;
+ assign T_3138_1 = 3'h3;
+ assign T_3138_2 = 3'h4;
+ assign T_3143 = T_3138_0 == io_outer_acquire_bits_a_type;
+ assign T_3144 = T_3138_1 == io_outer_acquire_bits_a_type;
+ assign T_3145 = T_3138_2 == io_outer_acquire_bits_a_type;
+ assign T_3147 = 1'h0 | T_3143;
+ assign T_3148 = T_3147 | T_3144;
+ assign T_3149 = T_3148 | T_3145;
+ assign T_3150 = io_outer_acquire_bits_is_builtin_type & T_3149;
+ assign T_3151 = T_3133 & T_3150;
+ assign T_3152 = outer_data_ptr_loc == 1'h0;
+ assign free_sdq = T_3151 & T_3152;
+ assign T_3156 = 1'h1 == outer_data_ptr_loc;
+ assign GEN_3 = GEN_21 ? vwbdq_3 : GEN_22 ? vwbdq_2 : GEN_23 ? vwbdq_1 : vwbdq_0;
+ assign T_3157 = T_3156 ? GEN_3 : io_inner_release_bits_data;
+ assign T_3158 = 1'h0 == outer_data_ptr_loc;
+ assign GEN_4 = GEN_24 ? sdq_3 : GEN_25 ? sdq_2 : GEN_26 ? sdq_1 : sdq_0;
+ assign T_3159 = T_3158 ? GEN_4 : T_3157;
+ assign T_3160 = io_outer_acquire_valid | sdq_enq;
+ assign T_3162 = 1'h1 << outer_data_ptr_idx;
+ assign T_3164 = 4'h0 - free_sdq;
+ assign T_3165 = T_3164[3:0];
+ assign T_3166 = T_3162 & T_3165;
+ assign T_3167 = ~ T_3166;
+ assign T_3168 = sdq_val & T_3167;
+ assign T_3169 = sdq_val;
+ assign T_3170 = ~ T_3169;
+ assign T_3171 = T_3170[0];
+ assign T_3172 = T_3170[1];
+ assign T_3173 = T_3170[2];
+ assign T_3174 = T_3170[3];
+ assign T_3180_0 = 4'h1;
+ assign T_3180_1 = 4'h2;
+ assign T_3180_2 = 4'h4;
+ assign T_3180_3 = 4'h8;
+ assign T_3188 = T_3174 ? T_3180_3 : 4'h0;
+ assign T_3189 = T_3173 ? T_3180_2 : T_3188;
+ assign T_3190 = T_3172 ? T_3180_1 : T_3189;
+ assign T_3191 = T_3171 ? T_3180_0 : T_3190;
+ assign T_3193 = 4'h0 - sdq_enq;
+ assign T_3194 = T_3193[3:0];
+ assign T_3195 = T_3191 & T_3194;
+ assign T_3196 = T_3168 | T_3195;
+ assign GEN_5 = T_2948 & T_2950;
+ assign GEN_6 = 1'h0 == sdq_alloc_id;
+ assign GEN_7 = 1'h1 == sdq_alloc_id;
+ assign GEN_8 = 2'h2 == sdq_alloc_id;
+ assign GEN_9 = 2'h3 == sdq_alloc_id;
+ assign GEN_10 = 1'h0 == rel_data_cnt;
+ assign GEN_11 = 1'h1 == rel_data_cnt;
+ assign GEN_12 = 2'h2 == rel_data_cnt;
+ assign GEN_13 = 2'h3 == rel_data_cnt;
+ assign GEN_14 = 3'h7 == io_inner_finish_bits_manager_xact_id;
+ assign GEN_15 = 3'h6 == io_inner_finish_bits_manager_xact_id;
+ assign GEN_16 = 3'h5 == io_inner_finish_bits_manager_xact_id;
+ assign GEN_17 = 3'h4 == io_inner_finish_bits_manager_xact_id;
+ assign GEN_18 = 2'h3 == io_inner_finish_bits_manager_xact_id;
+ assign GEN_19 = 2'h2 == io_inner_finish_bits_manager_xact_id;
+ assign GEN_20 = 1'h1 == io_inner_finish_bits_manager_xact_id;
+ assign GEN_21 = 2'h3 == outer_data_ptr_idx;
+ assign GEN_22 = 2'h2 == outer_data_ptr_idx;
+ assign GEN_23 = 1'h1 == outer_data_ptr_idx;
+ assign GEN_24 = 2'h3 == outer_data_ptr_idx;
+ assign GEN_25 = 2'h2 == outer_data_ptr_idx;
+ assign GEN_26 = 1'h1 == outer_data_ptr_idx;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ sdq_0 = {4{$random}};
+ sdq_1 = {4{$random}};
+ sdq_2 = {4{$random}};
+ sdq_3 = {4{$random}};
+ sdq_val = {1{$random}};
+ rel_data_cnt = {1{$random}};
+ vwbdq_0 = {4{$random}};
+ vwbdq_1 = {4{$random}};
+ vwbdq_2 = {4{$random}};
+ vwbdq_3 = {4{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(1'h0) begin
+ ;
+ end else begin
+ if(sdq_enq) begin
+ if(GEN_6) begin
+ sdq_0 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(sdq_enq) begin
+ if(GEN_7) begin
+ sdq_1 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(sdq_enq) begin
+ if(GEN_8) begin
+ sdq_2 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(sdq_enq) begin
+ if(GEN_9) begin
+ sdq_3 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ sdq_val <= 4'h0;
+ end else begin
+ if(T_3160) begin
+ sdq_val <= T_3196;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ rel_data_cnt <= 2'h0;
+ end else begin
+ if(vwbdq_enq) begin
+ rel_data_cnt <= T_2082;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(vwbdq_enq) begin
+ if(GEN_10) begin
+ vwbdq_0 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(vwbdq_enq) begin
+ if(GEN_11) begin
+ vwbdq_1 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(vwbdq_enq) begin
+ if(GEN_12) begin
+ vwbdq_2 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(vwbdq_enq) begin
+ if(GEN_13) begin
+ vwbdq_3 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ `ifndef SYNTHESIS
+ if(GEN_5 & T_2952) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Non-voluntary release should always have a Tracker waiting for it.");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_2948 & T_2950) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ end
+endmodule
+module Queue_36(
+ input clk,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [31:0] io_enq_bits_addr,
+ input [7:0] io_enq_bits_len,
+ input [2:0] io_enq_bits_size,
+ input [1:0] io_enq_bits_burst,
+ input io_enq_bits_lock,
+ input [3:0] io_enq_bits_cache,
+ input [2:0] io_enq_bits_prot,
+ input [3:0] io_enq_bits_qos,
+ input [3:0] io_enq_bits_region,
+ input [4:0] io_enq_bits_id,
+ input io_enq_bits_user,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [31:0] io_deq_bits_addr,
+ output [7:0] io_deq_bits_len,
+ output [2:0] io_deq_bits_size,
+ output [1:0] io_deq_bits_burst,
+ output io_deq_bits_lock,
+ output [3:0] io_deq_bits_cache,
+ output [2:0] io_deq_bits_prot,
+ output [3:0] io_deq_bits_qos,
+ output [3:0] io_deq_bits_region,
+ output [4:0] io_deq_bits_id,
+ output io_deq_bits_user,
+ output [1:0] io_count
+);
+ reg [31:0] ram_addr [0:1];
+ wire [31:0] ram_addr_T_187_data;
+ wire ram_addr_T_187_addr;
+ wire ram_addr_T_187_en;
+ wire ram_addr_T_187_clk;
+ wire [31:0] ram_addr_T_146_data;
+ wire ram_addr_T_146_addr;
+ wire ram_addr_T_146_mask;
+ wire ram_addr_T_146_en;
+ wire ram_addr_T_146_clk;
+ reg [7:0] ram_len [0:1];
+ wire [7:0] ram_len_T_187_data;
+ wire ram_len_T_187_addr;
+ wire ram_len_T_187_en;
+ wire ram_len_T_187_clk;
+ wire [7:0] ram_len_T_146_data;
+ wire ram_len_T_146_addr;
+ wire ram_len_T_146_mask;
+ wire ram_len_T_146_en;
+ wire ram_len_T_146_clk;
+ reg [2:0] ram_size [0:1];
+ wire [2:0] ram_size_T_187_data;
+ wire ram_size_T_187_addr;
+ wire ram_size_T_187_en;
+ wire ram_size_T_187_clk;
+ wire [2:0] ram_size_T_146_data;
+ wire ram_size_T_146_addr;
+ wire ram_size_T_146_mask;
+ wire ram_size_T_146_en;
+ wire ram_size_T_146_clk;
+ reg [1:0] ram_burst [0:1];
+ wire [1:0] ram_burst_T_187_data;
+ wire ram_burst_T_187_addr;
+ wire ram_burst_T_187_en;
+ wire ram_burst_T_187_clk;
+ wire [1:0] ram_burst_T_146_data;
+ wire ram_burst_T_146_addr;
+ wire ram_burst_T_146_mask;
+ wire ram_burst_T_146_en;
+ wire ram_burst_T_146_clk;
+ reg ram_lock [0:1];
+ wire ram_lock_T_187_data;
+ wire ram_lock_T_187_addr;
+ wire ram_lock_T_187_en;
+ wire ram_lock_T_187_clk;
+ wire ram_lock_T_146_data;
+ wire ram_lock_T_146_addr;
+ wire ram_lock_T_146_mask;
+ wire ram_lock_T_146_en;
+ wire ram_lock_T_146_clk;
+ reg [3:0] ram_cache [0:1];
+ wire [3:0] ram_cache_T_187_data;
+ wire ram_cache_T_187_addr;
+ wire ram_cache_T_187_en;
+ wire ram_cache_T_187_clk;
+ wire [3:0] ram_cache_T_146_data;
+ wire ram_cache_T_146_addr;
+ wire ram_cache_T_146_mask;
+ wire ram_cache_T_146_en;
+ wire ram_cache_T_146_clk;
+ reg [2:0] ram_prot [0:1];
+ wire [2:0] ram_prot_T_187_data;
+ wire ram_prot_T_187_addr;
+ wire ram_prot_T_187_en;
+ wire ram_prot_T_187_clk;
+ wire [2:0] ram_prot_T_146_data;
+ wire ram_prot_T_146_addr;
+ wire ram_prot_T_146_mask;
+ wire ram_prot_T_146_en;
+ wire ram_prot_T_146_clk;
+ reg [3:0] ram_qos [0:1];
+ wire [3:0] ram_qos_T_187_data;
+ wire ram_qos_T_187_addr;
+ wire ram_qos_T_187_en;
+ wire ram_qos_T_187_clk;
+ wire [3:0] ram_qos_T_146_data;
+ wire ram_qos_T_146_addr;
+ wire ram_qos_T_146_mask;
+ wire ram_qos_T_146_en;
+ wire ram_qos_T_146_clk;
+ reg [3:0] ram_region [0:1];
+ wire [3:0] ram_region_T_187_data;
+ wire ram_region_T_187_addr;
+ wire ram_region_T_187_en;
+ wire ram_region_T_187_clk;
+ wire [3:0] ram_region_T_146_data;
+ wire ram_region_T_146_addr;
+ wire ram_region_T_146_mask;
+ wire ram_region_T_146_en;
+ wire ram_region_T_146_clk;
+ reg [4:0] ram_id [0:1];
+ wire [4:0] ram_id_T_187_data;
+ wire ram_id_T_187_addr;
+ wire ram_id_T_187_en;
+ wire ram_id_T_187_clk;
+ wire [4:0] ram_id_T_146_data;
+ wire ram_id_T_146_addr;
+ wire ram_id_T_146_mask;
+ wire ram_id_T_146_en;
+ wire ram_id_T_146_clk;
+ reg ram_user [0:1];
+ wire ram_user_T_187_data;
+ wire ram_user_T_187_addr;
+ wire ram_user_T_187_en;
+ wire ram_user_T_187_clk;
+ wire ram_user_T_146_data;
+ wire ram_user_T_146_addr;
+ wire ram_user_T_146_mask;
+ wire ram_user_T_146_en;
+ wire ram_user_T_146_clk;
+ reg T_125;
+ reg T_127;
+ reg maybe_full;
+ wire ptr_match;
+ wire T_132;
+ wire empty;
+ wire full;
+ wire maybe_flow;
+ wire do_flow;
+ wire T_138;
+ wire T_140;
+ wire do_enq;
+ wire T_142;
+ wire T_144;
+ wire do_deq;
+ wire T_159;
+ wire T_161;
+ wire [1:0] T_164;
+ wire T_165;
+ wire T_166;
+ wire T_168;
+ wire T_170;
+ wire [1:0] T_173;
+ wire T_174;
+ wire T_175;
+ wire T_176;
+ wire T_178;
+ wire T_180;
+ wire T_181;
+ wire T_183;
+ wire T_185;
+ wire T_186;
+ wire [31:0] T_199_addr;
+ wire [7:0] T_199_len;
+ wire [2:0] T_199_size;
+ wire [1:0] T_199_burst;
+ wire T_199_lock;
+ wire [3:0] T_199_cache;
+ wire [2:0] T_199_prot;
+ wire [3:0] T_199_qos;
+ wire [3:0] T_199_region;
+ wire [4:0] T_199_id;
+ wire T_199_user;
+ wire [1:0] T_211;
+ wire ptr_diff;
+ wire T_213;
+ wire [1:0] T_214;
+ assign io_enq_ready = T_186;
+ assign io_deq_valid = T_181;
+ assign io_deq_bits_addr = T_199_addr;
+ assign io_deq_bits_len = T_199_len;
+ assign io_deq_bits_size = T_199_size;
+ assign io_deq_bits_burst = T_199_burst;
+ assign io_deq_bits_lock = T_199_lock;
+ assign io_deq_bits_cache = T_199_cache;
+ assign io_deq_bits_prot = T_199_prot;
+ assign io_deq_bits_qos = T_199_qos;
+ assign io_deq_bits_region = T_199_region;
+ assign io_deq_bits_id = T_199_id;
+ assign io_deq_bits_user = T_199_user;
+ assign io_count = T_214;
+ assign ram_addr_T_187_addr = T_127;
+ assign ram_addr_T_187_en = 1'h1;
+ assign ram_addr_T_187_clk = clk;
+ assign ram_addr_T_187_data = ram_addr[ram_addr_T_187_addr];
+ assign ram_addr_T_146_data = io_enq_bits_addr;
+ assign ram_addr_T_146_addr = T_125;
+ assign ram_addr_T_146_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_addr_T_146_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_addr_T_146_clk = clk;
+ assign ram_len_T_187_addr = T_127;
+ assign ram_len_T_187_en = 1'h1;
+ assign ram_len_T_187_clk = clk;
+ assign ram_len_T_187_data = ram_len[ram_len_T_187_addr];
+ assign ram_len_T_146_data = io_enq_bits_len;
+ assign ram_len_T_146_addr = T_125;
+ assign ram_len_T_146_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_len_T_146_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_len_T_146_clk = clk;
+ assign ram_size_T_187_addr = T_127;
+ assign ram_size_T_187_en = 1'h1;
+ assign ram_size_T_187_clk = clk;
+ assign ram_size_T_187_data = ram_size[ram_size_T_187_addr];
+ assign ram_size_T_146_data = io_enq_bits_size;
+ assign ram_size_T_146_addr = T_125;
+ assign ram_size_T_146_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_size_T_146_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_size_T_146_clk = clk;
+ assign ram_burst_T_187_addr = T_127;
+ assign ram_burst_T_187_en = 1'h1;
+ assign ram_burst_T_187_clk = clk;
+ assign ram_burst_T_187_data = ram_burst[ram_burst_T_187_addr];
+ assign ram_burst_T_146_data = io_enq_bits_burst;
+ assign ram_burst_T_146_addr = T_125;
+ assign ram_burst_T_146_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_burst_T_146_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_burst_T_146_clk = clk;
+ assign ram_lock_T_187_addr = T_127;
+ assign ram_lock_T_187_en = 1'h1;
+ assign ram_lock_T_187_clk = clk;
+ assign ram_lock_T_187_data = ram_lock[ram_lock_T_187_addr];
+ assign ram_lock_T_146_data = io_enq_bits_lock;
+ assign ram_lock_T_146_addr = T_125;
+ assign ram_lock_T_146_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_lock_T_146_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_lock_T_146_clk = clk;
+ assign ram_cache_T_187_addr = T_127;
+ assign ram_cache_T_187_en = 1'h1;
+ assign ram_cache_T_187_clk = clk;
+ assign ram_cache_T_187_data = ram_cache[ram_cache_T_187_addr];
+ assign ram_cache_T_146_data = io_enq_bits_cache;
+ assign ram_cache_T_146_addr = T_125;
+ assign ram_cache_T_146_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_cache_T_146_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_cache_T_146_clk = clk;
+ assign ram_prot_T_187_addr = T_127;
+ assign ram_prot_T_187_en = 1'h1;
+ assign ram_prot_T_187_clk = clk;
+ assign ram_prot_T_187_data = ram_prot[ram_prot_T_187_addr];
+ assign ram_prot_T_146_data = io_enq_bits_prot;
+ assign ram_prot_T_146_addr = T_125;
+ assign ram_prot_T_146_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_prot_T_146_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_prot_T_146_clk = clk;
+ assign ram_qos_T_187_addr = T_127;
+ assign ram_qos_T_187_en = 1'h1;
+ assign ram_qos_T_187_clk = clk;
+ assign ram_qos_T_187_data = ram_qos[ram_qos_T_187_addr];
+ assign ram_qos_T_146_data = io_enq_bits_qos;
+ assign ram_qos_T_146_addr = T_125;
+ assign ram_qos_T_146_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_qos_T_146_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_qos_T_146_clk = clk;
+ assign ram_region_T_187_addr = T_127;
+ assign ram_region_T_187_en = 1'h1;
+ assign ram_region_T_187_clk = clk;
+ assign ram_region_T_187_data = ram_region[ram_region_T_187_addr];
+ assign ram_region_T_146_data = io_enq_bits_region;
+ assign ram_region_T_146_addr = T_125;
+ assign ram_region_T_146_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_region_T_146_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_region_T_146_clk = clk;
+ assign ram_id_T_187_addr = T_127;
+ assign ram_id_T_187_en = 1'h1;
+ assign ram_id_T_187_clk = clk;
+ assign ram_id_T_187_data = ram_id[ram_id_T_187_addr];
+ assign ram_id_T_146_data = io_enq_bits_id;
+ assign ram_id_T_146_addr = T_125;
+ assign ram_id_T_146_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_id_T_146_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_id_T_146_clk = clk;
+ assign ram_user_T_187_addr = T_127;
+ assign ram_user_T_187_en = 1'h1;
+ assign ram_user_T_187_clk = clk;
+ assign ram_user_T_187_data = ram_user[ram_user_T_187_addr];
+ assign ram_user_T_146_data = io_enq_bits_user;
+ assign ram_user_T_146_addr = T_125;
+ assign ram_user_T_146_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_user_T_146_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_user_T_146_clk = clk;
+ assign ptr_match = T_125 == T_127;
+ assign T_132 = maybe_full == 1'h0;
+ assign empty = ptr_match & T_132;
+ assign full = ptr_match & maybe_full;
+ assign maybe_flow = 1'h0 & empty;
+ assign do_flow = maybe_flow & io_deq_ready;
+ assign T_138 = io_enq_ready & io_enq_valid;
+ assign T_140 = do_flow == 1'h0;
+ assign do_enq = T_138 & T_140;
+ assign T_142 = io_deq_ready & io_deq_valid;
+ assign T_144 = do_flow == 1'h0;
+ assign do_deq = T_142 & T_144;
+ assign T_159 = T_125 == 1'h1;
+ assign T_161 = 1'h0 & T_159;
+ assign T_164 = T_125 + 1'h1;
+ assign T_165 = T_164[0:0];
+ assign T_166 = T_161 ? 1'h0 : T_165;
+ assign T_168 = T_127 == 1'h1;
+ assign T_170 = 1'h0 & T_168;
+ assign T_173 = T_127 + 1'h1;
+ assign T_174 = T_173[0:0];
+ assign T_175 = T_170 ? 1'h0 : T_174;
+ assign T_176 = do_enq != do_deq;
+ assign T_178 = empty == 1'h0;
+ assign T_180 = 1'h0 & io_enq_valid;
+ assign T_181 = T_178 | T_180;
+ assign T_183 = full == 1'h0;
+ assign T_185 = 1'h0 & io_deq_ready;
+ assign T_186 = T_183 | T_185;
+ assign T_199_addr = maybe_flow ? io_enq_bits_addr : ram_addr_T_187_data;
+ assign T_199_len = maybe_flow ? io_enq_bits_len : ram_len_T_187_data;
+ assign T_199_size = maybe_flow ? io_enq_bits_size : ram_size_T_187_data;
+ assign T_199_burst = maybe_flow ? io_enq_bits_burst : ram_burst_T_187_data;
+ assign T_199_lock = maybe_flow ? io_enq_bits_lock : ram_lock_T_187_data;
+ assign T_199_cache = maybe_flow ? io_enq_bits_cache : ram_cache_T_187_data;
+ assign T_199_prot = maybe_flow ? io_enq_bits_prot : ram_prot_T_187_data;
+ assign T_199_qos = maybe_flow ? io_enq_bits_qos : ram_qos_T_187_data;
+ assign T_199_region = maybe_flow ? io_enq_bits_region : ram_region_T_187_data;
+ assign T_199_id = maybe_flow ? io_enq_bits_id : ram_id_T_187_data;
+ assign T_199_user = maybe_flow ? io_enq_bits_user : ram_user_T_187_data;
+ assign T_211 = T_125 - T_127;
+ assign ptr_diff = T_211[0:0];
+ assign T_213 = maybe_full & ptr_match;
+ assign T_214 = {T_213,ptr_diff};
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_addr[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_len[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_size[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_burst[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_lock[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_cache[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_prot[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_qos[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_region[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_id[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_user[initvar] = {1{$random}};
+ T_125 = {1{$random}};
+ T_127 = {1{$random}};
+ maybe_full = {1{$random}};
+ end
+`endif
+ always @(posedge ram_addr_T_146_clk) begin
+ if(ram_addr_T_146_en & ram_addr_T_146_mask) begin
+ ram_addr[ram_addr_T_146_addr] <= ram_addr_T_146_data;
+ end
+ end
+ always @(posedge ram_len_T_146_clk) begin
+ if(ram_len_T_146_en & ram_len_T_146_mask) begin
+ ram_len[ram_len_T_146_addr] <= ram_len_T_146_data;
+ end
+ end
+ always @(posedge ram_size_T_146_clk) begin
+ if(ram_size_T_146_en & ram_size_T_146_mask) begin
+ ram_size[ram_size_T_146_addr] <= ram_size_T_146_data;
+ end
+ end
+ always @(posedge ram_burst_T_146_clk) begin
+ if(ram_burst_T_146_en & ram_burst_T_146_mask) begin
+ ram_burst[ram_burst_T_146_addr] <= ram_burst_T_146_data;
+ end
+ end
+ always @(posedge ram_lock_T_146_clk) begin
+ if(ram_lock_T_146_en & ram_lock_T_146_mask) begin
+ ram_lock[ram_lock_T_146_addr] <= ram_lock_T_146_data;
+ end
+ end
+ always @(posedge ram_cache_T_146_clk) begin
+ if(ram_cache_T_146_en & ram_cache_T_146_mask) begin
+ ram_cache[ram_cache_T_146_addr] <= ram_cache_T_146_data;
+ end
+ end
+ always @(posedge ram_prot_T_146_clk) begin
+ if(ram_prot_T_146_en & ram_prot_T_146_mask) begin
+ ram_prot[ram_prot_T_146_addr] <= ram_prot_T_146_data;
+ end
+ end
+ always @(posedge ram_qos_T_146_clk) begin
+ if(ram_qos_T_146_en & ram_qos_T_146_mask) begin
+ ram_qos[ram_qos_T_146_addr] <= ram_qos_T_146_data;
+ end
+ end
+ always @(posedge ram_region_T_146_clk) begin
+ if(ram_region_T_146_en & ram_region_T_146_mask) begin
+ ram_region[ram_region_T_146_addr] <= ram_region_T_146_data;
+ end
+ end
+ always @(posedge ram_id_T_146_clk) begin
+ if(ram_id_T_146_en & ram_id_T_146_mask) begin
+ ram_id[ram_id_T_146_addr] <= ram_id_T_146_data;
+ end
+ end
+ always @(posedge ram_user_T_146_clk) begin
+ if(ram_user_T_146_en & ram_user_T_146_mask) begin
+ ram_user[ram_user_T_146_addr] <= ram_user_T_146_data;
+ end
+ end
+ always @(posedge clk) begin
+ if(reset) begin
+ T_125 <= 1'h0;
+ end else begin
+ if(do_enq) begin
+ T_125 <= T_166;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_127 <= 1'h0;
+ end else begin
+ if(do_deq) begin
+ T_127 <= T_175;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ maybe_full <= 1'h0;
+ end else begin
+ if(T_176) begin
+ maybe_full <= do_enq;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module Queue_37(
+ input clk,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [4:0] io_enq_bits,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [4:0] io_deq_bits,
+ output [1:0] io_count
+);
+ reg [4:0] ram [0:1];
+ wire [4:0] ram_T_77_data;
+ wire ram_T_77_addr;
+ wire ram_T_77_en;
+ wire ram_T_77_clk;
+ wire [4:0] ram_T_47_data;
+ wire ram_T_47_addr;
+ wire ram_T_47_mask;
+ wire ram_T_47_en;
+ wire ram_T_47_clk;
+ reg T_26;
+ reg T_28;
+ reg maybe_full;
+ wire ptr_match;
+ wire T_33;
+ wire empty;
+ wire full;
+ wire maybe_flow;
+ wire do_flow;
+ wire T_39;
+ wire T_41;
+ wire do_enq;
+ wire T_43;
+ wire T_45;
+ wire do_deq;
+ wire T_49;
+ wire T_51;
+ wire [1:0] T_54;
+ wire T_55;
+ wire T_56;
+ wire T_58;
+ wire T_60;
+ wire [1:0] T_63;
+ wire T_64;
+ wire T_65;
+ wire T_66;
+ wire T_68;
+ wire T_70;
+ wire T_71;
+ wire T_73;
+ wire T_75;
+ wire T_76;
+ wire [4:0] T_78;
+ wire [1:0] T_79;
+ wire ptr_diff;
+ wire T_81;
+ wire [1:0] T_82;
+ assign io_enq_ready = T_76;
+ assign io_deq_valid = T_71;
+ assign io_deq_bits = T_78;
+ assign io_count = T_82;
+ assign ram_T_77_addr = T_28;
+ assign ram_T_77_en = 1'h1;
+ assign ram_T_77_clk = clk;
+ assign ram_T_77_data = ram[ram_T_77_addr];
+ assign ram_T_47_data = io_enq_bits;
+ assign ram_T_47_addr = T_26;
+ assign ram_T_47_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_T_47_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_T_47_clk = clk;
+ assign ptr_match = T_26 == T_28;
+ assign T_33 = maybe_full == 1'h0;
+ assign empty = ptr_match & T_33;
+ assign full = ptr_match & maybe_full;
+ assign maybe_flow = 1'h0 & empty;
+ assign do_flow = maybe_flow & io_deq_ready;
+ assign T_39 = io_enq_ready & io_enq_valid;
+ assign T_41 = do_flow == 1'h0;
+ assign do_enq = T_39 & T_41;
+ assign T_43 = io_deq_ready & io_deq_valid;
+ assign T_45 = do_flow == 1'h0;
+ assign do_deq = T_43 & T_45;
+ assign T_49 = T_26 == 1'h1;
+ assign T_51 = 1'h0 & T_49;
+ assign T_54 = T_26 + 1'h1;
+ assign T_55 = T_54[0:0];
+ assign T_56 = T_51 ? 1'h0 : T_55;
+ assign T_58 = T_28 == 1'h1;
+ assign T_60 = 1'h0 & T_58;
+ assign T_63 = T_28 + 1'h1;
+ assign T_64 = T_63[0:0];
+ assign T_65 = T_60 ? 1'h0 : T_64;
+ assign T_66 = do_enq != do_deq;
+ assign T_68 = empty == 1'h0;
+ assign T_70 = 1'h0 & io_enq_valid;
+ assign T_71 = T_68 | T_70;
+ assign T_73 = full == 1'h0;
+ assign T_75 = 1'h0 & io_deq_ready;
+ assign T_76 = T_73 | T_75;
+ assign T_78 = maybe_flow ? io_enq_bits : ram_T_77_data;
+ assign T_79 = T_26 - T_28;
+ assign ptr_diff = T_79[0:0];
+ assign T_81 = maybe_full & ptr_match;
+ assign T_82 = {T_81,ptr_diff};
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram[initvar] = {1{$random}};
+ T_26 = {1{$random}};
+ T_28 = {1{$random}};
+ maybe_full = {1{$random}};
+ end
+`endif
+ always @(posedge ram_T_47_clk) begin
+ if(ram_T_47_en & ram_T_47_mask) begin
+ ram[ram_T_47_addr] <= ram_T_47_data;
+ end
+ end
+ always @(posedge clk) begin
+ if(reset) begin
+ T_26 <= 1'h0;
+ end else begin
+ if(do_enq) begin
+ T_26 <= T_56;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_28 <= 1'h0;
+ end else begin
+ if(do_deq) begin
+ T_28 <= T_65;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ maybe_full <= 1'h0;
+ end else begin
+ if(T_66) begin
+ maybe_full <= do_enq;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module NastiErrorSlave(
+ input clk,
+ input reset,
+ output io_aw_ready,
+ input io_aw_valid,
+ input [31:0] io_aw_bits_addr,
+ input [7:0] io_aw_bits_len,
+ input [2:0] io_aw_bits_size,
+ input [1:0] io_aw_bits_burst,
+ input io_aw_bits_lock,
+ input [3:0] io_aw_bits_cache,
+ input [2:0] io_aw_bits_prot,
+ input [3:0] io_aw_bits_qos,
+ input [3:0] io_aw_bits_region,
+ input [4:0] io_aw_bits_id,
+ input io_aw_bits_user,
+ output io_w_ready,
+ input io_w_valid,
+ input [63:0] io_w_bits_data,
+ input io_w_bits_last,
+ input [7:0] io_w_bits_strb,
+ input io_w_bits_user,
+ input io_b_ready,
+ output io_b_valid,
+ output [1:0] io_b_bits_resp,
+ output [4:0] io_b_bits_id,
+ output io_b_bits_user,
+ output io_ar_ready,
+ input io_ar_valid,
+ input [31:0] io_ar_bits_addr,
+ input [7:0] io_ar_bits_len,
+ input [2:0] io_ar_bits_size,
+ input [1:0] io_ar_bits_burst,
+ input io_ar_bits_lock,
+ input [3:0] io_ar_bits_cache,
+ input [2:0] io_ar_bits_prot,
+ input [3:0] io_ar_bits_qos,
+ input [3:0] io_ar_bits_region,
+ input [4:0] io_ar_bits_id,
+ input io_ar_bits_user,
+ input io_r_ready,
+ output io_r_valid,
+ output [1:0] io_r_bits_resp,
+ output [63:0] io_r_bits_data,
+ output io_r_bits_last,
+ output [4:0] io_r_bits_id,
+ output io_r_bits_user
+);
+ wire T_322;
+ wire T_324;
+ wire T_325;
+ wire T_327;
+ wire r_queue_clk;
+ wire r_queue_reset;
+ wire r_queue_io_enq_ready;
+ wire r_queue_io_enq_valid;
+ wire [31:0] r_queue_io_enq_bits_addr;
+ wire [7:0] r_queue_io_enq_bits_len;
+ wire [2:0] r_queue_io_enq_bits_size;
+ wire [1:0] r_queue_io_enq_bits_burst;
+ wire r_queue_io_enq_bits_lock;
+ wire [3:0] r_queue_io_enq_bits_cache;
+ wire [2:0] r_queue_io_enq_bits_prot;
+ wire [3:0] r_queue_io_enq_bits_qos;
+ wire [3:0] r_queue_io_enq_bits_region;
+ wire [4:0] r_queue_io_enq_bits_id;
+ wire r_queue_io_enq_bits_user;
+ wire r_queue_io_deq_ready;
+ wire r_queue_io_deq_valid;
+ wire [31:0] r_queue_io_deq_bits_addr;
+ wire [7:0] r_queue_io_deq_bits_len;
+ wire [2:0] r_queue_io_deq_bits_size;
+ wire [1:0] r_queue_io_deq_bits_burst;
+ wire r_queue_io_deq_bits_lock;
+ wire [3:0] r_queue_io_deq_bits_cache;
+ wire [2:0] r_queue_io_deq_bits_prot;
+ wire [3:0] r_queue_io_deq_bits_qos;
+ wire [3:0] r_queue_io_deq_bits_region;
+ wire [4:0] r_queue_io_deq_bits_id;
+ wire r_queue_io_deq_bits_user;
+ wire [1:0] r_queue_io_count;
+ reg responding;
+ reg [7:0] beats_left;
+ wire T_346;
+ wire T_347;
+ wire T_349;
+ wire T_359;
+ wire T_360;
+ wire T_361;
+ wire T_362;
+ wire T_364;
+ wire T_367;
+ wire [8:0] T_369;
+ wire [7:0] T_370;
+ reg draining;
+ wire T_373;
+ wire T_375;
+ wire T_376;
+ wire b_queue_clk;
+ wire b_queue_reset;
+ wire b_queue_io_enq_ready;
+ wire b_queue_io_enq_valid;
+ wire [4:0] b_queue_io_enq_bits;
+ wire b_queue_io_deq_ready;
+ wire b_queue_io_deq_valid;
+ wire [4:0] b_queue_io_deq_bits;
+ wire [1:0] b_queue_io_count;
+ wire T_381;
+ wire T_382;
+ wire T_384;
+ wire T_385;
+ wire T_387;
+ wire T_388;
+ wire T_391;
+ wire T_392;
+ reg GEN_0;
+ reg GEN_1;
+ Queue_36 r_queue (
+ .clk(r_queue_clk),
+ .reset(r_queue_reset),
+ .io_enq_ready(r_queue_io_enq_ready),
+ .io_enq_valid(r_queue_io_enq_valid),
+ .io_enq_bits_addr(r_queue_io_enq_bits_addr),
+ .io_enq_bits_len(r_queue_io_enq_bits_len),
+ .io_enq_bits_size(r_queue_io_enq_bits_size),
+ .io_enq_bits_burst(r_queue_io_enq_bits_burst),
+ .io_enq_bits_lock(r_queue_io_enq_bits_lock),
+ .io_enq_bits_cache(r_queue_io_enq_bits_cache),
+ .io_enq_bits_prot(r_queue_io_enq_bits_prot),
+ .io_enq_bits_qos(r_queue_io_enq_bits_qos),
+ .io_enq_bits_region(r_queue_io_enq_bits_region),
+ .io_enq_bits_id(r_queue_io_enq_bits_id),
+ .io_enq_bits_user(r_queue_io_enq_bits_user),
+ .io_deq_ready(r_queue_io_deq_ready),
+ .io_deq_valid(r_queue_io_deq_valid),
+ .io_deq_bits_addr(r_queue_io_deq_bits_addr),
+ .io_deq_bits_len(r_queue_io_deq_bits_len),
+ .io_deq_bits_size(r_queue_io_deq_bits_size),
+ .io_deq_bits_burst(r_queue_io_deq_bits_burst),
+ .io_deq_bits_lock(r_queue_io_deq_bits_lock),
+ .io_deq_bits_cache(r_queue_io_deq_bits_cache),
+ .io_deq_bits_prot(r_queue_io_deq_bits_prot),
+ .io_deq_bits_qos(r_queue_io_deq_bits_qos),
+ .io_deq_bits_region(r_queue_io_deq_bits_region),
+ .io_deq_bits_id(r_queue_io_deq_bits_id),
+ .io_deq_bits_user(r_queue_io_deq_bits_user),
+ .io_count(r_queue_io_count)
+ );
+ Queue_37 b_queue (
+ .clk(b_queue_clk),
+ .reset(b_queue_reset),
+ .io_enq_ready(b_queue_io_enq_ready),
+ .io_enq_valid(b_queue_io_enq_valid),
+ .io_enq_bits(b_queue_io_enq_bits),
+ .io_deq_ready(b_queue_io_deq_ready),
+ .io_deq_valid(b_queue_io_deq_valid),
+ .io_deq_bits(b_queue_io_deq_bits),
+ .io_count(b_queue_io_count)
+ );
+ assign io_aw_ready = T_385;
+ assign io_w_ready = draining;
+ assign io_b_valid = T_388;
+ assign io_b_bits_resp = 2'h3;
+ assign io_b_bits_id = b_queue_io_deq_bits;
+ assign io_b_bits_user = GEN_0;
+ assign io_ar_ready = r_queue_io_enq_ready;
+ assign io_r_valid = T_349;
+ assign io_r_bits_resp = 2'h3;
+ assign io_r_bits_data = 1'h0;
+ assign io_r_bits_last = T_359;
+ assign io_r_bits_id = r_queue_io_deq_bits_id;
+ assign io_r_bits_user = GEN_1;
+ assign T_322 = io_ar_ready & io_ar_valid;
+ assign T_324 = reset == 1'h0;
+ assign T_325 = io_aw_ready & io_aw_valid;
+ assign T_327 = reset == 1'h0;
+ assign r_queue_clk = clk;
+ assign r_queue_reset = reset;
+ assign r_queue_io_enq_valid = io_ar_valid;
+ assign r_queue_io_enq_bits_addr = io_ar_bits_addr;
+ assign r_queue_io_enq_bits_len = io_ar_bits_len;
+ assign r_queue_io_enq_bits_size = io_ar_bits_size;
+ assign r_queue_io_enq_bits_burst = io_ar_bits_burst;
+ assign r_queue_io_enq_bits_lock = io_ar_bits_lock;
+ assign r_queue_io_enq_bits_cache = io_ar_bits_cache;
+ assign r_queue_io_enq_bits_prot = io_ar_bits_prot;
+ assign r_queue_io_enq_bits_qos = io_ar_bits_qos;
+ assign r_queue_io_enq_bits_region = io_ar_bits_region;
+ assign r_queue_io_enq_bits_id = io_ar_bits_id;
+ assign r_queue_io_enq_bits_user = io_ar_bits_user;
+ assign r_queue_io_deq_ready = T_361;
+ assign T_346 = responding == 1'h0;
+ assign T_347 = T_346 & r_queue_io_deq_valid;
+ assign T_349 = r_queue_io_deq_valid & responding;
+ assign T_359 = beats_left == 1'h0;
+ assign T_360 = io_r_ready & io_r_valid;
+ assign T_361 = T_360 & io_r_bits_last;
+ assign T_362 = io_r_ready & io_r_valid;
+ assign T_364 = beats_left == 1'h0;
+ assign T_367 = T_364 == 1'h0;
+ assign T_369 = beats_left - 1'h1;
+ assign T_370 = T_369[7:0];
+ assign T_373 = io_aw_ready & io_aw_valid;
+ assign T_375 = io_w_ready & io_w_valid;
+ assign T_376 = T_375 & io_w_bits_last;
+ assign b_queue_clk = clk;
+ assign b_queue_reset = reset;
+ assign b_queue_io_enq_valid = T_382;
+ assign b_queue_io_enq_bits = io_aw_bits_id;
+ assign b_queue_io_deq_ready = T_392;
+ assign T_381 = draining == 1'h0;
+ assign T_382 = io_aw_valid & T_381;
+ assign T_384 = draining == 1'h0;
+ assign T_385 = b_queue_io_enq_ready & T_384;
+ assign T_387 = draining == 1'h0;
+ assign T_388 = b_queue_io_deq_valid & T_387;
+ assign T_391 = draining == 1'h0;
+ assign T_392 = io_b_ready & T_391;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ responding = {1{$random}};
+ beats_left = {1{$random}};
+ draining = {1{$random}};
+ GEN_0 = {1{$random}};
+ GEN_1 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ responding <= 1'h0;
+ end else begin
+ if(T_362) begin
+ if(T_364) begin
+ responding <= 1'h0;
+ end else begin
+ if(T_347) begin
+ responding <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_347) begin
+ responding <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ beats_left <= 8'h0;
+ end else begin
+ if(T_362) begin
+ if(T_367) begin
+ beats_left <= T_370;
+ end else begin
+ if(T_347) begin
+ beats_left <= r_queue_io_deq_bits_len;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_347) begin
+ beats_left <= r_queue_io_deq_bits_len;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ draining <= 1'h0;
+ end else begin
+ if(T_376) begin
+ draining <= 1'h0;
+ end else begin
+ if(T_373) begin
+ draining <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ `ifndef SYNTHESIS
+ if(T_322 & T_324) begin
+ $fwrite(32'h80000002,"Invalid read address %h\n",io_ar_bits_addr);
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_325 & T_327) begin
+ $fwrite(32'h80000002,"Invalid write address %h\n",io_aw_bits_addr);
+ end
+ `endif
+ end
+endmodule
+module RRArbiter_38(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input [1:0] io_in_0_bits_resp,
+ input [4:0] io_in_0_bits_id,
+ input io_in_0_bits_user,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input [1:0] io_in_1_bits_resp,
+ input [4:0] io_in_1_bits_id,
+ input io_in_1_bits_user,
+ output io_in_2_ready,
+ input io_in_2_valid,
+ input [1:0] io_in_2_bits_resp,
+ input [4:0] io_in_2_bits_id,
+ input io_in_2_bits_user,
+ output io_in_3_ready,
+ input io_in_3_valid,
+ input [1:0] io_in_3_bits_resp,
+ input [4:0] io_in_3_bits_id,
+ input io_in_3_bits_user,
+ output io_in_4_ready,
+ input io_in_4_valid,
+ input [1:0] io_in_4_bits_resp,
+ input [4:0] io_in_4_bits_id,
+ input io_in_4_bits_user,
+ input io_out_ready,
+ output io_out_valid,
+ output [1:0] io_out_bits_resp,
+ output [4:0] io_out_bits_id,
+ output io_out_bits_user,
+ output [2:0] io_chosen
+);
+ wire [2:0] T_196;
+ wire GEN_0;
+ wire [1:0] GEN_1;
+ wire [4:0] GEN_2;
+ wire GEN_3;
+ wire GEN_4;
+ reg [2:0] T_233;
+ wire T_234;
+ wire T_235;
+ wire T_237;
+ wire T_238;
+ wire T_240;
+ wire T_241;
+ wire T_243;
+ wire T_244;
+ wire T_246;
+ wire T_247;
+ wire T_250;
+ wire T_252;
+ wire T_254;
+ wire T_255;
+ wire T_257;
+ wire T_259;
+ wire T_260;
+ wire T_261;
+ wire T_263;
+ wire T_265;
+ wire T_266;
+ wire T_267;
+ wire T_268;
+ wire T_270;
+ wire T_272;
+ wire T_273;
+ wire T_274;
+ wire T_275;
+ wire T_276;
+ wire T_278;
+ wire T_280;
+ wire T_281;
+ wire T_282;
+ wire T_283;
+ wire T_284;
+ wire T_285;
+ wire T_287;
+ wire T_289;
+ wire T_290;
+ wire T_291;
+ wire T_292;
+ wire T_293;
+ wire T_294;
+ wire T_295;
+ wire T_297;
+ wire T_299;
+ wire T_300;
+ wire T_301;
+ wire T_302;
+ wire T_303;
+ wire T_304;
+ wire T_305;
+ wire T_306;
+ wire T_308;
+ wire T_310;
+ wire T_311;
+ wire T_312;
+ wire T_313;
+ wire T_314;
+ wire T_315;
+ wire T_316;
+ wire T_317;
+ wire T_318;
+ wire T_320;
+ wire T_322;
+ wire T_323;
+ wire T_324;
+ wire T_326;
+ wire T_327;
+ wire T_328;
+ wire T_330;
+ wire T_331;
+ wire T_332;
+ wire T_334;
+ wire T_335;
+ wire T_336;
+ wire T_338;
+ wire T_339;
+ wire T_340;
+ wire T_342;
+ wire T_343;
+ wire T_344;
+ wire T_346;
+ wire T_347;
+ wire T_348;
+ wire T_350;
+ wire T_351;
+ wire T_352;
+ wire T_354;
+ wire T_355;
+ wire T_356;
+ wire T_358;
+ wire T_359;
+ wire T_360;
+ wire [2:0] T_363;
+ wire [2:0] T_365;
+ wire [2:0] T_367;
+ wire [2:0] T_369;
+ wire T_371;
+ wire T_372;
+ wire [2:0] T_374;
+ wire T_376;
+ wire T_377;
+ wire [2:0] T_379;
+ wire T_381;
+ wire T_382;
+ wire [2:0] T_384;
+ wire T_386;
+ wire T_387;
+ wire [2:0] T_389;
+ wire [2:0] T_390;
+ wire T_391;
+ wire GEN_5;
+ wire GEN_6;
+ wire GEN_7;
+ wire GEN_8;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ wire GEN_17;
+ wire GEN_18;
+ wire GEN_19;
+ wire GEN_20;
+ assign io_in_0_ready = T_344;
+ assign io_in_1_ready = T_348;
+ assign io_in_2_ready = T_352;
+ assign io_in_3_ready = T_356;
+ assign io_in_4_ready = T_360;
+ assign io_out_valid = GEN_0;
+ assign io_out_bits_resp = GEN_1;
+ assign io_out_bits_id = GEN_2;
+ assign io_out_bits_user = GEN_3;
+ assign io_chosen = T_196;
+ assign T_196 = T_390;
+ assign GEN_0 = GEN_5 ? io_in_4_valid : GEN_6 ? io_in_3_valid : GEN_7 ? io_in_2_valid : GEN_8 ? io_in_1_valid : io_in_0_valid;
+ assign GEN_1 = GEN_9 ? io_in_4_bits_resp : GEN_10 ? io_in_3_bits_resp : GEN_11 ? io_in_2_bits_resp : GEN_12 ? io_in_1_bits_resp : io_in_0_bits_resp;
+ assign GEN_2 = GEN_13 ? io_in_4_bits_id : GEN_14 ? io_in_3_bits_id : GEN_15 ? io_in_2_bits_id : GEN_16 ? io_in_1_bits_id : io_in_0_bits_id;
+ assign GEN_3 = GEN_17 ? io_in_4_bits_user : GEN_18 ? io_in_3_bits_user : GEN_19 ? io_in_2_bits_user : GEN_20 ? io_in_1_bits_user : io_in_0_bits_user;
+ assign GEN_4 = 1'h0;
+ assign T_234 = 1'h0 > T_233;
+ assign T_235 = io_in_0_valid & T_234;
+ assign T_237 = 1'h1 > T_233;
+ assign T_238 = io_in_1_valid & T_237;
+ assign T_240 = 2'h2 > T_233;
+ assign T_241 = io_in_2_valid & T_240;
+ assign T_243 = 2'h3 > T_233;
+ assign T_244 = io_in_3_valid & T_243;
+ assign T_246 = 3'h4 > T_233;
+ assign T_247 = io_in_4_valid & T_246;
+ assign T_250 = 1'h0 | T_235;
+ assign T_252 = T_250 == 1'h0;
+ assign T_254 = 1'h0 | T_235;
+ assign T_255 = T_254 | T_238;
+ assign T_257 = T_255 == 1'h0;
+ assign T_259 = 1'h0 | T_235;
+ assign T_260 = T_259 | T_238;
+ assign T_261 = T_260 | T_241;
+ assign T_263 = T_261 == 1'h0;
+ assign T_265 = 1'h0 | T_235;
+ assign T_266 = T_265 | T_238;
+ assign T_267 = T_266 | T_241;
+ assign T_268 = T_267 | T_244;
+ assign T_270 = T_268 == 1'h0;
+ assign T_272 = 1'h0 | T_235;
+ assign T_273 = T_272 | T_238;
+ assign T_274 = T_273 | T_241;
+ assign T_275 = T_274 | T_244;
+ assign T_276 = T_275 | T_247;
+ assign T_278 = T_276 == 1'h0;
+ assign T_280 = 1'h0 | T_235;
+ assign T_281 = T_280 | T_238;
+ assign T_282 = T_281 | T_241;
+ assign T_283 = T_282 | T_244;
+ assign T_284 = T_283 | T_247;
+ assign T_285 = T_284 | io_in_0_valid;
+ assign T_287 = T_285 == 1'h0;
+ assign T_289 = 1'h0 | T_235;
+ assign T_290 = T_289 | T_238;
+ assign T_291 = T_290 | T_241;
+ assign T_292 = T_291 | T_244;
+ assign T_293 = T_292 | T_247;
+ assign T_294 = T_293 | io_in_0_valid;
+ assign T_295 = T_294 | io_in_1_valid;
+ assign T_297 = T_295 == 1'h0;
+ assign T_299 = 1'h0 | T_235;
+ assign T_300 = T_299 | T_238;
+ assign T_301 = T_300 | T_241;
+ assign T_302 = T_301 | T_244;
+ assign T_303 = T_302 | T_247;
+ assign T_304 = T_303 | io_in_0_valid;
+ assign T_305 = T_304 | io_in_1_valid;
+ assign T_306 = T_305 | io_in_2_valid;
+ assign T_308 = T_306 == 1'h0;
+ assign T_310 = 1'h0 | T_235;
+ assign T_311 = T_310 | T_238;
+ assign T_312 = T_311 | T_241;
+ assign T_313 = T_312 | T_244;
+ assign T_314 = T_313 | T_247;
+ assign T_315 = T_314 | io_in_0_valid;
+ assign T_316 = T_315 | io_in_1_valid;
+ assign T_317 = T_316 | io_in_2_valid;
+ assign T_318 = T_317 | io_in_3_valid;
+ assign T_320 = T_318 == 1'h0;
+ assign T_322 = 1'h0 > T_233;
+ assign T_323 = 1'h1 & T_322;
+ assign T_324 = T_323 | T_278;
+ assign T_326 = 1'h1 > T_233;
+ assign T_327 = T_252 & T_326;
+ assign T_328 = T_327 | T_287;
+ assign T_330 = 2'h2 > T_233;
+ assign T_331 = T_257 & T_330;
+ assign T_332 = T_331 | T_297;
+ assign T_334 = 2'h3 > T_233;
+ assign T_335 = T_263 & T_334;
+ assign T_336 = T_335 | T_308;
+ assign T_338 = 3'h4 > T_233;
+ assign T_339 = T_270 & T_338;
+ assign T_340 = T_339 | T_320;
+ assign T_342 = 3'h4 == 1'h0;
+ assign T_343 = 1'h0 ? T_342 : T_324;
+ assign T_344 = T_343 & io_out_ready;
+ assign T_346 = 3'h4 == 1'h1;
+ assign T_347 = 1'h0 ? T_346 : T_328;
+ assign T_348 = T_347 & io_out_ready;
+ assign T_350 = 3'h4 == 2'h2;
+ assign T_351 = 1'h0 ? T_350 : T_332;
+ assign T_352 = T_351 & io_out_ready;
+ assign T_354 = 3'h4 == 2'h3;
+ assign T_355 = 1'h0 ? T_354 : T_336;
+ assign T_356 = T_355 & io_out_ready;
+ assign T_358 = 3'h4 == 3'h4;
+ assign T_359 = 1'h0 ? T_358 : T_340;
+ assign T_360 = T_359 & io_out_ready;
+ assign T_363 = io_in_3_valid ? 2'h3 : 3'h4;
+ assign T_365 = io_in_2_valid ? 2'h2 : T_363;
+ assign T_367 = io_in_1_valid ? 1'h1 : T_365;
+ assign T_369 = io_in_0_valid ? 1'h0 : T_367;
+ assign T_371 = 3'h4 > T_233;
+ assign T_372 = io_in_4_valid & T_371;
+ assign T_374 = T_372 ? 3'h4 : T_369;
+ assign T_376 = 2'h3 > T_233;
+ assign T_377 = io_in_3_valid & T_376;
+ assign T_379 = T_377 ? 2'h3 : T_374;
+ assign T_381 = 2'h2 > T_233;
+ assign T_382 = io_in_2_valid & T_381;
+ assign T_384 = T_382 ? 2'h2 : T_379;
+ assign T_386 = 1'h1 > T_233;
+ assign T_387 = io_in_1_valid & T_386;
+ assign T_389 = T_387 ? 1'h1 : T_384;
+ assign T_390 = 1'h0 ? 3'h4 : T_389;
+ assign T_391 = io_out_ready & io_out_valid;
+ assign GEN_5 = 3'h4 == T_196;
+ assign GEN_6 = 2'h3 == T_196;
+ assign GEN_7 = 2'h2 == T_196;
+ assign GEN_8 = 1'h1 == T_196;
+ assign GEN_9 = 3'h4 == T_196;
+ assign GEN_10 = 2'h3 == T_196;
+ assign GEN_11 = 2'h2 == T_196;
+ assign GEN_12 = 1'h1 == T_196;
+ assign GEN_13 = 3'h4 == T_196;
+ assign GEN_14 = 2'h3 == T_196;
+ assign GEN_15 = 2'h2 == T_196;
+ assign GEN_16 = 1'h1 == T_196;
+ assign GEN_17 = 3'h4 == T_196;
+ assign GEN_18 = 2'h3 == T_196;
+ assign GEN_19 = 2'h2 == T_196;
+ assign GEN_20 = 1'h1 == T_196;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_233 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ T_233 <= 3'h0;
+ end else begin
+ if(T_391) begin
+ T_233 <= T_196;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module JunctionsPeekingArbiter(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input [1:0] io_in_0_bits_resp,
+ input [63:0] io_in_0_bits_data,
+ input io_in_0_bits_last,
+ input [4:0] io_in_0_bits_id,
+ input io_in_0_bits_user,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input [1:0] io_in_1_bits_resp,
+ input [63:0] io_in_1_bits_data,
+ input io_in_1_bits_last,
+ input [4:0] io_in_1_bits_id,
+ input io_in_1_bits_user,
+ output io_in_2_ready,
+ input io_in_2_valid,
+ input [1:0] io_in_2_bits_resp,
+ input [63:0] io_in_2_bits_data,
+ input io_in_2_bits_last,
+ input [4:0] io_in_2_bits_id,
+ input io_in_2_bits_user,
+ output io_in_3_ready,
+ input io_in_3_valid,
+ input [1:0] io_in_3_bits_resp,
+ input [63:0] io_in_3_bits_data,
+ input io_in_3_bits_last,
+ input [4:0] io_in_3_bits_id,
+ input io_in_3_bits_user,
+ output io_in_4_ready,
+ input io_in_4_valid,
+ input [1:0] io_in_4_bits_resp,
+ input [63:0] io_in_4_bits_data,
+ input io_in_4_bits_last,
+ input [4:0] io_in_4_bits_id,
+ input io_in_4_bits_user,
+ input io_out_ready,
+ output io_out_valid,
+ output [1:0] io_out_bits_resp,
+ output [63:0] io_out_bits_data,
+ output io_out_bits_last,
+ output [4:0] io_out_bits_id,
+ output io_out_bits_user
+);
+ reg [2:0] T_273;
+ reg T_275;
+ wire T_277_0;
+ wire T_277_1;
+ wire T_277_2;
+ wire T_277_3;
+ wire T_277_4;
+ wire [3:0] T_285;
+ wire [2:0] T_286;
+ wire T_288;
+ wire [3:0] T_290;
+ wire [2:0] T_291;
+ wire [3:0] T_294;
+ wire [2:0] T_295;
+ wire GEN_0;
+ wire GEN_1;
+ wire T_297;
+ wire T_299;
+ wire [3:0] T_301;
+ wire [2:0] T_302;
+ wire [3:0] T_305;
+ wire [2:0] T_306;
+ wire GEN_2;
+ wire GEN_3;
+ wire T_308;
+ wire T_310;
+ wire [3:0] T_312;
+ wire [2:0] T_313;
+ wire [3:0] T_316;
+ wire [2:0] T_317;
+ wire GEN_4;
+ wire GEN_5;
+ wire T_319;
+ wire T_321;
+ wire [3:0] T_323;
+ wire [2:0] T_324;
+ wire [3:0] T_327;
+ wire [2:0] T_328;
+ wire GEN_6;
+ wire GEN_7;
+ wire T_330;
+ wire T_332;
+ wire [3:0] T_334;
+ wire [2:0] T_335;
+ wire [3:0] T_338;
+ wire [2:0] T_339;
+ wire GEN_8;
+ wire GEN_9;
+ wire T_341;
+ wire T_343_0;
+ wire T_343_1;
+ wire T_343_2;
+ wire T_343_3;
+ wire T_343_4;
+ wire [2:0] T_356_0;
+ wire [2:0] T_356_1;
+ wire [2:0] T_356_2;
+ wire [2:0] T_356_3;
+ wire [2:0] T_356_4;
+ wire [3:0] T_364;
+ wire [2:0] T_365;
+ wire T_367;
+ wire [3:0] T_369;
+ wire [2:0] T_370;
+ wire [3:0] T_373;
+ wire [2:0] T_374;
+ wire [2:0] GEN_10;
+ wire [2:0] GEN_11;
+ wire [2:0] T_376;
+ wire T_378;
+ wire [3:0] T_380;
+ wire [2:0] T_381;
+ wire [3:0] T_384;
+ wire [2:0] T_385;
+ wire [2:0] GEN_12;
+ wire [2:0] GEN_13;
+ wire [2:0] T_387;
+ wire T_389;
+ wire [3:0] T_391;
+ wire [2:0] T_392;
+ wire [3:0] T_395;
+ wire [2:0] T_396;
+ wire [2:0] GEN_14;
+ wire [2:0] GEN_15;
+ wire [2:0] T_398;
+ wire T_400;
+ wire [3:0] T_402;
+ wire [2:0] T_403;
+ wire [3:0] T_406;
+ wire [2:0] T_407;
+ wire [2:0] GEN_16;
+ wire [2:0] GEN_17;
+ wire [2:0] T_409;
+ wire T_411;
+ wire [3:0] T_413;
+ wire [2:0] T_414;
+ wire [3:0] T_417;
+ wire [2:0] T_418;
+ wire [2:0] GEN_18;
+ wire [2:0] GEN_19;
+ wire [2:0] T_420;
+ wire [2:0] T_422_0;
+ wire [2:0] T_422_1;
+ wire [2:0] T_422_2;
+ wire [2:0] T_422_3;
+ wire [2:0] T_422_4;
+ wire [2:0] T_429;
+ wire [2:0] T_430;
+ wire [2:0] T_431;
+ wire [2:0] T_432;
+ wire [2:0] T_433;
+ wire T_435;
+ wire T_436;
+ wire T_438;
+ wire T_439;
+ wire T_441;
+ wire T_442;
+ wire T_444;
+ wire T_445;
+ wire T_447;
+ wire T_448;
+ wire GEN_20;
+ wire [1:0] GEN_21;
+ wire [63:0] GEN_22;
+ wire GEN_23;
+ wire [4:0] GEN_24;
+ wire GEN_25;
+ wire T_479;
+ wire T_481;
+ wire T_483;
+ wire GEN_26;
+ wire GEN_27;
+ wire GEN_28;
+ wire GEN_29;
+ wire GEN_30;
+ wire GEN_31;
+ wire GEN_32;
+ wire GEN_33;
+ wire GEN_34;
+ wire GEN_35;
+ wire GEN_36;
+ wire GEN_37;
+ wire GEN_38;
+ wire GEN_39;
+ wire GEN_40;
+ wire GEN_41;
+ wire GEN_42;
+ wire GEN_43;
+ wire GEN_44;
+ wire GEN_45;
+ wire GEN_46;
+ wire GEN_47;
+ wire GEN_48;
+ wire GEN_49;
+ wire GEN_50;
+ wire GEN_51;
+ wire GEN_52;
+ wire GEN_53;
+ wire GEN_54;
+ wire GEN_55;
+ wire GEN_56;
+ wire GEN_57;
+ wire GEN_58;
+ wire GEN_59;
+ wire GEN_60;
+ wire GEN_61;
+ wire GEN_62;
+ wire GEN_63;
+ wire GEN_64;
+ wire GEN_65;
+ wire GEN_66;
+ wire GEN_67;
+ wire GEN_68;
+ wire GEN_69;
+ wire GEN_70;
+ wire GEN_71;
+ wire GEN_72;
+ wire GEN_73;
+ wire GEN_74;
+ wire GEN_75;
+ wire GEN_76;
+ wire GEN_77;
+ wire GEN_78;
+ wire GEN_79;
+ wire GEN_80;
+ wire GEN_81;
+ wire GEN_82;
+ wire GEN_83;
+ wire GEN_84;
+ wire GEN_85;
+ wire GEN_86;
+ wire GEN_87;
+ wire GEN_88;
+ wire GEN_89;
+ wire GEN_90;
+ wire GEN_91;
+ wire GEN_92;
+ wire GEN_93;
+ wire GEN_94;
+ wire GEN_95;
+ wire GEN_96;
+ wire GEN_97;
+ wire GEN_98;
+ wire GEN_99;
+ wire GEN_100;
+ wire GEN_101;
+ wire GEN_102;
+ wire GEN_103;
+ wire GEN_104;
+ wire GEN_105;
+ wire GEN_106;
+ wire GEN_107;
+ wire GEN_108;
+ wire GEN_109;
+ wire GEN_110;
+ wire GEN_111;
+ wire GEN_112;
+ wire GEN_113;
+ wire GEN_114;
+ wire GEN_115;
+ wire GEN_116;
+ wire GEN_117;
+ wire GEN_118;
+ wire GEN_119;
+ wire GEN_120;
+ wire GEN_121;
+ wire GEN_122;
+ wire GEN_123;
+ wire GEN_124;
+ wire GEN_125;
+ wire GEN_126;
+ wire GEN_127;
+ wire GEN_128;
+ wire GEN_129;
+ assign io_in_0_ready = T_436;
+ assign io_in_1_ready = T_439;
+ assign io_in_2_ready = T_442;
+ assign io_in_3_ready = T_445;
+ assign io_in_4_ready = T_448;
+ assign io_out_valid = GEN_20;
+ assign io_out_bits_resp = GEN_21;
+ assign io_out_bits_data = GEN_22;
+ assign io_out_bits_last = GEN_23;
+ assign io_out_bits_id = GEN_24;
+ assign io_out_bits_user = GEN_25;
+ assign T_277_0 = io_in_0_valid;
+ assign T_277_1 = io_in_1_valid;
+ assign T_277_2 = io_in_2_valid;
+ assign T_277_3 = io_in_3_valid;
+ assign T_277_4 = io_in_4_valid;
+ assign T_285 = T_273 + 1'h1;
+ assign T_286 = T_285[2:0];
+ assign T_288 = T_286 < 3'h5;
+ assign T_290 = 1'h0 + T_286;
+ assign T_291 = T_290[2:0];
+ assign T_294 = T_286 - 3'h5;
+ assign T_295 = T_294[2:0];
+ assign GEN_0 = GEN_26 ? T_277_4 : GEN_27 ? T_277_3 : GEN_28 ? T_277_2 : GEN_29 ? T_277_1 : T_277_0;
+ assign GEN_1 = GEN_30 ? T_277_4 : GEN_31 ? T_277_3 : GEN_32 ? T_277_2 : GEN_33 ? T_277_1 : T_277_0;
+ assign T_297 = T_288 ? GEN_0 : GEN_1;
+ assign T_299 = T_286 < 3'h4;
+ assign T_301 = 1'h1 + T_286;
+ assign T_302 = T_301[2:0];
+ assign T_305 = T_286 - 3'h4;
+ assign T_306 = T_305[2:0];
+ assign GEN_2 = GEN_34 ? T_277_4 : GEN_35 ? T_277_3 : GEN_36 ? T_277_2 : GEN_37 ? T_277_1 : T_277_0;
+ assign GEN_3 = GEN_38 ? T_277_4 : GEN_39 ? T_277_3 : GEN_40 ? T_277_2 : GEN_41 ? T_277_1 : T_277_0;
+ assign T_308 = T_299 ? GEN_2 : GEN_3;
+ assign T_310 = T_286 < 2'h3;
+ assign T_312 = 2'h2 + T_286;
+ assign T_313 = T_312[2:0];
+ assign T_316 = T_286 - 2'h3;
+ assign T_317 = T_316[2:0];
+ assign GEN_4 = GEN_42 ? T_277_4 : GEN_43 ? T_277_3 : GEN_44 ? T_277_2 : GEN_45 ? T_277_1 : T_277_0;
+ assign GEN_5 = GEN_46 ? T_277_4 : GEN_47 ? T_277_3 : GEN_48 ? T_277_2 : GEN_49 ? T_277_1 : T_277_0;
+ assign T_319 = T_310 ? GEN_4 : GEN_5;
+ assign T_321 = T_286 < 2'h2;
+ assign T_323 = 2'h3 + T_286;
+ assign T_324 = T_323[2:0];
+ assign T_327 = T_286 - 2'h2;
+ assign T_328 = T_327[2:0];
+ assign GEN_6 = GEN_50 ? T_277_4 : GEN_51 ? T_277_3 : GEN_52 ? T_277_2 : GEN_53 ? T_277_1 : T_277_0;
+ assign GEN_7 = GEN_54 ? T_277_4 : GEN_55 ? T_277_3 : GEN_56 ? T_277_2 : GEN_57 ? T_277_1 : T_277_0;
+ assign T_330 = T_321 ? GEN_6 : GEN_7;
+ assign T_332 = T_286 < 1'h1;
+ assign T_334 = 3'h4 + T_286;
+ assign T_335 = T_334[2:0];
+ assign T_338 = T_286 - 1'h1;
+ assign T_339 = T_338[2:0];
+ assign GEN_8 = GEN_58 ? T_277_4 : GEN_59 ? T_277_3 : GEN_60 ? T_277_2 : GEN_61 ? T_277_1 : T_277_0;
+ assign GEN_9 = GEN_62 ? T_277_4 : GEN_63 ? T_277_3 : GEN_64 ? T_277_2 : GEN_65 ? T_277_1 : T_277_0;
+ assign T_341 = T_332 ? GEN_8 : GEN_9;
+ assign T_343_0 = T_297;
+ assign T_343_1 = T_308;
+ assign T_343_2 = T_319;
+ assign T_343_3 = T_330;
+ assign T_343_4 = T_341;
+ assign T_356_0 = 1'h0;
+ assign T_356_1 = 1'h1;
+ assign T_356_2 = 2'h2;
+ assign T_356_3 = 2'h3;
+ assign T_356_4 = 3'h4;
+ assign T_364 = T_273 + 1'h1;
+ assign T_365 = T_364[2:0];
+ assign T_367 = T_365 < 3'h5;
+ assign T_369 = 1'h0 + T_365;
+ assign T_370 = T_369[2:0];
+ assign T_373 = T_365 - 3'h5;
+ assign T_374 = T_373[2:0];
+ assign GEN_10 = GEN_66 ? T_356_4 : GEN_67 ? T_356_3 : GEN_68 ? T_356_2 : GEN_69 ? T_356_1 : T_356_0;
+ assign GEN_11 = GEN_70 ? T_356_4 : GEN_71 ? T_356_3 : GEN_72 ? T_356_2 : GEN_73 ? T_356_1 : T_356_0;
+ assign T_376 = T_367 ? GEN_10 : GEN_11;
+ assign T_378 = T_365 < 3'h4;
+ assign T_380 = 1'h1 + T_365;
+ assign T_381 = T_380[2:0];
+ assign T_384 = T_365 - 3'h4;
+ assign T_385 = T_384[2:0];
+ assign GEN_12 = GEN_74 ? T_356_4 : GEN_75 ? T_356_3 : GEN_76 ? T_356_2 : GEN_77 ? T_356_1 : T_356_0;
+ assign GEN_13 = GEN_78 ? T_356_4 : GEN_79 ? T_356_3 : GEN_80 ? T_356_2 : GEN_81 ? T_356_1 : T_356_0;
+ assign T_387 = T_378 ? GEN_12 : GEN_13;
+ assign T_389 = T_365 < 2'h3;
+ assign T_391 = 2'h2 + T_365;
+ assign T_392 = T_391[2:0];
+ assign T_395 = T_365 - 2'h3;
+ assign T_396 = T_395[2:0];
+ assign GEN_14 = GEN_82 ? T_356_4 : GEN_83 ? T_356_3 : GEN_84 ? T_356_2 : GEN_85 ? T_356_1 : T_356_0;
+ assign GEN_15 = GEN_86 ? T_356_4 : GEN_87 ? T_356_3 : GEN_88 ? T_356_2 : GEN_89 ? T_356_1 : T_356_0;
+ assign T_398 = T_389 ? GEN_14 : GEN_15;
+ assign T_400 = T_365 < 2'h2;
+ assign T_402 = 2'h3 + T_365;
+ assign T_403 = T_402[2:0];
+ assign T_406 = T_365 - 2'h2;
+ assign T_407 = T_406[2:0];
+ assign GEN_16 = GEN_90 ? T_356_4 : GEN_91 ? T_356_3 : GEN_92 ? T_356_2 : GEN_93 ? T_356_1 : T_356_0;
+ assign GEN_17 = GEN_94 ? T_356_4 : GEN_95 ? T_356_3 : GEN_96 ? T_356_2 : GEN_97 ? T_356_1 : T_356_0;
+ assign T_409 = T_400 ? GEN_16 : GEN_17;
+ assign T_411 = T_365 < 1'h1;
+ assign T_413 = 3'h4 + T_365;
+ assign T_414 = T_413[2:0];
+ assign T_417 = T_365 - 1'h1;
+ assign T_418 = T_417[2:0];
+ assign GEN_18 = GEN_98 ? T_356_4 : GEN_99 ? T_356_3 : GEN_100 ? T_356_2 : GEN_101 ? T_356_1 : T_356_0;
+ assign GEN_19 = GEN_102 ? T_356_4 : GEN_103 ? T_356_3 : GEN_104 ? T_356_2 : GEN_105 ? T_356_1 : T_356_0;
+ assign T_420 = T_411 ? GEN_18 : GEN_19;
+ assign T_422_0 = T_376;
+ assign T_422_1 = T_387;
+ assign T_422_2 = T_398;
+ assign T_422_3 = T_409;
+ assign T_422_4 = T_420;
+ assign T_429 = T_343_3 ? T_422_3 : T_422_4;
+ assign T_430 = T_343_2 ? T_422_2 : T_429;
+ assign T_431 = T_343_1 ? T_422_1 : T_430;
+ assign T_432 = T_343_0 ? T_422_0 : T_431;
+ assign T_433 = T_275 ? T_273 : T_432;
+ assign T_435 = T_433 == 1'h0;
+ assign T_436 = io_out_ready & T_435;
+ assign T_438 = T_433 == 1'h1;
+ assign T_439 = io_out_ready & T_438;
+ assign T_441 = T_433 == 2'h2;
+ assign T_442 = io_out_ready & T_441;
+ assign T_444 = T_433 == 2'h3;
+ assign T_445 = io_out_ready & T_444;
+ assign T_447 = T_433 == 3'h4;
+ assign T_448 = io_out_ready & T_447;
+ assign GEN_20 = GEN_106 ? io_in_4_valid : GEN_107 ? io_in_3_valid : GEN_108 ? io_in_2_valid : GEN_109 ? io_in_1_valid : io_in_0_valid;
+ assign GEN_21 = GEN_110 ? io_in_4_bits_resp : GEN_111 ? io_in_3_bits_resp : GEN_112 ? io_in_2_bits_resp : GEN_113 ? io_in_1_bits_resp : io_in_0_bits_resp;
+ assign GEN_22 = GEN_114 ? io_in_4_bits_data : GEN_115 ? io_in_3_bits_data : GEN_116 ? io_in_2_bits_data : GEN_117 ? io_in_1_bits_data : io_in_0_bits_data;
+ assign GEN_23 = GEN_118 ? io_in_4_bits_last : GEN_119 ? io_in_3_bits_last : GEN_120 ? io_in_2_bits_last : GEN_121 ? io_in_1_bits_last : io_in_0_bits_last;
+ assign GEN_24 = GEN_122 ? io_in_4_bits_id : GEN_123 ? io_in_3_bits_id : GEN_124 ? io_in_2_bits_id : GEN_125 ? io_in_1_bits_id : io_in_0_bits_id;
+ assign GEN_25 = GEN_126 ? io_in_4_bits_user : GEN_127 ? io_in_3_bits_user : GEN_128 ? io_in_2_bits_user : GEN_129 ? io_in_1_bits_user : io_in_0_bits_user;
+ assign T_479 = io_out_ready & io_out_valid;
+ assign T_481 = T_275 == 1'h0;
+ assign T_483 = T_481 & 1'h1;
+ assign GEN_26 = 3'h4 == T_291;
+ assign GEN_27 = 2'h3 == T_291;
+ assign GEN_28 = 2'h2 == T_291;
+ assign GEN_29 = 1'h1 == T_291;
+ assign GEN_30 = 3'h4 == T_295;
+ assign GEN_31 = 2'h3 == T_295;
+ assign GEN_32 = 2'h2 == T_295;
+ assign GEN_33 = 1'h1 == T_295;
+ assign GEN_34 = 3'h4 == T_302;
+ assign GEN_35 = 2'h3 == T_302;
+ assign GEN_36 = 2'h2 == T_302;
+ assign GEN_37 = 1'h1 == T_302;
+ assign GEN_38 = 3'h4 == T_306;
+ assign GEN_39 = 2'h3 == T_306;
+ assign GEN_40 = 2'h2 == T_306;
+ assign GEN_41 = 1'h1 == T_306;
+ assign GEN_42 = 3'h4 == T_313;
+ assign GEN_43 = 2'h3 == T_313;
+ assign GEN_44 = 2'h2 == T_313;
+ assign GEN_45 = 1'h1 == T_313;
+ assign GEN_46 = 3'h4 == T_317;
+ assign GEN_47 = 2'h3 == T_317;
+ assign GEN_48 = 2'h2 == T_317;
+ assign GEN_49 = 1'h1 == T_317;
+ assign GEN_50 = 3'h4 == T_324;
+ assign GEN_51 = 2'h3 == T_324;
+ assign GEN_52 = 2'h2 == T_324;
+ assign GEN_53 = 1'h1 == T_324;
+ assign GEN_54 = 3'h4 == T_328;
+ assign GEN_55 = 2'h3 == T_328;
+ assign GEN_56 = 2'h2 == T_328;
+ assign GEN_57 = 1'h1 == T_328;
+ assign GEN_58 = 3'h4 == T_335;
+ assign GEN_59 = 2'h3 == T_335;
+ assign GEN_60 = 2'h2 == T_335;
+ assign GEN_61 = 1'h1 == T_335;
+ assign GEN_62 = 3'h4 == T_339;
+ assign GEN_63 = 2'h3 == T_339;
+ assign GEN_64 = 2'h2 == T_339;
+ assign GEN_65 = 1'h1 == T_339;
+ assign GEN_66 = 3'h4 == T_370;
+ assign GEN_67 = 2'h3 == T_370;
+ assign GEN_68 = 2'h2 == T_370;
+ assign GEN_69 = 1'h1 == T_370;
+ assign GEN_70 = 3'h4 == T_374;
+ assign GEN_71 = 2'h3 == T_374;
+ assign GEN_72 = 2'h2 == T_374;
+ assign GEN_73 = 1'h1 == T_374;
+ assign GEN_74 = 3'h4 == T_381;
+ assign GEN_75 = 2'h3 == T_381;
+ assign GEN_76 = 2'h2 == T_381;
+ assign GEN_77 = 1'h1 == T_381;
+ assign GEN_78 = 3'h4 == T_385;
+ assign GEN_79 = 2'h3 == T_385;
+ assign GEN_80 = 2'h2 == T_385;
+ assign GEN_81 = 1'h1 == T_385;
+ assign GEN_82 = 3'h4 == T_392;
+ assign GEN_83 = 2'h3 == T_392;
+ assign GEN_84 = 2'h2 == T_392;
+ assign GEN_85 = 1'h1 == T_392;
+ assign GEN_86 = 3'h4 == T_396;
+ assign GEN_87 = 2'h3 == T_396;
+ assign GEN_88 = 2'h2 == T_396;
+ assign GEN_89 = 1'h1 == T_396;
+ assign GEN_90 = 3'h4 == T_403;
+ assign GEN_91 = 2'h3 == T_403;
+ assign GEN_92 = 2'h2 == T_403;
+ assign GEN_93 = 1'h1 == T_403;
+ assign GEN_94 = 3'h4 == T_407;
+ assign GEN_95 = 2'h3 == T_407;
+ assign GEN_96 = 2'h2 == T_407;
+ assign GEN_97 = 1'h1 == T_407;
+ assign GEN_98 = 3'h4 == T_414;
+ assign GEN_99 = 2'h3 == T_414;
+ assign GEN_100 = 2'h2 == T_414;
+ assign GEN_101 = 1'h1 == T_414;
+ assign GEN_102 = 3'h4 == T_418;
+ assign GEN_103 = 2'h3 == T_418;
+ assign GEN_104 = 2'h2 == T_418;
+ assign GEN_105 = 1'h1 == T_418;
+ assign GEN_106 = 3'h4 == T_433;
+ assign GEN_107 = 2'h3 == T_433;
+ assign GEN_108 = 2'h2 == T_433;
+ assign GEN_109 = 1'h1 == T_433;
+ assign GEN_110 = 3'h4 == T_433;
+ assign GEN_111 = 2'h3 == T_433;
+ assign GEN_112 = 2'h2 == T_433;
+ assign GEN_113 = 1'h1 == T_433;
+ assign GEN_114 = 3'h4 == T_433;
+ assign GEN_115 = 2'h3 == T_433;
+ assign GEN_116 = 2'h2 == T_433;
+ assign GEN_117 = 1'h1 == T_433;
+ assign GEN_118 = 3'h4 == T_433;
+ assign GEN_119 = 2'h3 == T_433;
+ assign GEN_120 = 2'h2 == T_433;
+ assign GEN_121 = 1'h1 == T_433;
+ assign GEN_122 = 3'h4 == T_433;
+ assign GEN_123 = 2'h3 == T_433;
+ assign GEN_124 = 2'h2 == T_433;
+ assign GEN_125 = 1'h1 == T_433;
+ assign GEN_126 = 3'h4 == T_433;
+ assign GEN_127 = 2'h3 == T_433;
+ assign GEN_128 = 2'h2 == T_433;
+ assign GEN_129 = 1'h1 == T_433;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_273 = {1{$random}};
+ T_275 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ T_273 <= 3'h0;
+ end else begin
+ if(T_479) begin
+ if(T_483) begin
+ T_273 <= T_432;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_275 <= 1'h0;
+ end else begin
+ if(T_479) begin
+ if(io_out_bits_last) begin
+ T_275 <= 1'h0;
+ end else begin
+ if(T_483) begin
+ T_275 <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module NastiRouter(
+ input clk,
+ input reset,
+ output io_master_aw_ready,
+ input io_master_aw_valid,
+ input [31:0] io_master_aw_bits_addr,
+ input [7:0] io_master_aw_bits_len,
+ input [2:0] io_master_aw_bits_size,
+ input [1:0] io_master_aw_bits_burst,
+ input io_master_aw_bits_lock,
+ input [3:0] io_master_aw_bits_cache,
+ input [2:0] io_master_aw_bits_prot,
+ input [3:0] io_master_aw_bits_qos,
+ input [3:0] io_master_aw_bits_region,
+ input [4:0] io_master_aw_bits_id,
+ input io_master_aw_bits_user,
+ output io_master_w_ready,
+ input io_master_w_valid,
+ input [63:0] io_master_w_bits_data,
+ input io_master_w_bits_last,
+ input [7:0] io_master_w_bits_strb,
+ input io_master_w_bits_user,
+ input io_master_b_ready,
+ output io_master_b_valid,
+ output [1:0] io_master_b_bits_resp,
+ output [4:0] io_master_b_bits_id,
+ output io_master_b_bits_user,
+ output io_master_ar_ready,
+ input io_master_ar_valid,
+ input [31:0] io_master_ar_bits_addr,
+ input [7:0] io_master_ar_bits_len,
+ input [2:0] io_master_ar_bits_size,
+ input [1:0] io_master_ar_bits_burst,
+ input io_master_ar_bits_lock,
+ input [3:0] io_master_ar_bits_cache,
+ input [2:0] io_master_ar_bits_prot,
+ input [3:0] io_master_ar_bits_qos,
+ input [3:0] io_master_ar_bits_region,
+ input [4:0] io_master_ar_bits_id,
+ input io_master_ar_bits_user,
+ input io_master_r_ready,
+ output io_master_r_valid,
+ output [1:0] io_master_r_bits_resp,
+ output [63:0] io_master_r_bits_data,
+ output io_master_r_bits_last,
+ output [4:0] io_master_r_bits_id,
+ output io_master_r_bits_user,
+ input io_slave_0_aw_ready,
+ output io_slave_0_aw_valid,
+ output [31:0] io_slave_0_aw_bits_addr,
+ output [7:0] io_slave_0_aw_bits_len,
+ output [2:0] io_slave_0_aw_bits_size,
+ output [1:0] io_slave_0_aw_bits_burst,
+ output io_slave_0_aw_bits_lock,
+ output [3:0] io_slave_0_aw_bits_cache,
+ output [2:0] io_slave_0_aw_bits_prot,
+ output [3:0] io_slave_0_aw_bits_qos,
+ output [3:0] io_slave_0_aw_bits_region,
+ output [4:0] io_slave_0_aw_bits_id,
+ output io_slave_0_aw_bits_user,
+ input io_slave_0_w_ready,
+ output io_slave_0_w_valid,
+ output [63:0] io_slave_0_w_bits_data,
+ output io_slave_0_w_bits_last,
+ output [7:0] io_slave_0_w_bits_strb,
+ output io_slave_0_w_bits_user,
+ output io_slave_0_b_ready,
+ input io_slave_0_b_valid,
+ input [1:0] io_slave_0_b_bits_resp,
+ input [4:0] io_slave_0_b_bits_id,
+ input io_slave_0_b_bits_user,
+ input io_slave_0_ar_ready,
+ output io_slave_0_ar_valid,
+ output [31:0] io_slave_0_ar_bits_addr,
+ output [7:0] io_slave_0_ar_bits_len,
+ output [2:0] io_slave_0_ar_bits_size,
+ output [1:0] io_slave_0_ar_bits_burst,
+ output io_slave_0_ar_bits_lock,
+ output [3:0] io_slave_0_ar_bits_cache,
+ output [2:0] io_slave_0_ar_bits_prot,
+ output [3:0] io_slave_0_ar_bits_qos,
+ output [3:0] io_slave_0_ar_bits_region,
+ output [4:0] io_slave_0_ar_bits_id,
+ output io_slave_0_ar_bits_user,
+ output io_slave_0_r_ready,
+ input io_slave_0_r_valid,
+ input [1:0] io_slave_0_r_bits_resp,
+ input [63:0] io_slave_0_r_bits_data,
+ input io_slave_0_r_bits_last,
+ input [4:0] io_slave_0_r_bits_id,
+ input io_slave_0_r_bits_user,
+ input io_slave_1_aw_ready,
+ output io_slave_1_aw_valid,
+ output [31:0] io_slave_1_aw_bits_addr,
+ output [7:0] io_slave_1_aw_bits_len,
+ output [2:0] io_slave_1_aw_bits_size,
+ output [1:0] io_slave_1_aw_bits_burst,
+ output io_slave_1_aw_bits_lock,
+ output [3:0] io_slave_1_aw_bits_cache,
+ output [2:0] io_slave_1_aw_bits_prot,
+ output [3:0] io_slave_1_aw_bits_qos,
+ output [3:0] io_slave_1_aw_bits_region,
+ output [4:0] io_slave_1_aw_bits_id,
+ output io_slave_1_aw_bits_user,
+ input io_slave_1_w_ready,
+ output io_slave_1_w_valid,
+ output [63:0] io_slave_1_w_bits_data,
+ output io_slave_1_w_bits_last,
+ output [7:0] io_slave_1_w_bits_strb,
+ output io_slave_1_w_bits_user,
+ output io_slave_1_b_ready,
+ input io_slave_1_b_valid,
+ input [1:0] io_slave_1_b_bits_resp,
+ input [4:0] io_slave_1_b_bits_id,
+ input io_slave_1_b_bits_user,
+ input io_slave_1_ar_ready,
+ output io_slave_1_ar_valid,
+ output [31:0] io_slave_1_ar_bits_addr,
+ output [7:0] io_slave_1_ar_bits_len,
+ output [2:0] io_slave_1_ar_bits_size,
+ output [1:0] io_slave_1_ar_bits_burst,
+ output io_slave_1_ar_bits_lock,
+ output [3:0] io_slave_1_ar_bits_cache,
+ output [2:0] io_slave_1_ar_bits_prot,
+ output [3:0] io_slave_1_ar_bits_qos,
+ output [3:0] io_slave_1_ar_bits_region,
+ output [4:0] io_slave_1_ar_bits_id,
+ output io_slave_1_ar_bits_user,
+ output io_slave_1_r_ready,
+ input io_slave_1_r_valid,
+ input [1:0] io_slave_1_r_bits_resp,
+ input [63:0] io_slave_1_r_bits_data,
+ input io_slave_1_r_bits_last,
+ input [4:0] io_slave_1_r_bits_id,
+ input io_slave_1_r_bits_user,
+ input io_slave_2_aw_ready,
+ output io_slave_2_aw_valid,
+ output [31:0] io_slave_2_aw_bits_addr,
+ output [7:0] io_slave_2_aw_bits_len,
+ output [2:0] io_slave_2_aw_bits_size,
+ output [1:0] io_slave_2_aw_bits_burst,
+ output io_slave_2_aw_bits_lock,
+ output [3:0] io_slave_2_aw_bits_cache,
+ output [2:0] io_slave_2_aw_bits_prot,
+ output [3:0] io_slave_2_aw_bits_qos,
+ output [3:0] io_slave_2_aw_bits_region,
+ output [4:0] io_slave_2_aw_bits_id,
+ output io_slave_2_aw_bits_user,
+ input io_slave_2_w_ready,
+ output io_slave_2_w_valid,
+ output [63:0] io_slave_2_w_bits_data,
+ output io_slave_2_w_bits_last,
+ output [7:0] io_slave_2_w_bits_strb,
+ output io_slave_2_w_bits_user,
+ output io_slave_2_b_ready,
+ input io_slave_2_b_valid,
+ input [1:0] io_slave_2_b_bits_resp,
+ input [4:0] io_slave_2_b_bits_id,
+ input io_slave_2_b_bits_user,
+ input io_slave_2_ar_ready,
+ output io_slave_2_ar_valid,
+ output [31:0] io_slave_2_ar_bits_addr,
+ output [7:0] io_slave_2_ar_bits_len,
+ output [2:0] io_slave_2_ar_bits_size,
+ output [1:0] io_slave_2_ar_bits_burst,
+ output io_slave_2_ar_bits_lock,
+ output [3:0] io_slave_2_ar_bits_cache,
+ output [2:0] io_slave_2_ar_bits_prot,
+ output [3:0] io_slave_2_ar_bits_qos,
+ output [3:0] io_slave_2_ar_bits_region,
+ output [4:0] io_slave_2_ar_bits_id,
+ output io_slave_2_ar_bits_user,
+ output io_slave_2_r_ready,
+ input io_slave_2_r_valid,
+ input [1:0] io_slave_2_r_bits_resp,
+ input [63:0] io_slave_2_r_bits_data,
+ input io_slave_2_r_bits_last,
+ input [4:0] io_slave_2_r_bits_id,
+ input io_slave_2_r_bits_user,
+ input io_slave_3_aw_ready,
+ output io_slave_3_aw_valid,
+ output [31:0] io_slave_3_aw_bits_addr,
+ output [7:0] io_slave_3_aw_bits_len,
+ output [2:0] io_slave_3_aw_bits_size,
+ output [1:0] io_slave_3_aw_bits_burst,
+ output io_slave_3_aw_bits_lock,
+ output [3:0] io_slave_3_aw_bits_cache,
+ output [2:0] io_slave_3_aw_bits_prot,
+ output [3:0] io_slave_3_aw_bits_qos,
+ output [3:0] io_slave_3_aw_bits_region,
+ output [4:0] io_slave_3_aw_bits_id,
+ output io_slave_3_aw_bits_user,
+ input io_slave_3_w_ready,
+ output io_slave_3_w_valid,
+ output [63:0] io_slave_3_w_bits_data,
+ output io_slave_3_w_bits_last,
+ output [7:0] io_slave_3_w_bits_strb,
+ output io_slave_3_w_bits_user,
+ output io_slave_3_b_ready,
+ input io_slave_3_b_valid,
+ input [1:0] io_slave_3_b_bits_resp,
+ input [4:0] io_slave_3_b_bits_id,
+ input io_slave_3_b_bits_user,
+ input io_slave_3_ar_ready,
+ output io_slave_3_ar_valid,
+ output [31:0] io_slave_3_ar_bits_addr,
+ output [7:0] io_slave_3_ar_bits_len,
+ output [2:0] io_slave_3_ar_bits_size,
+ output [1:0] io_slave_3_ar_bits_burst,
+ output io_slave_3_ar_bits_lock,
+ output [3:0] io_slave_3_ar_bits_cache,
+ output [2:0] io_slave_3_ar_bits_prot,
+ output [3:0] io_slave_3_ar_bits_qos,
+ output [3:0] io_slave_3_ar_bits_region,
+ output [4:0] io_slave_3_ar_bits_id,
+ output io_slave_3_ar_bits_user,
+ output io_slave_3_r_ready,
+ input io_slave_3_r_valid,
+ input [1:0] io_slave_3_r_bits_resp,
+ input [63:0] io_slave_3_r_bits_data,
+ input io_slave_3_r_bits_last,
+ input [4:0] io_slave_3_r_bits_id,
+ input io_slave_3_r_bits_user
+);
+ wire T_1437;
+ wire T_1439;
+ wire T_1440;
+ wire T_1442;
+ wire T_1444;
+ wire T_1445;
+ wire T_1447;
+ wire T_1449;
+ wire T_1450;
+ wire T_1452;
+ wire T_1454;
+ wire T_1455;
+ wire T_1457_0;
+ wire T_1457_1;
+ wire T_1457_2;
+ wire T_1457_3;
+ wire [1:0] T_1463;
+ wire [1:0] T_1464;
+ wire [3:0] ar_route;
+ wire T_1467;
+ wire T_1469;
+ wire T_1470;
+ wire T_1472;
+ wire T_1474;
+ wire T_1475;
+ wire T_1477;
+ wire T_1479;
+ wire T_1480;
+ wire T_1482;
+ wire T_1484;
+ wire T_1485;
+ wire T_1487_0;
+ wire T_1487_1;
+ wire T_1487_2;
+ wire T_1487_3;
+ wire [1:0] T_1493;
+ wire [1:0] T_1494;
+ wire [3:0] aw_route;
+ wire T_1499;
+ wire T_1500;
+ wire T_1501;
+ wire T_1502;
+ wire T_1503;
+ wire T_1504;
+ wire T_1505;
+ wire T_1506;
+ wire T_1507;
+ wire T_1508;
+ reg T_1510;
+ wire T_1511;
+ wire T_1513;
+ wire T_1514;
+ wire T_1516;
+ wire T_1517;
+ wire T_1518;
+ wire T_1519;
+ wire T_1520;
+ wire T_1521;
+ wire T_1522;
+ wire T_1523;
+ wire T_1524;
+ wire T_1525;
+ wire T_1526;
+ wire T_1527;
+ wire T_1528;
+ reg T_1530;
+ wire T_1531;
+ wire T_1533;
+ wire T_1534;
+ wire T_1536;
+ wire T_1537;
+ wire T_1538;
+ wire T_1539;
+ wire T_1540;
+ wire T_1541;
+ wire T_1542;
+ wire T_1543;
+ wire T_1544;
+ wire T_1545;
+ wire T_1546;
+ wire T_1547;
+ wire T_1548;
+ reg T_1550;
+ wire T_1551;
+ wire T_1553;
+ wire T_1554;
+ wire T_1556;
+ wire T_1557;
+ wire T_1558;
+ wire T_1559;
+ wire T_1560;
+ wire T_1561;
+ wire T_1562;
+ wire ar_ready;
+ wire T_1564;
+ wire T_1565;
+ wire T_1566;
+ wire T_1567;
+ wire aw_ready;
+ reg T_1570;
+ wire T_1571;
+ wire T_1573;
+ wire T_1574;
+ wire T_1576;
+ wire T_1577;
+ wire w_ready;
+ wire T_1580;
+ wire r_invalid;
+ wire T_1584;
+ wire w_invalid;
+ wire err_slave_clk;
+ wire err_slave_reset;
+ wire err_slave_io_aw_ready;
+ wire err_slave_io_aw_valid;
+ wire [31:0] err_slave_io_aw_bits_addr;
+ wire [7:0] err_slave_io_aw_bits_len;
+ wire [2:0] err_slave_io_aw_bits_size;
+ wire [1:0] err_slave_io_aw_bits_burst;
+ wire err_slave_io_aw_bits_lock;
+ wire [3:0] err_slave_io_aw_bits_cache;
+ wire [2:0] err_slave_io_aw_bits_prot;
+ wire [3:0] err_slave_io_aw_bits_qos;
+ wire [3:0] err_slave_io_aw_bits_region;
+ wire [4:0] err_slave_io_aw_bits_id;
+ wire err_slave_io_aw_bits_user;
+ wire err_slave_io_w_ready;
+ wire err_slave_io_w_valid;
+ wire [63:0] err_slave_io_w_bits_data;
+ wire err_slave_io_w_bits_last;
+ wire [7:0] err_slave_io_w_bits_strb;
+ wire err_slave_io_w_bits_user;
+ wire err_slave_io_b_ready;
+ wire err_slave_io_b_valid;
+ wire [1:0] err_slave_io_b_bits_resp;
+ wire [4:0] err_slave_io_b_bits_id;
+ wire err_slave_io_b_bits_user;
+ wire err_slave_io_ar_ready;
+ wire err_slave_io_ar_valid;
+ wire [31:0] err_slave_io_ar_bits_addr;
+ wire [7:0] err_slave_io_ar_bits_len;
+ wire [2:0] err_slave_io_ar_bits_size;
+ wire [1:0] err_slave_io_ar_bits_burst;
+ wire err_slave_io_ar_bits_lock;
+ wire [3:0] err_slave_io_ar_bits_cache;
+ wire [2:0] err_slave_io_ar_bits_prot;
+ wire [3:0] err_slave_io_ar_bits_qos;
+ wire [3:0] err_slave_io_ar_bits_region;
+ wire [4:0] err_slave_io_ar_bits_id;
+ wire err_slave_io_ar_bits_user;
+ wire err_slave_io_r_ready;
+ wire err_slave_io_r_valid;
+ wire [1:0] err_slave_io_r_bits_resp;
+ wire [63:0] err_slave_io_r_bits_data;
+ wire err_slave_io_r_bits_last;
+ wire [4:0] err_slave_io_r_bits_id;
+ wire err_slave_io_r_bits_user;
+ wire T_1588;
+ wire T_1589;
+ wire T_1590;
+ wire T_1591;
+ wire T_1592;
+ wire T_1593;
+ wire T_1594;
+ wire b_arb_clk;
+ wire b_arb_reset;
+ wire b_arb_io_in_0_ready;
+ wire b_arb_io_in_0_valid;
+ wire [1:0] b_arb_io_in_0_bits_resp;
+ wire [4:0] b_arb_io_in_0_bits_id;
+ wire b_arb_io_in_0_bits_user;
+ wire b_arb_io_in_1_ready;
+ wire b_arb_io_in_1_valid;
+ wire [1:0] b_arb_io_in_1_bits_resp;
+ wire [4:0] b_arb_io_in_1_bits_id;
+ wire b_arb_io_in_1_bits_user;
+ wire b_arb_io_in_2_ready;
+ wire b_arb_io_in_2_valid;
+ wire [1:0] b_arb_io_in_2_bits_resp;
+ wire [4:0] b_arb_io_in_2_bits_id;
+ wire b_arb_io_in_2_bits_user;
+ wire b_arb_io_in_3_ready;
+ wire b_arb_io_in_3_valid;
+ wire [1:0] b_arb_io_in_3_bits_resp;
+ wire [4:0] b_arb_io_in_3_bits_id;
+ wire b_arb_io_in_3_bits_user;
+ wire b_arb_io_in_4_ready;
+ wire b_arb_io_in_4_valid;
+ wire [1:0] b_arb_io_in_4_bits_resp;
+ wire [4:0] b_arb_io_in_4_bits_id;
+ wire b_arb_io_in_4_bits_user;
+ wire b_arb_io_out_ready;
+ wire b_arb_io_out_valid;
+ wire [1:0] b_arb_io_out_bits_resp;
+ wire [4:0] b_arb_io_out_bits_id;
+ wire b_arb_io_out_bits_user;
+ wire [2:0] b_arb_io_chosen;
+ wire r_arb_clk;
+ wire r_arb_reset;
+ wire r_arb_io_in_0_ready;
+ wire r_arb_io_in_0_valid;
+ wire [1:0] r_arb_io_in_0_bits_resp;
+ wire [63:0] r_arb_io_in_0_bits_data;
+ wire r_arb_io_in_0_bits_last;
+ wire [4:0] r_arb_io_in_0_bits_id;
+ wire r_arb_io_in_0_bits_user;
+ wire r_arb_io_in_1_ready;
+ wire r_arb_io_in_1_valid;
+ wire [1:0] r_arb_io_in_1_bits_resp;
+ wire [63:0] r_arb_io_in_1_bits_data;
+ wire r_arb_io_in_1_bits_last;
+ wire [4:0] r_arb_io_in_1_bits_id;
+ wire r_arb_io_in_1_bits_user;
+ wire r_arb_io_in_2_ready;
+ wire r_arb_io_in_2_valid;
+ wire [1:0] r_arb_io_in_2_bits_resp;
+ wire [63:0] r_arb_io_in_2_bits_data;
+ wire r_arb_io_in_2_bits_last;
+ wire [4:0] r_arb_io_in_2_bits_id;
+ wire r_arb_io_in_2_bits_user;
+ wire r_arb_io_in_3_ready;
+ wire r_arb_io_in_3_valid;
+ wire [1:0] r_arb_io_in_3_bits_resp;
+ wire [63:0] r_arb_io_in_3_bits_data;
+ wire r_arb_io_in_3_bits_last;
+ wire [4:0] r_arb_io_in_3_bits_id;
+ wire r_arb_io_in_3_bits_user;
+ wire r_arb_io_in_4_ready;
+ wire r_arb_io_in_4_valid;
+ wire [1:0] r_arb_io_in_4_bits_resp;
+ wire [63:0] r_arb_io_in_4_bits_data;
+ wire r_arb_io_in_4_bits_last;
+ wire [4:0] r_arb_io_in_4_bits_id;
+ wire r_arb_io_in_4_bits_user;
+ wire r_arb_io_out_ready;
+ wire r_arb_io_out_valid;
+ wire [1:0] r_arb_io_out_bits_resp;
+ wire [63:0] r_arb_io_out_bits_data;
+ wire r_arb_io_out_bits_last;
+ wire [4:0] r_arb_io_out_bits_id;
+ wire r_arb_io_out_bits_user;
+ NastiErrorSlave err_slave (
+ .clk(err_slave_clk),
+ .reset(err_slave_reset),
+ .io_aw_ready(err_slave_io_aw_ready),
+ .io_aw_valid(err_slave_io_aw_valid),
+ .io_aw_bits_addr(err_slave_io_aw_bits_addr),
+ .io_aw_bits_len(err_slave_io_aw_bits_len),
+ .io_aw_bits_size(err_slave_io_aw_bits_size),
+ .io_aw_bits_burst(err_slave_io_aw_bits_burst),
+ .io_aw_bits_lock(err_slave_io_aw_bits_lock),
+ .io_aw_bits_cache(err_slave_io_aw_bits_cache),
+ .io_aw_bits_prot(err_slave_io_aw_bits_prot),
+ .io_aw_bits_qos(err_slave_io_aw_bits_qos),
+ .io_aw_bits_region(err_slave_io_aw_bits_region),
+ .io_aw_bits_id(err_slave_io_aw_bits_id),
+ .io_aw_bits_user(err_slave_io_aw_bits_user),
+ .io_w_ready(err_slave_io_w_ready),
+ .io_w_valid(err_slave_io_w_valid),
+ .io_w_bits_data(err_slave_io_w_bits_data),
+ .io_w_bits_last(err_slave_io_w_bits_last),
+ .io_w_bits_strb(err_slave_io_w_bits_strb),
+ .io_w_bits_user(err_slave_io_w_bits_user),
+ .io_b_ready(err_slave_io_b_ready),
+ .io_b_valid(err_slave_io_b_valid),
+ .io_b_bits_resp(err_slave_io_b_bits_resp),
+ .io_b_bits_id(err_slave_io_b_bits_id),
+ .io_b_bits_user(err_slave_io_b_bits_user),
+ .io_ar_ready(err_slave_io_ar_ready),
+ .io_ar_valid(err_slave_io_ar_valid),
+ .io_ar_bits_addr(err_slave_io_ar_bits_addr),
+ .io_ar_bits_len(err_slave_io_ar_bits_len),
+ .io_ar_bits_size(err_slave_io_ar_bits_size),
+ .io_ar_bits_burst(err_slave_io_ar_bits_burst),
+ .io_ar_bits_lock(err_slave_io_ar_bits_lock),
+ .io_ar_bits_cache(err_slave_io_ar_bits_cache),
+ .io_ar_bits_prot(err_slave_io_ar_bits_prot),
+ .io_ar_bits_qos(err_slave_io_ar_bits_qos),
+ .io_ar_bits_region(err_slave_io_ar_bits_region),
+ .io_ar_bits_id(err_slave_io_ar_bits_id),
+ .io_ar_bits_user(err_slave_io_ar_bits_user),
+ .io_r_ready(err_slave_io_r_ready),
+ .io_r_valid(err_slave_io_r_valid),
+ .io_r_bits_resp(err_slave_io_r_bits_resp),
+ .io_r_bits_data(err_slave_io_r_bits_data),
+ .io_r_bits_last(err_slave_io_r_bits_last),
+ .io_r_bits_id(err_slave_io_r_bits_id),
+ .io_r_bits_user(err_slave_io_r_bits_user)
+ );
+ RRArbiter_38 b_arb (
+ .clk(b_arb_clk),
+ .reset(b_arb_reset),
+ .io_in_0_ready(b_arb_io_in_0_ready),
+ .io_in_0_valid(b_arb_io_in_0_valid),
+ .io_in_0_bits_resp(b_arb_io_in_0_bits_resp),
+ .io_in_0_bits_id(b_arb_io_in_0_bits_id),
+ .io_in_0_bits_user(b_arb_io_in_0_bits_user),
+ .io_in_1_ready(b_arb_io_in_1_ready),
+ .io_in_1_valid(b_arb_io_in_1_valid),
+ .io_in_1_bits_resp(b_arb_io_in_1_bits_resp),
+ .io_in_1_bits_id(b_arb_io_in_1_bits_id),
+ .io_in_1_bits_user(b_arb_io_in_1_bits_user),
+ .io_in_2_ready(b_arb_io_in_2_ready),
+ .io_in_2_valid(b_arb_io_in_2_valid),
+ .io_in_2_bits_resp(b_arb_io_in_2_bits_resp),
+ .io_in_2_bits_id(b_arb_io_in_2_bits_id),
+ .io_in_2_bits_user(b_arb_io_in_2_bits_user),
+ .io_in_3_ready(b_arb_io_in_3_ready),
+ .io_in_3_valid(b_arb_io_in_3_valid),
+ .io_in_3_bits_resp(b_arb_io_in_3_bits_resp),
+ .io_in_3_bits_id(b_arb_io_in_3_bits_id),
+ .io_in_3_bits_user(b_arb_io_in_3_bits_user),
+ .io_in_4_ready(b_arb_io_in_4_ready),
+ .io_in_4_valid(b_arb_io_in_4_valid),
+ .io_in_4_bits_resp(b_arb_io_in_4_bits_resp),
+ .io_in_4_bits_id(b_arb_io_in_4_bits_id),
+ .io_in_4_bits_user(b_arb_io_in_4_bits_user),
+ .io_out_ready(b_arb_io_out_ready),
+ .io_out_valid(b_arb_io_out_valid),
+ .io_out_bits_resp(b_arb_io_out_bits_resp),
+ .io_out_bits_id(b_arb_io_out_bits_id),
+ .io_out_bits_user(b_arb_io_out_bits_user),
+ .io_chosen(b_arb_io_chosen)
+ );
+ JunctionsPeekingArbiter r_arb (
+ .clk(r_arb_clk),
+ .reset(r_arb_reset),
+ .io_in_0_ready(r_arb_io_in_0_ready),
+ .io_in_0_valid(r_arb_io_in_0_valid),
+ .io_in_0_bits_resp(r_arb_io_in_0_bits_resp),
+ .io_in_0_bits_data(r_arb_io_in_0_bits_data),
+ .io_in_0_bits_last(r_arb_io_in_0_bits_last),
+ .io_in_0_bits_id(r_arb_io_in_0_bits_id),
+ .io_in_0_bits_user(r_arb_io_in_0_bits_user),
+ .io_in_1_ready(r_arb_io_in_1_ready),
+ .io_in_1_valid(r_arb_io_in_1_valid),
+ .io_in_1_bits_resp(r_arb_io_in_1_bits_resp),
+ .io_in_1_bits_data(r_arb_io_in_1_bits_data),
+ .io_in_1_bits_last(r_arb_io_in_1_bits_last),
+ .io_in_1_bits_id(r_arb_io_in_1_bits_id),
+ .io_in_1_bits_user(r_arb_io_in_1_bits_user),
+ .io_in_2_ready(r_arb_io_in_2_ready),
+ .io_in_2_valid(r_arb_io_in_2_valid),
+ .io_in_2_bits_resp(r_arb_io_in_2_bits_resp),
+ .io_in_2_bits_data(r_arb_io_in_2_bits_data),
+ .io_in_2_bits_last(r_arb_io_in_2_bits_last),
+ .io_in_2_bits_id(r_arb_io_in_2_bits_id),
+ .io_in_2_bits_user(r_arb_io_in_2_bits_user),
+ .io_in_3_ready(r_arb_io_in_3_ready),
+ .io_in_3_valid(r_arb_io_in_3_valid),
+ .io_in_3_bits_resp(r_arb_io_in_3_bits_resp),
+ .io_in_3_bits_data(r_arb_io_in_3_bits_data),
+ .io_in_3_bits_last(r_arb_io_in_3_bits_last),
+ .io_in_3_bits_id(r_arb_io_in_3_bits_id),
+ .io_in_3_bits_user(r_arb_io_in_3_bits_user),
+ .io_in_4_ready(r_arb_io_in_4_ready),
+ .io_in_4_valid(r_arb_io_in_4_valid),
+ .io_in_4_bits_resp(r_arb_io_in_4_bits_resp),
+ .io_in_4_bits_data(r_arb_io_in_4_bits_data),
+ .io_in_4_bits_last(r_arb_io_in_4_bits_last),
+ .io_in_4_bits_id(r_arb_io_in_4_bits_id),
+ .io_in_4_bits_user(r_arb_io_in_4_bits_user),
+ .io_out_ready(r_arb_io_out_ready),
+ .io_out_valid(r_arb_io_out_valid),
+ .io_out_bits_resp(r_arb_io_out_bits_resp),
+ .io_out_bits_data(r_arb_io_out_bits_data),
+ .io_out_bits_last(r_arb_io_out_bits_last),
+ .io_out_bits_id(r_arb_io_out_bits_id),
+ .io_out_bits_user(r_arb_io_out_bits_user)
+ );
+ assign io_master_aw_ready = T_1593;
+ assign io_master_w_ready = T_1594;
+ assign io_master_b_valid = b_arb_io_out_valid;
+ assign io_master_b_bits_resp = b_arb_io_out_bits_resp;
+ assign io_master_b_bits_id = b_arb_io_out_bits_id;
+ assign io_master_b_bits_user = b_arb_io_out_bits_user;
+ assign io_master_ar_ready = T_1591;
+ assign io_master_r_valid = r_arb_io_out_valid;
+ assign io_master_r_bits_resp = r_arb_io_out_bits_resp;
+ assign io_master_r_bits_data = r_arb_io_out_bits_data;
+ assign io_master_r_bits_last = r_arb_io_out_bits_last;
+ assign io_master_r_bits_id = r_arb_io_out_bits_id;
+ assign io_master_r_bits_user = r_arb_io_out_bits_user;
+ assign io_slave_0_aw_valid = T_1505;
+ assign io_slave_0_aw_bits_addr = io_master_aw_bits_addr;
+ assign io_slave_0_aw_bits_len = io_master_aw_bits_len;
+ assign io_slave_0_aw_bits_size = io_master_aw_bits_size;
+ assign io_slave_0_aw_bits_burst = io_master_aw_bits_burst;
+ assign io_slave_0_aw_bits_lock = io_master_aw_bits_lock;
+ assign io_slave_0_aw_bits_cache = io_master_aw_bits_cache;
+ assign io_slave_0_aw_bits_prot = io_master_aw_bits_prot;
+ assign io_slave_0_aw_bits_qos = io_master_aw_bits_qos;
+ assign io_slave_0_aw_bits_region = io_master_aw_bits_region;
+ assign io_slave_0_aw_bits_id = io_master_aw_bits_id;
+ assign io_slave_0_aw_bits_user = io_master_aw_bits_user;
+ assign io_slave_0_w_valid = T_1516;
+ assign io_slave_0_w_bits_data = io_master_w_bits_data;
+ assign io_slave_0_w_bits_last = io_master_w_bits_last;
+ assign io_slave_0_w_bits_strb = io_master_w_bits_strb;
+ assign io_slave_0_w_bits_user = io_master_w_bits_user;
+ assign io_slave_0_b_ready = b_arb_io_in_0_ready;
+ assign io_slave_0_ar_valid = T_1500;
+ assign io_slave_0_ar_bits_addr = io_master_ar_bits_addr;
+ assign io_slave_0_ar_bits_len = io_master_ar_bits_len;
+ assign io_slave_0_ar_bits_size = io_master_ar_bits_size;
+ assign io_slave_0_ar_bits_burst = io_master_ar_bits_burst;
+ assign io_slave_0_ar_bits_lock = io_master_ar_bits_lock;
+ assign io_slave_0_ar_bits_cache = io_master_ar_bits_cache;
+ assign io_slave_0_ar_bits_prot = io_master_ar_bits_prot;
+ assign io_slave_0_ar_bits_qos = io_master_ar_bits_qos;
+ assign io_slave_0_ar_bits_region = io_master_ar_bits_region;
+ assign io_slave_0_ar_bits_id = io_master_ar_bits_id;
+ assign io_slave_0_ar_bits_user = io_master_ar_bits_user;
+ assign io_slave_0_r_ready = r_arb_io_in_0_ready;
+ assign io_slave_1_aw_valid = T_1525;
+ assign io_slave_1_aw_bits_addr = io_master_aw_bits_addr;
+ assign io_slave_1_aw_bits_len = io_master_aw_bits_len;
+ assign io_slave_1_aw_bits_size = io_master_aw_bits_size;
+ assign io_slave_1_aw_bits_burst = io_master_aw_bits_burst;
+ assign io_slave_1_aw_bits_lock = io_master_aw_bits_lock;
+ assign io_slave_1_aw_bits_cache = io_master_aw_bits_cache;
+ assign io_slave_1_aw_bits_prot = io_master_aw_bits_prot;
+ assign io_slave_1_aw_bits_qos = io_master_aw_bits_qos;
+ assign io_slave_1_aw_bits_region = io_master_aw_bits_region;
+ assign io_slave_1_aw_bits_id = io_master_aw_bits_id;
+ assign io_slave_1_aw_bits_user = io_master_aw_bits_user;
+ assign io_slave_1_w_valid = T_1536;
+ assign io_slave_1_w_bits_data = io_master_w_bits_data;
+ assign io_slave_1_w_bits_last = io_master_w_bits_last;
+ assign io_slave_1_w_bits_strb = io_master_w_bits_strb;
+ assign io_slave_1_w_bits_user = io_master_w_bits_user;
+ assign io_slave_1_b_ready = b_arb_io_in_1_ready;
+ assign io_slave_1_ar_valid = T_1520;
+ assign io_slave_1_ar_bits_addr = io_master_ar_bits_addr;
+ assign io_slave_1_ar_bits_len = io_master_ar_bits_len;
+ assign io_slave_1_ar_bits_size = io_master_ar_bits_size;
+ assign io_slave_1_ar_bits_burst = io_master_ar_bits_burst;
+ assign io_slave_1_ar_bits_lock = io_master_ar_bits_lock;
+ assign io_slave_1_ar_bits_cache = io_master_ar_bits_cache;
+ assign io_slave_1_ar_bits_prot = io_master_ar_bits_prot;
+ assign io_slave_1_ar_bits_qos = io_master_ar_bits_qos;
+ assign io_slave_1_ar_bits_region = io_master_ar_bits_region;
+ assign io_slave_1_ar_bits_id = io_master_ar_bits_id;
+ assign io_slave_1_ar_bits_user = io_master_ar_bits_user;
+ assign io_slave_1_r_ready = r_arb_io_in_1_ready;
+ assign io_slave_2_aw_valid = T_1545;
+ assign io_slave_2_aw_bits_addr = io_master_aw_bits_addr;
+ assign io_slave_2_aw_bits_len = io_master_aw_bits_len;
+ assign io_slave_2_aw_bits_size = io_master_aw_bits_size;
+ assign io_slave_2_aw_bits_burst = io_master_aw_bits_burst;
+ assign io_slave_2_aw_bits_lock = io_master_aw_bits_lock;
+ assign io_slave_2_aw_bits_cache = io_master_aw_bits_cache;
+ assign io_slave_2_aw_bits_prot = io_master_aw_bits_prot;
+ assign io_slave_2_aw_bits_qos = io_master_aw_bits_qos;
+ assign io_slave_2_aw_bits_region = io_master_aw_bits_region;
+ assign io_slave_2_aw_bits_id = io_master_aw_bits_id;
+ assign io_slave_2_aw_bits_user = io_master_aw_bits_user;
+ assign io_slave_2_w_valid = T_1556;
+ assign io_slave_2_w_bits_data = io_master_w_bits_data;
+ assign io_slave_2_w_bits_last = io_master_w_bits_last;
+ assign io_slave_2_w_bits_strb = io_master_w_bits_strb;
+ assign io_slave_2_w_bits_user = io_master_w_bits_user;
+ assign io_slave_2_b_ready = b_arb_io_in_2_ready;
+ assign io_slave_2_ar_valid = T_1540;
+ assign io_slave_2_ar_bits_addr = io_master_ar_bits_addr;
+ assign io_slave_2_ar_bits_len = io_master_ar_bits_len;
+ assign io_slave_2_ar_bits_size = io_master_ar_bits_size;
+ assign io_slave_2_ar_bits_burst = io_master_ar_bits_burst;
+ assign io_slave_2_ar_bits_lock = io_master_ar_bits_lock;
+ assign io_slave_2_ar_bits_cache = io_master_ar_bits_cache;
+ assign io_slave_2_ar_bits_prot = io_master_ar_bits_prot;
+ assign io_slave_2_ar_bits_qos = io_master_ar_bits_qos;
+ assign io_slave_2_ar_bits_region = io_master_ar_bits_region;
+ assign io_slave_2_ar_bits_id = io_master_ar_bits_id;
+ assign io_slave_2_ar_bits_user = io_master_ar_bits_user;
+ assign io_slave_2_r_ready = r_arb_io_in_2_ready;
+ assign io_slave_3_aw_valid = T_1565;
+ assign io_slave_3_aw_bits_addr = io_master_aw_bits_addr;
+ assign io_slave_3_aw_bits_len = io_master_aw_bits_len;
+ assign io_slave_3_aw_bits_size = io_master_aw_bits_size;
+ assign io_slave_3_aw_bits_burst = io_master_aw_bits_burst;
+ assign io_slave_3_aw_bits_lock = io_master_aw_bits_lock;
+ assign io_slave_3_aw_bits_cache = io_master_aw_bits_cache;
+ assign io_slave_3_aw_bits_prot = io_master_aw_bits_prot;
+ assign io_slave_3_aw_bits_qos = io_master_aw_bits_qos;
+ assign io_slave_3_aw_bits_region = io_master_aw_bits_region;
+ assign io_slave_3_aw_bits_id = io_master_aw_bits_id;
+ assign io_slave_3_aw_bits_user = io_master_aw_bits_user;
+ assign io_slave_3_w_valid = T_1576;
+ assign io_slave_3_w_bits_data = io_master_w_bits_data;
+ assign io_slave_3_w_bits_last = io_master_w_bits_last;
+ assign io_slave_3_w_bits_strb = io_master_w_bits_strb;
+ assign io_slave_3_w_bits_user = io_master_w_bits_user;
+ assign io_slave_3_b_ready = b_arb_io_in_3_ready;
+ assign io_slave_3_ar_valid = T_1560;
+ assign io_slave_3_ar_bits_addr = io_master_ar_bits_addr;
+ assign io_slave_3_ar_bits_len = io_master_ar_bits_len;
+ assign io_slave_3_ar_bits_size = io_master_ar_bits_size;
+ assign io_slave_3_ar_bits_burst = io_master_ar_bits_burst;
+ assign io_slave_3_ar_bits_lock = io_master_ar_bits_lock;
+ assign io_slave_3_ar_bits_cache = io_master_ar_bits_cache;
+ assign io_slave_3_ar_bits_prot = io_master_ar_bits_prot;
+ assign io_slave_3_ar_bits_qos = io_master_ar_bits_qos;
+ assign io_slave_3_ar_bits_region = io_master_ar_bits_region;
+ assign io_slave_3_ar_bits_id = io_master_ar_bits_id;
+ assign io_slave_3_ar_bits_user = io_master_ar_bits_user;
+ assign io_slave_3_r_ready = r_arb_io_in_3_ready;
+ assign T_1437 = io_master_ar_bits_addr >= 1'h0;
+ assign T_1439 = io_master_ar_bits_addr < 31'h40000000;
+ assign T_1440 = T_1437 & T_1439;
+ assign T_1442 = io_master_ar_bits_addr >= 31'h40000000;
+ assign T_1444 = io_master_ar_bits_addr < 31'h60000000;
+ assign T_1445 = T_1442 & T_1444;
+ assign T_1447 = io_master_ar_bits_addr >= 31'h60000000;
+ assign T_1449 = io_master_ar_bits_addr < 32'h80000000;
+ assign T_1450 = T_1447 & T_1449;
+ assign T_1452 = io_master_ar_bits_addr >= 32'h80000000;
+ assign T_1454 = io_master_ar_bits_addr < 33'h100000000;
+ assign T_1455 = T_1452 & T_1454;
+ assign T_1457_0 = T_1440;
+ assign T_1457_1 = T_1445;
+ assign T_1457_2 = T_1450;
+ assign T_1457_3 = T_1455;
+ assign T_1463 = {T_1457_3,T_1457_2};
+ assign T_1464 = {T_1457_1,T_1457_0};
+ assign ar_route = {T_1463,T_1464};
+ assign T_1467 = io_master_aw_bits_addr >= 1'h0;
+ assign T_1469 = io_master_aw_bits_addr < 31'h40000000;
+ assign T_1470 = T_1467 & T_1469;
+ assign T_1472 = io_master_aw_bits_addr >= 31'h40000000;
+ assign T_1474 = io_master_aw_bits_addr < 31'h60000000;
+ assign T_1475 = T_1472 & T_1474;
+ assign T_1477 = io_master_aw_bits_addr >= 31'h60000000;
+ assign T_1479 = io_master_aw_bits_addr < 32'h80000000;
+ assign T_1480 = T_1477 & T_1479;
+ assign T_1482 = io_master_aw_bits_addr >= 32'h80000000;
+ assign T_1484 = io_master_aw_bits_addr < 33'h100000000;
+ assign T_1485 = T_1482 & T_1484;
+ assign T_1487_0 = T_1470;
+ assign T_1487_1 = T_1475;
+ assign T_1487_2 = T_1480;
+ assign T_1487_3 = T_1485;
+ assign T_1493 = {T_1487_3,T_1487_2};
+ assign T_1494 = {T_1487_1,T_1487_0};
+ assign aw_route = {T_1493,T_1494};
+ assign T_1499 = ar_route[0];
+ assign T_1500 = io_master_ar_valid & T_1499;
+ assign T_1501 = ar_route[0];
+ assign T_1502 = io_slave_0_ar_ready & T_1501;
+ assign T_1503 = 1'h0 | T_1502;
+ assign T_1504 = aw_route[0];
+ assign T_1505 = io_master_aw_valid & T_1504;
+ assign T_1506 = aw_route[0];
+ assign T_1507 = io_slave_0_aw_ready & T_1506;
+ assign T_1508 = 1'h0 | T_1507;
+ assign T_1511 = io_slave_0_aw_ready & io_slave_0_aw_valid;
+ assign T_1513 = io_slave_0_w_ready & io_slave_0_w_valid;
+ assign T_1514 = T_1513 & io_slave_0_w_bits_last;
+ assign T_1516 = io_master_w_valid & T_1510;
+ assign T_1517 = io_slave_0_w_ready & T_1510;
+ assign T_1518 = 1'h0 | T_1517;
+ assign T_1519 = ar_route[1];
+ assign T_1520 = io_master_ar_valid & T_1519;
+ assign T_1521 = ar_route[1];
+ assign T_1522 = io_slave_1_ar_ready & T_1521;
+ assign T_1523 = T_1503 | T_1522;
+ assign T_1524 = aw_route[1];
+ assign T_1525 = io_master_aw_valid & T_1524;
+ assign T_1526 = aw_route[1];
+ assign T_1527 = io_slave_1_aw_ready & T_1526;
+ assign T_1528 = T_1508 | T_1527;
+ assign T_1531 = io_slave_1_aw_ready & io_slave_1_aw_valid;
+ assign T_1533 = io_slave_1_w_ready & io_slave_1_w_valid;
+ assign T_1534 = T_1533 & io_slave_1_w_bits_last;
+ assign T_1536 = io_master_w_valid & T_1530;
+ assign T_1537 = io_slave_1_w_ready & T_1530;
+ assign T_1538 = T_1518 | T_1537;
+ assign T_1539 = ar_route[2];
+ assign T_1540 = io_master_ar_valid & T_1539;
+ assign T_1541 = ar_route[2];
+ assign T_1542 = io_slave_2_ar_ready & T_1541;
+ assign T_1543 = T_1523 | T_1542;
+ assign T_1544 = aw_route[2];
+ assign T_1545 = io_master_aw_valid & T_1544;
+ assign T_1546 = aw_route[2];
+ assign T_1547 = io_slave_2_aw_ready & T_1546;
+ assign T_1548 = T_1528 | T_1547;
+ assign T_1551 = io_slave_2_aw_ready & io_slave_2_aw_valid;
+ assign T_1553 = io_slave_2_w_ready & io_slave_2_w_valid;
+ assign T_1554 = T_1553 & io_slave_2_w_bits_last;
+ assign T_1556 = io_master_w_valid & T_1550;
+ assign T_1557 = io_slave_2_w_ready & T_1550;
+ assign T_1558 = T_1538 | T_1557;
+ assign T_1559 = ar_route[3];
+ assign T_1560 = io_master_ar_valid & T_1559;
+ assign T_1561 = ar_route[3];
+ assign T_1562 = io_slave_3_ar_ready & T_1561;
+ assign ar_ready = T_1543 | T_1562;
+ assign T_1564 = aw_route[3];
+ assign T_1565 = io_master_aw_valid & T_1564;
+ assign T_1566 = aw_route[3];
+ assign T_1567 = io_slave_3_aw_ready & T_1566;
+ assign aw_ready = T_1548 | T_1567;
+ assign T_1571 = io_slave_3_aw_ready & io_slave_3_aw_valid;
+ assign T_1573 = io_slave_3_w_ready & io_slave_3_w_valid;
+ assign T_1574 = T_1573 & io_slave_3_w_bits_last;
+ assign T_1576 = io_master_w_valid & T_1570;
+ assign T_1577 = io_slave_3_w_ready & T_1570;
+ assign w_ready = T_1558 | T_1577;
+ assign T_1580 = ar_route != 1'h0;
+ assign r_invalid = T_1580 == 1'h0;
+ assign T_1584 = aw_route != 1'h0;
+ assign w_invalid = T_1584 == 1'h0;
+ assign err_slave_clk = clk;
+ assign err_slave_reset = reset;
+ assign err_slave_io_aw_valid = T_1589;
+ assign err_slave_io_aw_bits_addr = io_master_aw_bits_addr;
+ assign err_slave_io_aw_bits_len = io_master_aw_bits_len;
+ assign err_slave_io_aw_bits_size = io_master_aw_bits_size;
+ assign err_slave_io_aw_bits_burst = io_master_aw_bits_burst;
+ assign err_slave_io_aw_bits_lock = io_master_aw_bits_lock;
+ assign err_slave_io_aw_bits_cache = io_master_aw_bits_cache;
+ assign err_slave_io_aw_bits_prot = io_master_aw_bits_prot;
+ assign err_slave_io_aw_bits_qos = io_master_aw_bits_qos;
+ assign err_slave_io_aw_bits_region = io_master_aw_bits_region;
+ assign err_slave_io_aw_bits_id = io_master_aw_bits_id;
+ assign err_slave_io_aw_bits_user = io_master_aw_bits_user;
+ assign err_slave_io_w_valid = io_master_w_valid;
+ assign err_slave_io_w_bits_data = io_master_w_bits_data;
+ assign err_slave_io_w_bits_last = io_master_w_bits_last;
+ assign err_slave_io_w_bits_strb = io_master_w_bits_strb;
+ assign err_slave_io_w_bits_user = io_master_w_bits_user;
+ assign err_slave_io_b_ready = b_arb_io_in_4_ready;
+ assign err_slave_io_ar_valid = T_1588;
+ assign err_slave_io_ar_bits_addr = io_master_ar_bits_addr;
+ assign err_slave_io_ar_bits_len = io_master_ar_bits_len;
+ assign err_slave_io_ar_bits_size = io_master_ar_bits_size;
+ assign err_slave_io_ar_bits_burst = io_master_ar_bits_burst;
+ assign err_slave_io_ar_bits_lock = io_master_ar_bits_lock;
+ assign err_slave_io_ar_bits_cache = io_master_ar_bits_cache;
+ assign err_slave_io_ar_bits_prot = io_master_ar_bits_prot;
+ assign err_slave_io_ar_bits_qos = io_master_ar_bits_qos;
+ assign err_slave_io_ar_bits_region = io_master_ar_bits_region;
+ assign err_slave_io_ar_bits_id = io_master_ar_bits_id;
+ assign err_slave_io_ar_bits_user = io_master_ar_bits_user;
+ assign err_slave_io_r_ready = r_arb_io_in_4_ready;
+ assign T_1588 = r_invalid & io_master_ar_valid;
+ assign T_1589 = w_invalid & io_master_aw_valid;
+ assign T_1590 = r_invalid & err_slave_io_ar_ready;
+ assign T_1591 = ar_ready | T_1590;
+ assign T_1592 = w_invalid & err_slave_io_aw_ready;
+ assign T_1593 = aw_ready | T_1592;
+ assign T_1594 = w_ready | err_slave_io_w_ready;
+ assign b_arb_clk = clk;
+ assign b_arb_reset = reset;
+ assign b_arb_io_in_0_valid = io_slave_0_b_valid;
+ assign b_arb_io_in_0_bits_resp = io_slave_0_b_bits_resp;
+ assign b_arb_io_in_0_bits_id = io_slave_0_b_bits_id;
+ assign b_arb_io_in_0_bits_user = io_slave_0_b_bits_user;
+ assign b_arb_io_in_1_valid = io_slave_1_b_valid;
+ assign b_arb_io_in_1_bits_resp = io_slave_1_b_bits_resp;
+ assign b_arb_io_in_1_bits_id = io_slave_1_b_bits_id;
+ assign b_arb_io_in_1_bits_user = io_slave_1_b_bits_user;
+ assign b_arb_io_in_2_valid = io_slave_2_b_valid;
+ assign b_arb_io_in_2_bits_resp = io_slave_2_b_bits_resp;
+ assign b_arb_io_in_2_bits_id = io_slave_2_b_bits_id;
+ assign b_arb_io_in_2_bits_user = io_slave_2_b_bits_user;
+ assign b_arb_io_in_3_valid = io_slave_3_b_valid;
+ assign b_arb_io_in_3_bits_resp = io_slave_3_b_bits_resp;
+ assign b_arb_io_in_3_bits_id = io_slave_3_b_bits_id;
+ assign b_arb_io_in_3_bits_user = io_slave_3_b_bits_user;
+ assign b_arb_io_in_4_valid = err_slave_io_b_valid;
+ assign b_arb_io_in_4_bits_resp = err_slave_io_b_bits_resp;
+ assign b_arb_io_in_4_bits_id = err_slave_io_b_bits_id;
+ assign b_arb_io_in_4_bits_user = err_slave_io_b_bits_user;
+ assign b_arb_io_out_ready = io_master_b_ready;
+ assign r_arb_clk = clk;
+ assign r_arb_reset = reset;
+ assign r_arb_io_in_0_valid = io_slave_0_r_valid;
+ assign r_arb_io_in_0_bits_resp = io_slave_0_r_bits_resp;
+ assign r_arb_io_in_0_bits_data = io_slave_0_r_bits_data;
+ assign r_arb_io_in_0_bits_last = io_slave_0_r_bits_last;
+ assign r_arb_io_in_0_bits_id = io_slave_0_r_bits_id;
+ assign r_arb_io_in_0_bits_user = io_slave_0_r_bits_user;
+ assign r_arb_io_in_1_valid = io_slave_1_r_valid;
+ assign r_arb_io_in_1_bits_resp = io_slave_1_r_bits_resp;
+ assign r_arb_io_in_1_bits_data = io_slave_1_r_bits_data;
+ assign r_arb_io_in_1_bits_last = io_slave_1_r_bits_last;
+ assign r_arb_io_in_1_bits_id = io_slave_1_r_bits_id;
+ assign r_arb_io_in_1_bits_user = io_slave_1_r_bits_user;
+ assign r_arb_io_in_2_valid = io_slave_2_r_valid;
+ assign r_arb_io_in_2_bits_resp = io_slave_2_r_bits_resp;
+ assign r_arb_io_in_2_bits_data = io_slave_2_r_bits_data;
+ assign r_arb_io_in_2_bits_last = io_slave_2_r_bits_last;
+ assign r_arb_io_in_2_bits_id = io_slave_2_r_bits_id;
+ assign r_arb_io_in_2_bits_user = io_slave_2_r_bits_user;
+ assign r_arb_io_in_3_valid = io_slave_3_r_valid;
+ assign r_arb_io_in_3_bits_resp = io_slave_3_r_bits_resp;
+ assign r_arb_io_in_3_bits_data = io_slave_3_r_bits_data;
+ assign r_arb_io_in_3_bits_last = io_slave_3_r_bits_last;
+ assign r_arb_io_in_3_bits_id = io_slave_3_r_bits_id;
+ assign r_arb_io_in_3_bits_user = io_slave_3_r_bits_user;
+ assign r_arb_io_in_4_valid = err_slave_io_r_valid;
+ assign r_arb_io_in_4_bits_resp = err_slave_io_r_bits_resp;
+ assign r_arb_io_in_4_bits_data = err_slave_io_r_bits_data;
+ assign r_arb_io_in_4_bits_last = err_slave_io_r_bits_last;
+ assign r_arb_io_in_4_bits_id = err_slave_io_r_bits_id;
+ assign r_arb_io_in_4_bits_user = err_slave_io_r_bits_user;
+ assign r_arb_io_out_ready = io_master_r_ready;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_1510 = {1{$random}};
+ T_1530 = {1{$random}};
+ T_1550 = {1{$random}};
+ T_1570 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ T_1510 <= 1'h0;
+ end else begin
+ if(T_1514) begin
+ T_1510 <= 1'h0;
+ end else begin
+ if(T_1511) begin
+ T_1510 <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ T_1530 <= 1'h0;
+ end else begin
+ if(T_1534) begin
+ T_1530 <= 1'h0;
+ end else begin
+ if(T_1531) begin
+ T_1530 <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ T_1550 <= 1'h0;
+ end else begin
+ if(T_1554) begin
+ T_1550 <= 1'h0;
+ end else begin
+ if(T_1551) begin
+ T_1550 <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ T_1570 <= 1'h0;
+ end else begin
+ if(T_1574) begin
+ T_1570 <= 1'h0;
+ end else begin
+ if(T_1571) begin
+ T_1570 <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+endmodule
+module NastiErrorSlave_40(
+ input clk,
+ input reset,
+ output io_aw_ready,
+ input io_aw_valid,
+ input [31:0] io_aw_bits_addr,
+ input [7:0] io_aw_bits_len,
+ input [2:0] io_aw_bits_size,
+ input [1:0] io_aw_bits_burst,
+ input io_aw_bits_lock,
+ input [3:0] io_aw_bits_cache,
+ input [2:0] io_aw_bits_prot,
+ input [3:0] io_aw_bits_qos,
+ input [3:0] io_aw_bits_region,
+ input [4:0] io_aw_bits_id,
+ input io_aw_bits_user,
+ output io_w_ready,
+ input io_w_valid,
+ input [63:0] io_w_bits_data,
+ input io_w_bits_last,
+ input [7:0] io_w_bits_strb,
+ input io_w_bits_user,
+ input io_b_ready,
+ output io_b_valid,
+ output [1:0] io_b_bits_resp,
+ output [4:0] io_b_bits_id,
+ output io_b_bits_user,
+ output io_ar_ready,
+ input io_ar_valid,
+ input [31:0] io_ar_bits_addr,
+ input [7:0] io_ar_bits_len,
+ input [2:0] io_ar_bits_size,
+ input [1:0] io_ar_bits_burst,
+ input io_ar_bits_lock,
+ input [3:0] io_ar_bits_cache,
+ input [2:0] io_ar_bits_prot,
+ input [3:0] io_ar_bits_qos,
+ input [3:0] io_ar_bits_region,
+ input [4:0] io_ar_bits_id,
+ input io_ar_bits_user,
+ input io_r_ready,
+ output io_r_valid,
+ output [1:0] io_r_bits_resp,
+ output [63:0] io_r_bits_data,
+ output io_r_bits_last,
+ output [4:0] io_r_bits_id,
+ output io_r_bits_user
+);
+ wire T_322;
+ wire T_324;
+ wire T_325;
+ wire T_327;
+ wire r_queue_clk;
+ wire r_queue_reset;
+ wire r_queue_io_enq_ready;
+ wire r_queue_io_enq_valid;
+ wire [31:0] r_queue_io_enq_bits_addr;
+ wire [7:0] r_queue_io_enq_bits_len;
+ wire [2:0] r_queue_io_enq_bits_size;
+ wire [1:0] r_queue_io_enq_bits_burst;
+ wire r_queue_io_enq_bits_lock;
+ wire [3:0] r_queue_io_enq_bits_cache;
+ wire [2:0] r_queue_io_enq_bits_prot;
+ wire [3:0] r_queue_io_enq_bits_qos;
+ wire [3:0] r_queue_io_enq_bits_region;
+ wire [4:0] r_queue_io_enq_bits_id;
+ wire r_queue_io_enq_bits_user;
+ wire r_queue_io_deq_ready;
+ wire r_queue_io_deq_valid;
+ wire [31:0] r_queue_io_deq_bits_addr;
+ wire [7:0] r_queue_io_deq_bits_len;
+ wire [2:0] r_queue_io_deq_bits_size;
+ wire [1:0] r_queue_io_deq_bits_burst;
+ wire r_queue_io_deq_bits_lock;
+ wire [3:0] r_queue_io_deq_bits_cache;
+ wire [2:0] r_queue_io_deq_bits_prot;
+ wire [3:0] r_queue_io_deq_bits_qos;
+ wire [3:0] r_queue_io_deq_bits_region;
+ wire [4:0] r_queue_io_deq_bits_id;
+ wire r_queue_io_deq_bits_user;
+ wire [1:0] r_queue_io_count;
+ reg responding;
+ reg [7:0] beats_left;
+ wire T_346;
+ wire T_347;
+ wire T_349;
+ wire T_352;
+ wire T_353;
+ wire T_354;
+ wire T_355;
+ wire T_357;
+ wire T_360;
+ wire [8:0] T_362;
+ wire [7:0] T_363;
+ reg draining;
+ wire T_366;
+ wire T_368;
+ wire T_369;
+ wire b_queue_clk;
+ wire b_queue_reset;
+ wire b_queue_io_enq_ready;
+ wire b_queue_io_enq_valid;
+ wire [4:0] b_queue_io_enq_bits;
+ wire b_queue_io_deq_ready;
+ wire b_queue_io_deq_valid;
+ wire [4:0] b_queue_io_deq_bits;
+ wire [1:0] b_queue_io_count;
+ wire T_374;
+ wire T_375;
+ wire T_377;
+ wire T_378;
+ wire T_380;
+ wire T_381;
+ wire T_384;
+ wire T_385;
+ reg GEN_0;
+ reg GEN_1;
+ Queue_36 r_queue (
+ .clk(r_queue_clk),
+ .reset(r_queue_reset),
+ .io_enq_ready(r_queue_io_enq_ready),
+ .io_enq_valid(r_queue_io_enq_valid),
+ .io_enq_bits_addr(r_queue_io_enq_bits_addr),
+ .io_enq_bits_len(r_queue_io_enq_bits_len),
+ .io_enq_bits_size(r_queue_io_enq_bits_size),
+ .io_enq_bits_burst(r_queue_io_enq_bits_burst),
+ .io_enq_bits_lock(r_queue_io_enq_bits_lock),
+ .io_enq_bits_cache(r_queue_io_enq_bits_cache),
+ .io_enq_bits_prot(r_queue_io_enq_bits_prot),
+ .io_enq_bits_qos(r_queue_io_enq_bits_qos),
+ .io_enq_bits_region(r_queue_io_enq_bits_region),
+ .io_enq_bits_id(r_queue_io_enq_bits_id),
+ .io_enq_bits_user(r_queue_io_enq_bits_user),
+ .io_deq_ready(r_queue_io_deq_ready),
+ .io_deq_valid(r_queue_io_deq_valid),
+ .io_deq_bits_addr(r_queue_io_deq_bits_addr),
+ .io_deq_bits_len(r_queue_io_deq_bits_len),
+ .io_deq_bits_size(r_queue_io_deq_bits_size),
+ .io_deq_bits_burst(r_queue_io_deq_bits_burst),
+ .io_deq_bits_lock(r_queue_io_deq_bits_lock),
+ .io_deq_bits_cache(r_queue_io_deq_bits_cache),
+ .io_deq_bits_prot(r_queue_io_deq_bits_prot),
+ .io_deq_bits_qos(r_queue_io_deq_bits_qos),
+ .io_deq_bits_region(r_queue_io_deq_bits_region),
+ .io_deq_bits_id(r_queue_io_deq_bits_id),
+ .io_deq_bits_user(r_queue_io_deq_bits_user),
+ .io_count(r_queue_io_count)
+ );
+ Queue_37 b_queue (
+ .clk(b_queue_clk),
+ .reset(b_queue_reset),
+ .io_enq_ready(b_queue_io_enq_ready),
+ .io_enq_valid(b_queue_io_enq_valid),
+ .io_enq_bits(b_queue_io_enq_bits),
+ .io_deq_ready(b_queue_io_deq_ready),
+ .io_deq_valid(b_queue_io_deq_valid),
+ .io_deq_bits(b_queue_io_deq_bits),
+ .io_count(b_queue_io_count)
+ );
+ assign io_aw_ready = T_378;
+ assign io_w_ready = draining;
+ assign io_b_valid = T_381;
+ assign io_b_bits_resp = 2'h3;
+ assign io_b_bits_id = b_queue_io_deq_bits;
+ assign io_b_bits_user = GEN_0;
+ assign io_ar_ready = r_queue_io_enq_ready;
+ assign io_r_valid = T_349;
+ assign io_r_bits_resp = 2'h3;
+ assign io_r_bits_data = 1'h0;
+ assign io_r_bits_last = T_352;
+ assign io_r_bits_id = r_queue_io_deq_bits_id;
+ assign io_r_bits_user = GEN_1;
+ assign T_322 = io_ar_ready & io_ar_valid;
+ assign T_324 = reset == 1'h0;
+ assign T_325 = io_aw_ready & io_aw_valid;
+ assign T_327 = reset == 1'h0;
+ assign r_queue_clk = clk;
+ assign r_queue_reset = reset;
+ assign r_queue_io_enq_valid = io_ar_valid;
+ assign r_queue_io_enq_bits_addr = io_ar_bits_addr;
+ assign r_queue_io_enq_bits_len = io_ar_bits_len;
+ assign r_queue_io_enq_bits_size = io_ar_bits_size;
+ assign r_queue_io_enq_bits_burst = io_ar_bits_burst;
+ assign r_queue_io_enq_bits_lock = io_ar_bits_lock;
+ assign r_queue_io_enq_bits_cache = io_ar_bits_cache;
+ assign r_queue_io_enq_bits_prot = io_ar_bits_prot;
+ assign r_queue_io_enq_bits_qos = io_ar_bits_qos;
+ assign r_queue_io_enq_bits_region = io_ar_bits_region;
+ assign r_queue_io_enq_bits_id = io_ar_bits_id;
+ assign r_queue_io_enq_bits_user = io_ar_bits_user;
+ assign r_queue_io_deq_ready = T_354;
+ assign T_346 = responding == 1'h0;
+ assign T_347 = T_346 & r_queue_io_deq_valid;
+ assign T_349 = r_queue_io_deq_valid & responding;
+ assign T_352 = beats_left == 1'h0;
+ assign T_353 = io_r_ready & io_r_valid;
+ assign T_354 = T_353 & io_r_bits_last;
+ assign T_355 = io_r_ready & io_r_valid;
+ assign T_357 = beats_left == 1'h0;
+ assign T_360 = T_357 == 1'h0;
+ assign T_362 = beats_left - 1'h1;
+ assign T_363 = T_362[7:0];
+ assign T_366 = io_aw_ready & io_aw_valid;
+ assign T_368 = io_w_ready & io_w_valid;
+ assign T_369 = T_368 & io_w_bits_last;
+ assign b_queue_clk = clk;
+ assign b_queue_reset = reset;
+ assign b_queue_io_enq_valid = T_375;
+ assign b_queue_io_enq_bits = io_aw_bits_id;
+ assign b_queue_io_deq_ready = T_385;
+ assign T_374 = draining == 1'h0;
+ assign T_375 = io_aw_valid & T_374;
+ assign T_377 = draining == 1'h0;
+ assign T_378 = b_queue_io_enq_ready & T_377;
+ assign T_380 = draining == 1'h0;
+ assign T_381 = b_queue_io_deq_valid & T_380;
+ assign T_384 = draining == 1'h0;
+ assign T_385 = io_b_ready & T_384;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ responding = {1{$random}};
+ beats_left = {1{$random}};
+ draining = {1{$random}};
+ GEN_0 = {1{$random}};
+ GEN_1 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ responding <= 1'h0;
+ end else begin
+ if(T_355) begin
+ if(T_357) begin
+ responding <= 1'h0;
+ end else begin
+ if(T_347) begin
+ responding <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_347) begin
+ responding <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ beats_left <= 8'h0;
+ end else begin
+ if(T_355) begin
+ if(T_360) begin
+ beats_left <= T_363;
+ end else begin
+ if(T_347) begin
+ beats_left <= r_queue_io_deq_bits_len;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_347) begin
+ beats_left <= r_queue_io_deq_bits_len;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ draining <= 1'h0;
+ end else begin
+ if(T_369) begin
+ draining <= 1'h0;
+ end else begin
+ if(T_366) begin
+ draining <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ `ifndef SYNTHESIS
+ if(T_322 & T_324) begin
+ $fwrite(32'h80000002,"Invalid read address %h\n",io_ar_bits_addr);
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_325 & T_327) begin
+ $fwrite(32'h80000002,"Invalid write address %h\n",io_aw_bits_addr);
+ end
+ `endif
+ end
+endmodule
+module NastiRouter_39(
+ input clk,
+ input reset,
+ output io_master_aw_ready,
+ input io_master_aw_valid,
+ input [31:0] io_master_aw_bits_addr,
+ input [7:0] io_master_aw_bits_len,
+ input [2:0] io_master_aw_bits_size,
+ input [1:0] io_master_aw_bits_burst,
+ input io_master_aw_bits_lock,
+ input [3:0] io_master_aw_bits_cache,
+ input [2:0] io_master_aw_bits_prot,
+ input [3:0] io_master_aw_bits_qos,
+ input [3:0] io_master_aw_bits_region,
+ input [4:0] io_master_aw_bits_id,
+ input io_master_aw_bits_user,
+ output io_master_w_ready,
+ input io_master_w_valid,
+ input [63:0] io_master_w_bits_data,
+ input io_master_w_bits_last,
+ input [7:0] io_master_w_bits_strb,
+ input io_master_w_bits_user,
+ input io_master_b_ready,
+ output io_master_b_valid,
+ output [1:0] io_master_b_bits_resp,
+ output [4:0] io_master_b_bits_id,
+ output io_master_b_bits_user,
+ output io_master_ar_ready,
+ input io_master_ar_valid,
+ input [31:0] io_master_ar_bits_addr,
+ input [7:0] io_master_ar_bits_len,
+ input [2:0] io_master_ar_bits_size,
+ input [1:0] io_master_ar_bits_burst,
+ input io_master_ar_bits_lock,
+ input [3:0] io_master_ar_bits_cache,
+ input [2:0] io_master_ar_bits_prot,
+ input [3:0] io_master_ar_bits_qos,
+ input [3:0] io_master_ar_bits_region,
+ input [4:0] io_master_ar_bits_id,
+ input io_master_ar_bits_user,
+ input io_master_r_ready,
+ output io_master_r_valid,
+ output [1:0] io_master_r_bits_resp,
+ output [63:0] io_master_r_bits_data,
+ output io_master_r_bits_last,
+ output [4:0] io_master_r_bits_id,
+ output io_master_r_bits_user,
+ input io_slave_0_aw_ready,
+ output io_slave_0_aw_valid,
+ output [31:0] io_slave_0_aw_bits_addr,
+ output [7:0] io_slave_0_aw_bits_len,
+ output [2:0] io_slave_0_aw_bits_size,
+ output [1:0] io_slave_0_aw_bits_burst,
+ output io_slave_0_aw_bits_lock,
+ output [3:0] io_slave_0_aw_bits_cache,
+ output [2:0] io_slave_0_aw_bits_prot,
+ output [3:0] io_slave_0_aw_bits_qos,
+ output [3:0] io_slave_0_aw_bits_region,
+ output [4:0] io_slave_0_aw_bits_id,
+ output io_slave_0_aw_bits_user,
+ input io_slave_0_w_ready,
+ output io_slave_0_w_valid,
+ output [63:0] io_slave_0_w_bits_data,
+ output io_slave_0_w_bits_last,
+ output [7:0] io_slave_0_w_bits_strb,
+ output io_slave_0_w_bits_user,
+ output io_slave_0_b_ready,
+ input io_slave_0_b_valid,
+ input [1:0] io_slave_0_b_bits_resp,
+ input [4:0] io_slave_0_b_bits_id,
+ input io_slave_0_b_bits_user,
+ input io_slave_0_ar_ready,
+ output io_slave_0_ar_valid,
+ output [31:0] io_slave_0_ar_bits_addr,
+ output [7:0] io_slave_0_ar_bits_len,
+ output [2:0] io_slave_0_ar_bits_size,
+ output [1:0] io_slave_0_ar_bits_burst,
+ output io_slave_0_ar_bits_lock,
+ output [3:0] io_slave_0_ar_bits_cache,
+ output [2:0] io_slave_0_ar_bits_prot,
+ output [3:0] io_slave_0_ar_bits_qos,
+ output [3:0] io_slave_0_ar_bits_region,
+ output [4:0] io_slave_0_ar_bits_id,
+ output io_slave_0_ar_bits_user,
+ output io_slave_0_r_ready,
+ input io_slave_0_r_valid,
+ input [1:0] io_slave_0_r_bits_resp,
+ input [63:0] io_slave_0_r_bits_data,
+ input io_slave_0_r_bits_last,
+ input [4:0] io_slave_0_r_bits_id,
+ input io_slave_0_r_bits_user,
+ input io_slave_1_aw_ready,
+ output io_slave_1_aw_valid,
+ output [31:0] io_slave_1_aw_bits_addr,
+ output [7:0] io_slave_1_aw_bits_len,
+ output [2:0] io_slave_1_aw_bits_size,
+ output [1:0] io_slave_1_aw_bits_burst,
+ output io_slave_1_aw_bits_lock,
+ output [3:0] io_slave_1_aw_bits_cache,
+ output [2:0] io_slave_1_aw_bits_prot,
+ output [3:0] io_slave_1_aw_bits_qos,
+ output [3:0] io_slave_1_aw_bits_region,
+ output [4:0] io_slave_1_aw_bits_id,
+ output io_slave_1_aw_bits_user,
+ input io_slave_1_w_ready,
+ output io_slave_1_w_valid,
+ output [63:0] io_slave_1_w_bits_data,
+ output io_slave_1_w_bits_last,
+ output [7:0] io_slave_1_w_bits_strb,
+ output io_slave_1_w_bits_user,
+ output io_slave_1_b_ready,
+ input io_slave_1_b_valid,
+ input [1:0] io_slave_1_b_bits_resp,
+ input [4:0] io_slave_1_b_bits_id,
+ input io_slave_1_b_bits_user,
+ input io_slave_1_ar_ready,
+ output io_slave_1_ar_valid,
+ output [31:0] io_slave_1_ar_bits_addr,
+ output [7:0] io_slave_1_ar_bits_len,
+ output [2:0] io_slave_1_ar_bits_size,
+ output [1:0] io_slave_1_ar_bits_burst,
+ output io_slave_1_ar_bits_lock,
+ output [3:0] io_slave_1_ar_bits_cache,
+ output [2:0] io_slave_1_ar_bits_prot,
+ output [3:0] io_slave_1_ar_bits_qos,
+ output [3:0] io_slave_1_ar_bits_region,
+ output [4:0] io_slave_1_ar_bits_id,
+ output io_slave_1_ar_bits_user,
+ output io_slave_1_r_ready,
+ input io_slave_1_r_valid,
+ input [1:0] io_slave_1_r_bits_resp,
+ input [63:0] io_slave_1_r_bits_data,
+ input io_slave_1_r_bits_last,
+ input [4:0] io_slave_1_r_bits_id,
+ input io_slave_1_r_bits_user,
+ input io_slave_2_aw_ready,
+ output io_slave_2_aw_valid,
+ output [31:0] io_slave_2_aw_bits_addr,
+ output [7:0] io_slave_2_aw_bits_len,
+ output [2:0] io_slave_2_aw_bits_size,
+ output [1:0] io_slave_2_aw_bits_burst,
+ output io_slave_2_aw_bits_lock,
+ output [3:0] io_slave_2_aw_bits_cache,
+ output [2:0] io_slave_2_aw_bits_prot,
+ output [3:0] io_slave_2_aw_bits_qos,
+ output [3:0] io_slave_2_aw_bits_region,
+ output [4:0] io_slave_2_aw_bits_id,
+ output io_slave_2_aw_bits_user,
+ input io_slave_2_w_ready,
+ output io_slave_2_w_valid,
+ output [63:0] io_slave_2_w_bits_data,
+ output io_slave_2_w_bits_last,
+ output [7:0] io_slave_2_w_bits_strb,
+ output io_slave_2_w_bits_user,
+ output io_slave_2_b_ready,
+ input io_slave_2_b_valid,
+ input [1:0] io_slave_2_b_bits_resp,
+ input [4:0] io_slave_2_b_bits_id,
+ input io_slave_2_b_bits_user,
+ input io_slave_2_ar_ready,
+ output io_slave_2_ar_valid,
+ output [31:0] io_slave_2_ar_bits_addr,
+ output [7:0] io_slave_2_ar_bits_len,
+ output [2:0] io_slave_2_ar_bits_size,
+ output [1:0] io_slave_2_ar_bits_burst,
+ output io_slave_2_ar_bits_lock,
+ output [3:0] io_slave_2_ar_bits_cache,
+ output [2:0] io_slave_2_ar_bits_prot,
+ output [3:0] io_slave_2_ar_bits_qos,
+ output [3:0] io_slave_2_ar_bits_region,
+ output [4:0] io_slave_2_ar_bits_id,
+ output io_slave_2_ar_bits_user,
+ output io_slave_2_r_ready,
+ input io_slave_2_r_valid,
+ input [1:0] io_slave_2_r_bits_resp,
+ input [63:0] io_slave_2_r_bits_data,
+ input io_slave_2_r_bits_last,
+ input [4:0] io_slave_2_r_bits_id,
+ input io_slave_2_r_bits_user,
+ input io_slave_3_aw_ready,
+ output io_slave_3_aw_valid,
+ output [31:0] io_slave_3_aw_bits_addr,
+ output [7:0] io_slave_3_aw_bits_len,
+ output [2:0] io_slave_3_aw_bits_size,
+ output [1:0] io_slave_3_aw_bits_burst,
+ output io_slave_3_aw_bits_lock,
+ output [3:0] io_slave_3_aw_bits_cache,
+ output [2:0] io_slave_3_aw_bits_prot,
+ output [3:0] io_slave_3_aw_bits_qos,
+ output [3:0] io_slave_3_aw_bits_region,
+ output [4:0] io_slave_3_aw_bits_id,
+ output io_slave_3_aw_bits_user,
+ input io_slave_3_w_ready,
+ output io_slave_3_w_valid,
+ output [63:0] io_slave_3_w_bits_data,
+ output io_slave_3_w_bits_last,
+ output [7:0] io_slave_3_w_bits_strb,
+ output io_slave_3_w_bits_user,
+ output io_slave_3_b_ready,
+ input io_slave_3_b_valid,
+ input [1:0] io_slave_3_b_bits_resp,
+ input [4:0] io_slave_3_b_bits_id,
+ input io_slave_3_b_bits_user,
+ input io_slave_3_ar_ready,
+ output io_slave_3_ar_valid,
+ output [31:0] io_slave_3_ar_bits_addr,
+ output [7:0] io_slave_3_ar_bits_len,
+ output [2:0] io_slave_3_ar_bits_size,
+ output [1:0] io_slave_3_ar_bits_burst,
+ output io_slave_3_ar_bits_lock,
+ output [3:0] io_slave_3_ar_bits_cache,
+ output [2:0] io_slave_3_ar_bits_prot,
+ output [3:0] io_slave_3_ar_bits_qos,
+ output [3:0] io_slave_3_ar_bits_region,
+ output [4:0] io_slave_3_ar_bits_id,
+ output io_slave_3_ar_bits_user,
+ output io_slave_3_r_ready,
+ input io_slave_3_r_valid,
+ input [1:0] io_slave_3_r_bits_resp,
+ input [63:0] io_slave_3_r_bits_data,
+ input io_slave_3_r_bits_last,
+ input [4:0] io_slave_3_r_bits_id,
+ input io_slave_3_r_bits_user
+);
+ wire T_1437;
+ wire T_1439;
+ wire T_1440;
+ wire T_1442;
+ wire T_1444;
+ wire T_1445;
+ wire T_1447;
+ wire T_1449;
+ wire T_1450;
+ wire T_1452;
+ wire T_1454;
+ wire T_1455;
+ wire T_1457_0;
+ wire T_1457_1;
+ wire T_1457_2;
+ wire T_1457_3;
+ wire [1:0] T_1463;
+ wire [1:0] T_1464;
+ wire [3:0] ar_route;
+ wire T_1467;
+ wire T_1469;
+ wire T_1470;
+ wire T_1472;
+ wire T_1474;
+ wire T_1475;
+ wire T_1477;
+ wire T_1479;
+ wire T_1480;
+ wire T_1482;
+ wire T_1484;
+ wire T_1485;
+ wire T_1487_0;
+ wire T_1487_1;
+ wire T_1487_2;
+ wire T_1487_3;
+ wire [1:0] T_1493;
+ wire [1:0] T_1494;
+ wire [3:0] aw_route;
+ wire T_1499;
+ wire T_1500;
+ wire T_1501;
+ wire T_1502;
+ wire T_1503;
+ wire T_1504;
+ wire T_1505;
+ wire T_1506;
+ wire T_1507;
+ wire T_1508;
+ reg T_1510;
+ wire T_1511;
+ wire T_1513;
+ wire T_1514;
+ wire T_1516;
+ wire T_1517;
+ wire T_1518;
+ wire T_1519;
+ wire T_1520;
+ wire T_1521;
+ wire T_1522;
+ wire T_1523;
+ wire T_1524;
+ wire T_1525;
+ wire T_1526;
+ wire T_1527;
+ wire T_1528;
+ reg T_1530;
+ wire T_1531;
+ wire T_1533;
+ wire T_1534;
+ wire T_1536;
+ wire T_1537;
+ wire T_1538;
+ wire T_1539;
+ wire T_1540;
+ wire T_1541;
+ wire T_1542;
+ wire T_1543;
+ wire T_1544;
+ wire T_1545;
+ wire T_1546;
+ wire T_1547;
+ wire T_1548;
+ reg T_1550;
+ wire T_1551;
+ wire T_1553;
+ wire T_1554;
+ wire T_1556;
+ wire T_1557;
+ wire T_1558;
+ wire T_1559;
+ wire T_1560;
+ wire T_1561;
+ wire T_1562;
+ wire ar_ready;
+ wire T_1564;
+ wire T_1565;
+ wire T_1566;
+ wire T_1567;
+ wire aw_ready;
+ reg T_1570;
+ wire T_1571;
+ wire T_1573;
+ wire T_1574;
+ wire T_1576;
+ wire T_1577;
+ wire w_ready;
+ wire T_1580;
+ wire r_invalid;
+ wire T_1584;
+ wire w_invalid;
+ wire err_slave_clk;
+ wire err_slave_reset;
+ wire err_slave_io_aw_ready;
+ wire err_slave_io_aw_valid;
+ wire [31:0] err_slave_io_aw_bits_addr;
+ wire [7:0] err_slave_io_aw_bits_len;
+ wire [2:0] err_slave_io_aw_bits_size;
+ wire [1:0] err_slave_io_aw_bits_burst;
+ wire err_slave_io_aw_bits_lock;
+ wire [3:0] err_slave_io_aw_bits_cache;
+ wire [2:0] err_slave_io_aw_bits_prot;
+ wire [3:0] err_slave_io_aw_bits_qos;
+ wire [3:0] err_slave_io_aw_bits_region;
+ wire [4:0] err_slave_io_aw_bits_id;
+ wire err_slave_io_aw_bits_user;
+ wire err_slave_io_w_ready;
+ wire err_slave_io_w_valid;
+ wire [63:0] err_slave_io_w_bits_data;
+ wire err_slave_io_w_bits_last;
+ wire [7:0] err_slave_io_w_bits_strb;
+ wire err_slave_io_w_bits_user;
+ wire err_slave_io_b_ready;
+ wire err_slave_io_b_valid;
+ wire [1:0] err_slave_io_b_bits_resp;
+ wire [4:0] err_slave_io_b_bits_id;
+ wire err_slave_io_b_bits_user;
+ wire err_slave_io_ar_ready;
+ wire err_slave_io_ar_valid;
+ wire [31:0] err_slave_io_ar_bits_addr;
+ wire [7:0] err_slave_io_ar_bits_len;
+ wire [2:0] err_slave_io_ar_bits_size;
+ wire [1:0] err_slave_io_ar_bits_burst;
+ wire err_slave_io_ar_bits_lock;
+ wire [3:0] err_slave_io_ar_bits_cache;
+ wire [2:0] err_slave_io_ar_bits_prot;
+ wire [3:0] err_slave_io_ar_bits_qos;
+ wire [3:0] err_slave_io_ar_bits_region;
+ wire [4:0] err_slave_io_ar_bits_id;
+ wire err_slave_io_ar_bits_user;
+ wire err_slave_io_r_ready;
+ wire err_slave_io_r_valid;
+ wire [1:0] err_slave_io_r_bits_resp;
+ wire [63:0] err_slave_io_r_bits_data;
+ wire err_slave_io_r_bits_last;
+ wire [4:0] err_slave_io_r_bits_id;
+ wire err_slave_io_r_bits_user;
+ wire T_1588;
+ wire T_1589;
+ wire T_1590;
+ wire T_1591;
+ wire T_1592;
+ wire T_1593;
+ wire T_1594;
+ wire b_arb_clk;
+ wire b_arb_reset;
+ wire b_arb_io_in_0_ready;
+ wire b_arb_io_in_0_valid;
+ wire [1:0] b_arb_io_in_0_bits_resp;
+ wire [4:0] b_arb_io_in_0_bits_id;
+ wire b_arb_io_in_0_bits_user;
+ wire b_arb_io_in_1_ready;
+ wire b_arb_io_in_1_valid;
+ wire [1:0] b_arb_io_in_1_bits_resp;
+ wire [4:0] b_arb_io_in_1_bits_id;
+ wire b_arb_io_in_1_bits_user;
+ wire b_arb_io_in_2_ready;
+ wire b_arb_io_in_2_valid;
+ wire [1:0] b_arb_io_in_2_bits_resp;
+ wire [4:0] b_arb_io_in_2_bits_id;
+ wire b_arb_io_in_2_bits_user;
+ wire b_arb_io_in_3_ready;
+ wire b_arb_io_in_3_valid;
+ wire [1:0] b_arb_io_in_3_bits_resp;
+ wire [4:0] b_arb_io_in_3_bits_id;
+ wire b_arb_io_in_3_bits_user;
+ wire b_arb_io_in_4_ready;
+ wire b_arb_io_in_4_valid;
+ wire [1:0] b_arb_io_in_4_bits_resp;
+ wire [4:0] b_arb_io_in_4_bits_id;
+ wire b_arb_io_in_4_bits_user;
+ wire b_arb_io_out_ready;
+ wire b_arb_io_out_valid;
+ wire [1:0] b_arb_io_out_bits_resp;
+ wire [4:0] b_arb_io_out_bits_id;
+ wire b_arb_io_out_bits_user;
+ wire [2:0] b_arb_io_chosen;
+ wire r_arb_clk;
+ wire r_arb_reset;
+ wire r_arb_io_in_0_ready;
+ wire r_arb_io_in_0_valid;
+ wire [1:0] r_arb_io_in_0_bits_resp;
+ wire [63:0] r_arb_io_in_0_bits_data;
+ wire r_arb_io_in_0_bits_last;
+ wire [4:0] r_arb_io_in_0_bits_id;
+ wire r_arb_io_in_0_bits_user;
+ wire r_arb_io_in_1_ready;
+ wire r_arb_io_in_1_valid;
+ wire [1:0] r_arb_io_in_1_bits_resp;
+ wire [63:0] r_arb_io_in_1_bits_data;
+ wire r_arb_io_in_1_bits_last;
+ wire [4:0] r_arb_io_in_1_bits_id;
+ wire r_arb_io_in_1_bits_user;
+ wire r_arb_io_in_2_ready;
+ wire r_arb_io_in_2_valid;
+ wire [1:0] r_arb_io_in_2_bits_resp;
+ wire [63:0] r_arb_io_in_2_bits_data;
+ wire r_arb_io_in_2_bits_last;
+ wire [4:0] r_arb_io_in_2_bits_id;
+ wire r_arb_io_in_2_bits_user;
+ wire r_arb_io_in_3_ready;
+ wire r_arb_io_in_3_valid;
+ wire [1:0] r_arb_io_in_3_bits_resp;
+ wire [63:0] r_arb_io_in_3_bits_data;
+ wire r_arb_io_in_3_bits_last;
+ wire [4:0] r_arb_io_in_3_bits_id;
+ wire r_arb_io_in_3_bits_user;
+ wire r_arb_io_in_4_ready;
+ wire r_arb_io_in_4_valid;
+ wire [1:0] r_arb_io_in_4_bits_resp;
+ wire [63:0] r_arb_io_in_4_bits_data;
+ wire r_arb_io_in_4_bits_last;
+ wire [4:0] r_arb_io_in_4_bits_id;
+ wire r_arb_io_in_4_bits_user;
+ wire r_arb_io_out_ready;
+ wire r_arb_io_out_valid;
+ wire [1:0] r_arb_io_out_bits_resp;
+ wire [63:0] r_arb_io_out_bits_data;
+ wire r_arb_io_out_bits_last;
+ wire [4:0] r_arb_io_out_bits_id;
+ wire r_arb_io_out_bits_user;
+ NastiErrorSlave_40 err_slave (
+ .clk(err_slave_clk),
+ .reset(err_slave_reset),
+ .io_aw_ready(err_slave_io_aw_ready),
+ .io_aw_valid(err_slave_io_aw_valid),
+ .io_aw_bits_addr(err_slave_io_aw_bits_addr),
+ .io_aw_bits_len(err_slave_io_aw_bits_len),
+ .io_aw_bits_size(err_slave_io_aw_bits_size),
+ .io_aw_bits_burst(err_slave_io_aw_bits_burst),
+ .io_aw_bits_lock(err_slave_io_aw_bits_lock),
+ .io_aw_bits_cache(err_slave_io_aw_bits_cache),
+ .io_aw_bits_prot(err_slave_io_aw_bits_prot),
+ .io_aw_bits_qos(err_slave_io_aw_bits_qos),
+ .io_aw_bits_region(err_slave_io_aw_bits_region),
+ .io_aw_bits_id(err_slave_io_aw_bits_id),
+ .io_aw_bits_user(err_slave_io_aw_bits_user),
+ .io_w_ready(err_slave_io_w_ready),
+ .io_w_valid(err_slave_io_w_valid),
+ .io_w_bits_data(err_slave_io_w_bits_data),
+ .io_w_bits_last(err_slave_io_w_bits_last),
+ .io_w_bits_strb(err_slave_io_w_bits_strb),
+ .io_w_bits_user(err_slave_io_w_bits_user),
+ .io_b_ready(err_slave_io_b_ready),
+ .io_b_valid(err_slave_io_b_valid),
+ .io_b_bits_resp(err_slave_io_b_bits_resp),
+ .io_b_bits_id(err_slave_io_b_bits_id),
+ .io_b_bits_user(err_slave_io_b_bits_user),
+ .io_ar_ready(err_slave_io_ar_ready),
+ .io_ar_valid(err_slave_io_ar_valid),
+ .io_ar_bits_addr(err_slave_io_ar_bits_addr),
+ .io_ar_bits_len(err_slave_io_ar_bits_len),
+ .io_ar_bits_size(err_slave_io_ar_bits_size),
+ .io_ar_bits_burst(err_slave_io_ar_bits_burst),
+ .io_ar_bits_lock(err_slave_io_ar_bits_lock),
+ .io_ar_bits_cache(err_slave_io_ar_bits_cache),
+ .io_ar_bits_prot(err_slave_io_ar_bits_prot),
+ .io_ar_bits_qos(err_slave_io_ar_bits_qos),
+ .io_ar_bits_region(err_slave_io_ar_bits_region),
+ .io_ar_bits_id(err_slave_io_ar_bits_id),
+ .io_ar_bits_user(err_slave_io_ar_bits_user),
+ .io_r_ready(err_slave_io_r_ready),
+ .io_r_valid(err_slave_io_r_valid),
+ .io_r_bits_resp(err_slave_io_r_bits_resp),
+ .io_r_bits_data(err_slave_io_r_bits_data),
+ .io_r_bits_last(err_slave_io_r_bits_last),
+ .io_r_bits_id(err_slave_io_r_bits_id),
+ .io_r_bits_user(err_slave_io_r_bits_user)
+ );
+ RRArbiter_38 b_arb (
+ .clk(b_arb_clk),
+ .reset(b_arb_reset),
+ .io_in_0_ready(b_arb_io_in_0_ready),
+ .io_in_0_valid(b_arb_io_in_0_valid),
+ .io_in_0_bits_resp(b_arb_io_in_0_bits_resp),
+ .io_in_0_bits_id(b_arb_io_in_0_bits_id),
+ .io_in_0_bits_user(b_arb_io_in_0_bits_user),
+ .io_in_1_ready(b_arb_io_in_1_ready),
+ .io_in_1_valid(b_arb_io_in_1_valid),
+ .io_in_1_bits_resp(b_arb_io_in_1_bits_resp),
+ .io_in_1_bits_id(b_arb_io_in_1_bits_id),
+ .io_in_1_bits_user(b_arb_io_in_1_bits_user),
+ .io_in_2_ready(b_arb_io_in_2_ready),
+ .io_in_2_valid(b_arb_io_in_2_valid),
+ .io_in_2_bits_resp(b_arb_io_in_2_bits_resp),
+ .io_in_2_bits_id(b_arb_io_in_2_bits_id),
+ .io_in_2_bits_user(b_arb_io_in_2_bits_user),
+ .io_in_3_ready(b_arb_io_in_3_ready),
+ .io_in_3_valid(b_arb_io_in_3_valid),
+ .io_in_3_bits_resp(b_arb_io_in_3_bits_resp),
+ .io_in_3_bits_id(b_arb_io_in_3_bits_id),
+ .io_in_3_bits_user(b_arb_io_in_3_bits_user),
+ .io_in_4_ready(b_arb_io_in_4_ready),
+ .io_in_4_valid(b_arb_io_in_4_valid),
+ .io_in_4_bits_resp(b_arb_io_in_4_bits_resp),
+ .io_in_4_bits_id(b_arb_io_in_4_bits_id),
+ .io_in_4_bits_user(b_arb_io_in_4_bits_user),
+ .io_out_ready(b_arb_io_out_ready),
+ .io_out_valid(b_arb_io_out_valid),
+ .io_out_bits_resp(b_arb_io_out_bits_resp),
+ .io_out_bits_id(b_arb_io_out_bits_id),
+ .io_out_bits_user(b_arb_io_out_bits_user),
+ .io_chosen(b_arb_io_chosen)
+ );
+ JunctionsPeekingArbiter r_arb (
+ .clk(r_arb_clk),
+ .reset(r_arb_reset),
+ .io_in_0_ready(r_arb_io_in_0_ready),
+ .io_in_0_valid(r_arb_io_in_0_valid),
+ .io_in_0_bits_resp(r_arb_io_in_0_bits_resp),
+ .io_in_0_bits_data(r_arb_io_in_0_bits_data),
+ .io_in_0_bits_last(r_arb_io_in_0_bits_last),
+ .io_in_0_bits_id(r_arb_io_in_0_bits_id),
+ .io_in_0_bits_user(r_arb_io_in_0_bits_user),
+ .io_in_1_ready(r_arb_io_in_1_ready),
+ .io_in_1_valid(r_arb_io_in_1_valid),
+ .io_in_1_bits_resp(r_arb_io_in_1_bits_resp),
+ .io_in_1_bits_data(r_arb_io_in_1_bits_data),
+ .io_in_1_bits_last(r_arb_io_in_1_bits_last),
+ .io_in_1_bits_id(r_arb_io_in_1_bits_id),
+ .io_in_1_bits_user(r_arb_io_in_1_bits_user),
+ .io_in_2_ready(r_arb_io_in_2_ready),
+ .io_in_2_valid(r_arb_io_in_2_valid),
+ .io_in_2_bits_resp(r_arb_io_in_2_bits_resp),
+ .io_in_2_bits_data(r_arb_io_in_2_bits_data),
+ .io_in_2_bits_last(r_arb_io_in_2_bits_last),
+ .io_in_2_bits_id(r_arb_io_in_2_bits_id),
+ .io_in_2_bits_user(r_arb_io_in_2_bits_user),
+ .io_in_3_ready(r_arb_io_in_3_ready),
+ .io_in_3_valid(r_arb_io_in_3_valid),
+ .io_in_3_bits_resp(r_arb_io_in_3_bits_resp),
+ .io_in_3_bits_data(r_arb_io_in_3_bits_data),
+ .io_in_3_bits_last(r_arb_io_in_3_bits_last),
+ .io_in_3_bits_id(r_arb_io_in_3_bits_id),
+ .io_in_3_bits_user(r_arb_io_in_3_bits_user),
+ .io_in_4_ready(r_arb_io_in_4_ready),
+ .io_in_4_valid(r_arb_io_in_4_valid),
+ .io_in_4_bits_resp(r_arb_io_in_4_bits_resp),
+ .io_in_4_bits_data(r_arb_io_in_4_bits_data),
+ .io_in_4_bits_last(r_arb_io_in_4_bits_last),
+ .io_in_4_bits_id(r_arb_io_in_4_bits_id),
+ .io_in_4_bits_user(r_arb_io_in_4_bits_user),
+ .io_out_ready(r_arb_io_out_ready),
+ .io_out_valid(r_arb_io_out_valid),
+ .io_out_bits_resp(r_arb_io_out_bits_resp),
+ .io_out_bits_data(r_arb_io_out_bits_data),
+ .io_out_bits_last(r_arb_io_out_bits_last),
+ .io_out_bits_id(r_arb_io_out_bits_id),
+ .io_out_bits_user(r_arb_io_out_bits_user)
+ );
+ assign io_master_aw_ready = T_1593;
+ assign io_master_w_ready = T_1594;
+ assign io_master_b_valid = b_arb_io_out_valid;
+ assign io_master_b_bits_resp = b_arb_io_out_bits_resp;
+ assign io_master_b_bits_id = b_arb_io_out_bits_id;
+ assign io_master_b_bits_user = b_arb_io_out_bits_user;
+ assign io_master_ar_ready = T_1591;
+ assign io_master_r_valid = r_arb_io_out_valid;
+ assign io_master_r_bits_resp = r_arb_io_out_bits_resp;
+ assign io_master_r_bits_data = r_arb_io_out_bits_data;
+ assign io_master_r_bits_last = r_arb_io_out_bits_last;
+ assign io_master_r_bits_id = r_arb_io_out_bits_id;
+ assign io_master_r_bits_user = r_arb_io_out_bits_user;
+ assign io_slave_0_aw_valid = T_1505;
+ assign io_slave_0_aw_bits_addr = io_master_aw_bits_addr;
+ assign io_slave_0_aw_bits_len = io_master_aw_bits_len;
+ assign io_slave_0_aw_bits_size = io_master_aw_bits_size;
+ assign io_slave_0_aw_bits_burst = io_master_aw_bits_burst;
+ assign io_slave_0_aw_bits_lock = io_master_aw_bits_lock;
+ assign io_slave_0_aw_bits_cache = io_master_aw_bits_cache;
+ assign io_slave_0_aw_bits_prot = io_master_aw_bits_prot;
+ assign io_slave_0_aw_bits_qos = io_master_aw_bits_qos;
+ assign io_slave_0_aw_bits_region = io_master_aw_bits_region;
+ assign io_slave_0_aw_bits_id = io_master_aw_bits_id;
+ assign io_slave_0_aw_bits_user = io_master_aw_bits_user;
+ assign io_slave_0_w_valid = T_1516;
+ assign io_slave_0_w_bits_data = io_master_w_bits_data;
+ assign io_slave_0_w_bits_last = io_master_w_bits_last;
+ assign io_slave_0_w_bits_strb = io_master_w_bits_strb;
+ assign io_slave_0_w_bits_user = io_master_w_bits_user;
+ assign io_slave_0_b_ready = b_arb_io_in_0_ready;
+ assign io_slave_0_ar_valid = T_1500;
+ assign io_slave_0_ar_bits_addr = io_master_ar_bits_addr;
+ assign io_slave_0_ar_bits_len = io_master_ar_bits_len;
+ assign io_slave_0_ar_bits_size = io_master_ar_bits_size;
+ assign io_slave_0_ar_bits_burst = io_master_ar_bits_burst;
+ assign io_slave_0_ar_bits_lock = io_master_ar_bits_lock;
+ assign io_slave_0_ar_bits_cache = io_master_ar_bits_cache;
+ assign io_slave_0_ar_bits_prot = io_master_ar_bits_prot;
+ assign io_slave_0_ar_bits_qos = io_master_ar_bits_qos;
+ assign io_slave_0_ar_bits_region = io_master_ar_bits_region;
+ assign io_slave_0_ar_bits_id = io_master_ar_bits_id;
+ assign io_slave_0_ar_bits_user = io_master_ar_bits_user;
+ assign io_slave_0_r_ready = r_arb_io_in_0_ready;
+ assign io_slave_1_aw_valid = T_1525;
+ assign io_slave_1_aw_bits_addr = io_master_aw_bits_addr;
+ assign io_slave_1_aw_bits_len = io_master_aw_bits_len;
+ assign io_slave_1_aw_bits_size = io_master_aw_bits_size;
+ assign io_slave_1_aw_bits_burst = io_master_aw_bits_burst;
+ assign io_slave_1_aw_bits_lock = io_master_aw_bits_lock;
+ assign io_slave_1_aw_bits_cache = io_master_aw_bits_cache;
+ assign io_slave_1_aw_bits_prot = io_master_aw_bits_prot;
+ assign io_slave_1_aw_bits_qos = io_master_aw_bits_qos;
+ assign io_slave_1_aw_bits_region = io_master_aw_bits_region;
+ assign io_slave_1_aw_bits_id = io_master_aw_bits_id;
+ assign io_slave_1_aw_bits_user = io_master_aw_bits_user;
+ assign io_slave_1_w_valid = T_1536;
+ assign io_slave_1_w_bits_data = io_master_w_bits_data;
+ assign io_slave_1_w_bits_last = io_master_w_bits_last;
+ assign io_slave_1_w_bits_strb = io_master_w_bits_strb;
+ assign io_slave_1_w_bits_user = io_master_w_bits_user;
+ assign io_slave_1_b_ready = b_arb_io_in_1_ready;
+ assign io_slave_1_ar_valid = T_1520;
+ assign io_slave_1_ar_bits_addr = io_master_ar_bits_addr;
+ assign io_slave_1_ar_bits_len = io_master_ar_bits_len;
+ assign io_slave_1_ar_bits_size = io_master_ar_bits_size;
+ assign io_slave_1_ar_bits_burst = io_master_ar_bits_burst;
+ assign io_slave_1_ar_bits_lock = io_master_ar_bits_lock;
+ assign io_slave_1_ar_bits_cache = io_master_ar_bits_cache;
+ assign io_slave_1_ar_bits_prot = io_master_ar_bits_prot;
+ assign io_slave_1_ar_bits_qos = io_master_ar_bits_qos;
+ assign io_slave_1_ar_bits_region = io_master_ar_bits_region;
+ assign io_slave_1_ar_bits_id = io_master_ar_bits_id;
+ assign io_slave_1_ar_bits_user = io_master_ar_bits_user;
+ assign io_slave_1_r_ready = r_arb_io_in_1_ready;
+ assign io_slave_2_aw_valid = T_1545;
+ assign io_slave_2_aw_bits_addr = io_master_aw_bits_addr;
+ assign io_slave_2_aw_bits_len = io_master_aw_bits_len;
+ assign io_slave_2_aw_bits_size = io_master_aw_bits_size;
+ assign io_slave_2_aw_bits_burst = io_master_aw_bits_burst;
+ assign io_slave_2_aw_bits_lock = io_master_aw_bits_lock;
+ assign io_slave_2_aw_bits_cache = io_master_aw_bits_cache;
+ assign io_slave_2_aw_bits_prot = io_master_aw_bits_prot;
+ assign io_slave_2_aw_bits_qos = io_master_aw_bits_qos;
+ assign io_slave_2_aw_bits_region = io_master_aw_bits_region;
+ assign io_slave_2_aw_bits_id = io_master_aw_bits_id;
+ assign io_slave_2_aw_bits_user = io_master_aw_bits_user;
+ assign io_slave_2_w_valid = T_1556;
+ assign io_slave_2_w_bits_data = io_master_w_bits_data;
+ assign io_slave_2_w_bits_last = io_master_w_bits_last;
+ assign io_slave_2_w_bits_strb = io_master_w_bits_strb;
+ assign io_slave_2_w_bits_user = io_master_w_bits_user;
+ assign io_slave_2_b_ready = b_arb_io_in_2_ready;
+ assign io_slave_2_ar_valid = T_1540;
+ assign io_slave_2_ar_bits_addr = io_master_ar_bits_addr;
+ assign io_slave_2_ar_bits_len = io_master_ar_bits_len;
+ assign io_slave_2_ar_bits_size = io_master_ar_bits_size;
+ assign io_slave_2_ar_bits_burst = io_master_ar_bits_burst;
+ assign io_slave_2_ar_bits_lock = io_master_ar_bits_lock;
+ assign io_slave_2_ar_bits_cache = io_master_ar_bits_cache;
+ assign io_slave_2_ar_bits_prot = io_master_ar_bits_prot;
+ assign io_slave_2_ar_bits_qos = io_master_ar_bits_qos;
+ assign io_slave_2_ar_bits_region = io_master_ar_bits_region;
+ assign io_slave_2_ar_bits_id = io_master_ar_bits_id;
+ assign io_slave_2_ar_bits_user = io_master_ar_bits_user;
+ assign io_slave_2_r_ready = r_arb_io_in_2_ready;
+ assign io_slave_3_aw_valid = T_1565;
+ assign io_slave_3_aw_bits_addr = io_master_aw_bits_addr;
+ assign io_slave_3_aw_bits_len = io_master_aw_bits_len;
+ assign io_slave_3_aw_bits_size = io_master_aw_bits_size;
+ assign io_slave_3_aw_bits_burst = io_master_aw_bits_burst;
+ assign io_slave_3_aw_bits_lock = io_master_aw_bits_lock;
+ assign io_slave_3_aw_bits_cache = io_master_aw_bits_cache;
+ assign io_slave_3_aw_bits_prot = io_master_aw_bits_prot;
+ assign io_slave_3_aw_bits_qos = io_master_aw_bits_qos;
+ assign io_slave_3_aw_bits_region = io_master_aw_bits_region;
+ assign io_slave_3_aw_bits_id = io_master_aw_bits_id;
+ assign io_slave_3_aw_bits_user = io_master_aw_bits_user;
+ assign io_slave_3_w_valid = T_1576;
+ assign io_slave_3_w_bits_data = io_master_w_bits_data;
+ assign io_slave_3_w_bits_last = io_master_w_bits_last;
+ assign io_slave_3_w_bits_strb = io_master_w_bits_strb;
+ assign io_slave_3_w_bits_user = io_master_w_bits_user;
+ assign io_slave_3_b_ready = b_arb_io_in_3_ready;
+ assign io_slave_3_ar_valid = T_1560;
+ assign io_slave_3_ar_bits_addr = io_master_ar_bits_addr;
+ assign io_slave_3_ar_bits_len = io_master_ar_bits_len;
+ assign io_slave_3_ar_bits_size = io_master_ar_bits_size;
+ assign io_slave_3_ar_bits_burst = io_master_ar_bits_burst;
+ assign io_slave_3_ar_bits_lock = io_master_ar_bits_lock;
+ assign io_slave_3_ar_bits_cache = io_master_ar_bits_cache;
+ assign io_slave_3_ar_bits_prot = io_master_ar_bits_prot;
+ assign io_slave_3_ar_bits_qos = io_master_ar_bits_qos;
+ assign io_slave_3_ar_bits_region = io_master_ar_bits_region;
+ assign io_slave_3_ar_bits_id = io_master_ar_bits_id;
+ assign io_slave_3_ar_bits_user = io_master_ar_bits_user;
+ assign io_slave_3_r_ready = r_arb_io_in_3_ready;
+ assign T_1437 = io_master_ar_bits_addr >= 1'h0;
+ assign T_1439 = io_master_ar_bits_addr < 31'h40000000;
+ assign T_1440 = T_1437 & T_1439;
+ assign T_1442 = io_master_ar_bits_addr >= 31'h40000000;
+ assign T_1444 = io_master_ar_bits_addr < 31'h60000000;
+ assign T_1445 = T_1442 & T_1444;
+ assign T_1447 = io_master_ar_bits_addr >= 31'h60000000;
+ assign T_1449 = io_master_ar_bits_addr < 32'h80000000;
+ assign T_1450 = T_1447 & T_1449;
+ assign T_1452 = io_master_ar_bits_addr >= 32'h80000000;
+ assign T_1454 = io_master_ar_bits_addr < 33'h100000000;
+ assign T_1455 = T_1452 & T_1454;
+ assign T_1457_0 = T_1440;
+ assign T_1457_1 = T_1445;
+ assign T_1457_2 = T_1450;
+ assign T_1457_3 = T_1455;
+ assign T_1463 = {T_1457_3,T_1457_2};
+ assign T_1464 = {T_1457_1,T_1457_0};
+ assign ar_route = {T_1463,T_1464};
+ assign T_1467 = io_master_aw_bits_addr >= 1'h0;
+ assign T_1469 = io_master_aw_bits_addr < 31'h40000000;
+ assign T_1470 = T_1467 & T_1469;
+ assign T_1472 = io_master_aw_bits_addr >= 31'h40000000;
+ assign T_1474 = io_master_aw_bits_addr < 31'h60000000;
+ assign T_1475 = T_1472 & T_1474;
+ assign T_1477 = io_master_aw_bits_addr >= 31'h60000000;
+ assign T_1479 = io_master_aw_bits_addr < 32'h80000000;
+ assign T_1480 = T_1477 & T_1479;
+ assign T_1482 = io_master_aw_bits_addr >= 32'h80000000;
+ assign T_1484 = io_master_aw_bits_addr < 33'h100000000;
+ assign T_1485 = T_1482 & T_1484;
+ assign T_1487_0 = T_1470;
+ assign T_1487_1 = T_1475;
+ assign T_1487_2 = T_1480;
+ assign T_1487_3 = T_1485;
+ assign T_1493 = {T_1487_3,T_1487_2};
+ assign T_1494 = {T_1487_1,T_1487_0};
+ assign aw_route = {T_1493,T_1494};
+ assign T_1499 = ar_route[0];
+ assign T_1500 = io_master_ar_valid & T_1499;
+ assign T_1501 = ar_route[0];
+ assign T_1502 = io_slave_0_ar_ready & T_1501;
+ assign T_1503 = 1'h0 | T_1502;
+ assign T_1504 = aw_route[0];
+ assign T_1505 = io_master_aw_valid & T_1504;
+ assign T_1506 = aw_route[0];
+ assign T_1507 = io_slave_0_aw_ready & T_1506;
+ assign T_1508 = 1'h0 | T_1507;
+ assign T_1511 = io_slave_0_aw_ready & io_slave_0_aw_valid;
+ assign T_1513 = io_slave_0_w_ready & io_slave_0_w_valid;
+ assign T_1514 = T_1513 & io_slave_0_w_bits_last;
+ assign T_1516 = io_master_w_valid & T_1510;
+ assign T_1517 = io_slave_0_w_ready & T_1510;
+ assign T_1518 = 1'h0 | T_1517;
+ assign T_1519 = ar_route[1];
+ assign T_1520 = io_master_ar_valid & T_1519;
+ assign T_1521 = ar_route[1];
+ assign T_1522 = io_slave_1_ar_ready & T_1521;
+ assign T_1523 = T_1503 | T_1522;
+ assign T_1524 = aw_route[1];
+ assign T_1525 = io_master_aw_valid & T_1524;
+ assign T_1526 = aw_route[1];
+ assign T_1527 = io_slave_1_aw_ready & T_1526;
+ assign T_1528 = T_1508 | T_1527;
+ assign T_1531 = io_slave_1_aw_ready & io_slave_1_aw_valid;
+ assign T_1533 = io_slave_1_w_ready & io_slave_1_w_valid;
+ assign T_1534 = T_1533 & io_slave_1_w_bits_last;
+ assign T_1536 = io_master_w_valid & T_1530;
+ assign T_1537 = io_slave_1_w_ready & T_1530;
+ assign T_1538 = T_1518 | T_1537;
+ assign T_1539 = ar_route[2];
+ assign T_1540 = io_master_ar_valid & T_1539;
+ assign T_1541 = ar_route[2];
+ assign T_1542 = io_slave_2_ar_ready & T_1541;
+ assign T_1543 = T_1523 | T_1542;
+ assign T_1544 = aw_route[2];
+ assign T_1545 = io_master_aw_valid & T_1544;
+ assign T_1546 = aw_route[2];
+ assign T_1547 = io_slave_2_aw_ready & T_1546;
+ assign T_1548 = T_1528 | T_1547;
+ assign T_1551 = io_slave_2_aw_ready & io_slave_2_aw_valid;
+ assign T_1553 = io_slave_2_w_ready & io_slave_2_w_valid;
+ assign T_1554 = T_1553 & io_slave_2_w_bits_last;
+ assign T_1556 = io_master_w_valid & T_1550;
+ assign T_1557 = io_slave_2_w_ready & T_1550;
+ assign T_1558 = T_1538 | T_1557;
+ assign T_1559 = ar_route[3];
+ assign T_1560 = io_master_ar_valid & T_1559;
+ assign T_1561 = ar_route[3];
+ assign T_1562 = io_slave_3_ar_ready & T_1561;
+ assign ar_ready = T_1543 | T_1562;
+ assign T_1564 = aw_route[3];
+ assign T_1565 = io_master_aw_valid & T_1564;
+ assign T_1566 = aw_route[3];
+ assign T_1567 = io_slave_3_aw_ready & T_1566;
+ assign aw_ready = T_1548 | T_1567;
+ assign T_1571 = io_slave_3_aw_ready & io_slave_3_aw_valid;
+ assign T_1573 = io_slave_3_w_ready & io_slave_3_w_valid;
+ assign T_1574 = T_1573 & io_slave_3_w_bits_last;
+ assign T_1576 = io_master_w_valid & T_1570;
+ assign T_1577 = io_slave_3_w_ready & T_1570;
+ assign w_ready = T_1558 | T_1577;
+ assign T_1580 = ar_route != 1'h0;
+ assign r_invalid = T_1580 == 1'h0;
+ assign T_1584 = aw_route != 1'h0;
+ assign w_invalid = T_1584 == 1'h0;
+ assign err_slave_clk = clk;
+ assign err_slave_reset = reset;
+ assign err_slave_io_aw_valid = T_1589;
+ assign err_slave_io_aw_bits_addr = io_master_aw_bits_addr;
+ assign err_slave_io_aw_bits_len = io_master_aw_bits_len;
+ assign err_slave_io_aw_bits_size = io_master_aw_bits_size;
+ assign err_slave_io_aw_bits_burst = io_master_aw_bits_burst;
+ assign err_slave_io_aw_bits_lock = io_master_aw_bits_lock;
+ assign err_slave_io_aw_bits_cache = io_master_aw_bits_cache;
+ assign err_slave_io_aw_bits_prot = io_master_aw_bits_prot;
+ assign err_slave_io_aw_bits_qos = io_master_aw_bits_qos;
+ assign err_slave_io_aw_bits_region = io_master_aw_bits_region;
+ assign err_slave_io_aw_bits_id = io_master_aw_bits_id;
+ assign err_slave_io_aw_bits_user = io_master_aw_bits_user;
+ assign err_slave_io_w_valid = io_master_w_valid;
+ assign err_slave_io_w_bits_data = io_master_w_bits_data;
+ assign err_slave_io_w_bits_last = io_master_w_bits_last;
+ assign err_slave_io_w_bits_strb = io_master_w_bits_strb;
+ assign err_slave_io_w_bits_user = io_master_w_bits_user;
+ assign err_slave_io_b_ready = b_arb_io_in_4_ready;
+ assign err_slave_io_ar_valid = T_1588;
+ assign err_slave_io_ar_bits_addr = io_master_ar_bits_addr;
+ assign err_slave_io_ar_bits_len = io_master_ar_bits_len;
+ assign err_slave_io_ar_bits_size = io_master_ar_bits_size;
+ assign err_slave_io_ar_bits_burst = io_master_ar_bits_burst;
+ assign err_slave_io_ar_bits_lock = io_master_ar_bits_lock;
+ assign err_slave_io_ar_bits_cache = io_master_ar_bits_cache;
+ assign err_slave_io_ar_bits_prot = io_master_ar_bits_prot;
+ assign err_slave_io_ar_bits_qos = io_master_ar_bits_qos;
+ assign err_slave_io_ar_bits_region = io_master_ar_bits_region;
+ assign err_slave_io_ar_bits_id = io_master_ar_bits_id;
+ assign err_slave_io_ar_bits_user = io_master_ar_bits_user;
+ assign err_slave_io_r_ready = r_arb_io_in_4_ready;
+ assign T_1588 = r_invalid & io_master_ar_valid;
+ assign T_1589 = w_invalid & io_master_aw_valid;
+ assign T_1590 = r_invalid & err_slave_io_ar_ready;
+ assign T_1591 = ar_ready | T_1590;
+ assign T_1592 = w_invalid & err_slave_io_aw_ready;
+ assign T_1593 = aw_ready | T_1592;
+ assign T_1594 = w_ready | err_slave_io_w_ready;
+ assign b_arb_clk = clk;
+ assign b_arb_reset = reset;
+ assign b_arb_io_in_0_valid = io_slave_0_b_valid;
+ assign b_arb_io_in_0_bits_resp = io_slave_0_b_bits_resp;
+ assign b_arb_io_in_0_bits_id = io_slave_0_b_bits_id;
+ assign b_arb_io_in_0_bits_user = io_slave_0_b_bits_user;
+ assign b_arb_io_in_1_valid = io_slave_1_b_valid;
+ assign b_arb_io_in_1_bits_resp = io_slave_1_b_bits_resp;
+ assign b_arb_io_in_1_bits_id = io_slave_1_b_bits_id;
+ assign b_arb_io_in_1_bits_user = io_slave_1_b_bits_user;
+ assign b_arb_io_in_2_valid = io_slave_2_b_valid;
+ assign b_arb_io_in_2_bits_resp = io_slave_2_b_bits_resp;
+ assign b_arb_io_in_2_bits_id = io_slave_2_b_bits_id;
+ assign b_arb_io_in_2_bits_user = io_slave_2_b_bits_user;
+ assign b_arb_io_in_3_valid = io_slave_3_b_valid;
+ assign b_arb_io_in_3_bits_resp = io_slave_3_b_bits_resp;
+ assign b_arb_io_in_3_bits_id = io_slave_3_b_bits_id;
+ assign b_arb_io_in_3_bits_user = io_slave_3_b_bits_user;
+ assign b_arb_io_in_4_valid = err_slave_io_b_valid;
+ assign b_arb_io_in_4_bits_resp = err_slave_io_b_bits_resp;
+ assign b_arb_io_in_4_bits_id = err_slave_io_b_bits_id;
+ assign b_arb_io_in_4_bits_user = err_slave_io_b_bits_user;
+ assign b_arb_io_out_ready = io_master_b_ready;
+ assign r_arb_clk = clk;
+ assign r_arb_reset = reset;
+ assign r_arb_io_in_0_valid = io_slave_0_r_valid;
+ assign r_arb_io_in_0_bits_resp = io_slave_0_r_bits_resp;
+ assign r_arb_io_in_0_bits_data = io_slave_0_r_bits_data;
+ assign r_arb_io_in_0_bits_last = io_slave_0_r_bits_last;
+ assign r_arb_io_in_0_bits_id = io_slave_0_r_bits_id;
+ assign r_arb_io_in_0_bits_user = io_slave_0_r_bits_user;
+ assign r_arb_io_in_1_valid = io_slave_1_r_valid;
+ assign r_arb_io_in_1_bits_resp = io_slave_1_r_bits_resp;
+ assign r_arb_io_in_1_bits_data = io_slave_1_r_bits_data;
+ assign r_arb_io_in_1_bits_last = io_slave_1_r_bits_last;
+ assign r_arb_io_in_1_bits_id = io_slave_1_r_bits_id;
+ assign r_arb_io_in_1_bits_user = io_slave_1_r_bits_user;
+ assign r_arb_io_in_2_valid = io_slave_2_r_valid;
+ assign r_arb_io_in_2_bits_resp = io_slave_2_r_bits_resp;
+ assign r_arb_io_in_2_bits_data = io_slave_2_r_bits_data;
+ assign r_arb_io_in_2_bits_last = io_slave_2_r_bits_last;
+ assign r_arb_io_in_2_bits_id = io_slave_2_r_bits_id;
+ assign r_arb_io_in_2_bits_user = io_slave_2_r_bits_user;
+ assign r_arb_io_in_3_valid = io_slave_3_r_valid;
+ assign r_arb_io_in_3_bits_resp = io_slave_3_r_bits_resp;
+ assign r_arb_io_in_3_bits_data = io_slave_3_r_bits_data;
+ assign r_arb_io_in_3_bits_last = io_slave_3_r_bits_last;
+ assign r_arb_io_in_3_bits_id = io_slave_3_r_bits_id;
+ assign r_arb_io_in_3_bits_user = io_slave_3_r_bits_user;
+ assign r_arb_io_in_4_valid = err_slave_io_r_valid;
+ assign r_arb_io_in_4_bits_resp = err_slave_io_r_bits_resp;
+ assign r_arb_io_in_4_bits_data = err_slave_io_r_bits_data;
+ assign r_arb_io_in_4_bits_last = err_slave_io_r_bits_last;
+ assign r_arb_io_in_4_bits_id = err_slave_io_r_bits_id;
+ assign r_arb_io_in_4_bits_user = err_slave_io_r_bits_user;
+ assign r_arb_io_out_ready = io_master_r_ready;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_1510 = {1{$random}};
+ T_1530 = {1{$random}};
+ T_1550 = {1{$random}};
+ T_1570 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ T_1510 <= 1'h0;
+ end else begin
+ if(T_1514) begin
+ T_1510 <= 1'h0;
+ end else begin
+ if(T_1511) begin
+ T_1510 <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ T_1530 <= 1'h0;
+ end else begin
+ if(T_1534) begin
+ T_1530 <= 1'h0;
+ end else begin
+ if(T_1531) begin
+ T_1530 <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ T_1550 <= 1'h0;
+ end else begin
+ if(T_1554) begin
+ T_1550 <= 1'h0;
+ end else begin
+ if(T_1551) begin
+ T_1550 <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ T_1570 <= 1'h0;
+ end else begin
+ if(T_1574) begin
+ T_1570 <= 1'h0;
+ end else begin
+ if(T_1571) begin
+ T_1570 <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+endmodule
+module RRArbiter_45(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input [31:0] io_in_0_bits_addr,
+ input [7:0] io_in_0_bits_len,
+ input [2:0] io_in_0_bits_size,
+ input [1:0] io_in_0_bits_burst,
+ input io_in_0_bits_lock,
+ input [3:0] io_in_0_bits_cache,
+ input [2:0] io_in_0_bits_prot,
+ input [3:0] io_in_0_bits_qos,
+ input [3:0] io_in_0_bits_region,
+ input [4:0] io_in_0_bits_id,
+ input io_in_0_bits_user,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input [31:0] io_in_1_bits_addr,
+ input [7:0] io_in_1_bits_len,
+ input [2:0] io_in_1_bits_size,
+ input [1:0] io_in_1_bits_burst,
+ input io_in_1_bits_lock,
+ input [3:0] io_in_1_bits_cache,
+ input [2:0] io_in_1_bits_prot,
+ input [3:0] io_in_1_bits_qos,
+ input [3:0] io_in_1_bits_region,
+ input [4:0] io_in_1_bits_id,
+ input io_in_1_bits_user,
+ input io_out_ready,
+ output io_out_valid,
+ output [31:0] io_out_bits_addr,
+ output [7:0] io_out_bits_len,
+ output [2:0] io_out_bits_size,
+ output [1:0] io_out_bits_burst,
+ output io_out_bits_lock,
+ output [3:0] io_out_bits_cache,
+ output [2:0] io_out_bits_prot,
+ output [3:0] io_out_bits_qos,
+ output [3:0] io_out_bits_region,
+ output [4:0] io_out_bits_id,
+ output io_out_bits_user,
+ output io_chosen
+);
+ wire T_306;
+ wire GEN_0;
+ wire [31:0] GEN_1;
+ wire [7:0] GEN_2;
+ wire [2:0] GEN_3;
+ wire [1:0] GEN_4;
+ wire GEN_5;
+ wire [3:0] GEN_6;
+ wire [2:0] GEN_7;
+ wire [3:0] GEN_8;
+ wire [3:0] GEN_9;
+ wire [4:0] GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ reg T_391;
+ wire T_392;
+ wire T_393;
+ wire T_395;
+ wire T_396;
+ wire T_399;
+ wire T_401;
+ wire T_403;
+ wire T_404;
+ wire T_406;
+ wire T_408;
+ wire T_409;
+ wire T_410;
+ wire T_412;
+ wire T_414;
+ wire T_415;
+ wire T_416;
+ wire T_418;
+ wire T_419;
+ wire T_420;
+ wire T_422;
+ wire T_423;
+ wire T_424;
+ wire T_426;
+ wire T_427;
+ wire T_428;
+ wire T_431;
+ wire T_433;
+ wire T_434;
+ wire T_436;
+ wire T_437;
+ wire T_438;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ wire GEN_17;
+ wire GEN_18;
+ wire GEN_19;
+ wire GEN_20;
+ wire GEN_21;
+ wire GEN_22;
+ wire GEN_23;
+ wire GEN_24;
+ assign io_in_0_ready = T_424;
+ assign io_in_1_ready = T_428;
+ assign io_out_valid = GEN_0;
+ assign io_out_bits_addr = GEN_1;
+ assign io_out_bits_len = GEN_2;
+ assign io_out_bits_size = GEN_3;
+ assign io_out_bits_burst = GEN_4;
+ assign io_out_bits_lock = GEN_5;
+ assign io_out_bits_cache = GEN_6;
+ assign io_out_bits_prot = GEN_7;
+ assign io_out_bits_qos = GEN_8;
+ assign io_out_bits_region = GEN_9;
+ assign io_out_bits_id = GEN_10;
+ assign io_out_bits_user = GEN_11;
+ assign io_chosen = T_306;
+ assign T_306 = T_437;
+ assign GEN_0 = GEN_13 ? io_in_1_valid : io_in_0_valid;
+ assign GEN_1 = GEN_14 ? io_in_1_bits_addr : io_in_0_bits_addr;
+ assign GEN_2 = GEN_15 ? io_in_1_bits_len : io_in_0_bits_len;
+ assign GEN_3 = GEN_16 ? io_in_1_bits_size : io_in_0_bits_size;
+ assign GEN_4 = GEN_17 ? io_in_1_bits_burst : io_in_0_bits_burst;
+ assign GEN_5 = GEN_18 ? io_in_1_bits_lock : io_in_0_bits_lock;
+ assign GEN_6 = GEN_19 ? io_in_1_bits_cache : io_in_0_bits_cache;
+ assign GEN_7 = GEN_20 ? io_in_1_bits_prot : io_in_0_bits_prot;
+ assign GEN_8 = GEN_21 ? io_in_1_bits_qos : io_in_0_bits_qos;
+ assign GEN_9 = GEN_22 ? io_in_1_bits_region : io_in_0_bits_region;
+ assign GEN_10 = GEN_23 ? io_in_1_bits_id : io_in_0_bits_id;
+ assign GEN_11 = GEN_24 ? io_in_1_bits_user : io_in_0_bits_user;
+ assign GEN_12 = 1'h0;
+ assign T_392 = 1'h0 > T_391;
+ assign T_393 = io_in_0_valid & T_392;
+ assign T_395 = 1'h1 > T_391;
+ assign T_396 = io_in_1_valid & T_395;
+ assign T_399 = 1'h0 | T_393;
+ assign T_401 = T_399 == 1'h0;
+ assign T_403 = 1'h0 | T_393;
+ assign T_404 = T_403 | T_396;
+ assign T_406 = T_404 == 1'h0;
+ assign T_408 = 1'h0 | T_393;
+ assign T_409 = T_408 | T_396;
+ assign T_410 = T_409 | io_in_0_valid;
+ assign T_412 = T_410 == 1'h0;
+ assign T_414 = 1'h0 > T_391;
+ assign T_415 = 1'h1 & T_414;
+ assign T_416 = T_415 | T_406;
+ assign T_418 = 1'h1 > T_391;
+ assign T_419 = T_401 & T_418;
+ assign T_420 = T_419 | T_412;
+ assign T_422 = 1'h1 == 1'h0;
+ assign T_423 = 1'h0 ? T_422 : T_416;
+ assign T_424 = T_423 & io_out_ready;
+ assign T_426 = 1'h1 == 1'h1;
+ assign T_427 = 1'h0 ? T_426 : T_420;
+ assign T_428 = T_427 & io_out_ready;
+ assign T_431 = io_in_0_valid ? 1'h0 : 1'h1;
+ assign T_433 = 1'h1 > T_391;
+ assign T_434 = io_in_1_valid & T_433;
+ assign T_436 = T_434 ? 1'h1 : T_431;
+ assign T_437 = 1'h0 ? 1'h1 : T_436;
+ assign T_438 = io_out_ready & io_out_valid;
+ assign GEN_13 = 1'h1 == T_306;
+ assign GEN_14 = 1'h1 == T_306;
+ assign GEN_15 = 1'h1 == T_306;
+ assign GEN_16 = 1'h1 == T_306;
+ assign GEN_17 = 1'h1 == T_306;
+ assign GEN_18 = 1'h1 == T_306;
+ assign GEN_19 = 1'h1 == T_306;
+ assign GEN_20 = 1'h1 == T_306;
+ assign GEN_21 = 1'h1 == T_306;
+ assign GEN_22 = 1'h1 == T_306;
+ assign GEN_23 = 1'h1 == T_306;
+ assign GEN_24 = 1'h1 == T_306;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_391 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ T_391 <= 1'h0;
+ end else begin
+ if(T_438) begin
+ T_391 <= T_306;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module NastiArbiter(
+ input clk,
+ input reset,
+ output io_master_0_aw_ready,
+ input io_master_0_aw_valid,
+ input [31:0] io_master_0_aw_bits_addr,
+ input [7:0] io_master_0_aw_bits_len,
+ input [2:0] io_master_0_aw_bits_size,
+ input [1:0] io_master_0_aw_bits_burst,
+ input io_master_0_aw_bits_lock,
+ input [3:0] io_master_0_aw_bits_cache,
+ input [2:0] io_master_0_aw_bits_prot,
+ input [3:0] io_master_0_aw_bits_qos,
+ input [3:0] io_master_0_aw_bits_region,
+ input [4:0] io_master_0_aw_bits_id,
+ input io_master_0_aw_bits_user,
+ output io_master_0_w_ready,
+ input io_master_0_w_valid,
+ input [63:0] io_master_0_w_bits_data,
+ input io_master_0_w_bits_last,
+ input [7:0] io_master_0_w_bits_strb,
+ input io_master_0_w_bits_user,
+ input io_master_0_b_ready,
+ output io_master_0_b_valid,
+ output [1:0] io_master_0_b_bits_resp,
+ output [4:0] io_master_0_b_bits_id,
+ output io_master_0_b_bits_user,
+ output io_master_0_ar_ready,
+ input io_master_0_ar_valid,
+ input [31:0] io_master_0_ar_bits_addr,
+ input [7:0] io_master_0_ar_bits_len,
+ input [2:0] io_master_0_ar_bits_size,
+ input [1:0] io_master_0_ar_bits_burst,
+ input io_master_0_ar_bits_lock,
+ input [3:0] io_master_0_ar_bits_cache,
+ input [2:0] io_master_0_ar_bits_prot,
+ input [3:0] io_master_0_ar_bits_qos,
+ input [3:0] io_master_0_ar_bits_region,
+ input [4:0] io_master_0_ar_bits_id,
+ input io_master_0_ar_bits_user,
+ input io_master_0_r_ready,
+ output io_master_0_r_valid,
+ output [1:0] io_master_0_r_bits_resp,
+ output [63:0] io_master_0_r_bits_data,
+ output io_master_0_r_bits_last,
+ output [4:0] io_master_0_r_bits_id,
+ output io_master_0_r_bits_user,
+ output io_master_1_aw_ready,
+ input io_master_1_aw_valid,
+ input [31:0] io_master_1_aw_bits_addr,
+ input [7:0] io_master_1_aw_bits_len,
+ input [2:0] io_master_1_aw_bits_size,
+ input [1:0] io_master_1_aw_bits_burst,
+ input io_master_1_aw_bits_lock,
+ input [3:0] io_master_1_aw_bits_cache,
+ input [2:0] io_master_1_aw_bits_prot,
+ input [3:0] io_master_1_aw_bits_qos,
+ input [3:0] io_master_1_aw_bits_region,
+ input [4:0] io_master_1_aw_bits_id,
+ input io_master_1_aw_bits_user,
+ output io_master_1_w_ready,
+ input io_master_1_w_valid,
+ input [63:0] io_master_1_w_bits_data,
+ input io_master_1_w_bits_last,
+ input [7:0] io_master_1_w_bits_strb,
+ input io_master_1_w_bits_user,
+ input io_master_1_b_ready,
+ output io_master_1_b_valid,
+ output [1:0] io_master_1_b_bits_resp,
+ output [4:0] io_master_1_b_bits_id,
+ output io_master_1_b_bits_user,
+ output io_master_1_ar_ready,
+ input io_master_1_ar_valid,
+ input [31:0] io_master_1_ar_bits_addr,
+ input [7:0] io_master_1_ar_bits_len,
+ input [2:0] io_master_1_ar_bits_size,
+ input [1:0] io_master_1_ar_bits_burst,
+ input io_master_1_ar_bits_lock,
+ input [3:0] io_master_1_ar_bits_cache,
+ input [2:0] io_master_1_ar_bits_prot,
+ input [3:0] io_master_1_ar_bits_qos,
+ input [3:0] io_master_1_ar_bits_region,
+ input [4:0] io_master_1_ar_bits_id,
+ input io_master_1_ar_bits_user,
+ input io_master_1_r_ready,
+ output io_master_1_r_valid,
+ output [1:0] io_master_1_r_bits_resp,
+ output [63:0] io_master_1_r_bits_data,
+ output io_master_1_r_bits_last,
+ output [4:0] io_master_1_r_bits_id,
+ output io_master_1_r_bits_user,
+ input io_slave_aw_ready,
+ output io_slave_aw_valid,
+ output [31:0] io_slave_aw_bits_addr,
+ output [7:0] io_slave_aw_bits_len,
+ output [2:0] io_slave_aw_bits_size,
+ output [1:0] io_slave_aw_bits_burst,
+ output io_slave_aw_bits_lock,
+ output [3:0] io_slave_aw_bits_cache,
+ output [2:0] io_slave_aw_bits_prot,
+ output [3:0] io_slave_aw_bits_qos,
+ output [3:0] io_slave_aw_bits_region,
+ output [4:0] io_slave_aw_bits_id,
+ output io_slave_aw_bits_user,
+ input io_slave_w_ready,
+ output io_slave_w_valid,
+ output [63:0] io_slave_w_bits_data,
+ output io_slave_w_bits_last,
+ output [7:0] io_slave_w_bits_strb,
+ output io_slave_w_bits_user,
+ output io_slave_b_ready,
+ input io_slave_b_valid,
+ input [1:0] io_slave_b_bits_resp,
+ input [4:0] io_slave_b_bits_id,
+ input io_slave_b_bits_user,
+ input io_slave_ar_ready,
+ output io_slave_ar_valid,
+ output [31:0] io_slave_ar_bits_addr,
+ output [7:0] io_slave_ar_bits_len,
+ output [2:0] io_slave_ar_bits_size,
+ output [1:0] io_slave_ar_bits_burst,
+ output io_slave_ar_bits_lock,
+ output [3:0] io_slave_ar_bits_cache,
+ output [2:0] io_slave_ar_bits_prot,
+ output [3:0] io_slave_ar_bits_qos,
+ output [3:0] io_slave_ar_bits_region,
+ output [4:0] io_slave_ar_bits_id,
+ output io_slave_ar_bits_user,
+ output io_slave_r_ready,
+ input io_slave_r_valid,
+ input [1:0] io_slave_r_bits_resp,
+ input [63:0] io_slave_r_bits_data,
+ input io_slave_r_bits_last,
+ input [4:0] io_slave_r_bits_id,
+ input io_slave_r_bits_user
+);
+ wire T_1767_clk;
+ wire T_1767_reset;
+ wire T_1767_io_in_0_ready;
+ wire T_1767_io_in_0_valid;
+ wire [31:0] T_1767_io_in_0_bits_addr;
+ wire [7:0] T_1767_io_in_0_bits_len;
+ wire [2:0] T_1767_io_in_0_bits_size;
+ wire [1:0] T_1767_io_in_0_bits_burst;
+ wire T_1767_io_in_0_bits_lock;
+ wire [3:0] T_1767_io_in_0_bits_cache;
+ wire [2:0] T_1767_io_in_0_bits_prot;
+ wire [3:0] T_1767_io_in_0_bits_qos;
+ wire [3:0] T_1767_io_in_0_bits_region;
+ wire [4:0] T_1767_io_in_0_bits_id;
+ wire T_1767_io_in_0_bits_user;
+ wire T_1767_io_in_1_ready;
+ wire T_1767_io_in_1_valid;
+ wire [31:0] T_1767_io_in_1_bits_addr;
+ wire [7:0] T_1767_io_in_1_bits_len;
+ wire [2:0] T_1767_io_in_1_bits_size;
+ wire [1:0] T_1767_io_in_1_bits_burst;
+ wire T_1767_io_in_1_bits_lock;
+ wire [3:0] T_1767_io_in_1_bits_cache;
+ wire [2:0] T_1767_io_in_1_bits_prot;
+ wire [3:0] T_1767_io_in_1_bits_qos;
+ wire [3:0] T_1767_io_in_1_bits_region;
+ wire [4:0] T_1767_io_in_1_bits_id;
+ wire T_1767_io_in_1_bits_user;
+ wire T_1767_io_out_ready;
+ wire T_1767_io_out_valid;
+ wire [31:0] T_1767_io_out_bits_addr;
+ wire [7:0] T_1767_io_out_bits_len;
+ wire [2:0] T_1767_io_out_bits_size;
+ wire [1:0] T_1767_io_out_bits_burst;
+ wire T_1767_io_out_bits_lock;
+ wire [3:0] T_1767_io_out_bits_cache;
+ wire [2:0] T_1767_io_out_bits_prot;
+ wire [3:0] T_1767_io_out_bits_qos;
+ wire [3:0] T_1767_io_out_bits_region;
+ wire [4:0] T_1767_io_out_bits_id;
+ wire T_1767_io_out_bits_user;
+ wire T_1767_io_chosen;
+ wire T_1780_clk;
+ wire T_1780_reset;
+ wire T_1780_io_in_0_ready;
+ wire T_1780_io_in_0_valid;
+ wire [31:0] T_1780_io_in_0_bits_addr;
+ wire [7:0] T_1780_io_in_0_bits_len;
+ wire [2:0] T_1780_io_in_0_bits_size;
+ wire [1:0] T_1780_io_in_0_bits_burst;
+ wire T_1780_io_in_0_bits_lock;
+ wire [3:0] T_1780_io_in_0_bits_cache;
+ wire [2:0] T_1780_io_in_0_bits_prot;
+ wire [3:0] T_1780_io_in_0_bits_qos;
+ wire [3:0] T_1780_io_in_0_bits_region;
+ wire [4:0] T_1780_io_in_0_bits_id;
+ wire T_1780_io_in_0_bits_user;
+ wire T_1780_io_in_1_ready;
+ wire T_1780_io_in_1_valid;
+ wire [31:0] T_1780_io_in_1_bits_addr;
+ wire [7:0] T_1780_io_in_1_bits_len;
+ wire [2:0] T_1780_io_in_1_bits_size;
+ wire [1:0] T_1780_io_in_1_bits_burst;
+ wire T_1780_io_in_1_bits_lock;
+ wire [3:0] T_1780_io_in_1_bits_cache;
+ wire [2:0] T_1780_io_in_1_bits_prot;
+ wire [3:0] T_1780_io_in_1_bits_qos;
+ wire [3:0] T_1780_io_in_1_bits_region;
+ wire [4:0] T_1780_io_in_1_bits_id;
+ wire T_1780_io_in_1_bits_user;
+ wire T_1780_io_out_ready;
+ wire T_1780_io_out_valid;
+ wire [31:0] T_1780_io_out_bits_addr;
+ wire [7:0] T_1780_io_out_bits_len;
+ wire [2:0] T_1780_io_out_bits_size;
+ wire [1:0] T_1780_io_out_bits_burst;
+ wire T_1780_io_out_bits_lock;
+ wire [3:0] T_1780_io_out_bits_cache;
+ wire [2:0] T_1780_io_out_bits_prot;
+ wire [3:0] T_1780_io_out_bits_qos;
+ wire [3:0] T_1780_io_out_bits_region;
+ wire [4:0] T_1780_io_out_bits_id;
+ wire T_1780_io_out_bits_user;
+ wire T_1780_io_chosen;
+ wire T_1781;
+ wire T_1782;
+ reg T_1784;
+ reg T_1786;
+ wire T_1787;
+ wire T_1789;
+ wire T_1790;
+ wire [5:0] T_1793;
+ wire [5:0] T_1795;
+ wire T_1797;
+ wire T_1798;
+ wire [4:0] T_1800;
+ wire T_1802;
+ wire T_1803;
+ wire [4:0] T_1805;
+ wire T_1807;
+ wire T_1808;
+ wire T_1810;
+ wire T_1811;
+ wire [5:0] T_1813;
+ wire [5:0] T_1815;
+ wire T_1817;
+ wire T_1818;
+ wire [4:0] T_1820;
+ wire T_1822;
+ wire T_1823;
+ wire [4:0] T_1825;
+ wire T_1827;
+ wire T_1828;
+ wire T_1830;
+ wire T_1831;
+ wire GEN_0;
+ wire GEN_1;
+ wire [63:0] GEN_2;
+ wire GEN_3;
+ wire [7:0] GEN_4;
+ wire GEN_5;
+ wire T_2469;
+ wire GEN_6;
+ wire T_2470;
+ wire T_2471;
+ wire T_2472;
+ wire GEN_7;
+ wire GEN_8;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ RRArbiter_45 T_1767 (
+ .clk(T_1767_clk),
+ .reset(T_1767_reset),
+ .io_in_0_ready(T_1767_io_in_0_ready),
+ .io_in_0_valid(T_1767_io_in_0_valid),
+ .io_in_0_bits_addr(T_1767_io_in_0_bits_addr),
+ .io_in_0_bits_len(T_1767_io_in_0_bits_len),
+ .io_in_0_bits_size(T_1767_io_in_0_bits_size),
+ .io_in_0_bits_burst(T_1767_io_in_0_bits_burst),
+ .io_in_0_bits_lock(T_1767_io_in_0_bits_lock),
+ .io_in_0_bits_cache(T_1767_io_in_0_bits_cache),
+ .io_in_0_bits_prot(T_1767_io_in_0_bits_prot),
+ .io_in_0_bits_qos(T_1767_io_in_0_bits_qos),
+ .io_in_0_bits_region(T_1767_io_in_0_bits_region),
+ .io_in_0_bits_id(T_1767_io_in_0_bits_id),
+ .io_in_0_bits_user(T_1767_io_in_0_bits_user),
+ .io_in_1_ready(T_1767_io_in_1_ready),
+ .io_in_1_valid(T_1767_io_in_1_valid),
+ .io_in_1_bits_addr(T_1767_io_in_1_bits_addr),
+ .io_in_1_bits_len(T_1767_io_in_1_bits_len),
+ .io_in_1_bits_size(T_1767_io_in_1_bits_size),
+ .io_in_1_bits_burst(T_1767_io_in_1_bits_burst),
+ .io_in_1_bits_lock(T_1767_io_in_1_bits_lock),
+ .io_in_1_bits_cache(T_1767_io_in_1_bits_cache),
+ .io_in_1_bits_prot(T_1767_io_in_1_bits_prot),
+ .io_in_1_bits_qos(T_1767_io_in_1_bits_qos),
+ .io_in_1_bits_region(T_1767_io_in_1_bits_region),
+ .io_in_1_bits_id(T_1767_io_in_1_bits_id),
+ .io_in_1_bits_user(T_1767_io_in_1_bits_user),
+ .io_out_ready(T_1767_io_out_ready),
+ .io_out_valid(T_1767_io_out_valid),
+ .io_out_bits_addr(T_1767_io_out_bits_addr),
+ .io_out_bits_len(T_1767_io_out_bits_len),
+ .io_out_bits_size(T_1767_io_out_bits_size),
+ .io_out_bits_burst(T_1767_io_out_bits_burst),
+ .io_out_bits_lock(T_1767_io_out_bits_lock),
+ .io_out_bits_cache(T_1767_io_out_bits_cache),
+ .io_out_bits_prot(T_1767_io_out_bits_prot),
+ .io_out_bits_qos(T_1767_io_out_bits_qos),
+ .io_out_bits_region(T_1767_io_out_bits_region),
+ .io_out_bits_id(T_1767_io_out_bits_id),
+ .io_out_bits_user(T_1767_io_out_bits_user),
+ .io_chosen(T_1767_io_chosen)
+ );
+ RRArbiter_45 T_1780 (
+ .clk(T_1780_clk),
+ .reset(T_1780_reset),
+ .io_in_0_ready(T_1780_io_in_0_ready),
+ .io_in_0_valid(T_1780_io_in_0_valid),
+ .io_in_0_bits_addr(T_1780_io_in_0_bits_addr),
+ .io_in_0_bits_len(T_1780_io_in_0_bits_len),
+ .io_in_0_bits_size(T_1780_io_in_0_bits_size),
+ .io_in_0_bits_burst(T_1780_io_in_0_bits_burst),
+ .io_in_0_bits_lock(T_1780_io_in_0_bits_lock),
+ .io_in_0_bits_cache(T_1780_io_in_0_bits_cache),
+ .io_in_0_bits_prot(T_1780_io_in_0_bits_prot),
+ .io_in_0_bits_qos(T_1780_io_in_0_bits_qos),
+ .io_in_0_bits_region(T_1780_io_in_0_bits_region),
+ .io_in_0_bits_id(T_1780_io_in_0_bits_id),
+ .io_in_0_bits_user(T_1780_io_in_0_bits_user),
+ .io_in_1_ready(T_1780_io_in_1_ready),
+ .io_in_1_valid(T_1780_io_in_1_valid),
+ .io_in_1_bits_addr(T_1780_io_in_1_bits_addr),
+ .io_in_1_bits_len(T_1780_io_in_1_bits_len),
+ .io_in_1_bits_size(T_1780_io_in_1_bits_size),
+ .io_in_1_bits_burst(T_1780_io_in_1_bits_burst),
+ .io_in_1_bits_lock(T_1780_io_in_1_bits_lock),
+ .io_in_1_bits_cache(T_1780_io_in_1_bits_cache),
+ .io_in_1_bits_prot(T_1780_io_in_1_bits_prot),
+ .io_in_1_bits_qos(T_1780_io_in_1_bits_qos),
+ .io_in_1_bits_region(T_1780_io_in_1_bits_region),
+ .io_in_1_bits_id(T_1780_io_in_1_bits_id),
+ .io_in_1_bits_user(T_1780_io_in_1_bits_user),
+ .io_out_ready(T_1780_io_out_ready),
+ .io_out_valid(T_1780_io_out_valid),
+ .io_out_bits_addr(T_1780_io_out_bits_addr),
+ .io_out_bits_len(T_1780_io_out_bits_len),
+ .io_out_bits_size(T_1780_io_out_bits_size),
+ .io_out_bits_burst(T_1780_io_out_bits_burst),
+ .io_out_bits_lock(T_1780_io_out_bits_lock),
+ .io_out_bits_cache(T_1780_io_out_bits_cache),
+ .io_out_bits_prot(T_1780_io_out_bits_prot),
+ .io_out_bits_qos(T_1780_io_out_bits_qos),
+ .io_out_bits_region(T_1780_io_out_bits_region),
+ .io_out_bits_id(T_1780_io_out_bits_id),
+ .io_out_bits_user(T_1780_io_out_bits_user),
+ .io_chosen(T_1780_io_chosen)
+ );
+ assign io_master_0_aw_ready = T_1780_io_in_0_ready;
+ assign io_master_0_w_ready = T_1811;
+ assign io_master_0_b_valid = T_1803;
+ assign io_master_0_b_bits_resp = io_slave_b_bits_resp;
+ assign io_master_0_b_bits_id = T_1805;
+ assign io_master_0_b_bits_user = io_slave_b_bits_user;
+ assign io_master_0_ar_ready = T_1767_io_in_0_ready;
+ assign io_master_0_r_valid = T_1798;
+ assign io_master_0_r_bits_resp = io_slave_r_bits_resp;
+ assign io_master_0_r_bits_data = io_slave_r_bits_data;
+ assign io_master_0_r_bits_last = io_slave_r_bits_last;
+ assign io_master_0_r_bits_id = T_1800;
+ assign io_master_0_r_bits_user = io_slave_r_bits_user;
+ assign io_master_1_aw_ready = T_1780_io_in_1_ready;
+ assign io_master_1_w_ready = T_1831;
+ assign io_master_1_b_valid = T_1823;
+ assign io_master_1_b_bits_resp = io_slave_b_bits_resp;
+ assign io_master_1_b_bits_id = T_1825;
+ assign io_master_1_b_bits_user = io_slave_b_bits_user;
+ assign io_master_1_ar_ready = T_1767_io_in_1_ready;
+ assign io_master_1_r_valid = T_1818;
+ assign io_master_1_r_bits_resp = io_slave_r_bits_resp;
+ assign io_master_1_r_bits_data = io_slave_r_bits_data;
+ assign io_master_1_r_bits_last = io_slave_r_bits_last;
+ assign io_master_1_r_bits_id = T_1820;
+ assign io_master_1_r_bits_user = io_slave_r_bits_user;
+ assign io_slave_aw_valid = T_2471;
+ assign io_slave_aw_bits_addr = T_1780_io_out_bits_addr;
+ assign io_slave_aw_bits_len = T_1780_io_out_bits_len;
+ assign io_slave_aw_bits_size = T_1780_io_out_bits_size;
+ assign io_slave_aw_bits_burst = T_1780_io_out_bits_burst;
+ assign io_slave_aw_bits_lock = T_1780_io_out_bits_lock;
+ assign io_slave_aw_bits_cache = T_1780_io_out_bits_cache;
+ assign io_slave_aw_bits_prot = T_1780_io_out_bits_prot;
+ assign io_slave_aw_bits_qos = T_1780_io_out_bits_qos;
+ assign io_slave_aw_bits_region = T_1780_io_out_bits_region;
+ assign io_slave_aw_bits_id = T_1780_io_out_bits_id;
+ assign io_slave_aw_bits_user = T_1780_io_out_bits_user;
+ assign io_slave_w_valid = T_2470;
+ assign io_slave_w_bits_data = GEN_2;
+ assign io_slave_w_bits_last = GEN_3;
+ assign io_slave_w_bits_strb = GEN_4;
+ assign io_slave_w_bits_user = GEN_5;
+ assign io_slave_b_ready = GEN_1;
+ assign io_slave_ar_valid = T_1767_io_out_valid;
+ assign io_slave_ar_bits_addr = T_1767_io_out_bits_addr;
+ assign io_slave_ar_bits_len = T_1767_io_out_bits_len;
+ assign io_slave_ar_bits_size = T_1767_io_out_bits_size;
+ assign io_slave_ar_bits_burst = T_1767_io_out_bits_burst;
+ assign io_slave_ar_bits_lock = T_1767_io_out_bits_lock;
+ assign io_slave_ar_bits_cache = T_1767_io_out_bits_cache;
+ assign io_slave_ar_bits_prot = T_1767_io_out_bits_prot;
+ assign io_slave_ar_bits_qos = T_1767_io_out_bits_qos;
+ assign io_slave_ar_bits_region = T_1767_io_out_bits_region;
+ assign io_slave_ar_bits_id = T_1767_io_out_bits_id;
+ assign io_slave_ar_bits_user = T_1767_io_out_bits_user;
+ assign io_slave_r_ready = GEN_0;
+ assign T_1767_clk = clk;
+ assign T_1767_reset = reset;
+ assign T_1767_io_in_0_valid = io_master_0_ar_valid;
+ assign T_1767_io_in_0_bits_addr = io_master_0_ar_bits_addr;
+ assign T_1767_io_in_0_bits_len = io_master_0_ar_bits_len;
+ assign T_1767_io_in_0_bits_size = io_master_0_ar_bits_size;
+ assign T_1767_io_in_0_bits_burst = io_master_0_ar_bits_burst;
+ assign T_1767_io_in_0_bits_lock = io_master_0_ar_bits_lock;
+ assign T_1767_io_in_0_bits_cache = io_master_0_ar_bits_cache;
+ assign T_1767_io_in_0_bits_prot = io_master_0_ar_bits_prot;
+ assign T_1767_io_in_0_bits_qos = io_master_0_ar_bits_qos;
+ assign T_1767_io_in_0_bits_region = io_master_0_ar_bits_region;
+ assign T_1767_io_in_0_bits_id = T_1793;
+ assign T_1767_io_in_0_bits_user = io_master_0_ar_bits_user;
+ assign T_1767_io_in_1_valid = io_master_1_ar_valid;
+ assign T_1767_io_in_1_bits_addr = io_master_1_ar_bits_addr;
+ assign T_1767_io_in_1_bits_len = io_master_1_ar_bits_len;
+ assign T_1767_io_in_1_bits_size = io_master_1_ar_bits_size;
+ assign T_1767_io_in_1_bits_burst = io_master_1_ar_bits_burst;
+ assign T_1767_io_in_1_bits_lock = io_master_1_ar_bits_lock;
+ assign T_1767_io_in_1_bits_cache = io_master_1_ar_bits_cache;
+ assign T_1767_io_in_1_bits_prot = io_master_1_ar_bits_prot;
+ assign T_1767_io_in_1_bits_qos = io_master_1_ar_bits_qos;
+ assign T_1767_io_in_1_bits_region = io_master_1_ar_bits_region;
+ assign T_1767_io_in_1_bits_id = T_1813;
+ assign T_1767_io_in_1_bits_user = io_master_1_ar_bits_user;
+ assign T_1767_io_out_ready = io_slave_ar_ready;
+ assign T_1780_clk = clk;
+ assign T_1780_reset = reset;
+ assign T_1780_io_in_0_valid = io_master_0_aw_valid;
+ assign T_1780_io_in_0_bits_addr = io_master_0_aw_bits_addr;
+ assign T_1780_io_in_0_bits_len = io_master_0_aw_bits_len;
+ assign T_1780_io_in_0_bits_size = io_master_0_aw_bits_size;
+ assign T_1780_io_in_0_bits_burst = io_master_0_aw_bits_burst;
+ assign T_1780_io_in_0_bits_lock = io_master_0_aw_bits_lock;
+ assign T_1780_io_in_0_bits_cache = io_master_0_aw_bits_cache;
+ assign T_1780_io_in_0_bits_prot = io_master_0_aw_bits_prot;
+ assign T_1780_io_in_0_bits_qos = io_master_0_aw_bits_qos;
+ assign T_1780_io_in_0_bits_region = io_master_0_aw_bits_region;
+ assign T_1780_io_in_0_bits_id = T_1795;
+ assign T_1780_io_in_0_bits_user = io_master_0_aw_bits_user;
+ assign T_1780_io_in_1_valid = io_master_1_aw_valid;
+ assign T_1780_io_in_1_bits_addr = io_master_1_aw_bits_addr;
+ assign T_1780_io_in_1_bits_len = io_master_1_aw_bits_len;
+ assign T_1780_io_in_1_bits_size = io_master_1_aw_bits_size;
+ assign T_1780_io_in_1_bits_burst = io_master_1_aw_bits_burst;
+ assign T_1780_io_in_1_bits_lock = io_master_1_aw_bits_lock;
+ assign T_1780_io_in_1_bits_cache = io_master_1_aw_bits_cache;
+ assign T_1780_io_in_1_bits_prot = io_master_1_aw_bits_prot;
+ assign T_1780_io_in_1_bits_qos = io_master_1_aw_bits_qos;
+ assign T_1780_io_in_1_bits_region = io_master_1_aw_bits_region;
+ assign T_1780_io_in_1_bits_id = T_1815;
+ assign T_1780_io_in_1_bits_user = io_master_1_aw_bits_user;
+ assign T_1780_io_out_ready = T_2472;
+ assign T_1781 = io_slave_r_bits_id[0];
+ assign T_1782 = io_slave_b_bits_id[0];
+ assign T_1787 = T_1780_io_out_ready & T_1780_io_out_valid;
+ assign T_1789 = io_slave_w_ready & io_slave_w_valid;
+ assign T_1790 = T_1789 & io_slave_w_bits_last;
+ assign T_1793 = {io_master_0_ar_bits_id,1'h0};
+ assign T_1795 = {io_master_0_aw_bits_id,1'h0};
+ assign T_1797 = T_1781 == 1'h0;
+ assign T_1798 = io_slave_r_valid & T_1797;
+ assign T_1800 = io_slave_r_bits_id >> 1'h1;
+ assign T_1802 = T_1782 == 1'h0;
+ assign T_1803 = io_slave_b_valid & T_1802;
+ assign T_1805 = io_slave_b_bits_id >> 1'h1;
+ assign T_1807 = T_1784 == 1'h0;
+ assign T_1808 = io_slave_w_ready & T_1807;
+ assign T_1810 = T_1786 == 1'h0;
+ assign T_1811 = T_1808 & T_1810;
+ assign T_1813 = {io_master_1_ar_bits_id,1'h1};
+ assign T_1815 = {io_master_1_aw_bits_id,1'h1};
+ assign T_1817 = T_1781 == 1'h1;
+ assign T_1818 = io_slave_r_valid & T_1817;
+ assign T_1820 = io_slave_r_bits_id >> 1'h1;
+ assign T_1822 = T_1782 == 1'h1;
+ assign T_1823 = io_slave_b_valid & T_1822;
+ assign T_1825 = io_slave_b_bits_id >> 1'h1;
+ assign T_1827 = T_1784 == 1'h1;
+ assign T_1828 = io_slave_w_ready & T_1827;
+ assign T_1830 = T_1786 == 1'h0;
+ assign T_1831 = T_1828 & T_1830;
+ assign GEN_0 = GEN_7 ? io_master_1_r_ready : io_master_0_r_ready;
+ assign GEN_1 = GEN_8 ? io_master_1_b_ready : io_master_0_b_ready;
+ assign GEN_2 = GEN_9 ? io_master_1_w_bits_data : io_master_0_w_bits_data;
+ assign GEN_3 = GEN_10 ? io_master_1_w_bits_last : io_master_0_w_bits_last;
+ assign GEN_4 = GEN_11 ? io_master_1_w_bits_strb : io_master_0_w_bits_strb;
+ assign GEN_5 = GEN_12 ? io_master_1_w_bits_user : io_master_0_w_bits_user;
+ assign T_2469 = T_1786 == 1'h0;
+ assign GEN_6 = GEN_13 ? io_master_1_w_valid : io_master_0_w_valid;
+ assign T_2470 = GEN_6 & T_2469;
+ assign T_2471 = T_1780_io_out_valid & T_1786;
+ assign T_2472 = io_slave_aw_ready & T_1786;
+ assign GEN_7 = 1'h1 == T_1781;
+ assign GEN_8 = 1'h1 == T_1782;
+ assign GEN_9 = 1'h1 == T_1784;
+ assign GEN_10 = 1'h1 == T_1784;
+ assign GEN_11 = 1'h1 == T_1784;
+ assign GEN_12 = 1'h1 == T_1784;
+ assign GEN_13 = 1'h1 == T_1784;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_1784 = {1{$random}};
+ T_1786 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1787) begin
+ T_1784 <= T_1780_io_chosen;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_1786 <= 1'h1;
+ end else begin
+ if(T_1790) begin
+ T_1786 <= 1'h1;
+ end else begin
+ if(T_1787) begin
+ T_1786 <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+endmodule
+module NastiCrossbar(
+ input clk,
+ input reset,
+ output io_masters_0_aw_ready,
+ input io_masters_0_aw_valid,
+ input [31:0] io_masters_0_aw_bits_addr,
+ input [7:0] io_masters_0_aw_bits_len,
+ input [2:0] io_masters_0_aw_bits_size,
+ input [1:0] io_masters_0_aw_bits_burst,
+ input io_masters_0_aw_bits_lock,
+ input [3:0] io_masters_0_aw_bits_cache,
+ input [2:0] io_masters_0_aw_bits_prot,
+ input [3:0] io_masters_0_aw_bits_qos,
+ input [3:0] io_masters_0_aw_bits_region,
+ input [4:0] io_masters_0_aw_bits_id,
+ input io_masters_0_aw_bits_user,
+ output io_masters_0_w_ready,
+ input io_masters_0_w_valid,
+ input [63:0] io_masters_0_w_bits_data,
+ input io_masters_0_w_bits_last,
+ input [7:0] io_masters_0_w_bits_strb,
+ input io_masters_0_w_bits_user,
+ input io_masters_0_b_ready,
+ output io_masters_0_b_valid,
+ output [1:0] io_masters_0_b_bits_resp,
+ output [4:0] io_masters_0_b_bits_id,
+ output io_masters_0_b_bits_user,
+ output io_masters_0_ar_ready,
+ input io_masters_0_ar_valid,
+ input [31:0] io_masters_0_ar_bits_addr,
+ input [7:0] io_masters_0_ar_bits_len,
+ input [2:0] io_masters_0_ar_bits_size,
+ input [1:0] io_masters_0_ar_bits_burst,
+ input io_masters_0_ar_bits_lock,
+ input [3:0] io_masters_0_ar_bits_cache,
+ input [2:0] io_masters_0_ar_bits_prot,
+ input [3:0] io_masters_0_ar_bits_qos,
+ input [3:0] io_masters_0_ar_bits_region,
+ input [4:0] io_masters_0_ar_bits_id,
+ input io_masters_0_ar_bits_user,
+ input io_masters_0_r_ready,
+ output io_masters_0_r_valid,
+ output [1:0] io_masters_0_r_bits_resp,
+ output [63:0] io_masters_0_r_bits_data,
+ output io_masters_0_r_bits_last,
+ output [4:0] io_masters_0_r_bits_id,
+ output io_masters_0_r_bits_user,
+ output io_masters_1_aw_ready,
+ input io_masters_1_aw_valid,
+ input [31:0] io_masters_1_aw_bits_addr,
+ input [7:0] io_masters_1_aw_bits_len,
+ input [2:0] io_masters_1_aw_bits_size,
+ input [1:0] io_masters_1_aw_bits_burst,
+ input io_masters_1_aw_bits_lock,
+ input [3:0] io_masters_1_aw_bits_cache,
+ input [2:0] io_masters_1_aw_bits_prot,
+ input [3:0] io_masters_1_aw_bits_qos,
+ input [3:0] io_masters_1_aw_bits_region,
+ input [4:0] io_masters_1_aw_bits_id,
+ input io_masters_1_aw_bits_user,
+ output io_masters_1_w_ready,
+ input io_masters_1_w_valid,
+ input [63:0] io_masters_1_w_bits_data,
+ input io_masters_1_w_bits_last,
+ input [7:0] io_masters_1_w_bits_strb,
+ input io_masters_1_w_bits_user,
+ input io_masters_1_b_ready,
+ output io_masters_1_b_valid,
+ output [1:0] io_masters_1_b_bits_resp,
+ output [4:0] io_masters_1_b_bits_id,
+ output io_masters_1_b_bits_user,
+ output io_masters_1_ar_ready,
+ input io_masters_1_ar_valid,
+ input [31:0] io_masters_1_ar_bits_addr,
+ input [7:0] io_masters_1_ar_bits_len,
+ input [2:0] io_masters_1_ar_bits_size,
+ input [1:0] io_masters_1_ar_bits_burst,
+ input io_masters_1_ar_bits_lock,
+ input [3:0] io_masters_1_ar_bits_cache,
+ input [2:0] io_masters_1_ar_bits_prot,
+ input [3:0] io_masters_1_ar_bits_qos,
+ input [3:0] io_masters_1_ar_bits_region,
+ input [4:0] io_masters_1_ar_bits_id,
+ input io_masters_1_ar_bits_user,
+ input io_masters_1_r_ready,
+ output io_masters_1_r_valid,
+ output [1:0] io_masters_1_r_bits_resp,
+ output [63:0] io_masters_1_r_bits_data,
+ output io_masters_1_r_bits_last,
+ output [4:0] io_masters_1_r_bits_id,
+ output io_masters_1_r_bits_user,
+ input io_slaves_0_aw_ready,
+ output io_slaves_0_aw_valid,
+ output [31:0] io_slaves_0_aw_bits_addr,
+ output [7:0] io_slaves_0_aw_bits_len,
+ output [2:0] io_slaves_0_aw_bits_size,
+ output [1:0] io_slaves_0_aw_bits_burst,
+ output io_slaves_0_aw_bits_lock,
+ output [3:0] io_slaves_0_aw_bits_cache,
+ output [2:0] io_slaves_0_aw_bits_prot,
+ output [3:0] io_slaves_0_aw_bits_qos,
+ output [3:0] io_slaves_0_aw_bits_region,
+ output [4:0] io_slaves_0_aw_bits_id,
+ output io_slaves_0_aw_bits_user,
+ input io_slaves_0_w_ready,
+ output io_slaves_0_w_valid,
+ output [63:0] io_slaves_0_w_bits_data,
+ output io_slaves_0_w_bits_last,
+ output [7:0] io_slaves_0_w_bits_strb,
+ output io_slaves_0_w_bits_user,
+ output io_slaves_0_b_ready,
+ input io_slaves_0_b_valid,
+ input [1:0] io_slaves_0_b_bits_resp,
+ input [4:0] io_slaves_0_b_bits_id,
+ input io_slaves_0_b_bits_user,
+ input io_slaves_0_ar_ready,
+ output io_slaves_0_ar_valid,
+ output [31:0] io_slaves_0_ar_bits_addr,
+ output [7:0] io_slaves_0_ar_bits_len,
+ output [2:0] io_slaves_0_ar_bits_size,
+ output [1:0] io_slaves_0_ar_bits_burst,
+ output io_slaves_0_ar_bits_lock,
+ output [3:0] io_slaves_0_ar_bits_cache,
+ output [2:0] io_slaves_0_ar_bits_prot,
+ output [3:0] io_slaves_0_ar_bits_qos,
+ output [3:0] io_slaves_0_ar_bits_region,
+ output [4:0] io_slaves_0_ar_bits_id,
+ output io_slaves_0_ar_bits_user,
+ output io_slaves_0_r_ready,
+ input io_slaves_0_r_valid,
+ input [1:0] io_slaves_0_r_bits_resp,
+ input [63:0] io_slaves_0_r_bits_data,
+ input io_slaves_0_r_bits_last,
+ input [4:0] io_slaves_0_r_bits_id,
+ input io_slaves_0_r_bits_user,
+ input io_slaves_1_aw_ready,
+ output io_slaves_1_aw_valid,
+ output [31:0] io_slaves_1_aw_bits_addr,
+ output [7:0] io_slaves_1_aw_bits_len,
+ output [2:0] io_slaves_1_aw_bits_size,
+ output [1:0] io_slaves_1_aw_bits_burst,
+ output io_slaves_1_aw_bits_lock,
+ output [3:0] io_slaves_1_aw_bits_cache,
+ output [2:0] io_slaves_1_aw_bits_prot,
+ output [3:0] io_slaves_1_aw_bits_qos,
+ output [3:0] io_slaves_1_aw_bits_region,
+ output [4:0] io_slaves_1_aw_bits_id,
+ output io_slaves_1_aw_bits_user,
+ input io_slaves_1_w_ready,
+ output io_slaves_1_w_valid,
+ output [63:0] io_slaves_1_w_bits_data,
+ output io_slaves_1_w_bits_last,
+ output [7:0] io_slaves_1_w_bits_strb,
+ output io_slaves_1_w_bits_user,
+ output io_slaves_1_b_ready,
+ input io_slaves_1_b_valid,
+ input [1:0] io_slaves_1_b_bits_resp,
+ input [4:0] io_slaves_1_b_bits_id,
+ input io_slaves_1_b_bits_user,
+ input io_slaves_1_ar_ready,
+ output io_slaves_1_ar_valid,
+ output [31:0] io_slaves_1_ar_bits_addr,
+ output [7:0] io_slaves_1_ar_bits_len,
+ output [2:0] io_slaves_1_ar_bits_size,
+ output [1:0] io_slaves_1_ar_bits_burst,
+ output io_slaves_1_ar_bits_lock,
+ output [3:0] io_slaves_1_ar_bits_cache,
+ output [2:0] io_slaves_1_ar_bits_prot,
+ output [3:0] io_slaves_1_ar_bits_qos,
+ output [3:0] io_slaves_1_ar_bits_region,
+ output [4:0] io_slaves_1_ar_bits_id,
+ output io_slaves_1_ar_bits_user,
+ output io_slaves_1_r_ready,
+ input io_slaves_1_r_valid,
+ input [1:0] io_slaves_1_r_bits_resp,
+ input [63:0] io_slaves_1_r_bits_data,
+ input io_slaves_1_r_bits_last,
+ input [4:0] io_slaves_1_r_bits_id,
+ input io_slaves_1_r_bits_user,
+ input io_slaves_2_aw_ready,
+ output io_slaves_2_aw_valid,
+ output [31:0] io_slaves_2_aw_bits_addr,
+ output [7:0] io_slaves_2_aw_bits_len,
+ output [2:0] io_slaves_2_aw_bits_size,
+ output [1:0] io_slaves_2_aw_bits_burst,
+ output io_slaves_2_aw_bits_lock,
+ output [3:0] io_slaves_2_aw_bits_cache,
+ output [2:0] io_slaves_2_aw_bits_prot,
+ output [3:0] io_slaves_2_aw_bits_qos,
+ output [3:0] io_slaves_2_aw_bits_region,
+ output [4:0] io_slaves_2_aw_bits_id,
+ output io_slaves_2_aw_bits_user,
+ input io_slaves_2_w_ready,
+ output io_slaves_2_w_valid,
+ output [63:0] io_slaves_2_w_bits_data,
+ output io_slaves_2_w_bits_last,
+ output [7:0] io_slaves_2_w_bits_strb,
+ output io_slaves_2_w_bits_user,
+ output io_slaves_2_b_ready,
+ input io_slaves_2_b_valid,
+ input [1:0] io_slaves_2_b_bits_resp,
+ input [4:0] io_slaves_2_b_bits_id,
+ input io_slaves_2_b_bits_user,
+ input io_slaves_2_ar_ready,
+ output io_slaves_2_ar_valid,
+ output [31:0] io_slaves_2_ar_bits_addr,
+ output [7:0] io_slaves_2_ar_bits_len,
+ output [2:0] io_slaves_2_ar_bits_size,
+ output [1:0] io_slaves_2_ar_bits_burst,
+ output io_slaves_2_ar_bits_lock,
+ output [3:0] io_slaves_2_ar_bits_cache,
+ output [2:0] io_slaves_2_ar_bits_prot,
+ output [3:0] io_slaves_2_ar_bits_qos,
+ output [3:0] io_slaves_2_ar_bits_region,
+ output [4:0] io_slaves_2_ar_bits_id,
+ output io_slaves_2_ar_bits_user,
+ output io_slaves_2_r_ready,
+ input io_slaves_2_r_valid,
+ input [1:0] io_slaves_2_r_bits_resp,
+ input [63:0] io_slaves_2_r_bits_data,
+ input io_slaves_2_r_bits_last,
+ input [4:0] io_slaves_2_r_bits_id,
+ input io_slaves_2_r_bits_user,
+ input io_slaves_3_aw_ready,
+ output io_slaves_3_aw_valid,
+ output [31:0] io_slaves_3_aw_bits_addr,
+ output [7:0] io_slaves_3_aw_bits_len,
+ output [2:0] io_slaves_3_aw_bits_size,
+ output [1:0] io_slaves_3_aw_bits_burst,
+ output io_slaves_3_aw_bits_lock,
+ output [3:0] io_slaves_3_aw_bits_cache,
+ output [2:0] io_slaves_3_aw_bits_prot,
+ output [3:0] io_slaves_3_aw_bits_qos,
+ output [3:0] io_slaves_3_aw_bits_region,
+ output [4:0] io_slaves_3_aw_bits_id,
+ output io_slaves_3_aw_bits_user,
+ input io_slaves_3_w_ready,
+ output io_slaves_3_w_valid,
+ output [63:0] io_slaves_3_w_bits_data,
+ output io_slaves_3_w_bits_last,
+ output [7:0] io_slaves_3_w_bits_strb,
+ output io_slaves_3_w_bits_user,
+ output io_slaves_3_b_ready,
+ input io_slaves_3_b_valid,
+ input [1:0] io_slaves_3_b_bits_resp,
+ input [4:0] io_slaves_3_b_bits_id,
+ input io_slaves_3_b_bits_user,
+ input io_slaves_3_ar_ready,
+ output io_slaves_3_ar_valid,
+ output [31:0] io_slaves_3_ar_bits_addr,
+ output [7:0] io_slaves_3_ar_bits_len,
+ output [2:0] io_slaves_3_ar_bits_size,
+ output [1:0] io_slaves_3_ar_bits_burst,
+ output io_slaves_3_ar_bits_lock,
+ output [3:0] io_slaves_3_ar_bits_cache,
+ output [2:0] io_slaves_3_ar_bits_prot,
+ output [3:0] io_slaves_3_ar_bits_qos,
+ output [3:0] io_slaves_3_ar_bits_region,
+ output [4:0] io_slaves_3_ar_bits_id,
+ output io_slaves_3_ar_bits_user,
+ output io_slaves_3_r_ready,
+ input io_slaves_3_r_valid,
+ input [1:0] io_slaves_3_r_bits_resp,
+ input [63:0] io_slaves_3_r_bits_data,
+ input io_slaves_3_r_bits_last,
+ input [4:0] io_slaves_3_r_bits_id,
+ input io_slaves_3_r_bits_user
+);
+ wire T_2710_clk;
+ wire T_2710_reset;
+ wire T_2710_io_master_aw_ready;
+ wire T_2710_io_master_aw_valid;
+ wire [31:0] T_2710_io_master_aw_bits_addr;
+ wire [7:0] T_2710_io_master_aw_bits_len;
+ wire [2:0] T_2710_io_master_aw_bits_size;
+ wire [1:0] T_2710_io_master_aw_bits_burst;
+ wire T_2710_io_master_aw_bits_lock;
+ wire [3:0] T_2710_io_master_aw_bits_cache;
+ wire [2:0] T_2710_io_master_aw_bits_prot;
+ wire [3:0] T_2710_io_master_aw_bits_qos;
+ wire [3:0] T_2710_io_master_aw_bits_region;
+ wire [4:0] T_2710_io_master_aw_bits_id;
+ wire T_2710_io_master_aw_bits_user;
+ wire T_2710_io_master_w_ready;
+ wire T_2710_io_master_w_valid;
+ wire [63:0] T_2710_io_master_w_bits_data;
+ wire T_2710_io_master_w_bits_last;
+ wire [7:0] T_2710_io_master_w_bits_strb;
+ wire T_2710_io_master_w_bits_user;
+ wire T_2710_io_master_b_ready;
+ wire T_2710_io_master_b_valid;
+ wire [1:0] T_2710_io_master_b_bits_resp;
+ wire [4:0] T_2710_io_master_b_bits_id;
+ wire T_2710_io_master_b_bits_user;
+ wire T_2710_io_master_ar_ready;
+ wire T_2710_io_master_ar_valid;
+ wire [31:0] T_2710_io_master_ar_bits_addr;
+ wire [7:0] T_2710_io_master_ar_bits_len;
+ wire [2:0] T_2710_io_master_ar_bits_size;
+ wire [1:0] T_2710_io_master_ar_bits_burst;
+ wire T_2710_io_master_ar_bits_lock;
+ wire [3:0] T_2710_io_master_ar_bits_cache;
+ wire [2:0] T_2710_io_master_ar_bits_prot;
+ wire [3:0] T_2710_io_master_ar_bits_qos;
+ wire [3:0] T_2710_io_master_ar_bits_region;
+ wire [4:0] T_2710_io_master_ar_bits_id;
+ wire T_2710_io_master_ar_bits_user;
+ wire T_2710_io_master_r_ready;
+ wire T_2710_io_master_r_valid;
+ wire [1:0] T_2710_io_master_r_bits_resp;
+ wire [63:0] T_2710_io_master_r_bits_data;
+ wire T_2710_io_master_r_bits_last;
+ wire [4:0] T_2710_io_master_r_bits_id;
+ wire T_2710_io_master_r_bits_user;
+ wire T_2710_io_slave_0_aw_ready;
+ wire T_2710_io_slave_0_aw_valid;
+ wire [31:0] T_2710_io_slave_0_aw_bits_addr;
+ wire [7:0] T_2710_io_slave_0_aw_bits_len;
+ wire [2:0] T_2710_io_slave_0_aw_bits_size;
+ wire [1:0] T_2710_io_slave_0_aw_bits_burst;
+ wire T_2710_io_slave_0_aw_bits_lock;
+ wire [3:0] T_2710_io_slave_0_aw_bits_cache;
+ wire [2:0] T_2710_io_slave_0_aw_bits_prot;
+ wire [3:0] T_2710_io_slave_0_aw_bits_qos;
+ wire [3:0] T_2710_io_slave_0_aw_bits_region;
+ wire [4:0] T_2710_io_slave_0_aw_bits_id;
+ wire T_2710_io_slave_0_aw_bits_user;
+ wire T_2710_io_slave_0_w_ready;
+ wire T_2710_io_slave_0_w_valid;
+ wire [63:0] T_2710_io_slave_0_w_bits_data;
+ wire T_2710_io_slave_0_w_bits_last;
+ wire [7:0] T_2710_io_slave_0_w_bits_strb;
+ wire T_2710_io_slave_0_w_bits_user;
+ wire T_2710_io_slave_0_b_ready;
+ wire T_2710_io_slave_0_b_valid;
+ wire [1:0] T_2710_io_slave_0_b_bits_resp;
+ wire [4:0] T_2710_io_slave_0_b_bits_id;
+ wire T_2710_io_slave_0_b_bits_user;
+ wire T_2710_io_slave_0_ar_ready;
+ wire T_2710_io_slave_0_ar_valid;
+ wire [31:0] T_2710_io_slave_0_ar_bits_addr;
+ wire [7:0] T_2710_io_slave_0_ar_bits_len;
+ wire [2:0] T_2710_io_slave_0_ar_bits_size;
+ wire [1:0] T_2710_io_slave_0_ar_bits_burst;
+ wire T_2710_io_slave_0_ar_bits_lock;
+ wire [3:0] T_2710_io_slave_0_ar_bits_cache;
+ wire [2:0] T_2710_io_slave_0_ar_bits_prot;
+ wire [3:0] T_2710_io_slave_0_ar_bits_qos;
+ wire [3:0] T_2710_io_slave_0_ar_bits_region;
+ wire [4:0] T_2710_io_slave_0_ar_bits_id;
+ wire T_2710_io_slave_0_ar_bits_user;
+ wire T_2710_io_slave_0_r_ready;
+ wire T_2710_io_slave_0_r_valid;
+ wire [1:0] T_2710_io_slave_0_r_bits_resp;
+ wire [63:0] T_2710_io_slave_0_r_bits_data;
+ wire T_2710_io_slave_0_r_bits_last;
+ wire [4:0] T_2710_io_slave_0_r_bits_id;
+ wire T_2710_io_slave_0_r_bits_user;
+ wire T_2710_io_slave_1_aw_ready;
+ wire T_2710_io_slave_1_aw_valid;
+ wire [31:0] T_2710_io_slave_1_aw_bits_addr;
+ wire [7:0] T_2710_io_slave_1_aw_bits_len;
+ wire [2:0] T_2710_io_slave_1_aw_bits_size;
+ wire [1:0] T_2710_io_slave_1_aw_bits_burst;
+ wire T_2710_io_slave_1_aw_bits_lock;
+ wire [3:0] T_2710_io_slave_1_aw_bits_cache;
+ wire [2:0] T_2710_io_slave_1_aw_bits_prot;
+ wire [3:0] T_2710_io_slave_1_aw_bits_qos;
+ wire [3:0] T_2710_io_slave_1_aw_bits_region;
+ wire [4:0] T_2710_io_slave_1_aw_bits_id;
+ wire T_2710_io_slave_1_aw_bits_user;
+ wire T_2710_io_slave_1_w_ready;
+ wire T_2710_io_slave_1_w_valid;
+ wire [63:0] T_2710_io_slave_1_w_bits_data;
+ wire T_2710_io_slave_1_w_bits_last;
+ wire [7:0] T_2710_io_slave_1_w_bits_strb;
+ wire T_2710_io_slave_1_w_bits_user;
+ wire T_2710_io_slave_1_b_ready;
+ wire T_2710_io_slave_1_b_valid;
+ wire [1:0] T_2710_io_slave_1_b_bits_resp;
+ wire [4:0] T_2710_io_slave_1_b_bits_id;
+ wire T_2710_io_slave_1_b_bits_user;
+ wire T_2710_io_slave_1_ar_ready;
+ wire T_2710_io_slave_1_ar_valid;
+ wire [31:0] T_2710_io_slave_1_ar_bits_addr;
+ wire [7:0] T_2710_io_slave_1_ar_bits_len;
+ wire [2:0] T_2710_io_slave_1_ar_bits_size;
+ wire [1:0] T_2710_io_slave_1_ar_bits_burst;
+ wire T_2710_io_slave_1_ar_bits_lock;
+ wire [3:0] T_2710_io_slave_1_ar_bits_cache;
+ wire [2:0] T_2710_io_slave_1_ar_bits_prot;
+ wire [3:0] T_2710_io_slave_1_ar_bits_qos;
+ wire [3:0] T_2710_io_slave_1_ar_bits_region;
+ wire [4:0] T_2710_io_slave_1_ar_bits_id;
+ wire T_2710_io_slave_1_ar_bits_user;
+ wire T_2710_io_slave_1_r_ready;
+ wire T_2710_io_slave_1_r_valid;
+ wire [1:0] T_2710_io_slave_1_r_bits_resp;
+ wire [63:0] T_2710_io_slave_1_r_bits_data;
+ wire T_2710_io_slave_1_r_bits_last;
+ wire [4:0] T_2710_io_slave_1_r_bits_id;
+ wire T_2710_io_slave_1_r_bits_user;
+ wire T_2710_io_slave_2_aw_ready;
+ wire T_2710_io_slave_2_aw_valid;
+ wire [31:0] T_2710_io_slave_2_aw_bits_addr;
+ wire [7:0] T_2710_io_slave_2_aw_bits_len;
+ wire [2:0] T_2710_io_slave_2_aw_bits_size;
+ wire [1:0] T_2710_io_slave_2_aw_bits_burst;
+ wire T_2710_io_slave_2_aw_bits_lock;
+ wire [3:0] T_2710_io_slave_2_aw_bits_cache;
+ wire [2:0] T_2710_io_slave_2_aw_bits_prot;
+ wire [3:0] T_2710_io_slave_2_aw_bits_qos;
+ wire [3:0] T_2710_io_slave_2_aw_bits_region;
+ wire [4:0] T_2710_io_slave_2_aw_bits_id;
+ wire T_2710_io_slave_2_aw_bits_user;
+ wire T_2710_io_slave_2_w_ready;
+ wire T_2710_io_slave_2_w_valid;
+ wire [63:0] T_2710_io_slave_2_w_bits_data;
+ wire T_2710_io_slave_2_w_bits_last;
+ wire [7:0] T_2710_io_slave_2_w_bits_strb;
+ wire T_2710_io_slave_2_w_bits_user;
+ wire T_2710_io_slave_2_b_ready;
+ wire T_2710_io_slave_2_b_valid;
+ wire [1:0] T_2710_io_slave_2_b_bits_resp;
+ wire [4:0] T_2710_io_slave_2_b_bits_id;
+ wire T_2710_io_slave_2_b_bits_user;
+ wire T_2710_io_slave_2_ar_ready;
+ wire T_2710_io_slave_2_ar_valid;
+ wire [31:0] T_2710_io_slave_2_ar_bits_addr;
+ wire [7:0] T_2710_io_slave_2_ar_bits_len;
+ wire [2:0] T_2710_io_slave_2_ar_bits_size;
+ wire [1:0] T_2710_io_slave_2_ar_bits_burst;
+ wire T_2710_io_slave_2_ar_bits_lock;
+ wire [3:0] T_2710_io_slave_2_ar_bits_cache;
+ wire [2:0] T_2710_io_slave_2_ar_bits_prot;
+ wire [3:0] T_2710_io_slave_2_ar_bits_qos;
+ wire [3:0] T_2710_io_slave_2_ar_bits_region;
+ wire [4:0] T_2710_io_slave_2_ar_bits_id;
+ wire T_2710_io_slave_2_ar_bits_user;
+ wire T_2710_io_slave_2_r_ready;
+ wire T_2710_io_slave_2_r_valid;
+ wire [1:0] T_2710_io_slave_2_r_bits_resp;
+ wire [63:0] T_2710_io_slave_2_r_bits_data;
+ wire T_2710_io_slave_2_r_bits_last;
+ wire [4:0] T_2710_io_slave_2_r_bits_id;
+ wire T_2710_io_slave_2_r_bits_user;
+ wire T_2710_io_slave_3_aw_ready;
+ wire T_2710_io_slave_3_aw_valid;
+ wire [31:0] T_2710_io_slave_3_aw_bits_addr;
+ wire [7:0] T_2710_io_slave_3_aw_bits_len;
+ wire [2:0] T_2710_io_slave_3_aw_bits_size;
+ wire [1:0] T_2710_io_slave_3_aw_bits_burst;
+ wire T_2710_io_slave_3_aw_bits_lock;
+ wire [3:0] T_2710_io_slave_3_aw_bits_cache;
+ wire [2:0] T_2710_io_slave_3_aw_bits_prot;
+ wire [3:0] T_2710_io_slave_3_aw_bits_qos;
+ wire [3:0] T_2710_io_slave_3_aw_bits_region;
+ wire [4:0] T_2710_io_slave_3_aw_bits_id;
+ wire T_2710_io_slave_3_aw_bits_user;
+ wire T_2710_io_slave_3_w_ready;
+ wire T_2710_io_slave_3_w_valid;
+ wire [63:0] T_2710_io_slave_3_w_bits_data;
+ wire T_2710_io_slave_3_w_bits_last;
+ wire [7:0] T_2710_io_slave_3_w_bits_strb;
+ wire T_2710_io_slave_3_w_bits_user;
+ wire T_2710_io_slave_3_b_ready;
+ wire T_2710_io_slave_3_b_valid;
+ wire [1:0] T_2710_io_slave_3_b_bits_resp;
+ wire [4:0] T_2710_io_slave_3_b_bits_id;
+ wire T_2710_io_slave_3_b_bits_user;
+ wire T_2710_io_slave_3_ar_ready;
+ wire T_2710_io_slave_3_ar_valid;
+ wire [31:0] T_2710_io_slave_3_ar_bits_addr;
+ wire [7:0] T_2710_io_slave_3_ar_bits_len;
+ wire [2:0] T_2710_io_slave_3_ar_bits_size;
+ wire [1:0] T_2710_io_slave_3_ar_bits_burst;
+ wire T_2710_io_slave_3_ar_bits_lock;
+ wire [3:0] T_2710_io_slave_3_ar_bits_cache;
+ wire [2:0] T_2710_io_slave_3_ar_bits_prot;
+ wire [3:0] T_2710_io_slave_3_ar_bits_qos;
+ wire [3:0] T_2710_io_slave_3_ar_bits_region;
+ wire [4:0] T_2710_io_slave_3_ar_bits_id;
+ wire T_2710_io_slave_3_ar_bits_user;
+ wire T_2710_io_slave_3_r_ready;
+ wire T_2710_io_slave_3_r_valid;
+ wire [1:0] T_2710_io_slave_3_r_bits_resp;
+ wire [63:0] T_2710_io_slave_3_r_bits_data;
+ wire T_2710_io_slave_3_r_bits_last;
+ wire [4:0] T_2710_io_slave_3_r_bits_id;
+ wire T_2710_io_slave_3_r_bits_user;
+ wire T_2711_clk;
+ wire T_2711_reset;
+ wire T_2711_io_master_aw_ready;
+ wire T_2711_io_master_aw_valid;
+ wire [31:0] T_2711_io_master_aw_bits_addr;
+ wire [7:0] T_2711_io_master_aw_bits_len;
+ wire [2:0] T_2711_io_master_aw_bits_size;
+ wire [1:0] T_2711_io_master_aw_bits_burst;
+ wire T_2711_io_master_aw_bits_lock;
+ wire [3:0] T_2711_io_master_aw_bits_cache;
+ wire [2:0] T_2711_io_master_aw_bits_prot;
+ wire [3:0] T_2711_io_master_aw_bits_qos;
+ wire [3:0] T_2711_io_master_aw_bits_region;
+ wire [4:0] T_2711_io_master_aw_bits_id;
+ wire T_2711_io_master_aw_bits_user;
+ wire T_2711_io_master_w_ready;
+ wire T_2711_io_master_w_valid;
+ wire [63:0] T_2711_io_master_w_bits_data;
+ wire T_2711_io_master_w_bits_last;
+ wire [7:0] T_2711_io_master_w_bits_strb;
+ wire T_2711_io_master_w_bits_user;
+ wire T_2711_io_master_b_ready;
+ wire T_2711_io_master_b_valid;
+ wire [1:0] T_2711_io_master_b_bits_resp;
+ wire [4:0] T_2711_io_master_b_bits_id;
+ wire T_2711_io_master_b_bits_user;
+ wire T_2711_io_master_ar_ready;
+ wire T_2711_io_master_ar_valid;
+ wire [31:0] T_2711_io_master_ar_bits_addr;
+ wire [7:0] T_2711_io_master_ar_bits_len;
+ wire [2:0] T_2711_io_master_ar_bits_size;
+ wire [1:0] T_2711_io_master_ar_bits_burst;
+ wire T_2711_io_master_ar_bits_lock;
+ wire [3:0] T_2711_io_master_ar_bits_cache;
+ wire [2:0] T_2711_io_master_ar_bits_prot;
+ wire [3:0] T_2711_io_master_ar_bits_qos;
+ wire [3:0] T_2711_io_master_ar_bits_region;
+ wire [4:0] T_2711_io_master_ar_bits_id;
+ wire T_2711_io_master_ar_bits_user;
+ wire T_2711_io_master_r_ready;
+ wire T_2711_io_master_r_valid;
+ wire [1:0] T_2711_io_master_r_bits_resp;
+ wire [63:0] T_2711_io_master_r_bits_data;
+ wire T_2711_io_master_r_bits_last;
+ wire [4:0] T_2711_io_master_r_bits_id;
+ wire T_2711_io_master_r_bits_user;
+ wire T_2711_io_slave_0_aw_ready;
+ wire T_2711_io_slave_0_aw_valid;
+ wire [31:0] T_2711_io_slave_0_aw_bits_addr;
+ wire [7:0] T_2711_io_slave_0_aw_bits_len;
+ wire [2:0] T_2711_io_slave_0_aw_bits_size;
+ wire [1:0] T_2711_io_slave_0_aw_bits_burst;
+ wire T_2711_io_slave_0_aw_bits_lock;
+ wire [3:0] T_2711_io_slave_0_aw_bits_cache;
+ wire [2:0] T_2711_io_slave_0_aw_bits_prot;
+ wire [3:0] T_2711_io_slave_0_aw_bits_qos;
+ wire [3:0] T_2711_io_slave_0_aw_bits_region;
+ wire [4:0] T_2711_io_slave_0_aw_bits_id;
+ wire T_2711_io_slave_0_aw_bits_user;
+ wire T_2711_io_slave_0_w_ready;
+ wire T_2711_io_slave_0_w_valid;
+ wire [63:0] T_2711_io_slave_0_w_bits_data;
+ wire T_2711_io_slave_0_w_bits_last;
+ wire [7:0] T_2711_io_slave_0_w_bits_strb;
+ wire T_2711_io_slave_0_w_bits_user;
+ wire T_2711_io_slave_0_b_ready;
+ wire T_2711_io_slave_0_b_valid;
+ wire [1:0] T_2711_io_slave_0_b_bits_resp;
+ wire [4:0] T_2711_io_slave_0_b_bits_id;
+ wire T_2711_io_slave_0_b_bits_user;
+ wire T_2711_io_slave_0_ar_ready;
+ wire T_2711_io_slave_0_ar_valid;
+ wire [31:0] T_2711_io_slave_0_ar_bits_addr;
+ wire [7:0] T_2711_io_slave_0_ar_bits_len;
+ wire [2:0] T_2711_io_slave_0_ar_bits_size;
+ wire [1:0] T_2711_io_slave_0_ar_bits_burst;
+ wire T_2711_io_slave_0_ar_bits_lock;
+ wire [3:0] T_2711_io_slave_0_ar_bits_cache;
+ wire [2:0] T_2711_io_slave_0_ar_bits_prot;
+ wire [3:0] T_2711_io_slave_0_ar_bits_qos;
+ wire [3:0] T_2711_io_slave_0_ar_bits_region;
+ wire [4:0] T_2711_io_slave_0_ar_bits_id;
+ wire T_2711_io_slave_0_ar_bits_user;
+ wire T_2711_io_slave_0_r_ready;
+ wire T_2711_io_slave_0_r_valid;
+ wire [1:0] T_2711_io_slave_0_r_bits_resp;
+ wire [63:0] T_2711_io_slave_0_r_bits_data;
+ wire T_2711_io_slave_0_r_bits_last;
+ wire [4:0] T_2711_io_slave_0_r_bits_id;
+ wire T_2711_io_slave_0_r_bits_user;
+ wire T_2711_io_slave_1_aw_ready;
+ wire T_2711_io_slave_1_aw_valid;
+ wire [31:0] T_2711_io_slave_1_aw_bits_addr;
+ wire [7:0] T_2711_io_slave_1_aw_bits_len;
+ wire [2:0] T_2711_io_slave_1_aw_bits_size;
+ wire [1:0] T_2711_io_slave_1_aw_bits_burst;
+ wire T_2711_io_slave_1_aw_bits_lock;
+ wire [3:0] T_2711_io_slave_1_aw_bits_cache;
+ wire [2:0] T_2711_io_slave_1_aw_bits_prot;
+ wire [3:0] T_2711_io_slave_1_aw_bits_qos;
+ wire [3:0] T_2711_io_slave_1_aw_bits_region;
+ wire [4:0] T_2711_io_slave_1_aw_bits_id;
+ wire T_2711_io_slave_1_aw_bits_user;
+ wire T_2711_io_slave_1_w_ready;
+ wire T_2711_io_slave_1_w_valid;
+ wire [63:0] T_2711_io_slave_1_w_bits_data;
+ wire T_2711_io_slave_1_w_bits_last;
+ wire [7:0] T_2711_io_slave_1_w_bits_strb;
+ wire T_2711_io_slave_1_w_bits_user;
+ wire T_2711_io_slave_1_b_ready;
+ wire T_2711_io_slave_1_b_valid;
+ wire [1:0] T_2711_io_slave_1_b_bits_resp;
+ wire [4:0] T_2711_io_slave_1_b_bits_id;
+ wire T_2711_io_slave_1_b_bits_user;
+ wire T_2711_io_slave_1_ar_ready;
+ wire T_2711_io_slave_1_ar_valid;
+ wire [31:0] T_2711_io_slave_1_ar_bits_addr;
+ wire [7:0] T_2711_io_slave_1_ar_bits_len;
+ wire [2:0] T_2711_io_slave_1_ar_bits_size;
+ wire [1:0] T_2711_io_slave_1_ar_bits_burst;
+ wire T_2711_io_slave_1_ar_bits_lock;
+ wire [3:0] T_2711_io_slave_1_ar_bits_cache;
+ wire [2:0] T_2711_io_slave_1_ar_bits_prot;
+ wire [3:0] T_2711_io_slave_1_ar_bits_qos;
+ wire [3:0] T_2711_io_slave_1_ar_bits_region;
+ wire [4:0] T_2711_io_slave_1_ar_bits_id;
+ wire T_2711_io_slave_1_ar_bits_user;
+ wire T_2711_io_slave_1_r_ready;
+ wire T_2711_io_slave_1_r_valid;
+ wire [1:0] T_2711_io_slave_1_r_bits_resp;
+ wire [63:0] T_2711_io_slave_1_r_bits_data;
+ wire T_2711_io_slave_1_r_bits_last;
+ wire [4:0] T_2711_io_slave_1_r_bits_id;
+ wire T_2711_io_slave_1_r_bits_user;
+ wire T_2711_io_slave_2_aw_ready;
+ wire T_2711_io_slave_2_aw_valid;
+ wire [31:0] T_2711_io_slave_2_aw_bits_addr;
+ wire [7:0] T_2711_io_slave_2_aw_bits_len;
+ wire [2:0] T_2711_io_slave_2_aw_bits_size;
+ wire [1:0] T_2711_io_slave_2_aw_bits_burst;
+ wire T_2711_io_slave_2_aw_bits_lock;
+ wire [3:0] T_2711_io_slave_2_aw_bits_cache;
+ wire [2:0] T_2711_io_slave_2_aw_bits_prot;
+ wire [3:0] T_2711_io_slave_2_aw_bits_qos;
+ wire [3:0] T_2711_io_slave_2_aw_bits_region;
+ wire [4:0] T_2711_io_slave_2_aw_bits_id;
+ wire T_2711_io_slave_2_aw_bits_user;
+ wire T_2711_io_slave_2_w_ready;
+ wire T_2711_io_slave_2_w_valid;
+ wire [63:0] T_2711_io_slave_2_w_bits_data;
+ wire T_2711_io_slave_2_w_bits_last;
+ wire [7:0] T_2711_io_slave_2_w_bits_strb;
+ wire T_2711_io_slave_2_w_bits_user;
+ wire T_2711_io_slave_2_b_ready;
+ wire T_2711_io_slave_2_b_valid;
+ wire [1:0] T_2711_io_slave_2_b_bits_resp;
+ wire [4:0] T_2711_io_slave_2_b_bits_id;
+ wire T_2711_io_slave_2_b_bits_user;
+ wire T_2711_io_slave_2_ar_ready;
+ wire T_2711_io_slave_2_ar_valid;
+ wire [31:0] T_2711_io_slave_2_ar_bits_addr;
+ wire [7:0] T_2711_io_slave_2_ar_bits_len;
+ wire [2:0] T_2711_io_slave_2_ar_bits_size;
+ wire [1:0] T_2711_io_slave_2_ar_bits_burst;
+ wire T_2711_io_slave_2_ar_bits_lock;
+ wire [3:0] T_2711_io_slave_2_ar_bits_cache;
+ wire [2:0] T_2711_io_slave_2_ar_bits_prot;
+ wire [3:0] T_2711_io_slave_2_ar_bits_qos;
+ wire [3:0] T_2711_io_slave_2_ar_bits_region;
+ wire [4:0] T_2711_io_slave_2_ar_bits_id;
+ wire T_2711_io_slave_2_ar_bits_user;
+ wire T_2711_io_slave_2_r_ready;
+ wire T_2711_io_slave_2_r_valid;
+ wire [1:0] T_2711_io_slave_2_r_bits_resp;
+ wire [63:0] T_2711_io_slave_2_r_bits_data;
+ wire T_2711_io_slave_2_r_bits_last;
+ wire [4:0] T_2711_io_slave_2_r_bits_id;
+ wire T_2711_io_slave_2_r_bits_user;
+ wire T_2711_io_slave_3_aw_ready;
+ wire T_2711_io_slave_3_aw_valid;
+ wire [31:0] T_2711_io_slave_3_aw_bits_addr;
+ wire [7:0] T_2711_io_slave_3_aw_bits_len;
+ wire [2:0] T_2711_io_slave_3_aw_bits_size;
+ wire [1:0] T_2711_io_slave_3_aw_bits_burst;
+ wire T_2711_io_slave_3_aw_bits_lock;
+ wire [3:0] T_2711_io_slave_3_aw_bits_cache;
+ wire [2:0] T_2711_io_slave_3_aw_bits_prot;
+ wire [3:0] T_2711_io_slave_3_aw_bits_qos;
+ wire [3:0] T_2711_io_slave_3_aw_bits_region;
+ wire [4:0] T_2711_io_slave_3_aw_bits_id;
+ wire T_2711_io_slave_3_aw_bits_user;
+ wire T_2711_io_slave_3_w_ready;
+ wire T_2711_io_slave_3_w_valid;
+ wire [63:0] T_2711_io_slave_3_w_bits_data;
+ wire T_2711_io_slave_3_w_bits_last;
+ wire [7:0] T_2711_io_slave_3_w_bits_strb;
+ wire T_2711_io_slave_3_w_bits_user;
+ wire T_2711_io_slave_3_b_ready;
+ wire T_2711_io_slave_3_b_valid;
+ wire [1:0] T_2711_io_slave_3_b_bits_resp;
+ wire [4:0] T_2711_io_slave_3_b_bits_id;
+ wire T_2711_io_slave_3_b_bits_user;
+ wire T_2711_io_slave_3_ar_ready;
+ wire T_2711_io_slave_3_ar_valid;
+ wire [31:0] T_2711_io_slave_3_ar_bits_addr;
+ wire [7:0] T_2711_io_slave_3_ar_bits_len;
+ wire [2:0] T_2711_io_slave_3_ar_bits_size;
+ wire [1:0] T_2711_io_slave_3_ar_bits_burst;
+ wire T_2711_io_slave_3_ar_bits_lock;
+ wire [3:0] T_2711_io_slave_3_ar_bits_cache;
+ wire [2:0] T_2711_io_slave_3_ar_bits_prot;
+ wire [3:0] T_2711_io_slave_3_ar_bits_qos;
+ wire [3:0] T_2711_io_slave_3_ar_bits_region;
+ wire [4:0] T_2711_io_slave_3_ar_bits_id;
+ wire T_2711_io_slave_3_ar_bits_user;
+ wire T_2711_io_slave_3_r_ready;
+ wire T_2711_io_slave_3_r_valid;
+ wire [1:0] T_2711_io_slave_3_r_bits_resp;
+ wire [63:0] T_2711_io_slave_3_r_bits_data;
+ wire T_2711_io_slave_3_r_bits_last;
+ wire [4:0] T_2711_io_slave_3_r_bits_id;
+ wire T_2711_io_slave_3_r_bits_user;
+ wire T_4146_0_master_aw_ready;
+ wire T_4146_0_master_aw_valid;
+ wire [31:0] T_4146_0_master_aw_bits_addr;
+ wire [7:0] T_4146_0_master_aw_bits_len;
+ wire [2:0] T_4146_0_master_aw_bits_size;
+ wire [1:0] T_4146_0_master_aw_bits_burst;
+ wire T_4146_0_master_aw_bits_lock;
+ wire [3:0] T_4146_0_master_aw_bits_cache;
+ wire [2:0] T_4146_0_master_aw_bits_prot;
+ wire [3:0] T_4146_0_master_aw_bits_qos;
+ wire [3:0] T_4146_0_master_aw_bits_region;
+ wire [4:0] T_4146_0_master_aw_bits_id;
+ wire T_4146_0_master_aw_bits_user;
+ wire T_4146_0_master_w_ready;
+ wire T_4146_0_master_w_valid;
+ wire [63:0] T_4146_0_master_w_bits_data;
+ wire T_4146_0_master_w_bits_last;
+ wire [7:0] T_4146_0_master_w_bits_strb;
+ wire T_4146_0_master_w_bits_user;
+ wire T_4146_0_master_b_ready;
+ wire T_4146_0_master_b_valid;
+ wire [1:0] T_4146_0_master_b_bits_resp;
+ wire [4:0] T_4146_0_master_b_bits_id;
+ wire T_4146_0_master_b_bits_user;
+ wire T_4146_0_master_ar_ready;
+ wire T_4146_0_master_ar_valid;
+ wire [31:0] T_4146_0_master_ar_bits_addr;
+ wire [7:0] T_4146_0_master_ar_bits_len;
+ wire [2:0] T_4146_0_master_ar_bits_size;
+ wire [1:0] T_4146_0_master_ar_bits_burst;
+ wire T_4146_0_master_ar_bits_lock;
+ wire [3:0] T_4146_0_master_ar_bits_cache;
+ wire [2:0] T_4146_0_master_ar_bits_prot;
+ wire [3:0] T_4146_0_master_ar_bits_qos;
+ wire [3:0] T_4146_0_master_ar_bits_region;
+ wire [4:0] T_4146_0_master_ar_bits_id;
+ wire T_4146_0_master_ar_bits_user;
+ wire T_4146_0_master_r_ready;
+ wire T_4146_0_master_r_valid;
+ wire [1:0] T_4146_0_master_r_bits_resp;
+ wire [63:0] T_4146_0_master_r_bits_data;
+ wire T_4146_0_master_r_bits_last;
+ wire [4:0] T_4146_0_master_r_bits_id;
+ wire T_4146_0_master_r_bits_user;
+ wire T_4146_0_slave_0_aw_ready;
+ wire T_4146_0_slave_0_aw_valid;
+ wire [31:0] T_4146_0_slave_0_aw_bits_addr;
+ wire [7:0] T_4146_0_slave_0_aw_bits_len;
+ wire [2:0] T_4146_0_slave_0_aw_bits_size;
+ wire [1:0] T_4146_0_slave_0_aw_bits_burst;
+ wire T_4146_0_slave_0_aw_bits_lock;
+ wire [3:0] T_4146_0_slave_0_aw_bits_cache;
+ wire [2:0] T_4146_0_slave_0_aw_bits_prot;
+ wire [3:0] T_4146_0_slave_0_aw_bits_qos;
+ wire [3:0] T_4146_0_slave_0_aw_bits_region;
+ wire [4:0] T_4146_0_slave_0_aw_bits_id;
+ wire T_4146_0_slave_0_aw_bits_user;
+ wire T_4146_0_slave_0_w_ready;
+ wire T_4146_0_slave_0_w_valid;
+ wire [63:0] T_4146_0_slave_0_w_bits_data;
+ wire T_4146_0_slave_0_w_bits_last;
+ wire [7:0] T_4146_0_slave_0_w_bits_strb;
+ wire T_4146_0_slave_0_w_bits_user;
+ wire T_4146_0_slave_0_b_ready;
+ wire T_4146_0_slave_0_b_valid;
+ wire [1:0] T_4146_0_slave_0_b_bits_resp;
+ wire [4:0] T_4146_0_slave_0_b_bits_id;
+ wire T_4146_0_slave_0_b_bits_user;
+ wire T_4146_0_slave_0_ar_ready;
+ wire T_4146_0_slave_0_ar_valid;
+ wire [31:0] T_4146_0_slave_0_ar_bits_addr;
+ wire [7:0] T_4146_0_slave_0_ar_bits_len;
+ wire [2:0] T_4146_0_slave_0_ar_bits_size;
+ wire [1:0] T_4146_0_slave_0_ar_bits_burst;
+ wire T_4146_0_slave_0_ar_bits_lock;
+ wire [3:0] T_4146_0_slave_0_ar_bits_cache;
+ wire [2:0] T_4146_0_slave_0_ar_bits_prot;
+ wire [3:0] T_4146_0_slave_0_ar_bits_qos;
+ wire [3:0] T_4146_0_slave_0_ar_bits_region;
+ wire [4:0] T_4146_0_slave_0_ar_bits_id;
+ wire T_4146_0_slave_0_ar_bits_user;
+ wire T_4146_0_slave_0_r_ready;
+ wire T_4146_0_slave_0_r_valid;
+ wire [1:0] T_4146_0_slave_0_r_bits_resp;
+ wire [63:0] T_4146_0_slave_0_r_bits_data;
+ wire T_4146_0_slave_0_r_bits_last;
+ wire [4:0] T_4146_0_slave_0_r_bits_id;
+ wire T_4146_0_slave_0_r_bits_user;
+ wire T_4146_0_slave_1_aw_ready;
+ wire T_4146_0_slave_1_aw_valid;
+ wire [31:0] T_4146_0_slave_1_aw_bits_addr;
+ wire [7:0] T_4146_0_slave_1_aw_bits_len;
+ wire [2:0] T_4146_0_slave_1_aw_bits_size;
+ wire [1:0] T_4146_0_slave_1_aw_bits_burst;
+ wire T_4146_0_slave_1_aw_bits_lock;
+ wire [3:0] T_4146_0_slave_1_aw_bits_cache;
+ wire [2:0] T_4146_0_slave_1_aw_bits_prot;
+ wire [3:0] T_4146_0_slave_1_aw_bits_qos;
+ wire [3:0] T_4146_0_slave_1_aw_bits_region;
+ wire [4:0] T_4146_0_slave_1_aw_bits_id;
+ wire T_4146_0_slave_1_aw_bits_user;
+ wire T_4146_0_slave_1_w_ready;
+ wire T_4146_0_slave_1_w_valid;
+ wire [63:0] T_4146_0_slave_1_w_bits_data;
+ wire T_4146_0_slave_1_w_bits_last;
+ wire [7:0] T_4146_0_slave_1_w_bits_strb;
+ wire T_4146_0_slave_1_w_bits_user;
+ wire T_4146_0_slave_1_b_ready;
+ wire T_4146_0_slave_1_b_valid;
+ wire [1:0] T_4146_0_slave_1_b_bits_resp;
+ wire [4:0] T_4146_0_slave_1_b_bits_id;
+ wire T_4146_0_slave_1_b_bits_user;
+ wire T_4146_0_slave_1_ar_ready;
+ wire T_4146_0_slave_1_ar_valid;
+ wire [31:0] T_4146_0_slave_1_ar_bits_addr;
+ wire [7:0] T_4146_0_slave_1_ar_bits_len;
+ wire [2:0] T_4146_0_slave_1_ar_bits_size;
+ wire [1:0] T_4146_0_slave_1_ar_bits_burst;
+ wire T_4146_0_slave_1_ar_bits_lock;
+ wire [3:0] T_4146_0_slave_1_ar_bits_cache;
+ wire [2:0] T_4146_0_slave_1_ar_bits_prot;
+ wire [3:0] T_4146_0_slave_1_ar_bits_qos;
+ wire [3:0] T_4146_0_slave_1_ar_bits_region;
+ wire [4:0] T_4146_0_slave_1_ar_bits_id;
+ wire T_4146_0_slave_1_ar_bits_user;
+ wire T_4146_0_slave_1_r_ready;
+ wire T_4146_0_slave_1_r_valid;
+ wire [1:0] T_4146_0_slave_1_r_bits_resp;
+ wire [63:0] T_4146_0_slave_1_r_bits_data;
+ wire T_4146_0_slave_1_r_bits_last;
+ wire [4:0] T_4146_0_slave_1_r_bits_id;
+ wire T_4146_0_slave_1_r_bits_user;
+ wire T_4146_0_slave_2_aw_ready;
+ wire T_4146_0_slave_2_aw_valid;
+ wire [31:0] T_4146_0_slave_2_aw_bits_addr;
+ wire [7:0] T_4146_0_slave_2_aw_bits_len;
+ wire [2:0] T_4146_0_slave_2_aw_bits_size;
+ wire [1:0] T_4146_0_slave_2_aw_bits_burst;
+ wire T_4146_0_slave_2_aw_bits_lock;
+ wire [3:0] T_4146_0_slave_2_aw_bits_cache;
+ wire [2:0] T_4146_0_slave_2_aw_bits_prot;
+ wire [3:0] T_4146_0_slave_2_aw_bits_qos;
+ wire [3:0] T_4146_0_slave_2_aw_bits_region;
+ wire [4:0] T_4146_0_slave_2_aw_bits_id;
+ wire T_4146_0_slave_2_aw_bits_user;
+ wire T_4146_0_slave_2_w_ready;
+ wire T_4146_0_slave_2_w_valid;
+ wire [63:0] T_4146_0_slave_2_w_bits_data;
+ wire T_4146_0_slave_2_w_bits_last;
+ wire [7:0] T_4146_0_slave_2_w_bits_strb;
+ wire T_4146_0_slave_2_w_bits_user;
+ wire T_4146_0_slave_2_b_ready;
+ wire T_4146_0_slave_2_b_valid;
+ wire [1:0] T_4146_0_slave_2_b_bits_resp;
+ wire [4:0] T_4146_0_slave_2_b_bits_id;
+ wire T_4146_0_slave_2_b_bits_user;
+ wire T_4146_0_slave_2_ar_ready;
+ wire T_4146_0_slave_2_ar_valid;
+ wire [31:0] T_4146_0_slave_2_ar_bits_addr;
+ wire [7:0] T_4146_0_slave_2_ar_bits_len;
+ wire [2:0] T_4146_0_slave_2_ar_bits_size;
+ wire [1:0] T_4146_0_slave_2_ar_bits_burst;
+ wire T_4146_0_slave_2_ar_bits_lock;
+ wire [3:0] T_4146_0_slave_2_ar_bits_cache;
+ wire [2:0] T_4146_0_slave_2_ar_bits_prot;
+ wire [3:0] T_4146_0_slave_2_ar_bits_qos;
+ wire [3:0] T_4146_0_slave_2_ar_bits_region;
+ wire [4:0] T_4146_0_slave_2_ar_bits_id;
+ wire T_4146_0_slave_2_ar_bits_user;
+ wire T_4146_0_slave_2_r_ready;
+ wire T_4146_0_slave_2_r_valid;
+ wire [1:0] T_4146_0_slave_2_r_bits_resp;
+ wire [63:0] T_4146_0_slave_2_r_bits_data;
+ wire T_4146_0_slave_2_r_bits_last;
+ wire [4:0] T_4146_0_slave_2_r_bits_id;
+ wire T_4146_0_slave_2_r_bits_user;
+ wire T_4146_0_slave_3_aw_ready;
+ wire T_4146_0_slave_3_aw_valid;
+ wire [31:0] T_4146_0_slave_3_aw_bits_addr;
+ wire [7:0] T_4146_0_slave_3_aw_bits_len;
+ wire [2:0] T_4146_0_slave_3_aw_bits_size;
+ wire [1:0] T_4146_0_slave_3_aw_bits_burst;
+ wire T_4146_0_slave_3_aw_bits_lock;
+ wire [3:0] T_4146_0_slave_3_aw_bits_cache;
+ wire [2:0] T_4146_0_slave_3_aw_bits_prot;
+ wire [3:0] T_4146_0_slave_3_aw_bits_qos;
+ wire [3:0] T_4146_0_slave_3_aw_bits_region;
+ wire [4:0] T_4146_0_slave_3_aw_bits_id;
+ wire T_4146_0_slave_3_aw_bits_user;
+ wire T_4146_0_slave_3_w_ready;
+ wire T_4146_0_slave_3_w_valid;
+ wire [63:0] T_4146_0_slave_3_w_bits_data;
+ wire T_4146_0_slave_3_w_bits_last;
+ wire [7:0] T_4146_0_slave_3_w_bits_strb;
+ wire T_4146_0_slave_3_w_bits_user;
+ wire T_4146_0_slave_3_b_ready;
+ wire T_4146_0_slave_3_b_valid;
+ wire [1:0] T_4146_0_slave_3_b_bits_resp;
+ wire [4:0] T_4146_0_slave_3_b_bits_id;
+ wire T_4146_0_slave_3_b_bits_user;
+ wire T_4146_0_slave_3_ar_ready;
+ wire T_4146_0_slave_3_ar_valid;
+ wire [31:0] T_4146_0_slave_3_ar_bits_addr;
+ wire [7:0] T_4146_0_slave_3_ar_bits_len;
+ wire [2:0] T_4146_0_slave_3_ar_bits_size;
+ wire [1:0] T_4146_0_slave_3_ar_bits_burst;
+ wire T_4146_0_slave_3_ar_bits_lock;
+ wire [3:0] T_4146_0_slave_3_ar_bits_cache;
+ wire [2:0] T_4146_0_slave_3_ar_bits_prot;
+ wire [3:0] T_4146_0_slave_3_ar_bits_qos;
+ wire [3:0] T_4146_0_slave_3_ar_bits_region;
+ wire [4:0] T_4146_0_slave_3_ar_bits_id;
+ wire T_4146_0_slave_3_ar_bits_user;
+ wire T_4146_0_slave_3_r_ready;
+ wire T_4146_0_slave_3_r_valid;
+ wire [1:0] T_4146_0_slave_3_r_bits_resp;
+ wire [63:0] T_4146_0_slave_3_r_bits_data;
+ wire T_4146_0_slave_3_r_bits_last;
+ wire [4:0] T_4146_0_slave_3_r_bits_id;
+ wire T_4146_0_slave_3_r_bits_user;
+ wire T_4146_1_master_aw_ready;
+ wire T_4146_1_master_aw_valid;
+ wire [31:0] T_4146_1_master_aw_bits_addr;
+ wire [7:0] T_4146_1_master_aw_bits_len;
+ wire [2:0] T_4146_1_master_aw_bits_size;
+ wire [1:0] T_4146_1_master_aw_bits_burst;
+ wire T_4146_1_master_aw_bits_lock;
+ wire [3:0] T_4146_1_master_aw_bits_cache;
+ wire [2:0] T_4146_1_master_aw_bits_prot;
+ wire [3:0] T_4146_1_master_aw_bits_qos;
+ wire [3:0] T_4146_1_master_aw_bits_region;
+ wire [4:0] T_4146_1_master_aw_bits_id;
+ wire T_4146_1_master_aw_bits_user;
+ wire T_4146_1_master_w_ready;
+ wire T_4146_1_master_w_valid;
+ wire [63:0] T_4146_1_master_w_bits_data;
+ wire T_4146_1_master_w_bits_last;
+ wire [7:0] T_4146_1_master_w_bits_strb;
+ wire T_4146_1_master_w_bits_user;
+ wire T_4146_1_master_b_ready;
+ wire T_4146_1_master_b_valid;
+ wire [1:0] T_4146_1_master_b_bits_resp;
+ wire [4:0] T_4146_1_master_b_bits_id;
+ wire T_4146_1_master_b_bits_user;
+ wire T_4146_1_master_ar_ready;
+ wire T_4146_1_master_ar_valid;
+ wire [31:0] T_4146_1_master_ar_bits_addr;
+ wire [7:0] T_4146_1_master_ar_bits_len;
+ wire [2:0] T_4146_1_master_ar_bits_size;
+ wire [1:0] T_4146_1_master_ar_bits_burst;
+ wire T_4146_1_master_ar_bits_lock;
+ wire [3:0] T_4146_1_master_ar_bits_cache;
+ wire [2:0] T_4146_1_master_ar_bits_prot;
+ wire [3:0] T_4146_1_master_ar_bits_qos;
+ wire [3:0] T_4146_1_master_ar_bits_region;
+ wire [4:0] T_4146_1_master_ar_bits_id;
+ wire T_4146_1_master_ar_bits_user;
+ wire T_4146_1_master_r_ready;
+ wire T_4146_1_master_r_valid;
+ wire [1:0] T_4146_1_master_r_bits_resp;
+ wire [63:0] T_4146_1_master_r_bits_data;
+ wire T_4146_1_master_r_bits_last;
+ wire [4:0] T_4146_1_master_r_bits_id;
+ wire T_4146_1_master_r_bits_user;
+ wire T_4146_1_slave_0_aw_ready;
+ wire T_4146_1_slave_0_aw_valid;
+ wire [31:0] T_4146_1_slave_0_aw_bits_addr;
+ wire [7:0] T_4146_1_slave_0_aw_bits_len;
+ wire [2:0] T_4146_1_slave_0_aw_bits_size;
+ wire [1:0] T_4146_1_slave_0_aw_bits_burst;
+ wire T_4146_1_slave_0_aw_bits_lock;
+ wire [3:0] T_4146_1_slave_0_aw_bits_cache;
+ wire [2:0] T_4146_1_slave_0_aw_bits_prot;
+ wire [3:0] T_4146_1_slave_0_aw_bits_qos;
+ wire [3:0] T_4146_1_slave_0_aw_bits_region;
+ wire [4:0] T_4146_1_slave_0_aw_bits_id;
+ wire T_4146_1_slave_0_aw_bits_user;
+ wire T_4146_1_slave_0_w_ready;
+ wire T_4146_1_slave_0_w_valid;
+ wire [63:0] T_4146_1_slave_0_w_bits_data;
+ wire T_4146_1_slave_0_w_bits_last;
+ wire [7:0] T_4146_1_slave_0_w_bits_strb;
+ wire T_4146_1_slave_0_w_bits_user;
+ wire T_4146_1_slave_0_b_ready;
+ wire T_4146_1_slave_0_b_valid;
+ wire [1:0] T_4146_1_slave_0_b_bits_resp;
+ wire [4:0] T_4146_1_slave_0_b_bits_id;
+ wire T_4146_1_slave_0_b_bits_user;
+ wire T_4146_1_slave_0_ar_ready;
+ wire T_4146_1_slave_0_ar_valid;
+ wire [31:0] T_4146_1_slave_0_ar_bits_addr;
+ wire [7:0] T_4146_1_slave_0_ar_bits_len;
+ wire [2:0] T_4146_1_slave_0_ar_bits_size;
+ wire [1:0] T_4146_1_slave_0_ar_bits_burst;
+ wire T_4146_1_slave_0_ar_bits_lock;
+ wire [3:0] T_4146_1_slave_0_ar_bits_cache;
+ wire [2:0] T_4146_1_slave_0_ar_bits_prot;
+ wire [3:0] T_4146_1_slave_0_ar_bits_qos;
+ wire [3:0] T_4146_1_slave_0_ar_bits_region;
+ wire [4:0] T_4146_1_slave_0_ar_bits_id;
+ wire T_4146_1_slave_0_ar_bits_user;
+ wire T_4146_1_slave_0_r_ready;
+ wire T_4146_1_slave_0_r_valid;
+ wire [1:0] T_4146_1_slave_0_r_bits_resp;
+ wire [63:0] T_4146_1_slave_0_r_bits_data;
+ wire T_4146_1_slave_0_r_bits_last;
+ wire [4:0] T_4146_1_slave_0_r_bits_id;
+ wire T_4146_1_slave_0_r_bits_user;
+ wire T_4146_1_slave_1_aw_ready;
+ wire T_4146_1_slave_1_aw_valid;
+ wire [31:0] T_4146_1_slave_1_aw_bits_addr;
+ wire [7:0] T_4146_1_slave_1_aw_bits_len;
+ wire [2:0] T_4146_1_slave_1_aw_bits_size;
+ wire [1:0] T_4146_1_slave_1_aw_bits_burst;
+ wire T_4146_1_slave_1_aw_bits_lock;
+ wire [3:0] T_4146_1_slave_1_aw_bits_cache;
+ wire [2:0] T_4146_1_slave_1_aw_bits_prot;
+ wire [3:0] T_4146_1_slave_1_aw_bits_qos;
+ wire [3:0] T_4146_1_slave_1_aw_bits_region;
+ wire [4:0] T_4146_1_slave_1_aw_bits_id;
+ wire T_4146_1_slave_1_aw_bits_user;
+ wire T_4146_1_slave_1_w_ready;
+ wire T_4146_1_slave_1_w_valid;
+ wire [63:0] T_4146_1_slave_1_w_bits_data;
+ wire T_4146_1_slave_1_w_bits_last;
+ wire [7:0] T_4146_1_slave_1_w_bits_strb;
+ wire T_4146_1_slave_1_w_bits_user;
+ wire T_4146_1_slave_1_b_ready;
+ wire T_4146_1_slave_1_b_valid;
+ wire [1:0] T_4146_1_slave_1_b_bits_resp;
+ wire [4:0] T_4146_1_slave_1_b_bits_id;
+ wire T_4146_1_slave_1_b_bits_user;
+ wire T_4146_1_slave_1_ar_ready;
+ wire T_4146_1_slave_1_ar_valid;
+ wire [31:0] T_4146_1_slave_1_ar_bits_addr;
+ wire [7:0] T_4146_1_slave_1_ar_bits_len;
+ wire [2:0] T_4146_1_slave_1_ar_bits_size;
+ wire [1:0] T_4146_1_slave_1_ar_bits_burst;
+ wire T_4146_1_slave_1_ar_bits_lock;
+ wire [3:0] T_4146_1_slave_1_ar_bits_cache;
+ wire [2:0] T_4146_1_slave_1_ar_bits_prot;
+ wire [3:0] T_4146_1_slave_1_ar_bits_qos;
+ wire [3:0] T_4146_1_slave_1_ar_bits_region;
+ wire [4:0] T_4146_1_slave_1_ar_bits_id;
+ wire T_4146_1_slave_1_ar_bits_user;
+ wire T_4146_1_slave_1_r_ready;
+ wire T_4146_1_slave_1_r_valid;
+ wire [1:0] T_4146_1_slave_1_r_bits_resp;
+ wire [63:0] T_4146_1_slave_1_r_bits_data;
+ wire T_4146_1_slave_1_r_bits_last;
+ wire [4:0] T_4146_1_slave_1_r_bits_id;
+ wire T_4146_1_slave_1_r_bits_user;
+ wire T_4146_1_slave_2_aw_ready;
+ wire T_4146_1_slave_2_aw_valid;
+ wire [31:0] T_4146_1_slave_2_aw_bits_addr;
+ wire [7:0] T_4146_1_slave_2_aw_bits_len;
+ wire [2:0] T_4146_1_slave_2_aw_bits_size;
+ wire [1:0] T_4146_1_slave_2_aw_bits_burst;
+ wire T_4146_1_slave_2_aw_bits_lock;
+ wire [3:0] T_4146_1_slave_2_aw_bits_cache;
+ wire [2:0] T_4146_1_slave_2_aw_bits_prot;
+ wire [3:0] T_4146_1_slave_2_aw_bits_qos;
+ wire [3:0] T_4146_1_slave_2_aw_bits_region;
+ wire [4:0] T_4146_1_slave_2_aw_bits_id;
+ wire T_4146_1_slave_2_aw_bits_user;
+ wire T_4146_1_slave_2_w_ready;
+ wire T_4146_1_slave_2_w_valid;
+ wire [63:0] T_4146_1_slave_2_w_bits_data;
+ wire T_4146_1_slave_2_w_bits_last;
+ wire [7:0] T_4146_1_slave_2_w_bits_strb;
+ wire T_4146_1_slave_2_w_bits_user;
+ wire T_4146_1_slave_2_b_ready;
+ wire T_4146_1_slave_2_b_valid;
+ wire [1:0] T_4146_1_slave_2_b_bits_resp;
+ wire [4:0] T_4146_1_slave_2_b_bits_id;
+ wire T_4146_1_slave_2_b_bits_user;
+ wire T_4146_1_slave_2_ar_ready;
+ wire T_4146_1_slave_2_ar_valid;
+ wire [31:0] T_4146_1_slave_2_ar_bits_addr;
+ wire [7:0] T_4146_1_slave_2_ar_bits_len;
+ wire [2:0] T_4146_1_slave_2_ar_bits_size;
+ wire [1:0] T_4146_1_slave_2_ar_bits_burst;
+ wire T_4146_1_slave_2_ar_bits_lock;
+ wire [3:0] T_4146_1_slave_2_ar_bits_cache;
+ wire [2:0] T_4146_1_slave_2_ar_bits_prot;
+ wire [3:0] T_4146_1_slave_2_ar_bits_qos;
+ wire [3:0] T_4146_1_slave_2_ar_bits_region;
+ wire [4:0] T_4146_1_slave_2_ar_bits_id;
+ wire T_4146_1_slave_2_ar_bits_user;
+ wire T_4146_1_slave_2_r_ready;
+ wire T_4146_1_slave_2_r_valid;
+ wire [1:0] T_4146_1_slave_2_r_bits_resp;
+ wire [63:0] T_4146_1_slave_2_r_bits_data;
+ wire T_4146_1_slave_2_r_bits_last;
+ wire [4:0] T_4146_1_slave_2_r_bits_id;
+ wire T_4146_1_slave_2_r_bits_user;
+ wire T_4146_1_slave_3_aw_ready;
+ wire T_4146_1_slave_3_aw_valid;
+ wire [31:0] T_4146_1_slave_3_aw_bits_addr;
+ wire [7:0] T_4146_1_slave_3_aw_bits_len;
+ wire [2:0] T_4146_1_slave_3_aw_bits_size;
+ wire [1:0] T_4146_1_slave_3_aw_bits_burst;
+ wire T_4146_1_slave_3_aw_bits_lock;
+ wire [3:0] T_4146_1_slave_3_aw_bits_cache;
+ wire [2:0] T_4146_1_slave_3_aw_bits_prot;
+ wire [3:0] T_4146_1_slave_3_aw_bits_qos;
+ wire [3:0] T_4146_1_slave_3_aw_bits_region;
+ wire [4:0] T_4146_1_slave_3_aw_bits_id;
+ wire T_4146_1_slave_3_aw_bits_user;
+ wire T_4146_1_slave_3_w_ready;
+ wire T_4146_1_slave_3_w_valid;
+ wire [63:0] T_4146_1_slave_3_w_bits_data;
+ wire T_4146_1_slave_3_w_bits_last;
+ wire [7:0] T_4146_1_slave_3_w_bits_strb;
+ wire T_4146_1_slave_3_w_bits_user;
+ wire T_4146_1_slave_3_b_ready;
+ wire T_4146_1_slave_3_b_valid;
+ wire [1:0] T_4146_1_slave_3_b_bits_resp;
+ wire [4:0] T_4146_1_slave_3_b_bits_id;
+ wire T_4146_1_slave_3_b_bits_user;
+ wire T_4146_1_slave_3_ar_ready;
+ wire T_4146_1_slave_3_ar_valid;
+ wire [31:0] T_4146_1_slave_3_ar_bits_addr;
+ wire [7:0] T_4146_1_slave_3_ar_bits_len;
+ wire [2:0] T_4146_1_slave_3_ar_bits_size;
+ wire [1:0] T_4146_1_slave_3_ar_bits_burst;
+ wire T_4146_1_slave_3_ar_bits_lock;
+ wire [3:0] T_4146_1_slave_3_ar_bits_cache;
+ wire [2:0] T_4146_1_slave_3_ar_bits_prot;
+ wire [3:0] T_4146_1_slave_3_ar_bits_qos;
+ wire [3:0] T_4146_1_slave_3_ar_bits_region;
+ wire [4:0] T_4146_1_slave_3_ar_bits_id;
+ wire T_4146_1_slave_3_ar_bits_user;
+ wire T_4146_1_slave_3_r_ready;
+ wire T_4146_1_slave_3_r_valid;
+ wire [1:0] T_4146_1_slave_3_r_bits_resp;
+ wire [63:0] T_4146_1_slave_3_r_bits_data;
+ wire T_4146_1_slave_3_r_bits_last;
+ wire [4:0] T_4146_1_slave_3_r_bits_id;
+ wire T_4146_1_slave_3_r_bits_user;
+ wire T_8449_clk;
+ wire T_8449_reset;
+ wire T_8449_io_master_0_aw_ready;
+ wire T_8449_io_master_0_aw_valid;
+ wire [31:0] T_8449_io_master_0_aw_bits_addr;
+ wire [7:0] T_8449_io_master_0_aw_bits_len;
+ wire [2:0] T_8449_io_master_0_aw_bits_size;
+ wire [1:0] T_8449_io_master_0_aw_bits_burst;
+ wire T_8449_io_master_0_aw_bits_lock;
+ wire [3:0] T_8449_io_master_0_aw_bits_cache;
+ wire [2:0] T_8449_io_master_0_aw_bits_prot;
+ wire [3:0] T_8449_io_master_0_aw_bits_qos;
+ wire [3:0] T_8449_io_master_0_aw_bits_region;
+ wire [4:0] T_8449_io_master_0_aw_bits_id;
+ wire T_8449_io_master_0_aw_bits_user;
+ wire T_8449_io_master_0_w_ready;
+ wire T_8449_io_master_0_w_valid;
+ wire [63:0] T_8449_io_master_0_w_bits_data;
+ wire T_8449_io_master_0_w_bits_last;
+ wire [7:0] T_8449_io_master_0_w_bits_strb;
+ wire T_8449_io_master_0_w_bits_user;
+ wire T_8449_io_master_0_b_ready;
+ wire T_8449_io_master_0_b_valid;
+ wire [1:0] T_8449_io_master_0_b_bits_resp;
+ wire [4:0] T_8449_io_master_0_b_bits_id;
+ wire T_8449_io_master_0_b_bits_user;
+ wire T_8449_io_master_0_ar_ready;
+ wire T_8449_io_master_0_ar_valid;
+ wire [31:0] T_8449_io_master_0_ar_bits_addr;
+ wire [7:0] T_8449_io_master_0_ar_bits_len;
+ wire [2:0] T_8449_io_master_0_ar_bits_size;
+ wire [1:0] T_8449_io_master_0_ar_bits_burst;
+ wire T_8449_io_master_0_ar_bits_lock;
+ wire [3:0] T_8449_io_master_0_ar_bits_cache;
+ wire [2:0] T_8449_io_master_0_ar_bits_prot;
+ wire [3:0] T_8449_io_master_0_ar_bits_qos;
+ wire [3:0] T_8449_io_master_0_ar_bits_region;
+ wire [4:0] T_8449_io_master_0_ar_bits_id;
+ wire T_8449_io_master_0_ar_bits_user;
+ wire T_8449_io_master_0_r_ready;
+ wire T_8449_io_master_0_r_valid;
+ wire [1:0] T_8449_io_master_0_r_bits_resp;
+ wire [63:0] T_8449_io_master_0_r_bits_data;
+ wire T_8449_io_master_0_r_bits_last;
+ wire [4:0] T_8449_io_master_0_r_bits_id;
+ wire T_8449_io_master_0_r_bits_user;
+ wire T_8449_io_master_1_aw_ready;
+ wire T_8449_io_master_1_aw_valid;
+ wire [31:0] T_8449_io_master_1_aw_bits_addr;
+ wire [7:0] T_8449_io_master_1_aw_bits_len;
+ wire [2:0] T_8449_io_master_1_aw_bits_size;
+ wire [1:0] T_8449_io_master_1_aw_bits_burst;
+ wire T_8449_io_master_1_aw_bits_lock;
+ wire [3:0] T_8449_io_master_1_aw_bits_cache;
+ wire [2:0] T_8449_io_master_1_aw_bits_prot;
+ wire [3:0] T_8449_io_master_1_aw_bits_qos;
+ wire [3:0] T_8449_io_master_1_aw_bits_region;
+ wire [4:0] T_8449_io_master_1_aw_bits_id;
+ wire T_8449_io_master_1_aw_bits_user;
+ wire T_8449_io_master_1_w_ready;
+ wire T_8449_io_master_1_w_valid;
+ wire [63:0] T_8449_io_master_1_w_bits_data;
+ wire T_8449_io_master_1_w_bits_last;
+ wire [7:0] T_8449_io_master_1_w_bits_strb;
+ wire T_8449_io_master_1_w_bits_user;
+ wire T_8449_io_master_1_b_ready;
+ wire T_8449_io_master_1_b_valid;
+ wire [1:0] T_8449_io_master_1_b_bits_resp;
+ wire [4:0] T_8449_io_master_1_b_bits_id;
+ wire T_8449_io_master_1_b_bits_user;
+ wire T_8449_io_master_1_ar_ready;
+ wire T_8449_io_master_1_ar_valid;
+ wire [31:0] T_8449_io_master_1_ar_bits_addr;
+ wire [7:0] T_8449_io_master_1_ar_bits_len;
+ wire [2:0] T_8449_io_master_1_ar_bits_size;
+ wire [1:0] T_8449_io_master_1_ar_bits_burst;
+ wire T_8449_io_master_1_ar_bits_lock;
+ wire [3:0] T_8449_io_master_1_ar_bits_cache;
+ wire [2:0] T_8449_io_master_1_ar_bits_prot;
+ wire [3:0] T_8449_io_master_1_ar_bits_qos;
+ wire [3:0] T_8449_io_master_1_ar_bits_region;
+ wire [4:0] T_8449_io_master_1_ar_bits_id;
+ wire T_8449_io_master_1_ar_bits_user;
+ wire T_8449_io_master_1_r_ready;
+ wire T_8449_io_master_1_r_valid;
+ wire [1:0] T_8449_io_master_1_r_bits_resp;
+ wire [63:0] T_8449_io_master_1_r_bits_data;
+ wire T_8449_io_master_1_r_bits_last;
+ wire [4:0] T_8449_io_master_1_r_bits_id;
+ wire T_8449_io_master_1_r_bits_user;
+ wire T_8449_io_slave_aw_ready;
+ wire T_8449_io_slave_aw_valid;
+ wire [31:0] T_8449_io_slave_aw_bits_addr;
+ wire [7:0] T_8449_io_slave_aw_bits_len;
+ wire [2:0] T_8449_io_slave_aw_bits_size;
+ wire [1:0] T_8449_io_slave_aw_bits_burst;
+ wire T_8449_io_slave_aw_bits_lock;
+ wire [3:0] T_8449_io_slave_aw_bits_cache;
+ wire [2:0] T_8449_io_slave_aw_bits_prot;
+ wire [3:0] T_8449_io_slave_aw_bits_qos;
+ wire [3:0] T_8449_io_slave_aw_bits_region;
+ wire [4:0] T_8449_io_slave_aw_bits_id;
+ wire T_8449_io_slave_aw_bits_user;
+ wire T_8449_io_slave_w_ready;
+ wire T_8449_io_slave_w_valid;
+ wire [63:0] T_8449_io_slave_w_bits_data;
+ wire T_8449_io_slave_w_bits_last;
+ wire [7:0] T_8449_io_slave_w_bits_strb;
+ wire T_8449_io_slave_w_bits_user;
+ wire T_8449_io_slave_b_ready;
+ wire T_8449_io_slave_b_valid;
+ wire [1:0] T_8449_io_slave_b_bits_resp;
+ wire [4:0] T_8449_io_slave_b_bits_id;
+ wire T_8449_io_slave_b_bits_user;
+ wire T_8449_io_slave_ar_ready;
+ wire T_8449_io_slave_ar_valid;
+ wire [31:0] T_8449_io_slave_ar_bits_addr;
+ wire [7:0] T_8449_io_slave_ar_bits_len;
+ wire [2:0] T_8449_io_slave_ar_bits_size;
+ wire [1:0] T_8449_io_slave_ar_bits_burst;
+ wire T_8449_io_slave_ar_bits_lock;
+ wire [3:0] T_8449_io_slave_ar_bits_cache;
+ wire [2:0] T_8449_io_slave_ar_bits_prot;
+ wire [3:0] T_8449_io_slave_ar_bits_qos;
+ wire [3:0] T_8449_io_slave_ar_bits_region;
+ wire [4:0] T_8449_io_slave_ar_bits_id;
+ wire T_8449_io_slave_ar_bits_user;
+ wire T_8449_io_slave_r_ready;
+ wire T_8449_io_slave_r_valid;
+ wire [1:0] T_8449_io_slave_r_bits_resp;
+ wire [63:0] T_8449_io_slave_r_bits_data;
+ wire T_8449_io_slave_r_bits_last;
+ wire [4:0] T_8449_io_slave_r_bits_id;
+ wire T_8449_io_slave_r_bits_user;
+ wire T_8450_clk;
+ wire T_8450_reset;
+ wire T_8450_io_master_0_aw_ready;
+ wire T_8450_io_master_0_aw_valid;
+ wire [31:0] T_8450_io_master_0_aw_bits_addr;
+ wire [7:0] T_8450_io_master_0_aw_bits_len;
+ wire [2:0] T_8450_io_master_0_aw_bits_size;
+ wire [1:0] T_8450_io_master_0_aw_bits_burst;
+ wire T_8450_io_master_0_aw_bits_lock;
+ wire [3:0] T_8450_io_master_0_aw_bits_cache;
+ wire [2:0] T_8450_io_master_0_aw_bits_prot;
+ wire [3:0] T_8450_io_master_0_aw_bits_qos;
+ wire [3:0] T_8450_io_master_0_aw_bits_region;
+ wire [4:0] T_8450_io_master_0_aw_bits_id;
+ wire T_8450_io_master_0_aw_bits_user;
+ wire T_8450_io_master_0_w_ready;
+ wire T_8450_io_master_0_w_valid;
+ wire [63:0] T_8450_io_master_0_w_bits_data;
+ wire T_8450_io_master_0_w_bits_last;
+ wire [7:0] T_8450_io_master_0_w_bits_strb;
+ wire T_8450_io_master_0_w_bits_user;
+ wire T_8450_io_master_0_b_ready;
+ wire T_8450_io_master_0_b_valid;
+ wire [1:0] T_8450_io_master_0_b_bits_resp;
+ wire [4:0] T_8450_io_master_0_b_bits_id;
+ wire T_8450_io_master_0_b_bits_user;
+ wire T_8450_io_master_0_ar_ready;
+ wire T_8450_io_master_0_ar_valid;
+ wire [31:0] T_8450_io_master_0_ar_bits_addr;
+ wire [7:0] T_8450_io_master_0_ar_bits_len;
+ wire [2:0] T_8450_io_master_0_ar_bits_size;
+ wire [1:0] T_8450_io_master_0_ar_bits_burst;
+ wire T_8450_io_master_0_ar_bits_lock;
+ wire [3:0] T_8450_io_master_0_ar_bits_cache;
+ wire [2:0] T_8450_io_master_0_ar_bits_prot;
+ wire [3:0] T_8450_io_master_0_ar_bits_qos;
+ wire [3:0] T_8450_io_master_0_ar_bits_region;
+ wire [4:0] T_8450_io_master_0_ar_bits_id;
+ wire T_8450_io_master_0_ar_bits_user;
+ wire T_8450_io_master_0_r_ready;
+ wire T_8450_io_master_0_r_valid;
+ wire [1:0] T_8450_io_master_0_r_bits_resp;
+ wire [63:0] T_8450_io_master_0_r_bits_data;
+ wire T_8450_io_master_0_r_bits_last;
+ wire [4:0] T_8450_io_master_0_r_bits_id;
+ wire T_8450_io_master_0_r_bits_user;
+ wire T_8450_io_master_1_aw_ready;
+ wire T_8450_io_master_1_aw_valid;
+ wire [31:0] T_8450_io_master_1_aw_bits_addr;
+ wire [7:0] T_8450_io_master_1_aw_bits_len;
+ wire [2:0] T_8450_io_master_1_aw_bits_size;
+ wire [1:0] T_8450_io_master_1_aw_bits_burst;
+ wire T_8450_io_master_1_aw_bits_lock;
+ wire [3:0] T_8450_io_master_1_aw_bits_cache;
+ wire [2:0] T_8450_io_master_1_aw_bits_prot;
+ wire [3:0] T_8450_io_master_1_aw_bits_qos;
+ wire [3:0] T_8450_io_master_1_aw_bits_region;
+ wire [4:0] T_8450_io_master_1_aw_bits_id;
+ wire T_8450_io_master_1_aw_bits_user;
+ wire T_8450_io_master_1_w_ready;
+ wire T_8450_io_master_1_w_valid;
+ wire [63:0] T_8450_io_master_1_w_bits_data;
+ wire T_8450_io_master_1_w_bits_last;
+ wire [7:0] T_8450_io_master_1_w_bits_strb;
+ wire T_8450_io_master_1_w_bits_user;
+ wire T_8450_io_master_1_b_ready;
+ wire T_8450_io_master_1_b_valid;
+ wire [1:0] T_8450_io_master_1_b_bits_resp;
+ wire [4:0] T_8450_io_master_1_b_bits_id;
+ wire T_8450_io_master_1_b_bits_user;
+ wire T_8450_io_master_1_ar_ready;
+ wire T_8450_io_master_1_ar_valid;
+ wire [31:0] T_8450_io_master_1_ar_bits_addr;
+ wire [7:0] T_8450_io_master_1_ar_bits_len;
+ wire [2:0] T_8450_io_master_1_ar_bits_size;
+ wire [1:0] T_8450_io_master_1_ar_bits_burst;
+ wire T_8450_io_master_1_ar_bits_lock;
+ wire [3:0] T_8450_io_master_1_ar_bits_cache;
+ wire [2:0] T_8450_io_master_1_ar_bits_prot;
+ wire [3:0] T_8450_io_master_1_ar_bits_qos;
+ wire [3:0] T_8450_io_master_1_ar_bits_region;
+ wire [4:0] T_8450_io_master_1_ar_bits_id;
+ wire T_8450_io_master_1_ar_bits_user;
+ wire T_8450_io_master_1_r_ready;
+ wire T_8450_io_master_1_r_valid;
+ wire [1:0] T_8450_io_master_1_r_bits_resp;
+ wire [63:0] T_8450_io_master_1_r_bits_data;
+ wire T_8450_io_master_1_r_bits_last;
+ wire [4:0] T_8450_io_master_1_r_bits_id;
+ wire T_8450_io_master_1_r_bits_user;
+ wire T_8450_io_slave_aw_ready;
+ wire T_8450_io_slave_aw_valid;
+ wire [31:0] T_8450_io_slave_aw_bits_addr;
+ wire [7:0] T_8450_io_slave_aw_bits_len;
+ wire [2:0] T_8450_io_slave_aw_bits_size;
+ wire [1:0] T_8450_io_slave_aw_bits_burst;
+ wire T_8450_io_slave_aw_bits_lock;
+ wire [3:0] T_8450_io_slave_aw_bits_cache;
+ wire [2:0] T_8450_io_slave_aw_bits_prot;
+ wire [3:0] T_8450_io_slave_aw_bits_qos;
+ wire [3:0] T_8450_io_slave_aw_bits_region;
+ wire [4:0] T_8450_io_slave_aw_bits_id;
+ wire T_8450_io_slave_aw_bits_user;
+ wire T_8450_io_slave_w_ready;
+ wire T_8450_io_slave_w_valid;
+ wire [63:0] T_8450_io_slave_w_bits_data;
+ wire T_8450_io_slave_w_bits_last;
+ wire [7:0] T_8450_io_slave_w_bits_strb;
+ wire T_8450_io_slave_w_bits_user;
+ wire T_8450_io_slave_b_ready;
+ wire T_8450_io_slave_b_valid;
+ wire [1:0] T_8450_io_slave_b_bits_resp;
+ wire [4:0] T_8450_io_slave_b_bits_id;
+ wire T_8450_io_slave_b_bits_user;
+ wire T_8450_io_slave_ar_ready;
+ wire T_8450_io_slave_ar_valid;
+ wire [31:0] T_8450_io_slave_ar_bits_addr;
+ wire [7:0] T_8450_io_slave_ar_bits_len;
+ wire [2:0] T_8450_io_slave_ar_bits_size;
+ wire [1:0] T_8450_io_slave_ar_bits_burst;
+ wire T_8450_io_slave_ar_bits_lock;
+ wire [3:0] T_8450_io_slave_ar_bits_cache;
+ wire [2:0] T_8450_io_slave_ar_bits_prot;
+ wire [3:0] T_8450_io_slave_ar_bits_qos;
+ wire [3:0] T_8450_io_slave_ar_bits_region;
+ wire [4:0] T_8450_io_slave_ar_bits_id;
+ wire T_8450_io_slave_ar_bits_user;
+ wire T_8450_io_slave_r_ready;
+ wire T_8450_io_slave_r_valid;
+ wire [1:0] T_8450_io_slave_r_bits_resp;
+ wire [63:0] T_8450_io_slave_r_bits_data;
+ wire T_8450_io_slave_r_bits_last;
+ wire [4:0] T_8450_io_slave_r_bits_id;
+ wire T_8450_io_slave_r_bits_user;
+ wire T_8451_clk;
+ wire T_8451_reset;
+ wire T_8451_io_master_0_aw_ready;
+ wire T_8451_io_master_0_aw_valid;
+ wire [31:0] T_8451_io_master_0_aw_bits_addr;
+ wire [7:0] T_8451_io_master_0_aw_bits_len;
+ wire [2:0] T_8451_io_master_0_aw_bits_size;
+ wire [1:0] T_8451_io_master_0_aw_bits_burst;
+ wire T_8451_io_master_0_aw_bits_lock;
+ wire [3:0] T_8451_io_master_0_aw_bits_cache;
+ wire [2:0] T_8451_io_master_0_aw_bits_prot;
+ wire [3:0] T_8451_io_master_0_aw_bits_qos;
+ wire [3:0] T_8451_io_master_0_aw_bits_region;
+ wire [4:0] T_8451_io_master_0_aw_bits_id;
+ wire T_8451_io_master_0_aw_bits_user;
+ wire T_8451_io_master_0_w_ready;
+ wire T_8451_io_master_0_w_valid;
+ wire [63:0] T_8451_io_master_0_w_bits_data;
+ wire T_8451_io_master_0_w_bits_last;
+ wire [7:0] T_8451_io_master_0_w_bits_strb;
+ wire T_8451_io_master_0_w_bits_user;
+ wire T_8451_io_master_0_b_ready;
+ wire T_8451_io_master_0_b_valid;
+ wire [1:0] T_8451_io_master_0_b_bits_resp;
+ wire [4:0] T_8451_io_master_0_b_bits_id;
+ wire T_8451_io_master_0_b_bits_user;
+ wire T_8451_io_master_0_ar_ready;
+ wire T_8451_io_master_0_ar_valid;
+ wire [31:0] T_8451_io_master_0_ar_bits_addr;
+ wire [7:0] T_8451_io_master_0_ar_bits_len;
+ wire [2:0] T_8451_io_master_0_ar_bits_size;
+ wire [1:0] T_8451_io_master_0_ar_bits_burst;
+ wire T_8451_io_master_0_ar_bits_lock;
+ wire [3:0] T_8451_io_master_0_ar_bits_cache;
+ wire [2:0] T_8451_io_master_0_ar_bits_prot;
+ wire [3:0] T_8451_io_master_0_ar_bits_qos;
+ wire [3:0] T_8451_io_master_0_ar_bits_region;
+ wire [4:0] T_8451_io_master_0_ar_bits_id;
+ wire T_8451_io_master_0_ar_bits_user;
+ wire T_8451_io_master_0_r_ready;
+ wire T_8451_io_master_0_r_valid;
+ wire [1:0] T_8451_io_master_0_r_bits_resp;
+ wire [63:0] T_8451_io_master_0_r_bits_data;
+ wire T_8451_io_master_0_r_bits_last;
+ wire [4:0] T_8451_io_master_0_r_bits_id;
+ wire T_8451_io_master_0_r_bits_user;
+ wire T_8451_io_master_1_aw_ready;
+ wire T_8451_io_master_1_aw_valid;
+ wire [31:0] T_8451_io_master_1_aw_bits_addr;
+ wire [7:0] T_8451_io_master_1_aw_bits_len;
+ wire [2:0] T_8451_io_master_1_aw_bits_size;
+ wire [1:0] T_8451_io_master_1_aw_bits_burst;
+ wire T_8451_io_master_1_aw_bits_lock;
+ wire [3:0] T_8451_io_master_1_aw_bits_cache;
+ wire [2:0] T_8451_io_master_1_aw_bits_prot;
+ wire [3:0] T_8451_io_master_1_aw_bits_qos;
+ wire [3:0] T_8451_io_master_1_aw_bits_region;
+ wire [4:0] T_8451_io_master_1_aw_bits_id;
+ wire T_8451_io_master_1_aw_bits_user;
+ wire T_8451_io_master_1_w_ready;
+ wire T_8451_io_master_1_w_valid;
+ wire [63:0] T_8451_io_master_1_w_bits_data;
+ wire T_8451_io_master_1_w_bits_last;
+ wire [7:0] T_8451_io_master_1_w_bits_strb;
+ wire T_8451_io_master_1_w_bits_user;
+ wire T_8451_io_master_1_b_ready;
+ wire T_8451_io_master_1_b_valid;
+ wire [1:0] T_8451_io_master_1_b_bits_resp;
+ wire [4:0] T_8451_io_master_1_b_bits_id;
+ wire T_8451_io_master_1_b_bits_user;
+ wire T_8451_io_master_1_ar_ready;
+ wire T_8451_io_master_1_ar_valid;
+ wire [31:0] T_8451_io_master_1_ar_bits_addr;
+ wire [7:0] T_8451_io_master_1_ar_bits_len;
+ wire [2:0] T_8451_io_master_1_ar_bits_size;
+ wire [1:0] T_8451_io_master_1_ar_bits_burst;
+ wire T_8451_io_master_1_ar_bits_lock;
+ wire [3:0] T_8451_io_master_1_ar_bits_cache;
+ wire [2:0] T_8451_io_master_1_ar_bits_prot;
+ wire [3:0] T_8451_io_master_1_ar_bits_qos;
+ wire [3:0] T_8451_io_master_1_ar_bits_region;
+ wire [4:0] T_8451_io_master_1_ar_bits_id;
+ wire T_8451_io_master_1_ar_bits_user;
+ wire T_8451_io_master_1_r_ready;
+ wire T_8451_io_master_1_r_valid;
+ wire [1:0] T_8451_io_master_1_r_bits_resp;
+ wire [63:0] T_8451_io_master_1_r_bits_data;
+ wire T_8451_io_master_1_r_bits_last;
+ wire [4:0] T_8451_io_master_1_r_bits_id;
+ wire T_8451_io_master_1_r_bits_user;
+ wire T_8451_io_slave_aw_ready;
+ wire T_8451_io_slave_aw_valid;
+ wire [31:0] T_8451_io_slave_aw_bits_addr;
+ wire [7:0] T_8451_io_slave_aw_bits_len;
+ wire [2:0] T_8451_io_slave_aw_bits_size;
+ wire [1:0] T_8451_io_slave_aw_bits_burst;
+ wire T_8451_io_slave_aw_bits_lock;
+ wire [3:0] T_8451_io_slave_aw_bits_cache;
+ wire [2:0] T_8451_io_slave_aw_bits_prot;
+ wire [3:0] T_8451_io_slave_aw_bits_qos;
+ wire [3:0] T_8451_io_slave_aw_bits_region;
+ wire [4:0] T_8451_io_slave_aw_bits_id;
+ wire T_8451_io_slave_aw_bits_user;
+ wire T_8451_io_slave_w_ready;
+ wire T_8451_io_slave_w_valid;
+ wire [63:0] T_8451_io_slave_w_bits_data;
+ wire T_8451_io_slave_w_bits_last;
+ wire [7:0] T_8451_io_slave_w_bits_strb;
+ wire T_8451_io_slave_w_bits_user;
+ wire T_8451_io_slave_b_ready;
+ wire T_8451_io_slave_b_valid;
+ wire [1:0] T_8451_io_slave_b_bits_resp;
+ wire [4:0] T_8451_io_slave_b_bits_id;
+ wire T_8451_io_slave_b_bits_user;
+ wire T_8451_io_slave_ar_ready;
+ wire T_8451_io_slave_ar_valid;
+ wire [31:0] T_8451_io_slave_ar_bits_addr;
+ wire [7:0] T_8451_io_slave_ar_bits_len;
+ wire [2:0] T_8451_io_slave_ar_bits_size;
+ wire [1:0] T_8451_io_slave_ar_bits_burst;
+ wire T_8451_io_slave_ar_bits_lock;
+ wire [3:0] T_8451_io_slave_ar_bits_cache;
+ wire [2:0] T_8451_io_slave_ar_bits_prot;
+ wire [3:0] T_8451_io_slave_ar_bits_qos;
+ wire [3:0] T_8451_io_slave_ar_bits_region;
+ wire [4:0] T_8451_io_slave_ar_bits_id;
+ wire T_8451_io_slave_ar_bits_user;
+ wire T_8451_io_slave_r_ready;
+ wire T_8451_io_slave_r_valid;
+ wire [1:0] T_8451_io_slave_r_bits_resp;
+ wire [63:0] T_8451_io_slave_r_bits_data;
+ wire T_8451_io_slave_r_bits_last;
+ wire [4:0] T_8451_io_slave_r_bits_id;
+ wire T_8451_io_slave_r_bits_user;
+ wire T_8452_clk;
+ wire T_8452_reset;
+ wire T_8452_io_master_0_aw_ready;
+ wire T_8452_io_master_0_aw_valid;
+ wire [31:0] T_8452_io_master_0_aw_bits_addr;
+ wire [7:0] T_8452_io_master_0_aw_bits_len;
+ wire [2:0] T_8452_io_master_0_aw_bits_size;
+ wire [1:0] T_8452_io_master_0_aw_bits_burst;
+ wire T_8452_io_master_0_aw_bits_lock;
+ wire [3:0] T_8452_io_master_0_aw_bits_cache;
+ wire [2:0] T_8452_io_master_0_aw_bits_prot;
+ wire [3:0] T_8452_io_master_0_aw_bits_qos;
+ wire [3:0] T_8452_io_master_0_aw_bits_region;
+ wire [4:0] T_8452_io_master_0_aw_bits_id;
+ wire T_8452_io_master_0_aw_bits_user;
+ wire T_8452_io_master_0_w_ready;
+ wire T_8452_io_master_0_w_valid;
+ wire [63:0] T_8452_io_master_0_w_bits_data;
+ wire T_8452_io_master_0_w_bits_last;
+ wire [7:0] T_8452_io_master_0_w_bits_strb;
+ wire T_8452_io_master_0_w_bits_user;
+ wire T_8452_io_master_0_b_ready;
+ wire T_8452_io_master_0_b_valid;
+ wire [1:0] T_8452_io_master_0_b_bits_resp;
+ wire [4:0] T_8452_io_master_0_b_bits_id;
+ wire T_8452_io_master_0_b_bits_user;
+ wire T_8452_io_master_0_ar_ready;
+ wire T_8452_io_master_0_ar_valid;
+ wire [31:0] T_8452_io_master_0_ar_bits_addr;
+ wire [7:0] T_8452_io_master_0_ar_bits_len;
+ wire [2:0] T_8452_io_master_0_ar_bits_size;
+ wire [1:0] T_8452_io_master_0_ar_bits_burst;
+ wire T_8452_io_master_0_ar_bits_lock;
+ wire [3:0] T_8452_io_master_0_ar_bits_cache;
+ wire [2:0] T_8452_io_master_0_ar_bits_prot;
+ wire [3:0] T_8452_io_master_0_ar_bits_qos;
+ wire [3:0] T_8452_io_master_0_ar_bits_region;
+ wire [4:0] T_8452_io_master_0_ar_bits_id;
+ wire T_8452_io_master_0_ar_bits_user;
+ wire T_8452_io_master_0_r_ready;
+ wire T_8452_io_master_0_r_valid;
+ wire [1:0] T_8452_io_master_0_r_bits_resp;
+ wire [63:0] T_8452_io_master_0_r_bits_data;
+ wire T_8452_io_master_0_r_bits_last;
+ wire [4:0] T_8452_io_master_0_r_bits_id;
+ wire T_8452_io_master_0_r_bits_user;
+ wire T_8452_io_master_1_aw_ready;
+ wire T_8452_io_master_1_aw_valid;
+ wire [31:0] T_8452_io_master_1_aw_bits_addr;
+ wire [7:0] T_8452_io_master_1_aw_bits_len;
+ wire [2:0] T_8452_io_master_1_aw_bits_size;
+ wire [1:0] T_8452_io_master_1_aw_bits_burst;
+ wire T_8452_io_master_1_aw_bits_lock;
+ wire [3:0] T_8452_io_master_1_aw_bits_cache;
+ wire [2:0] T_8452_io_master_1_aw_bits_prot;
+ wire [3:0] T_8452_io_master_1_aw_bits_qos;
+ wire [3:0] T_8452_io_master_1_aw_bits_region;
+ wire [4:0] T_8452_io_master_1_aw_bits_id;
+ wire T_8452_io_master_1_aw_bits_user;
+ wire T_8452_io_master_1_w_ready;
+ wire T_8452_io_master_1_w_valid;
+ wire [63:0] T_8452_io_master_1_w_bits_data;
+ wire T_8452_io_master_1_w_bits_last;
+ wire [7:0] T_8452_io_master_1_w_bits_strb;
+ wire T_8452_io_master_1_w_bits_user;
+ wire T_8452_io_master_1_b_ready;
+ wire T_8452_io_master_1_b_valid;
+ wire [1:0] T_8452_io_master_1_b_bits_resp;
+ wire [4:0] T_8452_io_master_1_b_bits_id;
+ wire T_8452_io_master_1_b_bits_user;
+ wire T_8452_io_master_1_ar_ready;
+ wire T_8452_io_master_1_ar_valid;
+ wire [31:0] T_8452_io_master_1_ar_bits_addr;
+ wire [7:0] T_8452_io_master_1_ar_bits_len;
+ wire [2:0] T_8452_io_master_1_ar_bits_size;
+ wire [1:0] T_8452_io_master_1_ar_bits_burst;
+ wire T_8452_io_master_1_ar_bits_lock;
+ wire [3:0] T_8452_io_master_1_ar_bits_cache;
+ wire [2:0] T_8452_io_master_1_ar_bits_prot;
+ wire [3:0] T_8452_io_master_1_ar_bits_qos;
+ wire [3:0] T_8452_io_master_1_ar_bits_region;
+ wire [4:0] T_8452_io_master_1_ar_bits_id;
+ wire T_8452_io_master_1_ar_bits_user;
+ wire T_8452_io_master_1_r_ready;
+ wire T_8452_io_master_1_r_valid;
+ wire [1:0] T_8452_io_master_1_r_bits_resp;
+ wire [63:0] T_8452_io_master_1_r_bits_data;
+ wire T_8452_io_master_1_r_bits_last;
+ wire [4:0] T_8452_io_master_1_r_bits_id;
+ wire T_8452_io_master_1_r_bits_user;
+ wire T_8452_io_slave_aw_ready;
+ wire T_8452_io_slave_aw_valid;
+ wire [31:0] T_8452_io_slave_aw_bits_addr;
+ wire [7:0] T_8452_io_slave_aw_bits_len;
+ wire [2:0] T_8452_io_slave_aw_bits_size;
+ wire [1:0] T_8452_io_slave_aw_bits_burst;
+ wire T_8452_io_slave_aw_bits_lock;
+ wire [3:0] T_8452_io_slave_aw_bits_cache;
+ wire [2:0] T_8452_io_slave_aw_bits_prot;
+ wire [3:0] T_8452_io_slave_aw_bits_qos;
+ wire [3:0] T_8452_io_slave_aw_bits_region;
+ wire [4:0] T_8452_io_slave_aw_bits_id;
+ wire T_8452_io_slave_aw_bits_user;
+ wire T_8452_io_slave_w_ready;
+ wire T_8452_io_slave_w_valid;
+ wire [63:0] T_8452_io_slave_w_bits_data;
+ wire T_8452_io_slave_w_bits_last;
+ wire [7:0] T_8452_io_slave_w_bits_strb;
+ wire T_8452_io_slave_w_bits_user;
+ wire T_8452_io_slave_b_ready;
+ wire T_8452_io_slave_b_valid;
+ wire [1:0] T_8452_io_slave_b_bits_resp;
+ wire [4:0] T_8452_io_slave_b_bits_id;
+ wire T_8452_io_slave_b_bits_user;
+ wire T_8452_io_slave_ar_ready;
+ wire T_8452_io_slave_ar_valid;
+ wire [31:0] T_8452_io_slave_ar_bits_addr;
+ wire [7:0] T_8452_io_slave_ar_bits_len;
+ wire [2:0] T_8452_io_slave_ar_bits_size;
+ wire [1:0] T_8452_io_slave_ar_bits_burst;
+ wire T_8452_io_slave_ar_bits_lock;
+ wire [3:0] T_8452_io_slave_ar_bits_cache;
+ wire [2:0] T_8452_io_slave_ar_bits_prot;
+ wire [3:0] T_8452_io_slave_ar_bits_qos;
+ wire [3:0] T_8452_io_slave_ar_bits_region;
+ wire [4:0] T_8452_io_slave_ar_bits_id;
+ wire T_8452_io_slave_ar_bits_user;
+ wire T_8452_io_slave_r_ready;
+ wire T_8452_io_slave_r_valid;
+ wire [1:0] T_8452_io_slave_r_bits_resp;
+ wire [63:0] T_8452_io_slave_r_bits_data;
+ wire T_8452_io_slave_r_bits_last;
+ wire [4:0] T_8452_io_slave_r_bits_id;
+ wire T_8452_io_slave_r_bits_user;
+ wire T_10206_0_master_0_aw_ready;
+ wire T_10206_0_master_0_aw_valid;
+ wire [31:0] T_10206_0_master_0_aw_bits_addr;
+ wire [7:0] T_10206_0_master_0_aw_bits_len;
+ wire [2:0] T_10206_0_master_0_aw_bits_size;
+ wire [1:0] T_10206_0_master_0_aw_bits_burst;
+ wire T_10206_0_master_0_aw_bits_lock;
+ wire [3:0] T_10206_0_master_0_aw_bits_cache;
+ wire [2:0] T_10206_0_master_0_aw_bits_prot;
+ wire [3:0] T_10206_0_master_0_aw_bits_qos;
+ wire [3:0] T_10206_0_master_0_aw_bits_region;
+ wire [4:0] T_10206_0_master_0_aw_bits_id;
+ wire T_10206_0_master_0_aw_bits_user;
+ wire T_10206_0_master_0_w_ready;
+ wire T_10206_0_master_0_w_valid;
+ wire [63:0] T_10206_0_master_0_w_bits_data;
+ wire T_10206_0_master_0_w_bits_last;
+ wire [7:0] T_10206_0_master_0_w_bits_strb;
+ wire T_10206_0_master_0_w_bits_user;
+ wire T_10206_0_master_0_b_ready;
+ wire T_10206_0_master_0_b_valid;
+ wire [1:0] T_10206_0_master_0_b_bits_resp;
+ wire [4:0] T_10206_0_master_0_b_bits_id;
+ wire T_10206_0_master_0_b_bits_user;
+ wire T_10206_0_master_0_ar_ready;
+ wire T_10206_0_master_0_ar_valid;
+ wire [31:0] T_10206_0_master_0_ar_bits_addr;
+ wire [7:0] T_10206_0_master_0_ar_bits_len;
+ wire [2:0] T_10206_0_master_0_ar_bits_size;
+ wire [1:0] T_10206_0_master_0_ar_bits_burst;
+ wire T_10206_0_master_0_ar_bits_lock;
+ wire [3:0] T_10206_0_master_0_ar_bits_cache;
+ wire [2:0] T_10206_0_master_0_ar_bits_prot;
+ wire [3:0] T_10206_0_master_0_ar_bits_qos;
+ wire [3:0] T_10206_0_master_0_ar_bits_region;
+ wire [4:0] T_10206_0_master_0_ar_bits_id;
+ wire T_10206_0_master_0_ar_bits_user;
+ wire T_10206_0_master_0_r_ready;
+ wire T_10206_0_master_0_r_valid;
+ wire [1:0] T_10206_0_master_0_r_bits_resp;
+ wire [63:0] T_10206_0_master_0_r_bits_data;
+ wire T_10206_0_master_0_r_bits_last;
+ wire [4:0] T_10206_0_master_0_r_bits_id;
+ wire T_10206_0_master_0_r_bits_user;
+ wire T_10206_0_master_1_aw_ready;
+ wire T_10206_0_master_1_aw_valid;
+ wire [31:0] T_10206_0_master_1_aw_bits_addr;
+ wire [7:0] T_10206_0_master_1_aw_bits_len;
+ wire [2:0] T_10206_0_master_1_aw_bits_size;
+ wire [1:0] T_10206_0_master_1_aw_bits_burst;
+ wire T_10206_0_master_1_aw_bits_lock;
+ wire [3:0] T_10206_0_master_1_aw_bits_cache;
+ wire [2:0] T_10206_0_master_1_aw_bits_prot;
+ wire [3:0] T_10206_0_master_1_aw_bits_qos;
+ wire [3:0] T_10206_0_master_1_aw_bits_region;
+ wire [4:0] T_10206_0_master_1_aw_bits_id;
+ wire T_10206_0_master_1_aw_bits_user;
+ wire T_10206_0_master_1_w_ready;
+ wire T_10206_0_master_1_w_valid;
+ wire [63:0] T_10206_0_master_1_w_bits_data;
+ wire T_10206_0_master_1_w_bits_last;
+ wire [7:0] T_10206_0_master_1_w_bits_strb;
+ wire T_10206_0_master_1_w_bits_user;
+ wire T_10206_0_master_1_b_ready;
+ wire T_10206_0_master_1_b_valid;
+ wire [1:0] T_10206_0_master_1_b_bits_resp;
+ wire [4:0] T_10206_0_master_1_b_bits_id;
+ wire T_10206_0_master_1_b_bits_user;
+ wire T_10206_0_master_1_ar_ready;
+ wire T_10206_0_master_1_ar_valid;
+ wire [31:0] T_10206_0_master_1_ar_bits_addr;
+ wire [7:0] T_10206_0_master_1_ar_bits_len;
+ wire [2:0] T_10206_0_master_1_ar_bits_size;
+ wire [1:0] T_10206_0_master_1_ar_bits_burst;
+ wire T_10206_0_master_1_ar_bits_lock;
+ wire [3:0] T_10206_0_master_1_ar_bits_cache;
+ wire [2:0] T_10206_0_master_1_ar_bits_prot;
+ wire [3:0] T_10206_0_master_1_ar_bits_qos;
+ wire [3:0] T_10206_0_master_1_ar_bits_region;
+ wire [4:0] T_10206_0_master_1_ar_bits_id;
+ wire T_10206_0_master_1_ar_bits_user;
+ wire T_10206_0_master_1_r_ready;
+ wire T_10206_0_master_1_r_valid;
+ wire [1:0] T_10206_0_master_1_r_bits_resp;
+ wire [63:0] T_10206_0_master_1_r_bits_data;
+ wire T_10206_0_master_1_r_bits_last;
+ wire [4:0] T_10206_0_master_1_r_bits_id;
+ wire T_10206_0_master_1_r_bits_user;
+ wire T_10206_0_slave_aw_ready;
+ wire T_10206_0_slave_aw_valid;
+ wire [31:0] T_10206_0_slave_aw_bits_addr;
+ wire [7:0] T_10206_0_slave_aw_bits_len;
+ wire [2:0] T_10206_0_slave_aw_bits_size;
+ wire [1:0] T_10206_0_slave_aw_bits_burst;
+ wire T_10206_0_slave_aw_bits_lock;
+ wire [3:0] T_10206_0_slave_aw_bits_cache;
+ wire [2:0] T_10206_0_slave_aw_bits_prot;
+ wire [3:0] T_10206_0_slave_aw_bits_qos;
+ wire [3:0] T_10206_0_slave_aw_bits_region;
+ wire [4:0] T_10206_0_slave_aw_bits_id;
+ wire T_10206_0_slave_aw_bits_user;
+ wire T_10206_0_slave_w_ready;
+ wire T_10206_0_slave_w_valid;
+ wire [63:0] T_10206_0_slave_w_bits_data;
+ wire T_10206_0_slave_w_bits_last;
+ wire [7:0] T_10206_0_slave_w_bits_strb;
+ wire T_10206_0_slave_w_bits_user;
+ wire T_10206_0_slave_b_ready;
+ wire T_10206_0_slave_b_valid;
+ wire [1:0] T_10206_0_slave_b_bits_resp;
+ wire [4:0] T_10206_0_slave_b_bits_id;
+ wire T_10206_0_slave_b_bits_user;
+ wire T_10206_0_slave_ar_ready;
+ wire T_10206_0_slave_ar_valid;
+ wire [31:0] T_10206_0_slave_ar_bits_addr;
+ wire [7:0] T_10206_0_slave_ar_bits_len;
+ wire [2:0] T_10206_0_slave_ar_bits_size;
+ wire [1:0] T_10206_0_slave_ar_bits_burst;
+ wire T_10206_0_slave_ar_bits_lock;
+ wire [3:0] T_10206_0_slave_ar_bits_cache;
+ wire [2:0] T_10206_0_slave_ar_bits_prot;
+ wire [3:0] T_10206_0_slave_ar_bits_qos;
+ wire [3:0] T_10206_0_slave_ar_bits_region;
+ wire [4:0] T_10206_0_slave_ar_bits_id;
+ wire T_10206_0_slave_ar_bits_user;
+ wire T_10206_0_slave_r_ready;
+ wire T_10206_0_slave_r_valid;
+ wire [1:0] T_10206_0_slave_r_bits_resp;
+ wire [63:0] T_10206_0_slave_r_bits_data;
+ wire T_10206_0_slave_r_bits_last;
+ wire [4:0] T_10206_0_slave_r_bits_id;
+ wire T_10206_0_slave_r_bits_user;
+ wire T_10206_1_master_0_aw_ready;
+ wire T_10206_1_master_0_aw_valid;
+ wire [31:0] T_10206_1_master_0_aw_bits_addr;
+ wire [7:0] T_10206_1_master_0_aw_bits_len;
+ wire [2:0] T_10206_1_master_0_aw_bits_size;
+ wire [1:0] T_10206_1_master_0_aw_bits_burst;
+ wire T_10206_1_master_0_aw_bits_lock;
+ wire [3:0] T_10206_1_master_0_aw_bits_cache;
+ wire [2:0] T_10206_1_master_0_aw_bits_prot;
+ wire [3:0] T_10206_1_master_0_aw_bits_qos;
+ wire [3:0] T_10206_1_master_0_aw_bits_region;
+ wire [4:0] T_10206_1_master_0_aw_bits_id;
+ wire T_10206_1_master_0_aw_bits_user;
+ wire T_10206_1_master_0_w_ready;
+ wire T_10206_1_master_0_w_valid;
+ wire [63:0] T_10206_1_master_0_w_bits_data;
+ wire T_10206_1_master_0_w_bits_last;
+ wire [7:0] T_10206_1_master_0_w_bits_strb;
+ wire T_10206_1_master_0_w_bits_user;
+ wire T_10206_1_master_0_b_ready;
+ wire T_10206_1_master_0_b_valid;
+ wire [1:0] T_10206_1_master_0_b_bits_resp;
+ wire [4:0] T_10206_1_master_0_b_bits_id;
+ wire T_10206_1_master_0_b_bits_user;
+ wire T_10206_1_master_0_ar_ready;
+ wire T_10206_1_master_0_ar_valid;
+ wire [31:0] T_10206_1_master_0_ar_bits_addr;
+ wire [7:0] T_10206_1_master_0_ar_bits_len;
+ wire [2:0] T_10206_1_master_0_ar_bits_size;
+ wire [1:0] T_10206_1_master_0_ar_bits_burst;
+ wire T_10206_1_master_0_ar_bits_lock;
+ wire [3:0] T_10206_1_master_0_ar_bits_cache;
+ wire [2:0] T_10206_1_master_0_ar_bits_prot;
+ wire [3:0] T_10206_1_master_0_ar_bits_qos;
+ wire [3:0] T_10206_1_master_0_ar_bits_region;
+ wire [4:0] T_10206_1_master_0_ar_bits_id;
+ wire T_10206_1_master_0_ar_bits_user;
+ wire T_10206_1_master_0_r_ready;
+ wire T_10206_1_master_0_r_valid;
+ wire [1:0] T_10206_1_master_0_r_bits_resp;
+ wire [63:0] T_10206_1_master_0_r_bits_data;
+ wire T_10206_1_master_0_r_bits_last;
+ wire [4:0] T_10206_1_master_0_r_bits_id;
+ wire T_10206_1_master_0_r_bits_user;
+ wire T_10206_1_master_1_aw_ready;
+ wire T_10206_1_master_1_aw_valid;
+ wire [31:0] T_10206_1_master_1_aw_bits_addr;
+ wire [7:0] T_10206_1_master_1_aw_bits_len;
+ wire [2:0] T_10206_1_master_1_aw_bits_size;
+ wire [1:0] T_10206_1_master_1_aw_bits_burst;
+ wire T_10206_1_master_1_aw_bits_lock;
+ wire [3:0] T_10206_1_master_1_aw_bits_cache;
+ wire [2:0] T_10206_1_master_1_aw_bits_prot;
+ wire [3:0] T_10206_1_master_1_aw_bits_qos;
+ wire [3:0] T_10206_1_master_1_aw_bits_region;
+ wire [4:0] T_10206_1_master_1_aw_bits_id;
+ wire T_10206_1_master_1_aw_bits_user;
+ wire T_10206_1_master_1_w_ready;
+ wire T_10206_1_master_1_w_valid;
+ wire [63:0] T_10206_1_master_1_w_bits_data;
+ wire T_10206_1_master_1_w_bits_last;
+ wire [7:0] T_10206_1_master_1_w_bits_strb;
+ wire T_10206_1_master_1_w_bits_user;
+ wire T_10206_1_master_1_b_ready;
+ wire T_10206_1_master_1_b_valid;
+ wire [1:0] T_10206_1_master_1_b_bits_resp;
+ wire [4:0] T_10206_1_master_1_b_bits_id;
+ wire T_10206_1_master_1_b_bits_user;
+ wire T_10206_1_master_1_ar_ready;
+ wire T_10206_1_master_1_ar_valid;
+ wire [31:0] T_10206_1_master_1_ar_bits_addr;
+ wire [7:0] T_10206_1_master_1_ar_bits_len;
+ wire [2:0] T_10206_1_master_1_ar_bits_size;
+ wire [1:0] T_10206_1_master_1_ar_bits_burst;
+ wire T_10206_1_master_1_ar_bits_lock;
+ wire [3:0] T_10206_1_master_1_ar_bits_cache;
+ wire [2:0] T_10206_1_master_1_ar_bits_prot;
+ wire [3:0] T_10206_1_master_1_ar_bits_qos;
+ wire [3:0] T_10206_1_master_1_ar_bits_region;
+ wire [4:0] T_10206_1_master_1_ar_bits_id;
+ wire T_10206_1_master_1_ar_bits_user;
+ wire T_10206_1_master_1_r_ready;
+ wire T_10206_1_master_1_r_valid;
+ wire [1:0] T_10206_1_master_1_r_bits_resp;
+ wire [63:0] T_10206_1_master_1_r_bits_data;
+ wire T_10206_1_master_1_r_bits_last;
+ wire [4:0] T_10206_1_master_1_r_bits_id;
+ wire T_10206_1_master_1_r_bits_user;
+ wire T_10206_1_slave_aw_ready;
+ wire T_10206_1_slave_aw_valid;
+ wire [31:0] T_10206_1_slave_aw_bits_addr;
+ wire [7:0] T_10206_1_slave_aw_bits_len;
+ wire [2:0] T_10206_1_slave_aw_bits_size;
+ wire [1:0] T_10206_1_slave_aw_bits_burst;
+ wire T_10206_1_slave_aw_bits_lock;
+ wire [3:0] T_10206_1_slave_aw_bits_cache;
+ wire [2:0] T_10206_1_slave_aw_bits_prot;
+ wire [3:0] T_10206_1_slave_aw_bits_qos;
+ wire [3:0] T_10206_1_slave_aw_bits_region;
+ wire [4:0] T_10206_1_slave_aw_bits_id;
+ wire T_10206_1_slave_aw_bits_user;
+ wire T_10206_1_slave_w_ready;
+ wire T_10206_1_slave_w_valid;
+ wire [63:0] T_10206_1_slave_w_bits_data;
+ wire T_10206_1_slave_w_bits_last;
+ wire [7:0] T_10206_1_slave_w_bits_strb;
+ wire T_10206_1_slave_w_bits_user;
+ wire T_10206_1_slave_b_ready;
+ wire T_10206_1_slave_b_valid;
+ wire [1:0] T_10206_1_slave_b_bits_resp;
+ wire [4:0] T_10206_1_slave_b_bits_id;
+ wire T_10206_1_slave_b_bits_user;
+ wire T_10206_1_slave_ar_ready;
+ wire T_10206_1_slave_ar_valid;
+ wire [31:0] T_10206_1_slave_ar_bits_addr;
+ wire [7:0] T_10206_1_slave_ar_bits_len;
+ wire [2:0] T_10206_1_slave_ar_bits_size;
+ wire [1:0] T_10206_1_slave_ar_bits_burst;
+ wire T_10206_1_slave_ar_bits_lock;
+ wire [3:0] T_10206_1_slave_ar_bits_cache;
+ wire [2:0] T_10206_1_slave_ar_bits_prot;
+ wire [3:0] T_10206_1_slave_ar_bits_qos;
+ wire [3:0] T_10206_1_slave_ar_bits_region;
+ wire [4:0] T_10206_1_slave_ar_bits_id;
+ wire T_10206_1_slave_ar_bits_user;
+ wire T_10206_1_slave_r_ready;
+ wire T_10206_1_slave_r_valid;
+ wire [1:0] T_10206_1_slave_r_bits_resp;
+ wire [63:0] T_10206_1_slave_r_bits_data;
+ wire T_10206_1_slave_r_bits_last;
+ wire [4:0] T_10206_1_slave_r_bits_id;
+ wire T_10206_1_slave_r_bits_user;
+ wire T_10206_2_master_0_aw_ready;
+ wire T_10206_2_master_0_aw_valid;
+ wire [31:0] T_10206_2_master_0_aw_bits_addr;
+ wire [7:0] T_10206_2_master_0_aw_bits_len;
+ wire [2:0] T_10206_2_master_0_aw_bits_size;
+ wire [1:0] T_10206_2_master_0_aw_bits_burst;
+ wire T_10206_2_master_0_aw_bits_lock;
+ wire [3:0] T_10206_2_master_0_aw_bits_cache;
+ wire [2:0] T_10206_2_master_0_aw_bits_prot;
+ wire [3:0] T_10206_2_master_0_aw_bits_qos;
+ wire [3:0] T_10206_2_master_0_aw_bits_region;
+ wire [4:0] T_10206_2_master_0_aw_bits_id;
+ wire T_10206_2_master_0_aw_bits_user;
+ wire T_10206_2_master_0_w_ready;
+ wire T_10206_2_master_0_w_valid;
+ wire [63:0] T_10206_2_master_0_w_bits_data;
+ wire T_10206_2_master_0_w_bits_last;
+ wire [7:0] T_10206_2_master_0_w_bits_strb;
+ wire T_10206_2_master_0_w_bits_user;
+ wire T_10206_2_master_0_b_ready;
+ wire T_10206_2_master_0_b_valid;
+ wire [1:0] T_10206_2_master_0_b_bits_resp;
+ wire [4:0] T_10206_2_master_0_b_bits_id;
+ wire T_10206_2_master_0_b_bits_user;
+ wire T_10206_2_master_0_ar_ready;
+ wire T_10206_2_master_0_ar_valid;
+ wire [31:0] T_10206_2_master_0_ar_bits_addr;
+ wire [7:0] T_10206_2_master_0_ar_bits_len;
+ wire [2:0] T_10206_2_master_0_ar_bits_size;
+ wire [1:0] T_10206_2_master_0_ar_bits_burst;
+ wire T_10206_2_master_0_ar_bits_lock;
+ wire [3:0] T_10206_2_master_0_ar_bits_cache;
+ wire [2:0] T_10206_2_master_0_ar_bits_prot;
+ wire [3:0] T_10206_2_master_0_ar_bits_qos;
+ wire [3:0] T_10206_2_master_0_ar_bits_region;
+ wire [4:0] T_10206_2_master_0_ar_bits_id;
+ wire T_10206_2_master_0_ar_bits_user;
+ wire T_10206_2_master_0_r_ready;
+ wire T_10206_2_master_0_r_valid;
+ wire [1:0] T_10206_2_master_0_r_bits_resp;
+ wire [63:0] T_10206_2_master_0_r_bits_data;
+ wire T_10206_2_master_0_r_bits_last;
+ wire [4:0] T_10206_2_master_0_r_bits_id;
+ wire T_10206_2_master_0_r_bits_user;
+ wire T_10206_2_master_1_aw_ready;
+ wire T_10206_2_master_1_aw_valid;
+ wire [31:0] T_10206_2_master_1_aw_bits_addr;
+ wire [7:0] T_10206_2_master_1_aw_bits_len;
+ wire [2:0] T_10206_2_master_1_aw_bits_size;
+ wire [1:0] T_10206_2_master_1_aw_bits_burst;
+ wire T_10206_2_master_1_aw_bits_lock;
+ wire [3:0] T_10206_2_master_1_aw_bits_cache;
+ wire [2:0] T_10206_2_master_1_aw_bits_prot;
+ wire [3:0] T_10206_2_master_1_aw_bits_qos;
+ wire [3:0] T_10206_2_master_1_aw_bits_region;
+ wire [4:0] T_10206_2_master_1_aw_bits_id;
+ wire T_10206_2_master_1_aw_bits_user;
+ wire T_10206_2_master_1_w_ready;
+ wire T_10206_2_master_1_w_valid;
+ wire [63:0] T_10206_2_master_1_w_bits_data;
+ wire T_10206_2_master_1_w_bits_last;
+ wire [7:0] T_10206_2_master_1_w_bits_strb;
+ wire T_10206_2_master_1_w_bits_user;
+ wire T_10206_2_master_1_b_ready;
+ wire T_10206_2_master_1_b_valid;
+ wire [1:0] T_10206_2_master_1_b_bits_resp;
+ wire [4:0] T_10206_2_master_1_b_bits_id;
+ wire T_10206_2_master_1_b_bits_user;
+ wire T_10206_2_master_1_ar_ready;
+ wire T_10206_2_master_1_ar_valid;
+ wire [31:0] T_10206_2_master_1_ar_bits_addr;
+ wire [7:0] T_10206_2_master_1_ar_bits_len;
+ wire [2:0] T_10206_2_master_1_ar_bits_size;
+ wire [1:0] T_10206_2_master_1_ar_bits_burst;
+ wire T_10206_2_master_1_ar_bits_lock;
+ wire [3:0] T_10206_2_master_1_ar_bits_cache;
+ wire [2:0] T_10206_2_master_1_ar_bits_prot;
+ wire [3:0] T_10206_2_master_1_ar_bits_qos;
+ wire [3:0] T_10206_2_master_1_ar_bits_region;
+ wire [4:0] T_10206_2_master_1_ar_bits_id;
+ wire T_10206_2_master_1_ar_bits_user;
+ wire T_10206_2_master_1_r_ready;
+ wire T_10206_2_master_1_r_valid;
+ wire [1:0] T_10206_2_master_1_r_bits_resp;
+ wire [63:0] T_10206_2_master_1_r_bits_data;
+ wire T_10206_2_master_1_r_bits_last;
+ wire [4:0] T_10206_2_master_1_r_bits_id;
+ wire T_10206_2_master_1_r_bits_user;
+ wire T_10206_2_slave_aw_ready;
+ wire T_10206_2_slave_aw_valid;
+ wire [31:0] T_10206_2_slave_aw_bits_addr;
+ wire [7:0] T_10206_2_slave_aw_bits_len;
+ wire [2:0] T_10206_2_slave_aw_bits_size;
+ wire [1:0] T_10206_2_slave_aw_bits_burst;
+ wire T_10206_2_slave_aw_bits_lock;
+ wire [3:0] T_10206_2_slave_aw_bits_cache;
+ wire [2:0] T_10206_2_slave_aw_bits_prot;
+ wire [3:0] T_10206_2_slave_aw_bits_qos;
+ wire [3:0] T_10206_2_slave_aw_bits_region;
+ wire [4:0] T_10206_2_slave_aw_bits_id;
+ wire T_10206_2_slave_aw_bits_user;
+ wire T_10206_2_slave_w_ready;
+ wire T_10206_2_slave_w_valid;
+ wire [63:0] T_10206_2_slave_w_bits_data;
+ wire T_10206_2_slave_w_bits_last;
+ wire [7:0] T_10206_2_slave_w_bits_strb;
+ wire T_10206_2_slave_w_bits_user;
+ wire T_10206_2_slave_b_ready;
+ wire T_10206_2_slave_b_valid;
+ wire [1:0] T_10206_2_slave_b_bits_resp;
+ wire [4:0] T_10206_2_slave_b_bits_id;
+ wire T_10206_2_slave_b_bits_user;
+ wire T_10206_2_slave_ar_ready;
+ wire T_10206_2_slave_ar_valid;
+ wire [31:0] T_10206_2_slave_ar_bits_addr;
+ wire [7:0] T_10206_2_slave_ar_bits_len;
+ wire [2:0] T_10206_2_slave_ar_bits_size;
+ wire [1:0] T_10206_2_slave_ar_bits_burst;
+ wire T_10206_2_slave_ar_bits_lock;
+ wire [3:0] T_10206_2_slave_ar_bits_cache;
+ wire [2:0] T_10206_2_slave_ar_bits_prot;
+ wire [3:0] T_10206_2_slave_ar_bits_qos;
+ wire [3:0] T_10206_2_slave_ar_bits_region;
+ wire [4:0] T_10206_2_slave_ar_bits_id;
+ wire T_10206_2_slave_ar_bits_user;
+ wire T_10206_2_slave_r_ready;
+ wire T_10206_2_slave_r_valid;
+ wire [1:0] T_10206_2_slave_r_bits_resp;
+ wire [63:0] T_10206_2_slave_r_bits_data;
+ wire T_10206_2_slave_r_bits_last;
+ wire [4:0] T_10206_2_slave_r_bits_id;
+ wire T_10206_2_slave_r_bits_user;
+ wire T_10206_3_master_0_aw_ready;
+ wire T_10206_3_master_0_aw_valid;
+ wire [31:0] T_10206_3_master_0_aw_bits_addr;
+ wire [7:0] T_10206_3_master_0_aw_bits_len;
+ wire [2:0] T_10206_3_master_0_aw_bits_size;
+ wire [1:0] T_10206_3_master_0_aw_bits_burst;
+ wire T_10206_3_master_0_aw_bits_lock;
+ wire [3:0] T_10206_3_master_0_aw_bits_cache;
+ wire [2:0] T_10206_3_master_0_aw_bits_prot;
+ wire [3:0] T_10206_3_master_0_aw_bits_qos;
+ wire [3:0] T_10206_3_master_0_aw_bits_region;
+ wire [4:0] T_10206_3_master_0_aw_bits_id;
+ wire T_10206_3_master_0_aw_bits_user;
+ wire T_10206_3_master_0_w_ready;
+ wire T_10206_3_master_0_w_valid;
+ wire [63:0] T_10206_3_master_0_w_bits_data;
+ wire T_10206_3_master_0_w_bits_last;
+ wire [7:0] T_10206_3_master_0_w_bits_strb;
+ wire T_10206_3_master_0_w_bits_user;
+ wire T_10206_3_master_0_b_ready;
+ wire T_10206_3_master_0_b_valid;
+ wire [1:0] T_10206_3_master_0_b_bits_resp;
+ wire [4:0] T_10206_3_master_0_b_bits_id;
+ wire T_10206_3_master_0_b_bits_user;
+ wire T_10206_3_master_0_ar_ready;
+ wire T_10206_3_master_0_ar_valid;
+ wire [31:0] T_10206_3_master_0_ar_bits_addr;
+ wire [7:0] T_10206_3_master_0_ar_bits_len;
+ wire [2:0] T_10206_3_master_0_ar_bits_size;
+ wire [1:0] T_10206_3_master_0_ar_bits_burst;
+ wire T_10206_3_master_0_ar_bits_lock;
+ wire [3:0] T_10206_3_master_0_ar_bits_cache;
+ wire [2:0] T_10206_3_master_0_ar_bits_prot;
+ wire [3:0] T_10206_3_master_0_ar_bits_qos;
+ wire [3:0] T_10206_3_master_0_ar_bits_region;
+ wire [4:0] T_10206_3_master_0_ar_bits_id;
+ wire T_10206_3_master_0_ar_bits_user;
+ wire T_10206_3_master_0_r_ready;
+ wire T_10206_3_master_0_r_valid;
+ wire [1:0] T_10206_3_master_0_r_bits_resp;
+ wire [63:0] T_10206_3_master_0_r_bits_data;
+ wire T_10206_3_master_0_r_bits_last;
+ wire [4:0] T_10206_3_master_0_r_bits_id;
+ wire T_10206_3_master_0_r_bits_user;
+ wire T_10206_3_master_1_aw_ready;
+ wire T_10206_3_master_1_aw_valid;
+ wire [31:0] T_10206_3_master_1_aw_bits_addr;
+ wire [7:0] T_10206_3_master_1_aw_bits_len;
+ wire [2:0] T_10206_3_master_1_aw_bits_size;
+ wire [1:0] T_10206_3_master_1_aw_bits_burst;
+ wire T_10206_3_master_1_aw_bits_lock;
+ wire [3:0] T_10206_3_master_1_aw_bits_cache;
+ wire [2:0] T_10206_3_master_1_aw_bits_prot;
+ wire [3:0] T_10206_3_master_1_aw_bits_qos;
+ wire [3:0] T_10206_3_master_1_aw_bits_region;
+ wire [4:0] T_10206_3_master_1_aw_bits_id;
+ wire T_10206_3_master_1_aw_bits_user;
+ wire T_10206_3_master_1_w_ready;
+ wire T_10206_3_master_1_w_valid;
+ wire [63:0] T_10206_3_master_1_w_bits_data;
+ wire T_10206_3_master_1_w_bits_last;
+ wire [7:0] T_10206_3_master_1_w_bits_strb;
+ wire T_10206_3_master_1_w_bits_user;
+ wire T_10206_3_master_1_b_ready;
+ wire T_10206_3_master_1_b_valid;
+ wire [1:0] T_10206_3_master_1_b_bits_resp;
+ wire [4:0] T_10206_3_master_1_b_bits_id;
+ wire T_10206_3_master_1_b_bits_user;
+ wire T_10206_3_master_1_ar_ready;
+ wire T_10206_3_master_1_ar_valid;
+ wire [31:0] T_10206_3_master_1_ar_bits_addr;
+ wire [7:0] T_10206_3_master_1_ar_bits_len;
+ wire [2:0] T_10206_3_master_1_ar_bits_size;
+ wire [1:0] T_10206_3_master_1_ar_bits_burst;
+ wire T_10206_3_master_1_ar_bits_lock;
+ wire [3:0] T_10206_3_master_1_ar_bits_cache;
+ wire [2:0] T_10206_3_master_1_ar_bits_prot;
+ wire [3:0] T_10206_3_master_1_ar_bits_qos;
+ wire [3:0] T_10206_3_master_1_ar_bits_region;
+ wire [4:0] T_10206_3_master_1_ar_bits_id;
+ wire T_10206_3_master_1_ar_bits_user;
+ wire T_10206_3_master_1_r_ready;
+ wire T_10206_3_master_1_r_valid;
+ wire [1:0] T_10206_3_master_1_r_bits_resp;
+ wire [63:0] T_10206_3_master_1_r_bits_data;
+ wire T_10206_3_master_1_r_bits_last;
+ wire [4:0] T_10206_3_master_1_r_bits_id;
+ wire T_10206_3_master_1_r_bits_user;
+ wire T_10206_3_slave_aw_ready;
+ wire T_10206_3_slave_aw_valid;
+ wire [31:0] T_10206_3_slave_aw_bits_addr;
+ wire [7:0] T_10206_3_slave_aw_bits_len;
+ wire [2:0] T_10206_3_slave_aw_bits_size;
+ wire [1:0] T_10206_3_slave_aw_bits_burst;
+ wire T_10206_3_slave_aw_bits_lock;
+ wire [3:0] T_10206_3_slave_aw_bits_cache;
+ wire [2:0] T_10206_3_slave_aw_bits_prot;
+ wire [3:0] T_10206_3_slave_aw_bits_qos;
+ wire [3:0] T_10206_3_slave_aw_bits_region;
+ wire [4:0] T_10206_3_slave_aw_bits_id;
+ wire T_10206_3_slave_aw_bits_user;
+ wire T_10206_3_slave_w_ready;
+ wire T_10206_3_slave_w_valid;
+ wire [63:0] T_10206_3_slave_w_bits_data;
+ wire T_10206_3_slave_w_bits_last;
+ wire [7:0] T_10206_3_slave_w_bits_strb;
+ wire T_10206_3_slave_w_bits_user;
+ wire T_10206_3_slave_b_ready;
+ wire T_10206_3_slave_b_valid;
+ wire [1:0] T_10206_3_slave_b_bits_resp;
+ wire [4:0] T_10206_3_slave_b_bits_id;
+ wire T_10206_3_slave_b_bits_user;
+ wire T_10206_3_slave_ar_ready;
+ wire T_10206_3_slave_ar_valid;
+ wire [31:0] T_10206_3_slave_ar_bits_addr;
+ wire [7:0] T_10206_3_slave_ar_bits_len;
+ wire [2:0] T_10206_3_slave_ar_bits_size;
+ wire [1:0] T_10206_3_slave_ar_bits_burst;
+ wire T_10206_3_slave_ar_bits_lock;
+ wire [3:0] T_10206_3_slave_ar_bits_cache;
+ wire [2:0] T_10206_3_slave_ar_bits_prot;
+ wire [3:0] T_10206_3_slave_ar_bits_qos;
+ wire [3:0] T_10206_3_slave_ar_bits_region;
+ wire [4:0] T_10206_3_slave_ar_bits_id;
+ wire T_10206_3_slave_ar_bits_user;
+ wire T_10206_3_slave_r_ready;
+ wire T_10206_3_slave_r_valid;
+ wire [1:0] T_10206_3_slave_r_bits_resp;
+ wire [63:0] T_10206_3_slave_r_bits_data;
+ wire T_10206_3_slave_r_bits_last;
+ wire [4:0] T_10206_3_slave_r_bits_id;
+ wire T_10206_3_slave_r_bits_user;
+ wire T_19131_0_aw_ready;
+ wire T_19131_0_aw_valid;
+ wire [31:0] T_19131_0_aw_bits_addr;
+ wire [7:0] T_19131_0_aw_bits_len;
+ wire [2:0] T_19131_0_aw_bits_size;
+ wire [1:0] T_19131_0_aw_bits_burst;
+ wire T_19131_0_aw_bits_lock;
+ wire [3:0] T_19131_0_aw_bits_cache;
+ wire [2:0] T_19131_0_aw_bits_prot;
+ wire [3:0] T_19131_0_aw_bits_qos;
+ wire [3:0] T_19131_0_aw_bits_region;
+ wire [4:0] T_19131_0_aw_bits_id;
+ wire T_19131_0_aw_bits_user;
+ wire T_19131_0_w_ready;
+ wire T_19131_0_w_valid;
+ wire [63:0] T_19131_0_w_bits_data;
+ wire T_19131_0_w_bits_last;
+ wire [7:0] T_19131_0_w_bits_strb;
+ wire T_19131_0_w_bits_user;
+ wire T_19131_0_b_ready;
+ wire T_19131_0_b_valid;
+ wire [1:0] T_19131_0_b_bits_resp;
+ wire [4:0] T_19131_0_b_bits_id;
+ wire T_19131_0_b_bits_user;
+ wire T_19131_0_ar_ready;
+ wire T_19131_0_ar_valid;
+ wire [31:0] T_19131_0_ar_bits_addr;
+ wire [7:0] T_19131_0_ar_bits_len;
+ wire [2:0] T_19131_0_ar_bits_size;
+ wire [1:0] T_19131_0_ar_bits_burst;
+ wire T_19131_0_ar_bits_lock;
+ wire [3:0] T_19131_0_ar_bits_cache;
+ wire [2:0] T_19131_0_ar_bits_prot;
+ wire [3:0] T_19131_0_ar_bits_qos;
+ wire [3:0] T_19131_0_ar_bits_region;
+ wire [4:0] T_19131_0_ar_bits_id;
+ wire T_19131_0_ar_bits_user;
+ wire T_19131_0_r_ready;
+ wire T_19131_0_r_valid;
+ wire [1:0] T_19131_0_r_bits_resp;
+ wire [63:0] T_19131_0_r_bits_data;
+ wire T_19131_0_r_bits_last;
+ wire [4:0] T_19131_0_r_bits_id;
+ wire T_19131_0_r_bits_user;
+ wire T_19131_1_aw_ready;
+ wire T_19131_1_aw_valid;
+ wire [31:0] T_19131_1_aw_bits_addr;
+ wire [7:0] T_19131_1_aw_bits_len;
+ wire [2:0] T_19131_1_aw_bits_size;
+ wire [1:0] T_19131_1_aw_bits_burst;
+ wire T_19131_1_aw_bits_lock;
+ wire [3:0] T_19131_1_aw_bits_cache;
+ wire [2:0] T_19131_1_aw_bits_prot;
+ wire [3:0] T_19131_1_aw_bits_qos;
+ wire [3:0] T_19131_1_aw_bits_region;
+ wire [4:0] T_19131_1_aw_bits_id;
+ wire T_19131_1_aw_bits_user;
+ wire T_19131_1_w_ready;
+ wire T_19131_1_w_valid;
+ wire [63:0] T_19131_1_w_bits_data;
+ wire T_19131_1_w_bits_last;
+ wire [7:0] T_19131_1_w_bits_strb;
+ wire T_19131_1_w_bits_user;
+ wire T_19131_1_b_ready;
+ wire T_19131_1_b_valid;
+ wire [1:0] T_19131_1_b_bits_resp;
+ wire [4:0] T_19131_1_b_bits_id;
+ wire T_19131_1_b_bits_user;
+ wire T_19131_1_ar_ready;
+ wire T_19131_1_ar_valid;
+ wire [31:0] T_19131_1_ar_bits_addr;
+ wire [7:0] T_19131_1_ar_bits_len;
+ wire [2:0] T_19131_1_ar_bits_size;
+ wire [1:0] T_19131_1_ar_bits_burst;
+ wire T_19131_1_ar_bits_lock;
+ wire [3:0] T_19131_1_ar_bits_cache;
+ wire [2:0] T_19131_1_ar_bits_prot;
+ wire [3:0] T_19131_1_ar_bits_qos;
+ wire [3:0] T_19131_1_ar_bits_region;
+ wire [4:0] T_19131_1_ar_bits_id;
+ wire T_19131_1_ar_bits_user;
+ wire T_19131_1_r_ready;
+ wire T_19131_1_r_valid;
+ wire [1:0] T_19131_1_r_bits_resp;
+ wire [63:0] T_19131_1_r_bits_data;
+ wire T_19131_1_r_bits_last;
+ wire [4:0] T_19131_1_r_bits_id;
+ wire T_19131_1_r_bits_user;
+ wire T_19768_0_aw_ready;
+ wire T_19768_0_aw_valid;
+ wire [31:0] T_19768_0_aw_bits_addr;
+ wire [7:0] T_19768_0_aw_bits_len;
+ wire [2:0] T_19768_0_aw_bits_size;
+ wire [1:0] T_19768_0_aw_bits_burst;
+ wire T_19768_0_aw_bits_lock;
+ wire [3:0] T_19768_0_aw_bits_cache;
+ wire [2:0] T_19768_0_aw_bits_prot;
+ wire [3:0] T_19768_0_aw_bits_qos;
+ wire [3:0] T_19768_0_aw_bits_region;
+ wire [4:0] T_19768_0_aw_bits_id;
+ wire T_19768_0_aw_bits_user;
+ wire T_19768_0_w_ready;
+ wire T_19768_0_w_valid;
+ wire [63:0] T_19768_0_w_bits_data;
+ wire T_19768_0_w_bits_last;
+ wire [7:0] T_19768_0_w_bits_strb;
+ wire T_19768_0_w_bits_user;
+ wire T_19768_0_b_ready;
+ wire T_19768_0_b_valid;
+ wire [1:0] T_19768_0_b_bits_resp;
+ wire [4:0] T_19768_0_b_bits_id;
+ wire T_19768_0_b_bits_user;
+ wire T_19768_0_ar_ready;
+ wire T_19768_0_ar_valid;
+ wire [31:0] T_19768_0_ar_bits_addr;
+ wire [7:0] T_19768_0_ar_bits_len;
+ wire [2:0] T_19768_0_ar_bits_size;
+ wire [1:0] T_19768_0_ar_bits_burst;
+ wire T_19768_0_ar_bits_lock;
+ wire [3:0] T_19768_0_ar_bits_cache;
+ wire [2:0] T_19768_0_ar_bits_prot;
+ wire [3:0] T_19768_0_ar_bits_qos;
+ wire [3:0] T_19768_0_ar_bits_region;
+ wire [4:0] T_19768_0_ar_bits_id;
+ wire T_19768_0_ar_bits_user;
+ wire T_19768_0_r_ready;
+ wire T_19768_0_r_valid;
+ wire [1:0] T_19768_0_r_bits_resp;
+ wire [63:0] T_19768_0_r_bits_data;
+ wire T_19768_0_r_bits_last;
+ wire [4:0] T_19768_0_r_bits_id;
+ wire T_19768_0_r_bits_user;
+ wire T_19768_1_aw_ready;
+ wire T_19768_1_aw_valid;
+ wire [31:0] T_19768_1_aw_bits_addr;
+ wire [7:0] T_19768_1_aw_bits_len;
+ wire [2:0] T_19768_1_aw_bits_size;
+ wire [1:0] T_19768_1_aw_bits_burst;
+ wire T_19768_1_aw_bits_lock;
+ wire [3:0] T_19768_1_aw_bits_cache;
+ wire [2:0] T_19768_1_aw_bits_prot;
+ wire [3:0] T_19768_1_aw_bits_qos;
+ wire [3:0] T_19768_1_aw_bits_region;
+ wire [4:0] T_19768_1_aw_bits_id;
+ wire T_19768_1_aw_bits_user;
+ wire T_19768_1_w_ready;
+ wire T_19768_1_w_valid;
+ wire [63:0] T_19768_1_w_bits_data;
+ wire T_19768_1_w_bits_last;
+ wire [7:0] T_19768_1_w_bits_strb;
+ wire T_19768_1_w_bits_user;
+ wire T_19768_1_b_ready;
+ wire T_19768_1_b_valid;
+ wire [1:0] T_19768_1_b_bits_resp;
+ wire [4:0] T_19768_1_b_bits_id;
+ wire T_19768_1_b_bits_user;
+ wire T_19768_1_ar_ready;
+ wire T_19768_1_ar_valid;
+ wire [31:0] T_19768_1_ar_bits_addr;
+ wire [7:0] T_19768_1_ar_bits_len;
+ wire [2:0] T_19768_1_ar_bits_size;
+ wire [1:0] T_19768_1_ar_bits_burst;
+ wire T_19768_1_ar_bits_lock;
+ wire [3:0] T_19768_1_ar_bits_cache;
+ wire [2:0] T_19768_1_ar_bits_prot;
+ wire [3:0] T_19768_1_ar_bits_qos;
+ wire [3:0] T_19768_1_ar_bits_region;
+ wire [4:0] T_19768_1_ar_bits_id;
+ wire T_19768_1_ar_bits_user;
+ wire T_19768_1_r_ready;
+ wire T_19768_1_r_valid;
+ wire [1:0] T_19768_1_r_bits_resp;
+ wire [63:0] T_19768_1_r_bits_data;
+ wire T_19768_1_r_bits_last;
+ wire [4:0] T_19768_1_r_bits_id;
+ wire T_19768_1_r_bits_user;
+ wire T_20405_0_aw_ready;
+ wire T_20405_0_aw_valid;
+ wire [31:0] T_20405_0_aw_bits_addr;
+ wire [7:0] T_20405_0_aw_bits_len;
+ wire [2:0] T_20405_0_aw_bits_size;
+ wire [1:0] T_20405_0_aw_bits_burst;
+ wire T_20405_0_aw_bits_lock;
+ wire [3:0] T_20405_0_aw_bits_cache;
+ wire [2:0] T_20405_0_aw_bits_prot;
+ wire [3:0] T_20405_0_aw_bits_qos;
+ wire [3:0] T_20405_0_aw_bits_region;
+ wire [4:0] T_20405_0_aw_bits_id;
+ wire T_20405_0_aw_bits_user;
+ wire T_20405_0_w_ready;
+ wire T_20405_0_w_valid;
+ wire [63:0] T_20405_0_w_bits_data;
+ wire T_20405_0_w_bits_last;
+ wire [7:0] T_20405_0_w_bits_strb;
+ wire T_20405_0_w_bits_user;
+ wire T_20405_0_b_ready;
+ wire T_20405_0_b_valid;
+ wire [1:0] T_20405_0_b_bits_resp;
+ wire [4:0] T_20405_0_b_bits_id;
+ wire T_20405_0_b_bits_user;
+ wire T_20405_0_ar_ready;
+ wire T_20405_0_ar_valid;
+ wire [31:0] T_20405_0_ar_bits_addr;
+ wire [7:0] T_20405_0_ar_bits_len;
+ wire [2:0] T_20405_0_ar_bits_size;
+ wire [1:0] T_20405_0_ar_bits_burst;
+ wire T_20405_0_ar_bits_lock;
+ wire [3:0] T_20405_0_ar_bits_cache;
+ wire [2:0] T_20405_0_ar_bits_prot;
+ wire [3:0] T_20405_0_ar_bits_qos;
+ wire [3:0] T_20405_0_ar_bits_region;
+ wire [4:0] T_20405_0_ar_bits_id;
+ wire T_20405_0_ar_bits_user;
+ wire T_20405_0_r_ready;
+ wire T_20405_0_r_valid;
+ wire [1:0] T_20405_0_r_bits_resp;
+ wire [63:0] T_20405_0_r_bits_data;
+ wire T_20405_0_r_bits_last;
+ wire [4:0] T_20405_0_r_bits_id;
+ wire T_20405_0_r_bits_user;
+ wire T_20405_1_aw_ready;
+ wire T_20405_1_aw_valid;
+ wire [31:0] T_20405_1_aw_bits_addr;
+ wire [7:0] T_20405_1_aw_bits_len;
+ wire [2:0] T_20405_1_aw_bits_size;
+ wire [1:0] T_20405_1_aw_bits_burst;
+ wire T_20405_1_aw_bits_lock;
+ wire [3:0] T_20405_1_aw_bits_cache;
+ wire [2:0] T_20405_1_aw_bits_prot;
+ wire [3:0] T_20405_1_aw_bits_qos;
+ wire [3:0] T_20405_1_aw_bits_region;
+ wire [4:0] T_20405_1_aw_bits_id;
+ wire T_20405_1_aw_bits_user;
+ wire T_20405_1_w_ready;
+ wire T_20405_1_w_valid;
+ wire [63:0] T_20405_1_w_bits_data;
+ wire T_20405_1_w_bits_last;
+ wire [7:0] T_20405_1_w_bits_strb;
+ wire T_20405_1_w_bits_user;
+ wire T_20405_1_b_ready;
+ wire T_20405_1_b_valid;
+ wire [1:0] T_20405_1_b_bits_resp;
+ wire [4:0] T_20405_1_b_bits_id;
+ wire T_20405_1_b_bits_user;
+ wire T_20405_1_ar_ready;
+ wire T_20405_1_ar_valid;
+ wire [31:0] T_20405_1_ar_bits_addr;
+ wire [7:0] T_20405_1_ar_bits_len;
+ wire [2:0] T_20405_1_ar_bits_size;
+ wire [1:0] T_20405_1_ar_bits_burst;
+ wire T_20405_1_ar_bits_lock;
+ wire [3:0] T_20405_1_ar_bits_cache;
+ wire [2:0] T_20405_1_ar_bits_prot;
+ wire [3:0] T_20405_1_ar_bits_qos;
+ wire [3:0] T_20405_1_ar_bits_region;
+ wire [4:0] T_20405_1_ar_bits_id;
+ wire T_20405_1_ar_bits_user;
+ wire T_20405_1_r_ready;
+ wire T_20405_1_r_valid;
+ wire [1:0] T_20405_1_r_bits_resp;
+ wire [63:0] T_20405_1_r_bits_data;
+ wire T_20405_1_r_bits_last;
+ wire [4:0] T_20405_1_r_bits_id;
+ wire T_20405_1_r_bits_user;
+ wire T_21042_0_aw_ready;
+ wire T_21042_0_aw_valid;
+ wire [31:0] T_21042_0_aw_bits_addr;
+ wire [7:0] T_21042_0_aw_bits_len;
+ wire [2:0] T_21042_0_aw_bits_size;
+ wire [1:0] T_21042_0_aw_bits_burst;
+ wire T_21042_0_aw_bits_lock;
+ wire [3:0] T_21042_0_aw_bits_cache;
+ wire [2:0] T_21042_0_aw_bits_prot;
+ wire [3:0] T_21042_0_aw_bits_qos;
+ wire [3:0] T_21042_0_aw_bits_region;
+ wire [4:0] T_21042_0_aw_bits_id;
+ wire T_21042_0_aw_bits_user;
+ wire T_21042_0_w_ready;
+ wire T_21042_0_w_valid;
+ wire [63:0] T_21042_0_w_bits_data;
+ wire T_21042_0_w_bits_last;
+ wire [7:0] T_21042_0_w_bits_strb;
+ wire T_21042_0_w_bits_user;
+ wire T_21042_0_b_ready;
+ wire T_21042_0_b_valid;
+ wire [1:0] T_21042_0_b_bits_resp;
+ wire [4:0] T_21042_0_b_bits_id;
+ wire T_21042_0_b_bits_user;
+ wire T_21042_0_ar_ready;
+ wire T_21042_0_ar_valid;
+ wire [31:0] T_21042_0_ar_bits_addr;
+ wire [7:0] T_21042_0_ar_bits_len;
+ wire [2:0] T_21042_0_ar_bits_size;
+ wire [1:0] T_21042_0_ar_bits_burst;
+ wire T_21042_0_ar_bits_lock;
+ wire [3:0] T_21042_0_ar_bits_cache;
+ wire [2:0] T_21042_0_ar_bits_prot;
+ wire [3:0] T_21042_0_ar_bits_qos;
+ wire [3:0] T_21042_0_ar_bits_region;
+ wire [4:0] T_21042_0_ar_bits_id;
+ wire T_21042_0_ar_bits_user;
+ wire T_21042_0_r_ready;
+ wire T_21042_0_r_valid;
+ wire [1:0] T_21042_0_r_bits_resp;
+ wire [63:0] T_21042_0_r_bits_data;
+ wire T_21042_0_r_bits_last;
+ wire [4:0] T_21042_0_r_bits_id;
+ wire T_21042_0_r_bits_user;
+ wire T_21042_1_aw_ready;
+ wire T_21042_1_aw_valid;
+ wire [31:0] T_21042_1_aw_bits_addr;
+ wire [7:0] T_21042_1_aw_bits_len;
+ wire [2:0] T_21042_1_aw_bits_size;
+ wire [1:0] T_21042_1_aw_bits_burst;
+ wire T_21042_1_aw_bits_lock;
+ wire [3:0] T_21042_1_aw_bits_cache;
+ wire [2:0] T_21042_1_aw_bits_prot;
+ wire [3:0] T_21042_1_aw_bits_qos;
+ wire [3:0] T_21042_1_aw_bits_region;
+ wire [4:0] T_21042_1_aw_bits_id;
+ wire T_21042_1_aw_bits_user;
+ wire T_21042_1_w_ready;
+ wire T_21042_1_w_valid;
+ wire [63:0] T_21042_1_w_bits_data;
+ wire T_21042_1_w_bits_last;
+ wire [7:0] T_21042_1_w_bits_strb;
+ wire T_21042_1_w_bits_user;
+ wire T_21042_1_b_ready;
+ wire T_21042_1_b_valid;
+ wire [1:0] T_21042_1_b_bits_resp;
+ wire [4:0] T_21042_1_b_bits_id;
+ wire T_21042_1_b_bits_user;
+ wire T_21042_1_ar_ready;
+ wire T_21042_1_ar_valid;
+ wire [31:0] T_21042_1_ar_bits_addr;
+ wire [7:0] T_21042_1_ar_bits_len;
+ wire [2:0] T_21042_1_ar_bits_size;
+ wire [1:0] T_21042_1_ar_bits_burst;
+ wire T_21042_1_ar_bits_lock;
+ wire [3:0] T_21042_1_ar_bits_cache;
+ wire [2:0] T_21042_1_ar_bits_prot;
+ wire [3:0] T_21042_1_ar_bits_qos;
+ wire [3:0] T_21042_1_ar_bits_region;
+ wire [4:0] T_21042_1_ar_bits_id;
+ wire T_21042_1_ar_bits_user;
+ wire T_21042_1_r_ready;
+ wire T_21042_1_r_valid;
+ wire [1:0] T_21042_1_r_bits_resp;
+ wire [63:0] T_21042_1_r_bits_data;
+ wire T_21042_1_r_bits_last;
+ wire [4:0] T_21042_1_r_bits_id;
+ wire T_21042_1_r_bits_user;
+ NastiRouter T_2710 (
+ .clk(T_2710_clk),
+ .reset(T_2710_reset),
+ .io_master_aw_ready(T_2710_io_master_aw_ready),
+ .io_master_aw_valid(T_2710_io_master_aw_valid),
+ .io_master_aw_bits_addr(T_2710_io_master_aw_bits_addr),
+ .io_master_aw_bits_len(T_2710_io_master_aw_bits_len),
+ .io_master_aw_bits_size(T_2710_io_master_aw_bits_size),
+ .io_master_aw_bits_burst(T_2710_io_master_aw_bits_burst),
+ .io_master_aw_bits_lock(T_2710_io_master_aw_bits_lock),
+ .io_master_aw_bits_cache(T_2710_io_master_aw_bits_cache),
+ .io_master_aw_bits_prot(T_2710_io_master_aw_bits_prot),
+ .io_master_aw_bits_qos(T_2710_io_master_aw_bits_qos),
+ .io_master_aw_bits_region(T_2710_io_master_aw_bits_region),
+ .io_master_aw_bits_id(T_2710_io_master_aw_bits_id),
+ .io_master_aw_bits_user(T_2710_io_master_aw_bits_user),
+ .io_master_w_ready(T_2710_io_master_w_ready),
+ .io_master_w_valid(T_2710_io_master_w_valid),
+ .io_master_w_bits_data(T_2710_io_master_w_bits_data),
+ .io_master_w_bits_last(T_2710_io_master_w_bits_last),
+ .io_master_w_bits_strb(T_2710_io_master_w_bits_strb),
+ .io_master_w_bits_user(T_2710_io_master_w_bits_user),
+ .io_master_b_ready(T_2710_io_master_b_ready),
+ .io_master_b_valid(T_2710_io_master_b_valid),
+ .io_master_b_bits_resp(T_2710_io_master_b_bits_resp),
+ .io_master_b_bits_id(T_2710_io_master_b_bits_id),
+ .io_master_b_bits_user(T_2710_io_master_b_bits_user),
+ .io_master_ar_ready(T_2710_io_master_ar_ready),
+ .io_master_ar_valid(T_2710_io_master_ar_valid),
+ .io_master_ar_bits_addr(T_2710_io_master_ar_bits_addr),
+ .io_master_ar_bits_len(T_2710_io_master_ar_bits_len),
+ .io_master_ar_bits_size(T_2710_io_master_ar_bits_size),
+ .io_master_ar_bits_burst(T_2710_io_master_ar_bits_burst),
+ .io_master_ar_bits_lock(T_2710_io_master_ar_bits_lock),
+ .io_master_ar_bits_cache(T_2710_io_master_ar_bits_cache),
+ .io_master_ar_bits_prot(T_2710_io_master_ar_bits_prot),
+ .io_master_ar_bits_qos(T_2710_io_master_ar_bits_qos),
+ .io_master_ar_bits_region(T_2710_io_master_ar_bits_region),
+ .io_master_ar_bits_id(T_2710_io_master_ar_bits_id),
+ .io_master_ar_bits_user(T_2710_io_master_ar_bits_user),
+ .io_master_r_ready(T_2710_io_master_r_ready),
+ .io_master_r_valid(T_2710_io_master_r_valid),
+ .io_master_r_bits_resp(T_2710_io_master_r_bits_resp),
+ .io_master_r_bits_data(T_2710_io_master_r_bits_data),
+ .io_master_r_bits_last(T_2710_io_master_r_bits_last),
+ .io_master_r_bits_id(T_2710_io_master_r_bits_id),
+ .io_master_r_bits_user(T_2710_io_master_r_bits_user),
+ .io_slave_0_aw_ready(T_2710_io_slave_0_aw_ready),
+ .io_slave_0_aw_valid(T_2710_io_slave_0_aw_valid),
+ .io_slave_0_aw_bits_addr(T_2710_io_slave_0_aw_bits_addr),
+ .io_slave_0_aw_bits_len(T_2710_io_slave_0_aw_bits_len),
+ .io_slave_0_aw_bits_size(T_2710_io_slave_0_aw_bits_size),
+ .io_slave_0_aw_bits_burst(T_2710_io_slave_0_aw_bits_burst),
+ .io_slave_0_aw_bits_lock(T_2710_io_slave_0_aw_bits_lock),
+ .io_slave_0_aw_bits_cache(T_2710_io_slave_0_aw_bits_cache),
+ .io_slave_0_aw_bits_prot(T_2710_io_slave_0_aw_bits_prot),
+ .io_slave_0_aw_bits_qos(T_2710_io_slave_0_aw_bits_qos),
+ .io_slave_0_aw_bits_region(T_2710_io_slave_0_aw_bits_region),
+ .io_slave_0_aw_bits_id(T_2710_io_slave_0_aw_bits_id),
+ .io_slave_0_aw_bits_user(T_2710_io_slave_0_aw_bits_user),
+ .io_slave_0_w_ready(T_2710_io_slave_0_w_ready),
+ .io_slave_0_w_valid(T_2710_io_slave_0_w_valid),
+ .io_slave_0_w_bits_data(T_2710_io_slave_0_w_bits_data),
+ .io_slave_0_w_bits_last(T_2710_io_slave_0_w_bits_last),
+ .io_slave_0_w_bits_strb(T_2710_io_slave_0_w_bits_strb),
+ .io_slave_0_w_bits_user(T_2710_io_slave_0_w_bits_user),
+ .io_slave_0_b_ready(T_2710_io_slave_0_b_ready),
+ .io_slave_0_b_valid(T_2710_io_slave_0_b_valid),
+ .io_slave_0_b_bits_resp(T_2710_io_slave_0_b_bits_resp),
+ .io_slave_0_b_bits_id(T_2710_io_slave_0_b_bits_id),
+ .io_slave_0_b_bits_user(T_2710_io_slave_0_b_bits_user),
+ .io_slave_0_ar_ready(T_2710_io_slave_0_ar_ready),
+ .io_slave_0_ar_valid(T_2710_io_slave_0_ar_valid),
+ .io_slave_0_ar_bits_addr(T_2710_io_slave_0_ar_bits_addr),
+ .io_slave_0_ar_bits_len(T_2710_io_slave_0_ar_bits_len),
+ .io_slave_0_ar_bits_size(T_2710_io_slave_0_ar_bits_size),
+ .io_slave_0_ar_bits_burst(T_2710_io_slave_0_ar_bits_burst),
+ .io_slave_0_ar_bits_lock(T_2710_io_slave_0_ar_bits_lock),
+ .io_slave_0_ar_bits_cache(T_2710_io_slave_0_ar_bits_cache),
+ .io_slave_0_ar_bits_prot(T_2710_io_slave_0_ar_bits_prot),
+ .io_slave_0_ar_bits_qos(T_2710_io_slave_0_ar_bits_qos),
+ .io_slave_0_ar_bits_region(T_2710_io_slave_0_ar_bits_region),
+ .io_slave_0_ar_bits_id(T_2710_io_slave_0_ar_bits_id),
+ .io_slave_0_ar_bits_user(T_2710_io_slave_0_ar_bits_user),
+ .io_slave_0_r_ready(T_2710_io_slave_0_r_ready),
+ .io_slave_0_r_valid(T_2710_io_slave_0_r_valid),
+ .io_slave_0_r_bits_resp(T_2710_io_slave_0_r_bits_resp),
+ .io_slave_0_r_bits_data(T_2710_io_slave_0_r_bits_data),
+ .io_slave_0_r_bits_last(T_2710_io_slave_0_r_bits_last),
+ .io_slave_0_r_bits_id(T_2710_io_slave_0_r_bits_id),
+ .io_slave_0_r_bits_user(T_2710_io_slave_0_r_bits_user),
+ .io_slave_1_aw_ready(T_2710_io_slave_1_aw_ready),
+ .io_slave_1_aw_valid(T_2710_io_slave_1_aw_valid),
+ .io_slave_1_aw_bits_addr(T_2710_io_slave_1_aw_bits_addr),
+ .io_slave_1_aw_bits_len(T_2710_io_slave_1_aw_bits_len),
+ .io_slave_1_aw_bits_size(T_2710_io_slave_1_aw_bits_size),
+ .io_slave_1_aw_bits_burst(T_2710_io_slave_1_aw_bits_burst),
+ .io_slave_1_aw_bits_lock(T_2710_io_slave_1_aw_bits_lock),
+ .io_slave_1_aw_bits_cache(T_2710_io_slave_1_aw_bits_cache),
+ .io_slave_1_aw_bits_prot(T_2710_io_slave_1_aw_bits_prot),
+ .io_slave_1_aw_bits_qos(T_2710_io_slave_1_aw_bits_qos),
+ .io_slave_1_aw_bits_region(T_2710_io_slave_1_aw_bits_region),
+ .io_slave_1_aw_bits_id(T_2710_io_slave_1_aw_bits_id),
+ .io_slave_1_aw_bits_user(T_2710_io_slave_1_aw_bits_user),
+ .io_slave_1_w_ready(T_2710_io_slave_1_w_ready),
+ .io_slave_1_w_valid(T_2710_io_slave_1_w_valid),
+ .io_slave_1_w_bits_data(T_2710_io_slave_1_w_bits_data),
+ .io_slave_1_w_bits_last(T_2710_io_slave_1_w_bits_last),
+ .io_slave_1_w_bits_strb(T_2710_io_slave_1_w_bits_strb),
+ .io_slave_1_w_bits_user(T_2710_io_slave_1_w_bits_user),
+ .io_slave_1_b_ready(T_2710_io_slave_1_b_ready),
+ .io_slave_1_b_valid(T_2710_io_slave_1_b_valid),
+ .io_slave_1_b_bits_resp(T_2710_io_slave_1_b_bits_resp),
+ .io_slave_1_b_bits_id(T_2710_io_slave_1_b_bits_id),
+ .io_slave_1_b_bits_user(T_2710_io_slave_1_b_bits_user),
+ .io_slave_1_ar_ready(T_2710_io_slave_1_ar_ready),
+ .io_slave_1_ar_valid(T_2710_io_slave_1_ar_valid),
+ .io_slave_1_ar_bits_addr(T_2710_io_slave_1_ar_bits_addr),
+ .io_slave_1_ar_bits_len(T_2710_io_slave_1_ar_bits_len),
+ .io_slave_1_ar_bits_size(T_2710_io_slave_1_ar_bits_size),
+ .io_slave_1_ar_bits_burst(T_2710_io_slave_1_ar_bits_burst),
+ .io_slave_1_ar_bits_lock(T_2710_io_slave_1_ar_bits_lock),
+ .io_slave_1_ar_bits_cache(T_2710_io_slave_1_ar_bits_cache),
+ .io_slave_1_ar_bits_prot(T_2710_io_slave_1_ar_bits_prot),
+ .io_slave_1_ar_bits_qos(T_2710_io_slave_1_ar_bits_qos),
+ .io_slave_1_ar_bits_region(T_2710_io_slave_1_ar_bits_region),
+ .io_slave_1_ar_bits_id(T_2710_io_slave_1_ar_bits_id),
+ .io_slave_1_ar_bits_user(T_2710_io_slave_1_ar_bits_user),
+ .io_slave_1_r_ready(T_2710_io_slave_1_r_ready),
+ .io_slave_1_r_valid(T_2710_io_slave_1_r_valid),
+ .io_slave_1_r_bits_resp(T_2710_io_slave_1_r_bits_resp),
+ .io_slave_1_r_bits_data(T_2710_io_slave_1_r_bits_data),
+ .io_slave_1_r_bits_last(T_2710_io_slave_1_r_bits_last),
+ .io_slave_1_r_bits_id(T_2710_io_slave_1_r_bits_id),
+ .io_slave_1_r_bits_user(T_2710_io_slave_1_r_bits_user),
+ .io_slave_2_aw_ready(T_2710_io_slave_2_aw_ready),
+ .io_slave_2_aw_valid(T_2710_io_slave_2_aw_valid),
+ .io_slave_2_aw_bits_addr(T_2710_io_slave_2_aw_bits_addr),
+ .io_slave_2_aw_bits_len(T_2710_io_slave_2_aw_bits_len),
+ .io_slave_2_aw_bits_size(T_2710_io_slave_2_aw_bits_size),
+ .io_slave_2_aw_bits_burst(T_2710_io_slave_2_aw_bits_burst),
+ .io_slave_2_aw_bits_lock(T_2710_io_slave_2_aw_bits_lock),
+ .io_slave_2_aw_bits_cache(T_2710_io_slave_2_aw_bits_cache),
+ .io_slave_2_aw_bits_prot(T_2710_io_slave_2_aw_bits_prot),
+ .io_slave_2_aw_bits_qos(T_2710_io_slave_2_aw_bits_qos),
+ .io_slave_2_aw_bits_region(T_2710_io_slave_2_aw_bits_region),
+ .io_slave_2_aw_bits_id(T_2710_io_slave_2_aw_bits_id),
+ .io_slave_2_aw_bits_user(T_2710_io_slave_2_aw_bits_user),
+ .io_slave_2_w_ready(T_2710_io_slave_2_w_ready),
+ .io_slave_2_w_valid(T_2710_io_slave_2_w_valid),
+ .io_slave_2_w_bits_data(T_2710_io_slave_2_w_bits_data),
+ .io_slave_2_w_bits_last(T_2710_io_slave_2_w_bits_last),
+ .io_slave_2_w_bits_strb(T_2710_io_slave_2_w_bits_strb),
+ .io_slave_2_w_bits_user(T_2710_io_slave_2_w_bits_user),
+ .io_slave_2_b_ready(T_2710_io_slave_2_b_ready),
+ .io_slave_2_b_valid(T_2710_io_slave_2_b_valid),
+ .io_slave_2_b_bits_resp(T_2710_io_slave_2_b_bits_resp),
+ .io_slave_2_b_bits_id(T_2710_io_slave_2_b_bits_id),
+ .io_slave_2_b_bits_user(T_2710_io_slave_2_b_bits_user),
+ .io_slave_2_ar_ready(T_2710_io_slave_2_ar_ready),
+ .io_slave_2_ar_valid(T_2710_io_slave_2_ar_valid),
+ .io_slave_2_ar_bits_addr(T_2710_io_slave_2_ar_bits_addr),
+ .io_slave_2_ar_bits_len(T_2710_io_slave_2_ar_bits_len),
+ .io_slave_2_ar_bits_size(T_2710_io_slave_2_ar_bits_size),
+ .io_slave_2_ar_bits_burst(T_2710_io_slave_2_ar_bits_burst),
+ .io_slave_2_ar_bits_lock(T_2710_io_slave_2_ar_bits_lock),
+ .io_slave_2_ar_bits_cache(T_2710_io_slave_2_ar_bits_cache),
+ .io_slave_2_ar_bits_prot(T_2710_io_slave_2_ar_bits_prot),
+ .io_slave_2_ar_bits_qos(T_2710_io_slave_2_ar_bits_qos),
+ .io_slave_2_ar_bits_region(T_2710_io_slave_2_ar_bits_region),
+ .io_slave_2_ar_bits_id(T_2710_io_slave_2_ar_bits_id),
+ .io_slave_2_ar_bits_user(T_2710_io_slave_2_ar_bits_user),
+ .io_slave_2_r_ready(T_2710_io_slave_2_r_ready),
+ .io_slave_2_r_valid(T_2710_io_slave_2_r_valid),
+ .io_slave_2_r_bits_resp(T_2710_io_slave_2_r_bits_resp),
+ .io_slave_2_r_bits_data(T_2710_io_slave_2_r_bits_data),
+ .io_slave_2_r_bits_last(T_2710_io_slave_2_r_bits_last),
+ .io_slave_2_r_bits_id(T_2710_io_slave_2_r_bits_id),
+ .io_slave_2_r_bits_user(T_2710_io_slave_2_r_bits_user),
+ .io_slave_3_aw_ready(T_2710_io_slave_3_aw_ready),
+ .io_slave_3_aw_valid(T_2710_io_slave_3_aw_valid),
+ .io_slave_3_aw_bits_addr(T_2710_io_slave_3_aw_bits_addr),
+ .io_slave_3_aw_bits_len(T_2710_io_slave_3_aw_bits_len),
+ .io_slave_3_aw_bits_size(T_2710_io_slave_3_aw_bits_size),
+ .io_slave_3_aw_bits_burst(T_2710_io_slave_3_aw_bits_burst),
+ .io_slave_3_aw_bits_lock(T_2710_io_slave_3_aw_bits_lock),
+ .io_slave_3_aw_bits_cache(T_2710_io_slave_3_aw_bits_cache),
+ .io_slave_3_aw_bits_prot(T_2710_io_slave_3_aw_bits_prot),
+ .io_slave_3_aw_bits_qos(T_2710_io_slave_3_aw_bits_qos),
+ .io_slave_3_aw_bits_region(T_2710_io_slave_3_aw_bits_region),
+ .io_slave_3_aw_bits_id(T_2710_io_slave_3_aw_bits_id),
+ .io_slave_3_aw_bits_user(T_2710_io_slave_3_aw_bits_user),
+ .io_slave_3_w_ready(T_2710_io_slave_3_w_ready),
+ .io_slave_3_w_valid(T_2710_io_slave_3_w_valid),
+ .io_slave_3_w_bits_data(T_2710_io_slave_3_w_bits_data),
+ .io_slave_3_w_bits_last(T_2710_io_slave_3_w_bits_last),
+ .io_slave_3_w_bits_strb(T_2710_io_slave_3_w_bits_strb),
+ .io_slave_3_w_bits_user(T_2710_io_slave_3_w_bits_user),
+ .io_slave_3_b_ready(T_2710_io_slave_3_b_ready),
+ .io_slave_3_b_valid(T_2710_io_slave_3_b_valid),
+ .io_slave_3_b_bits_resp(T_2710_io_slave_3_b_bits_resp),
+ .io_slave_3_b_bits_id(T_2710_io_slave_3_b_bits_id),
+ .io_slave_3_b_bits_user(T_2710_io_slave_3_b_bits_user),
+ .io_slave_3_ar_ready(T_2710_io_slave_3_ar_ready),
+ .io_slave_3_ar_valid(T_2710_io_slave_3_ar_valid),
+ .io_slave_3_ar_bits_addr(T_2710_io_slave_3_ar_bits_addr),
+ .io_slave_3_ar_bits_len(T_2710_io_slave_3_ar_bits_len),
+ .io_slave_3_ar_bits_size(T_2710_io_slave_3_ar_bits_size),
+ .io_slave_3_ar_bits_burst(T_2710_io_slave_3_ar_bits_burst),
+ .io_slave_3_ar_bits_lock(T_2710_io_slave_3_ar_bits_lock),
+ .io_slave_3_ar_bits_cache(T_2710_io_slave_3_ar_bits_cache),
+ .io_slave_3_ar_bits_prot(T_2710_io_slave_3_ar_bits_prot),
+ .io_slave_3_ar_bits_qos(T_2710_io_slave_3_ar_bits_qos),
+ .io_slave_3_ar_bits_region(T_2710_io_slave_3_ar_bits_region),
+ .io_slave_3_ar_bits_id(T_2710_io_slave_3_ar_bits_id),
+ .io_slave_3_ar_bits_user(T_2710_io_slave_3_ar_bits_user),
+ .io_slave_3_r_ready(T_2710_io_slave_3_r_ready),
+ .io_slave_3_r_valid(T_2710_io_slave_3_r_valid),
+ .io_slave_3_r_bits_resp(T_2710_io_slave_3_r_bits_resp),
+ .io_slave_3_r_bits_data(T_2710_io_slave_3_r_bits_data),
+ .io_slave_3_r_bits_last(T_2710_io_slave_3_r_bits_last),
+ .io_slave_3_r_bits_id(T_2710_io_slave_3_r_bits_id),
+ .io_slave_3_r_bits_user(T_2710_io_slave_3_r_bits_user)
+ );
+ NastiRouter_39 T_2711 (
+ .clk(T_2711_clk),
+ .reset(T_2711_reset),
+ .io_master_aw_ready(T_2711_io_master_aw_ready),
+ .io_master_aw_valid(T_2711_io_master_aw_valid),
+ .io_master_aw_bits_addr(T_2711_io_master_aw_bits_addr),
+ .io_master_aw_bits_len(T_2711_io_master_aw_bits_len),
+ .io_master_aw_bits_size(T_2711_io_master_aw_bits_size),
+ .io_master_aw_bits_burst(T_2711_io_master_aw_bits_burst),
+ .io_master_aw_bits_lock(T_2711_io_master_aw_bits_lock),
+ .io_master_aw_bits_cache(T_2711_io_master_aw_bits_cache),
+ .io_master_aw_bits_prot(T_2711_io_master_aw_bits_prot),
+ .io_master_aw_bits_qos(T_2711_io_master_aw_bits_qos),
+ .io_master_aw_bits_region(T_2711_io_master_aw_bits_region),
+ .io_master_aw_bits_id(T_2711_io_master_aw_bits_id),
+ .io_master_aw_bits_user(T_2711_io_master_aw_bits_user),
+ .io_master_w_ready(T_2711_io_master_w_ready),
+ .io_master_w_valid(T_2711_io_master_w_valid),
+ .io_master_w_bits_data(T_2711_io_master_w_bits_data),
+ .io_master_w_bits_last(T_2711_io_master_w_bits_last),
+ .io_master_w_bits_strb(T_2711_io_master_w_bits_strb),
+ .io_master_w_bits_user(T_2711_io_master_w_bits_user),
+ .io_master_b_ready(T_2711_io_master_b_ready),
+ .io_master_b_valid(T_2711_io_master_b_valid),
+ .io_master_b_bits_resp(T_2711_io_master_b_bits_resp),
+ .io_master_b_bits_id(T_2711_io_master_b_bits_id),
+ .io_master_b_bits_user(T_2711_io_master_b_bits_user),
+ .io_master_ar_ready(T_2711_io_master_ar_ready),
+ .io_master_ar_valid(T_2711_io_master_ar_valid),
+ .io_master_ar_bits_addr(T_2711_io_master_ar_bits_addr),
+ .io_master_ar_bits_len(T_2711_io_master_ar_bits_len),
+ .io_master_ar_bits_size(T_2711_io_master_ar_bits_size),
+ .io_master_ar_bits_burst(T_2711_io_master_ar_bits_burst),
+ .io_master_ar_bits_lock(T_2711_io_master_ar_bits_lock),
+ .io_master_ar_bits_cache(T_2711_io_master_ar_bits_cache),
+ .io_master_ar_bits_prot(T_2711_io_master_ar_bits_prot),
+ .io_master_ar_bits_qos(T_2711_io_master_ar_bits_qos),
+ .io_master_ar_bits_region(T_2711_io_master_ar_bits_region),
+ .io_master_ar_bits_id(T_2711_io_master_ar_bits_id),
+ .io_master_ar_bits_user(T_2711_io_master_ar_bits_user),
+ .io_master_r_ready(T_2711_io_master_r_ready),
+ .io_master_r_valid(T_2711_io_master_r_valid),
+ .io_master_r_bits_resp(T_2711_io_master_r_bits_resp),
+ .io_master_r_bits_data(T_2711_io_master_r_bits_data),
+ .io_master_r_bits_last(T_2711_io_master_r_bits_last),
+ .io_master_r_bits_id(T_2711_io_master_r_bits_id),
+ .io_master_r_bits_user(T_2711_io_master_r_bits_user),
+ .io_slave_0_aw_ready(T_2711_io_slave_0_aw_ready),
+ .io_slave_0_aw_valid(T_2711_io_slave_0_aw_valid),
+ .io_slave_0_aw_bits_addr(T_2711_io_slave_0_aw_bits_addr),
+ .io_slave_0_aw_bits_len(T_2711_io_slave_0_aw_bits_len),
+ .io_slave_0_aw_bits_size(T_2711_io_slave_0_aw_bits_size),
+ .io_slave_0_aw_bits_burst(T_2711_io_slave_0_aw_bits_burst),
+ .io_slave_0_aw_bits_lock(T_2711_io_slave_0_aw_bits_lock),
+ .io_slave_0_aw_bits_cache(T_2711_io_slave_0_aw_bits_cache),
+ .io_slave_0_aw_bits_prot(T_2711_io_slave_0_aw_bits_prot),
+ .io_slave_0_aw_bits_qos(T_2711_io_slave_0_aw_bits_qos),
+ .io_slave_0_aw_bits_region(T_2711_io_slave_0_aw_bits_region),
+ .io_slave_0_aw_bits_id(T_2711_io_slave_0_aw_bits_id),
+ .io_slave_0_aw_bits_user(T_2711_io_slave_0_aw_bits_user),
+ .io_slave_0_w_ready(T_2711_io_slave_0_w_ready),
+ .io_slave_0_w_valid(T_2711_io_slave_0_w_valid),
+ .io_slave_0_w_bits_data(T_2711_io_slave_0_w_bits_data),
+ .io_slave_0_w_bits_last(T_2711_io_slave_0_w_bits_last),
+ .io_slave_0_w_bits_strb(T_2711_io_slave_0_w_bits_strb),
+ .io_slave_0_w_bits_user(T_2711_io_slave_0_w_bits_user),
+ .io_slave_0_b_ready(T_2711_io_slave_0_b_ready),
+ .io_slave_0_b_valid(T_2711_io_slave_0_b_valid),
+ .io_slave_0_b_bits_resp(T_2711_io_slave_0_b_bits_resp),
+ .io_slave_0_b_bits_id(T_2711_io_slave_0_b_bits_id),
+ .io_slave_0_b_bits_user(T_2711_io_slave_0_b_bits_user),
+ .io_slave_0_ar_ready(T_2711_io_slave_0_ar_ready),
+ .io_slave_0_ar_valid(T_2711_io_slave_0_ar_valid),
+ .io_slave_0_ar_bits_addr(T_2711_io_slave_0_ar_bits_addr),
+ .io_slave_0_ar_bits_len(T_2711_io_slave_0_ar_bits_len),
+ .io_slave_0_ar_bits_size(T_2711_io_slave_0_ar_bits_size),
+ .io_slave_0_ar_bits_burst(T_2711_io_slave_0_ar_bits_burst),
+ .io_slave_0_ar_bits_lock(T_2711_io_slave_0_ar_bits_lock),
+ .io_slave_0_ar_bits_cache(T_2711_io_slave_0_ar_bits_cache),
+ .io_slave_0_ar_bits_prot(T_2711_io_slave_0_ar_bits_prot),
+ .io_slave_0_ar_bits_qos(T_2711_io_slave_0_ar_bits_qos),
+ .io_slave_0_ar_bits_region(T_2711_io_slave_0_ar_bits_region),
+ .io_slave_0_ar_bits_id(T_2711_io_slave_0_ar_bits_id),
+ .io_slave_0_ar_bits_user(T_2711_io_slave_0_ar_bits_user),
+ .io_slave_0_r_ready(T_2711_io_slave_0_r_ready),
+ .io_slave_0_r_valid(T_2711_io_slave_0_r_valid),
+ .io_slave_0_r_bits_resp(T_2711_io_slave_0_r_bits_resp),
+ .io_slave_0_r_bits_data(T_2711_io_slave_0_r_bits_data),
+ .io_slave_0_r_bits_last(T_2711_io_slave_0_r_bits_last),
+ .io_slave_0_r_bits_id(T_2711_io_slave_0_r_bits_id),
+ .io_slave_0_r_bits_user(T_2711_io_slave_0_r_bits_user),
+ .io_slave_1_aw_ready(T_2711_io_slave_1_aw_ready),
+ .io_slave_1_aw_valid(T_2711_io_slave_1_aw_valid),
+ .io_slave_1_aw_bits_addr(T_2711_io_slave_1_aw_bits_addr),
+ .io_slave_1_aw_bits_len(T_2711_io_slave_1_aw_bits_len),
+ .io_slave_1_aw_bits_size(T_2711_io_slave_1_aw_bits_size),
+ .io_slave_1_aw_bits_burst(T_2711_io_slave_1_aw_bits_burst),
+ .io_slave_1_aw_bits_lock(T_2711_io_slave_1_aw_bits_lock),
+ .io_slave_1_aw_bits_cache(T_2711_io_slave_1_aw_bits_cache),
+ .io_slave_1_aw_bits_prot(T_2711_io_slave_1_aw_bits_prot),
+ .io_slave_1_aw_bits_qos(T_2711_io_slave_1_aw_bits_qos),
+ .io_slave_1_aw_bits_region(T_2711_io_slave_1_aw_bits_region),
+ .io_slave_1_aw_bits_id(T_2711_io_slave_1_aw_bits_id),
+ .io_slave_1_aw_bits_user(T_2711_io_slave_1_aw_bits_user),
+ .io_slave_1_w_ready(T_2711_io_slave_1_w_ready),
+ .io_slave_1_w_valid(T_2711_io_slave_1_w_valid),
+ .io_slave_1_w_bits_data(T_2711_io_slave_1_w_bits_data),
+ .io_slave_1_w_bits_last(T_2711_io_slave_1_w_bits_last),
+ .io_slave_1_w_bits_strb(T_2711_io_slave_1_w_bits_strb),
+ .io_slave_1_w_bits_user(T_2711_io_slave_1_w_bits_user),
+ .io_slave_1_b_ready(T_2711_io_slave_1_b_ready),
+ .io_slave_1_b_valid(T_2711_io_slave_1_b_valid),
+ .io_slave_1_b_bits_resp(T_2711_io_slave_1_b_bits_resp),
+ .io_slave_1_b_bits_id(T_2711_io_slave_1_b_bits_id),
+ .io_slave_1_b_bits_user(T_2711_io_slave_1_b_bits_user),
+ .io_slave_1_ar_ready(T_2711_io_slave_1_ar_ready),
+ .io_slave_1_ar_valid(T_2711_io_slave_1_ar_valid),
+ .io_slave_1_ar_bits_addr(T_2711_io_slave_1_ar_bits_addr),
+ .io_slave_1_ar_bits_len(T_2711_io_slave_1_ar_bits_len),
+ .io_slave_1_ar_bits_size(T_2711_io_slave_1_ar_bits_size),
+ .io_slave_1_ar_bits_burst(T_2711_io_slave_1_ar_bits_burst),
+ .io_slave_1_ar_bits_lock(T_2711_io_slave_1_ar_bits_lock),
+ .io_slave_1_ar_bits_cache(T_2711_io_slave_1_ar_bits_cache),
+ .io_slave_1_ar_bits_prot(T_2711_io_slave_1_ar_bits_prot),
+ .io_slave_1_ar_bits_qos(T_2711_io_slave_1_ar_bits_qos),
+ .io_slave_1_ar_bits_region(T_2711_io_slave_1_ar_bits_region),
+ .io_slave_1_ar_bits_id(T_2711_io_slave_1_ar_bits_id),
+ .io_slave_1_ar_bits_user(T_2711_io_slave_1_ar_bits_user),
+ .io_slave_1_r_ready(T_2711_io_slave_1_r_ready),
+ .io_slave_1_r_valid(T_2711_io_slave_1_r_valid),
+ .io_slave_1_r_bits_resp(T_2711_io_slave_1_r_bits_resp),
+ .io_slave_1_r_bits_data(T_2711_io_slave_1_r_bits_data),
+ .io_slave_1_r_bits_last(T_2711_io_slave_1_r_bits_last),
+ .io_slave_1_r_bits_id(T_2711_io_slave_1_r_bits_id),
+ .io_slave_1_r_bits_user(T_2711_io_slave_1_r_bits_user),
+ .io_slave_2_aw_ready(T_2711_io_slave_2_aw_ready),
+ .io_slave_2_aw_valid(T_2711_io_slave_2_aw_valid),
+ .io_slave_2_aw_bits_addr(T_2711_io_slave_2_aw_bits_addr),
+ .io_slave_2_aw_bits_len(T_2711_io_slave_2_aw_bits_len),
+ .io_slave_2_aw_bits_size(T_2711_io_slave_2_aw_bits_size),
+ .io_slave_2_aw_bits_burst(T_2711_io_slave_2_aw_bits_burst),
+ .io_slave_2_aw_bits_lock(T_2711_io_slave_2_aw_bits_lock),
+ .io_slave_2_aw_bits_cache(T_2711_io_slave_2_aw_bits_cache),
+ .io_slave_2_aw_bits_prot(T_2711_io_slave_2_aw_bits_prot),
+ .io_slave_2_aw_bits_qos(T_2711_io_slave_2_aw_bits_qos),
+ .io_slave_2_aw_bits_region(T_2711_io_slave_2_aw_bits_region),
+ .io_slave_2_aw_bits_id(T_2711_io_slave_2_aw_bits_id),
+ .io_slave_2_aw_bits_user(T_2711_io_slave_2_aw_bits_user),
+ .io_slave_2_w_ready(T_2711_io_slave_2_w_ready),
+ .io_slave_2_w_valid(T_2711_io_slave_2_w_valid),
+ .io_slave_2_w_bits_data(T_2711_io_slave_2_w_bits_data),
+ .io_slave_2_w_bits_last(T_2711_io_slave_2_w_bits_last),
+ .io_slave_2_w_bits_strb(T_2711_io_slave_2_w_bits_strb),
+ .io_slave_2_w_bits_user(T_2711_io_slave_2_w_bits_user),
+ .io_slave_2_b_ready(T_2711_io_slave_2_b_ready),
+ .io_slave_2_b_valid(T_2711_io_slave_2_b_valid),
+ .io_slave_2_b_bits_resp(T_2711_io_slave_2_b_bits_resp),
+ .io_slave_2_b_bits_id(T_2711_io_slave_2_b_bits_id),
+ .io_slave_2_b_bits_user(T_2711_io_slave_2_b_bits_user),
+ .io_slave_2_ar_ready(T_2711_io_slave_2_ar_ready),
+ .io_slave_2_ar_valid(T_2711_io_slave_2_ar_valid),
+ .io_slave_2_ar_bits_addr(T_2711_io_slave_2_ar_bits_addr),
+ .io_slave_2_ar_bits_len(T_2711_io_slave_2_ar_bits_len),
+ .io_slave_2_ar_bits_size(T_2711_io_slave_2_ar_bits_size),
+ .io_slave_2_ar_bits_burst(T_2711_io_slave_2_ar_bits_burst),
+ .io_slave_2_ar_bits_lock(T_2711_io_slave_2_ar_bits_lock),
+ .io_slave_2_ar_bits_cache(T_2711_io_slave_2_ar_bits_cache),
+ .io_slave_2_ar_bits_prot(T_2711_io_slave_2_ar_bits_prot),
+ .io_slave_2_ar_bits_qos(T_2711_io_slave_2_ar_bits_qos),
+ .io_slave_2_ar_bits_region(T_2711_io_slave_2_ar_bits_region),
+ .io_slave_2_ar_bits_id(T_2711_io_slave_2_ar_bits_id),
+ .io_slave_2_ar_bits_user(T_2711_io_slave_2_ar_bits_user),
+ .io_slave_2_r_ready(T_2711_io_slave_2_r_ready),
+ .io_slave_2_r_valid(T_2711_io_slave_2_r_valid),
+ .io_slave_2_r_bits_resp(T_2711_io_slave_2_r_bits_resp),
+ .io_slave_2_r_bits_data(T_2711_io_slave_2_r_bits_data),
+ .io_slave_2_r_bits_last(T_2711_io_slave_2_r_bits_last),
+ .io_slave_2_r_bits_id(T_2711_io_slave_2_r_bits_id),
+ .io_slave_2_r_bits_user(T_2711_io_slave_2_r_bits_user),
+ .io_slave_3_aw_ready(T_2711_io_slave_3_aw_ready),
+ .io_slave_3_aw_valid(T_2711_io_slave_3_aw_valid),
+ .io_slave_3_aw_bits_addr(T_2711_io_slave_3_aw_bits_addr),
+ .io_slave_3_aw_bits_len(T_2711_io_slave_3_aw_bits_len),
+ .io_slave_3_aw_bits_size(T_2711_io_slave_3_aw_bits_size),
+ .io_slave_3_aw_bits_burst(T_2711_io_slave_3_aw_bits_burst),
+ .io_slave_3_aw_bits_lock(T_2711_io_slave_3_aw_bits_lock),
+ .io_slave_3_aw_bits_cache(T_2711_io_slave_3_aw_bits_cache),
+ .io_slave_3_aw_bits_prot(T_2711_io_slave_3_aw_bits_prot),
+ .io_slave_3_aw_bits_qos(T_2711_io_slave_3_aw_bits_qos),
+ .io_slave_3_aw_bits_region(T_2711_io_slave_3_aw_bits_region),
+ .io_slave_3_aw_bits_id(T_2711_io_slave_3_aw_bits_id),
+ .io_slave_3_aw_bits_user(T_2711_io_slave_3_aw_bits_user),
+ .io_slave_3_w_ready(T_2711_io_slave_3_w_ready),
+ .io_slave_3_w_valid(T_2711_io_slave_3_w_valid),
+ .io_slave_3_w_bits_data(T_2711_io_slave_3_w_bits_data),
+ .io_slave_3_w_bits_last(T_2711_io_slave_3_w_bits_last),
+ .io_slave_3_w_bits_strb(T_2711_io_slave_3_w_bits_strb),
+ .io_slave_3_w_bits_user(T_2711_io_slave_3_w_bits_user),
+ .io_slave_3_b_ready(T_2711_io_slave_3_b_ready),
+ .io_slave_3_b_valid(T_2711_io_slave_3_b_valid),
+ .io_slave_3_b_bits_resp(T_2711_io_slave_3_b_bits_resp),
+ .io_slave_3_b_bits_id(T_2711_io_slave_3_b_bits_id),
+ .io_slave_3_b_bits_user(T_2711_io_slave_3_b_bits_user),
+ .io_slave_3_ar_ready(T_2711_io_slave_3_ar_ready),
+ .io_slave_3_ar_valid(T_2711_io_slave_3_ar_valid),
+ .io_slave_3_ar_bits_addr(T_2711_io_slave_3_ar_bits_addr),
+ .io_slave_3_ar_bits_len(T_2711_io_slave_3_ar_bits_len),
+ .io_slave_3_ar_bits_size(T_2711_io_slave_3_ar_bits_size),
+ .io_slave_3_ar_bits_burst(T_2711_io_slave_3_ar_bits_burst),
+ .io_slave_3_ar_bits_lock(T_2711_io_slave_3_ar_bits_lock),
+ .io_slave_3_ar_bits_cache(T_2711_io_slave_3_ar_bits_cache),
+ .io_slave_3_ar_bits_prot(T_2711_io_slave_3_ar_bits_prot),
+ .io_slave_3_ar_bits_qos(T_2711_io_slave_3_ar_bits_qos),
+ .io_slave_3_ar_bits_region(T_2711_io_slave_3_ar_bits_region),
+ .io_slave_3_ar_bits_id(T_2711_io_slave_3_ar_bits_id),
+ .io_slave_3_ar_bits_user(T_2711_io_slave_3_ar_bits_user),
+ .io_slave_3_r_ready(T_2711_io_slave_3_r_ready),
+ .io_slave_3_r_valid(T_2711_io_slave_3_r_valid),
+ .io_slave_3_r_bits_resp(T_2711_io_slave_3_r_bits_resp),
+ .io_slave_3_r_bits_data(T_2711_io_slave_3_r_bits_data),
+ .io_slave_3_r_bits_last(T_2711_io_slave_3_r_bits_last),
+ .io_slave_3_r_bits_id(T_2711_io_slave_3_r_bits_id),
+ .io_slave_3_r_bits_user(T_2711_io_slave_3_r_bits_user)
+ );
+ NastiArbiter T_8449 (
+ .clk(T_8449_clk),
+ .reset(T_8449_reset),
+ .io_master_0_aw_ready(T_8449_io_master_0_aw_ready),
+ .io_master_0_aw_valid(T_8449_io_master_0_aw_valid),
+ .io_master_0_aw_bits_addr(T_8449_io_master_0_aw_bits_addr),
+ .io_master_0_aw_bits_len(T_8449_io_master_0_aw_bits_len),
+ .io_master_0_aw_bits_size(T_8449_io_master_0_aw_bits_size),
+ .io_master_0_aw_bits_burst(T_8449_io_master_0_aw_bits_burst),
+ .io_master_0_aw_bits_lock(T_8449_io_master_0_aw_bits_lock),
+ .io_master_0_aw_bits_cache(T_8449_io_master_0_aw_bits_cache),
+ .io_master_0_aw_bits_prot(T_8449_io_master_0_aw_bits_prot),
+ .io_master_0_aw_bits_qos(T_8449_io_master_0_aw_bits_qos),
+ .io_master_0_aw_bits_region(T_8449_io_master_0_aw_bits_region),
+ .io_master_0_aw_bits_id(T_8449_io_master_0_aw_bits_id),
+ .io_master_0_aw_bits_user(T_8449_io_master_0_aw_bits_user),
+ .io_master_0_w_ready(T_8449_io_master_0_w_ready),
+ .io_master_0_w_valid(T_8449_io_master_0_w_valid),
+ .io_master_0_w_bits_data(T_8449_io_master_0_w_bits_data),
+ .io_master_0_w_bits_last(T_8449_io_master_0_w_bits_last),
+ .io_master_0_w_bits_strb(T_8449_io_master_0_w_bits_strb),
+ .io_master_0_w_bits_user(T_8449_io_master_0_w_bits_user),
+ .io_master_0_b_ready(T_8449_io_master_0_b_ready),
+ .io_master_0_b_valid(T_8449_io_master_0_b_valid),
+ .io_master_0_b_bits_resp(T_8449_io_master_0_b_bits_resp),
+ .io_master_0_b_bits_id(T_8449_io_master_0_b_bits_id),
+ .io_master_0_b_bits_user(T_8449_io_master_0_b_bits_user),
+ .io_master_0_ar_ready(T_8449_io_master_0_ar_ready),
+ .io_master_0_ar_valid(T_8449_io_master_0_ar_valid),
+ .io_master_0_ar_bits_addr(T_8449_io_master_0_ar_bits_addr),
+ .io_master_0_ar_bits_len(T_8449_io_master_0_ar_bits_len),
+ .io_master_0_ar_bits_size(T_8449_io_master_0_ar_bits_size),
+ .io_master_0_ar_bits_burst(T_8449_io_master_0_ar_bits_burst),
+ .io_master_0_ar_bits_lock(T_8449_io_master_0_ar_bits_lock),
+ .io_master_0_ar_bits_cache(T_8449_io_master_0_ar_bits_cache),
+ .io_master_0_ar_bits_prot(T_8449_io_master_0_ar_bits_prot),
+ .io_master_0_ar_bits_qos(T_8449_io_master_0_ar_bits_qos),
+ .io_master_0_ar_bits_region(T_8449_io_master_0_ar_bits_region),
+ .io_master_0_ar_bits_id(T_8449_io_master_0_ar_bits_id),
+ .io_master_0_ar_bits_user(T_8449_io_master_0_ar_bits_user),
+ .io_master_0_r_ready(T_8449_io_master_0_r_ready),
+ .io_master_0_r_valid(T_8449_io_master_0_r_valid),
+ .io_master_0_r_bits_resp(T_8449_io_master_0_r_bits_resp),
+ .io_master_0_r_bits_data(T_8449_io_master_0_r_bits_data),
+ .io_master_0_r_bits_last(T_8449_io_master_0_r_bits_last),
+ .io_master_0_r_bits_id(T_8449_io_master_0_r_bits_id),
+ .io_master_0_r_bits_user(T_8449_io_master_0_r_bits_user),
+ .io_master_1_aw_ready(T_8449_io_master_1_aw_ready),
+ .io_master_1_aw_valid(T_8449_io_master_1_aw_valid),
+ .io_master_1_aw_bits_addr(T_8449_io_master_1_aw_bits_addr),
+ .io_master_1_aw_bits_len(T_8449_io_master_1_aw_bits_len),
+ .io_master_1_aw_bits_size(T_8449_io_master_1_aw_bits_size),
+ .io_master_1_aw_bits_burst(T_8449_io_master_1_aw_bits_burst),
+ .io_master_1_aw_bits_lock(T_8449_io_master_1_aw_bits_lock),
+ .io_master_1_aw_bits_cache(T_8449_io_master_1_aw_bits_cache),
+ .io_master_1_aw_bits_prot(T_8449_io_master_1_aw_bits_prot),
+ .io_master_1_aw_bits_qos(T_8449_io_master_1_aw_bits_qos),
+ .io_master_1_aw_bits_region(T_8449_io_master_1_aw_bits_region),
+ .io_master_1_aw_bits_id(T_8449_io_master_1_aw_bits_id),
+ .io_master_1_aw_bits_user(T_8449_io_master_1_aw_bits_user),
+ .io_master_1_w_ready(T_8449_io_master_1_w_ready),
+ .io_master_1_w_valid(T_8449_io_master_1_w_valid),
+ .io_master_1_w_bits_data(T_8449_io_master_1_w_bits_data),
+ .io_master_1_w_bits_last(T_8449_io_master_1_w_bits_last),
+ .io_master_1_w_bits_strb(T_8449_io_master_1_w_bits_strb),
+ .io_master_1_w_bits_user(T_8449_io_master_1_w_bits_user),
+ .io_master_1_b_ready(T_8449_io_master_1_b_ready),
+ .io_master_1_b_valid(T_8449_io_master_1_b_valid),
+ .io_master_1_b_bits_resp(T_8449_io_master_1_b_bits_resp),
+ .io_master_1_b_bits_id(T_8449_io_master_1_b_bits_id),
+ .io_master_1_b_bits_user(T_8449_io_master_1_b_bits_user),
+ .io_master_1_ar_ready(T_8449_io_master_1_ar_ready),
+ .io_master_1_ar_valid(T_8449_io_master_1_ar_valid),
+ .io_master_1_ar_bits_addr(T_8449_io_master_1_ar_bits_addr),
+ .io_master_1_ar_bits_len(T_8449_io_master_1_ar_bits_len),
+ .io_master_1_ar_bits_size(T_8449_io_master_1_ar_bits_size),
+ .io_master_1_ar_bits_burst(T_8449_io_master_1_ar_bits_burst),
+ .io_master_1_ar_bits_lock(T_8449_io_master_1_ar_bits_lock),
+ .io_master_1_ar_bits_cache(T_8449_io_master_1_ar_bits_cache),
+ .io_master_1_ar_bits_prot(T_8449_io_master_1_ar_bits_prot),
+ .io_master_1_ar_bits_qos(T_8449_io_master_1_ar_bits_qos),
+ .io_master_1_ar_bits_region(T_8449_io_master_1_ar_bits_region),
+ .io_master_1_ar_bits_id(T_8449_io_master_1_ar_bits_id),
+ .io_master_1_ar_bits_user(T_8449_io_master_1_ar_bits_user),
+ .io_master_1_r_ready(T_8449_io_master_1_r_ready),
+ .io_master_1_r_valid(T_8449_io_master_1_r_valid),
+ .io_master_1_r_bits_resp(T_8449_io_master_1_r_bits_resp),
+ .io_master_1_r_bits_data(T_8449_io_master_1_r_bits_data),
+ .io_master_1_r_bits_last(T_8449_io_master_1_r_bits_last),
+ .io_master_1_r_bits_id(T_8449_io_master_1_r_bits_id),
+ .io_master_1_r_bits_user(T_8449_io_master_1_r_bits_user),
+ .io_slave_aw_ready(T_8449_io_slave_aw_ready),
+ .io_slave_aw_valid(T_8449_io_slave_aw_valid),
+ .io_slave_aw_bits_addr(T_8449_io_slave_aw_bits_addr),
+ .io_slave_aw_bits_len(T_8449_io_slave_aw_bits_len),
+ .io_slave_aw_bits_size(T_8449_io_slave_aw_bits_size),
+ .io_slave_aw_bits_burst(T_8449_io_slave_aw_bits_burst),
+ .io_slave_aw_bits_lock(T_8449_io_slave_aw_bits_lock),
+ .io_slave_aw_bits_cache(T_8449_io_slave_aw_bits_cache),
+ .io_slave_aw_bits_prot(T_8449_io_slave_aw_bits_prot),
+ .io_slave_aw_bits_qos(T_8449_io_slave_aw_bits_qos),
+ .io_slave_aw_bits_region(T_8449_io_slave_aw_bits_region),
+ .io_slave_aw_bits_id(T_8449_io_slave_aw_bits_id),
+ .io_slave_aw_bits_user(T_8449_io_slave_aw_bits_user),
+ .io_slave_w_ready(T_8449_io_slave_w_ready),
+ .io_slave_w_valid(T_8449_io_slave_w_valid),
+ .io_slave_w_bits_data(T_8449_io_slave_w_bits_data),
+ .io_slave_w_bits_last(T_8449_io_slave_w_bits_last),
+ .io_slave_w_bits_strb(T_8449_io_slave_w_bits_strb),
+ .io_slave_w_bits_user(T_8449_io_slave_w_bits_user),
+ .io_slave_b_ready(T_8449_io_slave_b_ready),
+ .io_slave_b_valid(T_8449_io_slave_b_valid),
+ .io_slave_b_bits_resp(T_8449_io_slave_b_bits_resp),
+ .io_slave_b_bits_id(T_8449_io_slave_b_bits_id),
+ .io_slave_b_bits_user(T_8449_io_slave_b_bits_user),
+ .io_slave_ar_ready(T_8449_io_slave_ar_ready),
+ .io_slave_ar_valid(T_8449_io_slave_ar_valid),
+ .io_slave_ar_bits_addr(T_8449_io_slave_ar_bits_addr),
+ .io_slave_ar_bits_len(T_8449_io_slave_ar_bits_len),
+ .io_slave_ar_bits_size(T_8449_io_slave_ar_bits_size),
+ .io_slave_ar_bits_burst(T_8449_io_slave_ar_bits_burst),
+ .io_slave_ar_bits_lock(T_8449_io_slave_ar_bits_lock),
+ .io_slave_ar_bits_cache(T_8449_io_slave_ar_bits_cache),
+ .io_slave_ar_bits_prot(T_8449_io_slave_ar_bits_prot),
+ .io_slave_ar_bits_qos(T_8449_io_slave_ar_bits_qos),
+ .io_slave_ar_bits_region(T_8449_io_slave_ar_bits_region),
+ .io_slave_ar_bits_id(T_8449_io_slave_ar_bits_id),
+ .io_slave_ar_bits_user(T_8449_io_slave_ar_bits_user),
+ .io_slave_r_ready(T_8449_io_slave_r_ready),
+ .io_slave_r_valid(T_8449_io_slave_r_valid),
+ .io_slave_r_bits_resp(T_8449_io_slave_r_bits_resp),
+ .io_slave_r_bits_data(T_8449_io_slave_r_bits_data),
+ .io_slave_r_bits_last(T_8449_io_slave_r_bits_last),
+ .io_slave_r_bits_id(T_8449_io_slave_r_bits_id),
+ .io_slave_r_bits_user(T_8449_io_slave_r_bits_user)
+ );
+ NastiArbiter T_8450 (
+ .clk(T_8450_clk),
+ .reset(T_8450_reset),
+ .io_master_0_aw_ready(T_8450_io_master_0_aw_ready),
+ .io_master_0_aw_valid(T_8450_io_master_0_aw_valid),
+ .io_master_0_aw_bits_addr(T_8450_io_master_0_aw_bits_addr),
+ .io_master_0_aw_bits_len(T_8450_io_master_0_aw_bits_len),
+ .io_master_0_aw_bits_size(T_8450_io_master_0_aw_bits_size),
+ .io_master_0_aw_bits_burst(T_8450_io_master_0_aw_bits_burst),
+ .io_master_0_aw_bits_lock(T_8450_io_master_0_aw_bits_lock),
+ .io_master_0_aw_bits_cache(T_8450_io_master_0_aw_bits_cache),
+ .io_master_0_aw_bits_prot(T_8450_io_master_0_aw_bits_prot),
+ .io_master_0_aw_bits_qos(T_8450_io_master_0_aw_bits_qos),
+ .io_master_0_aw_bits_region(T_8450_io_master_0_aw_bits_region),
+ .io_master_0_aw_bits_id(T_8450_io_master_0_aw_bits_id),
+ .io_master_0_aw_bits_user(T_8450_io_master_0_aw_bits_user),
+ .io_master_0_w_ready(T_8450_io_master_0_w_ready),
+ .io_master_0_w_valid(T_8450_io_master_0_w_valid),
+ .io_master_0_w_bits_data(T_8450_io_master_0_w_bits_data),
+ .io_master_0_w_bits_last(T_8450_io_master_0_w_bits_last),
+ .io_master_0_w_bits_strb(T_8450_io_master_0_w_bits_strb),
+ .io_master_0_w_bits_user(T_8450_io_master_0_w_bits_user),
+ .io_master_0_b_ready(T_8450_io_master_0_b_ready),
+ .io_master_0_b_valid(T_8450_io_master_0_b_valid),
+ .io_master_0_b_bits_resp(T_8450_io_master_0_b_bits_resp),
+ .io_master_0_b_bits_id(T_8450_io_master_0_b_bits_id),
+ .io_master_0_b_bits_user(T_8450_io_master_0_b_bits_user),
+ .io_master_0_ar_ready(T_8450_io_master_0_ar_ready),
+ .io_master_0_ar_valid(T_8450_io_master_0_ar_valid),
+ .io_master_0_ar_bits_addr(T_8450_io_master_0_ar_bits_addr),
+ .io_master_0_ar_bits_len(T_8450_io_master_0_ar_bits_len),
+ .io_master_0_ar_bits_size(T_8450_io_master_0_ar_bits_size),
+ .io_master_0_ar_bits_burst(T_8450_io_master_0_ar_bits_burst),
+ .io_master_0_ar_bits_lock(T_8450_io_master_0_ar_bits_lock),
+ .io_master_0_ar_bits_cache(T_8450_io_master_0_ar_bits_cache),
+ .io_master_0_ar_bits_prot(T_8450_io_master_0_ar_bits_prot),
+ .io_master_0_ar_bits_qos(T_8450_io_master_0_ar_bits_qos),
+ .io_master_0_ar_bits_region(T_8450_io_master_0_ar_bits_region),
+ .io_master_0_ar_bits_id(T_8450_io_master_0_ar_bits_id),
+ .io_master_0_ar_bits_user(T_8450_io_master_0_ar_bits_user),
+ .io_master_0_r_ready(T_8450_io_master_0_r_ready),
+ .io_master_0_r_valid(T_8450_io_master_0_r_valid),
+ .io_master_0_r_bits_resp(T_8450_io_master_0_r_bits_resp),
+ .io_master_0_r_bits_data(T_8450_io_master_0_r_bits_data),
+ .io_master_0_r_bits_last(T_8450_io_master_0_r_bits_last),
+ .io_master_0_r_bits_id(T_8450_io_master_0_r_bits_id),
+ .io_master_0_r_bits_user(T_8450_io_master_0_r_bits_user),
+ .io_master_1_aw_ready(T_8450_io_master_1_aw_ready),
+ .io_master_1_aw_valid(T_8450_io_master_1_aw_valid),
+ .io_master_1_aw_bits_addr(T_8450_io_master_1_aw_bits_addr),
+ .io_master_1_aw_bits_len(T_8450_io_master_1_aw_bits_len),
+ .io_master_1_aw_bits_size(T_8450_io_master_1_aw_bits_size),
+ .io_master_1_aw_bits_burst(T_8450_io_master_1_aw_bits_burst),
+ .io_master_1_aw_bits_lock(T_8450_io_master_1_aw_bits_lock),
+ .io_master_1_aw_bits_cache(T_8450_io_master_1_aw_bits_cache),
+ .io_master_1_aw_bits_prot(T_8450_io_master_1_aw_bits_prot),
+ .io_master_1_aw_bits_qos(T_8450_io_master_1_aw_bits_qos),
+ .io_master_1_aw_bits_region(T_8450_io_master_1_aw_bits_region),
+ .io_master_1_aw_bits_id(T_8450_io_master_1_aw_bits_id),
+ .io_master_1_aw_bits_user(T_8450_io_master_1_aw_bits_user),
+ .io_master_1_w_ready(T_8450_io_master_1_w_ready),
+ .io_master_1_w_valid(T_8450_io_master_1_w_valid),
+ .io_master_1_w_bits_data(T_8450_io_master_1_w_bits_data),
+ .io_master_1_w_bits_last(T_8450_io_master_1_w_bits_last),
+ .io_master_1_w_bits_strb(T_8450_io_master_1_w_bits_strb),
+ .io_master_1_w_bits_user(T_8450_io_master_1_w_bits_user),
+ .io_master_1_b_ready(T_8450_io_master_1_b_ready),
+ .io_master_1_b_valid(T_8450_io_master_1_b_valid),
+ .io_master_1_b_bits_resp(T_8450_io_master_1_b_bits_resp),
+ .io_master_1_b_bits_id(T_8450_io_master_1_b_bits_id),
+ .io_master_1_b_bits_user(T_8450_io_master_1_b_bits_user),
+ .io_master_1_ar_ready(T_8450_io_master_1_ar_ready),
+ .io_master_1_ar_valid(T_8450_io_master_1_ar_valid),
+ .io_master_1_ar_bits_addr(T_8450_io_master_1_ar_bits_addr),
+ .io_master_1_ar_bits_len(T_8450_io_master_1_ar_bits_len),
+ .io_master_1_ar_bits_size(T_8450_io_master_1_ar_bits_size),
+ .io_master_1_ar_bits_burst(T_8450_io_master_1_ar_bits_burst),
+ .io_master_1_ar_bits_lock(T_8450_io_master_1_ar_bits_lock),
+ .io_master_1_ar_bits_cache(T_8450_io_master_1_ar_bits_cache),
+ .io_master_1_ar_bits_prot(T_8450_io_master_1_ar_bits_prot),
+ .io_master_1_ar_bits_qos(T_8450_io_master_1_ar_bits_qos),
+ .io_master_1_ar_bits_region(T_8450_io_master_1_ar_bits_region),
+ .io_master_1_ar_bits_id(T_8450_io_master_1_ar_bits_id),
+ .io_master_1_ar_bits_user(T_8450_io_master_1_ar_bits_user),
+ .io_master_1_r_ready(T_8450_io_master_1_r_ready),
+ .io_master_1_r_valid(T_8450_io_master_1_r_valid),
+ .io_master_1_r_bits_resp(T_8450_io_master_1_r_bits_resp),
+ .io_master_1_r_bits_data(T_8450_io_master_1_r_bits_data),
+ .io_master_1_r_bits_last(T_8450_io_master_1_r_bits_last),
+ .io_master_1_r_bits_id(T_8450_io_master_1_r_bits_id),
+ .io_master_1_r_bits_user(T_8450_io_master_1_r_bits_user),
+ .io_slave_aw_ready(T_8450_io_slave_aw_ready),
+ .io_slave_aw_valid(T_8450_io_slave_aw_valid),
+ .io_slave_aw_bits_addr(T_8450_io_slave_aw_bits_addr),
+ .io_slave_aw_bits_len(T_8450_io_slave_aw_bits_len),
+ .io_slave_aw_bits_size(T_8450_io_slave_aw_bits_size),
+ .io_slave_aw_bits_burst(T_8450_io_slave_aw_bits_burst),
+ .io_slave_aw_bits_lock(T_8450_io_slave_aw_bits_lock),
+ .io_slave_aw_bits_cache(T_8450_io_slave_aw_bits_cache),
+ .io_slave_aw_bits_prot(T_8450_io_slave_aw_bits_prot),
+ .io_slave_aw_bits_qos(T_8450_io_slave_aw_bits_qos),
+ .io_slave_aw_bits_region(T_8450_io_slave_aw_bits_region),
+ .io_slave_aw_bits_id(T_8450_io_slave_aw_bits_id),
+ .io_slave_aw_bits_user(T_8450_io_slave_aw_bits_user),
+ .io_slave_w_ready(T_8450_io_slave_w_ready),
+ .io_slave_w_valid(T_8450_io_slave_w_valid),
+ .io_slave_w_bits_data(T_8450_io_slave_w_bits_data),
+ .io_slave_w_bits_last(T_8450_io_slave_w_bits_last),
+ .io_slave_w_bits_strb(T_8450_io_slave_w_bits_strb),
+ .io_slave_w_bits_user(T_8450_io_slave_w_bits_user),
+ .io_slave_b_ready(T_8450_io_slave_b_ready),
+ .io_slave_b_valid(T_8450_io_slave_b_valid),
+ .io_slave_b_bits_resp(T_8450_io_slave_b_bits_resp),
+ .io_slave_b_bits_id(T_8450_io_slave_b_bits_id),
+ .io_slave_b_bits_user(T_8450_io_slave_b_bits_user),
+ .io_slave_ar_ready(T_8450_io_slave_ar_ready),
+ .io_slave_ar_valid(T_8450_io_slave_ar_valid),
+ .io_slave_ar_bits_addr(T_8450_io_slave_ar_bits_addr),
+ .io_slave_ar_bits_len(T_8450_io_slave_ar_bits_len),
+ .io_slave_ar_bits_size(T_8450_io_slave_ar_bits_size),
+ .io_slave_ar_bits_burst(T_8450_io_slave_ar_bits_burst),
+ .io_slave_ar_bits_lock(T_8450_io_slave_ar_bits_lock),
+ .io_slave_ar_bits_cache(T_8450_io_slave_ar_bits_cache),
+ .io_slave_ar_bits_prot(T_8450_io_slave_ar_bits_prot),
+ .io_slave_ar_bits_qos(T_8450_io_slave_ar_bits_qos),
+ .io_slave_ar_bits_region(T_8450_io_slave_ar_bits_region),
+ .io_slave_ar_bits_id(T_8450_io_slave_ar_bits_id),
+ .io_slave_ar_bits_user(T_8450_io_slave_ar_bits_user),
+ .io_slave_r_ready(T_8450_io_slave_r_ready),
+ .io_slave_r_valid(T_8450_io_slave_r_valid),
+ .io_slave_r_bits_resp(T_8450_io_slave_r_bits_resp),
+ .io_slave_r_bits_data(T_8450_io_slave_r_bits_data),
+ .io_slave_r_bits_last(T_8450_io_slave_r_bits_last),
+ .io_slave_r_bits_id(T_8450_io_slave_r_bits_id),
+ .io_slave_r_bits_user(T_8450_io_slave_r_bits_user)
+ );
+ NastiArbiter T_8451 (
+ .clk(T_8451_clk),
+ .reset(T_8451_reset),
+ .io_master_0_aw_ready(T_8451_io_master_0_aw_ready),
+ .io_master_0_aw_valid(T_8451_io_master_0_aw_valid),
+ .io_master_0_aw_bits_addr(T_8451_io_master_0_aw_bits_addr),
+ .io_master_0_aw_bits_len(T_8451_io_master_0_aw_bits_len),
+ .io_master_0_aw_bits_size(T_8451_io_master_0_aw_bits_size),
+ .io_master_0_aw_bits_burst(T_8451_io_master_0_aw_bits_burst),
+ .io_master_0_aw_bits_lock(T_8451_io_master_0_aw_bits_lock),
+ .io_master_0_aw_bits_cache(T_8451_io_master_0_aw_bits_cache),
+ .io_master_0_aw_bits_prot(T_8451_io_master_0_aw_bits_prot),
+ .io_master_0_aw_bits_qos(T_8451_io_master_0_aw_bits_qos),
+ .io_master_0_aw_bits_region(T_8451_io_master_0_aw_bits_region),
+ .io_master_0_aw_bits_id(T_8451_io_master_0_aw_bits_id),
+ .io_master_0_aw_bits_user(T_8451_io_master_0_aw_bits_user),
+ .io_master_0_w_ready(T_8451_io_master_0_w_ready),
+ .io_master_0_w_valid(T_8451_io_master_0_w_valid),
+ .io_master_0_w_bits_data(T_8451_io_master_0_w_bits_data),
+ .io_master_0_w_bits_last(T_8451_io_master_0_w_bits_last),
+ .io_master_0_w_bits_strb(T_8451_io_master_0_w_bits_strb),
+ .io_master_0_w_bits_user(T_8451_io_master_0_w_bits_user),
+ .io_master_0_b_ready(T_8451_io_master_0_b_ready),
+ .io_master_0_b_valid(T_8451_io_master_0_b_valid),
+ .io_master_0_b_bits_resp(T_8451_io_master_0_b_bits_resp),
+ .io_master_0_b_bits_id(T_8451_io_master_0_b_bits_id),
+ .io_master_0_b_bits_user(T_8451_io_master_0_b_bits_user),
+ .io_master_0_ar_ready(T_8451_io_master_0_ar_ready),
+ .io_master_0_ar_valid(T_8451_io_master_0_ar_valid),
+ .io_master_0_ar_bits_addr(T_8451_io_master_0_ar_bits_addr),
+ .io_master_0_ar_bits_len(T_8451_io_master_0_ar_bits_len),
+ .io_master_0_ar_bits_size(T_8451_io_master_0_ar_bits_size),
+ .io_master_0_ar_bits_burst(T_8451_io_master_0_ar_bits_burst),
+ .io_master_0_ar_bits_lock(T_8451_io_master_0_ar_bits_lock),
+ .io_master_0_ar_bits_cache(T_8451_io_master_0_ar_bits_cache),
+ .io_master_0_ar_bits_prot(T_8451_io_master_0_ar_bits_prot),
+ .io_master_0_ar_bits_qos(T_8451_io_master_0_ar_bits_qos),
+ .io_master_0_ar_bits_region(T_8451_io_master_0_ar_bits_region),
+ .io_master_0_ar_bits_id(T_8451_io_master_0_ar_bits_id),
+ .io_master_0_ar_bits_user(T_8451_io_master_0_ar_bits_user),
+ .io_master_0_r_ready(T_8451_io_master_0_r_ready),
+ .io_master_0_r_valid(T_8451_io_master_0_r_valid),
+ .io_master_0_r_bits_resp(T_8451_io_master_0_r_bits_resp),
+ .io_master_0_r_bits_data(T_8451_io_master_0_r_bits_data),
+ .io_master_0_r_bits_last(T_8451_io_master_0_r_bits_last),
+ .io_master_0_r_bits_id(T_8451_io_master_0_r_bits_id),
+ .io_master_0_r_bits_user(T_8451_io_master_0_r_bits_user),
+ .io_master_1_aw_ready(T_8451_io_master_1_aw_ready),
+ .io_master_1_aw_valid(T_8451_io_master_1_aw_valid),
+ .io_master_1_aw_bits_addr(T_8451_io_master_1_aw_bits_addr),
+ .io_master_1_aw_bits_len(T_8451_io_master_1_aw_bits_len),
+ .io_master_1_aw_bits_size(T_8451_io_master_1_aw_bits_size),
+ .io_master_1_aw_bits_burst(T_8451_io_master_1_aw_bits_burst),
+ .io_master_1_aw_bits_lock(T_8451_io_master_1_aw_bits_lock),
+ .io_master_1_aw_bits_cache(T_8451_io_master_1_aw_bits_cache),
+ .io_master_1_aw_bits_prot(T_8451_io_master_1_aw_bits_prot),
+ .io_master_1_aw_bits_qos(T_8451_io_master_1_aw_bits_qos),
+ .io_master_1_aw_bits_region(T_8451_io_master_1_aw_bits_region),
+ .io_master_1_aw_bits_id(T_8451_io_master_1_aw_bits_id),
+ .io_master_1_aw_bits_user(T_8451_io_master_1_aw_bits_user),
+ .io_master_1_w_ready(T_8451_io_master_1_w_ready),
+ .io_master_1_w_valid(T_8451_io_master_1_w_valid),
+ .io_master_1_w_bits_data(T_8451_io_master_1_w_bits_data),
+ .io_master_1_w_bits_last(T_8451_io_master_1_w_bits_last),
+ .io_master_1_w_bits_strb(T_8451_io_master_1_w_bits_strb),
+ .io_master_1_w_bits_user(T_8451_io_master_1_w_bits_user),
+ .io_master_1_b_ready(T_8451_io_master_1_b_ready),
+ .io_master_1_b_valid(T_8451_io_master_1_b_valid),
+ .io_master_1_b_bits_resp(T_8451_io_master_1_b_bits_resp),
+ .io_master_1_b_bits_id(T_8451_io_master_1_b_bits_id),
+ .io_master_1_b_bits_user(T_8451_io_master_1_b_bits_user),
+ .io_master_1_ar_ready(T_8451_io_master_1_ar_ready),
+ .io_master_1_ar_valid(T_8451_io_master_1_ar_valid),
+ .io_master_1_ar_bits_addr(T_8451_io_master_1_ar_bits_addr),
+ .io_master_1_ar_bits_len(T_8451_io_master_1_ar_bits_len),
+ .io_master_1_ar_bits_size(T_8451_io_master_1_ar_bits_size),
+ .io_master_1_ar_bits_burst(T_8451_io_master_1_ar_bits_burst),
+ .io_master_1_ar_bits_lock(T_8451_io_master_1_ar_bits_lock),
+ .io_master_1_ar_bits_cache(T_8451_io_master_1_ar_bits_cache),
+ .io_master_1_ar_bits_prot(T_8451_io_master_1_ar_bits_prot),
+ .io_master_1_ar_bits_qos(T_8451_io_master_1_ar_bits_qos),
+ .io_master_1_ar_bits_region(T_8451_io_master_1_ar_bits_region),
+ .io_master_1_ar_bits_id(T_8451_io_master_1_ar_bits_id),
+ .io_master_1_ar_bits_user(T_8451_io_master_1_ar_bits_user),
+ .io_master_1_r_ready(T_8451_io_master_1_r_ready),
+ .io_master_1_r_valid(T_8451_io_master_1_r_valid),
+ .io_master_1_r_bits_resp(T_8451_io_master_1_r_bits_resp),
+ .io_master_1_r_bits_data(T_8451_io_master_1_r_bits_data),
+ .io_master_1_r_bits_last(T_8451_io_master_1_r_bits_last),
+ .io_master_1_r_bits_id(T_8451_io_master_1_r_bits_id),
+ .io_master_1_r_bits_user(T_8451_io_master_1_r_bits_user),
+ .io_slave_aw_ready(T_8451_io_slave_aw_ready),
+ .io_slave_aw_valid(T_8451_io_slave_aw_valid),
+ .io_slave_aw_bits_addr(T_8451_io_slave_aw_bits_addr),
+ .io_slave_aw_bits_len(T_8451_io_slave_aw_bits_len),
+ .io_slave_aw_bits_size(T_8451_io_slave_aw_bits_size),
+ .io_slave_aw_bits_burst(T_8451_io_slave_aw_bits_burst),
+ .io_slave_aw_bits_lock(T_8451_io_slave_aw_bits_lock),
+ .io_slave_aw_bits_cache(T_8451_io_slave_aw_bits_cache),
+ .io_slave_aw_bits_prot(T_8451_io_slave_aw_bits_prot),
+ .io_slave_aw_bits_qos(T_8451_io_slave_aw_bits_qos),
+ .io_slave_aw_bits_region(T_8451_io_slave_aw_bits_region),
+ .io_slave_aw_bits_id(T_8451_io_slave_aw_bits_id),
+ .io_slave_aw_bits_user(T_8451_io_slave_aw_bits_user),
+ .io_slave_w_ready(T_8451_io_slave_w_ready),
+ .io_slave_w_valid(T_8451_io_slave_w_valid),
+ .io_slave_w_bits_data(T_8451_io_slave_w_bits_data),
+ .io_slave_w_bits_last(T_8451_io_slave_w_bits_last),
+ .io_slave_w_bits_strb(T_8451_io_slave_w_bits_strb),
+ .io_slave_w_bits_user(T_8451_io_slave_w_bits_user),
+ .io_slave_b_ready(T_8451_io_slave_b_ready),
+ .io_slave_b_valid(T_8451_io_slave_b_valid),
+ .io_slave_b_bits_resp(T_8451_io_slave_b_bits_resp),
+ .io_slave_b_bits_id(T_8451_io_slave_b_bits_id),
+ .io_slave_b_bits_user(T_8451_io_slave_b_bits_user),
+ .io_slave_ar_ready(T_8451_io_slave_ar_ready),
+ .io_slave_ar_valid(T_8451_io_slave_ar_valid),
+ .io_slave_ar_bits_addr(T_8451_io_slave_ar_bits_addr),
+ .io_slave_ar_bits_len(T_8451_io_slave_ar_bits_len),
+ .io_slave_ar_bits_size(T_8451_io_slave_ar_bits_size),
+ .io_slave_ar_bits_burst(T_8451_io_slave_ar_bits_burst),
+ .io_slave_ar_bits_lock(T_8451_io_slave_ar_bits_lock),
+ .io_slave_ar_bits_cache(T_8451_io_slave_ar_bits_cache),
+ .io_slave_ar_bits_prot(T_8451_io_slave_ar_bits_prot),
+ .io_slave_ar_bits_qos(T_8451_io_slave_ar_bits_qos),
+ .io_slave_ar_bits_region(T_8451_io_slave_ar_bits_region),
+ .io_slave_ar_bits_id(T_8451_io_slave_ar_bits_id),
+ .io_slave_ar_bits_user(T_8451_io_slave_ar_bits_user),
+ .io_slave_r_ready(T_8451_io_slave_r_ready),
+ .io_slave_r_valid(T_8451_io_slave_r_valid),
+ .io_slave_r_bits_resp(T_8451_io_slave_r_bits_resp),
+ .io_slave_r_bits_data(T_8451_io_slave_r_bits_data),
+ .io_slave_r_bits_last(T_8451_io_slave_r_bits_last),
+ .io_slave_r_bits_id(T_8451_io_slave_r_bits_id),
+ .io_slave_r_bits_user(T_8451_io_slave_r_bits_user)
+ );
+ NastiArbiter T_8452 (
+ .clk(T_8452_clk),
+ .reset(T_8452_reset),
+ .io_master_0_aw_ready(T_8452_io_master_0_aw_ready),
+ .io_master_0_aw_valid(T_8452_io_master_0_aw_valid),
+ .io_master_0_aw_bits_addr(T_8452_io_master_0_aw_bits_addr),
+ .io_master_0_aw_bits_len(T_8452_io_master_0_aw_bits_len),
+ .io_master_0_aw_bits_size(T_8452_io_master_0_aw_bits_size),
+ .io_master_0_aw_bits_burst(T_8452_io_master_0_aw_bits_burst),
+ .io_master_0_aw_bits_lock(T_8452_io_master_0_aw_bits_lock),
+ .io_master_0_aw_bits_cache(T_8452_io_master_0_aw_bits_cache),
+ .io_master_0_aw_bits_prot(T_8452_io_master_0_aw_bits_prot),
+ .io_master_0_aw_bits_qos(T_8452_io_master_0_aw_bits_qos),
+ .io_master_0_aw_bits_region(T_8452_io_master_0_aw_bits_region),
+ .io_master_0_aw_bits_id(T_8452_io_master_0_aw_bits_id),
+ .io_master_0_aw_bits_user(T_8452_io_master_0_aw_bits_user),
+ .io_master_0_w_ready(T_8452_io_master_0_w_ready),
+ .io_master_0_w_valid(T_8452_io_master_0_w_valid),
+ .io_master_0_w_bits_data(T_8452_io_master_0_w_bits_data),
+ .io_master_0_w_bits_last(T_8452_io_master_0_w_bits_last),
+ .io_master_0_w_bits_strb(T_8452_io_master_0_w_bits_strb),
+ .io_master_0_w_bits_user(T_8452_io_master_0_w_bits_user),
+ .io_master_0_b_ready(T_8452_io_master_0_b_ready),
+ .io_master_0_b_valid(T_8452_io_master_0_b_valid),
+ .io_master_0_b_bits_resp(T_8452_io_master_0_b_bits_resp),
+ .io_master_0_b_bits_id(T_8452_io_master_0_b_bits_id),
+ .io_master_0_b_bits_user(T_8452_io_master_0_b_bits_user),
+ .io_master_0_ar_ready(T_8452_io_master_0_ar_ready),
+ .io_master_0_ar_valid(T_8452_io_master_0_ar_valid),
+ .io_master_0_ar_bits_addr(T_8452_io_master_0_ar_bits_addr),
+ .io_master_0_ar_bits_len(T_8452_io_master_0_ar_bits_len),
+ .io_master_0_ar_bits_size(T_8452_io_master_0_ar_bits_size),
+ .io_master_0_ar_bits_burst(T_8452_io_master_0_ar_bits_burst),
+ .io_master_0_ar_bits_lock(T_8452_io_master_0_ar_bits_lock),
+ .io_master_0_ar_bits_cache(T_8452_io_master_0_ar_bits_cache),
+ .io_master_0_ar_bits_prot(T_8452_io_master_0_ar_bits_prot),
+ .io_master_0_ar_bits_qos(T_8452_io_master_0_ar_bits_qos),
+ .io_master_0_ar_bits_region(T_8452_io_master_0_ar_bits_region),
+ .io_master_0_ar_bits_id(T_8452_io_master_0_ar_bits_id),
+ .io_master_0_ar_bits_user(T_8452_io_master_0_ar_bits_user),
+ .io_master_0_r_ready(T_8452_io_master_0_r_ready),
+ .io_master_0_r_valid(T_8452_io_master_0_r_valid),
+ .io_master_0_r_bits_resp(T_8452_io_master_0_r_bits_resp),
+ .io_master_0_r_bits_data(T_8452_io_master_0_r_bits_data),
+ .io_master_0_r_bits_last(T_8452_io_master_0_r_bits_last),
+ .io_master_0_r_bits_id(T_8452_io_master_0_r_bits_id),
+ .io_master_0_r_bits_user(T_8452_io_master_0_r_bits_user),
+ .io_master_1_aw_ready(T_8452_io_master_1_aw_ready),
+ .io_master_1_aw_valid(T_8452_io_master_1_aw_valid),
+ .io_master_1_aw_bits_addr(T_8452_io_master_1_aw_bits_addr),
+ .io_master_1_aw_bits_len(T_8452_io_master_1_aw_bits_len),
+ .io_master_1_aw_bits_size(T_8452_io_master_1_aw_bits_size),
+ .io_master_1_aw_bits_burst(T_8452_io_master_1_aw_bits_burst),
+ .io_master_1_aw_bits_lock(T_8452_io_master_1_aw_bits_lock),
+ .io_master_1_aw_bits_cache(T_8452_io_master_1_aw_bits_cache),
+ .io_master_1_aw_bits_prot(T_8452_io_master_1_aw_bits_prot),
+ .io_master_1_aw_bits_qos(T_8452_io_master_1_aw_bits_qos),
+ .io_master_1_aw_bits_region(T_8452_io_master_1_aw_bits_region),
+ .io_master_1_aw_bits_id(T_8452_io_master_1_aw_bits_id),
+ .io_master_1_aw_bits_user(T_8452_io_master_1_aw_bits_user),
+ .io_master_1_w_ready(T_8452_io_master_1_w_ready),
+ .io_master_1_w_valid(T_8452_io_master_1_w_valid),
+ .io_master_1_w_bits_data(T_8452_io_master_1_w_bits_data),
+ .io_master_1_w_bits_last(T_8452_io_master_1_w_bits_last),
+ .io_master_1_w_bits_strb(T_8452_io_master_1_w_bits_strb),
+ .io_master_1_w_bits_user(T_8452_io_master_1_w_bits_user),
+ .io_master_1_b_ready(T_8452_io_master_1_b_ready),
+ .io_master_1_b_valid(T_8452_io_master_1_b_valid),
+ .io_master_1_b_bits_resp(T_8452_io_master_1_b_bits_resp),
+ .io_master_1_b_bits_id(T_8452_io_master_1_b_bits_id),
+ .io_master_1_b_bits_user(T_8452_io_master_1_b_bits_user),
+ .io_master_1_ar_ready(T_8452_io_master_1_ar_ready),
+ .io_master_1_ar_valid(T_8452_io_master_1_ar_valid),
+ .io_master_1_ar_bits_addr(T_8452_io_master_1_ar_bits_addr),
+ .io_master_1_ar_bits_len(T_8452_io_master_1_ar_bits_len),
+ .io_master_1_ar_bits_size(T_8452_io_master_1_ar_bits_size),
+ .io_master_1_ar_bits_burst(T_8452_io_master_1_ar_bits_burst),
+ .io_master_1_ar_bits_lock(T_8452_io_master_1_ar_bits_lock),
+ .io_master_1_ar_bits_cache(T_8452_io_master_1_ar_bits_cache),
+ .io_master_1_ar_bits_prot(T_8452_io_master_1_ar_bits_prot),
+ .io_master_1_ar_bits_qos(T_8452_io_master_1_ar_bits_qos),
+ .io_master_1_ar_bits_region(T_8452_io_master_1_ar_bits_region),
+ .io_master_1_ar_bits_id(T_8452_io_master_1_ar_bits_id),
+ .io_master_1_ar_bits_user(T_8452_io_master_1_ar_bits_user),
+ .io_master_1_r_ready(T_8452_io_master_1_r_ready),
+ .io_master_1_r_valid(T_8452_io_master_1_r_valid),
+ .io_master_1_r_bits_resp(T_8452_io_master_1_r_bits_resp),
+ .io_master_1_r_bits_data(T_8452_io_master_1_r_bits_data),
+ .io_master_1_r_bits_last(T_8452_io_master_1_r_bits_last),
+ .io_master_1_r_bits_id(T_8452_io_master_1_r_bits_id),
+ .io_master_1_r_bits_user(T_8452_io_master_1_r_bits_user),
+ .io_slave_aw_ready(T_8452_io_slave_aw_ready),
+ .io_slave_aw_valid(T_8452_io_slave_aw_valid),
+ .io_slave_aw_bits_addr(T_8452_io_slave_aw_bits_addr),
+ .io_slave_aw_bits_len(T_8452_io_slave_aw_bits_len),
+ .io_slave_aw_bits_size(T_8452_io_slave_aw_bits_size),
+ .io_slave_aw_bits_burst(T_8452_io_slave_aw_bits_burst),
+ .io_slave_aw_bits_lock(T_8452_io_slave_aw_bits_lock),
+ .io_slave_aw_bits_cache(T_8452_io_slave_aw_bits_cache),
+ .io_slave_aw_bits_prot(T_8452_io_slave_aw_bits_prot),
+ .io_slave_aw_bits_qos(T_8452_io_slave_aw_bits_qos),
+ .io_slave_aw_bits_region(T_8452_io_slave_aw_bits_region),
+ .io_slave_aw_bits_id(T_8452_io_slave_aw_bits_id),
+ .io_slave_aw_bits_user(T_8452_io_slave_aw_bits_user),
+ .io_slave_w_ready(T_8452_io_slave_w_ready),
+ .io_slave_w_valid(T_8452_io_slave_w_valid),
+ .io_slave_w_bits_data(T_8452_io_slave_w_bits_data),
+ .io_slave_w_bits_last(T_8452_io_slave_w_bits_last),
+ .io_slave_w_bits_strb(T_8452_io_slave_w_bits_strb),
+ .io_slave_w_bits_user(T_8452_io_slave_w_bits_user),
+ .io_slave_b_ready(T_8452_io_slave_b_ready),
+ .io_slave_b_valid(T_8452_io_slave_b_valid),
+ .io_slave_b_bits_resp(T_8452_io_slave_b_bits_resp),
+ .io_slave_b_bits_id(T_8452_io_slave_b_bits_id),
+ .io_slave_b_bits_user(T_8452_io_slave_b_bits_user),
+ .io_slave_ar_ready(T_8452_io_slave_ar_ready),
+ .io_slave_ar_valid(T_8452_io_slave_ar_valid),
+ .io_slave_ar_bits_addr(T_8452_io_slave_ar_bits_addr),
+ .io_slave_ar_bits_len(T_8452_io_slave_ar_bits_len),
+ .io_slave_ar_bits_size(T_8452_io_slave_ar_bits_size),
+ .io_slave_ar_bits_burst(T_8452_io_slave_ar_bits_burst),
+ .io_slave_ar_bits_lock(T_8452_io_slave_ar_bits_lock),
+ .io_slave_ar_bits_cache(T_8452_io_slave_ar_bits_cache),
+ .io_slave_ar_bits_prot(T_8452_io_slave_ar_bits_prot),
+ .io_slave_ar_bits_qos(T_8452_io_slave_ar_bits_qos),
+ .io_slave_ar_bits_region(T_8452_io_slave_ar_bits_region),
+ .io_slave_ar_bits_id(T_8452_io_slave_ar_bits_id),
+ .io_slave_ar_bits_user(T_8452_io_slave_ar_bits_user),
+ .io_slave_r_ready(T_8452_io_slave_r_ready),
+ .io_slave_r_valid(T_8452_io_slave_r_valid),
+ .io_slave_r_bits_resp(T_8452_io_slave_r_bits_resp),
+ .io_slave_r_bits_data(T_8452_io_slave_r_bits_data),
+ .io_slave_r_bits_last(T_8452_io_slave_r_bits_last),
+ .io_slave_r_bits_id(T_8452_io_slave_r_bits_id),
+ .io_slave_r_bits_user(T_8452_io_slave_r_bits_user)
+ );
+ assign io_masters_0_aw_ready = T_4146_0_master_aw_ready;
+ assign io_masters_0_w_ready = T_4146_0_master_w_ready;
+ assign io_masters_0_b_valid = T_4146_0_master_b_valid;
+ assign io_masters_0_b_bits_resp = T_4146_0_master_b_bits_resp;
+ assign io_masters_0_b_bits_id = T_4146_0_master_b_bits_id;
+ assign io_masters_0_b_bits_user = T_4146_0_master_b_bits_user;
+ assign io_masters_0_ar_ready = T_4146_0_master_ar_ready;
+ assign io_masters_0_r_valid = T_4146_0_master_r_valid;
+ assign io_masters_0_r_bits_resp = T_4146_0_master_r_bits_resp;
+ assign io_masters_0_r_bits_data = T_4146_0_master_r_bits_data;
+ assign io_masters_0_r_bits_last = T_4146_0_master_r_bits_last;
+ assign io_masters_0_r_bits_id = T_4146_0_master_r_bits_id;
+ assign io_masters_0_r_bits_user = T_4146_0_master_r_bits_user;
+ assign io_masters_1_aw_ready = T_4146_1_master_aw_ready;
+ assign io_masters_1_w_ready = T_4146_1_master_w_ready;
+ assign io_masters_1_b_valid = T_4146_1_master_b_valid;
+ assign io_masters_1_b_bits_resp = T_4146_1_master_b_bits_resp;
+ assign io_masters_1_b_bits_id = T_4146_1_master_b_bits_id;
+ assign io_masters_1_b_bits_user = T_4146_1_master_b_bits_user;
+ assign io_masters_1_ar_ready = T_4146_1_master_ar_ready;
+ assign io_masters_1_r_valid = T_4146_1_master_r_valid;
+ assign io_masters_1_r_bits_resp = T_4146_1_master_r_bits_resp;
+ assign io_masters_1_r_bits_data = T_4146_1_master_r_bits_data;
+ assign io_masters_1_r_bits_last = T_4146_1_master_r_bits_last;
+ assign io_masters_1_r_bits_id = T_4146_1_master_r_bits_id;
+ assign io_masters_1_r_bits_user = T_4146_1_master_r_bits_user;
+ assign io_slaves_0_aw_valid = T_10206_0_slave_aw_valid;
+ assign io_slaves_0_aw_bits_addr = T_10206_0_slave_aw_bits_addr;
+ assign io_slaves_0_aw_bits_len = T_10206_0_slave_aw_bits_len;
+ assign io_slaves_0_aw_bits_size = T_10206_0_slave_aw_bits_size;
+ assign io_slaves_0_aw_bits_burst = T_10206_0_slave_aw_bits_burst;
+ assign io_slaves_0_aw_bits_lock = T_10206_0_slave_aw_bits_lock;
+ assign io_slaves_0_aw_bits_cache = T_10206_0_slave_aw_bits_cache;
+ assign io_slaves_0_aw_bits_prot = T_10206_0_slave_aw_bits_prot;
+ assign io_slaves_0_aw_bits_qos = T_10206_0_slave_aw_bits_qos;
+ assign io_slaves_0_aw_bits_region = T_10206_0_slave_aw_bits_region;
+ assign io_slaves_0_aw_bits_id = T_10206_0_slave_aw_bits_id;
+ assign io_slaves_0_aw_bits_user = T_10206_0_slave_aw_bits_user;
+ assign io_slaves_0_w_valid = T_10206_0_slave_w_valid;
+ assign io_slaves_0_w_bits_data = T_10206_0_slave_w_bits_data;
+ assign io_slaves_0_w_bits_last = T_10206_0_slave_w_bits_last;
+ assign io_slaves_0_w_bits_strb = T_10206_0_slave_w_bits_strb;
+ assign io_slaves_0_w_bits_user = T_10206_0_slave_w_bits_user;
+ assign io_slaves_0_b_ready = T_10206_0_slave_b_ready;
+ assign io_slaves_0_ar_valid = T_10206_0_slave_ar_valid;
+ assign io_slaves_0_ar_bits_addr = T_10206_0_slave_ar_bits_addr;
+ assign io_slaves_0_ar_bits_len = T_10206_0_slave_ar_bits_len;
+ assign io_slaves_0_ar_bits_size = T_10206_0_slave_ar_bits_size;
+ assign io_slaves_0_ar_bits_burst = T_10206_0_slave_ar_bits_burst;
+ assign io_slaves_0_ar_bits_lock = T_10206_0_slave_ar_bits_lock;
+ assign io_slaves_0_ar_bits_cache = T_10206_0_slave_ar_bits_cache;
+ assign io_slaves_0_ar_bits_prot = T_10206_0_slave_ar_bits_prot;
+ assign io_slaves_0_ar_bits_qos = T_10206_0_slave_ar_bits_qos;
+ assign io_slaves_0_ar_bits_region = T_10206_0_slave_ar_bits_region;
+ assign io_slaves_0_ar_bits_id = T_10206_0_slave_ar_bits_id;
+ assign io_slaves_0_ar_bits_user = T_10206_0_slave_ar_bits_user;
+ assign io_slaves_0_r_ready = T_10206_0_slave_r_ready;
+ assign io_slaves_1_aw_valid = T_10206_1_slave_aw_valid;
+ assign io_slaves_1_aw_bits_addr = T_10206_1_slave_aw_bits_addr;
+ assign io_slaves_1_aw_bits_len = T_10206_1_slave_aw_bits_len;
+ assign io_slaves_1_aw_bits_size = T_10206_1_slave_aw_bits_size;
+ assign io_slaves_1_aw_bits_burst = T_10206_1_slave_aw_bits_burst;
+ assign io_slaves_1_aw_bits_lock = T_10206_1_slave_aw_bits_lock;
+ assign io_slaves_1_aw_bits_cache = T_10206_1_slave_aw_bits_cache;
+ assign io_slaves_1_aw_bits_prot = T_10206_1_slave_aw_bits_prot;
+ assign io_slaves_1_aw_bits_qos = T_10206_1_slave_aw_bits_qos;
+ assign io_slaves_1_aw_bits_region = T_10206_1_slave_aw_bits_region;
+ assign io_slaves_1_aw_bits_id = T_10206_1_slave_aw_bits_id;
+ assign io_slaves_1_aw_bits_user = T_10206_1_slave_aw_bits_user;
+ assign io_slaves_1_w_valid = T_10206_1_slave_w_valid;
+ assign io_slaves_1_w_bits_data = T_10206_1_slave_w_bits_data;
+ assign io_slaves_1_w_bits_last = T_10206_1_slave_w_bits_last;
+ assign io_slaves_1_w_bits_strb = T_10206_1_slave_w_bits_strb;
+ assign io_slaves_1_w_bits_user = T_10206_1_slave_w_bits_user;
+ assign io_slaves_1_b_ready = T_10206_1_slave_b_ready;
+ assign io_slaves_1_ar_valid = T_10206_1_slave_ar_valid;
+ assign io_slaves_1_ar_bits_addr = T_10206_1_slave_ar_bits_addr;
+ assign io_slaves_1_ar_bits_len = T_10206_1_slave_ar_bits_len;
+ assign io_slaves_1_ar_bits_size = T_10206_1_slave_ar_bits_size;
+ assign io_slaves_1_ar_bits_burst = T_10206_1_slave_ar_bits_burst;
+ assign io_slaves_1_ar_bits_lock = T_10206_1_slave_ar_bits_lock;
+ assign io_slaves_1_ar_bits_cache = T_10206_1_slave_ar_bits_cache;
+ assign io_slaves_1_ar_bits_prot = T_10206_1_slave_ar_bits_prot;
+ assign io_slaves_1_ar_bits_qos = T_10206_1_slave_ar_bits_qos;
+ assign io_slaves_1_ar_bits_region = T_10206_1_slave_ar_bits_region;
+ assign io_slaves_1_ar_bits_id = T_10206_1_slave_ar_bits_id;
+ assign io_slaves_1_ar_bits_user = T_10206_1_slave_ar_bits_user;
+ assign io_slaves_1_r_ready = T_10206_1_slave_r_ready;
+ assign io_slaves_2_aw_valid = T_10206_2_slave_aw_valid;
+ assign io_slaves_2_aw_bits_addr = T_10206_2_slave_aw_bits_addr;
+ assign io_slaves_2_aw_bits_len = T_10206_2_slave_aw_bits_len;
+ assign io_slaves_2_aw_bits_size = T_10206_2_slave_aw_bits_size;
+ assign io_slaves_2_aw_bits_burst = T_10206_2_slave_aw_bits_burst;
+ assign io_slaves_2_aw_bits_lock = T_10206_2_slave_aw_bits_lock;
+ assign io_slaves_2_aw_bits_cache = T_10206_2_slave_aw_bits_cache;
+ assign io_slaves_2_aw_bits_prot = T_10206_2_slave_aw_bits_prot;
+ assign io_slaves_2_aw_bits_qos = T_10206_2_slave_aw_bits_qos;
+ assign io_slaves_2_aw_bits_region = T_10206_2_slave_aw_bits_region;
+ assign io_slaves_2_aw_bits_id = T_10206_2_slave_aw_bits_id;
+ assign io_slaves_2_aw_bits_user = T_10206_2_slave_aw_bits_user;
+ assign io_slaves_2_w_valid = T_10206_2_slave_w_valid;
+ assign io_slaves_2_w_bits_data = T_10206_2_slave_w_bits_data;
+ assign io_slaves_2_w_bits_last = T_10206_2_slave_w_bits_last;
+ assign io_slaves_2_w_bits_strb = T_10206_2_slave_w_bits_strb;
+ assign io_slaves_2_w_bits_user = T_10206_2_slave_w_bits_user;
+ assign io_slaves_2_b_ready = T_10206_2_slave_b_ready;
+ assign io_slaves_2_ar_valid = T_10206_2_slave_ar_valid;
+ assign io_slaves_2_ar_bits_addr = T_10206_2_slave_ar_bits_addr;
+ assign io_slaves_2_ar_bits_len = T_10206_2_slave_ar_bits_len;
+ assign io_slaves_2_ar_bits_size = T_10206_2_slave_ar_bits_size;
+ assign io_slaves_2_ar_bits_burst = T_10206_2_slave_ar_bits_burst;
+ assign io_slaves_2_ar_bits_lock = T_10206_2_slave_ar_bits_lock;
+ assign io_slaves_2_ar_bits_cache = T_10206_2_slave_ar_bits_cache;
+ assign io_slaves_2_ar_bits_prot = T_10206_2_slave_ar_bits_prot;
+ assign io_slaves_2_ar_bits_qos = T_10206_2_slave_ar_bits_qos;
+ assign io_slaves_2_ar_bits_region = T_10206_2_slave_ar_bits_region;
+ assign io_slaves_2_ar_bits_id = T_10206_2_slave_ar_bits_id;
+ assign io_slaves_2_ar_bits_user = T_10206_2_slave_ar_bits_user;
+ assign io_slaves_2_r_ready = T_10206_2_slave_r_ready;
+ assign io_slaves_3_aw_valid = T_10206_3_slave_aw_valid;
+ assign io_slaves_3_aw_bits_addr = T_10206_3_slave_aw_bits_addr;
+ assign io_slaves_3_aw_bits_len = T_10206_3_slave_aw_bits_len;
+ assign io_slaves_3_aw_bits_size = T_10206_3_slave_aw_bits_size;
+ assign io_slaves_3_aw_bits_burst = T_10206_3_slave_aw_bits_burst;
+ assign io_slaves_3_aw_bits_lock = T_10206_3_slave_aw_bits_lock;
+ assign io_slaves_3_aw_bits_cache = T_10206_3_slave_aw_bits_cache;
+ assign io_slaves_3_aw_bits_prot = T_10206_3_slave_aw_bits_prot;
+ assign io_slaves_3_aw_bits_qos = T_10206_3_slave_aw_bits_qos;
+ assign io_slaves_3_aw_bits_region = T_10206_3_slave_aw_bits_region;
+ assign io_slaves_3_aw_bits_id = T_10206_3_slave_aw_bits_id;
+ assign io_slaves_3_aw_bits_user = T_10206_3_slave_aw_bits_user;
+ assign io_slaves_3_w_valid = T_10206_3_slave_w_valid;
+ assign io_slaves_3_w_bits_data = T_10206_3_slave_w_bits_data;
+ assign io_slaves_3_w_bits_last = T_10206_3_slave_w_bits_last;
+ assign io_slaves_3_w_bits_strb = T_10206_3_slave_w_bits_strb;
+ assign io_slaves_3_w_bits_user = T_10206_3_slave_w_bits_user;
+ assign io_slaves_3_b_ready = T_10206_3_slave_b_ready;
+ assign io_slaves_3_ar_valid = T_10206_3_slave_ar_valid;
+ assign io_slaves_3_ar_bits_addr = T_10206_3_slave_ar_bits_addr;
+ assign io_slaves_3_ar_bits_len = T_10206_3_slave_ar_bits_len;
+ assign io_slaves_3_ar_bits_size = T_10206_3_slave_ar_bits_size;
+ assign io_slaves_3_ar_bits_burst = T_10206_3_slave_ar_bits_burst;
+ assign io_slaves_3_ar_bits_lock = T_10206_3_slave_ar_bits_lock;
+ assign io_slaves_3_ar_bits_cache = T_10206_3_slave_ar_bits_cache;
+ assign io_slaves_3_ar_bits_prot = T_10206_3_slave_ar_bits_prot;
+ assign io_slaves_3_ar_bits_qos = T_10206_3_slave_ar_bits_qos;
+ assign io_slaves_3_ar_bits_region = T_10206_3_slave_ar_bits_region;
+ assign io_slaves_3_ar_bits_id = T_10206_3_slave_ar_bits_id;
+ assign io_slaves_3_ar_bits_user = T_10206_3_slave_ar_bits_user;
+ assign io_slaves_3_r_ready = T_10206_3_slave_r_ready;
+ assign T_2710_clk = clk;
+ assign T_2710_reset = reset;
+ assign T_2710_io_master_aw_valid = T_4146_0_master_aw_valid;
+ assign T_2710_io_master_aw_bits_addr = T_4146_0_master_aw_bits_addr;
+ assign T_2710_io_master_aw_bits_len = T_4146_0_master_aw_bits_len;
+ assign T_2710_io_master_aw_bits_size = T_4146_0_master_aw_bits_size;
+ assign T_2710_io_master_aw_bits_burst = T_4146_0_master_aw_bits_burst;
+ assign T_2710_io_master_aw_bits_lock = T_4146_0_master_aw_bits_lock;
+ assign T_2710_io_master_aw_bits_cache = T_4146_0_master_aw_bits_cache;
+ assign T_2710_io_master_aw_bits_prot = T_4146_0_master_aw_bits_prot;
+ assign T_2710_io_master_aw_bits_qos = T_4146_0_master_aw_bits_qos;
+ assign T_2710_io_master_aw_bits_region = T_4146_0_master_aw_bits_region;
+ assign T_2710_io_master_aw_bits_id = T_4146_0_master_aw_bits_id;
+ assign T_2710_io_master_aw_bits_user = T_4146_0_master_aw_bits_user;
+ assign T_2710_io_master_w_valid = T_4146_0_master_w_valid;
+ assign T_2710_io_master_w_bits_data = T_4146_0_master_w_bits_data;
+ assign T_2710_io_master_w_bits_last = T_4146_0_master_w_bits_last;
+ assign T_2710_io_master_w_bits_strb = T_4146_0_master_w_bits_strb;
+ assign T_2710_io_master_w_bits_user = T_4146_0_master_w_bits_user;
+ assign T_2710_io_master_b_ready = T_4146_0_master_b_ready;
+ assign T_2710_io_master_ar_valid = T_4146_0_master_ar_valid;
+ assign T_2710_io_master_ar_bits_addr = T_4146_0_master_ar_bits_addr;
+ assign T_2710_io_master_ar_bits_len = T_4146_0_master_ar_bits_len;
+ assign T_2710_io_master_ar_bits_size = T_4146_0_master_ar_bits_size;
+ assign T_2710_io_master_ar_bits_burst = T_4146_0_master_ar_bits_burst;
+ assign T_2710_io_master_ar_bits_lock = T_4146_0_master_ar_bits_lock;
+ assign T_2710_io_master_ar_bits_cache = T_4146_0_master_ar_bits_cache;
+ assign T_2710_io_master_ar_bits_prot = T_4146_0_master_ar_bits_prot;
+ assign T_2710_io_master_ar_bits_qos = T_4146_0_master_ar_bits_qos;
+ assign T_2710_io_master_ar_bits_region = T_4146_0_master_ar_bits_region;
+ assign T_2710_io_master_ar_bits_id = T_4146_0_master_ar_bits_id;
+ assign T_2710_io_master_ar_bits_user = T_4146_0_master_ar_bits_user;
+ assign T_2710_io_master_r_ready = T_4146_0_master_r_ready;
+ assign T_2710_io_slave_0_aw_ready = T_4146_0_slave_0_aw_ready;
+ assign T_2710_io_slave_0_w_ready = T_4146_0_slave_0_w_ready;
+ assign T_2710_io_slave_0_b_valid = T_4146_0_slave_0_b_valid;
+ assign T_2710_io_slave_0_b_bits_resp = T_4146_0_slave_0_b_bits_resp;
+ assign T_2710_io_slave_0_b_bits_id = T_4146_0_slave_0_b_bits_id;
+ assign T_2710_io_slave_0_b_bits_user = T_4146_0_slave_0_b_bits_user;
+ assign T_2710_io_slave_0_ar_ready = T_4146_0_slave_0_ar_ready;
+ assign T_2710_io_slave_0_r_valid = T_4146_0_slave_0_r_valid;
+ assign T_2710_io_slave_0_r_bits_resp = T_4146_0_slave_0_r_bits_resp;
+ assign T_2710_io_slave_0_r_bits_data = T_4146_0_slave_0_r_bits_data;
+ assign T_2710_io_slave_0_r_bits_last = T_4146_0_slave_0_r_bits_last;
+ assign T_2710_io_slave_0_r_bits_id = T_4146_0_slave_0_r_bits_id;
+ assign T_2710_io_slave_0_r_bits_user = T_4146_0_slave_0_r_bits_user;
+ assign T_2710_io_slave_1_aw_ready = T_4146_0_slave_1_aw_ready;
+ assign T_2710_io_slave_1_w_ready = T_4146_0_slave_1_w_ready;
+ assign T_2710_io_slave_1_b_valid = T_4146_0_slave_1_b_valid;
+ assign T_2710_io_slave_1_b_bits_resp = T_4146_0_slave_1_b_bits_resp;
+ assign T_2710_io_slave_1_b_bits_id = T_4146_0_slave_1_b_bits_id;
+ assign T_2710_io_slave_1_b_bits_user = T_4146_0_slave_1_b_bits_user;
+ assign T_2710_io_slave_1_ar_ready = T_4146_0_slave_1_ar_ready;
+ assign T_2710_io_slave_1_r_valid = T_4146_0_slave_1_r_valid;
+ assign T_2710_io_slave_1_r_bits_resp = T_4146_0_slave_1_r_bits_resp;
+ assign T_2710_io_slave_1_r_bits_data = T_4146_0_slave_1_r_bits_data;
+ assign T_2710_io_slave_1_r_bits_last = T_4146_0_slave_1_r_bits_last;
+ assign T_2710_io_slave_1_r_bits_id = T_4146_0_slave_1_r_bits_id;
+ assign T_2710_io_slave_1_r_bits_user = T_4146_0_slave_1_r_bits_user;
+ assign T_2710_io_slave_2_aw_ready = T_4146_0_slave_2_aw_ready;
+ assign T_2710_io_slave_2_w_ready = T_4146_0_slave_2_w_ready;
+ assign T_2710_io_slave_2_b_valid = T_4146_0_slave_2_b_valid;
+ assign T_2710_io_slave_2_b_bits_resp = T_4146_0_slave_2_b_bits_resp;
+ assign T_2710_io_slave_2_b_bits_id = T_4146_0_slave_2_b_bits_id;
+ assign T_2710_io_slave_2_b_bits_user = T_4146_0_slave_2_b_bits_user;
+ assign T_2710_io_slave_2_ar_ready = T_4146_0_slave_2_ar_ready;
+ assign T_2710_io_slave_2_r_valid = T_4146_0_slave_2_r_valid;
+ assign T_2710_io_slave_2_r_bits_resp = T_4146_0_slave_2_r_bits_resp;
+ assign T_2710_io_slave_2_r_bits_data = T_4146_0_slave_2_r_bits_data;
+ assign T_2710_io_slave_2_r_bits_last = T_4146_0_slave_2_r_bits_last;
+ assign T_2710_io_slave_2_r_bits_id = T_4146_0_slave_2_r_bits_id;
+ assign T_2710_io_slave_2_r_bits_user = T_4146_0_slave_2_r_bits_user;
+ assign T_2710_io_slave_3_aw_ready = T_4146_0_slave_3_aw_ready;
+ assign T_2710_io_slave_3_w_ready = T_4146_0_slave_3_w_ready;
+ assign T_2710_io_slave_3_b_valid = T_4146_0_slave_3_b_valid;
+ assign T_2710_io_slave_3_b_bits_resp = T_4146_0_slave_3_b_bits_resp;
+ assign T_2710_io_slave_3_b_bits_id = T_4146_0_slave_3_b_bits_id;
+ assign T_2710_io_slave_3_b_bits_user = T_4146_0_slave_3_b_bits_user;
+ assign T_2710_io_slave_3_ar_ready = T_4146_0_slave_3_ar_ready;
+ assign T_2710_io_slave_3_r_valid = T_4146_0_slave_3_r_valid;
+ assign T_2710_io_slave_3_r_bits_resp = T_4146_0_slave_3_r_bits_resp;
+ assign T_2710_io_slave_3_r_bits_data = T_4146_0_slave_3_r_bits_data;
+ assign T_2710_io_slave_3_r_bits_last = T_4146_0_slave_3_r_bits_last;
+ assign T_2710_io_slave_3_r_bits_id = T_4146_0_slave_3_r_bits_id;
+ assign T_2710_io_slave_3_r_bits_user = T_4146_0_slave_3_r_bits_user;
+ assign T_2711_clk = clk;
+ assign T_2711_reset = reset;
+ assign T_2711_io_master_aw_valid = T_4146_1_master_aw_valid;
+ assign T_2711_io_master_aw_bits_addr = T_4146_1_master_aw_bits_addr;
+ assign T_2711_io_master_aw_bits_len = T_4146_1_master_aw_bits_len;
+ assign T_2711_io_master_aw_bits_size = T_4146_1_master_aw_bits_size;
+ assign T_2711_io_master_aw_bits_burst = T_4146_1_master_aw_bits_burst;
+ assign T_2711_io_master_aw_bits_lock = T_4146_1_master_aw_bits_lock;
+ assign T_2711_io_master_aw_bits_cache = T_4146_1_master_aw_bits_cache;
+ assign T_2711_io_master_aw_bits_prot = T_4146_1_master_aw_bits_prot;
+ assign T_2711_io_master_aw_bits_qos = T_4146_1_master_aw_bits_qos;
+ assign T_2711_io_master_aw_bits_region = T_4146_1_master_aw_bits_region;
+ assign T_2711_io_master_aw_bits_id = T_4146_1_master_aw_bits_id;
+ assign T_2711_io_master_aw_bits_user = T_4146_1_master_aw_bits_user;
+ assign T_2711_io_master_w_valid = T_4146_1_master_w_valid;
+ assign T_2711_io_master_w_bits_data = T_4146_1_master_w_bits_data;
+ assign T_2711_io_master_w_bits_last = T_4146_1_master_w_bits_last;
+ assign T_2711_io_master_w_bits_strb = T_4146_1_master_w_bits_strb;
+ assign T_2711_io_master_w_bits_user = T_4146_1_master_w_bits_user;
+ assign T_2711_io_master_b_ready = T_4146_1_master_b_ready;
+ assign T_2711_io_master_ar_valid = T_4146_1_master_ar_valid;
+ assign T_2711_io_master_ar_bits_addr = T_4146_1_master_ar_bits_addr;
+ assign T_2711_io_master_ar_bits_len = T_4146_1_master_ar_bits_len;
+ assign T_2711_io_master_ar_bits_size = T_4146_1_master_ar_bits_size;
+ assign T_2711_io_master_ar_bits_burst = T_4146_1_master_ar_bits_burst;
+ assign T_2711_io_master_ar_bits_lock = T_4146_1_master_ar_bits_lock;
+ assign T_2711_io_master_ar_bits_cache = T_4146_1_master_ar_bits_cache;
+ assign T_2711_io_master_ar_bits_prot = T_4146_1_master_ar_bits_prot;
+ assign T_2711_io_master_ar_bits_qos = T_4146_1_master_ar_bits_qos;
+ assign T_2711_io_master_ar_bits_region = T_4146_1_master_ar_bits_region;
+ assign T_2711_io_master_ar_bits_id = T_4146_1_master_ar_bits_id;
+ assign T_2711_io_master_ar_bits_user = T_4146_1_master_ar_bits_user;
+ assign T_2711_io_master_r_ready = T_4146_1_master_r_ready;
+ assign T_2711_io_slave_0_aw_ready = T_4146_1_slave_0_aw_ready;
+ assign T_2711_io_slave_0_w_ready = T_4146_1_slave_0_w_ready;
+ assign T_2711_io_slave_0_b_valid = T_4146_1_slave_0_b_valid;
+ assign T_2711_io_slave_0_b_bits_resp = T_4146_1_slave_0_b_bits_resp;
+ assign T_2711_io_slave_0_b_bits_id = T_4146_1_slave_0_b_bits_id;
+ assign T_2711_io_slave_0_b_bits_user = T_4146_1_slave_0_b_bits_user;
+ assign T_2711_io_slave_0_ar_ready = T_4146_1_slave_0_ar_ready;
+ assign T_2711_io_slave_0_r_valid = T_4146_1_slave_0_r_valid;
+ assign T_2711_io_slave_0_r_bits_resp = T_4146_1_slave_0_r_bits_resp;
+ assign T_2711_io_slave_0_r_bits_data = T_4146_1_slave_0_r_bits_data;
+ assign T_2711_io_slave_0_r_bits_last = T_4146_1_slave_0_r_bits_last;
+ assign T_2711_io_slave_0_r_bits_id = T_4146_1_slave_0_r_bits_id;
+ assign T_2711_io_slave_0_r_bits_user = T_4146_1_slave_0_r_bits_user;
+ assign T_2711_io_slave_1_aw_ready = T_4146_1_slave_1_aw_ready;
+ assign T_2711_io_slave_1_w_ready = T_4146_1_slave_1_w_ready;
+ assign T_2711_io_slave_1_b_valid = T_4146_1_slave_1_b_valid;
+ assign T_2711_io_slave_1_b_bits_resp = T_4146_1_slave_1_b_bits_resp;
+ assign T_2711_io_slave_1_b_bits_id = T_4146_1_slave_1_b_bits_id;
+ assign T_2711_io_slave_1_b_bits_user = T_4146_1_slave_1_b_bits_user;
+ assign T_2711_io_slave_1_ar_ready = T_4146_1_slave_1_ar_ready;
+ assign T_2711_io_slave_1_r_valid = T_4146_1_slave_1_r_valid;
+ assign T_2711_io_slave_1_r_bits_resp = T_4146_1_slave_1_r_bits_resp;
+ assign T_2711_io_slave_1_r_bits_data = T_4146_1_slave_1_r_bits_data;
+ assign T_2711_io_slave_1_r_bits_last = T_4146_1_slave_1_r_bits_last;
+ assign T_2711_io_slave_1_r_bits_id = T_4146_1_slave_1_r_bits_id;
+ assign T_2711_io_slave_1_r_bits_user = T_4146_1_slave_1_r_bits_user;
+ assign T_2711_io_slave_2_aw_ready = T_4146_1_slave_2_aw_ready;
+ assign T_2711_io_slave_2_w_ready = T_4146_1_slave_2_w_ready;
+ assign T_2711_io_slave_2_b_valid = T_4146_1_slave_2_b_valid;
+ assign T_2711_io_slave_2_b_bits_resp = T_4146_1_slave_2_b_bits_resp;
+ assign T_2711_io_slave_2_b_bits_id = T_4146_1_slave_2_b_bits_id;
+ assign T_2711_io_slave_2_b_bits_user = T_4146_1_slave_2_b_bits_user;
+ assign T_2711_io_slave_2_ar_ready = T_4146_1_slave_2_ar_ready;
+ assign T_2711_io_slave_2_r_valid = T_4146_1_slave_2_r_valid;
+ assign T_2711_io_slave_2_r_bits_resp = T_4146_1_slave_2_r_bits_resp;
+ assign T_2711_io_slave_2_r_bits_data = T_4146_1_slave_2_r_bits_data;
+ assign T_2711_io_slave_2_r_bits_last = T_4146_1_slave_2_r_bits_last;
+ assign T_2711_io_slave_2_r_bits_id = T_4146_1_slave_2_r_bits_id;
+ assign T_2711_io_slave_2_r_bits_user = T_4146_1_slave_2_r_bits_user;
+ assign T_2711_io_slave_3_aw_ready = T_4146_1_slave_3_aw_ready;
+ assign T_2711_io_slave_3_w_ready = T_4146_1_slave_3_w_ready;
+ assign T_2711_io_slave_3_b_valid = T_4146_1_slave_3_b_valid;
+ assign T_2711_io_slave_3_b_bits_resp = T_4146_1_slave_3_b_bits_resp;
+ assign T_2711_io_slave_3_b_bits_id = T_4146_1_slave_3_b_bits_id;
+ assign T_2711_io_slave_3_b_bits_user = T_4146_1_slave_3_b_bits_user;
+ assign T_2711_io_slave_3_ar_ready = T_4146_1_slave_3_ar_ready;
+ assign T_2711_io_slave_3_r_valid = T_4146_1_slave_3_r_valid;
+ assign T_2711_io_slave_3_r_bits_resp = T_4146_1_slave_3_r_bits_resp;
+ assign T_2711_io_slave_3_r_bits_data = T_4146_1_slave_3_r_bits_data;
+ assign T_2711_io_slave_3_r_bits_last = T_4146_1_slave_3_r_bits_last;
+ assign T_2711_io_slave_3_r_bits_id = T_4146_1_slave_3_r_bits_id;
+ assign T_2711_io_slave_3_r_bits_user = T_4146_1_slave_3_r_bits_user;
+ assign T_4146_0_master_aw_ready = T_2710_io_master_aw_ready;
+ assign T_4146_0_master_aw_valid = io_masters_0_aw_valid;
+ assign T_4146_0_master_aw_bits_addr = io_masters_0_aw_bits_addr;
+ assign T_4146_0_master_aw_bits_len = io_masters_0_aw_bits_len;
+ assign T_4146_0_master_aw_bits_size = io_masters_0_aw_bits_size;
+ assign T_4146_0_master_aw_bits_burst = io_masters_0_aw_bits_burst;
+ assign T_4146_0_master_aw_bits_lock = io_masters_0_aw_bits_lock;
+ assign T_4146_0_master_aw_bits_cache = io_masters_0_aw_bits_cache;
+ assign T_4146_0_master_aw_bits_prot = io_masters_0_aw_bits_prot;
+ assign T_4146_0_master_aw_bits_qos = io_masters_0_aw_bits_qos;
+ assign T_4146_0_master_aw_bits_region = io_masters_0_aw_bits_region;
+ assign T_4146_0_master_aw_bits_id = io_masters_0_aw_bits_id;
+ assign T_4146_0_master_aw_bits_user = io_masters_0_aw_bits_user;
+ assign T_4146_0_master_w_ready = T_2710_io_master_w_ready;
+ assign T_4146_0_master_w_valid = io_masters_0_w_valid;
+ assign T_4146_0_master_w_bits_data = io_masters_0_w_bits_data;
+ assign T_4146_0_master_w_bits_last = io_masters_0_w_bits_last;
+ assign T_4146_0_master_w_bits_strb = io_masters_0_w_bits_strb;
+ assign T_4146_0_master_w_bits_user = io_masters_0_w_bits_user;
+ assign T_4146_0_master_b_ready = io_masters_0_b_ready;
+ assign T_4146_0_master_b_valid = T_2710_io_master_b_valid;
+ assign T_4146_0_master_b_bits_resp = T_2710_io_master_b_bits_resp;
+ assign T_4146_0_master_b_bits_id = T_2710_io_master_b_bits_id;
+ assign T_4146_0_master_b_bits_user = T_2710_io_master_b_bits_user;
+ assign T_4146_0_master_ar_ready = T_2710_io_master_ar_ready;
+ assign T_4146_0_master_ar_valid = io_masters_0_ar_valid;
+ assign T_4146_0_master_ar_bits_addr = io_masters_0_ar_bits_addr;
+ assign T_4146_0_master_ar_bits_len = io_masters_0_ar_bits_len;
+ assign T_4146_0_master_ar_bits_size = io_masters_0_ar_bits_size;
+ assign T_4146_0_master_ar_bits_burst = io_masters_0_ar_bits_burst;
+ assign T_4146_0_master_ar_bits_lock = io_masters_0_ar_bits_lock;
+ assign T_4146_0_master_ar_bits_cache = io_masters_0_ar_bits_cache;
+ assign T_4146_0_master_ar_bits_prot = io_masters_0_ar_bits_prot;
+ assign T_4146_0_master_ar_bits_qos = io_masters_0_ar_bits_qos;
+ assign T_4146_0_master_ar_bits_region = io_masters_0_ar_bits_region;
+ assign T_4146_0_master_ar_bits_id = io_masters_0_ar_bits_id;
+ assign T_4146_0_master_ar_bits_user = io_masters_0_ar_bits_user;
+ assign T_4146_0_master_r_ready = io_masters_0_r_ready;
+ assign T_4146_0_master_r_valid = T_2710_io_master_r_valid;
+ assign T_4146_0_master_r_bits_resp = T_2710_io_master_r_bits_resp;
+ assign T_4146_0_master_r_bits_data = T_2710_io_master_r_bits_data;
+ assign T_4146_0_master_r_bits_last = T_2710_io_master_r_bits_last;
+ assign T_4146_0_master_r_bits_id = T_2710_io_master_r_bits_id;
+ assign T_4146_0_master_r_bits_user = T_2710_io_master_r_bits_user;
+ assign T_4146_0_slave_0_aw_ready = T_19131_0_aw_ready;
+ assign T_4146_0_slave_0_aw_valid = T_2710_io_slave_0_aw_valid;
+ assign T_4146_0_slave_0_aw_bits_addr = T_2710_io_slave_0_aw_bits_addr;
+ assign T_4146_0_slave_0_aw_bits_len = T_2710_io_slave_0_aw_bits_len;
+ assign T_4146_0_slave_0_aw_bits_size = T_2710_io_slave_0_aw_bits_size;
+ assign T_4146_0_slave_0_aw_bits_burst = T_2710_io_slave_0_aw_bits_burst;
+ assign T_4146_0_slave_0_aw_bits_lock = T_2710_io_slave_0_aw_bits_lock;
+ assign T_4146_0_slave_0_aw_bits_cache = T_2710_io_slave_0_aw_bits_cache;
+ assign T_4146_0_slave_0_aw_bits_prot = T_2710_io_slave_0_aw_bits_prot;
+ assign T_4146_0_slave_0_aw_bits_qos = T_2710_io_slave_0_aw_bits_qos;
+ assign T_4146_0_slave_0_aw_bits_region = T_2710_io_slave_0_aw_bits_region;
+ assign T_4146_0_slave_0_aw_bits_id = T_2710_io_slave_0_aw_bits_id;
+ assign T_4146_0_slave_0_aw_bits_user = T_2710_io_slave_0_aw_bits_user;
+ assign T_4146_0_slave_0_w_ready = T_19131_0_w_ready;
+ assign T_4146_0_slave_0_w_valid = T_2710_io_slave_0_w_valid;
+ assign T_4146_0_slave_0_w_bits_data = T_2710_io_slave_0_w_bits_data;
+ assign T_4146_0_slave_0_w_bits_last = T_2710_io_slave_0_w_bits_last;
+ assign T_4146_0_slave_0_w_bits_strb = T_2710_io_slave_0_w_bits_strb;
+ assign T_4146_0_slave_0_w_bits_user = T_2710_io_slave_0_w_bits_user;
+ assign T_4146_0_slave_0_b_ready = T_2710_io_slave_0_b_ready;
+ assign T_4146_0_slave_0_b_valid = T_19131_0_b_valid;
+ assign T_4146_0_slave_0_b_bits_resp = T_19131_0_b_bits_resp;
+ assign T_4146_0_slave_0_b_bits_id = T_19131_0_b_bits_id;
+ assign T_4146_0_slave_0_b_bits_user = T_19131_0_b_bits_user;
+ assign T_4146_0_slave_0_ar_ready = T_19131_0_ar_ready;
+ assign T_4146_0_slave_0_ar_valid = T_2710_io_slave_0_ar_valid;
+ assign T_4146_0_slave_0_ar_bits_addr = T_2710_io_slave_0_ar_bits_addr;
+ assign T_4146_0_slave_0_ar_bits_len = T_2710_io_slave_0_ar_bits_len;
+ assign T_4146_0_slave_0_ar_bits_size = T_2710_io_slave_0_ar_bits_size;
+ assign T_4146_0_slave_0_ar_bits_burst = T_2710_io_slave_0_ar_bits_burst;
+ assign T_4146_0_slave_0_ar_bits_lock = T_2710_io_slave_0_ar_bits_lock;
+ assign T_4146_0_slave_0_ar_bits_cache = T_2710_io_slave_0_ar_bits_cache;
+ assign T_4146_0_slave_0_ar_bits_prot = T_2710_io_slave_0_ar_bits_prot;
+ assign T_4146_0_slave_0_ar_bits_qos = T_2710_io_slave_0_ar_bits_qos;
+ assign T_4146_0_slave_0_ar_bits_region = T_2710_io_slave_0_ar_bits_region;
+ assign T_4146_0_slave_0_ar_bits_id = T_2710_io_slave_0_ar_bits_id;
+ assign T_4146_0_slave_0_ar_bits_user = T_2710_io_slave_0_ar_bits_user;
+ assign T_4146_0_slave_0_r_ready = T_2710_io_slave_0_r_ready;
+ assign T_4146_0_slave_0_r_valid = T_19131_0_r_valid;
+ assign T_4146_0_slave_0_r_bits_resp = T_19131_0_r_bits_resp;
+ assign T_4146_0_slave_0_r_bits_data = T_19131_0_r_bits_data;
+ assign T_4146_0_slave_0_r_bits_last = T_19131_0_r_bits_last;
+ assign T_4146_0_slave_0_r_bits_id = T_19131_0_r_bits_id;
+ assign T_4146_0_slave_0_r_bits_user = T_19131_0_r_bits_user;
+ assign T_4146_0_slave_1_aw_ready = T_19768_0_aw_ready;
+ assign T_4146_0_slave_1_aw_valid = T_2710_io_slave_1_aw_valid;
+ assign T_4146_0_slave_1_aw_bits_addr = T_2710_io_slave_1_aw_bits_addr;
+ assign T_4146_0_slave_1_aw_bits_len = T_2710_io_slave_1_aw_bits_len;
+ assign T_4146_0_slave_1_aw_bits_size = T_2710_io_slave_1_aw_bits_size;
+ assign T_4146_0_slave_1_aw_bits_burst = T_2710_io_slave_1_aw_bits_burst;
+ assign T_4146_0_slave_1_aw_bits_lock = T_2710_io_slave_1_aw_bits_lock;
+ assign T_4146_0_slave_1_aw_bits_cache = T_2710_io_slave_1_aw_bits_cache;
+ assign T_4146_0_slave_1_aw_bits_prot = T_2710_io_slave_1_aw_bits_prot;
+ assign T_4146_0_slave_1_aw_bits_qos = T_2710_io_slave_1_aw_bits_qos;
+ assign T_4146_0_slave_1_aw_bits_region = T_2710_io_slave_1_aw_bits_region;
+ assign T_4146_0_slave_1_aw_bits_id = T_2710_io_slave_1_aw_bits_id;
+ assign T_4146_0_slave_1_aw_bits_user = T_2710_io_slave_1_aw_bits_user;
+ assign T_4146_0_slave_1_w_ready = T_19768_0_w_ready;
+ assign T_4146_0_slave_1_w_valid = T_2710_io_slave_1_w_valid;
+ assign T_4146_0_slave_1_w_bits_data = T_2710_io_slave_1_w_bits_data;
+ assign T_4146_0_slave_1_w_bits_last = T_2710_io_slave_1_w_bits_last;
+ assign T_4146_0_slave_1_w_bits_strb = T_2710_io_slave_1_w_bits_strb;
+ assign T_4146_0_slave_1_w_bits_user = T_2710_io_slave_1_w_bits_user;
+ assign T_4146_0_slave_1_b_ready = T_2710_io_slave_1_b_ready;
+ assign T_4146_0_slave_1_b_valid = T_19768_0_b_valid;
+ assign T_4146_0_slave_1_b_bits_resp = T_19768_0_b_bits_resp;
+ assign T_4146_0_slave_1_b_bits_id = T_19768_0_b_bits_id;
+ assign T_4146_0_slave_1_b_bits_user = T_19768_0_b_bits_user;
+ assign T_4146_0_slave_1_ar_ready = T_19768_0_ar_ready;
+ assign T_4146_0_slave_1_ar_valid = T_2710_io_slave_1_ar_valid;
+ assign T_4146_0_slave_1_ar_bits_addr = T_2710_io_slave_1_ar_bits_addr;
+ assign T_4146_0_slave_1_ar_bits_len = T_2710_io_slave_1_ar_bits_len;
+ assign T_4146_0_slave_1_ar_bits_size = T_2710_io_slave_1_ar_bits_size;
+ assign T_4146_0_slave_1_ar_bits_burst = T_2710_io_slave_1_ar_bits_burst;
+ assign T_4146_0_slave_1_ar_bits_lock = T_2710_io_slave_1_ar_bits_lock;
+ assign T_4146_0_slave_1_ar_bits_cache = T_2710_io_slave_1_ar_bits_cache;
+ assign T_4146_0_slave_1_ar_bits_prot = T_2710_io_slave_1_ar_bits_prot;
+ assign T_4146_0_slave_1_ar_bits_qos = T_2710_io_slave_1_ar_bits_qos;
+ assign T_4146_0_slave_1_ar_bits_region = T_2710_io_slave_1_ar_bits_region;
+ assign T_4146_0_slave_1_ar_bits_id = T_2710_io_slave_1_ar_bits_id;
+ assign T_4146_0_slave_1_ar_bits_user = T_2710_io_slave_1_ar_bits_user;
+ assign T_4146_0_slave_1_r_ready = T_2710_io_slave_1_r_ready;
+ assign T_4146_0_slave_1_r_valid = T_19768_0_r_valid;
+ assign T_4146_0_slave_1_r_bits_resp = T_19768_0_r_bits_resp;
+ assign T_4146_0_slave_1_r_bits_data = T_19768_0_r_bits_data;
+ assign T_4146_0_slave_1_r_bits_last = T_19768_0_r_bits_last;
+ assign T_4146_0_slave_1_r_bits_id = T_19768_0_r_bits_id;
+ assign T_4146_0_slave_1_r_bits_user = T_19768_0_r_bits_user;
+ assign T_4146_0_slave_2_aw_ready = T_20405_0_aw_ready;
+ assign T_4146_0_slave_2_aw_valid = T_2710_io_slave_2_aw_valid;
+ assign T_4146_0_slave_2_aw_bits_addr = T_2710_io_slave_2_aw_bits_addr;
+ assign T_4146_0_slave_2_aw_bits_len = T_2710_io_slave_2_aw_bits_len;
+ assign T_4146_0_slave_2_aw_bits_size = T_2710_io_slave_2_aw_bits_size;
+ assign T_4146_0_slave_2_aw_bits_burst = T_2710_io_slave_2_aw_bits_burst;
+ assign T_4146_0_slave_2_aw_bits_lock = T_2710_io_slave_2_aw_bits_lock;
+ assign T_4146_0_slave_2_aw_bits_cache = T_2710_io_slave_2_aw_bits_cache;
+ assign T_4146_0_slave_2_aw_bits_prot = T_2710_io_slave_2_aw_bits_prot;
+ assign T_4146_0_slave_2_aw_bits_qos = T_2710_io_slave_2_aw_bits_qos;
+ assign T_4146_0_slave_2_aw_bits_region = T_2710_io_slave_2_aw_bits_region;
+ assign T_4146_0_slave_2_aw_bits_id = T_2710_io_slave_2_aw_bits_id;
+ assign T_4146_0_slave_2_aw_bits_user = T_2710_io_slave_2_aw_bits_user;
+ assign T_4146_0_slave_2_w_ready = T_20405_0_w_ready;
+ assign T_4146_0_slave_2_w_valid = T_2710_io_slave_2_w_valid;
+ assign T_4146_0_slave_2_w_bits_data = T_2710_io_slave_2_w_bits_data;
+ assign T_4146_0_slave_2_w_bits_last = T_2710_io_slave_2_w_bits_last;
+ assign T_4146_0_slave_2_w_bits_strb = T_2710_io_slave_2_w_bits_strb;
+ assign T_4146_0_slave_2_w_bits_user = T_2710_io_slave_2_w_bits_user;
+ assign T_4146_0_slave_2_b_ready = T_2710_io_slave_2_b_ready;
+ assign T_4146_0_slave_2_b_valid = T_20405_0_b_valid;
+ assign T_4146_0_slave_2_b_bits_resp = T_20405_0_b_bits_resp;
+ assign T_4146_0_slave_2_b_bits_id = T_20405_0_b_bits_id;
+ assign T_4146_0_slave_2_b_bits_user = T_20405_0_b_bits_user;
+ assign T_4146_0_slave_2_ar_ready = T_20405_0_ar_ready;
+ assign T_4146_0_slave_2_ar_valid = T_2710_io_slave_2_ar_valid;
+ assign T_4146_0_slave_2_ar_bits_addr = T_2710_io_slave_2_ar_bits_addr;
+ assign T_4146_0_slave_2_ar_bits_len = T_2710_io_slave_2_ar_bits_len;
+ assign T_4146_0_slave_2_ar_bits_size = T_2710_io_slave_2_ar_bits_size;
+ assign T_4146_0_slave_2_ar_bits_burst = T_2710_io_slave_2_ar_bits_burst;
+ assign T_4146_0_slave_2_ar_bits_lock = T_2710_io_slave_2_ar_bits_lock;
+ assign T_4146_0_slave_2_ar_bits_cache = T_2710_io_slave_2_ar_bits_cache;
+ assign T_4146_0_slave_2_ar_bits_prot = T_2710_io_slave_2_ar_bits_prot;
+ assign T_4146_0_slave_2_ar_bits_qos = T_2710_io_slave_2_ar_bits_qos;
+ assign T_4146_0_slave_2_ar_bits_region = T_2710_io_slave_2_ar_bits_region;
+ assign T_4146_0_slave_2_ar_bits_id = T_2710_io_slave_2_ar_bits_id;
+ assign T_4146_0_slave_2_ar_bits_user = T_2710_io_slave_2_ar_bits_user;
+ assign T_4146_0_slave_2_r_ready = T_2710_io_slave_2_r_ready;
+ assign T_4146_0_slave_2_r_valid = T_20405_0_r_valid;
+ assign T_4146_0_slave_2_r_bits_resp = T_20405_0_r_bits_resp;
+ assign T_4146_0_slave_2_r_bits_data = T_20405_0_r_bits_data;
+ assign T_4146_0_slave_2_r_bits_last = T_20405_0_r_bits_last;
+ assign T_4146_0_slave_2_r_bits_id = T_20405_0_r_bits_id;
+ assign T_4146_0_slave_2_r_bits_user = T_20405_0_r_bits_user;
+ assign T_4146_0_slave_3_aw_ready = T_21042_0_aw_ready;
+ assign T_4146_0_slave_3_aw_valid = T_2710_io_slave_3_aw_valid;
+ assign T_4146_0_slave_3_aw_bits_addr = T_2710_io_slave_3_aw_bits_addr;
+ assign T_4146_0_slave_3_aw_bits_len = T_2710_io_slave_3_aw_bits_len;
+ assign T_4146_0_slave_3_aw_bits_size = T_2710_io_slave_3_aw_bits_size;
+ assign T_4146_0_slave_3_aw_bits_burst = T_2710_io_slave_3_aw_bits_burst;
+ assign T_4146_0_slave_3_aw_bits_lock = T_2710_io_slave_3_aw_bits_lock;
+ assign T_4146_0_slave_3_aw_bits_cache = T_2710_io_slave_3_aw_bits_cache;
+ assign T_4146_0_slave_3_aw_bits_prot = T_2710_io_slave_3_aw_bits_prot;
+ assign T_4146_0_slave_3_aw_bits_qos = T_2710_io_slave_3_aw_bits_qos;
+ assign T_4146_0_slave_3_aw_bits_region = T_2710_io_slave_3_aw_bits_region;
+ assign T_4146_0_slave_3_aw_bits_id = T_2710_io_slave_3_aw_bits_id;
+ assign T_4146_0_slave_3_aw_bits_user = T_2710_io_slave_3_aw_bits_user;
+ assign T_4146_0_slave_3_w_ready = T_21042_0_w_ready;
+ assign T_4146_0_slave_3_w_valid = T_2710_io_slave_3_w_valid;
+ assign T_4146_0_slave_3_w_bits_data = T_2710_io_slave_3_w_bits_data;
+ assign T_4146_0_slave_3_w_bits_last = T_2710_io_slave_3_w_bits_last;
+ assign T_4146_0_slave_3_w_bits_strb = T_2710_io_slave_3_w_bits_strb;
+ assign T_4146_0_slave_3_w_bits_user = T_2710_io_slave_3_w_bits_user;
+ assign T_4146_0_slave_3_b_ready = T_2710_io_slave_3_b_ready;
+ assign T_4146_0_slave_3_b_valid = T_21042_0_b_valid;
+ assign T_4146_0_slave_3_b_bits_resp = T_21042_0_b_bits_resp;
+ assign T_4146_0_slave_3_b_bits_id = T_21042_0_b_bits_id;
+ assign T_4146_0_slave_3_b_bits_user = T_21042_0_b_bits_user;
+ assign T_4146_0_slave_3_ar_ready = T_21042_0_ar_ready;
+ assign T_4146_0_slave_3_ar_valid = T_2710_io_slave_3_ar_valid;
+ assign T_4146_0_slave_3_ar_bits_addr = T_2710_io_slave_3_ar_bits_addr;
+ assign T_4146_0_slave_3_ar_bits_len = T_2710_io_slave_3_ar_bits_len;
+ assign T_4146_0_slave_3_ar_bits_size = T_2710_io_slave_3_ar_bits_size;
+ assign T_4146_0_slave_3_ar_bits_burst = T_2710_io_slave_3_ar_bits_burst;
+ assign T_4146_0_slave_3_ar_bits_lock = T_2710_io_slave_3_ar_bits_lock;
+ assign T_4146_0_slave_3_ar_bits_cache = T_2710_io_slave_3_ar_bits_cache;
+ assign T_4146_0_slave_3_ar_bits_prot = T_2710_io_slave_3_ar_bits_prot;
+ assign T_4146_0_slave_3_ar_bits_qos = T_2710_io_slave_3_ar_bits_qos;
+ assign T_4146_0_slave_3_ar_bits_region = T_2710_io_slave_3_ar_bits_region;
+ assign T_4146_0_slave_3_ar_bits_id = T_2710_io_slave_3_ar_bits_id;
+ assign T_4146_0_slave_3_ar_bits_user = T_2710_io_slave_3_ar_bits_user;
+ assign T_4146_0_slave_3_r_ready = T_2710_io_slave_3_r_ready;
+ assign T_4146_0_slave_3_r_valid = T_21042_0_r_valid;
+ assign T_4146_0_slave_3_r_bits_resp = T_21042_0_r_bits_resp;
+ assign T_4146_0_slave_3_r_bits_data = T_21042_0_r_bits_data;
+ assign T_4146_0_slave_3_r_bits_last = T_21042_0_r_bits_last;
+ assign T_4146_0_slave_3_r_bits_id = T_21042_0_r_bits_id;
+ assign T_4146_0_slave_3_r_bits_user = T_21042_0_r_bits_user;
+ assign T_4146_1_master_aw_ready = T_2711_io_master_aw_ready;
+ assign T_4146_1_master_aw_valid = io_masters_1_aw_valid;
+ assign T_4146_1_master_aw_bits_addr = io_masters_1_aw_bits_addr;
+ assign T_4146_1_master_aw_bits_len = io_masters_1_aw_bits_len;
+ assign T_4146_1_master_aw_bits_size = io_masters_1_aw_bits_size;
+ assign T_4146_1_master_aw_bits_burst = io_masters_1_aw_bits_burst;
+ assign T_4146_1_master_aw_bits_lock = io_masters_1_aw_bits_lock;
+ assign T_4146_1_master_aw_bits_cache = io_masters_1_aw_bits_cache;
+ assign T_4146_1_master_aw_bits_prot = io_masters_1_aw_bits_prot;
+ assign T_4146_1_master_aw_bits_qos = io_masters_1_aw_bits_qos;
+ assign T_4146_1_master_aw_bits_region = io_masters_1_aw_bits_region;
+ assign T_4146_1_master_aw_bits_id = io_masters_1_aw_bits_id;
+ assign T_4146_1_master_aw_bits_user = io_masters_1_aw_bits_user;
+ assign T_4146_1_master_w_ready = T_2711_io_master_w_ready;
+ assign T_4146_1_master_w_valid = io_masters_1_w_valid;
+ assign T_4146_1_master_w_bits_data = io_masters_1_w_bits_data;
+ assign T_4146_1_master_w_bits_last = io_masters_1_w_bits_last;
+ assign T_4146_1_master_w_bits_strb = io_masters_1_w_bits_strb;
+ assign T_4146_1_master_w_bits_user = io_masters_1_w_bits_user;
+ assign T_4146_1_master_b_ready = io_masters_1_b_ready;
+ assign T_4146_1_master_b_valid = T_2711_io_master_b_valid;
+ assign T_4146_1_master_b_bits_resp = T_2711_io_master_b_bits_resp;
+ assign T_4146_1_master_b_bits_id = T_2711_io_master_b_bits_id;
+ assign T_4146_1_master_b_bits_user = T_2711_io_master_b_bits_user;
+ assign T_4146_1_master_ar_ready = T_2711_io_master_ar_ready;
+ assign T_4146_1_master_ar_valid = io_masters_1_ar_valid;
+ assign T_4146_1_master_ar_bits_addr = io_masters_1_ar_bits_addr;
+ assign T_4146_1_master_ar_bits_len = io_masters_1_ar_bits_len;
+ assign T_4146_1_master_ar_bits_size = io_masters_1_ar_bits_size;
+ assign T_4146_1_master_ar_bits_burst = io_masters_1_ar_bits_burst;
+ assign T_4146_1_master_ar_bits_lock = io_masters_1_ar_bits_lock;
+ assign T_4146_1_master_ar_bits_cache = io_masters_1_ar_bits_cache;
+ assign T_4146_1_master_ar_bits_prot = io_masters_1_ar_bits_prot;
+ assign T_4146_1_master_ar_bits_qos = io_masters_1_ar_bits_qos;
+ assign T_4146_1_master_ar_bits_region = io_masters_1_ar_bits_region;
+ assign T_4146_1_master_ar_bits_id = io_masters_1_ar_bits_id;
+ assign T_4146_1_master_ar_bits_user = io_masters_1_ar_bits_user;
+ assign T_4146_1_master_r_ready = io_masters_1_r_ready;
+ assign T_4146_1_master_r_valid = T_2711_io_master_r_valid;
+ assign T_4146_1_master_r_bits_resp = T_2711_io_master_r_bits_resp;
+ assign T_4146_1_master_r_bits_data = T_2711_io_master_r_bits_data;
+ assign T_4146_1_master_r_bits_last = T_2711_io_master_r_bits_last;
+ assign T_4146_1_master_r_bits_id = T_2711_io_master_r_bits_id;
+ assign T_4146_1_master_r_bits_user = T_2711_io_master_r_bits_user;
+ assign T_4146_1_slave_0_aw_ready = T_19131_1_aw_ready;
+ assign T_4146_1_slave_0_aw_valid = T_2711_io_slave_0_aw_valid;
+ assign T_4146_1_slave_0_aw_bits_addr = T_2711_io_slave_0_aw_bits_addr;
+ assign T_4146_1_slave_0_aw_bits_len = T_2711_io_slave_0_aw_bits_len;
+ assign T_4146_1_slave_0_aw_bits_size = T_2711_io_slave_0_aw_bits_size;
+ assign T_4146_1_slave_0_aw_bits_burst = T_2711_io_slave_0_aw_bits_burst;
+ assign T_4146_1_slave_0_aw_bits_lock = T_2711_io_slave_0_aw_bits_lock;
+ assign T_4146_1_slave_0_aw_bits_cache = T_2711_io_slave_0_aw_bits_cache;
+ assign T_4146_1_slave_0_aw_bits_prot = T_2711_io_slave_0_aw_bits_prot;
+ assign T_4146_1_slave_0_aw_bits_qos = T_2711_io_slave_0_aw_bits_qos;
+ assign T_4146_1_slave_0_aw_bits_region = T_2711_io_slave_0_aw_bits_region;
+ assign T_4146_1_slave_0_aw_bits_id = T_2711_io_slave_0_aw_bits_id;
+ assign T_4146_1_slave_0_aw_bits_user = T_2711_io_slave_0_aw_bits_user;
+ assign T_4146_1_slave_0_w_ready = T_19131_1_w_ready;
+ assign T_4146_1_slave_0_w_valid = T_2711_io_slave_0_w_valid;
+ assign T_4146_1_slave_0_w_bits_data = T_2711_io_slave_0_w_bits_data;
+ assign T_4146_1_slave_0_w_bits_last = T_2711_io_slave_0_w_bits_last;
+ assign T_4146_1_slave_0_w_bits_strb = T_2711_io_slave_0_w_bits_strb;
+ assign T_4146_1_slave_0_w_bits_user = T_2711_io_slave_0_w_bits_user;
+ assign T_4146_1_slave_0_b_ready = T_2711_io_slave_0_b_ready;
+ assign T_4146_1_slave_0_b_valid = T_19131_1_b_valid;
+ assign T_4146_1_slave_0_b_bits_resp = T_19131_1_b_bits_resp;
+ assign T_4146_1_slave_0_b_bits_id = T_19131_1_b_bits_id;
+ assign T_4146_1_slave_0_b_bits_user = T_19131_1_b_bits_user;
+ assign T_4146_1_slave_0_ar_ready = T_19131_1_ar_ready;
+ assign T_4146_1_slave_0_ar_valid = T_2711_io_slave_0_ar_valid;
+ assign T_4146_1_slave_0_ar_bits_addr = T_2711_io_slave_0_ar_bits_addr;
+ assign T_4146_1_slave_0_ar_bits_len = T_2711_io_slave_0_ar_bits_len;
+ assign T_4146_1_slave_0_ar_bits_size = T_2711_io_slave_0_ar_bits_size;
+ assign T_4146_1_slave_0_ar_bits_burst = T_2711_io_slave_0_ar_bits_burst;
+ assign T_4146_1_slave_0_ar_bits_lock = T_2711_io_slave_0_ar_bits_lock;
+ assign T_4146_1_slave_0_ar_bits_cache = T_2711_io_slave_0_ar_bits_cache;
+ assign T_4146_1_slave_0_ar_bits_prot = T_2711_io_slave_0_ar_bits_prot;
+ assign T_4146_1_slave_0_ar_bits_qos = T_2711_io_slave_0_ar_bits_qos;
+ assign T_4146_1_slave_0_ar_bits_region = T_2711_io_slave_0_ar_bits_region;
+ assign T_4146_1_slave_0_ar_bits_id = T_2711_io_slave_0_ar_bits_id;
+ assign T_4146_1_slave_0_ar_bits_user = T_2711_io_slave_0_ar_bits_user;
+ assign T_4146_1_slave_0_r_ready = T_2711_io_slave_0_r_ready;
+ assign T_4146_1_slave_0_r_valid = T_19131_1_r_valid;
+ assign T_4146_1_slave_0_r_bits_resp = T_19131_1_r_bits_resp;
+ assign T_4146_1_slave_0_r_bits_data = T_19131_1_r_bits_data;
+ assign T_4146_1_slave_0_r_bits_last = T_19131_1_r_bits_last;
+ assign T_4146_1_slave_0_r_bits_id = T_19131_1_r_bits_id;
+ assign T_4146_1_slave_0_r_bits_user = T_19131_1_r_bits_user;
+ assign T_4146_1_slave_1_aw_ready = T_19768_1_aw_ready;
+ assign T_4146_1_slave_1_aw_valid = T_2711_io_slave_1_aw_valid;
+ assign T_4146_1_slave_1_aw_bits_addr = T_2711_io_slave_1_aw_bits_addr;
+ assign T_4146_1_slave_1_aw_bits_len = T_2711_io_slave_1_aw_bits_len;
+ assign T_4146_1_slave_1_aw_bits_size = T_2711_io_slave_1_aw_bits_size;
+ assign T_4146_1_slave_1_aw_bits_burst = T_2711_io_slave_1_aw_bits_burst;
+ assign T_4146_1_slave_1_aw_bits_lock = T_2711_io_slave_1_aw_bits_lock;
+ assign T_4146_1_slave_1_aw_bits_cache = T_2711_io_slave_1_aw_bits_cache;
+ assign T_4146_1_slave_1_aw_bits_prot = T_2711_io_slave_1_aw_bits_prot;
+ assign T_4146_1_slave_1_aw_bits_qos = T_2711_io_slave_1_aw_bits_qos;
+ assign T_4146_1_slave_1_aw_bits_region = T_2711_io_slave_1_aw_bits_region;
+ assign T_4146_1_slave_1_aw_bits_id = T_2711_io_slave_1_aw_bits_id;
+ assign T_4146_1_slave_1_aw_bits_user = T_2711_io_slave_1_aw_bits_user;
+ assign T_4146_1_slave_1_w_ready = T_19768_1_w_ready;
+ assign T_4146_1_slave_1_w_valid = T_2711_io_slave_1_w_valid;
+ assign T_4146_1_slave_1_w_bits_data = T_2711_io_slave_1_w_bits_data;
+ assign T_4146_1_slave_1_w_bits_last = T_2711_io_slave_1_w_bits_last;
+ assign T_4146_1_slave_1_w_bits_strb = T_2711_io_slave_1_w_bits_strb;
+ assign T_4146_1_slave_1_w_bits_user = T_2711_io_slave_1_w_bits_user;
+ assign T_4146_1_slave_1_b_ready = T_2711_io_slave_1_b_ready;
+ assign T_4146_1_slave_1_b_valid = T_19768_1_b_valid;
+ assign T_4146_1_slave_1_b_bits_resp = T_19768_1_b_bits_resp;
+ assign T_4146_1_slave_1_b_bits_id = T_19768_1_b_bits_id;
+ assign T_4146_1_slave_1_b_bits_user = T_19768_1_b_bits_user;
+ assign T_4146_1_slave_1_ar_ready = T_19768_1_ar_ready;
+ assign T_4146_1_slave_1_ar_valid = T_2711_io_slave_1_ar_valid;
+ assign T_4146_1_slave_1_ar_bits_addr = T_2711_io_slave_1_ar_bits_addr;
+ assign T_4146_1_slave_1_ar_bits_len = T_2711_io_slave_1_ar_bits_len;
+ assign T_4146_1_slave_1_ar_bits_size = T_2711_io_slave_1_ar_bits_size;
+ assign T_4146_1_slave_1_ar_bits_burst = T_2711_io_slave_1_ar_bits_burst;
+ assign T_4146_1_slave_1_ar_bits_lock = T_2711_io_slave_1_ar_bits_lock;
+ assign T_4146_1_slave_1_ar_bits_cache = T_2711_io_slave_1_ar_bits_cache;
+ assign T_4146_1_slave_1_ar_bits_prot = T_2711_io_slave_1_ar_bits_prot;
+ assign T_4146_1_slave_1_ar_bits_qos = T_2711_io_slave_1_ar_bits_qos;
+ assign T_4146_1_slave_1_ar_bits_region = T_2711_io_slave_1_ar_bits_region;
+ assign T_4146_1_slave_1_ar_bits_id = T_2711_io_slave_1_ar_bits_id;
+ assign T_4146_1_slave_1_ar_bits_user = T_2711_io_slave_1_ar_bits_user;
+ assign T_4146_1_slave_1_r_ready = T_2711_io_slave_1_r_ready;
+ assign T_4146_1_slave_1_r_valid = T_19768_1_r_valid;
+ assign T_4146_1_slave_1_r_bits_resp = T_19768_1_r_bits_resp;
+ assign T_4146_1_slave_1_r_bits_data = T_19768_1_r_bits_data;
+ assign T_4146_1_slave_1_r_bits_last = T_19768_1_r_bits_last;
+ assign T_4146_1_slave_1_r_bits_id = T_19768_1_r_bits_id;
+ assign T_4146_1_slave_1_r_bits_user = T_19768_1_r_bits_user;
+ assign T_4146_1_slave_2_aw_ready = T_20405_1_aw_ready;
+ assign T_4146_1_slave_2_aw_valid = T_2711_io_slave_2_aw_valid;
+ assign T_4146_1_slave_2_aw_bits_addr = T_2711_io_slave_2_aw_bits_addr;
+ assign T_4146_1_slave_2_aw_bits_len = T_2711_io_slave_2_aw_bits_len;
+ assign T_4146_1_slave_2_aw_bits_size = T_2711_io_slave_2_aw_bits_size;
+ assign T_4146_1_slave_2_aw_bits_burst = T_2711_io_slave_2_aw_bits_burst;
+ assign T_4146_1_slave_2_aw_bits_lock = T_2711_io_slave_2_aw_bits_lock;
+ assign T_4146_1_slave_2_aw_bits_cache = T_2711_io_slave_2_aw_bits_cache;
+ assign T_4146_1_slave_2_aw_bits_prot = T_2711_io_slave_2_aw_bits_prot;
+ assign T_4146_1_slave_2_aw_bits_qos = T_2711_io_slave_2_aw_bits_qos;
+ assign T_4146_1_slave_2_aw_bits_region = T_2711_io_slave_2_aw_bits_region;
+ assign T_4146_1_slave_2_aw_bits_id = T_2711_io_slave_2_aw_bits_id;
+ assign T_4146_1_slave_2_aw_bits_user = T_2711_io_slave_2_aw_bits_user;
+ assign T_4146_1_slave_2_w_ready = T_20405_1_w_ready;
+ assign T_4146_1_slave_2_w_valid = T_2711_io_slave_2_w_valid;
+ assign T_4146_1_slave_2_w_bits_data = T_2711_io_slave_2_w_bits_data;
+ assign T_4146_1_slave_2_w_bits_last = T_2711_io_slave_2_w_bits_last;
+ assign T_4146_1_slave_2_w_bits_strb = T_2711_io_slave_2_w_bits_strb;
+ assign T_4146_1_slave_2_w_bits_user = T_2711_io_slave_2_w_bits_user;
+ assign T_4146_1_slave_2_b_ready = T_2711_io_slave_2_b_ready;
+ assign T_4146_1_slave_2_b_valid = T_20405_1_b_valid;
+ assign T_4146_1_slave_2_b_bits_resp = T_20405_1_b_bits_resp;
+ assign T_4146_1_slave_2_b_bits_id = T_20405_1_b_bits_id;
+ assign T_4146_1_slave_2_b_bits_user = T_20405_1_b_bits_user;
+ assign T_4146_1_slave_2_ar_ready = T_20405_1_ar_ready;
+ assign T_4146_1_slave_2_ar_valid = T_2711_io_slave_2_ar_valid;
+ assign T_4146_1_slave_2_ar_bits_addr = T_2711_io_slave_2_ar_bits_addr;
+ assign T_4146_1_slave_2_ar_bits_len = T_2711_io_slave_2_ar_bits_len;
+ assign T_4146_1_slave_2_ar_bits_size = T_2711_io_slave_2_ar_bits_size;
+ assign T_4146_1_slave_2_ar_bits_burst = T_2711_io_slave_2_ar_bits_burst;
+ assign T_4146_1_slave_2_ar_bits_lock = T_2711_io_slave_2_ar_bits_lock;
+ assign T_4146_1_slave_2_ar_bits_cache = T_2711_io_slave_2_ar_bits_cache;
+ assign T_4146_1_slave_2_ar_bits_prot = T_2711_io_slave_2_ar_bits_prot;
+ assign T_4146_1_slave_2_ar_bits_qos = T_2711_io_slave_2_ar_bits_qos;
+ assign T_4146_1_slave_2_ar_bits_region = T_2711_io_slave_2_ar_bits_region;
+ assign T_4146_1_slave_2_ar_bits_id = T_2711_io_slave_2_ar_bits_id;
+ assign T_4146_1_slave_2_ar_bits_user = T_2711_io_slave_2_ar_bits_user;
+ assign T_4146_1_slave_2_r_ready = T_2711_io_slave_2_r_ready;
+ assign T_4146_1_slave_2_r_valid = T_20405_1_r_valid;
+ assign T_4146_1_slave_2_r_bits_resp = T_20405_1_r_bits_resp;
+ assign T_4146_1_slave_2_r_bits_data = T_20405_1_r_bits_data;
+ assign T_4146_1_slave_2_r_bits_last = T_20405_1_r_bits_last;
+ assign T_4146_1_slave_2_r_bits_id = T_20405_1_r_bits_id;
+ assign T_4146_1_slave_2_r_bits_user = T_20405_1_r_bits_user;
+ assign T_4146_1_slave_3_aw_ready = T_21042_1_aw_ready;
+ assign T_4146_1_slave_3_aw_valid = T_2711_io_slave_3_aw_valid;
+ assign T_4146_1_slave_3_aw_bits_addr = T_2711_io_slave_3_aw_bits_addr;
+ assign T_4146_1_slave_3_aw_bits_len = T_2711_io_slave_3_aw_bits_len;
+ assign T_4146_1_slave_3_aw_bits_size = T_2711_io_slave_3_aw_bits_size;
+ assign T_4146_1_slave_3_aw_bits_burst = T_2711_io_slave_3_aw_bits_burst;
+ assign T_4146_1_slave_3_aw_bits_lock = T_2711_io_slave_3_aw_bits_lock;
+ assign T_4146_1_slave_3_aw_bits_cache = T_2711_io_slave_3_aw_bits_cache;
+ assign T_4146_1_slave_3_aw_bits_prot = T_2711_io_slave_3_aw_bits_prot;
+ assign T_4146_1_slave_3_aw_bits_qos = T_2711_io_slave_3_aw_bits_qos;
+ assign T_4146_1_slave_3_aw_bits_region = T_2711_io_slave_3_aw_bits_region;
+ assign T_4146_1_slave_3_aw_bits_id = T_2711_io_slave_3_aw_bits_id;
+ assign T_4146_1_slave_3_aw_bits_user = T_2711_io_slave_3_aw_bits_user;
+ assign T_4146_1_slave_3_w_ready = T_21042_1_w_ready;
+ assign T_4146_1_slave_3_w_valid = T_2711_io_slave_3_w_valid;
+ assign T_4146_1_slave_3_w_bits_data = T_2711_io_slave_3_w_bits_data;
+ assign T_4146_1_slave_3_w_bits_last = T_2711_io_slave_3_w_bits_last;
+ assign T_4146_1_slave_3_w_bits_strb = T_2711_io_slave_3_w_bits_strb;
+ assign T_4146_1_slave_3_w_bits_user = T_2711_io_slave_3_w_bits_user;
+ assign T_4146_1_slave_3_b_ready = T_2711_io_slave_3_b_ready;
+ assign T_4146_1_slave_3_b_valid = T_21042_1_b_valid;
+ assign T_4146_1_slave_3_b_bits_resp = T_21042_1_b_bits_resp;
+ assign T_4146_1_slave_3_b_bits_id = T_21042_1_b_bits_id;
+ assign T_4146_1_slave_3_b_bits_user = T_21042_1_b_bits_user;
+ assign T_4146_1_slave_3_ar_ready = T_21042_1_ar_ready;
+ assign T_4146_1_slave_3_ar_valid = T_2711_io_slave_3_ar_valid;
+ assign T_4146_1_slave_3_ar_bits_addr = T_2711_io_slave_3_ar_bits_addr;
+ assign T_4146_1_slave_3_ar_bits_len = T_2711_io_slave_3_ar_bits_len;
+ assign T_4146_1_slave_3_ar_bits_size = T_2711_io_slave_3_ar_bits_size;
+ assign T_4146_1_slave_3_ar_bits_burst = T_2711_io_slave_3_ar_bits_burst;
+ assign T_4146_1_slave_3_ar_bits_lock = T_2711_io_slave_3_ar_bits_lock;
+ assign T_4146_1_slave_3_ar_bits_cache = T_2711_io_slave_3_ar_bits_cache;
+ assign T_4146_1_slave_3_ar_bits_prot = T_2711_io_slave_3_ar_bits_prot;
+ assign T_4146_1_slave_3_ar_bits_qos = T_2711_io_slave_3_ar_bits_qos;
+ assign T_4146_1_slave_3_ar_bits_region = T_2711_io_slave_3_ar_bits_region;
+ assign T_4146_1_slave_3_ar_bits_id = T_2711_io_slave_3_ar_bits_id;
+ assign T_4146_1_slave_3_ar_bits_user = T_2711_io_slave_3_ar_bits_user;
+ assign T_4146_1_slave_3_r_ready = T_2711_io_slave_3_r_ready;
+ assign T_4146_1_slave_3_r_valid = T_21042_1_r_valid;
+ assign T_4146_1_slave_3_r_bits_resp = T_21042_1_r_bits_resp;
+ assign T_4146_1_slave_3_r_bits_data = T_21042_1_r_bits_data;
+ assign T_4146_1_slave_3_r_bits_last = T_21042_1_r_bits_last;
+ assign T_4146_1_slave_3_r_bits_id = T_21042_1_r_bits_id;
+ assign T_4146_1_slave_3_r_bits_user = T_21042_1_r_bits_user;
+ assign T_8449_clk = clk;
+ assign T_8449_reset = reset;
+ assign T_8449_io_master_0_aw_valid = T_10206_0_master_0_aw_valid;
+ assign T_8449_io_master_0_aw_bits_addr = T_10206_0_master_0_aw_bits_addr;
+ assign T_8449_io_master_0_aw_bits_len = T_10206_0_master_0_aw_bits_len;
+ assign T_8449_io_master_0_aw_bits_size = T_10206_0_master_0_aw_bits_size;
+ assign T_8449_io_master_0_aw_bits_burst = T_10206_0_master_0_aw_bits_burst;
+ assign T_8449_io_master_0_aw_bits_lock = T_10206_0_master_0_aw_bits_lock;
+ assign T_8449_io_master_0_aw_bits_cache = T_10206_0_master_0_aw_bits_cache;
+ assign T_8449_io_master_0_aw_bits_prot = T_10206_0_master_0_aw_bits_prot;
+ assign T_8449_io_master_0_aw_bits_qos = T_10206_0_master_0_aw_bits_qos;
+ assign T_8449_io_master_0_aw_bits_region = T_10206_0_master_0_aw_bits_region;
+ assign T_8449_io_master_0_aw_bits_id = T_10206_0_master_0_aw_bits_id;
+ assign T_8449_io_master_0_aw_bits_user = T_10206_0_master_0_aw_bits_user;
+ assign T_8449_io_master_0_w_valid = T_10206_0_master_0_w_valid;
+ assign T_8449_io_master_0_w_bits_data = T_10206_0_master_0_w_bits_data;
+ assign T_8449_io_master_0_w_bits_last = T_10206_0_master_0_w_bits_last;
+ assign T_8449_io_master_0_w_bits_strb = T_10206_0_master_0_w_bits_strb;
+ assign T_8449_io_master_0_w_bits_user = T_10206_0_master_0_w_bits_user;
+ assign T_8449_io_master_0_b_ready = T_10206_0_master_0_b_ready;
+ assign T_8449_io_master_0_ar_valid = T_10206_0_master_0_ar_valid;
+ assign T_8449_io_master_0_ar_bits_addr = T_10206_0_master_0_ar_bits_addr;
+ assign T_8449_io_master_0_ar_bits_len = T_10206_0_master_0_ar_bits_len;
+ assign T_8449_io_master_0_ar_bits_size = T_10206_0_master_0_ar_bits_size;
+ assign T_8449_io_master_0_ar_bits_burst = T_10206_0_master_0_ar_bits_burst;
+ assign T_8449_io_master_0_ar_bits_lock = T_10206_0_master_0_ar_bits_lock;
+ assign T_8449_io_master_0_ar_bits_cache = T_10206_0_master_0_ar_bits_cache;
+ assign T_8449_io_master_0_ar_bits_prot = T_10206_0_master_0_ar_bits_prot;
+ assign T_8449_io_master_0_ar_bits_qos = T_10206_0_master_0_ar_bits_qos;
+ assign T_8449_io_master_0_ar_bits_region = T_10206_0_master_0_ar_bits_region;
+ assign T_8449_io_master_0_ar_bits_id = T_10206_0_master_0_ar_bits_id;
+ assign T_8449_io_master_0_ar_bits_user = T_10206_0_master_0_ar_bits_user;
+ assign T_8449_io_master_0_r_ready = T_10206_0_master_0_r_ready;
+ assign T_8449_io_master_1_aw_valid = T_10206_0_master_1_aw_valid;
+ assign T_8449_io_master_1_aw_bits_addr = T_10206_0_master_1_aw_bits_addr;
+ assign T_8449_io_master_1_aw_bits_len = T_10206_0_master_1_aw_bits_len;
+ assign T_8449_io_master_1_aw_bits_size = T_10206_0_master_1_aw_bits_size;
+ assign T_8449_io_master_1_aw_bits_burst = T_10206_0_master_1_aw_bits_burst;
+ assign T_8449_io_master_1_aw_bits_lock = T_10206_0_master_1_aw_bits_lock;
+ assign T_8449_io_master_1_aw_bits_cache = T_10206_0_master_1_aw_bits_cache;
+ assign T_8449_io_master_1_aw_bits_prot = T_10206_0_master_1_aw_bits_prot;
+ assign T_8449_io_master_1_aw_bits_qos = T_10206_0_master_1_aw_bits_qos;
+ assign T_8449_io_master_1_aw_bits_region = T_10206_0_master_1_aw_bits_region;
+ assign T_8449_io_master_1_aw_bits_id = T_10206_0_master_1_aw_bits_id;
+ assign T_8449_io_master_1_aw_bits_user = T_10206_0_master_1_aw_bits_user;
+ assign T_8449_io_master_1_w_valid = T_10206_0_master_1_w_valid;
+ assign T_8449_io_master_1_w_bits_data = T_10206_0_master_1_w_bits_data;
+ assign T_8449_io_master_1_w_bits_last = T_10206_0_master_1_w_bits_last;
+ assign T_8449_io_master_1_w_bits_strb = T_10206_0_master_1_w_bits_strb;
+ assign T_8449_io_master_1_w_bits_user = T_10206_0_master_1_w_bits_user;
+ assign T_8449_io_master_1_b_ready = T_10206_0_master_1_b_ready;
+ assign T_8449_io_master_1_ar_valid = T_10206_0_master_1_ar_valid;
+ assign T_8449_io_master_1_ar_bits_addr = T_10206_0_master_1_ar_bits_addr;
+ assign T_8449_io_master_1_ar_bits_len = T_10206_0_master_1_ar_bits_len;
+ assign T_8449_io_master_1_ar_bits_size = T_10206_0_master_1_ar_bits_size;
+ assign T_8449_io_master_1_ar_bits_burst = T_10206_0_master_1_ar_bits_burst;
+ assign T_8449_io_master_1_ar_bits_lock = T_10206_0_master_1_ar_bits_lock;
+ assign T_8449_io_master_1_ar_bits_cache = T_10206_0_master_1_ar_bits_cache;
+ assign T_8449_io_master_1_ar_bits_prot = T_10206_0_master_1_ar_bits_prot;
+ assign T_8449_io_master_1_ar_bits_qos = T_10206_0_master_1_ar_bits_qos;
+ assign T_8449_io_master_1_ar_bits_region = T_10206_0_master_1_ar_bits_region;
+ assign T_8449_io_master_1_ar_bits_id = T_10206_0_master_1_ar_bits_id;
+ assign T_8449_io_master_1_ar_bits_user = T_10206_0_master_1_ar_bits_user;
+ assign T_8449_io_master_1_r_ready = T_10206_0_master_1_r_ready;
+ assign T_8449_io_slave_aw_ready = T_10206_0_slave_aw_ready;
+ assign T_8449_io_slave_w_ready = T_10206_0_slave_w_ready;
+ assign T_8449_io_slave_b_valid = T_10206_0_slave_b_valid;
+ assign T_8449_io_slave_b_bits_resp = T_10206_0_slave_b_bits_resp;
+ assign T_8449_io_slave_b_bits_id = T_10206_0_slave_b_bits_id;
+ assign T_8449_io_slave_b_bits_user = T_10206_0_slave_b_bits_user;
+ assign T_8449_io_slave_ar_ready = T_10206_0_slave_ar_ready;
+ assign T_8449_io_slave_r_valid = T_10206_0_slave_r_valid;
+ assign T_8449_io_slave_r_bits_resp = T_10206_0_slave_r_bits_resp;
+ assign T_8449_io_slave_r_bits_data = T_10206_0_slave_r_bits_data;
+ assign T_8449_io_slave_r_bits_last = T_10206_0_slave_r_bits_last;
+ assign T_8449_io_slave_r_bits_id = T_10206_0_slave_r_bits_id;
+ assign T_8449_io_slave_r_bits_user = T_10206_0_slave_r_bits_user;
+ assign T_8450_clk = clk;
+ assign T_8450_reset = reset;
+ assign T_8450_io_master_0_aw_valid = T_10206_1_master_0_aw_valid;
+ assign T_8450_io_master_0_aw_bits_addr = T_10206_1_master_0_aw_bits_addr;
+ assign T_8450_io_master_0_aw_bits_len = T_10206_1_master_0_aw_bits_len;
+ assign T_8450_io_master_0_aw_bits_size = T_10206_1_master_0_aw_bits_size;
+ assign T_8450_io_master_0_aw_bits_burst = T_10206_1_master_0_aw_bits_burst;
+ assign T_8450_io_master_0_aw_bits_lock = T_10206_1_master_0_aw_bits_lock;
+ assign T_8450_io_master_0_aw_bits_cache = T_10206_1_master_0_aw_bits_cache;
+ assign T_8450_io_master_0_aw_bits_prot = T_10206_1_master_0_aw_bits_prot;
+ assign T_8450_io_master_0_aw_bits_qos = T_10206_1_master_0_aw_bits_qos;
+ assign T_8450_io_master_0_aw_bits_region = T_10206_1_master_0_aw_bits_region;
+ assign T_8450_io_master_0_aw_bits_id = T_10206_1_master_0_aw_bits_id;
+ assign T_8450_io_master_0_aw_bits_user = T_10206_1_master_0_aw_bits_user;
+ assign T_8450_io_master_0_w_valid = T_10206_1_master_0_w_valid;
+ assign T_8450_io_master_0_w_bits_data = T_10206_1_master_0_w_bits_data;
+ assign T_8450_io_master_0_w_bits_last = T_10206_1_master_0_w_bits_last;
+ assign T_8450_io_master_0_w_bits_strb = T_10206_1_master_0_w_bits_strb;
+ assign T_8450_io_master_0_w_bits_user = T_10206_1_master_0_w_bits_user;
+ assign T_8450_io_master_0_b_ready = T_10206_1_master_0_b_ready;
+ assign T_8450_io_master_0_ar_valid = T_10206_1_master_0_ar_valid;
+ assign T_8450_io_master_0_ar_bits_addr = T_10206_1_master_0_ar_bits_addr;
+ assign T_8450_io_master_0_ar_bits_len = T_10206_1_master_0_ar_bits_len;
+ assign T_8450_io_master_0_ar_bits_size = T_10206_1_master_0_ar_bits_size;
+ assign T_8450_io_master_0_ar_bits_burst = T_10206_1_master_0_ar_bits_burst;
+ assign T_8450_io_master_0_ar_bits_lock = T_10206_1_master_0_ar_bits_lock;
+ assign T_8450_io_master_0_ar_bits_cache = T_10206_1_master_0_ar_bits_cache;
+ assign T_8450_io_master_0_ar_bits_prot = T_10206_1_master_0_ar_bits_prot;
+ assign T_8450_io_master_0_ar_bits_qos = T_10206_1_master_0_ar_bits_qos;
+ assign T_8450_io_master_0_ar_bits_region = T_10206_1_master_0_ar_bits_region;
+ assign T_8450_io_master_0_ar_bits_id = T_10206_1_master_0_ar_bits_id;
+ assign T_8450_io_master_0_ar_bits_user = T_10206_1_master_0_ar_bits_user;
+ assign T_8450_io_master_0_r_ready = T_10206_1_master_0_r_ready;
+ assign T_8450_io_master_1_aw_valid = T_10206_1_master_1_aw_valid;
+ assign T_8450_io_master_1_aw_bits_addr = T_10206_1_master_1_aw_bits_addr;
+ assign T_8450_io_master_1_aw_bits_len = T_10206_1_master_1_aw_bits_len;
+ assign T_8450_io_master_1_aw_bits_size = T_10206_1_master_1_aw_bits_size;
+ assign T_8450_io_master_1_aw_bits_burst = T_10206_1_master_1_aw_bits_burst;
+ assign T_8450_io_master_1_aw_bits_lock = T_10206_1_master_1_aw_bits_lock;
+ assign T_8450_io_master_1_aw_bits_cache = T_10206_1_master_1_aw_bits_cache;
+ assign T_8450_io_master_1_aw_bits_prot = T_10206_1_master_1_aw_bits_prot;
+ assign T_8450_io_master_1_aw_bits_qos = T_10206_1_master_1_aw_bits_qos;
+ assign T_8450_io_master_1_aw_bits_region = T_10206_1_master_1_aw_bits_region;
+ assign T_8450_io_master_1_aw_bits_id = T_10206_1_master_1_aw_bits_id;
+ assign T_8450_io_master_1_aw_bits_user = T_10206_1_master_1_aw_bits_user;
+ assign T_8450_io_master_1_w_valid = T_10206_1_master_1_w_valid;
+ assign T_8450_io_master_1_w_bits_data = T_10206_1_master_1_w_bits_data;
+ assign T_8450_io_master_1_w_bits_last = T_10206_1_master_1_w_bits_last;
+ assign T_8450_io_master_1_w_bits_strb = T_10206_1_master_1_w_bits_strb;
+ assign T_8450_io_master_1_w_bits_user = T_10206_1_master_1_w_bits_user;
+ assign T_8450_io_master_1_b_ready = T_10206_1_master_1_b_ready;
+ assign T_8450_io_master_1_ar_valid = T_10206_1_master_1_ar_valid;
+ assign T_8450_io_master_1_ar_bits_addr = T_10206_1_master_1_ar_bits_addr;
+ assign T_8450_io_master_1_ar_bits_len = T_10206_1_master_1_ar_bits_len;
+ assign T_8450_io_master_1_ar_bits_size = T_10206_1_master_1_ar_bits_size;
+ assign T_8450_io_master_1_ar_bits_burst = T_10206_1_master_1_ar_bits_burst;
+ assign T_8450_io_master_1_ar_bits_lock = T_10206_1_master_1_ar_bits_lock;
+ assign T_8450_io_master_1_ar_bits_cache = T_10206_1_master_1_ar_bits_cache;
+ assign T_8450_io_master_1_ar_bits_prot = T_10206_1_master_1_ar_bits_prot;
+ assign T_8450_io_master_1_ar_bits_qos = T_10206_1_master_1_ar_bits_qos;
+ assign T_8450_io_master_1_ar_bits_region = T_10206_1_master_1_ar_bits_region;
+ assign T_8450_io_master_1_ar_bits_id = T_10206_1_master_1_ar_bits_id;
+ assign T_8450_io_master_1_ar_bits_user = T_10206_1_master_1_ar_bits_user;
+ assign T_8450_io_master_1_r_ready = T_10206_1_master_1_r_ready;
+ assign T_8450_io_slave_aw_ready = T_10206_1_slave_aw_ready;
+ assign T_8450_io_slave_w_ready = T_10206_1_slave_w_ready;
+ assign T_8450_io_slave_b_valid = T_10206_1_slave_b_valid;
+ assign T_8450_io_slave_b_bits_resp = T_10206_1_slave_b_bits_resp;
+ assign T_8450_io_slave_b_bits_id = T_10206_1_slave_b_bits_id;
+ assign T_8450_io_slave_b_bits_user = T_10206_1_slave_b_bits_user;
+ assign T_8450_io_slave_ar_ready = T_10206_1_slave_ar_ready;
+ assign T_8450_io_slave_r_valid = T_10206_1_slave_r_valid;
+ assign T_8450_io_slave_r_bits_resp = T_10206_1_slave_r_bits_resp;
+ assign T_8450_io_slave_r_bits_data = T_10206_1_slave_r_bits_data;
+ assign T_8450_io_slave_r_bits_last = T_10206_1_slave_r_bits_last;
+ assign T_8450_io_slave_r_bits_id = T_10206_1_slave_r_bits_id;
+ assign T_8450_io_slave_r_bits_user = T_10206_1_slave_r_bits_user;
+ assign T_8451_clk = clk;
+ assign T_8451_reset = reset;
+ assign T_8451_io_master_0_aw_valid = T_10206_2_master_0_aw_valid;
+ assign T_8451_io_master_0_aw_bits_addr = T_10206_2_master_0_aw_bits_addr;
+ assign T_8451_io_master_0_aw_bits_len = T_10206_2_master_0_aw_bits_len;
+ assign T_8451_io_master_0_aw_bits_size = T_10206_2_master_0_aw_bits_size;
+ assign T_8451_io_master_0_aw_bits_burst = T_10206_2_master_0_aw_bits_burst;
+ assign T_8451_io_master_0_aw_bits_lock = T_10206_2_master_0_aw_bits_lock;
+ assign T_8451_io_master_0_aw_bits_cache = T_10206_2_master_0_aw_bits_cache;
+ assign T_8451_io_master_0_aw_bits_prot = T_10206_2_master_0_aw_bits_prot;
+ assign T_8451_io_master_0_aw_bits_qos = T_10206_2_master_0_aw_bits_qos;
+ assign T_8451_io_master_0_aw_bits_region = T_10206_2_master_0_aw_bits_region;
+ assign T_8451_io_master_0_aw_bits_id = T_10206_2_master_0_aw_bits_id;
+ assign T_8451_io_master_0_aw_bits_user = T_10206_2_master_0_aw_bits_user;
+ assign T_8451_io_master_0_w_valid = T_10206_2_master_0_w_valid;
+ assign T_8451_io_master_0_w_bits_data = T_10206_2_master_0_w_bits_data;
+ assign T_8451_io_master_0_w_bits_last = T_10206_2_master_0_w_bits_last;
+ assign T_8451_io_master_0_w_bits_strb = T_10206_2_master_0_w_bits_strb;
+ assign T_8451_io_master_0_w_bits_user = T_10206_2_master_0_w_bits_user;
+ assign T_8451_io_master_0_b_ready = T_10206_2_master_0_b_ready;
+ assign T_8451_io_master_0_ar_valid = T_10206_2_master_0_ar_valid;
+ assign T_8451_io_master_0_ar_bits_addr = T_10206_2_master_0_ar_bits_addr;
+ assign T_8451_io_master_0_ar_bits_len = T_10206_2_master_0_ar_bits_len;
+ assign T_8451_io_master_0_ar_bits_size = T_10206_2_master_0_ar_bits_size;
+ assign T_8451_io_master_0_ar_bits_burst = T_10206_2_master_0_ar_bits_burst;
+ assign T_8451_io_master_0_ar_bits_lock = T_10206_2_master_0_ar_bits_lock;
+ assign T_8451_io_master_0_ar_bits_cache = T_10206_2_master_0_ar_bits_cache;
+ assign T_8451_io_master_0_ar_bits_prot = T_10206_2_master_0_ar_bits_prot;
+ assign T_8451_io_master_0_ar_bits_qos = T_10206_2_master_0_ar_bits_qos;
+ assign T_8451_io_master_0_ar_bits_region = T_10206_2_master_0_ar_bits_region;
+ assign T_8451_io_master_0_ar_bits_id = T_10206_2_master_0_ar_bits_id;
+ assign T_8451_io_master_0_ar_bits_user = T_10206_2_master_0_ar_bits_user;
+ assign T_8451_io_master_0_r_ready = T_10206_2_master_0_r_ready;
+ assign T_8451_io_master_1_aw_valid = T_10206_2_master_1_aw_valid;
+ assign T_8451_io_master_1_aw_bits_addr = T_10206_2_master_1_aw_bits_addr;
+ assign T_8451_io_master_1_aw_bits_len = T_10206_2_master_1_aw_bits_len;
+ assign T_8451_io_master_1_aw_bits_size = T_10206_2_master_1_aw_bits_size;
+ assign T_8451_io_master_1_aw_bits_burst = T_10206_2_master_1_aw_bits_burst;
+ assign T_8451_io_master_1_aw_bits_lock = T_10206_2_master_1_aw_bits_lock;
+ assign T_8451_io_master_1_aw_bits_cache = T_10206_2_master_1_aw_bits_cache;
+ assign T_8451_io_master_1_aw_bits_prot = T_10206_2_master_1_aw_bits_prot;
+ assign T_8451_io_master_1_aw_bits_qos = T_10206_2_master_1_aw_bits_qos;
+ assign T_8451_io_master_1_aw_bits_region = T_10206_2_master_1_aw_bits_region;
+ assign T_8451_io_master_1_aw_bits_id = T_10206_2_master_1_aw_bits_id;
+ assign T_8451_io_master_1_aw_bits_user = T_10206_2_master_1_aw_bits_user;
+ assign T_8451_io_master_1_w_valid = T_10206_2_master_1_w_valid;
+ assign T_8451_io_master_1_w_bits_data = T_10206_2_master_1_w_bits_data;
+ assign T_8451_io_master_1_w_bits_last = T_10206_2_master_1_w_bits_last;
+ assign T_8451_io_master_1_w_bits_strb = T_10206_2_master_1_w_bits_strb;
+ assign T_8451_io_master_1_w_bits_user = T_10206_2_master_1_w_bits_user;
+ assign T_8451_io_master_1_b_ready = T_10206_2_master_1_b_ready;
+ assign T_8451_io_master_1_ar_valid = T_10206_2_master_1_ar_valid;
+ assign T_8451_io_master_1_ar_bits_addr = T_10206_2_master_1_ar_bits_addr;
+ assign T_8451_io_master_1_ar_bits_len = T_10206_2_master_1_ar_bits_len;
+ assign T_8451_io_master_1_ar_bits_size = T_10206_2_master_1_ar_bits_size;
+ assign T_8451_io_master_1_ar_bits_burst = T_10206_2_master_1_ar_bits_burst;
+ assign T_8451_io_master_1_ar_bits_lock = T_10206_2_master_1_ar_bits_lock;
+ assign T_8451_io_master_1_ar_bits_cache = T_10206_2_master_1_ar_bits_cache;
+ assign T_8451_io_master_1_ar_bits_prot = T_10206_2_master_1_ar_bits_prot;
+ assign T_8451_io_master_1_ar_bits_qos = T_10206_2_master_1_ar_bits_qos;
+ assign T_8451_io_master_1_ar_bits_region = T_10206_2_master_1_ar_bits_region;
+ assign T_8451_io_master_1_ar_bits_id = T_10206_2_master_1_ar_bits_id;
+ assign T_8451_io_master_1_ar_bits_user = T_10206_2_master_1_ar_bits_user;
+ assign T_8451_io_master_1_r_ready = T_10206_2_master_1_r_ready;
+ assign T_8451_io_slave_aw_ready = T_10206_2_slave_aw_ready;
+ assign T_8451_io_slave_w_ready = T_10206_2_slave_w_ready;
+ assign T_8451_io_slave_b_valid = T_10206_2_slave_b_valid;
+ assign T_8451_io_slave_b_bits_resp = T_10206_2_slave_b_bits_resp;
+ assign T_8451_io_slave_b_bits_id = T_10206_2_slave_b_bits_id;
+ assign T_8451_io_slave_b_bits_user = T_10206_2_slave_b_bits_user;
+ assign T_8451_io_slave_ar_ready = T_10206_2_slave_ar_ready;
+ assign T_8451_io_slave_r_valid = T_10206_2_slave_r_valid;
+ assign T_8451_io_slave_r_bits_resp = T_10206_2_slave_r_bits_resp;
+ assign T_8451_io_slave_r_bits_data = T_10206_2_slave_r_bits_data;
+ assign T_8451_io_slave_r_bits_last = T_10206_2_slave_r_bits_last;
+ assign T_8451_io_slave_r_bits_id = T_10206_2_slave_r_bits_id;
+ assign T_8451_io_slave_r_bits_user = T_10206_2_slave_r_bits_user;
+ assign T_8452_clk = clk;
+ assign T_8452_reset = reset;
+ assign T_8452_io_master_0_aw_valid = T_10206_3_master_0_aw_valid;
+ assign T_8452_io_master_0_aw_bits_addr = T_10206_3_master_0_aw_bits_addr;
+ assign T_8452_io_master_0_aw_bits_len = T_10206_3_master_0_aw_bits_len;
+ assign T_8452_io_master_0_aw_bits_size = T_10206_3_master_0_aw_bits_size;
+ assign T_8452_io_master_0_aw_bits_burst = T_10206_3_master_0_aw_bits_burst;
+ assign T_8452_io_master_0_aw_bits_lock = T_10206_3_master_0_aw_bits_lock;
+ assign T_8452_io_master_0_aw_bits_cache = T_10206_3_master_0_aw_bits_cache;
+ assign T_8452_io_master_0_aw_bits_prot = T_10206_3_master_0_aw_bits_prot;
+ assign T_8452_io_master_0_aw_bits_qos = T_10206_3_master_0_aw_bits_qos;
+ assign T_8452_io_master_0_aw_bits_region = T_10206_3_master_0_aw_bits_region;
+ assign T_8452_io_master_0_aw_bits_id = T_10206_3_master_0_aw_bits_id;
+ assign T_8452_io_master_0_aw_bits_user = T_10206_3_master_0_aw_bits_user;
+ assign T_8452_io_master_0_w_valid = T_10206_3_master_0_w_valid;
+ assign T_8452_io_master_0_w_bits_data = T_10206_3_master_0_w_bits_data;
+ assign T_8452_io_master_0_w_bits_last = T_10206_3_master_0_w_bits_last;
+ assign T_8452_io_master_0_w_bits_strb = T_10206_3_master_0_w_bits_strb;
+ assign T_8452_io_master_0_w_bits_user = T_10206_3_master_0_w_bits_user;
+ assign T_8452_io_master_0_b_ready = T_10206_3_master_0_b_ready;
+ assign T_8452_io_master_0_ar_valid = T_10206_3_master_0_ar_valid;
+ assign T_8452_io_master_0_ar_bits_addr = T_10206_3_master_0_ar_bits_addr;
+ assign T_8452_io_master_0_ar_bits_len = T_10206_3_master_0_ar_bits_len;
+ assign T_8452_io_master_0_ar_bits_size = T_10206_3_master_0_ar_bits_size;
+ assign T_8452_io_master_0_ar_bits_burst = T_10206_3_master_0_ar_bits_burst;
+ assign T_8452_io_master_0_ar_bits_lock = T_10206_3_master_0_ar_bits_lock;
+ assign T_8452_io_master_0_ar_bits_cache = T_10206_3_master_0_ar_bits_cache;
+ assign T_8452_io_master_0_ar_bits_prot = T_10206_3_master_0_ar_bits_prot;
+ assign T_8452_io_master_0_ar_bits_qos = T_10206_3_master_0_ar_bits_qos;
+ assign T_8452_io_master_0_ar_bits_region = T_10206_3_master_0_ar_bits_region;
+ assign T_8452_io_master_0_ar_bits_id = T_10206_3_master_0_ar_bits_id;
+ assign T_8452_io_master_0_ar_bits_user = T_10206_3_master_0_ar_bits_user;
+ assign T_8452_io_master_0_r_ready = T_10206_3_master_0_r_ready;
+ assign T_8452_io_master_1_aw_valid = T_10206_3_master_1_aw_valid;
+ assign T_8452_io_master_1_aw_bits_addr = T_10206_3_master_1_aw_bits_addr;
+ assign T_8452_io_master_1_aw_bits_len = T_10206_3_master_1_aw_bits_len;
+ assign T_8452_io_master_1_aw_bits_size = T_10206_3_master_1_aw_bits_size;
+ assign T_8452_io_master_1_aw_bits_burst = T_10206_3_master_1_aw_bits_burst;
+ assign T_8452_io_master_1_aw_bits_lock = T_10206_3_master_1_aw_bits_lock;
+ assign T_8452_io_master_1_aw_bits_cache = T_10206_3_master_1_aw_bits_cache;
+ assign T_8452_io_master_1_aw_bits_prot = T_10206_3_master_1_aw_bits_prot;
+ assign T_8452_io_master_1_aw_bits_qos = T_10206_3_master_1_aw_bits_qos;
+ assign T_8452_io_master_1_aw_bits_region = T_10206_3_master_1_aw_bits_region;
+ assign T_8452_io_master_1_aw_bits_id = T_10206_3_master_1_aw_bits_id;
+ assign T_8452_io_master_1_aw_bits_user = T_10206_3_master_1_aw_bits_user;
+ assign T_8452_io_master_1_w_valid = T_10206_3_master_1_w_valid;
+ assign T_8452_io_master_1_w_bits_data = T_10206_3_master_1_w_bits_data;
+ assign T_8452_io_master_1_w_bits_last = T_10206_3_master_1_w_bits_last;
+ assign T_8452_io_master_1_w_bits_strb = T_10206_3_master_1_w_bits_strb;
+ assign T_8452_io_master_1_w_bits_user = T_10206_3_master_1_w_bits_user;
+ assign T_8452_io_master_1_b_ready = T_10206_3_master_1_b_ready;
+ assign T_8452_io_master_1_ar_valid = T_10206_3_master_1_ar_valid;
+ assign T_8452_io_master_1_ar_bits_addr = T_10206_3_master_1_ar_bits_addr;
+ assign T_8452_io_master_1_ar_bits_len = T_10206_3_master_1_ar_bits_len;
+ assign T_8452_io_master_1_ar_bits_size = T_10206_3_master_1_ar_bits_size;
+ assign T_8452_io_master_1_ar_bits_burst = T_10206_3_master_1_ar_bits_burst;
+ assign T_8452_io_master_1_ar_bits_lock = T_10206_3_master_1_ar_bits_lock;
+ assign T_8452_io_master_1_ar_bits_cache = T_10206_3_master_1_ar_bits_cache;
+ assign T_8452_io_master_1_ar_bits_prot = T_10206_3_master_1_ar_bits_prot;
+ assign T_8452_io_master_1_ar_bits_qos = T_10206_3_master_1_ar_bits_qos;
+ assign T_8452_io_master_1_ar_bits_region = T_10206_3_master_1_ar_bits_region;
+ assign T_8452_io_master_1_ar_bits_id = T_10206_3_master_1_ar_bits_id;
+ assign T_8452_io_master_1_ar_bits_user = T_10206_3_master_1_ar_bits_user;
+ assign T_8452_io_master_1_r_ready = T_10206_3_master_1_r_ready;
+ assign T_8452_io_slave_aw_ready = T_10206_3_slave_aw_ready;
+ assign T_8452_io_slave_w_ready = T_10206_3_slave_w_ready;
+ assign T_8452_io_slave_b_valid = T_10206_3_slave_b_valid;
+ assign T_8452_io_slave_b_bits_resp = T_10206_3_slave_b_bits_resp;
+ assign T_8452_io_slave_b_bits_id = T_10206_3_slave_b_bits_id;
+ assign T_8452_io_slave_b_bits_user = T_10206_3_slave_b_bits_user;
+ assign T_8452_io_slave_ar_ready = T_10206_3_slave_ar_ready;
+ assign T_8452_io_slave_r_valid = T_10206_3_slave_r_valid;
+ assign T_8452_io_slave_r_bits_resp = T_10206_3_slave_r_bits_resp;
+ assign T_8452_io_slave_r_bits_data = T_10206_3_slave_r_bits_data;
+ assign T_8452_io_slave_r_bits_last = T_10206_3_slave_r_bits_last;
+ assign T_8452_io_slave_r_bits_id = T_10206_3_slave_r_bits_id;
+ assign T_8452_io_slave_r_bits_user = T_10206_3_slave_r_bits_user;
+ assign T_10206_0_master_0_aw_ready = T_8449_io_master_0_aw_ready;
+ assign T_10206_0_master_0_aw_valid = T_19131_0_aw_valid;
+ assign T_10206_0_master_0_aw_bits_addr = T_19131_0_aw_bits_addr;
+ assign T_10206_0_master_0_aw_bits_len = T_19131_0_aw_bits_len;
+ assign T_10206_0_master_0_aw_bits_size = T_19131_0_aw_bits_size;
+ assign T_10206_0_master_0_aw_bits_burst = T_19131_0_aw_bits_burst;
+ assign T_10206_0_master_0_aw_bits_lock = T_19131_0_aw_bits_lock;
+ assign T_10206_0_master_0_aw_bits_cache = T_19131_0_aw_bits_cache;
+ assign T_10206_0_master_0_aw_bits_prot = T_19131_0_aw_bits_prot;
+ assign T_10206_0_master_0_aw_bits_qos = T_19131_0_aw_bits_qos;
+ assign T_10206_0_master_0_aw_bits_region = T_19131_0_aw_bits_region;
+ assign T_10206_0_master_0_aw_bits_id = T_19131_0_aw_bits_id;
+ assign T_10206_0_master_0_aw_bits_user = T_19131_0_aw_bits_user;
+ assign T_10206_0_master_0_w_ready = T_8449_io_master_0_w_ready;
+ assign T_10206_0_master_0_w_valid = T_19131_0_w_valid;
+ assign T_10206_0_master_0_w_bits_data = T_19131_0_w_bits_data;
+ assign T_10206_0_master_0_w_bits_last = T_19131_0_w_bits_last;
+ assign T_10206_0_master_0_w_bits_strb = T_19131_0_w_bits_strb;
+ assign T_10206_0_master_0_w_bits_user = T_19131_0_w_bits_user;
+ assign T_10206_0_master_0_b_ready = T_19131_0_b_ready;
+ assign T_10206_0_master_0_b_valid = T_8449_io_master_0_b_valid;
+ assign T_10206_0_master_0_b_bits_resp = T_8449_io_master_0_b_bits_resp;
+ assign T_10206_0_master_0_b_bits_id = T_8449_io_master_0_b_bits_id;
+ assign T_10206_0_master_0_b_bits_user = T_8449_io_master_0_b_bits_user;
+ assign T_10206_0_master_0_ar_ready = T_8449_io_master_0_ar_ready;
+ assign T_10206_0_master_0_ar_valid = T_19131_0_ar_valid;
+ assign T_10206_0_master_0_ar_bits_addr = T_19131_0_ar_bits_addr;
+ assign T_10206_0_master_0_ar_bits_len = T_19131_0_ar_bits_len;
+ assign T_10206_0_master_0_ar_bits_size = T_19131_0_ar_bits_size;
+ assign T_10206_0_master_0_ar_bits_burst = T_19131_0_ar_bits_burst;
+ assign T_10206_0_master_0_ar_bits_lock = T_19131_0_ar_bits_lock;
+ assign T_10206_0_master_0_ar_bits_cache = T_19131_0_ar_bits_cache;
+ assign T_10206_0_master_0_ar_bits_prot = T_19131_0_ar_bits_prot;
+ assign T_10206_0_master_0_ar_bits_qos = T_19131_0_ar_bits_qos;
+ assign T_10206_0_master_0_ar_bits_region = T_19131_0_ar_bits_region;
+ assign T_10206_0_master_0_ar_bits_id = T_19131_0_ar_bits_id;
+ assign T_10206_0_master_0_ar_bits_user = T_19131_0_ar_bits_user;
+ assign T_10206_0_master_0_r_ready = T_19131_0_r_ready;
+ assign T_10206_0_master_0_r_valid = T_8449_io_master_0_r_valid;
+ assign T_10206_0_master_0_r_bits_resp = T_8449_io_master_0_r_bits_resp;
+ assign T_10206_0_master_0_r_bits_data = T_8449_io_master_0_r_bits_data;
+ assign T_10206_0_master_0_r_bits_last = T_8449_io_master_0_r_bits_last;
+ assign T_10206_0_master_0_r_bits_id = T_8449_io_master_0_r_bits_id;
+ assign T_10206_0_master_0_r_bits_user = T_8449_io_master_0_r_bits_user;
+ assign T_10206_0_master_1_aw_ready = T_8449_io_master_1_aw_ready;
+ assign T_10206_0_master_1_aw_valid = T_19131_1_aw_valid;
+ assign T_10206_0_master_1_aw_bits_addr = T_19131_1_aw_bits_addr;
+ assign T_10206_0_master_1_aw_bits_len = T_19131_1_aw_bits_len;
+ assign T_10206_0_master_1_aw_bits_size = T_19131_1_aw_bits_size;
+ assign T_10206_0_master_1_aw_bits_burst = T_19131_1_aw_bits_burst;
+ assign T_10206_0_master_1_aw_bits_lock = T_19131_1_aw_bits_lock;
+ assign T_10206_0_master_1_aw_bits_cache = T_19131_1_aw_bits_cache;
+ assign T_10206_0_master_1_aw_bits_prot = T_19131_1_aw_bits_prot;
+ assign T_10206_0_master_1_aw_bits_qos = T_19131_1_aw_bits_qos;
+ assign T_10206_0_master_1_aw_bits_region = T_19131_1_aw_bits_region;
+ assign T_10206_0_master_1_aw_bits_id = T_19131_1_aw_bits_id;
+ assign T_10206_0_master_1_aw_bits_user = T_19131_1_aw_bits_user;
+ assign T_10206_0_master_1_w_ready = T_8449_io_master_1_w_ready;
+ assign T_10206_0_master_1_w_valid = T_19131_1_w_valid;
+ assign T_10206_0_master_1_w_bits_data = T_19131_1_w_bits_data;
+ assign T_10206_0_master_1_w_bits_last = T_19131_1_w_bits_last;
+ assign T_10206_0_master_1_w_bits_strb = T_19131_1_w_bits_strb;
+ assign T_10206_0_master_1_w_bits_user = T_19131_1_w_bits_user;
+ assign T_10206_0_master_1_b_ready = T_19131_1_b_ready;
+ assign T_10206_0_master_1_b_valid = T_8449_io_master_1_b_valid;
+ assign T_10206_0_master_1_b_bits_resp = T_8449_io_master_1_b_bits_resp;
+ assign T_10206_0_master_1_b_bits_id = T_8449_io_master_1_b_bits_id;
+ assign T_10206_0_master_1_b_bits_user = T_8449_io_master_1_b_bits_user;
+ assign T_10206_0_master_1_ar_ready = T_8449_io_master_1_ar_ready;
+ assign T_10206_0_master_1_ar_valid = T_19131_1_ar_valid;
+ assign T_10206_0_master_1_ar_bits_addr = T_19131_1_ar_bits_addr;
+ assign T_10206_0_master_1_ar_bits_len = T_19131_1_ar_bits_len;
+ assign T_10206_0_master_1_ar_bits_size = T_19131_1_ar_bits_size;
+ assign T_10206_0_master_1_ar_bits_burst = T_19131_1_ar_bits_burst;
+ assign T_10206_0_master_1_ar_bits_lock = T_19131_1_ar_bits_lock;
+ assign T_10206_0_master_1_ar_bits_cache = T_19131_1_ar_bits_cache;
+ assign T_10206_0_master_1_ar_bits_prot = T_19131_1_ar_bits_prot;
+ assign T_10206_0_master_1_ar_bits_qos = T_19131_1_ar_bits_qos;
+ assign T_10206_0_master_1_ar_bits_region = T_19131_1_ar_bits_region;
+ assign T_10206_0_master_1_ar_bits_id = T_19131_1_ar_bits_id;
+ assign T_10206_0_master_1_ar_bits_user = T_19131_1_ar_bits_user;
+ assign T_10206_0_master_1_r_ready = T_19131_1_r_ready;
+ assign T_10206_0_master_1_r_valid = T_8449_io_master_1_r_valid;
+ assign T_10206_0_master_1_r_bits_resp = T_8449_io_master_1_r_bits_resp;
+ assign T_10206_0_master_1_r_bits_data = T_8449_io_master_1_r_bits_data;
+ assign T_10206_0_master_1_r_bits_last = T_8449_io_master_1_r_bits_last;
+ assign T_10206_0_master_1_r_bits_id = T_8449_io_master_1_r_bits_id;
+ assign T_10206_0_master_1_r_bits_user = T_8449_io_master_1_r_bits_user;
+ assign T_10206_0_slave_aw_ready = io_slaves_0_aw_ready;
+ assign T_10206_0_slave_aw_valid = T_8449_io_slave_aw_valid;
+ assign T_10206_0_slave_aw_bits_addr = T_8449_io_slave_aw_bits_addr;
+ assign T_10206_0_slave_aw_bits_len = T_8449_io_slave_aw_bits_len;
+ assign T_10206_0_slave_aw_bits_size = T_8449_io_slave_aw_bits_size;
+ assign T_10206_0_slave_aw_bits_burst = T_8449_io_slave_aw_bits_burst;
+ assign T_10206_0_slave_aw_bits_lock = T_8449_io_slave_aw_bits_lock;
+ assign T_10206_0_slave_aw_bits_cache = T_8449_io_slave_aw_bits_cache;
+ assign T_10206_0_slave_aw_bits_prot = T_8449_io_slave_aw_bits_prot;
+ assign T_10206_0_slave_aw_bits_qos = T_8449_io_slave_aw_bits_qos;
+ assign T_10206_0_slave_aw_bits_region = T_8449_io_slave_aw_bits_region;
+ assign T_10206_0_slave_aw_bits_id = T_8449_io_slave_aw_bits_id;
+ assign T_10206_0_slave_aw_bits_user = T_8449_io_slave_aw_bits_user;
+ assign T_10206_0_slave_w_ready = io_slaves_0_w_ready;
+ assign T_10206_0_slave_w_valid = T_8449_io_slave_w_valid;
+ assign T_10206_0_slave_w_bits_data = T_8449_io_slave_w_bits_data;
+ assign T_10206_0_slave_w_bits_last = T_8449_io_slave_w_bits_last;
+ assign T_10206_0_slave_w_bits_strb = T_8449_io_slave_w_bits_strb;
+ assign T_10206_0_slave_w_bits_user = T_8449_io_slave_w_bits_user;
+ assign T_10206_0_slave_b_ready = T_8449_io_slave_b_ready;
+ assign T_10206_0_slave_b_valid = io_slaves_0_b_valid;
+ assign T_10206_0_slave_b_bits_resp = io_slaves_0_b_bits_resp;
+ assign T_10206_0_slave_b_bits_id = io_slaves_0_b_bits_id;
+ assign T_10206_0_slave_b_bits_user = io_slaves_0_b_bits_user;
+ assign T_10206_0_slave_ar_ready = io_slaves_0_ar_ready;
+ assign T_10206_0_slave_ar_valid = T_8449_io_slave_ar_valid;
+ assign T_10206_0_slave_ar_bits_addr = T_8449_io_slave_ar_bits_addr;
+ assign T_10206_0_slave_ar_bits_len = T_8449_io_slave_ar_bits_len;
+ assign T_10206_0_slave_ar_bits_size = T_8449_io_slave_ar_bits_size;
+ assign T_10206_0_slave_ar_bits_burst = T_8449_io_slave_ar_bits_burst;
+ assign T_10206_0_slave_ar_bits_lock = T_8449_io_slave_ar_bits_lock;
+ assign T_10206_0_slave_ar_bits_cache = T_8449_io_slave_ar_bits_cache;
+ assign T_10206_0_slave_ar_bits_prot = T_8449_io_slave_ar_bits_prot;
+ assign T_10206_0_slave_ar_bits_qos = T_8449_io_slave_ar_bits_qos;
+ assign T_10206_0_slave_ar_bits_region = T_8449_io_slave_ar_bits_region;
+ assign T_10206_0_slave_ar_bits_id = T_8449_io_slave_ar_bits_id;
+ assign T_10206_0_slave_ar_bits_user = T_8449_io_slave_ar_bits_user;
+ assign T_10206_0_slave_r_ready = T_8449_io_slave_r_ready;
+ assign T_10206_0_slave_r_valid = io_slaves_0_r_valid;
+ assign T_10206_0_slave_r_bits_resp = io_slaves_0_r_bits_resp;
+ assign T_10206_0_slave_r_bits_data = io_slaves_0_r_bits_data;
+ assign T_10206_0_slave_r_bits_last = io_slaves_0_r_bits_last;
+ assign T_10206_0_slave_r_bits_id = io_slaves_0_r_bits_id;
+ assign T_10206_0_slave_r_bits_user = io_slaves_0_r_bits_user;
+ assign T_10206_1_master_0_aw_ready = T_8450_io_master_0_aw_ready;
+ assign T_10206_1_master_0_aw_valid = T_19768_0_aw_valid;
+ assign T_10206_1_master_0_aw_bits_addr = T_19768_0_aw_bits_addr;
+ assign T_10206_1_master_0_aw_bits_len = T_19768_0_aw_bits_len;
+ assign T_10206_1_master_0_aw_bits_size = T_19768_0_aw_bits_size;
+ assign T_10206_1_master_0_aw_bits_burst = T_19768_0_aw_bits_burst;
+ assign T_10206_1_master_0_aw_bits_lock = T_19768_0_aw_bits_lock;
+ assign T_10206_1_master_0_aw_bits_cache = T_19768_0_aw_bits_cache;
+ assign T_10206_1_master_0_aw_bits_prot = T_19768_0_aw_bits_prot;
+ assign T_10206_1_master_0_aw_bits_qos = T_19768_0_aw_bits_qos;
+ assign T_10206_1_master_0_aw_bits_region = T_19768_0_aw_bits_region;
+ assign T_10206_1_master_0_aw_bits_id = T_19768_0_aw_bits_id;
+ assign T_10206_1_master_0_aw_bits_user = T_19768_0_aw_bits_user;
+ assign T_10206_1_master_0_w_ready = T_8450_io_master_0_w_ready;
+ assign T_10206_1_master_0_w_valid = T_19768_0_w_valid;
+ assign T_10206_1_master_0_w_bits_data = T_19768_0_w_bits_data;
+ assign T_10206_1_master_0_w_bits_last = T_19768_0_w_bits_last;
+ assign T_10206_1_master_0_w_bits_strb = T_19768_0_w_bits_strb;
+ assign T_10206_1_master_0_w_bits_user = T_19768_0_w_bits_user;
+ assign T_10206_1_master_0_b_ready = T_19768_0_b_ready;
+ assign T_10206_1_master_0_b_valid = T_8450_io_master_0_b_valid;
+ assign T_10206_1_master_0_b_bits_resp = T_8450_io_master_0_b_bits_resp;
+ assign T_10206_1_master_0_b_bits_id = T_8450_io_master_0_b_bits_id;
+ assign T_10206_1_master_0_b_bits_user = T_8450_io_master_0_b_bits_user;
+ assign T_10206_1_master_0_ar_ready = T_8450_io_master_0_ar_ready;
+ assign T_10206_1_master_0_ar_valid = T_19768_0_ar_valid;
+ assign T_10206_1_master_0_ar_bits_addr = T_19768_0_ar_bits_addr;
+ assign T_10206_1_master_0_ar_bits_len = T_19768_0_ar_bits_len;
+ assign T_10206_1_master_0_ar_bits_size = T_19768_0_ar_bits_size;
+ assign T_10206_1_master_0_ar_bits_burst = T_19768_0_ar_bits_burst;
+ assign T_10206_1_master_0_ar_bits_lock = T_19768_0_ar_bits_lock;
+ assign T_10206_1_master_0_ar_bits_cache = T_19768_0_ar_bits_cache;
+ assign T_10206_1_master_0_ar_bits_prot = T_19768_0_ar_bits_prot;
+ assign T_10206_1_master_0_ar_bits_qos = T_19768_0_ar_bits_qos;
+ assign T_10206_1_master_0_ar_bits_region = T_19768_0_ar_bits_region;
+ assign T_10206_1_master_0_ar_bits_id = T_19768_0_ar_bits_id;
+ assign T_10206_1_master_0_ar_bits_user = T_19768_0_ar_bits_user;
+ assign T_10206_1_master_0_r_ready = T_19768_0_r_ready;
+ assign T_10206_1_master_0_r_valid = T_8450_io_master_0_r_valid;
+ assign T_10206_1_master_0_r_bits_resp = T_8450_io_master_0_r_bits_resp;
+ assign T_10206_1_master_0_r_bits_data = T_8450_io_master_0_r_bits_data;
+ assign T_10206_1_master_0_r_bits_last = T_8450_io_master_0_r_bits_last;
+ assign T_10206_1_master_0_r_bits_id = T_8450_io_master_0_r_bits_id;
+ assign T_10206_1_master_0_r_bits_user = T_8450_io_master_0_r_bits_user;
+ assign T_10206_1_master_1_aw_ready = T_8450_io_master_1_aw_ready;
+ assign T_10206_1_master_1_aw_valid = T_19768_1_aw_valid;
+ assign T_10206_1_master_1_aw_bits_addr = T_19768_1_aw_bits_addr;
+ assign T_10206_1_master_1_aw_bits_len = T_19768_1_aw_bits_len;
+ assign T_10206_1_master_1_aw_bits_size = T_19768_1_aw_bits_size;
+ assign T_10206_1_master_1_aw_bits_burst = T_19768_1_aw_bits_burst;
+ assign T_10206_1_master_1_aw_bits_lock = T_19768_1_aw_bits_lock;
+ assign T_10206_1_master_1_aw_bits_cache = T_19768_1_aw_bits_cache;
+ assign T_10206_1_master_1_aw_bits_prot = T_19768_1_aw_bits_prot;
+ assign T_10206_1_master_1_aw_bits_qos = T_19768_1_aw_bits_qos;
+ assign T_10206_1_master_1_aw_bits_region = T_19768_1_aw_bits_region;
+ assign T_10206_1_master_1_aw_bits_id = T_19768_1_aw_bits_id;
+ assign T_10206_1_master_1_aw_bits_user = T_19768_1_aw_bits_user;
+ assign T_10206_1_master_1_w_ready = T_8450_io_master_1_w_ready;
+ assign T_10206_1_master_1_w_valid = T_19768_1_w_valid;
+ assign T_10206_1_master_1_w_bits_data = T_19768_1_w_bits_data;
+ assign T_10206_1_master_1_w_bits_last = T_19768_1_w_bits_last;
+ assign T_10206_1_master_1_w_bits_strb = T_19768_1_w_bits_strb;
+ assign T_10206_1_master_1_w_bits_user = T_19768_1_w_bits_user;
+ assign T_10206_1_master_1_b_ready = T_19768_1_b_ready;
+ assign T_10206_1_master_1_b_valid = T_8450_io_master_1_b_valid;
+ assign T_10206_1_master_1_b_bits_resp = T_8450_io_master_1_b_bits_resp;
+ assign T_10206_1_master_1_b_bits_id = T_8450_io_master_1_b_bits_id;
+ assign T_10206_1_master_1_b_bits_user = T_8450_io_master_1_b_bits_user;
+ assign T_10206_1_master_1_ar_ready = T_8450_io_master_1_ar_ready;
+ assign T_10206_1_master_1_ar_valid = T_19768_1_ar_valid;
+ assign T_10206_1_master_1_ar_bits_addr = T_19768_1_ar_bits_addr;
+ assign T_10206_1_master_1_ar_bits_len = T_19768_1_ar_bits_len;
+ assign T_10206_1_master_1_ar_bits_size = T_19768_1_ar_bits_size;
+ assign T_10206_1_master_1_ar_bits_burst = T_19768_1_ar_bits_burst;
+ assign T_10206_1_master_1_ar_bits_lock = T_19768_1_ar_bits_lock;
+ assign T_10206_1_master_1_ar_bits_cache = T_19768_1_ar_bits_cache;
+ assign T_10206_1_master_1_ar_bits_prot = T_19768_1_ar_bits_prot;
+ assign T_10206_1_master_1_ar_bits_qos = T_19768_1_ar_bits_qos;
+ assign T_10206_1_master_1_ar_bits_region = T_19768_1_ar_bits_region;
+ assign T_10206_1_master_1_ar_bits_id = T_19768_1_ar_bits_id;
+ assign T_10206_1_master_1_ar_bits_user = T_19768_1_ar_bits_user;
+ assign T_10206_1_master_1_r_ready = T_19768_1_r_ready;
+ assign T_10206_1_master_1_r_valid = T_8450_io_master_1_r_valid;
+ assign T_10206_1_master_1_r_bits_resp = T_8450_io_master_1_r_bits_resp;
+ assign T_10206_1_master_1_r_bits_data = T_8450_io_master_1_r_bits_data;
+ assign T_10206_1_master_1_r_bits_last = T_8450_io_master_1_r_bits_last;
+ assign T_10206_1_master_1_r_bits_id = T_8450_io_master_1_r_bits_id;
+ assign T_10206_1_master_1_r_bits_user = T_8450_io_master_1_r_bits_user;
+ assign T_10206_1_slave_aw_ready = io_slaves_1_aw_ready;
+ assign T_10206_1_slave_aw_valid = T_8450_io_slave_aw_valid;
+ assign T_10206_1_slave_aw_bits_addr = T_8450_io_slave_aw_bits_addr;
+ assign T_10206_1_slave_aw_bits_len = T_8450_io_slave_aw_bits_len;
+ assign T_10206_1_slave_aw_bits_size = T_8450_io_slave_aw_bits_size;
+ assign T_10206_1_slave_aw_bits_burst = T_8450_io_slave_aw_bits_burst;
+ assign T_10206_1_slave_aw_bits_lock = T_8450_io_slave_aw_bits_lock;
+ assign T_10206_1_slave_aw_bits_cache = T_8450_io_slave_aw_bits_cache;
+ assign T_10206_1_slave_aw_bits_prot = T_8450_io_slave_aw_bits_prot;
+ assign T_10206_1_slave_aw_bits_qos = T_8450_io_slave_aw_bits_qos;
+ assign T_10206_1_slave_aw_bits_region = T_8450_io_slave_aw_bits_region;
+ assign T_10206_1_slave_aw_bits_id = T_8450_io_slave_aw_bits_id;
+ assign T_10206_1_slave_aw_bits_user = T_8450_io_slave_aw_bits_user;
+ assign T_10206_1_slave_w_ready = io_slaves_1_w_ready;
+ assign T_10206_1_slave_w_valid = T_8450_io_slave_w_valid;
+ assign T_10206_1_slave_w_bits_data = T_8450_io_slave_w_bits_data;
+ assign T_10206_1_slave_w_bits_last = T_8450_io_slave_w_bits_last;
+ assign T_10206_1_slave_w_bits_strb = T_8450_io_slave_w_bits_strb;
+ assign T_10206_1_slave_w_bits_user = T_8450_io_slave_w_bits_user;
+ assign T_10206_1_slave_b_ready = T_8450_io_slave_b_ready;
+ assign T_10206_1_slave_b_valid = io_slaves_1_b_valid;
+ assign T_10206_1_slave_b_bits_resp = io_slaves_1_b_bits_resp;
+ assign T_10206_1_slave_b_bits_id = io_slaves_1_b_bits_id;
+ assign T_10206_1_slave_b_bits_user = io_slaves_1_b_bits_user;
+ assign T_10206_1_slave_ar_ready = io_slaves_1_ar_ready;
+ assign T_10206_1_slave_ar_valid = T_8450_io_slave_ar_valid;
+ assign T_10206_1_slave_ar_bits_addr = T_8450_io_slave_ar_bits_addr;
+ assign T_10206_1_slave_ar_bits_len = T_8450_io_slave_ar_bits_len;
+ assign T_10206_1_slave_ar_bits_size = T_8450_io_slave_ar_bits_size;
+ assign T_10206_1_slave_ar_bits_burst = T_8450_io_slave_ar_bits_burst;
+ assign T_10206_1_slave_ar_bits_lock = T_8450_io_slave_ar_bits_lock;
+ assign T_10206_1_slave_ar_bits_cache = T_8450_io_slave_ar_bits_cache;
+ assign T_10206_1_slave_ar_bits_prot = T_8450_io_slave_ar_bits_prot;
+ assign T_10206_1_slave_ar_bits_qos = T_8450_io_slave_ar_bits_qos;
+ assign T_10206_1_slave_ar_bits_region = T_8450_io_slave_ar_bits_region;
+ assign T_10206_1_slave_ar_bits_id = T_8450_io_slave_ar_bits_id;
+ assign T_10206_1_slave_ar_bits_user = T_8450_io_slave_ar_bits_user;
+ assign T_10206_1_slave_r_ready = T_8450_io_slave_r_ready;
+ assign T_10206_1_slave_r_valid = io_slaves_1_r_valid;
+ assign T_10206_1_slave_r_bits_resp = io_slaves_1_r_bits_resp;
+ assign T_10206_1_slave_r_bits_data = io_slaves_1_r_bits_data;
+ assign T_10206_1_slave_r_bits_last = io_slaves_1_r_bits_last;
+ assign T_10206_1_slave_r_bits_id = io_slaves_1_r_bits_id;
+ assign T_10206_1_slave_r_bits_user = io_slaves_1_r_bits_user;
+ assign T_10206_2_master_0_aw_ready = T_8451_io_master_0_aw_ready;
+ assign T_10206_2_master_0_aw_valid = T_20405_0_aw_valid;
+ assign T_10206_2_master_0_aw_bits_addr = T_20405_0_aw_bits_addr;
+ assign T_10206_2_master_0_aw_bits_len = T_20405_0_aw_bits_len;
+ assign T_10206_2_master_0_aw_bits_size = T_20405_0_aw_bits_size;
+ assign T_10206_2_master_0_aw_bits_burst = T_20405_0_aw_bits_burst;
+ assign T_10206_2_master_0_aw_bits_lock = T_20405_0_aw_bits_lock;
+ assign T_10206_2_master_0_aw_bits_cache = T_20405_0_aw_bits_cache;
+ assign T_10206_2_master_0_aw_bits_prot = T_20405_0_aw_bits_prot;
+ assign T_10206_2_master_0_aw_bits_qos = T_20405_0_aw_bits_qos;
+ assign T_10206_2_master_0_aw_bits_region = T_20405_0_aw_bits_region;
+ assign T_10206_2_master_0_aw_bits_id = T_20405_0_aw_bits_id;
+ assign T_10206_2_master_0_aw_bits_user = T_20405_0_aw_bits_user;
+ assign T_10206_2_master_0_w_ready = T_8451_io_master_0_w_ready;
+ assign T_10206_2_master_0_w_valid = T_20405_0_w_valid;
+ assign T_10206_2_master_0_w_bits_data = T_20405_0_w_bits_data;
+ assign T_10206_2_master_0_w_bits_last = T_20405_0_w_bits_last;
+ assign T_10206_2_master_0_w_bits_strb = T_20405_0_w_bits_strb;
+ assign T_10206_2_master_0_w_bits_user = T_20405_0_w_bits_user;
+ assign T_10206_2_master_0_b_ready = T_20405_0_b_ready;
+ assign T_10206_2_master_0_b_valid = T_8451_io_master_0_b_valid;
+ assign T_10206_2_master_0_b_bits_resp = T_8451_io_master_0_b_bits_resp;
+ assign T_10206_2_master_0_b_bits_id = T_8451_io_master_0_b_bits_id;
+ assign T_10206_2_master_0_b_bits_user = T_8451_io_master_0_b_bits_user;
+ assign T_10206_2_master_0_ar_ready = T_8451_io_master_0_ar_ready;
+ assign T_10206_2_master_0_ar_valid = T_20405_0_ar_valid;
+ assign T_10206_2_master_0_ar_bits_addr = T_20405_0_ar_bits_addr;
+ assign T_10206_2_master_0_ar_bits_len = T_20405_0_ar_bits_len;
+ assign T_10206_2_master_0_ar_bits_size = T_20405_0_ar_bits_size;
+ assign T_10206_2_master_0_ar_bits_burst = T_20405_0_ar_bits_burst;
+ assign T_10206_2_master_0_ar_bits_lock = T_20405_0_ar_bits_lock;
+ assign T_10206_2_master_0_ar_bits_cache = T_20405_0_ar_bits_cache;
+ assign T_10206_2_master_0_ar_bits_prot = T_20405_0_ar_bits_prot;
+ assign T_10206_2_master_0_ar_bits_qos = T_20405_0_ar_bits_qos;
+ assign T_10206_2_master_0_ar_bits_region = T_20405_0_ar_bits_region;
+ assign T_10206_2_master_0_ar_bits_id = T_20405_0_ar_bits_id;
+ assign T_10206_2_master_0_ar_bits_user = T_20405_0_ar_bits_user;
+ assign T_10206_2_master_0_r_ready = T_20405_0_r_ready;
+ assign T_10206_2_master_0_r_valid = T_8451_io_master_0_r_valid;
+ assign T_10206_2_master_0_r_bits_resp = T_8451_io_master_0_r_bits_resp;
+ assign T_10206_2_master_0_r_bits_data = T_8451_io_master_0_r_bits_data;
+ assign T_10206_2_master_0_r_bits_last = T_8451_io_master_0_r_bits_last;
+ assign T_10206_2_master_0_r_bits_id = T_8451_io_master_0_r_bits_id;
+ assign T_10206_2_master_0_r_bits_user = T_8451_io_master_0_r_bits_user;
+ assign T_10206_2_master_1_aw_ready = T_8451_io_master_1_aw_ready;
+ assign T_10206_2_master_1_aw_valid = T_20405_1_aw_valid;
+ assign T_10206_2_master_1_aw_bits_addr = T_20405_1_aw_bits_addr;
+ assign T_10206_2_master_1_aw_bits_len = T_20405_1_aw_bits_len;
+ assign T_10206_2_master_1_aw_bits_size = T_20405_1_aw_bits_size;
+ assign T_10206_2_master_1_aw_bits_burst = T_20405_1_aw_bits_burst;
+ assign T_10206_2_master_1_aw_bits_lock = T_20405_1_aw_bits_lock;
+ assign T_10206_2_master_1_aw_bits_cache = T_20405_1_aw_bits_cache;
+ assign T_10206_2_master_1_aw_bits_prot = T_20405_1_aw_bits_prot;
+ assign T_10206_2_master_1_aw_bits_qos = T_20405_1_aw_bits_qos;
+ assign T_10206_2_master_1_aw_bits_region = T_20405_1_aw_bits_region;
+ assign T_10206_2_master_1_aw_bits_id = T_20405_1_aw_bits_id;
+ assign T_10206_2_master_1_aw_bits_user = T_20405_1_aw_bits_user;
+ assign T_10206_2_master_1_w_ready = T_8451_io_master_1_w_ready;
+ assign T_10206_2_master_1_w_valid = T_20405_1_w_valid;
+ assign T_10206_2_master_1_w_bits_data = T_20405_1_w_bits_data;
+ assign T_10206_2_master_1_w_bits_last = T_20405_1_w_bits_last;
+ assign T_10206_2_master_1_w_bits_strb = T_20405_1_w_bits_strb;
+ assign T_10206_2_master_1_w_bits_user = T_20405_1_w_bits_user;
+ assign T_10206_2_master_1_b_ready = T_20405_1_b_ready;
+ assign T_10206_2_master_1_b_valid = T_8451_io_master_1_b_valid;
+ assign T_10206_2_master_1_b_bits_resp = T_8451_io_master_1_b_bits_resp;
+ assign T_10206_2_master_1_b_bits_id = T_8451_io_master_1_b_bits_id;
+ assign T_10206_2_master_1_b_bits_user = T_8451_io_master_1_b_bits_user;
+ assign T_10206_2_master_1_ar_ready = T_8451_io_master_1_ar_ready;
+ assign T_10206_2_master_1_ar_valid = T_20405_1_ar_valid;
+ assign T_10206_2_master_1_ar_bits_addr = T_20405_1_ar_bits_addr;
+ assign T_10206_2_master_1_ar_bits_len = T_20405_1_ar_bits_len;
+ assign T_10206_2_master_1_ar_bits_size = T_20405_1_ar_bits_size;
+ assign T_10206_2_master_1_ar_bits_burst = T_20405_1_ar_bits_burst;
+ assign T_10206_2_master_1_ar_bits_lock = T_20405_1_ar_bits_lock;
+ assign T_10206_2_master_1_ar_bits_cache = T_20405_1_ar_bits_cache;
+ assign T_10206_2_master_1_ar_bits_prot = T_20405_1_ar_bits_prot;
+ assign T_10206_2_master_1_ar_bits_qos = T_20405_1_ar_bits_qos;
+ assign T_10206_2_master_1_ar_bits_region = T_20405_1_ar_bits_region;
+ assign T_10206_2_master_1_ar_bits_id = T_20405_1_ar_bits_id;
+ assign T_10206_2_master_1_ar_bits_user = T_20405_1_ar_bits_user;
+ assign T_10206_2_master_1_r_ready = T_20405_1_r_ready;
+ assign T_10206_2_master_1_r_valid = T_8451_io_master_1_r_valid;
+ assign T_10206_2_master_1_r_bits_resp = T_8451_io_master_1_r_bits_resp;
+ assign T_10206_2_master_1_r_bits_data = T_8451_io_master_1_r_bits_data;
+ assign T_10206_2_master_1_r_bits_last = T_8451_io_master_1_r_bits_last;
+ assign T_10206_2_master_1_r_bits_id = T_8451_io_master_1_r_bits_id;
+ assign T_10206_2_master_1_r_bits_user = T_8451_io_master_1_r_bits_user;
+ assign T_10206_2_slave_aw_ready = io_slaves_2_aw_ready;
+ assign T_10206_2_slave_aw_valid = T_8451_io_slave_aw_valid;
+ assign T_10206_2_slave_aw_bits_addr = T_8451_io_slave_aw_bits_addr;
+ assign T_10206_2_slave_aw_bits_len = T_8451_io_slave_aw_bits_len;
+ assign T_10206_2_slave_aw_bits_size = T_8451_io_slave_aw_bits_size;
+ assign T_10206_2_slave_aw_bits_burst = T_8451_io_slave_aw_bits_burst;
+ assign T_10206_2_slave_aw_bits_lock = T_8451_io_slave_aw_bits_lock;
+ assign T_10206_2_slave_aw_bits_cache = T_8451_io_slave_aw_bits_cache;
+ assign T_10206_2_slave_aw_bits_prot = T_8451_io_slave_aw_bits_prot;
+ assign T_10206_2_slave_aw_bits_qos = T_8451_io_slave_aw_bits_qos;
+ assign T_10206_2_slave_aw_bits_region = T_8451_io_slave_aw_bits_region;
+ assign T_10206_2_slave_aw_bits_id = T_8451_io_slave_aw_bits_id;
+ assign T_10206_2_slave_aw_bits_user = T_8451_io_slave_aw_bits_user;
+ assign T_10206_2_slave_w_ready = io_slaves_2_w_ready;
+ assign T_10206_2_slave_w_valid = T_8451_io_slave_w_valid;
+ assign T_10206_2_slave_w_bits_data = T_8451_io_slave_w_bits_data;
+ assign T_10206_2_slave_w_bits_last = T_8451_io_slave_w_bits_last;
+ assign T_10206_2_slave_w_bits_strb = T_8451_io_slave_w_bits_strb;
+ assign T_10206_2_slave_w_bits_user = T_8451_io_slave_w_bits_user;
+ assign T_10206_2_slave_b_ready = T_8451_io_slave_b_ready;
+ assign T_10206_2_slave_b_valid = io_slaves_2_b_valid;
+ assign T_10206_2_slave_b_bits_resp = io_slaves_2_b_bits_resp;
+ assign T_10206_2_slave_b_bits_id = io_slaves_2_b_bits_id;
+ assign T_10206_2_slave_b_bits_user = io_slaves_2_b_bits_user;
+ assign T_10206_2_slave_ar_ready = io_slaves_2_ar_ready;
+ assign T_10206_2_slave_ar_valid = T_8451_io_slave_ar_valid;
+ assign T_10206_2_slave_ar_bits_addr = T_8451_io_slave_ar_bits_addr;
+ assign T_10206_2_slave_ar_bits_len = T_8451_io_slave_ar_bits_len;
+ assign T_10206_2_slave_ar_bits_size = T_8451_io_slave_ar_bits_size;
+ assign T_10206_2_slave_ar_bits_burst = T_8451_io_slave_ar_bits_burst;
+ assign T_10206_2_slave_ar_bits_lock = T_8451_io_slave_ar_bits_lock;
+ assign T_10206_2_slave_ar_bits_cache = T_8451_io_slave_ar_bits_cache;
+ assign T_10206_2_slave_ar_bits_prot = T_8451_io_slave_ar_bits_prot;
+ assign T_10206_2_slave_ar_bits_qos = T_8451_io_slave_ar_bits_qos;
+ assign T_10206_2_slave_ar_bits_region = T_8451_io_slave_ar_bits_region;
+ assign T_10206_2_slave_ar_bits_id = T_8451_io_slave_ar_bits_id;
+ assign T_10206_2_slave_ar_bits_user = T_8451_io_slave_ar_bits_user;
+ assign T_10206_2_slave_r_ready = T_8451_io_slave_r_ready;
+ assign T_10206_2_slave_r_valid = io_slaves_2_r_valid;
+ assign T_10206_2_slave_r_bits_resp = io_slaves_2_r_bits_resp;
+ assign T_10206_2_slave_r_bits_data = io_slaves_2_r_bits_data;
+ assign T_10206_2_slave_r_bits_last = io_slaves_2_r_bits_last;
+ assign T_10206_2_slave_r_bits_id = io_slaves_2_r_bits_id;
+ assign T_10206_2_slave_r_bits_user = io_slaves_2_r_bits_user;
+ assign T_10206_3_master_0_aw_ready = T_8452_io_master_0_aw_ready;
+ assign T_10206_3_master_0_aw_valid = T_21042_0_aw_valid;
+ assign T_10206_3_master_0_aw_bits_addr = T_21042_0_aw_bits_addr;
+ assign T_10206_3_master_0_aw_bits_len = T_21042_0_aw_bits_len;
+ assign T_10206_3_master_0_aw_bits_size = T_21042_0_aw_bits_size;
+ assign T_10206_3_master_0_aw_bits_burst = T_21042_0_aw_bits_burst;
+ assign T_10206_3_master_0_aw_bits_lock = T_21042_0_aw_bits_lock;
+ assign T_10206_3_master_0_aw_bits_cache = T_21042_0_aw_bits_cache;
+ assign T_10206_3_master_0_aw_bits_prot = T_21042_0_aw_bits_prot;
+ assign T_10206_3_master_0_aw_bits_qos = T_21042_0_aw_bits_qos;
+ assign T_10206_3_master_0_aw_bits_region = T_21042_0_aw_bits_region;
+ assign T_10206_3_master_0_aw_bits_id = T_21042_0_aw_bits_id;
+ assign T_10206_3_master_0_aw_bits_user = T_21042_0_aw_bits_user;
+ assign T_10206_3_master_0_w_ready = T_8452_io_master_0_w_ready;
+ assign T_10206_3_master_0_w_valid = T_21042_0_w_valid;
+ assign T_10206_3_master_0_w_bits_data = T_21042_0_w_bits_data;
+ assign T_10206_3_master_0_w_bits_last = T_21042_0_w_bits_last;
+ assign T_10206_3_master_0_w_bits_strb = T_21042_0_w_bits_strb;
+ assign T_10206_3_master_0_w_bits_user = T_21042_0_w_bits_user;
+ assign T_10206_3_master_0_b_ready = T_21042_0_b_ready;
+ assign T_10206_3_master_0_b_valid = T_8452_io_master_0_b_valid;
+ assign T_10206_3_master_0_b_bits_resp = T_8452_io_master_0_b_bits_resp;
+ assign T_10206_3_master_0_b_bits_id = T_8452_io_master_0_b_bits_id;
+ assign T_10206_3_master_0_b_bits_user = T_8452_io_master_0_b_bits_user;
+ assign T_10206_3_master_0_ar_ready = T_8452_io_master_0_ar_ready;
+ assign T_10206_3_master_0_ar_valid = T_21042_0_ar_valid;
+ assign T_10206_3_master_0_ar_bits_addr = T_21042_0_ar_bits_addr;
+ assign T_10206_3_master_0_ar_bits_len = T_21042_0_ar_bits_len;
+ assign T_10206_3_master_0_ar_bits_size = T_21042_0_ar_bits_size;
+ assign T_10206_3_master_0_ar_bits_burst = T_21042_0_ar_bits_burst;
+ assign T_10206_3_master_0_ar_bits_lock = T_21042_0_ar_bits_lock;
+ assign T_10206_3_master_0_ar_bits_cache = T_21042_0_ar_bits_cache;
+ assign T_10206_3_master_0_ar_bits_prot = T_21042_0_ar_bits_prot;
+ assign T_10206_3_master_0_ar_bits_qos = T_21042_0_ar_bits_qos;
+ assign T_10206_3_master_0_ar_bits_region = T_21042_0_ar_bits_region;
+ assign T_10206_3_master_0_ar_bits_id = T_21042_0_ar_bits_id;
+ assign T_10206_3_master_0_ar_bits_user = T_21042_0_ar_bits_user;
+ assign T_10206_3_master_0_r_ready = T_21042_0_r_ready;
+ assign T_10206_3_master_0_r_valid = T_8452_io_master_0_r_valid;
+ assign T_10206_3_master_0_r_bits_resp = T_8452_io_master_0_r_bits_resp;
+ assign T_10206_3_master_0_r_bits_data = T_8452_io_master_0_r_bits_data;
+ assign T_10206_3_master_0_r_bits_last = T_8452_io_master_0_r_bits_last;
+ assign T_10206_3_master_0_r_bits_id = T_8452_io_master_0_r_bits_id;
+ assign T_10206_3_master_0_r_bits_user = T_8452_io_master_0_r_bits_user;
+ assign T_10206_3_master_1_aw_ready = T_8452_io_master_1_aw_ready;
+ assign T_10206_3_master_1_aw_valid = T_21042_1_aw_valid;
+ assign T_10206_3_master_1_aw_bits_addr = T_21042_1_aw_bits_addr;
+ assign T_10206_3_master_1_aw_bits_len = T_21042_1_aw_bits_len;
+ assign T_10206_3_master_1_aw_bits_size = T_21042_1_aw_bits_size;
+ assign T_10206_3_master_1_aw_bits_burst = T_21042_1_aw_bits_burst;
+ assign T_10206_3_master_1_aw_bits_lock = T_21042_1_aw_bits_lock;
+ assign T_10206_3_master_1_aw_bits_cache = T_21042_1_aw_bits_cache;
+ assign T_10206_3_master_1_aw_bits_prot = T_21042_1_aw_bits_prot;
+ assign T_10206_3_master_1_aw_bits_qos = T_21042_1_aw_bits_qos;
+ assign T_10206_3_master_1_aw_bits_region = T_21042_1_aw_bits_region;
+ assign T_10206_3_master_1_aw_bits_id = T_21042_1_aw_bits_id;
+ assign T_10206_3_master_1_aw_bits_user = T_21042_1_aw_bits_user;
+ assign T_10206_3_master_1_w_ready = T_8452_io_master_1_w_ready;
+ assign T_10206_3_master_1_w_valid = T_21042_1_w_valid;
+ assign T_10206_3_master_1_w_bits_data = T_21042_1_w_bits_data;
+ assign T_10206_3_master_1_w_bits_last = T_21042_1_w_bits_last;
+ assign T_10206_3_master_1_w_bits_strb = T_21042_1_w_bits_strb;
+ assign T_10206_3_master_1_w_bits_user = T_21042_1_w_bits_user;
+ assign T_10206_3_master_1_b_ready = T_21042_1_b_ready;
+ assign T_10206_3_master_1_b_valid = T_8452_io_master_1_b_valid;
+ assign T_10206_3_master_1_b_bits_resp = T_8452_io_master_1_b_bits_resp;
+ assign T_10206_3_master_1_b_bits_id = T_8452_io_master_1_b_bits_id;
+ assign T_10206_3_master_1_b_bits_user = T_8452_io_master_1_b_bits_user;
+ assign T_10206_3_master_1_ar_ready = T_8452_io_master_1_ar_ready;
+ assign T_10206_3_master_1_ar_valid = T_21042_1_ar_valid;
+ assign T_10206_3_master_1_ar_bits_addr = T_21042_1_ar_bits_addr;
+ assign T_10206_3_master_1_ar_bits_len = T_21042_1_ar_bits_len;
+ assign T_10206_3_master_1_ar_bits_size = T_21042_1_ar_bits_size;
+ assign T_10206_3_master_1_ar_bits_burst = T_21042_1_ar_bits_burst;
+ assign T_10206_3_master_1_ar_bits_lock = T_21042_1_ar_bits_lock;
+ assign T_10206_3_master_1_ar_bits_cache = T_21042_1_ar_bits_cache;
+ assign T_10206_3_master_1_ar_bits_prot = T_21042_1_ar_bits_prot;
+ assign T_10206_3_master_1_ar_bits_qos = T_21042_1_ar_bits_qos;
+ assign T_10206_3_master_1_ar_bits_region = T_21042_1_ar_bits_region;
+ assign T_10206_3_master_1_ar_bits_id = T_21042_1_ar_bits_id;
+ assign T_10206_3_master_1_ar_bits_user = T_21042_1_ar_bits_user;
+ assign T_10206_3_master_1_r_ready = T_21042_1_r_ready;
+ assign T_10206_3_master_1_r_valid = T_8452_io_master_1_r_valid;
+ assign T_10206_3_master_1_r_bits_resp = T_8452_io_master_1_r_bits_resp;
+ assign T_10206_3_master_1_r_bits_data = T_8452_io_master_1_r_bits_data;
+ assign T_10206_3_master_1_r_bits_last = T_8452_io_master_1_r_bits_last;
+ assign T_10206_3_master_1_r_bits_id = T_8452_io_master_1_r_bits_id;
+ assign T_10206_3_master_1_r_bits_user = T_8452_io_master_1_r_bits_user;
+ assign T_10206_3_slave_aw_ready = io_slaves_3_aw_ready;
+ assign T_10206_3_slave_aw_valid = T_8452_io_slave_aw_valid;
+ assign T_10206_3_slave_aw_bits_addr = T_8452_io_slave_aw_bits_addr;
+ assign T_10206_3_slave_aw_bits_len = T_8452_io_slave_aw_bits_len;
+ assign T_10206_3_slave_aw_bits_size = T_8452_io_slave_aw_bits_size;
+ assign T_10206_3_slave_aw_bits_burst = T_8452_io_slave_aw_bits_burst;
+ assign T_10206_3_slave_aw_bits_lock = T_8452_io_slave_aw_bits_lock;
+ assign T_10206_3_slave_aw_bits_cache = T_8452_io_slave_aw_bits_cache;
+ assign T_10206_3_slave_aw_bits_prot = T_8452_io_slave_aw_bits_prot;
+ assign T_10206_3_slave_aw_bits_qos = T_8452_io_slave_aw_bits_qos;
+ assign T_10206_3_slave_aw_bits_region = T_8452_io_slave_aw_bits_region;
+ assign T_10206_3_slave_aw_bits_id = T_8452_io_slave_aw_bits_id;
+ assign T_10206_3_slave_aw_bits_user = T_8452_io_slave_aw_bits_user;
+ assign T_10206_3_slave_w_ready = io_slaves_3_w_ready;
+ assign T_10206_3_slave_w_valid = T_8452_io_slave_w_valid;
+ assign T_10206_3_slave_w_bits_data = T_8452_io_slave_w_bits_data;
+ assign T_10206_3_slave_w_bits_last = T_8452_io_slave_w_bits_last;
+ assign T_10206_3_slave_w_bits_strb = T_8452_io_slave_w_bits_strb;
+ assign T_10206_3_slave_w_bits_user = T_8452_io_slave_w_bits_user;
+ assign T_10206_3_slave_b_ready = T_8452_io_slave_b_ready;
+ assign T_10206_3_slave_b_valid = io_slaves_3_b_valid;
+ assign T_10206_3_slave_b_bits_resp = io_slaves_3_b_bits_resp;
+ assign T_10206_3_slave_b_bits_id = io_slaves_3_b_bits_id;
+ assign T_10206_3_slave_b_bits_user = io_slaves_3_b_bits_user;
+ assign T_10206_3_slave_ar_ready = io_slaves_3_ar_ready;
+ assign T_10206_3_slave_ar_valid = T_8452_io_slave_ar_valid;
+ assign T_10206_3_slave_ar_bits_addr = T_8452_io_slave_ar_bits_addr;
+ assign T_10206_3_slave_ar_bits_len = T_8452_io_slave_ar_bits_len;
+ assign T_10206_3_slave_ar_bits_size = T_8452_io_slave_ar_bits_size;
+ assign T_10206_3_slave_ar_bits_burst = T_8452_io_slave_ar_bits_burst;
+ assign T_10206_3_slave_ar_bits_lock = T_8452_io_slave_ar_bits_lock;
+ assign T_10206_3_slave_ar_bits_cache = T_8452_io_slave_ar_bits_cache;
+ assign T_10206_3_slave_ar_bits_prot = T_8452_io_slave_ar_bits_prot;
+ assign T_10206_3_slave_ar_bits_qos = T_8452_io_slave_ar_bits_qos;
+ assign T_10206_3_slave_ar_bits_region = T_8452_io_slave_ar_bits_region;
+ assign T_10206_3_slave_ar_bits_id = T_8452_io_slave_ar_bits_id;
+ assign T_10206_3_slave_ar_bits_user = T_8452_io_slave_ar_bits_user;
+ assign T_10206_3_slave_r_ready = T_8452_io_slave_r_ready;
+ assign T_10206_3_slave_r_valid = io_slaves_3_r_valid;
+ assign T_10206_3_slave_r_bits_resp = io_slaves_3_r_bits_resp;
+ assign T_10206_3_slave_r_bits_data = io_slaves_3_r_bits_data;
+ assign T_10206_3_slave_r_bits_last = io_slaves_3_r_bits_last;
+ assign T_10206_3_slave_r_bits_id = io_slaves_3_r_bits_id;
+ assign T_10206_3_slave_r_bits_user = io_slaves_3_r_bits_user;
+ assign T_19131_0_aw_ready = T_10206_0_master_0_aw_ready;
+ assign T_19131_0_aw_valid = T_4146_0_slave_0_aw_valid;
+ assign T_19131_0_aw_bits_addr = T_4146_0_slave_0_aw_bits_addr;
+ assign T_19131_0_aw_bits_len = T_4146_0_slave_0_aw_bits_len;
+ assign T_19131_0_aw_bits_size = T_4146_0_slave_0_aw_bits_size;
+ assign T_19131_0_aw_bits_burst = T_4146_0_slave_0_aw_bits_burst;
+ assign T_19131_0_aw_bits_lock = T_4146_0_slave_0_aw_bits_lock;
+ assign T_19131_0_aw_bits_cache = T_4146_0_slave_0_aw_bits_cache;
+ assign T_19131_0_aw_bits_prot = T_4146_0_slave_0_aw_bits_prot;
+ assign T_19131_0_aw_bits_qos = T_4146_0_slave_0_aw_bits_qos;
+ assign T_19131_0_aw_bits_region = T_4146_0_slave_0_aw_bits_region;
+ assign T_19131_0_aw_bits_id = T_4146_0_slave_0_aw_bits_id;
+ assign T_19131_0_aw_bits_user = T_4146_0_slave_0_aw_bits_user;
+ assign T_19131_0_w_ready = T_10206_0_master_0_w_ready;
+ assign T_19131_0_w_valid = T_4146_0_slave_0_w_valid;
+ assign T_19131_0_w_bits_data = T_4146_0_slave_0_w_bits_data;
+ assign T_19131_0_w_bits_last = T_4146_0_slave_0_w_bits_last;
+ assign T_19131_0_w_bits_strb = T_4146_0_slave_0_w_bits_strb;
+ assign T_19131_0_w_bits_user = T_4146_0_slave_0_w_bits_user;
+ assign T_19131_0_b_ready = T_4146_0_slave_0_b_ready;
+ assign T_19131_0_b_valid = T_10206_0_master_0_b_valid;
+ assign T_19131_0_b_bits_resp = T_10206_0_master_0_b_bits_resp;
+ assign T_19131_0_b_bits_id = T_10206_0_master_0_b_bits_id;
+ assign T_19131_0_b_bits_user = T_10206_0_master_0_b_bits_user;
+ assign T_19131_0_ar_ready = T_10206_0_master_0_ar_ready;
+ assign T_19131_0_ar_valid = T_4146_0_slave_0_ar_valid;
+ assign T_19131_0_ar_bits_addr = T_4146_0_slave_0_ar_bits_addr;
+ assign T_19131_0_ar_bits_len = T_4146_0_slave_0_ar_bits_len;
+ assign T_19131_0_ar_bits_size = T_4146_0_slave_0_ar_bits_size;
+ assign T_19131_0_ar_bits_burst = T_4146_0_slave_0_ar_bits_burst;
+ assign T_19131_0_ar_bits_lock = T_4146_0_slave_0_ar_bits_lock;
+ assign T_19131_0_ar_bits_cache = T_4146_0_slave_0_ar_bits_cache;
+ assign T_19131_0_ar_bits_prot = T_4146_0_slave_0_ar_bits_prot;
+ assign T_19131_0_ar_bits_qos = T_4146_0_slave_0_ar_bits_qos;
+ assign T_19131_0_ar_bits_region = T_4146_0_slave_0_ar_bits_region;
+ assign T_19131_0_ar_bits_id = T_4146_0_slave_0_ar_bits_id;
+ assign T_19131_0_ar_bits_user = T_4146_0_slave_0_ar_bits_user;
+ assign T_19131_0_r_ready = T_4146_0_slave_0_r_ready;
+ assign T_19131_0_r_valid = T_10206_0_master_0_r_valid;
+ assign T_19131_0_r_bits_resp = T_10206_0_master_0_r_bits_resp;
+ assign T_19131_0_r_bits_data = T_10206_0_master_0_r_bits_data;
+ assign T_19131_0_r_bits_last = T_10206_0_master_0_r_bits_last;
+ assign T_19131_0_r_bits_id = T_10206_0_master_0_r_bits_id;
+ assign T_19131_0_r_bits_user = T_10206_0_master_0_r_bits_user;
+ assign T_19131_1_aw_ready = T_10206_0_master_1_aw_ready;
+ assign T_19131_1_aw_valid = T_4146_1_slave_0_aw_valid;
+ assign T_19131_1_aw_bits_addr = T_4146_1_slave_0_aw_bits_addr;
+ assign T_19131_1_aw_bits_len = T_4146_1_slave_0_aw_bits_len;
+ assign T_19131_1_aw_bits_size = T_4146_1_slave_0_aw_bits_size;
+ assign T_19131_1_aw_bits_burst = T_4146_1_slave_0_aw_bits_burst;
+ assign T_19131_1_aw_bits_lock = T_4146_1_slave_0_aw_bits_lock;
+ assign T_19131_1_aw_bits_cache = T_4146_1_slave_0_aw_bits_cache;
+ assign T_19131_1_aw_bits_prot = T_4146_1_slave_0_aw_bits_prot;
+ assign T_19131_1_aw_bits_qos = T_4146_1_slave_0_aw_bits_qos;
+ assign T_19131_1_aw_bits_region = T_4146_1_slave_0_aw_bits_region;
+ assign T_19131_1_aw_bits_id = T_4146_1_slave_0_aw_bits_id;
+ assign T_19131_1_aw_bits_user = T_4146_1_slave_0_aw_bits_user;
+ assign T_19131_1_w_ready = T_10206_0_master_1_w_ready;
+ assign T_19131_1_w_valid = T_4146_1_slave_0_w_valid;
+ assign T_19131_1_w_bits_data = T_4146_1_slave_0_w_bits_data;
+ assign T_19131_1_w_bits_last = T_4146_1_slave_0_w_bits_last;
+ assign T_19131_1_w_bits_strb = T_4146_1_slave_0_w_bits_strb;
+ assign T_19131_1_w_bits_user = T_4146_1_slave_0_w_bits_user;
+ assign T_19131_1_b_ready = T_4146_1_slave_0_b_ready;
+ assign T_19131_1_b_valid = T_10206_0_master_1_b_valid;
+ assign T_19131_1_b_bits_resp = T_10206_0_master_1_b_bits_resp;
+ assign T_19131_1_b_bits_id = T_10206_0_master_1_b_bits_id;
+ assign T_19131_1_b_bits_user = T_10206_0_master_1_b_bits_user;
+ assign T_19131_1_ar_ready = T_10206_0_master_1_ar_ready;
+ assign T_19131_1_ar_valid = T_4146_1_slave_0_ar_valid;
+ assign T_19131_1_ar_bits_addr = T_4146_1_slave_0_ar_bits_addr;
+ assign T_19131_1_ar_bits_len = T_4146_1_slave_0_ar_bits_len;
+ assign T_19131_1_ar_bits_size = T_4146_1_slave_0_ar_bits_size;
+ assign T_19131_1_ar_bits_burst = T_4146_1_slave_0_ar_bits_burst;
+ assign T_19131_1_ar_bits_lock = T_4146_1_slave_0_ar_bits_lock;
+ assign T_19131_1_ar_bits_cache = T_4146_1_slave_0_ar_bits_cache;
+ assign T_19131_1_ar_bits_prot = T_4146_1_slave_0_ar_bits_prot;
+ assign T_19131_1_ar_bits_qos = T_4146_1_slave_0_ar_bits_qos;
+ assign T_19131_1_ar_bits_region = T_4146_1_slave_0_ar_bits_region;
+ assign T_19131_1_ar_bits_id = T_4146_1_slave_0_ar_bits_id;
+ assign T_19131_1_ar_bits_user = T_4146_1_slave_0_ar_bits_user;
+ assign T_19131_1_r_ready = T_4146_1_slave_0_r_ready;
+ assign T_19131_1_r_valid = T_10206_0_master_1_r_valid;
+ assign T_19131_1_r_bits_resp = T_10206_0_master_1_r_bits_resp;
+ assign T_19131_1_r_bits_data = T_10206_0_master_1_r_bits_data;
+ assign T_19131_1_r_bits_last = T_10206_0_master_1_r_bits_last;
+ assign T_19131_1_r_bits_id = T_10206_0_master_1_r_bits_id;
+ assign T_19131_1_r_bits_user = T_10206_0_master_1_r_bits_user;
+ assign T_19768_0_aw_ready = T_10206_1_master_0_aw_ready;
+ assign T_19768_0_aw_valid = T_4146_0_slave_1_aw_valid;
+ assign T_19768_0_aw_bits_addr = T_4146_0_slave_1_aw_bits_addr;
+ assign T_19768_0_aw_bits_len = T_4146_0_slave_1_aw_bits_len;
+ assign T_19768_0_aw_bits_size = T_4146_0_slave_1_aw_bits_size;
+ assign T_19768_0_aw_bits_burst = T_4146_0_slave_1_aw_bits_burst;
+ assign T_19768_0_aw_bits_lock = T_4146_0_slave_1_aw_bits_lock;
+ assign T_19768_0_aw_bits_cache = T_4146_0_slave_1_aw_bits_cache;
+ assign T_19768_0_aw_bits_prot = T_4146_0_slave_1_aw_bits_prot;
+ assign T_19768_0_aw_bits_qos = T_4146_0_slave_1_aw_bits_qos;
+ assign T_19768_0_aw_bits_region = T_4146_0_slave_1_aw_bits_region;
+ assign T_19768_0_aw_bits_id = T_4146_0_slave_1_aw_bits_id;
+ assign T_19768_0_aw_bits_user = T_4146_0_slave_1_aw_bits_user;
+ assign T_19768_0_w_ready = T_10206_1_master_0_w_ready;
+ assign T_19768_0_w_valid = T_4146_0_slave_1_w_valid;
+ assign T_19768_0_w_bits_data = T_4146_0_slave_1_w_bits_data;
+ assign T_19768_0_w_bits_last = T_4146_0_slave_1_w_bits_last;
+ assign T_19768_0_w_bits_strb = T_4146_0_slave_1_w_bits_strb;
+ assign T_19768_0_w_bits_user = T_4146_0_slave_1_w_bits_user;
+ assign T_19768_0_b_ready = T_4146_0_slave_1_b_ready;
+ assign T_19768_0_b_valid = T_10206_1_master_0_b_valid;
+ assign T_19768_0_b_bits_resp = T_10206_1_master_0_b_bits_resp;
+ assign T_19768_0_b_bits_id = T_10206_1_master_0_b_bits_id;
+ assign T_19768_0_b_bits_user = T_10206_1_master_0_b_bits_user;
+ assign T_19768_0_ar_ready = T_10206_1_master_0_ar_ready;
+ assign T_19768_0_ar_valid = T_4146_0_slave_1_ar_valid;
+ assign T_19768_0_ar_bits_addr = T_4146_0_slave_1_ar_bits_addr;
+ assign T_19768_0_ar_bits_len = T_4146_0_slave_1_ar_bits_len;
+ assign T_19768_0_ar_bits_size = T_4146_0_slave_1_ar_bits_size;
+ assign T_19768_0_ar_bits_burst = T_4146_0_slave_1_ar_bits_burst;
+ assign T_19768_0_ar_bits_lock = T_4146_0_slave_1_ar_bits_lock;
+ assign T_19768_0_ar_bits_cache = T_4146_0_slave_1_ar_bits_cache;
+ assign T_19768_0_ar_bits_prot = T_4146_0_slave_1_ar_bits_prot;
+ assign T_19768_0_ar_bits_qos = T_4146_0_slave_1_ar_bits_qos;
+ assign T_19768_0_ar_bits_region = T_4146_0_slave_1_ar_bits_region;
+ assign T_19768_0_ar_bits_id = T_4146_0_slave_1_ar_bits_id;
+ assign T_19768_0_ar_bits_user = T_4146_0_slave_1_ar_bits_user;
+ assign T_19768_0_r_ready = T_4146_0_slave_1_r_ready;
+ assign T_19768_0_r_valid = T_10206_1_master_0_r_valid;
+ assign T_19768_0_r_bits_resp = T_10206_1_master_0_r_bits_resp;
+ assign T_19768_0_r_bits_data = T_10206_1_master_0_r_bits_data;
+ assign T_19768_0_r_bits_last = T_10206_1_master_0_r_bits_last;
+ assign T_19768_0_r_bits_id = T_10206_1_master_0_r_bits_id;
+ assign T_19768_0_r_bits_user = T_10206_1_master_0_r_bits_user;
+ assign T_19768_1_aw_ready = T_10206_1_master_1_aw_ready;
+ assign T_19768_1_aw_valid = T_4146_1_slave_1_aw_valid;
+ assign T_19768_1_aw_bits_addr = T_4146_1_slave_1_aw_bits_addr;
+ assign T_19768_1_aw_bits_len = T_4146_1_slave_1_aw_bits_len;
+ assign T_19768_1_aw_bits_size = T_4146_1_slave_1_aw_bits_size;
+ assign T_19768_1_aw_bits_burst = T_4146_1_slave_1_aw_bits_burst;
+ assign T_19768_1_aw_bits_lock = T_4146_1_slave_1_aw_bits_lock;
+ assign T_19768_1_aw_bits_cache = T_4146_1_slave_1_aw_bits_cache;
+ assign T_19768_1_aw_bits_prot = T_4146_1_slave_1_aw_bits_prot;
+ assign T_19768_1_aw_bits_qos = T_4146_1_slave_1_aw_bits_qos;
+ assign T_19768_1_aw_bits_region = T_4146_1_slave_1_aw_bits_region;
+ assign T_19768_1_aw_bits_id = T_4146_1_slave_1_aw_bits_id;
+ assign T_19768_1_aw_bits_user = T_4146_1_slave_1_aw_bits_user;
+ assign T_19768_1_w_ready = T_10206_1_master_1_w_ready;
+ assign T_19768_1_w_valid = T_4146_1_slave_1_w_valid;
+ assign T_19768_1_w_bits_data = T_4146_1_slave_1_w_bits_data;
+ assign T_19768_1_w_bits_last = T_4146_1_slave_1_w_bits_last;
+ assign T_19768_1_w_bits_strb = T_4146_1_slave_1_w_bits_strb;
+ assign T_19768_1_w_bits_user = T_4146_1_slave_1_w_bits_user;
+ assign T_19768_1_b_ready = T_4146_1_slave_1_b_ready;
+ assign T_19768_1_b_valid = T_10206_1_master_1_b_valid;
+ assign T_19768_1_b_bits_resp = T_10206_1_master_1_b_bits_resp;
+ assign T_19768_1_b_bits_id = T_10206_1_master_1_b_bits_id;
+ assign T_19768_1_b_bits_user = T_10206_1_master_1_b_bits_user;
+ assign T_19768_1_ar_ready = T_10206_1_master_1_ar_ready;
+ assign T_19768_1_ar_valid = T_4146_1_slave_1_ar_valid;
+ assign T_19768_1_ar_bits_addr = T_4146_1_slave_1_ar_bits_addr;
+ assign T_19768_1_ar_bits_len = T_4146_1_slave_1_ar_bits_len;
+ assign T_19768_1_ar_bits_size = T_4146_1_slave_1_ar_bits_size;
+ assign T_19768_1_ar_bits_burst = T_4146_1_slave_1_ar_bits_burst;
+ assign T_19768_1_ar_bits_lock = T_4146_1_slave_1_ar_bits_lock;
+ assign T_19768_1_ar_bits_cache = T_4146_1_slave_1_ar_bits_cache;
+ assign T_19768_1_ar_bits_prot = T_4146_1_slave_1_ar_bits_prot;
+ assign T_19768_1_ar_bits_qos = T_4146_1_slave_1_ar_bits_qos;
+ assign T_19768_1_ar_bits_region = T_4146_1_slave_1_ar_bits_region;
+ assign T_19768_1_ar_bits_id = T_4146_1_slave_1_ar_bits_id;
+ assign T_19768_1_ar_bits_user = T_4146_1_slave_1_ar_bits_user;
+ assign T_19768_1_r_ready = T_4146_1_slave_1_r_ready;
+ assign T_19768_1_r_valid = T_10206_1_master_1_r_valid;
+ assign T_19768_1_r_bits_resp = T_10206_1_master_1_r_bits_resp;
+ assign T_19768_1_r_bits_data = T_10206_1_master_1_r_bits_data;
+ assign T_19768_1_r_bits_last = T_10206_1_master_1_r_bits_last;
+ assign T_19768_1_r_bits_id = T_10206_1_master_1_r_bits_id;
+ assign T_19768_1_r_bits_user = T_10206_1_master_1_r_bits_user;
+ assign T_20405_0_aw_ready = T_10206_2_master_0_aw_ready;
+ assign T_20405_0_aw_valid = T_4146_0_slave_2_aw_valid;
+ assign T_20405_0_aw_bits_addr = T_4146_0_slave_2_aw_bits_addr;
+ assign T_20405_0_aw_bits_len = T_4146_0_slave_2_aw_bits_len;
+ assign T_20405_0_aw_bits_size = T_4146_0_slave_2_aw_bits_size;
+ assign T_20405_0_aw_bits_burst = T_4146_0_slave_2_aw_bits_burst;
+ assign T_20405_0_aw_bits_lock = T_4146_0_slave_2_aw_bits_lock;
+ assign T_20405_0_aw_bits_cache = T_4146_0_slave_2_aw_bits_cache;
+ assign T_20405_0_aw_bits_prot = T_4146_0_slave_2_aw_bits_prot;
+ assign T_20405_0_aw_bits_qos = T_4146_0_slave_2_aw_bits_qos;
+ assign T_20405_0_aw_bits_region = T_4146_0_slave_2_aw_bits_region;
+ assign T_20405_0_aw_bits_id = T_4146_0_slave_2_aw_bits_id;
+ assign T_20405_0_aw_bits_user = T_4146_0_slave_2_aw_bits_user;
+ assign T_20405_0_w_ready = T_10206_2_master_0_w_ready;
+ assign T_20405_0_w_valid = T_4146_0_slave_2_w_valid;
+ assign T_20405_0_w_bits_data = T_4146_0_slave_2_w_bits_data;
+ assign T_20405_0_w_bits_last = T_4146_0_slave_2_w_bits_last;
+ assign T_20405_0_w_bits_strb = T_4146_0_slave_2_w_bits_strb;
+ assign T_20405_0_w_bits_user = T_4146_0_slave_2_w_bits_user;
+ assign T_20405_0_b_ready = T_4146_0_slave_2_b_ready;
+ assign T_20405_0_b_valid = T_10206_2_master_0_b_valid;
+ assign T_20405_0_b_bits_resp = T_10206_2_master_0_b_bits_resp;
+ assign T_20405_0_b_bits_id = T_10206_2_master_0_b_bits_id;
+ assign T_20405_0_b_bits_user = T_10206_2_master_0_b_bits_user;
+ assign T_20405_0_ar_ready = T_10206_2_master_0_ar_ready;
+ assign T_20405_0_ar_valid = T_4146_0_slave_2_ar_valid;
+ assign T_20405_0_ar_bits_addr = T_4146_0_slave_2_ar_bits_addr;
+ assign T_20405_0_ar_bits_len = T_4146_0_slave_2_ar_bits_len;
+ assign T_20405_0_ar_bits_size = T_4146_0_slave_2_ar_bits_size;
+ assign T_20405_0_ar_bits_burst = T_4146_0_slave_2_ar_bits_burst;
+ assign T_20405_0_ar_bits_lock = T_4146_0_slave_2_ar_bits_lock;
+ assign T_20405_0_ar_bits_cache = T_4146_0_slave_2_ar_bits_cache;
+ assign T_20405_0_ar_bits_prot = T_4146_0_slave_2_ar_bits_prot;
+ assign T_20405_0_ar_bits_qos = T_4146_0_slave_2_ar_bits_qos;
+ assign T_20405_0_ar_bits_region = T_4146_0_slave_2_ar_bits_region;
+ assign T_20405_0_ar_bits_id = T_4146_0_slave_2_ar_bits_id;
+ assign T_20405_0_ar_bits_user = T_4146_0_slave_2_ar_bits_user;
+ assign T_20405_0_r_ready = T_4146_0_slave_2_r_ready;
+ assign T_20405_0_r_valid = T_10206_2_master_0_r_valid;
+ assign T_20405_0_r_bits_resp = T_10206_2_master_0_r_bits_resp;
+ assign T_20405_0_r_bits_data = T_10206_2_master_0_r_bits_data;
+ assign T_20405_0_r_bits_last = T_10206_2_master_0_r_bits_last;
+ assign T_20405_0_r_bits_id = T_10206_2_master_0_r_bits_id;
+ assign T_20405_0_r_bits_user = T_10206_2_master_0_r_bits_user;
+ assign T_20405_1_aw_ready = T_10206_2_master_1_aw_ready;
+ assign T_20405_1_aw_valid = T_4146_1_slave_2_aw_valid;
+ assign T_20405_1_aw_bits_addr = T_4146_1_slave_2_aw_bits_addr;
+ assign T_20405_1_aw_bits_len = T_4146_1_slave_2_aw_bits_len;
+ assign T_20405_1_aw_bits_size = T_4146_1_slave_2_aw_bits_size;
+ assign T_20405_1_aw_bits_burst = T_4146_1_slave_2_aw_bits_burst;
+ assign T_20405_1_aw_bits_lock = T_4146_1_slave_2_aw_bits_lock;
+ assign T_20405_1_aw_bits_cache = T_4146_1_slave_2_aw_bits_cache;
+ assign T_20405_1_aw_bits_prot = T_4146_1_slave_2_aw_bits_prot;
+ assign T_20405_1_aw_bits_qos = T_4146_1_slave_2_aw_bits_qos;
+ assign T_20405_1_aw_bits_region = T_4146_1_slave_2_aw_bits_region;
+ assign T_20405_1_aw_bits_id = T_4146_1_slave_2_aw_bits_id;
+ assign T_20405_1_aw_bits_user = T_4146_1_slave_2_aw_bits_user;
+ assign T_20405_1_w_ready = T_10206_2_master_1_w_ready;
+ assign T_20405_1_w_valid = T_4146_1_slave_2_w_valid;
+ assign T_20405_1_w_bits_data = T_4146_1_slave_2_w_bits_data;
+ assign T_20405_1_w_bits_last = T_4146_1_slave_2_w_bits_last;
+ assign T_20405_1_w_bits_strb = T_4146_1_slave_2_w_bits_strb;
+ assign T_20405_1_w_bits_user = T_4146_1_slave_2_w_bits_user;
+ assign T_20405_1_b_ready = T_4146_1_slave_2_b_ready;
+ assign T_20405_1_b_valid = T_10206_2_master_1_b_valid;
+ assign T_20405_1_b_bits_resp = T_10206_2_master_1_b_bits_resp;
+ assign T_20405_1_b_bits_id = T_10206_2_master_1_b_bits_id;
+ assign T_20405_1_b_bits_user = T_10206_2_master_1_b_bits_user;
+ assign T_20405_1_ar_ready = T_10206_2_master_1_ar_ready;
+ assign T_20405_1_ar_valid = T_4146_1_slave_2_ar_valid;
+ assign T_20405_1_ar_bits_addr = T_4146_1_slave_2_ar_bits_addr;
+ assign T_20405_1_ar_bits_len = T_4146_1_slave_2_ar_bits_len;
+ assign T_20405_1_ar_bits_size = T_4146_1_slave_2_ar_bits_size;
+ assign T_20405_1_ar_bits_burst = T_4146_1_slave_2_ar_bits_burst;
+ assign T_20405_1_ar_bits_lock = T_4146_1_slave_2_ar_bits_lock;
+ assign T_20405_1_ar_bits_cache = T_4146_1_slave_2_ar_bits_cache;
+ assign T_20405_1_ar_bits_prot = T_4146_1_slave_2_ar_bits_prot;
+ assign T_20405_1_ar_bits_qos = T_4146_1_slave_2_ar_bits_qos;
+ assign T_20405_1_ar_bits_region = T_4146_1_slave_2_ar_bits_region;
+ assign T_20405_1_ar_bits_id = T_4146_1_slave_2_ar_bits_id;
+ assign T_20405_1_ar_bits_user = T_4146_1_slave_2_ar_bits_user;
+ assign T_20405_1_r_ready = T_4146_1_slave_2_r_ready;
+ assign T_20405_1_r_valid = T_10206_2_master_1_r_valid;
+ assign T_20405_1_r_bits_resp = T_10206_2_master_1_r_bits_resp;
+ assign T_20405_1_r_bits_data = T_10206_2_master_1_r_bits_data;
+ assign T_20405_1_r_bits_last = T_10206_2_master_1_r_bits_last;
+ assign T_20405_1_r_bits_id = T_10206_2_master_1_r_bits_id;
+ assign T_20405_1_r_bits_user = T_10206_2_master_1_r_bits_user;
+ assign T_21042_0_aw_ready = T_10206_3_master_0_aw_ready;
+ assign T_21042_0_aw_valid = T_4146_0_slave_3_aw_valid;
+ assign T_21042_0_aw_bits_addr = T_4146_0_slave_3_aw_bits_addr;
+ assign T_21042_0_aw_bits_len = T_4146_0_slave_3_aw_bits_len;
+ assign T_21042_0_aw_bits_size = T_4146_0_slave_3_aw_bits_size;
+ assign T_21042_0_aw_bits_burst = T_4146_0_slave_3_aw_bits_burst;
+ assign T_21042_0_aw_bits_lock = T_4146_0_slave_3_aw_bits_lock;
+ assign T_21042_0_aw_bits_cache = T_4146_0_slave_3_aw_bits_cache;
+ assign T_21042_0_aw_bits_prot = T_4146_0_slave_3_aw_bits_prot;
+ assign T_21042_0_aw_bits_qos = T_4146_0_slave_3_aw_bits_qos;
+ assign T_21042_0_aw_bits_region = T_4146_0_slave_3_aw_bits_region;
+ assign T_21042_0_aw_bits_id = T_4146_0_slave_3_aw_bits_id;
+ assign T_21042_0_aw_bits_user = T_4146_0_slave_3_aw_bits_user;
+ assign T_21042_0_w_ready = T_10206_3_master_0_w_ready;
+ assign T_21042_0_w_valid = T_4146_0_slave_3_w_valid;
+ assign T_21042_0_w_bits_data = T_4146_0_slave_3_w_bits_data;
+ assign T_21042_0_w_bits_last = T_4146_0_slave_3_w_bits_last;
+ assign T_21042_0_w_bits_strb = T_4146_0_slave_3_w_bits_strb;
+ assign T_21042_0_w_bits_user = T_4146_0_slave_3_w_bits_user;
+ assign T_21042_0_b_ready = T_4146_0_slave_3_b_ready;
+ assign T_21042_0_b_valid = T_10206_3_master_0_b_valid;
+ assign T_21042_0_b_bits_resp = T_10206_3_master_0_b_bits_resp;
+ assign T_21042_0_b_bits_id = T_10206_3_master_0_b_bits_id;
+ assign T_21042_0_b_bits_user = T_10206_3_master_0_b_bits_user;
+ assign T_21042_0_ar_ready = T_10206_3_master_0_ar_ready;
+ assign T_21042_0_ar_valid = T_4146_0_slave_3_ar_valid;
+ assign T_21042_0_ar_bits_addr = T_4146_0_slave_3_ar_bits_addr;
+ assign T_21042_0_ar_bits_len = T_4146_0_slave_3_ar_bits_len;
+ assign T_21042_0_ar_bits_size = T_4146_0_slave_3_ar_bits_size;
+ assign T_21042_0_ar_bits_burst = T_4146_0_slave_3_ar_bits_burst;
+ assign T_21042_0_ar_bits_lock = T_4146_0_slave_3_ar_bits_lock;
+ assign T_21042_0_ar_bits_cache = T_4146_0_slave_3_ar_bits_cache;
+ assign T_21042_0_ar_bits_prot = T_4146_0_slave_3_ar_bits_prot;
+ assign T_21042_0_ar_bits_qos = T_4146_0_slave_3_ar_bits_qos;
+ assign T_21042_0_ar_bits_region = T_4146_0_slave_3_ar_bits_region;
+ assign T_21042_0_ar_bits_id = T_4146_0_slave_3_ar_bits_id;
+ assign T_21042_0_ar_bits_user = T_4146_0_slave_3_ar_bits_user;
+ assign T_21042_0_r_ready = T_4146_0_slave_3_r_ready;
+ assign T_21042_0_r_valid = T_10206_3_master_0_r_valid;
+ assign T_21042_0_r_bits_resp = T_10206_3_master_0_r_bits_resp;
+ assign T_21042_0_r_bits_data = T_10206_3_master_0_r_bits_data;
+ assign T_21042_0_r_bits_last = T_10206_3_master_0_r_bits_last;
+ assign T_21042_0_r_bits_id = T_10206_3_master_0_r_bits_id;
+ assign T_21042_0_r_bits_user = T_10206_3_master_0_r_bits_user;
+ assign T_21042_1_aw_ready = T_10206_3_master_1_aw_ready;
+ assign T_21042_1_aw_valid = T_4146_1_slave_3_aw_valid;
+ assign T_21042_1_aw_bits_addr = T_4146_1_slave_3_aw_bits_addr;
+ assign T_21042_1_aw_bits_len = T_4146_1_slave_3_aw_bits_len;
+ assign T_21042_1_aw_bits_size = T_4146_1_slave_3_aw_bits_size;
+ assign T_21042_1_aw_bits_burst = T_4146_1_slave_3_aw_bits_burst;
+ assign T_21042_1_aw_bits_lock = T_4146_1_slave_3_aw_bits_lock;
+ assign T_21042_1_aw_bits_cache = T_4146_1_slave_3_aw_bits_cache;
+ assign T_21042_1_aw_bits_prot = T_4146_1_slave_3_aw_bits_prot;
+ assign T_21042_1_aw_bits_qos = T_4146_1_slave_3_aw_bits_qos;
+ assign T_21042_1_aw_bits_region = T_4146_1_slave_3_aw_bits_region;
+ assign T_21042_1_aw_bits_id = T_4146_1_slave_3_aw_bits_id;
+ assign T_21042_1_aw_bits_user = T_4146_1_slave_3_aw_bits_user;
+ assign T_21042_1_w_ready = T_10206_3_master_1_w_ready;
+ assign T_21042_1_w_valid = T_4146_1_slave_3_w_valid;
+ assign T_21042_1_w_bits_data = T_4146_1_slave_3_w_bits_data;
+ assign T_21042_1_w_bits_last = T_4146_1_slave_3_w_bits_last;
+ assign T_21042_1_w_bits_strb = T_4146_1_slave_3_w_bits_strb;
+ assign T_21042_1_w_bits_user = T_4146_1_slave_3_w_bits_user;
+ assign T_21042_1_b_ready = T_4146_1_slave_3_b_ready;
+ assign T_21042_1_b_valid = T_10206_3_master_1_b_valid;
+ assign T_21042_1_b_bits_resp = T_10206_3_master_1_b_bits_resp;
+ assign T_21042_1_b_bits_id = T_10206_3_master_1_b_bits_id;
+ assign T_21042_1_b_bits_user = T_10206_3_master_1_b_bits_user;
+ assign T_21042_1_ar_ready = T_10206_3_master_1_ar_ready;
+ assign T_21042_1_ar_valid = T_4146_1_slave_3_ar_valid;
+ assign T_21042_1_ar_bits_addr = T_4146_1_slave_3_ar_bits_addr;
+ assign T_21042_1_ar_bits_len = T_4146_1_slave_3_ar_bits_len;
+ assign T_21042_1_ar_bits_size = T_4146_1_slave_3_ar_bits_size;
+ assign T_21042_1_ar_bits_burst = T_4146_1_slave_3_ar_bits_burst;
+ assign T_21042_1_ar_bits_lock = T_4146_1_slave_3_ar_bits_lock;
+ assign T_21042_1_ar_bits_cache = T_4146_1_slave_3_ar_bits_cache;
+ assign T_21042_1_ar_bits_prot = T_4146_1_slave_3_ar_bits_prot;
+ assign T_21042_1_ar_bits_qos = T_4146_1_slave_3_ar_bits_qos;
+ assign T_21042_1_ar_bits_region = T_4146_1_slave_3_ar_bits_region;
+ assign T_21042_1_ar_bits_id = T_4146_1_slave_3_ar_bits_id;
+ assign T_21042_1_ar_bits_user = T_4146_1_slave_3_ar_bits_user;
+ assign T_21042_1_r_ready = T_4146_1_slave_3_r_ready;
+ assign T_21042_1_r_valid = T_10206_3_master_1_r_valid;
+ assign T_21042_1_r_bits_resp = T_10206_3_master_1_r_bits_resp;
+ assign T_21042_1_r_bits_data = T_10206_3_master_1_r_bits_data;
+ assign T_21042_1_r_bits_last = T_10206_3_master_1_r_bits_last;
+ assign T_21042_1_r_bits_id = T_10206_3_master_1_r_bits_id;
+ assign T_21042_1_r_bits_user = T_10206_3_master_1_r_bits_user;
+endmodule
+module RRArbiter_62(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input [1:0] io_in_0_bits_resp,
+ input [4:0] io_in_0_bits_id,
+ input io_in_0_bits_user,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input [1:0] io_in_1_bits_resp,
+ input [4:0] io_in_1_bits_id,
+ input io_in_1_bits_user,
+ output io_in_2_ready,
+ input io_in_2_valid,
+ input [1:0] io_in_2_bits_resp,
+ input [4:0] io_in_2_bits_id,
+ input io_in_2_bits_user,
+ output io_in_3_ready,
+ input io_in_3_valid,
+ input [1:0] io_in_3_bits_resp,
+ input [4:0] io_in_3_bits_id,
+ input io_in_3_bits_user,
+ input io_out_ready,
+ output io_out_valid,
+ output [1:0] io_out_bits_resp,
+ output [4:0] io_out_bits_id,
+ output io_out_bits_user,
+ output [1:0] io_chosen
+);
+ wire [1:0] T_174;
+ wire GEN_0;
+ wire [1:0] GEN_1;
+ wire [4:0] GEN_2;
+ wire GEN_3;
+ wire GEN_4;
+ reg [1:0] T_211;
+ wire T_212;
+ wire T_213;
+ wire T_215;
+ wire T_216;
+ wire T_218;
+ wire T_219;
+ wire T_221;
+ wire T_222;
+ wire T_225;
+ wire T_227;
+ wire T_229;
+ wire T_230;
+ wire T_232;
+ wire T_234;
+ wire T_235;
+ wire T_236;
+ wire T_238;
+ wire T_240;
+ wire T_241;
+ wire T_242;
+ wire T_243;
+ wire T_245;
+ wire T_247;
+ wire T_248;
+ wire T_249;
+ wire T_250;
+ wire T_251;
+ wire T_253;
+ wire T_255;
+ wire T_256;
+ wire T_257;
+ wire T_258;
+ wire T_259;
+ wire T_260;
+ wire T_262;
+ wire T_264;
+ wire T_265;
+ wire T_266;
+ wire T_267;
+ wire T_268;
+ wire T_269;
+ wire T_270;
+ wire T_272;
+ wire T_274;
+ wire T_275;
+ wire T_276;
+ wire T_278;
+ wire T_279;
+ wire T_280;
+ wire T_282;
+ wire T_283;
+ wire T_284;
+ wire T_286;
+ wire T_287;
+ wire T_288;
+ wire T_290;
+ wire T_291;
+ wire T_292;
+ wire T_294;
+ wire T_295;
+ wire T_296;
+ wire T_298;
+ wire T_299;
+ wire T_300;
+ wire T_302;
+ wire T_303;
+ wire T_304;
+ wire [1:0] T_307;
+ wire [1:0] T_309;
+ wire [1:0] T_311;
+ wire T_313;
+ wire T_314;
+ wire [1:0] T_316;
+ wire T_318;
+ wire T_319;
+ wire [1:0] T_321;
+ wire T_323;
+ wire T_324;
+ wire [1:0] T_326;
+ wire [1:0] T_327;
+ wire T_328;
+ wire GEN_5;
+ wire GEN_6;
+ wire GEN_7;
+ wire GEN_8;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ assign io_in_0_ready = T_292;
+ assign io_in_1_ready = T_296;
+ assign io_in_2_ready = T_300;
+ assign io_in_3_ready = T_304;
+ assign io_out_valid = GEN_0;
+ assign io_out_bits_resp = GEN_1;
+ assign io_out_bits_id = GEN_2;
+ assign io_out_bits_user = GEN_3;
+ assign io_chosen = T_174;
+ assign T_174 = T_327;
+ assign GEN_0 = GEN_5 ? io_in_3_valid : GEN_6 ? io_in_2_valid : GEN_7 ? io_in_1_valid : io_in_0_valid;
+ assign GEN_1 = GEN_8 ? io_in_3_bits_resp : GEN_9 ? io_in_2_bits_resp : GEN_10 ? io_in_1_bits_resp : io_in_0_bits_resp;
+ assign GEN_2 = GEN_11 ? io_in_3_bits_id : GEN_12 ? io_in_2_bits_id : GEN_13 ? io_in_1_bits_id : io_in_0_bits_id;
+ assign GEN_3 = GEN_14 ? io_in_3_bits_user : GEN_15 ? io_in_2_bits_user : GEN_16 ? io_in_1_bits_user : io_in_0_bits_user;
+ assign GEN_4 = 1'h0;
+ assign T_212 = 1'h0 > T_211;
+ assign T_213 = io_in_0_valid & T_212;
+ assign T_215 = 1'h1 > T_211;
+ assign T_216 = io_in_1_valid & T_215;
+ assign T_218 = 2'h2 > T_211;
+ assign T_219 = io_in_2_valid & T_218;
+ assign T_221 = 2'h3 > T_211;
+ assign T_222 = io_in_3_valid & T_221;
+ assign T_225 = 1'h0 | T_213;
+ assign T_227 = T_225 == 1'h0;
+ assign T_229 = 1'h0 | T_213;
+ assign T_230 = T_229 | T_216;
+ assign T_232 = T_230 == 1'h0;
+ assign T_234 = 1'h0 | T_213;
+ assign T_235 = T_234 | T_216;
+ assign T_236 = T_235 | T_219;
+ assign T_238 = T_236 == 1'h0;
+ assign T_240 = 1'h0 | T_213;
+ assign T_241 = T_240 | T_216;
+ assign T_242 = T_241 | T_219;
+ assign T_243 = T_242 | T_222;
+ assign T_245 = T_243 == 1'h0;
+ assign T_247 = 1'h0 | T_213;
+ assign T_248 = T_247 | T_216;
+ assign T_249 = T_248 | T_219;
+ assign T_250 = T_249 | T_222;
+ assign T_251 = T_250 | io_in_0_valid;
+ assign T_253 = T_251 == 1'h0;
+ assign T_255 = 1'h0 | T_213;
+ assign T_256 = T_255 | T_216;
+ assign T_257 = T_256 | T_219;
+ assign T_258 = T_257 | T_222;
+ assign T_259 = T_258 | io_in_0_valid;
+ assign T_260 = T_259 | io_in_1_valid;
+ assign T_262 = T_260 == 1'h0;
+ assign T_264 = 1'h0 | T_213;
+ assign T_265 = T_264 | T_216;
+ assign T_266 = T_265 | T_219;
+ assign T_267 = T_266 | T_222;
+ assign T_268 = T_267 | io_in_0_valid;
+ assign T_269 = T_268 | io_in_1_valid;
+ assign T_270 = T_269 | io_in_2_valid;
+ assign T_272 = T_270 == 1'h0;
+ assign T_274 = 1'h0 > T_211;
+ assign T_275 = 1'h1 & T_274;
+ assign T_276 = T_275 | T_245;
+ assign T_278 = 1'h1 > T_211;
+ assign T_279 = T_227 & T_278;
+ assign T_280 = T_279 | T_253;
+ assign T_282 = 2'h2 > T_211;
+ assign T_283 = T_232 & T_282;
+ assign T_284 = T_283 | T_262;
+ assign T_286 = 2'h3 > T_211;
+ assign T_287 = T_238 & T_286;
+ assign T_288 = T_287 | T_272;
+ assign T_290 = 2'h3 == 1'h0;
+ assign T_291 = 1'h0 ? T_290 : T_276;
+ assign T_292 = T_291 & io_out_ready;
+ assign T_294 = 2'h3 == 1'h1;
+ assign T_295 = 1'h0 ? T_294 : T_280;
+ assign T_296 = T_295 & io_out_ready;
+ assign T_298 = 2'h3 == 2'h2;
+ assign T_299 = 1'h0 ? T_298 : T_284;
+ assign T_300 = T_299 & io_out_ready;
+ assign T_302 = 2'h3 == 2'h3;
+ assign T_303 = 1'h0 ? T_302 : T_288;
+ assign T_304 = T_303 & io_out_ready;
+ assign T_307 = io_in_2_valid ? 2'h2 : 2'h3;
+ assign T_309 = io_in_1_valid ? 1'h1 : T_307;
+ assign T_311 = io_in_0_valid ? 1'h0 : T_309;
+ assign T_313 = 2'h3 > T_211;
+ assign T_314 = io_in_3_valid & T_313;
+ assign T_316 = T_314 ? 2'h3 : T_311;
+ assign T_318 = 2'h2 > T_211;
+ assign T_319 = io_in_2_valid & T_318;
+ assign T_321 = T_319 ? 2'h2 : T_316;
+ assign T_323 = 1'h1 > T_211;
+ assign T_324 = io_in_1_valid & T_323;
+ assign T_326 = T_324 ? 1'h1 : T_321;
+ assign T_327 = 1'h0 ? 2'h3 : T_326;
+ assign T_328 = io_out_ready & io_out_valid;
+ assign GEN_5 = 2'h3 == T_174;
+ assign GEN_6 = 2'h2 == T_174;
+ assign GEN_7 = 1'h1 == T_174;
+ assign GEN_8 = 2'h3 == T_174;
+ assign GEN_9 = 2'h2 == T_174;
+ assign GEN_10 = 1'h1 == T_174;
+ assign GEN_11 = 2'h3 == T_174;
+ assign GEN_12 = 2'h2 == T_174;
+ assign GEN_13 = 1'h1 == T_174;
+ assign GEN_14 = 2'h3 == T_174;
+ assign GEN_15 = 2'h2 == T_174;
+ assign GEN_16 = 1'h1 == T_174;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_211 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ T_211 <= 2'h0;
+ end else begin
+ if(T_328) begin
+ T_211 <= T_174;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module JunctionsPeekingArbiter_63(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input [1:0] io_in_0_bits_resp,
+ input [63:0] io_in_0_bits_data,
+ input io_in_0_bits_last,
+ input [4:0] io_in_0_bits_id,
+ input io_in_0_bits_user,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input [1:0] io_in_1_bits_resp,
+ input [63:0] io_in_1_bits_data,
+ input io_in_1_bits_last,
+ input [4:0] io_in_1_bits_id,
+ input io_in_1_bits_user,
+ output io_in_2_ready,
+ input io_in_2_valid,
+ input [1:0] io_in_2_bits_resp,
+ input [63:0] io_in_2_bits_data,
+ input io_in_2_bits_last,
+ input [4:0] io_in_2_bits_id,
+ input io_in_2_bits_user,
+ output io_in_3_ready,
+ input io_in_3_valid,
+ input [1:0] io_in_3_bits_resp,
+ input [63:0] io_in_3_bits_data,
+ input io_in_3_bits_last,
+ input [4:0] io_in_3_bits_id,
+ input io_in_3_bits_user,
+ input io_out_ready,
+ output io_out_valid,
+ output [1:0] io_out_bits_resp,
+ output [63:0] io_out_bits_data,
+ output io_out_bits_last,
+ output [4:0] io_out_bits_id,
+ output io_out_bits_user
+);
+ reg [1:0] T_243;
+ reg T_245;
+ wire T_247_0;
+ wire T_247_1;
+ wire T_247_2;
+ wire T_247_3;
+ wire [2:0] T_254;
+ wire [1:0] T_255;
+ wire T_257;
+ wire [2:0] T_259;
+ wire [1:0] T_260;
+ wire [3:0] T_263;
+ wire [2:0] T_264;
+ wire GEN_0;
+ wire GEN_1;
+ wire T_266;
+ wire T_268;
+ wire [2:0] T_270;
+ wire [1:0] T_271;
+ wire [2:0] T_274;
+ wire [1:0] T_275;
+ wire GEN_2;
+ wire GEN_3;
+ wire T_277;
+ wire T_279;
+ wire [2:0] T_281;
+ wire [1:0] T_282;
+ wire [2:0] T_285;
+ wire [1:0] T_286;
+ wire GEN_4;
+ wire GEN_5;
+ wire T_288;
+ wire T_290;
+ wire [2:0] T_292;
+ wire [1:0] T_293;
+ wire [2:0] T_296;
+ wire [1:0] T_297;
+ wire GEN_6;
+ wire GEN_7;
+ wire T_299;
+ wire T_301_0;
+ wire T_301_1;
+ wire T_301_2;
+ wire T_301_3;
+ wire [1:0] T_312_0;
+ wire [1:0] T_312_1;
+ wire [1:0] T_312_2;
+ wire [1:0] T_312_3;
+ wire [2:0] T_319;
+ wire [1:0] T_320;
+ wire T_322;
+ wire [2:0] T_324;
+ wire [1:0] T_325;
+ wire [3:0] T_328;
+ wire [2:0] T_329;
+ wire [1:0] GEN_8;
+ wire [1:0] GEN_9;
+ wire [1:0] T_331;
+ wire T_333;
+ wire [2:0] T_335;
+ wire [1:0] T_336;
+ wire [2:0] T_339;
+ wire [1:0] T_340;
+ wire [1:0] GEN_10;
+ wire [1:0] GEN_11;
+ wire [1:0] T_342;
+ wire T_344;
+ wire [2:0] T_346;
+ wire [1:0] T_347;
+ wire [2:0] T_350;
+ wire [1:0] T_351;
+ wire [1:0] GEN_12;
+ wire [1:0] GEN_13;
+ wire [1:0] T_353;
+ wire T_355;
+ wire [2:0] T_357;
+ wire [1:0] T_358;
+ wire [2:0] T_361;
+ wire [1:0] T_362;
+ wire [1:0] GEN_14;
+ wire [1:0] GEN_15;
+ wire [1:0] T_364;
+ wire [1:0] T_366_0;
+ wire [1:0] T_366_1;
+ wire [1:0] T_366_2;
+ wire [1:0] T_366_3;
+ wire [1:0] T_372;
+ wire [1:0] T_373;
+ wire [1:0] T_374;
+ wire [1:0] T_375;
+ wire T_377;
+ wire T_378;
+ wire T_380;
+ wire T_381;
+ wire T_383;
+ wire T_384;
+ wire T_386;
+ wire T_387;
+ wire GEN_16;
+ wire [1:0] GEN_17;
+ wire [63:0] GEN_18;
+ wire GEN_19;
+ wire [4:0] GEN_20;
+ wire GEN_21;
+ wire T_418;
+ wire T_420;
+ wire T_422;
+ wire GEN_22;
+ wire GEN_23;
+ wire GEN_24;
+ wire GEN_25;
+ wire GEN_26;
+ wire GEN_27;
+ wire GEN_28;
+ wire GEN_29;
+ wire GEN_30;
+ wire GEN_31;
+ wire GEN_32;
+ wire GEN_33;
+ wire GEN_34;
+ wire GEN_35;
+ wire GEN_36;
+ wire GEN_37;
+ wire GEN_38;
+ wire GEN_39;
+ wire GEN_40;
+ wire GEN_41;
+ wire GEN_42;
+ wire GEN_43;
+ wire GEN_44;
+ wire GEN_45;
+ wire GEN_46;
+ wire GEN_47;
+ wire GEN_48;
+ wire GEN_49;
+ wire GEN_50;
+ wire GEN_51;
+ wire GEN_52;
+ wire GEN_53;
+ wire GEN_54;
+ wire GEN_55;
+ wire GEN_56;
+ wire GEN_57;
+ wire GEN_58;
+ wire GEN_59;
+ wire GEN_60;
+ wire GEN_61;
+ wire GEN_62;
+ wire GEN_63;
+ wire GEN_64;
+ wire GEN_65;
+ wire GEN_66;
+ wire GEN_67;
+ wire GEN_68;
+ wire GEN_69;
+ wire GEN_70;
+ wire GEN_71;
+ wire GEN_72;
+ wire GEN_73;
+ wire GEN_74;
+ wire GEN_75;
+ wire GEN_76;
+ wire GEN_77;
+ wire GEN_78;
+ wire GEN_79;
+ wire GEN_80;
+ wire GEN_81;
+ wire GEN_82;
+ wire GEN_83;
+ wire GEN_84;
+ wire GEN_85;
+ wire GEN_86;
+ wire GEN_87;
+ assign io_in_0_ready = T_378;
+ assign io_in_1_ready = T_381;
+ assign io_in_2_ready = T_384;
+ assign io_in_3_ready = T_387;
+ assign io_out_valid = GEN_16;
+ assign io_out_bits_resp = GEN_17;
+ assign io_out_bits_data = GEN_18;
+ assign io_out_bits_last = GEN_19;
+ assign io_out_bits_id = GEN_20;
+ assign io_out_bits_user = GEN_21;
+ assign T_247_0 = io_in_0_valid;
+ assign T_247_1 = io_in_1_valid;
+ assign T_247_2 = io_in_2_valid;
+ assign T_247_3 = io_in_3_valid;
+ assign T_254 = T_243 + 1'h1;
+ assign T_255 = T_254[1:0];
+ assign T_257 = T_255 < 3'h4;
+ assign T_259 = 1'h0 + T_255;
+ assign T_260 = T_259[1:0];
+ assign T_263 = T_255 - 3'h4;
+ assign T_264 = T_263[2:0];
+ assign GEN_0 = GEN_22 ? T_247_3 : GEN_23 ? T_247_2 : GEN_24 ? T_247_1 : T_247_0;
+ assign GEN_1 = GEN_25 ? T_247_3 : GEN_26 ? T_247_2 : GEN_27 ? T_247_1 : T_247_0;
+ assign T_266 = T_257 ? GEN_0 : GEN_1;
+ assign T_268 = T_255 < 2'h3;
+ assign T_270 = 1'h1 + T_255;
+ assign T_271 = T_270[1:0];
+ assign T_274 = T_255 - 2'h3;
+ assign T_275 = T_274[1:0];
+ assign GEN_2 = GEN_28 ? T_247_3 : GEN_29 ? T_247_2 : GEN_30 ? T_247_1 : T_247_0;
+ assign GEN_3 = GEN_31 ? T_247_3 : GEN_32 ? T_247_2 : GEN_33 ? T_247_1 : T_247_0;
+ assign T_277 = T_268 ? GEN_2 : GEN_3;
+ assign T_279 = T_255 < 2'h2;
+ assign T_281 = 2'h2 + T_255;
+ assign T_282 = T_281[1:0];
+ assign T_285 = T_255 - 2'h2;
+ assign T_286 = T_285[1:0];
+ assign GEN_4 = GEN_34 ? T_247_3 : GEN_35 ? T_247_2 : GEN_36 ? T_247_1 : T_247_0;
+ assign GEN_5 = GEN_37 ? T_247_3 : GEN_38 ? T_247_2 : GEN_39 ? T_247_1 : T_247_0;
+ assign T_288 = T_279 ? GEN_4 : GEN_5;
+ assign T_290 = T_255 < 1'h1;
+ assign T_292 = 2'h3 + T_255;
+ assign T_293 = T_292[1:0];
+ assign T_296 = T_255 - 1'h1;
+ assign T_297 = T_296[1:0];
+ assign GEN_6 = GEN_40 ? T_247_3 : GEN_41 ? T_247_2 : GEN_42 ? T_247_1 : T_247_0;
+ assign GEN_7 = GEN_43 ? T_247_3 : GEN_44 ? T_247_2 : GEN_45 ? T_247_1 : T_247_0;
+ assign T_299 = T_290 ? GEN_6 : GEN_7;
+ assign T_301_0 = T_266;
+ assign T_301_1 = T_277;
+ assign T_301_2 = T_288;
+ assign T_301_3 = T_299;
+ assign T_312_0 = 1'h0;
+ assign T_312_1 = 1'h1;
+ assign T_312_2 = 2'h2;
+ assign T_312_3 = 2'h3;
+ assign T_319 = T_243 + 1'h1;
+ assign T_320 = T_319[1:0];
+ assign T_322 = T_320 < 3'h4;
+ assign T_324 = 1'h0 + T_320;
+ assign T_325 = T_324[1:0];
+ assign T_328 = T_320 - 3'h4;
+ assign T_329 = T_328[2:0];
+ assign GEN_8 = GEN_46 ? T_312_3 : GEN_47 ? T_312_2 : GEN_48 ? T_312_1 : T_312_0;
+ assign GEN_9 = GEN_49 ? T_312_3 : GEN_50 ? T_312_2 : GEN_51 ? T_312_1 : T_312_0;
+ assign T_331 = T_322 ? GEN_8 : GEN_9;
+ assign T_333 = T_320 < 2'h3;
+ assign T_335 = 1'h1 + T_320;
+ assign T_336 = T_335[1:0];
+ assign T_339 = T_320 - 2'h3;
+ assign T_340 = T_339[1:0];
+ assign GEN_10 = GEN_52 ? T_312_3 : GEN_53 ? T_312_2 : GEN_54 ? T_312_1 : T_312_0;
+ assign GEN_11 = GEN_55 ? T_312_3 : GEN_56 ? T_312_2 : GEN_57 ? T_312_1 : T_312_0;
+ assign T_342 = T_333 ? GEN_10 : GEN_11;
+ assign T_344 = T_320 < 2'h2;
+ assign T_346 = 2'h2 + T_320;
+ assign T_347 = T_346[1:0];
+ assign T_350 = T_320 - 2'h2;
+ assign T_351 = T_350[1:0];
+ assign GEN_12 = GEN_58 ? T_312_3 : GEN_59 ? T_312_2 : GEN_60 ? T_312_1 : T_312_0;
+ assign GEN_13 = GEN_61 ? T_312_3 : GEN_62 ? T_312_2 : GEN_63 ? T_312_1 : T_312_0;
+ assign T_353 = T_344 ? GEN_12 : GEN_13;
+ assign T_355 = T_320 < 1'h1;
+ assign T_357 = 2'h3 + T_320;
+ assign T_358 = T_357[1:0];
+ assign T_361 = T_320 - 1'h1;
+ assign T_362 = T_361[1:0];
+ assign GEN_14 = GEN_64 ? T_312_3 : GEN_65 ? T_312_2 : GEN_66 ? T_312_1 : T_312_0;
+ assign GEN_15 = GEN_67 ? T_312_3 : GEN_68 ? T_312_2 : GEN_69 ? T_312_1 : T_312_0;
+ assign T_364 = T_355 ? GEN_14 : GEN_15;
+ assign T_366_0 = T_331;
+ assign T_366_1 = T_342;
+ assign T_366_2 = T_353;
+ assign T_366_3 = T_364;
+ assign T_372 = T_301_2 ? T_366_2 : T_366_3;
+ assign T_373 = T_301_1 ? T_366_1 : T_372;
+ assign T_374 = T_301_0 ? T_366_0 : T_373;
+ assign T_375 = T_245 ? T_243 : T_374;
+ assign T_377 = T_375 == 1'h0;
+ assign T_378 = io_out_ready & T_377;
+ assign T_380 = T_375 == 1'h1;
+ assign T_381 = io_out_ready & T_380;
+ assign T_383 = T_375 == 2'h2;
+ assign T_384 = io_out_ready & T_383;
+ assign T_386 = T_375 == 2'h3;
+ assign T_387 = io_out_ready & T_386;
+ assign GEN_16 = GEN_70 ? io_in_3_valid : GEN_71 ? io_in_2_valid : GEN_72 ? io_in_1_valid : io_in_0_valid;
+ assign GEN_17 = GEN_73 ? io_in_3_bits_resp : GEN_74 ? io_in_2_bits_resp : GEN_75 ? io_in_1_bits_resp : io_in_0_bits_resp;
+ assign GEN_18 = GEN_76 ? io_in_3_bits_data : GEN_77 ? io_in_2_bits_data : GEN_78 ? io_in_1_bits_data : io_in_0_bits_data;
+ assign GEN_19 = GEN_79 ? io_in_3_bits_last : GEN_80 ? io_in_2_bits_last : GEN_81 ? io_in_1_bits_last : io_in_0_bits_last;
+ assign GEN_20 = GEN_82 ? io_in_3_bits_id : GEN_83 ? io_in_2_bits_id : GEN_84 ? io_in_1_bits_id : io_in_0_bits_id;
+ assign GEN_21 = GEN_85 ? io_in_3_bits_user : GEN_86 ? io_in_2_bits_user : GEN_87 ? io_in_1_bits_user : io_in_0_bits_user;
+ assign T_418 = io_out_ready & io_out_valid;
+ assign T_420 = T_245 == 1'h0;
+ assign T_422 = T_420 & 1'h1;
+ assign GEN_22 = 2'h3 == T_260;
+ assign GEN_23 = 2'h2 == T_260;
+ assign GEN_24 = 1'h1 == T_260;
+ assign GEN_25 = 2'h3 == T_264;
+ assign GEN_26 = 2'h2 == T_264;
+ assign GEN_27 = 1'h1 == T_264;
+ assign GEN_28 = 2'h3 == T_271;
+ assign GEN_29 = 2'h2 == T_271;
+ assign GEN_30 = 1'h1 == T_271;
+ assign GEN_31 = 2'h3 == T_275;
+ assign GEN_32 = 2'h2 == T_275;
+ assign GEN_33 = 1'h1 == T_275;
+ assign GEN_34 = 2'h3 == T_282;
+ assign GEN_35 = 2'h2 == T_282;
+ assign GEN_36 = 1'h1 == T_282;
+ assign GEN_37 = 2'h3 == T_286;
+ assign GEN_38 = 2'h2 == T_286;
+ assign GEN_39 = 1'h1 == T_286;
+ assign GEN_40 = 2'h3 == T_293;
+ assign GEN_41 = 2'h2 == T_293;
+ assign GEN_42 = 1'h1 == T_293;
+ assign GEN_43 = 2'h3 == T_297;
+ assign GEN_44 = 2'h2 == T_297;
+ assign GEN_45 = 1'h1 == T_297;
+ assign GEN_46 = 2'h3 == T_325;
+ assign GEN_47 = 2'h2 == T_325;
+ assign GEN_48 = 1'h1 == T_325;
+ assign GEN_49 = 2'h3 == T_329;
+ assign GEN_50 = 2'h2 == T_329;
+ assign GEN_51 = 1'h1 == T_329;
+ assign GEN_52 = 2'h3 == T_336;
+ assign GEN_53 = 2'h2 == T_336;
+ assign GEN_54 = 1'h1 == T_336;
+ assign GEN_55 = 2'h3 == T_340;
+ assign GEN_56 = 2'h2 == T_340;
+ assign GEN_57 = 1'h1 == T_340;
+ assign GEN_58 = 2'h3 == T_347;
+ assign GEN_59 = 2'h2 == T_347;
+ assign GEN_60 = 1'h1 == T_347;
+ assign GEN_61 = 2'h3 == T_351;
+ assign GEN_62 = 2'h2 == T_351;
+ assign GEN_63 = 1'h1 == T_351;
+ assign GEN_64 = 2'h3 == T_358;
+ assign GEN_65 = 2'h2 == T_358;
+ assign GEN_66 = 1'h1 == T_358;
+ assign GEN_67 = 2'h3 == T_362;
+ assign GEN_68 = 2'h2 == T_362;
+ assign GEN_69 = 1'h1 == T_362;
+ assign GEN_70 = 2'h3 == T_375;
+ assign GEN_71 = 2'h2 == T_375;
+ assign GEN_72 = 1'h1 == T_375;
+ assign GEN_73 = 2'h3 == T_375;
+ assign GEN_74 = 2'h2 == T_375;
+ assign GEN_75 = 1'h1 == T_375;
+ assign GEN_76 = 2'h3 == T_375;
+ assign GEN_77 = 2'h2 == T_375;
+ assign GEN_78 = 1'h1 == T_375;
+ assign GEN_79 = 2'h3 == T_375;
+ assign GEN_80 = 2'h2 == T_375;
+ assign GEN_81 = 1'h1 == T_375;
+ assign GEN_82 = 2'h3 == T_375;
+ assign GEN_83 = 2'h2 == T_375;
+ assign GEN_84 = 1'h1 == T_375;
+ assign GEN_85 = 2'h3 == T_375;
+ assign GEN_86 = 2'h2 == T_375;
+ assign GEN_87 = 1'h1 == T_375;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_243 = {1{$random}};
+ T_245 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ T_243 <= 2'h0;
+ end else begin
+ if(T_418) begin
+ if(T_422) begin
+ T_243 <= T_374;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_245 <= 1'h0;
+ end else begin
+ if(T_418) begin
+ if(io_out_bits_last) begin
+ T_245 <= 1'h0;
+ end else begin
+ if(T_422) begin
+ T_245 <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module NastiRouter_58(
+ input clk,
+ input reset,
+ output io_master_aw_ready,
+ input io_master_aw_valid,
+ input [31:0] io_master_aw_bits_addr,
+ input [7:0] io_master_aw_bits_len,
+ input [2:0] io_master_aw_bits_size,
+ input [1:0] io_master_aw_bits_burst,
+ input io_master_aw_bits_lock,
+ input [3:0] io_master_aw_bits_cache,
+ input [2:0] io_master_aw_bits_prot,
+ input [3:0] io_master_aw_bits_qos,
+ input [3:0] io_master_aw_bits_region,
+ input [4:0] io_master_aw_bits_id,
+ input io_master_aw_bits_user,
+ output io_master_w_ready,
+ input io_master_w_valid,
+ input [63:0] io_master_w_bits_data,
+ input io_master_w_bits_last,
+ input [7:0] io_master_w_bits_strb,
+ input io_master_w_bits_user,
+ input io_master_b_ready,
+ output io_master_b_valid,
+ output [1:0] io_master_b_bits_resp,
+ output [4:0] io_master_b_bits_id,
+ output io_master_b_bits_user,
+ output io_master_ar_ready,
+ input io_master_ar_valid,
+ input [31:0] io_master_ar_bits_addr,
+ input [7:0] io_master_ar_bits_len,
+ input [2:0] io_master_ar_bits_size,
+ input [1:0] io_master_ar_bits_burst,
+ input io_master_ar_bits_lock,
+ input [3:0] io_master_ar_bits_cache,
+ input [2:0] io_master_ar_bits_prot,
+ input [3:0] io_master_ar_bits_qos,
+ input [3:0] io_master_ar_bits_region,
+ input [4:0] io_master_ar_bits_id,
+ input io_master_ar_bits_user,
+ input io_master_r_ready,
+ output io_master_r_valid,
+ output [1:0] io_master_r_bits_resp,
+ output [63:0] io_master_r_bits_data,
+ output io_master_r_bits_last,
+ output [4:0] io_master_r_bits_id,
+ output io_master_r_bits_user,
+ input io_slave_0_aw_ready,
+ output io_slave_0_aw_valid,
+ output [31:0] io_slave_0_aw_bits_addr,
+ output [7:0] io_slave_0_aw_bits_len,
+ output [2:0] io_slave_0_aw_bits_size,
+ output [1:0] io_slave_0_aw_bits_burst,
+ output io_slave_0_aw_bits_lock,
+ output [3:0] io_slave_0_aw_bits_cache,
+ output [2:0] io_slave_0_aw_bits_prot,
+ output [3:0] io_slave_0_aw_bits_qos,
+ output [3:0] io_slave_0_aw_bits_region,
+ output [4:0] io_slave_0_aw_bits_id,
+ output io_slave_0_aw_bits_user,
+ input io_slave_0_w_ready,
+ output io_slave_0_w_valid,
+ output [63:0] io_slave_0_w_bits_data,
+ output io_slave_0_w_bits_last,
+ output [7:0] io_slave_0_w_bits_strb,
+ output io_slave_0_w_bits_user,
+ output io_slave_0_b_ready,
+ input io_slave_0_b_valid,
+ input [1:0] io_slave_0_b_bits_resp,
+ input [4:0] io_slave_0_b_bits_id,
+ input io_slave_0_b_bits_user,
+ input io_slave_0_ar_ready,
+ output io_slave_0_ar_valid,
+ output [31:0] io_slave_0_ar_bits_addr,
+ output [7:0] io_slave_0_ar_bits_len,
+ output [2:0] io_slave_0_ar_bits_size,
+ output [1:0] io_slave_0_ar_bits_burst,
+ output io_slave_0_ar_bits_lock,
+ output [3:0] io_slave_0_ar_bits_cache,
+ output [2:0] io_slave_0_ar_bits_prot,
+ output [3:0] io_slave_0_ar_bits_qos,
+ output [3:0] io_slave_0_ar_bits_region,
+ output [4:0] io_slave_0_ar_bits_id,
+ output io_slave_0_ar_bits_user,
+ output io_slave_0_r_ready,
+ input io_slave_0_r_valid,
+ input [1:0] io_slave_0_r_bits_resp,
+ input [63:0] io_slave_0_r_bits_data,
+ input io_slave_0_r_bits_last,
+ input [4:0] io_slave_0_r_bits_id,
+ input io_slave_0_r_bits_user,
+ input io_slave_1_aw_ready,
+ output io_slave_1_aw_valid,
+ output [31:0] io_slave_1_aw_bits_addr,
+ output [7:0] io_slave_1_aw_bits_len,
+ output [2:0] io_slave_1_aw_bits_size,
+ output [1:0] io_slave_1_aw_bits_burst,
+ output io_slave_1_aw_bits_lock,
+ output [3:0] io_slave_1_aw_bits_cache,
+ output [2:0] io_slave_1_aw_bits_prot,
+ output [3:0] io_slave_1_aw_bits_qos,
+ output [3:0] io_slave_1_aw_bits_region,
+ output [4:0] io_slave_1_aw_bits_id,
+ output io_slave_1_aw_bits_user,
+ input io_slave_1_w_ready,
+ output io_slave_1_w_valid,
+ output [63:0] io_slave_1_w_bits_data,
+ output io_slave_1_w_bits_last,
+ output [7:0] io_slave_1_w_bits_strb,
+ output io_slave_1_w_bits_user,
+ output io_slave_1_b_ready,
+ input io_slave_1_b_valid,
+ input [1:0] io_slave_1_b_bits_resp,
+ input [4:0] io_slave_1_b_bits_id,
+ input io_slave_1_b_bits_user,
+ input io_slave_1_ar_ready,
+ output io_slave_1_ar_valid,
+ output [31:0] io_slave_1_ar_bits_addr,
+ output [7:0] io_slave_1_ar_bits_len,
+ output [2:0] io_slave_1_ar_bits_size,
+ output [1:0] io_slave_1_ar_bits_burst,
+ output io_slave_1_ar_bits_lock,
+ output [3:0] io_slave_1_ar_bits_cache,
+ output [2:0] io_slave_1_ar_bits_prot,
+ output [3:0] io_slave_1_ar_bits_qos,
+ output [3:0] io_slave_1_ar_bits_region,
+ output [4:0] io_slave_1_ar_bits_id,
+ output io_slave_1_ar_bits_user,
+ output io_slave_1_r_ready,
+ input io_slave_1_r_valid,
+ input [1:0] io_slave_1_r_bits_resp,
+ input [63:0] io_slave_1_r_bits_data,
+ input io_slave_1_r_bits_last,
+ input [4:0] io_slave_1_r_bits_id,
+ input io_slave_1_r_bits_user,
+ input io_slave_2_aw_ready,
+ output io_slave_2_aw_valid,
+ output [31:0] io_slave_2_aw_bits_addr,
+ output [7:0] io_slave_2_aw_bits_len,
+ output [2:0] io_slave_2_aw_bits_size,
+ output [1:0] io_slave_2_aw_bits_burst,
+ output io_slave_2_aw_bits_lock,
+ output [3:0] io_slave_2_aw_bits_cache,
+ output [2:0] io_slave_2_aw_bits_prot,
+ output [3:0] io_slave_2_aw_bits_qos,
+ output [3:0] io_slave_2_aw_bits_region,
+ output [4:0] io_slave_2_aw_bits_id,
+ output io_slave_2_aw_bits_user,
+ input io_slave_2_w_ready,
+ output io_slave_2_w_valid,
+ output [63:0] io_slave_2_w_bits_data,
+ output io_slave_2_w_bits_last,
+ output [7:0] io_slave_2_w_bits_strb,
+ output io_slave_2_w_bits_user,
+ output io_slave_2_b_ready,
+ input io_slave_2_b_valid,
+ input [1:0] io_slave_2_b_bits_resp,
+ input [4:0] io_slave_2_b_bits_id,
+ input io_slave_2_b_bits_user,
+ input io_slave_2_ar_ready,
+ output io_slave_2_ar_valid,
+ output [31:0] io_slave_2_ar_bits_addr,
+ output [7:0] io_slave_2_ar_bits_len,
+ output [2:0] io_slave_2_ar_bits_size,
+ output [1:0] io_slave_2_ar_bits_burst,
+ output io_slave_2_ar_bits_lock,
+ output [3:0] io_slave_2_ar_bits_cache,
+ output [2:0] io_slave_2_ar_bits_prot,
+ output [3:0] io_slave_2_ar_bits_qos,
+ output [3:0] io_slave_2_ar_bits_region,
+ output [4:0] io_slave_2_ar_bits_id,
+ output io_slave_2_ar_bits_user,
+ output io_slave_2_r_ready,
+ input io_slave_2_r_valid,
+ input [1:0] io_slave_2_r_bits_resp,
+ input [63:0] io_slave_2_r_bits_data,
+ input io_slave_2_r_bits_last,
+ input [4:0] io_slave_2_r_bits_id,
+ input io_slave_2_r_bits_user
+);
+ wire T_1278;
+ wire T_1280;
+ wire T_1281;
+ wire T_1283;
+ wire T_1285;
+ wire T_1286;
+ wire T_1288;
+ wire T_1290;
+ wire T_1291;
+ wire T_1293_0;
+ wire T_1293_1;
+ wire T_1293_2;
+ wire [1:0] T_1298;
+ wire [2:0] ar_route;
+ wire T_1301;
+ wire T_1303;
+ wire T_1304;
+ wire T_1306;
+ wire T_1308;
+ wire T_1309;
+ wire T_1311;
+ wire T_1313;
+ wire T_1314;
+ wire T_1316_0;
+ wire T_1316_1;
+ wire T_1316_2;
+ wire [1:0] T_1321;
+ wire [2:0] aw_route;
+ wire T_1326;
+ wire T_1327;
+ wire T_1328;
+ wire T_1329;
+ wire T_1330;
+ wire T_1331;
+ wire T_1332;
+ wire T_1333;
+ wire T_1334;
+ wire T_1335;
+ reg T_1337;
+ wire T_1338;
+ wire T_1340;
+ wire T_1341;
+ wire T_1343;
+ wire T_1344;
+ wire T_1345;
+ wire T_1346;
+ wire T_1347;
+ wire T_1348;
+ wire T_1349;
+ wire T_1350;
+ wire T_1351;
+ wire T_1352;
+ wire T_1353;
+ wire T_1354;
+ wire T_1355;
+ reg T_1357;
+ wire T_1358;
+ wire T_1360;
+ wire T_1361;
+ wire T_1363;
+ wire T_1364;
+ wire T_1365;
+ wire T_1366;
+ wire T_1367;
+ wire T_1368;
+ wire T_1369;
+ wire ar_ready;
+ wire T_1371;
+ wire T_1372;
+ wire T_1373;
+ wire T_1374;
+ wire aw_ready;
+ reg T_1377;
+ wire T_1378;
+ wire T_1380;
+ wire T_1381;
+ wire T_1383;
+ wire T_1384;
+ wire w_ready;
+ wire T_1387;
+ wire r_invalid;
+ wire T_1391;
+ wire w_invalid;
+ wire err_slave_clk;
+ wire err_slave_reset;
+ wire err_slave_io_aw_ready;
+ wire err_slave_io_aw_valid;
+ wire [31:0] err_slave_io_aw_bits_addr;
+ wire [7:0] err_slave_io_aw_bits_len;
+ wire [2:0] err_slave_io_aw_bits_size;
+ wire [1:0] err_slave_io_aw_bits_burst;
+ wire err_slave_io_aw_bits_lock;
+ wire [3:0] err_slave_io_aw_bits_cache;
+ wire [2:0] err_slave_io_aw_bits_prot;
+ wire [3:0] err_slave_io_aw_bits_qos;
+ wire [3:0] err_slave_io_aw_bits_region;
+ wire [4:0] err_slave_io_aw_bits_id;
+ wire err_slave_io_aw_bits_user;
+ wire err_slave_io_w_ready;
+ wire err_slave_io_w_valid;
+ wire [63:0] err_slave_io_w_bits_data;
+ wire err_slave_io_w_bits_last;
+ wire [7:0] err_slave_io_w_bits_strb;
+ wire err_slave_io_w_bits_user;
+ wire err_slave_io_b_ready;
+ wire err_slave_io_b_valid;
+ wire [1:0] err_slave_io_b_bits_resp;
+ wire [4:0] err_slave_io_b_bits_id;
+ wire err_slave_io_b_bits_user;
+ wire err_slave_io_ar_ready;
+ wire err_slave_io_ar_valid;
+ wire [31:0] err_slave_io_ar_bits_addr;
+ wire [7:0] err_slave_io_ar_bits_len;
+ wire [2:0] err_slave_io_ar_bits_size;
+ wire [1:0] err_slave_io_ar_bits_burst;
+ wire err_slave_io_ar_bits_lock;
+ wire [3:0] err_slave_io_ar_bits_cache;
+ wire [2:0] err_slave_io_ar_bits_prot;
+ wire [3:0] err_slave_io_ar_bits_qos;
+ wire [3:0] err_slave_io_ar_bits_region;
+ wire [4:0] err_slave_io_ar_bits_id;
+ wire err_slave_io_ar_bits_user;
+ wire err_slave_io_r_ready;
+ wire err_slave_io_r_valid;
+ wire [1:0] err_slave_io_r_bits_resp;
+ wire [63:0] err_slave_io_r_bits_data;
+ wire err_slave_io_r_bits_last;
+ wire [4:0] err_slave_io_r_bits_id;
+ wire err_slave_io_r_bits_user;
+ wire T_1395;
+ wire T_1396;
+ wire T_1397;
+ wire T_1398;
+ wire T_1399;
+ wire T_1400;
+ wire T_1401;
+ wire b_arb_clk;
+ wire b_arb_reset;
+ wire b_arb_io_in_0_ready;
+ wire b_arb_io_in_0_valid;
+ wire [1:0] b_arb_io_in_0_bits_resp;
+ wire [4:0] b_arb_io_in_0_bits_id;
+ wire b_arb_io_in_0_bits_user;
+ wire b_arb_io_in_1_ready;
+ wire b_arb_io_in_1_valid;
+ wire [1:0] b_arb_io_in_1_bits_resp;
+ wire [4:0] b_arb_io_in_1_bits_id;
+ wire b_arb_io_in_1_bits_user;
+ wire b_arb_io_in_2_ready;
+ wire b_arb_io_in_2_valid;
+ wire [1:0] b_arb_io_in_2_bits_resp;
+ wire [4:0] b_arb_io_in_2_bits_id;
+ wire b_arb_io_in_2_bits_user;
+ wire b_arb_io_in_3_ready;
+ wire b_arb_io_in_3_valid;
+ wire [1:0] b_arb_io_in_3_bits_resp;
+ wire [4:0] b_arb_io_in_3_bits_id;
+ wire b_arb_io_in_3_bits_user;
+ wire b_arb_io_out_ready;
+ wire b_arb_io_out_valid;
+ wire [1:0] b_arb_io_out_bits_resp;
+ wire [4:0] b_arb_io_out_bits_id;
+ wire b_arb_io_out_bits_user;
+ wire [1:0] b_arb_io_chosen;
+ wire r_arb_clk;
+ wire r_arb_reset;
+ wire r_arb_io_in_0_ready;
+ wire r_arb_io_in_0_valid;
+ wire [1:0] r_arb_io_in_0_bits_resp;
+ wire [63:0] r_arb_io_in_0_bits_data;
+ wire r_arb_io_in_0_bits_last;
+ wire [4:0] r_arb_io_in_0_bits_id;
+ wire r_arb_io_in_0_bits_user;
+ wire r_arb_io_in_1_ready;
+ wire r_arb_io_in_1_valid;
+ wire [1:0] r_arb_io_in_1_bits_resp;
+ wire [63:0] r_arb_io_in_1_bits_data;
+ wire r_arb_io_in_1_bits_last;
+ wire [4:0] r_arb_io_in_1_bits_id;
+ wire r_arb_io_in_1_bits_user;
+ wire r_arb_io_in_2_ready;
+ wire r_arb_io_in_2_valid;
+ wire [1:0] r_arb_io_in_2_bits_resp;
+ wire [63:0] r_arb_io_in_2_bits_data;
+ wire r_arb_io_in_2_bits_last;
+ wire [4:0] r_arb_io_in_2_bits_id;
+ wire r_arb_io_in_2_bits_user;
+ wire r_arb_io_in_3_ready;
+ wire r_arb_io_in_3_valid;
+ wire [1:0] r_arb_io_in_3_bits_resp;
+ wire [63:0] r_arb_io_in_3_bits_data;
+ wire r_arb_io_in_3_bits_last;
+ wire [4:0] r_arb_io_in_3_bits_id;
+ wire r_arb_io_in_3_bits_user;
+ wire r_arb_io_out_ready;
+ wire r_arb_io_out_valid;
+ wire [1:0] r_arb_io_out_bits_resp;
+ wire [63:0] r_arb_io_out_bits_data;
+ wire r_arb_io_out_bits_last;
+ wire [4:0] r_arb_io_out_bits_id;
+ wire r_arb_io_out_bits_user;
+ NastiErrorSlave_40 err_slave (
+ .clk(err_slave_clk),
+ .reset(err_slave_reset),
+ .io_aw_ready(err_slave_io_aw_ready),
+ .io_aw_valid(err_slave_io_aw_valid),
+ .io_aw_bits_addr(err_slave_io_aw_bits_addr),
+ .io_aw_bits_len(err_slave_io_aw_bits_len),
+ .io_aw_bits_size(err_slave_io_aw_bits_size),
+ .io_aw_bits_burst(err_slave_io_aw_bits_burst),
+ .io_aw_bits_lock(err_slave_io_aw_bits_lock),
+ .io_aw_bits_cache(err_slave_io_aw_bits_cache),
+ .io_aw_bits_prot(err_slave_io_aw_bits_prot),
+ .io_aw_bits_qos(err_slave_io_aw_bits_qos),
+ .io_aw_bits_region(err_slave_io_aw_bits_region),
+ .io_aw_bits_id(err_slave_io_aw_bits_id),
+ .io_aw_bits_user(err_slave_io_aw_bits_user),
+ .io_w_ready(err_slave_io_w_ready),
+ .io_w_valid(err_slave_io_w_valid),
+ .io_w_bits_data(err_slave_io_w_bits_data),
+ .io_w_bits_last(err_slave_io_w_bits_last),
+ .io_w_bits_strb(err_slave_io_w_bits_strb),
+ .io_w_bits_user(err_slave_io_w_bits_user),
+ .io_b_ready(err_slave_io_b_ready),
+ .io_b_valid(err_slave_io_b_valid),
+ .io_b_bits_resp(err_slave_io_b_bits_resp),
+ .io_b_bits_id(err_slave_io_b_bits_id),
+ .io_b_bits_user(err_slave_io_b_bits_user),
+ .io_ar_ready(err_slave_io_ar_ready),
+ .io_ar_valid(err_slave_io_ar_valid),
+ .io_ar_bits_addr(err_slave_io_ar_bits_addr),
+ .io_ar_bits_len(err_slave_io_ar_bits_len),
+ .io_ar_bits_size(err_slave_io_ar_bits_size),
+ .io_ar_bits_burst(err_slave_io_ar_bits_burst),
+ .io_ar_bits_lock(err_slave_io_ar_bits_lock),
+ .io_ar_bits_cache(err_slave_io_ar_bits_cache),
+ .io_ar_bits_prot(err_slave_io_ar_bits_prot),
+ .io_ar_bits_qos(err_slave_io_ar_bits_qos),
+ .io_ar_bits_region(err_slave_io_ar_bits_region),
+ .io_ar_bits_id(err_slave_io_ar_bits_id),
+ .io_ar_bits_user(err_slave_io_ar_bits_user),
+ .io_r_ready(err_slave_io_r_ready),
+ .io_r_valid(err_slave_io_r_valid),
+ .io_r_bits_resp(err_slave_io_r_bits_resp),
+ .io_r_bits_data(err_slave_io_r_bits_data),
+ .io_r_bits_last(err_slave_io_r_bits_last),
+ .io_r_bits_id(err_slave_io_r_bits_id),
+ .io_r_bits_user(err_slave_io_r_bits_user)
+ );
+ RRArbiter_62 b_arb (
+ .clk(b_arb_clk),
+ .reset(b_arb_reset),
+ .io_in_0_ready(b_arb_io_in_0_ready),
+ .io_in_0_valid(b_arb_io_in_0_valid),
+ .io_in_0_bits_resp(b_arb_io_in_0_bits_resp),
+ .io_in_0_bits_id(b_arb_io_in_0_bits_id),
+ .io_in_0_bits_user(b_arb_io_in_0_bits_user),
+ .io_in_1_ready(b_arb_io_in_1_ready),
+ .io_in_1_valid(b_arb_io_in_1_valid),
+ .io_in_1_bits_resp(b_arb_io_in_1_bits_resp),
+ .io_in_1_bits_id(b_arb_io_in_1_bits_id),
+ .io_in_1_bits_user(b_arb_io_in_1_bits_user),
+ .io_in_2_ready(b_arb_io_in_2_ready),
+ .io_in_2_valid(b_arb_io_in_2_valid),
+ .io_in_2_bits_resp(b_arb_io_in_2_bits_resp),
+ .io_in_2_bits_id(b_arb_io_in_2_bits_id),
+ .io_in_2_bits_user(b_arb_io_in_2_bits_user),
+ .io_in_3_ready(b_arb_io_in_3_ready),
+ .io_in_3_valid(b_arb_io_in_3_valid),
+ .io_in_3_bits_resp(b_arb_io_in_3_bits_resp),
+ .io_in_3_bits_id(b_arb_io_in_3_bits_id),
+ .io_in_3_bits_user(b_arb_io_in_3_bits_user),
+ .io_out_ready(b_arb_io_out_ready),
+ .io_out_valid(b_arb_io_out_valid),
+ .io_out_bits_resp(b_arb_io_out_bits_resp),
+ .io_out_bits_id(b_arb_io_out_bits_id),
+ .io_out_bits_user(b_arb_io_out_bits_user),
+ .io_chosen(b_arb_io_chosen)
+ );
+ JunctionsPeekingArbiter_63 r_arb (
+ .clk(r_arb_clk),
+ .reset(r_arb_reset),
+ .io_in_0_ready(r_arb_io_in_0_ready),
+ .io_in_0_valid(r_arb_io_in_0_valid),
+ .io_in_0_bits_resp(r_arb_io_in_0_bits_resp),
+ .io_in_0_bits_data(r_arb_io_in_0_bits_data),
+ .io_in_0_bits_last(r_arb_io_in_0_bits_last),
+ .io_in_0_bits_id(r_arb_io_in_0_bits_id),
+ .io_in_0_bits_user(r_arb_io_in_0_bits_user),
+ .io_in_1_ready(r_arb_io_in_1_ready),
+ .io_in_1_valid(r_arb_io_in_1_valid),
+ .io_in_1_bits_resp(r_arb_io_in_1_bits_resp),
+ .io_in_1_bits_data(r_arb_io_in_1_bits_data),
+ .io_in_1_bits_last(r_arb_io_in_1_bits_last),
+ .io_in_1_bits_id(r_arb_io_in_1_bits_id),
+ .io_in_1_bits_user(r_arb_io_in_1_bits_user),
+ .io_in_2_ready(r_arb_io_in_2_ready),
+ .io_in_2_valid(r_arb_io_in_2_valid),
+ .io_in_2_bits_resp(r_arb_io_in_2_bits_resp),
+ .io_in_2_bits_data(r_arb_io_in_2_bits_data),
+ .io_in_2_bits_last(r_arb_io_in_2_bits_last),
+ .io_in_2_bits_id(r_arb_io_in_2_bits_id),
+ .io_in_2_bits_user(r_arb_io_in_2_bits_user),
+ .io_in_3_ready(r_arb_io_in_3_ready),
+ .io_in_3_valid(r_arb_io_in_3_valid),
+ .io_in_3_bits_resp(r_arb_io_in_3_bits_resp),
+ .io_in_3_bits_data(r_arb_io_in_3_bits_data),
+ .io_in_3_bits_last(r_arb_io_in_3_bits_last),
+ .io_in_3_bits_id(r_arb_io_in_3_bits_id),
+ .io_in_3_bits_user(r_arb_io_in_3_bits_user),
+ .io_out_ready(r_arb_io_out_ready),
+ .io_out_valid(r_arb_io_out_valid),
+ .io_out_bits_resp(r_arb_io_out_bits_resp),
+ .io_out_bits_data(r_arb_io_out_bits_data),
+ .io_out_bits_last(r_arb_io_out_bits_last),
+ .io_out_bits_id(r_arb_io_out_bits_id),
+ .io_out_bits_user(r_arb_io_out_bits_user)
+ );
+ assign io_master_aw_ready = T_1400;
+ assign io_master_w_ready = T_1401;
+ assign io_master_b_valid = b_arb_io_out_valid;
+ assign io_master_b_bits_resp = b_arb_io_out_bits_resp;
+ assign io_master_b_bits_id = b_arb_io_out_bits_id;
+ assign io_master_b_bits_user = b_arb_io_out_bits_user;
+ assign io_master_ar_ready = T_1398;
+ assign io_master_r_valid = r_arb_io_out_valid;
+ assign io_master_r_bits_resp = r_arb_io_out_bits_resp;
+ assign io_master_r_bits_data = r_arb_io_out_bits_data;
+ assign io_master_r_bits_last = r_arb_io_out_bits_last;
+ assign io_master_r_bits_id = r_arb_io_out_bits_id;
+ assign io_master_r_bits_user = r_arb_io_out_bits_user;
+ assign io_slave_0_aw_valid = T_1332;
+ assign io_slave_0_aw_bits_addr = io_master_aw_bits_addr;
+ assign io_slave_0_aw_bits_len = io_master_aw_bits_len;
+ assign io_slave_0_aw_bits_size = io_master_aw_bits_size;
+ assign io_slave_0_aw_bits_burst = io_master_aw_bits_burst;
+ assign io_slave_0_aw_bits_lock = io_master_aw_bits_lock;
+ assign io_slave_0_aw_bits_cache = io_master_aw_bits_cache;
+ assign io_slave_0_aw_bits_prot = io_master_aw_bits_prot;
+ assign io_slave_0_aw_bits_qos = io_master_aw_bits_qos;
+ assign io_slave_0_aw_bits_region = io_master_aw_bits_region;
+ assign io_slave_0_aw_bits_id = io_master_aw_bits_id;
+ assign io_slave_0_aw_bits_user = io_master_aw_bits_user;
+ assign io_slave_0_w_valid = T_1343;
+ assign io_slave_0_w_bits_data = io_master_w_bits_data;
+ assign io_slave_0_w_bits_last = io_master_w_bits_last;
+ assign io_slave_0_w_bits_strb = io_master_w_bits_strb;
+ assign io_slave_0_w_bits_user = io_master_w_bits_user;
+ assign io_slave_0_b_ready = b_arb_io_in_0_ready;
+ assign io_slave_0_ar_valid = T_1327;
+ assign io_slave_0_ar_bits_addr = io_master_ar_bits_addr;
+ assign io_slave_0_ar_bits_len = io_master_ar_bits_len;
+ assign io_slave_0_ar_bits_size = io_master_ar_bits_size;
+ assign io_slave_0_ar_bits_burst = io_master_ar_bits_burst;
+ assign io_slave_0_ar_bits_lock = io_master_ar_bits_lock;
+ assign io_slave_0_ar_bits_cache = io_master_ar_bits_cache;
+ assign io_slave_0_ar_bits_prot = io_master_ar_bits_prot;
+ assign io_slave_0_ar_bits_qos = io_master_ar_bits_qos;
+ assign io_slave_0_ar_bits_region = io_master_ar_bits_region;
+ assign io_slave_0_ar_bits_id = io_master_ar_bits_id;
+ assign io_slave_0_ar_bits_user = io_master_ar_bits_user;
+ assign io_slave_0_r_ready = r_arb_io_in_0_ready;
+ assign io_slave_1_aw_valid = T_1352;
+ assign io_slave_1_aw_bits_addr = io_master_aw_bits_addr;
+ assign io_slave_1_aw_bits_len = io_master_aw_bits_len;
+ assign io_slave_1_aw_bits_size = io_master_aw_bits_size;
+ assign io_slave_1_aw_bits_burst = io_master_aw_bits_burst;
+ assign io_slave_1_aw_bits_lock = io_master_aw_bits_lock;
+ assign io_slave_1_aw_bits_cache = io_master_aw_bits_cache;
+ assign io_slave_1_aw_bits_prot = io_master_aw_bits_prot;
+ assign io_slave_1_aw_bits_qos = io_master_aw_bits_qos;
+ assign io_slave_1_aw_bits_region = io_master_aw_bits_region;
+ assign io_slave_1_aw_bits_id = io_master_aw_bits_id;
+ assign io_slave_1_aw_bits_user = io_master_aw_bits_user;
+ assign io_slave_1_w_valid = T_1363;
+ assign io_slave_1_w_bits_data = io_master_w_bits_data;
+ assign io_slave_1_w_bits_last = io_master_w_bits_last;
+ assign io_slave_1_w_bits_strb = io_master_w_bits_strb;
+ assign io_slave_1_w_bits_user = io_master_w_bits_user;
+ assign io_slave_1_b_ready = b_arb_io_in_1_ready;
+ assign io_slave_1_ar_valid = T_1347;
+ assign io_slave_1_ar_bits_addr = io_master_ar_bits_addr;
+ assign io_slave_1_ar_bits_len = io_master_ar_bits_len;
+ assign io_slave_1_ar_bits_size = io_master_ar_bits_size;
+ assign io_slave_1_ar_bits_burst = io_master_ar_bits_burst;
+ assign io_slave_1_ar_bits_lock = io_master_ar_bits_lock;
+ assign io_slave_1_ar_bits_cache = io_master_ar_bits_cache;
+ assign io_slave_1_ar_bits_prot = io_master_ar_bits_prot;
+ assign io_slave_1_ar_bits_qos = io_master_ar_bits_qos;
+ assign io_slave_1_ar_bits_region = io_master_ar_bits_region;
+ assign io_slave_1_ar_bits_id = io_master_ar_bits_id;
+ assign io_slave_1_ar_bits_user = io_master_ar_bits_user;
+ assign io_slave_1_r_ready = r_arb_io_in_1_ready;
+ assign io_slave_2_aw_valid = T_1372;
+ assign io_slave_2_aw_bits_addr = io_master_aw_bits_addr;
+ assign io_slave_2_aw_bits_len = io_master_aw_bits_len;
+ assign io_slave_2_aw_bits_size = io_master_aw_bits_size;
+ assign io_slave_2_aw_bits_burst = io_master_aw_bits_burst;
+ assign io_slave_2_aw_bits_lock = io_master_aw_bits_lock;
+ assign io_slave_2_aw_bits_cache = io_master_aw_bits_cache;
+ assign io_slave_2_aw_bits_prot = io_master_aw_bits_prot;
+ assign io_slave_2_aw_bits_qos = io_master_aw_bits_qos;
+ assign io_slave_2_aw_bits_region = io_master_aw_bits_region;
+ assign io_slave_2_aw_bits_id = io_master_aw_bits_id;
+ assign io_slave_2_aw_bits_user = io_master_aw_bits_user;
+ assign io_slave_2_w_valid = T_1383;
+ assign io_slave_2_w_bits_data = io_master_w_bits_data;
+ assign io_slave_2_w_bits_last = io_master_w_bits_last;
+ assign io_slave_2_w_bits_strb = io_master_w_bits_strb;
+ assign io_slave_2_w_bits_user = io_master_w_bits_user;
+ assign io_slave_2_b_ready = b_arb_io_in_2_ready;
+ assign io_slave_2_ar_valid = T_1367;
+ assign io_slave_2_ar_bits_addr = io_master_ar_bits_addr;
+ assign io_slave_2_ar_bits_len = io_master_ar_bits_len;
+ assign io_slave_2_ar_bits_size = io_master_ar_bits_size;
+ assign io_slave_2_ar_bits_burst = io_master_ar_bits_burst;
+ assign io_slave_2_ar_bits_lock = io_master_ar_bits_lock;
+ assign io_slave_2_ar_bits_cache = io_master_ar_bits_cache;
+ assign io_slave_2_ar_bits_prot = io_master_ar_bits_prot;
+ assign io_slave_2_ar_bits_qos = io_master_ar_bits_qos;
+ assign io_slave_2_ar_bits_region = io_master_ar_bits_region;
+ assign io_slave_2_ar_bits_id = io_master_ar_bits_id;
+ assign io_slave_2_ar_bits_user = io_master_ar_bits_user;
+ assign io_slave_2_r_ready = r_arb_io_in_2_ready;
+ assign T_1278 = io_master_ar_bits_addr >= 31'h40000000;
+ assign T_1280 = io_master_ar_bits_addr < 31'h40008000;
+ assign T_1281 = T_1278 & T_1280;
+ assign T_1283 = io_master_ar_bits_addr >= 31'h40008000;
+ assign T_1285 = io_master_ar_bits_addr < 31'h40010000;
+ assign T_1286 = T_1283 & T_1285;
+ assign T_1288 = io_master_ar_bits_addr >= 31'h40010000;
+ assign T_1290 = io_master_ar_bits_addr < 31'h40010200;
+ assign T_1291 = T_1288 & T_1290;
+ assign T_1293_0 = T_1281;
+ assign T_1293_1 = T_1286;
+ assign T_1293_2 = T_1291;
+ assign T_1298 = {T_1293_1,T_1293_0};
+ assign ar_route = {T_1293_2,T_1298};
+ assign T_1301 = io_master_aw_bits_addr >= 31'h40000000;
+ assign T_1303 = io_master_aw_bits_addr < 31'h40008000;
+ assign T_1304 = T_1301 & T_1303;
+ assign T_1306 = io_master_aw_bits_addr >= 31'h40008000;
+ assign T_1308 = io_master_aw_bits_addr < 31'h40010000;
+ assign T_1309 = T_1306 & T_1308;
+ assign T_1311 = io_master_aw_bits_addr >= 31'h40010000;
+ assign T_1313 = io_master_aw_bits_addr < 31'h40010200;
+ assign T_1314 = T_1311 & T_1313;
+ assign T_1316_0 = T_1304;
+ assign T_1316_1 = T_1309;
+ assign T_1316_2 = T_1314;
+ assign T_1321 = {T_1316_1,T_1316_0};
+ assign aw_route = {T_1316_2,T_1321};
+ assign T_1326 = ar_route[0];
+ assign T_1327 = io_master_ar_valid & T_1326;
+ assign T_1328 = ar_route[0];
+ assign T_1329 = io_slave_0_ar_ready & T_1328;
+ assign T_1330 = 1'h0 | T_1329;
+ assign T_1331 = aw_route[0];
+ assign T_1332 = io_master_aw_valid & T_1331;
+ assign T_1333 = aw_route[0];
+ assign T_1334 = io_slave_0_aw_ready & T_1333;
+ assign T_1335 = 1'h0 | T_1334;
+ assign T_1338 = io_slave_0_aw_ready & io_slave_0_aw_valid;
+ assign T_1340 = io_slave_0_w_ready & io_slave_0_w_valid;
+ assign T_1341 = T_1340 & io_slave_0_w_bits_last;
+ assign T_1343 = io_master_w_valid & T_1337;
+ assign T_1344 = io_slave_0_w_ready & T_1337;
+ assign T_1345 = 1'h0 | T_1344;
+ assign T_1346 = ar_route[1];
+ assign T_1347 = io_master_ar_valid & T_1346;
+ assign T_1348 = ar_route[1];
+ assign T_1349 = io_slave_1_ar_ready & T_1348;
+ assign T_1350 = T_1330 | T_1349;
+ assign T_1351 = aw_route[1];
+ assign T_1352 = io_master_aw_valid & T_1351;
+ assign T_1353 = aw_route[1];
+ assign T_1354 = io_slave_1_aw_ready & T_1353;
+ assign T_1355 = T_1335 | T_1354;
+ assign T_1358 = io_slave_1_aw_ready & io_slave_1_aw_valid;
+ assign T_1360 = io_slave_1_w_ready & io_slave_1_w_valid;
+ assign T_1361 = T_1360 & io_slave_1_w_bits_last;
+ assign T_1363 = io_master_w_valid & T_1357;
+ assign T_1364 = io_slave_1_w_ready & T_1357;
+ assign T_1365 = T_1345 | T_1364;
+ assign T_1366 = ar_route[2];
+ assign T_1367 = io_master_ar_valid & T_1366;
+ assign T_1368 = ar_route[2];
+ assign T_1369 = io_slave_2_ar_ready & T_1368;
+ assign ar_ready = T_1350 | T_1369;
+ assign T_1371 = aw_route[2];
+ assign T_1372 = io_master_aw_valid & T_1371;
+ assign T_1373 = aw_route[2];
+ assign T_1374 = io_slave_2_aw_ready & T_1373;
+ assign aw_ready = T_1355 | T_1374;
+ assign T_1378 = io_slave_2_aw_ready & io_slave_2_aw_valid;
+ assign T_1380 = io_slave_2_w_ready & io_slave_2_w_valid;
+ assign T_1381 = T_1380 & io_slave_2_w_bits_last;
+ assign T_1383 = io_master_w_valid & T_1377;
+ assign T_1384 = io_slave_2_w_ready & T_1377;
+ assign w_ready = T_1365 | T_1384;
+ assign T_1387 = ar_route != 1'h0;
+ assign r_invalid = T_1387 == 1'h0;
+ assign T_1391 = aw_route != 1'h0;
+ assign w_invalid = T_1391 == 1'h0;
+ assign err_slave_clk = clk;
+ assign err_slave_reset = reset;
+ assign err_slave_io_aw_valid = T_1396;
+ assign err_slave_io_aw_bits_addr = io_master_aw_bits_addr;
+ assign err_slave_io_aw_bits_len = io_master_aw_bits_len;
+ assign err_slave_io_aw_bits_size = io_master_aw_bits_size;
+ assign err_slave_io_aw_bits_burst = io_master_aw_bits_burst;
+ assign err_slave_io_aw_bits_lock = io_master_aw_bits_lock;
+ assign err_slave_io_aw_bits_cache = io_master_aw_bits_cache;
+ assign err_slave_io_aw_bits_prot = io_master_aw_bits_prot;
+ assign err_slave_io_aw_bits_qos = io_master_aw_bits_qos;
+ assign err_slave_io_aw_bits_region = io_master_aw_bits_region;
+ assign err_slave_io_aw_bits_id = io_master_aw_bits_id;
+ assign err_slave_io_aw_bits_user = io_master_aw_bits_user;
+ assign err_slave_io_w_valid = io_master_w_valid;
+ assign err_slave_io_w_bits_data = io_master_w_bits_data;
+ assign err_slave_io_w_bits_last = io_master_w_bits_last;
+ assign err_slave_io_w_bits_strb = io_master_w_bits_strb;
+ assign err_slave_io_w_bits_user = io_master_w_bits_user;
+ assign err_slave_io_b_ready = b_arb_io_in_3_ready;
+ assign err_slave_io_ar_valid = T_1395;
+ assign err_slave_io_ar_bits_addr = io_master_ar_bits_addr;
+ assign err_slave_io_ar_bits_len = io_master_ar_bits_len;
+ assign err_slave_io_ar_bits_size = io_master_ar_bits_size;
+ assign err_slave_io_ar_bits_burst = io_master_ar_bits_burst;
+ assign err_slave_io_ar_bits_lock = io_master_ar_bits_lock;
+ assign err_slave_io_ar_bits_cache = io_master_ar_bits_cache;
+ assign err_slave_io_ar_bits_prot = io_master_ar_bits_prot;
+ assign err_slave_io_ar_bits_qos = io_master_ar_bits_qos;
+ assign err_slave_io_ar_bits_region = io_master_ar_bits_region;
+ assign err_slave_io_ar_bits_id = io_master_ar_bits_id;
+ assign err_slave_io_ar_bits_user = io_master_ar_bits_user;
+ assign err_slave_io_r_ready = r_arb_io_in_3_ready;
+ assign T_1395 = r_invalid & io_master_ar_valid;
+ assign T_1396 = w_invalid & io_master_aw_valid;
+ assign T_1397 = r_invalid & err_slave_io_ar_ready;
+ assign T_1398 = ar_ready | T_1397;
+ assign T_1399 = w_invalid & err_slave_io_aw_ready;
+ assign T_1400 = aw_ready | T_1399;
+ assign T_1401 = w_ready | err_slave_io_w_ready;
+ assign b_arb_clk = clk;
+ assign b_arb_reset = reset;
+ assign b_arb_io_in_0_valid = io_slave_0_b_valid;
+ assign b_arb_io_in_0_bits_resp = io_slave_0_b_bits_resp;
+ assign b_arb_io_in_0_bits_id = io_slave_0_b_bits_id;
+ assign b_arb_io_in_0_bits_user = io_slave_0_b_bits_user;
+ assign b_arb_io_in_1_valid = io_slave_1_b_valid;
+ assign b_arb_io_in_1_bits_resp = io_slave_1_b_bits_resp;
+ assign b_arb_io_in_1_bits_id = io_slave_1_b_bits_id;
+ assign b_arb_io_in_1_bits_user = io_slave_1_b_bits_user;
+ assign b_arb_io_in_2_valid = io_slave_2_b_valid;
+ assign b_arb_io_in_2_bits_resp = io_slave_2_b_bits_resp;
+ assign b_arb_io_in_2_bits_id = io_slave_2_b_bits_id;
+ assign b_arb_io_in_2_bits_user = io_slave_2_b_bits_user;
+ assign b_arb_io_in_3_valid = err_slave_io_b_valid;
+ assign b_arb_io_in_3_bits_resp = err_slave_io_b_bits_resp;
+ assign b_arb_io_in_3_bits_id = err_slave_io_b_bits_id;
+ assign b_arb_io_in_3_bits_user = err_slave_io_b_bits_user;
+ assign b_arb_io_out_ready = io_master_b_ready;
+ assign r_arb_clk = clk;
+ assign r_arb_reset = reset;
+ assign r_arb_io_in_0_valid = io_slave_0_r_valid;
+ assign r_arb_io_in_0_bits_resp = io_slave_0_r_bits_resp;
+ assign r_arb_io_in_0_bits_data = io_slave_0_r_bits_data;
+ assign r_arb_io_in_0_bits_last = io_slave_0_r_bits_last;
+ assign r_arb_io_in_0_bits_id = io_slave_0_r_bits_id;
+ assign r_arb_io_in_0_bits_user = io_slave_0_r_bits_user;
+ assign r_arb_io_in_1_valid = io_slave_1_r_valid;
+ assign r_arb_io_in_1_bits_resp = io_slave_1_r_bits_resp;
+ assign r_arb_io_in_1_bits_data = io_slave_1_r_bits_data;
+ assign r_arb_io_in_1_bits_last = io_slave_1_r_bits_last;
+ assign r_arb_io_in_1_bits_id = io_slave_1_r_bits_id;
+ assign r_arb_io_in_1_bits_user = io_slave_1_r_bits_user;
+ assign r_arb_io_in_2_valid = io_slave_2_r_valid;
+ assign r_arb_io_in_2_bits_resp = io_slave_2_r_bits_resp;
+ assign r_arb_io_in_2_bits_data = io_slave_2_r_bits_data;
+ assign r_arb_io_in_2_bits_last = io_slave_2_r_bits_last;
+ assign r_arb_io_in_2_bits_id = io_slave_2_r_bits_id;
+ assign r_arb_io_in_2_bits_user = io_slave_2_r_bits_user;
+ assign r_arb_io_in_3_valid = err_slave_io_r_valid;
+ assign r_arb_io_in_3_bits_resp = err_slave_io_r_bits_resp;
+ assign r_arb_io_in_3_bits_data = err_slave_io_r_bits_data;
+ assign r_arb_io_in_3_bits_last = err_slave_io_r_bits_last;
+ assign r_arb_io_in_3_bits_id = err_slave_io_r_bits_id;
+ assign r_arb_io_in_3_bits_user = err_slave_io_r_bits_user;
+ assign r_arb_io_out_ready = io_master_r_ready;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_1337 = {1{$random}};
+ T_1357 = {1{$random}};
+ T_1377 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ T_1337 <= 1'h0;
+ end else begin
+ if(T_1341) begin
+ T_1337 <= 1'h0;
+ end else begin
+ if(T_1338) begin
+ T_1337 <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ T_1357 <= 1'h0;
+ end else begin
+ if(T_1361) begin
+ T_1357 <= 1'h0;
+ end else begin
+ if(T_1358) begin
+ T_1357 <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ T_1377 <= 1'h0;
+ end else begin
+ if(T_1381) begin
+ T_1377 <= 1'h0;
+ end else begin
+ if(T_1378) begin
+ T_1377 <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+endmodule
+module NastiCrossbar_57(
+ input clk,
+ input reset,
+ output io_masters_0_aw_ready,
+ input io_masters_0_aw_valid,
+ input [31:0] io_masters_0_aw_bits_addr,
+ input [7:0] io_masters_0_aw_bits_len,
+ input [2:0] io_masters_0_aw_bits_size,
+ input [1:0] io_masters_0_aw_bits_burst,
+ input io_masters_0_aw_bits_lock,
+ input [3:0] io_masters_0_aw_bits_cache,
+ input [2:0] io_masters_0_aw_bits_prot,
+ input [3:0] io_masters_0_aw_bits_qos,
+ input [3:0] io_masters_0_aw_bits_region,
+ input [4:0] io_masters_0_aw_bits_id,
+ input io_masters_0_aw_bits_user,
+ output io_masters_0_w_ready,
+ input io_masters_0_w_valid,
+ input [63:0] io_masters_0_w_bits_data,
+ input io_masters_0_w_bits_last,
+ input [7:0] io_masters_0_w_bits_strb,
+ input io_masters_0_w_bits_user,
+ input io_masters_0_b_ready,
+ output io_masters_0_b_valid,
+ output [1:0] io_masters_0_b_bits_resp,
+ output [4:0] io_masters_0_b_bits_id,
+ output io_masters_0_b_bits_user,
+ output io_masters_0_ar_ready,
+ input io_masters_0_ar_valid,
+ input [31:0] io_masters_0_ar_bits_addr,
+ input [7:0] io_masters_0_ar_bits_len,
+ input [2:0] io_masters_0_ar_bits_size,
+ input [1:0] io_masters_0_ar_bits_burst,
+ input io_masters_0_ar_bits_lock,
+ input [3:0] io_masters_0_ar_bits_cache,
+ input [2:0] io_masters_0_ar_bits_prot,
+ input [3:0] io_masters_0_ar_bits_qos,
+ input [3:0] io_masters_0_ar_bits_region,
+ input [4:0] io_masters_0_ar_bits_id,
+ input io_masters_0_ar_bits_user,
+ input io_masters_0_r_ready,
+ output io_masters_0_r_valid,
+ output [1:0] io_masters_0_r_bits_resp,
+ output [63:0] io_masters_0_r_bits_data,
+ output io_masters_0_r_bits_last,
+ output [4:0] io_masters_0_r_bits_id,
+ output io_masters_0_r_bits_user,
+ input io_slaves_0_aw_ready,
+ output io_slaves_0_aw_valid,
+ output [31:0] io_slaves_0_aw_bits_addr,
+ output [7:0] io_slaves_0_aw_bits_len,
+ output [2:0] io_slaves_0_aw_bits_size,
+ output [1:0] io_slaves_0_aw_bits_burst,
+ output io_slaves_0_aw_bits_lock,
+ output [3:0] io_slaves_0_aw_bits_cache,
+ output [2:0] io_slaves_0_aw_bits_prot,
+ output [3:0] io_slaves_0_aw_bits_qos,
+ output [3:0] io_slaves_0_aw_bits_region,
+ output [4:0] io_slaves_0_aw_bits_id,
+ output io_slaves_0_aw_bits_user,
+ input io_slaves_0_w_ready,
+ output io_slaves_0_w_valid,
+ output [63:0] io_slaves_0_w_bits_data,
+ output io_slaves_0_w_bits_last,
+ output [7:0] io_slaves_0_w_bits_strb,
+ output io_slaves_0_w_bits_user,
+ output io_slaves_0_b_ready,
+ input io_slaves_0_b_valid,
+ input [1:0] io_slaves_0_b_bits_resp,
+ input [4:0] io_slaves_0_b_bits_id,
+ input io_slaves_0_b_bits_user,
+ input io_slaves_0_ar_ready,
+ output io_slaves_0_ar_valid,
+ output [31:0] io_slaves_0_ar_bits_addr,
+ output [7:0] io_slaves_0_ar_bits_len,
+ output [2:0] io_slaves_0_ar_bits_size,
+ output [1:0] io_slaves_0_ar_bits_burst,
+ output io_slaves_0_ar_bits_lock,
+ output [3:0] io_slaves_0_ar_bits_cache,
+ output [2:0] io_slaves_0_ar_bits_prot,
+ output [3:0] io_slaves_0_ar_bits_qos,
+ output [3:0] io_slaves_0_ar_bits_region,
+ output [4:0] io_slaves_0_ar_bits_id,
+ output io_slaves_0_ar_bits_user,
+ output io_slaves_0_r_ready,
+ input io_slaves_0_r_valid,
+ input [1:0] io_slaves_0_r_bits_resp,
+ input [63:0] io_slaves_0_r_bits_data,
+ input io_slaves_0_r_bits_last,
+ input [4:0] io_slaves_0_r_bits_id,
+ input io_slaves_0_r_bits_user,
+ input io_slaves_1_aw_ready,
+ output io_slaves_1_aw_valid,
+ output [31:0] io_slaves_1_aw_bits_addr,
+ output [7:0] io_slaves_1_aw_bits_len,
+ output [2:0] io_slaves_1_aw_bits_size,
+ output [1:0] io_slaves_1_aw_bits_burst,
+ output io_slaves_1_aw_bits_lock,
+ output [3:0] io_slaves_1_aw_bits_cache,
+ output [2:0] io_slaves_1_aw_bits_prot,
+ output [3:0] io_slaves_1_aw_bits_qos,
+ output [3:0] io_slaves_1_aw_bits_region,
+ output [4:0] io_slaves_1_aw_bits_id,
+ output io_slaves_1_aw_bits_user,
+ input io_slaves_1_w_ready,
+ output io_slaves_1_w_valid,
+ output [63:0] io_slaves_1_w_bits_data,
+ output io_slaves_1_w_bits_last,
+ output [7:0] io_slaves_1_w_bits_strb,
+ output io_slaves_1_w_bits_user,
+ output io_slaves_1_b_ready,
+ input io_slaves_1_b_valid,
+ input [1:0] io_slaves_1_b_bits_resp,
+ input [4:0] io_slaves_1_b_bits_id,
+ input io_slaves_1_b_bits_user,
+ input io_slaves_1_ar_ready,
+ output io_slaves_1_ar_valid,
+ output [31:0] io_slaves_1_ar_bits_addr,
+ output [7:0] io_slaves_1_ar_bits_len,
+ output [2:0] io_slaves_1_ar_bits_size,
+ output [1:0] io_slaves_1_ar_bits_burst,
+ output io_slaves_1_ar_bits_lock,
+ output [3:0] io_slaves_1_ar_bits_cache,
+ output [2:0] io_slaves_1_ar_bits_prot,
+ output [3:0] io_slaves_1_ar_bits_qos,
+ output [3:0] io_slaves_1_ar_bits_region,
+ output [4:0] io_slaves_1_ar_bits_id,
+ output io_slaves_1_ar_bits_user,
+ output io_slaves_1_r_ready,
+ input io_slaves_1_r_valid,
+ input [1:0] io_slaves_1_r_bits_resp,
+ input [63:0] io_slaves_1_r_bits_data,
+ input io_slaves_1_r_bits_last,
+ input [4:0] io_slaves_1_r_bits_id,
+ input io_slaves_1_r_bits_user,
+ input io_slaves_2_aw_ready,
+ output io_slaves_2_aw_valid,
+ output [31:0] io_slaves_2_aw_bits_addr,
+ output [7:0] io_slaves_2_aw_bits_len,
+ output [2:0] io_slaves_2_aw_bits_size,
+ output [1:0] io_slaves_2_aw_bits_burst,
+ output io_slaves_2_aw_bits_lock,
+ output [3:0] io_slaves_2_aw_bits_cache,
+ output [2:0] io_slaves_2_aw_bits_prot,
+ output [3:0] io_slaves_2_aw_bits_qos,
+ output [3:0] io_slaves_2_aw_bits_region,
+ output [4:0] io_slaves_2_aw_bits_id,
+ output io_slaves_2_aw_bits_user,
+ input io_slaves_2_w_ready,
+ output io_slaves_2_w_valid,
+ output [63:0] io_slaves_2_w_bits_data,
+ output io_slaves_2_w_bits_last,
+ output [7:0] io_slaves_2_w_bits_strb,
+ output io_slaves_2_w_bits_user,
+ output io_slaves_2_b_ready,
+ input io_slaves_2_b_valid,
+ input [1:0] io_slaves_2_b_bits_resp,
+ input [4:0] io_slaves_2_b_bits_id,
+ input io_slaves_2_b_bits_user,
+ input io_slaves_2_ar_ready,
+ output io_slaves_2_ar_valid,
+ output [31:0] io_slaves_2_ar_bits_addr,
+ output [7:0] io_slaves_2_ar_bits_len,
+ output [2:0] io_slaves_2_ar_bits_size,
+ output [1:0] io_slaves_2_ar_bits_burst,
+ output io_slaves_2_ar_bits_lock,
+ output [3:0] io_slaves_2_ar_bits_cache,
+ output [2:0] io_slaves_2_ar_bits_prot,
+ output [3:0] io_slaves_2_ar_bits_qos,
+ output [3:0] io_slaves_2_ar_bits_region,
+ output [4:0] io_slaves_2_ar_bits_id,
+ output io_slaves_2_ar_bits_user,
+ output io_slaves_2_r_ready,
+ input io_slaves_2_r_valid,
+ input [1:0] io_slaves_2_r_bits_resp,
+ input [63:0] io_slaves_2_r_bits_data,
+ input io_slaves_2_r_bits_last,
+ input [4:0] io_slaves_2_r_bits_id,
+ input io_slaves_2_r_bits_user
+);
+ wire T_2233_clk;
+ wire T_2233_reset;
+ wire T_2233_io_master_aw_ready;
+ wire T_2233_io_master_aw_valid;
+ wire [31:0] T_2233_io_master_aw_bits_addr;
+ wire [7:0] T_2233_io_master_aw_bits_len;
+ wire [2:0] T_2233_io_master_aw_bits_size;
+ wire [1:0] T_2233_io_master_aw_bits_burst;
+ wire T_2233_io_master_aw_bits_lock;
+ wire [3:0] T_2233_io_master_aw_bits_cache;
+ wire [2:0] T_2233_io_master_aw_bits_prot;
+ wire [3:0] T_2233_io_master_aw_bits_qos;
+ wire [3:0] T_2233_io_master_aw_bits_region;
+ wire [4:0] T_2233_io_master_aw_bits_id;
+ wire T_2233_io_master_aw_bits_user;
+ wire T_2233_io_master_w_ready;
+ wire T_2233_io_master_w_valid;
+ wire [63:0] T_2233_io_master_w_bits_data;
+ wire T_2233_io_master_w_bits_last;
+ wire [7:0] T_2233_io_master_w_bits_strb;
+ wire T_2233_io_master_w_bits_user;
+ wire T_2233_io_master_b_ready;
+ wire T_2233_io_master_b_valid;
+ wire [1:0] T_2233_io_master_b_bits_resp;
+ wire [4:0] T_2233_io_master_b_bits_id;
+ wire T_2233_io_master_b_bits_user;
+ wire T_2233_io_master_ar_ready;
+ wire T_2233_io_master_ar_valid;
+ wire [31:0] T_2233_io_master_ar_bits_addr;
+ wire [7:0] T_2233_io_master_ar_bits_len;
+ wire [2:0] T_2233_io_master_ar_bits_size;
+ wire [1:0] T_2233_io_master_ar_bits_burst;
+ wire T_2233_io_master_ar_bits_lock;
+ wire [3:0] T_2233_io_master_ar_bits_cache;
+ wire [2:0] T_2233_io_master_ar_bits_prot;
+ wire [3:0] T_2233_io_master_ar_bits_qos;
+ wire [3:0] T_2233_io_master_ar_bits_region;
+ wire [4:0] T_2233_io_master_ar_bits_id;
+ wire T_2233_io_master_ar_bits_user;
+ wire T_2233_io_master_r_ready;
+ wire T_2233_io_master_r_valid;
+ wire [1:0] T_2233_io_master_r_bits_resp;
+ wire [63:0] T_2233_io_master_r_bits_data;
+ wire T_2233_io_master_r_bits_last;
+ wire [4:0] T_2233_io_master_r_bits_id;
+ wire T_2233_io_master_r_bits_user;
+ wire T_2233_io_slave_0_aw_ready;
+ wire T_2233_io_slave_0_aw_valid;
+ wire [31:0] T_2233_io_slave_0_aw_bits_addr;
+ wire [7:0] T_2233_io_slave_0_aw_bits_len;
+ wire [2:0] T_2233_io_slave_0_aw_bits_size;
+ wire [1:0] T_2233_io_slave_0_aw_bits_burst;
+ wire T_2233_io_slave_0_aw_bits_lock;
+ wire [3:0] T_2233_io_slave_0_aw_bits_cache;
+ wire [2:0] T_2233_io_slave_0_aw_bits_prot;
+ wire [3:0] T_2233_io_slave_0_aw_bits_qos;
+ wire [3:0] T_2233_io_slave_0_aw_bits_region;
+ wire [4:0] T_2233_io_slave_0_aw_bits_id;
+ wire T_2233_io_slave_0_aw_bits_user;
+ wire T_2233_io_slave_0_w_ready;
+ wire T_2233_io_slave_0_w_valid;
+ wire [63:0] T_2233_io_slave_0_w_bits_data;
+ wire T_2233_io_slave_0_w_bits_last;
+ wire [7:0] T_2233_io_slave_0_w_bits_strb;
+ wire T_2233_io_slave_0_w_bits_user;
+ wire T_2233_io_slave_0_b_ready;
+ wire T_2233_io_slave_0_b_valid;
+ wire [1:0] T_2233_io_slave_0_b_bits_resp;
+ wire [4:0] T_2233_io_slave_0_b_bits_id;
+ wire T_2233_io_slave_0_b_bits_user;
+ wire T_2233_io_slave_0_ar_ready;
+ wire T_2233_io_slave_0_ar_valid;
+ wire [31:0] T_2233_io_slave_0_ar_bits_addr;
+ wire [7:0] T_2233_io_slave_0_ar_bits_len;
+ wire [2:0] T_2233_io_slave_0_ar_bits_size;
+ wire [1:0] T_2233_io_slave_0_ar_bits_burst;
+ wire T_2233_io_slave_0_ar_bits_lock;
+ wire [3:0] T_2233_io_slave_0_ar_bits_cache;
+ wire [2:0] T_2233_io_slave_0_ar_bits_prot;
+ wire [3:0] T_2233_io_slave_0_ar_bits_qos;
+ wire [3:0] T_2233_io_slave_0_ar_bits_region;
+ wire [4:0] T_2233_io_slave_0_ar_bits_id;
+ wire T_2233_io_slave_0_ar_bits_user;
+ wire T_2233_io_slave_0_r_ready;
+ wire T_2233_io_slave_0_r_valid;
+ wire [1:0] T_2233_io_slave_0_r_bits_resp;
+ wire [63:0] T_2233_io_slave_0_r_bits_data;
+ wire T_2233_io_slave_0_r_bits_last;
+ wire [4:0] T_2233_io_slave_0_r_bits_id;
+ wire T_2233_io_slave_0_r_bits_user;
+ wire T_2233_io_slave_1_aw_ready;
+ wire T_2233_io_slave_1_aw_valid;
+ wire [31:0] T_2233_io_slave_1_aw_bits_addr;
+ wire [7:0] T_2233_io_slave_1_aw_bits_len;
+ wire [2:0] T_2233_io_slave_1_aw_bits_size;
+ wire [1:0] T_2233_io_slave_1_aw_bits_burst;
+ wire T_2233_io_slave_1_aw_bits_lock;
+ wire [3:0] T_2233_io_slave_1_aw_bits_cache;
+ wire [2:0] T_2233_io_slave_1_aw_bits_prot;
+ wire [3:0] T_2233_io_slave_1_aw_bits_qos;
+ wire [3:0] T_2233_io_slave_1_aw_bits_region;
+ wire [4:0] T_2233_io_slave_1_aw_bits_id;
+ wire T_2233_io_slave_1_aw_bits_user;
+ wire T_2233_io_slave_1_w_ready;
+ wire T_2233_io_slave_1_w_valid;
+ wire [63:0] T_2233_io_slave_1_w_bits_data;
+ wire T_2233_io_slave_1_w_bits_last;
+ wire [7:0] T_2233_io_slave_1_w_bits_strb;
+ wire T_2233_io_slave_1_w_bits_user;
+ wire T_2233_io_slave_1_b_ready;
+ wire T_2233_io_slave_1_b_valid;
+ wire [1:0] T_2233_io_slave_1_b_bits_resp;
+ wire [4:0] T_2233_io_slave_1_b_bits_id;
+ wire T_2233_io_slave_1_b_bits_user;
+ wire T_2233_io_slave_1_ar_ready;
+ wire T_2233_io_slave_1_ar_valid;
+ wire [31:0] T_2233_io_slave_1_ar_bits_addr;
+ wire [7:0] T_2233_io_slave_1_ar_bits_len;
+ wire [2:0] T_2233_io_slave_1_ar_bits_size;
+ wire [1:0] T_2233_io_slave_1_ar_bits_burst;
+ wire T_2233_io_slave_1_ar_bits_lock;
+ wire [3:0] T_2233_io_slave_1_ar_bits_cache;
+ wire [2:0] T_2233_io_slave_1_ar_bits_prot;
+ wire [3:0] T_2233_io_slave_1_ar_bits_qos;
+ wire [3:0] T_2233_io_slave_1_ar_bits_region;
+ wire [4:0] T_2233_io_slave_1_ar_bits_id;
+ wire T_2233_io_slave_1_ar_bits_user;
+ wire T_2233_io_slave_1_r_ready;
+ wire T_2233_io_slave_1_r_valid;
+ wire [1:0] T_2233_io_slave_1_r_bits_resp;
+ wire [63:0] T_2233_io_slave_1_r_bits_data;
+ wire T_2233_io_slave_1_r_bits_last;
+ wire [4:0] T_2233_io_slave_1_r_bits_id;
+ wire T_2233_io_slave_1_r_bits_user;
+ wire T_2233_io_slave_2_aw_ready;
+ wire T_2233_io_slave_2_aw_valid;
+ wire [31:0] T_2233_io_slave_2_aw_bits_addr;
+ wire [7:0] T_2233_io_slave_2_aw_bits_len;
+ wire [2:0] T_2233_io_slave_2_aw_bits_size;
+ wire [1:0] T_2233_io_slave_2_aw_bits_burst;
+ wire T_2233_io_slave_2_aw_bits_lock;
+ wire [3:0] T_2233_io_slave_2_aw_bits_cache;
+ wire [2:0] T_2233_io_slave_2_aw_bits_prot;
+ wire [3:0] T_2233_io_slave_2_aw_bits_qos;
+ wire [3:0] T_2233_io_slave_2_aw_bits_region;
+ wire [4:0] T_2233_io_slave_2_aw_bits_id;
+ wire T_2233_io_slave_2_aw_bits_user;
+ wire T_2233_io_slave_2_w_ready;
+ wire T_2233_io_slave_2_w_valid;
+ wire [63:0] T_2233_io_slave_2_w_bits_data;
+ wire T_2233_io_slave_2_w_bits_last;
+ wire [7:0] T_2233_io_slave_2_w_bits_strb;
+ wire T_2233_io_slave_2_w_bits_user;
+ wire T_2233_io_slave_2_b_ready;
+ wire T_2233_io_slave_2_b_valid;
+ wire [1:0] T_2233_io_slave_2_b_bits_resp;
+ wire [4:0] T_2233_io_slave_2_b_bits_id;
+ wire T_2233_io_slave_2_b_bits_user;
+ wire T_2233_io_slave_2_ar_ready;
+ wire T_2233_io_slave_2_ar_valid;
+ wire [31:0] T_2233_io_slave_2_ar_bits_addr;
+ wire [7:0] T_2233_io_slave_2_ar_bits_len;
+ wire [2:0] T_2233_io_slave_2_ar_bits_size;
+ wire [1:0] T_2233_io_slave_2_ar_bits_burst;
+ wire T_2233_io_slave_2_ar_bits_lock;
+ wire [3:0] T_2233_io_slave_2_ar_bits_cache;
+ wire [2:0] T_2233_io_slave_2_ar_bits_prot;
+ wire [3:0] T_2233_io_slave_2_ar_bits_qos;
+ wire [3:0] T_2233_io_slave_2_ar_bits_region;
+ wire [4:0] T_2233_io_slave_2_ar_bits_id;
+ wire T_2233_io_slave_2_ar_bits_user;
+ wire T_2233_io_slave_2_r_ready;
+ wire T_2233_io_slave_2_r_valid;
+ wire [1:0] T_2233_io_slave_2_r_bits_resp;
+ wire [63:0] T_2233_io_slave_2_r_bits_data;
+ wire T_2233_io_slave_2_r_bits_last;
+ wire [4:0] T_2233_io_slave_2_r_bits_id;
+ wire T_2233_io_slave_2_r_bits_user;
+ NastiRouter_58 T_2233 (
+ .clk(T_2233_clk),
+ .reset(T_2233_reset),
+ .io_master_aw_ready(T_2233_io_master_aw_ready),
+ .io_master_aw_valid(T_2233_io_master_aw_valid),
+ .io_master_aw_bits_addr(T_2233_io_master_aw_bits_addr),
+ .io_master_aw_bits_len(T_2233_io_master_aw_bits_len),
+ .io_master_aw_bits_size(T_2233_io_master_aw_bits_size),
+ .io_master_aw_bits_burst(T_2233_io_master_aw_bits_burst),
+ .io_master_aw_bits_lock(T_2233_io_master_aw_bits_lock),
+ .io_master_aw_bits_cache(T_2233_io_master_aw_bits_cache),
+ .io_master_aw_bits_prot(T_2233_io_master_aw_bits_prot),
+ .io_master_aw_bits_qos(T_2233_io_master_aw_bits_qos),
+ .io_master_aw_bits_region(T_2233_io_master_aw_bits_region),
+ .io_master_aw_bits_id(T_2233_io_master_aw_bits_id),
+ .io_master_aw_bits_user(T_2233_io_master_aw_bits_user),
+ .io_master_w_ready(T_2233_io_master_w_ready),
+ .io_master_w_valid(T_2233_io_master_w_valid),
+ .io_master_w_bits_data(T_2233_io_master_w_bits_data),
+ .io_master_w_bits_last(T_2233_io_master_w_bits_last),
+ .io_master_w_bits_strb(T_2233_io_master_w_bits_strb),
+ .io_master_w_bits_user(T_2233_io_master_w_bits_user),
+ .io_master_b_ready(T_2233_io_master_b_ready),
+ .io_master_b_valid(T_2233_io_master_b_valid),
+ .io_master_b_bits_resp(T_2233_io_master_b_bits_resp),
+ .io_master_b_bits_id(T_2233_io_master_b_bits_id),
+ .io_master_b_bits_user(T_2233_io_master_b_bits_user),
+ .io_master_ar_ready(T_2233_io_master_ar_ready),
+ .io_master_ar_valid(T_2233_io_master_ar_valid),
+ .io_master_ar_bits_addr(T_2233_io_master_ar_bits_addr),
+ .io_master_ar_bits_len(T_2233_io_master_ar_bits_len),
+ .io_master_ar_bits_size(T_2233_io_master_ar_bits_size),
+ .io_master_ar_bits_burst(T_2233_io_master_ar_bits_burst),
+ .io_master_ar_bits_lock(T_2233_io_master_ar_bits_lock),
+ .io_master_ar_bits_cache(T_2233_io_master_ar_bits_cache),
+ .io_master_ar_bits_prot(T_2233_io_master_ar_bits_prot),
+ .io_master_ar_bits_qos(T_2233_io_master_ar_bits_qos),
+ .io_master_ar_bits_region(T_2233_io_master_ar_bits_region),
+ .io_master_ar_bits_id(T_2233_io_master_ar_bits_id),
+ .io_master_ar_bits_user(T_2233_io_master_ar_bits_user),
+ .io_master_r_ready(T_2233_io_master_r_ready),
+ .io_master_r_valid(T_2233_io_master_r_valid),
+ .io_master_r_bits_resp(T_2233_io_master_r_bits_resp),
+ .io_master_r_bits_data(T_2233_io_master_r_bits_data),
+ .io_master_r_bits_last(T_2233_io_master_r_bits_last),
+ .io_master_r_bits_id(T_2233_io_master_r_bits_id),
+ .io_master_r_bits_user(T_2233_io_master_r_bits_user),
+ .io_slave_0_aw_ready(T_2233_io_slave_0_aw_ready),
+ .io_slave_0_aw_valid(T_2233_io_slave_0_aw_valid),
+ .io_slave_0_aw_bits_addr(T_2233_io_slave_0_aw_bits_addr),
+ .io_slave_0_aw_bits_len(T_2233_io_slave_0_aw_bits_len),
+ .io_slave_0_aw_bits_size(T_2233_io_slave_0_aw_bits_size),
+ .io_slave_0_aw_bits_burst(T_2233_io_slave_0_aw_bits_burst),
+ .io_slave_0_aw_bits_lock(T_2233_io_slave_0_aw_bits_lock),
+ .io_slave_0_aw_bits_cache(T_2233_io_slave_0_aw_bits_cache),
+ .io_slave_0_aw_bits_prot(T_2233_io_slave_0_aw_bits_prot),
+ .io_slave_0_aw_bits_qos(T_2233_io_slave_0_aw_bits_qos),
+ .io_slave_0_aw_bits_region(T_2233_io_slave_0_aw_bits_region),
+ .io_slave_0_aw_bits_id(T_2233_io_slave_0_aw_bits_id),
+ .io_slave_0_aw_bits_user(T_2233_io_slave_0_aw_bits_user),
+ .io_slave_0_w_ready(T_2233_io_slave_0_w_ready),
+ .io_slave_0_w_valid(T_2233_io_slave_0_w_valid),
+ .io_slave_0_w_bits_data(T_2233_io_slave_0_w_bits_data),
+ .io_slave_0_w_bits_last(T_2233_io_slave_0_w_bits_last),
+ .io_slave_0_w_bits_strb(T_2233_io_slave_0_w_bits_strb),
+ .io_slave_0_w_bits_user(T_2233_io_slave_0_w_bits_user),
+ .io_slave_0_b_ready(T_2233_io_slave_0_b_ready),
+ .io_slave_0_b_valid(T_2233_io_slave_0_b_valid),
+ .io_slave_0_b_bits_resp(T_2233_io_slave_0_b_bits_resp),
+ .io_slave_0_b_bits_id(T_2233_io_slave_0_b_bits_id),
+ .io_slave_0_b_bits_user(T_2233_io_slave_0_b_bits_user),
+ .io_slave_0_ar_ready(T_2233_io_slave_0_ar_ready),
+ .io_slave_0_ar_valid(T_2233_io_slave_0_ar_valid),
+ .io_slave_0_ar_bits_addr(T_2233_io_slave_0_ar_bits_addr),
+ .io_slave_0_ar_bits_len(T_2233_io_slave_0_ar_bits_len),
+ .io_slave_0_ar_bits_size(T_2233_io_slave_0_ar_bits_size),
+ .io_slave_0_ar_bits_burst(T_2233_io_slave_0_ar_bits_burst),
+ .io_slave_0_ar_bits_lock(T_2233_io_slave_0_ar_bits_lock),
+ .io_slave_0_ar_bits_cache(T_2233_io_slave_0_ar_bits_cache),
+ .io_slave_0_ar_bits_prot(T_2233_io_slave_0_ar_bits_prot),
+ .io_slave_0_ar_bits_qos(T_2233_io_slave_0_ar_bits_qos),
+ .io_slave_0_ar_bits_region(T_2233_io_slave_0_ar_bits_region),
+ .io_slave_0_ar_bits_id(T_2233_io_slave_0_ar_bits_id),
+ .io_slave_0_ar_bits_user(T_2233_io_slave_0_ar_bits_user),
+ .io_slave_0_r_ready(T_2233_io_slave_0_r_ready),
+ .io_slave_0_r_valid(T_2233_io_slave_0_r_valid),
+ .io_slave_0_r_bits_resp(T_2233_io_slave_0_r_bits_resp),
+ .io_slave_0_r_bits_data(T_2233_io_slave_0_r_bits_data),
+ .io_slave_0_r_bits_last(T_2233_io_slave_0_r_bits_last),
+ .io_slave_0_r_bits_id(T_2233_io_slave_0_r_bits_id),
+ .io_slave_0_r_bits_user(T_2233_io_slave_0_r_bits_user),
+ .io_slave_1_aw_ready(T_2233_io_slave_1_aw_ready),
+ .io_slave_1_aw_valid(T_2233_io_slave_1_aw_valid),
+ .io_slave_1_aw_bits_addr(T_2233_io_slave_1_aw_bits_addr),
+ .io_slave_1_aw_bits_len(T_2233_io_slave_1_aw_bits_len),
+ .io_slave_1_aw_bits_size(T_2233_io_slave_1_aw_bits_size),
+ .io_slave_1_aw_bits_burst(T_2233_io_slave_1_aw_bits_burst),
+ .io_slave_1_aw_bits_lock(T_2233_io_slave_1_aw_bits_lock),
+ .io_slave_1_aw_bits_cache(T_2233_io_slave_1_aw_bits_cache),
+ .io_slave_1_aw_bits_prot(T_2233_io_slave_1_aw_bits_prot),
+ .io_slave_1_aw_bits_qos(T_2233_io_slave_1_aw_bits_qos),
+ .io_slave_1_aw_bits_region(T_2233_io_slave_1_aw_bits_region),
+ .io_slave_1_aw_bits_id(T_2233_io_slave_1_aw_bits_id),
+ .io_slave_1_aw_bits_user(T_2233_io_slave_1_aw_bits_user),
+ .io_slave_1_w_ready(T_2233_io_slave_1_w_ready),
+ .io_slave_1_w_valid(T_2233_io_slave_1_w_valid),
+ .io_slave_1_w_bits_data(T_2233_io_slave_1_w_bits_data),
+ .io_slave_1_w_bits_last(T_2233_io_slave_1_w_bits_last),
+ .io_slave_1_w_bits_strb(T_2233_io_slave_1_w_bits_strb),
+ .io_slave_1_w_bits_user(T_2233_io_slave_1_w_bits_user),
+ .io_slave_1_b_ready(T_2233_io_slave_1_b_ready),
+ .io_slave_1_b_valid(T_2233_io_slave_1_b_valid),
+ .io_slave_1_b_bits_resp(T_2233_io_slave_1_b_bits_resp),
+ .io_slave_1_b_bits_id(T_2233_io_slave_1_b_bits_id),
+ .io_slave_1_b_bits_user(T_2233_io_slave_1_b_bits_user),
+ .io_slave_1_ar_ready(T_2233_io_slave_1_ar_ready),
+ .io_slave_1_ar_valid(T_2233_io_slave_1_ar_valid),
+ .io_slave_1_ar_bits_addr(T_2233_io_slave_1_ar_bits_addr),
+ .io_slave_1_ar_bits_len(T_2233_io_slave_1_ar_bits_len),
+ .io_slave_1_ar_bits_size(T_2233_io_slave_1_ar_bits_size),
+ .io_slave_1_ar_bits_burst(T_2233_io_slave_1_ar_bits_burst),
+ .io_slave_1_ar_bits_lock(T_2233_io_slave_1_ar_bits_lock),
+ .io_slave_1_ar_bits_cache(T_2233_io_slave_1_ar_bits_cache),
+ .io_slave_1_ar_bits_prot(T_2233_io_slave_1_ar_bits_prot),
+ .io_slave_1_ar_bits_qos(T_2233_io_slave_1_ar_bits_qos),
+ .io_slave_1_ar_bits_region(T_2233_io_slave_1_ar_bits_region),
+ .io_slave_1_ar_bits_id(T_2233_io_slave_1_ar_bits_id),
+ .io_slave_1_ar_bits_user(T_2233_io_slave_1_ar_bits_user),
+ .io_slave_1_r_ready(T_2233_io_slave_1_r_ready),
+ .io_slave_1_r_valid(T_2233_io_slave_1_r_valid),
+ .io_slave_1_r_bits_resp(T_2233_io_slave_1_r_bits_resp),
+ .io_slave_1_r_bits_data(T_2233_io_slave_1_r_bits_data),
+ .io_slave_1_r_bits_last(T_2233_io_slave_1_r_bits_last),
+ .io_slave_1_r_bits_id(T_2233_io_slave_1_r_bits_id),
+ .io_slave_1_r_bits_user(T_2233_io_slave_1_r_bits_user),
+ .io_slave_2_aw_ready(T_2233_io_slave_2_aw_ready),
+ .io_slave_2_aw_valid(T_2233_io_slave_2_aw_valid),
+ .io_slave_2_aw_bits_addr(T_2233_io_slave_2_aw_bits_addr),
+ .io_slave_2_aw_bits_len(T_2233_io_slave_2_aw_bits_len),
+ .io_slave_2_aw_bits_size(T_2233_io_slave_2_aw_bits_size),
+ .io_slave_2_aw_bits_burst(T_2233_io_slave_2_aw_bits_burst),
+ .io_slave_2_aw_bits_lock(T_2233_io_slave_2_aw_bits_lock),
+ .io_slave_2_aw_bits_cache(T_2233_io_slave_2_aw_bits_cache),
+ .io_slave_2_aw_bits_prot(T_2233_io_slave_2_aw_bits_prot),
+ .io_slave_2_aw_bits_qos(T_2233_io_slave_2_aw_bits_qos),
+ .io_slave_2_aw_bits_region(T_2233_io_slave_2_aw_bits_region),
+ .io_slave_2_aw_bits_id(T_2233_io_slave_2_aw_bits_id),
+ .io_slave_2_aw_bits_user(T_2233_io_slave_2_aw_bits_user),
+ .io_slave_2_w_ready(T_2233_io_slave_2_w_ready),
+ .io_slave_2_w_valid(T_2233_io_slave_2_w_valid),
+ .io_slave_2_w_bits_data(T_2233_io_slave_2_w_bits_data),
+ .io_slave_2_w_bits_last(T_2233_io_slave_2_w_bits_last),
+ .io_slave_2_w_bits_strb(T_2233_io_slave_2_w_bits_strb),
+ .io_slave_2_w_bits_user(T_2233_io_slave_2_w_bits_user),
+ .io_slave_2_b_ready(T_2233_io_slave_2_b_ready),
+ .io_slave_2_b_valid(T_2233_io_slave_2_b_valid),
+ .io_slave_2_b_bits_resp(T_2233_io_slave_2_b_bits_resp),
+ .io_slave_2_b_bits_id(T_2233_io_slave_2_b_bits_id),
+ .io_slave_2_b_bits_user(T_2233_io_slave_2_b_bits_user),
+ .io_slave_2_ar_ready(T_2233_io_slave_2_ar_ready),
+ .io_slave_2_ar_valid(T_2233_io_slave_2_ar_valid),
+ .io_slave_2_ar_bits_addr(T_2233_io_slave_2_ar_bits_addr),
+ .io_slave_2_ar_bits_len(T_2233_io_slave_2_ar_bits_len),
+ .io_slave_2_ar_bits_size(T_2233_io_slave_2_ar_bits_size),
+ .io_slave_2_ar_bits_burst(T_2233_io_slave_2_ar_bits_burst),
+ .io_slave_2_ar_bits_lock(T_2233_io_slave_2_ar_bits_lock),
+ .io_slave_2_ar_bits_cache(T_2233_io_slave_2_ar_bits_cache),
+ .io_slave_2_ar_bits_prot(T_2233_io_slave_2_ar_bits_prot),
+ .io_slave_2_ar_bits_qos(T_2233_io_slave_2_ar_bits_qos),
+ .io_slave_2_ar_bits_region(T_2233_io_slave_2_ar_bits_region),
+ .io_slave_2_ar_bits_id(T_2233_io_slave_2_ar_bits_id),
+ .io_slave_2_ar_bits_user(T_2233_io_slave_2_ar_bits_user),
+ .io_slave_2_r_ready(T_2233_io_slave_2_r_ready),
+ .io_slave_2_r_valid(T_2233_io_slave_2_r_valid),
+ .io_slave_2_r_bits_resp(T_2233_io_slave_2_r_bits_resp),
+ .io_slave_2_r_bits_data(T_2233_io_slave_2_r_bits_data),
+ .io_slave_2_r_bits_last(T_2233_io_slave_2_r_bits_last),
+ .io_slave_2_r_bits_id(T_2233_io_slave_2_r_bits_id),
+ .io_slave_2_r_bits_user(T_2233_io_slave_2_r_bits_user)
+ );
+ assign io_masters_0_aw_ready = T_2233_io_master_aw_ready;
+ assign io_masters_0_w_ready = T_2233_io_master_w_ready;
+ assign io_masters_0_b_valid = T_2233_io_master_b_valid;
+ assign io_masters_0_b_bits_resp = T_2233_io_master_b_bits_resp;
+ assign io_masters_0_b_bits_id = T_2233_io_master_b_bits_id;
+ assign io_masters_0_b_bits_user = T_2233_io_master_b_bits_user;
+ assign io_masters_0_ar_ready = T_2233_io_master_ar_ready;
+ assign io_masters_0_r_valid = T_2233_io_master_r_valid;
+ assign io_masters_0_r_bits_resp = T_2233_io_master_r_bits_resp;
+ assign io_masters_0_r_bits_data = T_2233_io_master_r_bits_data;
+ assign io_masters_0_r_bits_last = T_2233_io_master_r_bits_last;
+ assign io_masters_0_r_bits_id = T_2233_io_master_r_bits_id;
+ assign io_masters_0_r_bits_user = T_2233_io_master_r_bits_user;
+ assign io_slaves_0_aw_valid = T_2233_io_slave_0_aw_valid;
+ assign io_slaves_0_aw_bits_addr = T_2233_io_slave_0_aw_bits_addr;
+ assign io_slaves_0_aw_bits_len = T_2233_io_slave_0_aw_bits_len;
+ assign io_slaves_0_aw_bits_size = T_2233_io_slave_0_aw_bits_size;
+ assign io_slaves_0_aw_bits_burst = T_2233_io_slave_0_aw_bits_burst;
+ assign io_slaves_0_aw_bits_lock = T_2233_io_slave_0_aw_bits_lock;
+ assign io_slaves_0_aw_bits_cache = T_2233_io_slave_0_aw_bits_cache;
+ assign io_slaves_0_aw_bits_prot = T_2233_io_slave_0_aw_bits_prot;
+ assign io_slaves_0_aw_bits_qos = T_2233_io_slave_0_aw_bits_qos;
+ assign io_slaves_0_aw_bits_region = T_2233_io_slave_0_aw_bits_region;
+ assign io_slaves_0_aw_bits_id = T_2233_io_slave_0_aw_bits_id;
+ assign io_slaves_0_aw_bits_user = T_2233_io_slave_0_aw_bits_user;
+ assign io_slaves_0_w_valid = T_2233_io_slave_0_w_valid;
+ assign io_slaves_0_w_bits_data = T_2233_io_slave_0_w_bits_data;
+ assign io_slaves_0_w_bits_last = T_2233_io_slave_0_w_bits_last;
+ assign io_slaves_0_w_bits_strb = T_2233_io_slave_0_w_bits_strb;
+ assign io_slaves_0_w_bits_user = T_2233_io_slave_0_w_bits_user;
+ assign io_slaves_0_b_ready = T_2233_io_slave_0_b_ready;
+ assign io_slaves_0_ar_valid = T_2233_io_slave_0_ar_valid;
+ assign io_slaves_0_ar_bits_addr = T_2233_io_slave_0_ar_bits_addr;
+ assign io_slaves_0_ar_bits_len = T_2233_io_slave_0_ar_bits_len;
+ assign io_slaves_0_ar_bits_size = T_2233_io_slave_0_ar_bits_size;
+ assign io_slaves_0_ar_bits_burst = T_2233_io_slave_0_ar_bits_burst;
+ assign io_slaves_0_ar_bits_lock = T_2233_io_slave_0_ar_bits_lock;
+ assign io_slaves_0_ar_bits_cache = T_2233_io_slave_0_ar_bits_cache;
+ assign io_slaves_0_ar_bits_prot = T_2233_io_slave_0_ar_bits_prot;
+ assign io_slaves_0_ar_bits_qos = T_2233_io_slave_0_ar_bits_qos;
+ assign io_slaves_0_ar_bits_region = T_2233_io_slave_0_ar_bits_region;
+ assign io_slaves_0_ar_bits_id = T_2233_io_slave_0_ar_bits_id;
+ assign io_slaves_0_ar_bits_user = T_2233_io_slave_0_ar_bits_user;
+ assign io_slaves_0_r_ready = T_2233_io_slave_0_r_ready;
+ assign io_slaves_1_aw_valid = T_2233_io_slave_1_aw_valid;
+ assign io_slaves_1_aw_bits_addr = T_2233_io_slave_1_aw_bits_addr;
+ assign io_slaves_1_aw_bits_len = T_2233_io_slave_1_aw_bits_len;
+ assign io_slaves_1_aw_bits_size = T_2233_io_slave_1_aw_bits_size;
+ assign io_slaves_1_aw_bits_burst = T_2233_io_slave_1_aw_bits_burst;
+ assign io_slaves_1_aw_bits_lock = T_2233_io_slave_1_aw_bits_lock;
+ assign io_slaves_1_aw_bits_cache = T_2233_io_slave_1_aw_bits_cache;
+ assign io_slaves_1_aw_bits_prot = T_2233_io_slave_1_aw_bits_prot;
+ assign io_slaves_1_aw_bits_qos = T_2233_io_slave_1_aw_bits_qos;
+ assign io_slaves_1_aw_bits_region = T_2233_io_slave_1_aw_bits_region;
+ assign io_slaves_1_aw_bits_id = T_2233_io_slave_1_aw_bits_id;
+ assign io_slaves_1_aw_bits_user = T_2233_io_slave_1_aw_bits_user;
+ assign io_slaves_1_w_valid = T_2233_io_slave_1_w_valid;
+ assign io_slaves_1_w_bits_data = T_2233_io_slave_1_w_bits_data;
+ assign io_slaves_1_w_bits_last = T_2233_io_slave_1_w_bits_last;
+ assign io_slaves_1_w_bits_strb = T_2233_io_slave_1_w_bits_strb;
+ assign io_slaves_1_w_bits_user = T_2233_io_slave_1_w_bits_user;
+ assign io_slaves_1_b_ready = T_2233_io_slave_1_b_ready;
+ assign io_slaves_1_ar_valid = T_2233_io_slave_1_ar_valid;
+ assign io_slaves_1_ar_bits_addr = T_2233_io_slave_1_ar_bits_addr;
+ assign io_slaves_1_ar_bits_len = T_2233_io_slave_1_ar_bits_len;
+ assign io_slaves_1_ar_bits_size = T_2233_io_slave_1_ar_bits_size;
+ assign io_slaves_1_ar_bits_burst = T_2233_io_slave_1_ar_bits_burst;
+ assign io_slaves_1_ar_bits_lock = T_2233_io_slave_1_ar_bits_lock;
+ assign io_slaves_1_ar_bits_cache = T_2233_io_slave_1_ar_bits_cache;
+ assign io_slaves_1_ar_bits_prot = T_2233_io_slave_1_ar_bits_prot;
+ assign io_slaves_1_ar_bits_qos = T_2233_io_slave_1_ar_bits_qos;
+ assign io_slaves_1_ar_bits_region = T_2233_io_slave_1_ar_bits_region;
+ assign io_slaves_1_ar_bits_id = T_2233_io_slave_1_ar_bits_id;
+ assign io_slaves_1_ar_bits_user = T_2233_io_slave_1_ar_bits_user;
+ assign io_slaves_1_r_ready = T_2233_io_slave_1_r_ready;
+ assign io_slaves_2_aw_valid = T_2233_io_slave_2_aw_valid;
+ assign io_slaves_2_aw_bits_addr = T_2233_io_slave_2_aw_bits_addr;
+ assign io_slaves_2_aw_bits_len = T_2233_io_slave_2_aw_bits_len;
+ assign io_slaves_2_aw_bits_size = T_2233_io_slave_2_aw_bits_size;
+ assign io_slaves_2_aw_bits_burst = T_2233_io_slave_2_aw_bits_burst;
+ assign io_slaves_2_aw_bits_lock = T_2233_io_slave_2_aw_bits_lock;
+ assign io_slaves_2_aw_bits_cache = T_2233_io_slave_2_aw_bits_cache;
+ assign io_slaves_2_aw_bits_prot = T_2233_io_slave_2_aw_bits_prot;
+ assign io_slaves_2_aw_bits_qos = T_2233_io_slave_2_aw_bits_qos;
+ assign io_slaves_2_aw_bits_region = T_2233_io_slave_2_aw_bits_region;
+ assign io_slaves_2_aw_bits_id = T_2233_io_slave_2_aw_bits_id;
+ assign io_slaves_2_aw_bits_user = T_2233_io_slave_2_aw_bits_user;
+ assign io_slaves_2_w_valid = T_2233_io_slave_2_w_valid;
+ assign io_slaves_2_w_bits_data = T_2233_io_slave_2_w_bits_data;
+ assign io_slaves_2_w_bits_last = T_2233_io_slave_2_w_bits_last;
+ assign io_slaves_2_w_bits_strb = T_2233_io_slave_2_w_bits_strb;
+ assign io_slaves_2_w_bits_user = T_2233_io_slave_2_w_bits_user;
+ assign io_slaves_2_b_ready = T_2233_io_slave_2_b_ready;
+ assign io_slaves_2_ar_valid = T_2233_io_slave_2_ar_valid;
+ assign io_slaves_2_ar_bits_addr = T_2233_io_slave_2_ar_bits_addr;
+ assign io_slaves_2_ar_bits_len = T_2233_io_slave_2_ar_bits_len;
+ assign io_slaves_2_ar_bits_size = T_2233_io_slave_2_ar_bits_size;
+ assign io_slaves_2_ar_bits_burst = T_2233_io_slave_2_ar_bits_burst;
+ assign io_slaves_2_ar_bits_lock = T_2233_io_slave_2_ar_bits_lock;
+ assign io_slaves_2_ar_bits_cache = T_2233_io_slave_2_ar_bits_cache;
+ assign io_slaves_2_ar_bits_prot = T_2233_io_slave_2_ar_bits_prot;
+ assign io_slaves_2_ar_bits_qos = T_2233_io_slave_2_ar_bits_qos;
+ assign io_slaves_2_ar_bits_region = T_2233_io_slave_2_ar_bits_region;
+ assign io_slaves_2_ar_bits_id = T_2233_io_slave_2_ar_bits_id;
+ assign io_slaves_2_ar_bits_user = T_2233_io_slave_2_ar_bits_user;
+ assign io_slaves_2_r_ready = T_2233_io_slave_2_r_ready;
+ assign T_2233_clk = clk;
+ assign T_2233_reset = reset;
+ assign T_2233_io_master_aw_valid = io_masters_0_aw_valid;
+ assign T_2233_io_master_aw_bits_addr = io_masters_0_aw_bits_addr;
+ assign T_2233_io_master_aw_bits_len = io_masters_0_aw_bits_len;
+ assign T_2233_io_master_aw_bits_size = io_masters_0_aw_bits_size;
+ assign T_2233_io_master_aw_bits_burst = io_masters_0_aw_bits_burst;
+ assign T_2233_io_master_aw_bits_lock = io_masters_0_aw_bits_lock;
+ assign T_2233_io_master_aw_bits_cache = io_masters_0_aw_bits_cache;
+ assign T_2233_io_master_aw_bits_prot = io_masters_0_aw_bits_prot;
+ assign T_2233_io_master_aw_bits_qos = io_masters_0_aw_bits_qos;
+ assign T_2233_io_master_aw_bits_region = io_masters_0_aw_bits_region;
+ assign T_2233_io_master_aw_bits_id = io_masters_0_aw_bits_id;
+ assign T_2233_io_master_aw_bits_user = io_masters_0_aw_bits_user;
+ assign T_2233_io_master_w_valid = io_masters_0_w_valid;
+ assign T_2233_io_master_w_bits_data = io_masters_0_w_bits_data;
+ assign T_2233_io_master_w_bits_last = io_masters_0_w_bits_last;
+ assign T_2233_io_master_w_bits_strb = io_masters_0_w_bits_strb;
+ assign T_2233_io_master_w_bits_user = io_masters_0_w_bits_user;
+ assign T_2233_io_master_b_ready = io_masters_0_b_ready;
+ assign T_2233_io_master_ar_valid = io_masters_0_ar_valid;
+ assign T_2233_io_master_ar_bits_addr = io_masters_0_ar_bits_addr;
+ assign T_2233_io_master_ar_bits_len = io_masters_0_ar_bits_len;
+ assign T_2233_io_master_ar_bits_size = io_masters_0_ar_bits_size;
+ assign T_2233_io_master_ar_bits_burst = io_masters_0_ar_bits_burst;
+ assign T_2233_io_master_ar_bits_lock = io_masters_0_ar_bits_lock;
+ assign T_2233_io_master_ar_bits_cache = io_masters_0_ar_bits_cache;
+ assign T_2233_io_master_ar_bits_prot = io_masters_0_ar_bits_prot;
+ assign T_2233_io_master_ar_bits_qos = io_masters_0_ar_bits_qos;
+ assign T_2233_io_master_ar_bits_region = io_masters_0_ar_bits_region;
+ assign T_2233_io_master_ar_bits_id = io_masters_0_ar_bits_id;
+ assign T_2233_io_master_ar_bits_user = io_masters_0_ar_bits_user;
+ assign T_2233_io_master_r_ready = io_masters_0_r_ready;
+ assign T_2233_io_slave_0_aw_ready = io_slaves_0_aw_ready;
+ assign T_2233_io_slave_0_w_ready = io_slaves_0_w_ready;
+ assign T_2233_io_slave_0_b_valid = io_slaves_0_b_valid;
+ assign T_2233_io_slave_0_b_bits_resp = io_slaves_0_b_bits_resp;
+ assign T_2233_io_slave_0_b_bits_id = io_slaves_0_b_bits_id;
+ assign T_2233_io_slave_0_b_bits_user = io_slaves_0_b_bits_user;
+ assign T_2233_io_slave_0_ar_ready = io_slaves_0_ar_ready;
+ assign T_2233_io_slave_0_r_valid = io_slaves_0_r_valid;
+ assign T_2233_io_slave_0_r_bits_resp = io_slaves_0_r_bits_resp;
+ assign T_2233_io_slave_0_r_bits_data = io_slaves_0_r_bits_data;
+ assign T_2233_io_slave_0_r_bits_last = io_slaves_0_r_bits_last;
+ assign T_2233_io_slave_0_r_bits_id = io_slaves_0_r_bits_id;
+ assign T_2233_io_slave_0_r_bits_user = io_slaves_0_r_bits_user;
+ assign T_2233_io_slave_1_aw_ready = io_slaves_1_aw_ready;
+ assign T_2233_io_slave_1_w_ready = io_slaves_1_w_ready;
+ assign T_2233_io_slave_1_b_valid = io_slaves_1_b_valid;
+ assign T_2233_io_slave_1_b_bits_resp = io_slaves_1_b_bits_resp;
+ assign T_2233_io_slave_1_b_bits_id = io_slaves_1_b_bits_id;
+ assign T_2233_io_slave_1_b_bits_user = io_slaves_1_b_bits_user;
+ assign T_2233_io_slave_1_ar_ready = io_slaves_1_ar_ready;
+ assign T_2233_io_slave_1_r_valid = io_slaves_1_r_valid;
+ assign T_2233_io_slave_1_r_bits_resp = io_slaves_1_r_bits_resp;
+ assign T_2233_io_slave_1_r_bits_data = io_slaves_1_r_bits_data;
+ assign T_2233_io_slave_1_r_bits_last = io_slaves_1_r_bits_last;
+ assign T_2233_io_slave_1_r_bits_id = io_slaves_1_r_bits_id;
+ assign T_2233_io_slave_1_r_bits_user = io_slaves_1_r_bits_user;
+ assign T_2233_io_slave_2_aw_ready = io_slaves_2_aw_ready;
+ assign T_2233_io_slave_2_w_ready = io_slaves_2_w_ready;
+ assign T_2233_io_slave_2_b_valid = io_slaves_2_b_valid;
+ assign T_2233_io_slave_2_b_bits_resp = io_slaves_2_b_bits_resp;
+ assign T_2233_io_slave_2_b_bits_id = io_slaves_2_b_bits_id;
+ assign T_2233_io_slave_2_b_bits_user = io_slaves_2_b_bits_user;
+ assign T_2233_io_slave_2_ar_ready = io_slaves_2_ar_ready;
+ assign T_2233_io_slave_2_r_valid = io_slaves_2_r_valid;
+ assign T_2233_io_slave_2_r_bits_resp = io_slaves_2_r_bits_resp;
+ assign T_2233_io_slave_2_r_bits_data = io_slaves_2_r_bits_data;
+ assign T_2233_io_slave_2_r_bits_last = io_slaves_2_r_bits_last;
+ assign T_2233_io_slave_2_r_bits_id = io_slaves_2_r_bits_id;
+ assign T_2233_io_slave_2_r_bits_user = io_slaves_2_r_bits_user;
+endmodule
+module NastiRecursiveInterconnect_56(
+ input clk,
+ input reset,
+ output io_masters_0_aw_ready,
+ input io_masters_0_aw_valid,
+ input [31:0] io_masters_0_aw_bits_addr,
+ input [7:0] io_masters_0_aw_bits_len,
+ input [2:0] io_masters_0_aw_bits_size,
+ input [1:0] io_masters_0_aw_bits_burst,
+ input io_masters_0_aw_bits_lock,
+ input [3:0] io_masters_0_aw_bits_cache,
+ input [2:0] io_masters_0_aw_bits_prot,
+ input [3:0] io_masters_0_aw_bits_qos,
+ input [3:0] io_masters_0_aw_bits_region,
+ input [4:0] io_masters_0_aw_bits_id,
+ input io_masters_0_aw_bits_user,
+ output io_masters_0_w_ready,
+ input io_masters_0_w_valid,
+ input [63:0] io_masters_0_w_bits_data,
+ input io_masters_0_w_bits_last,
+ input [7:0] io_masters_0_w_bits_strb,
+ input io_masters_0_w_bits_user,
+ input io_masters_0_b_ready,
+ output io_masters_0_b_valid,
+ output [1:0] io_masters_0_b_bits_resp,
+ output [4:0] io_masters_0_b_bits_id,
+ output io_masters_0_b_bits_user,
+ output io_masters_0_ar_ready,
+ input io_masters_0_ar_valid,
+ input [31:0] io_masters_0_ar_bits_addr,
+ input [7:0] io_masters_0_ar_bits_len,
+ input [2:0] io_masters_0_ar_bits_size,
+ input [1:0] io_masters_0_ar_bits_burst,
+ input io_masters_0_ar_bits_lock,
+ input [3:0] io_masters_0_ar_bits_cache,
+ input [2:0] io_masters_0_ar_bits_prot,
+ input [3:0] io_masters_0_ar_bits_qos,
+ input [3:0] io_masters_0_ar_bits_region,
+ input [4:0] io_masters_0_ar_bits_id,
+ input io_masters_0_ar_bits_user,
+ input io_masters_0_r_ready,
+ output io_masters_0_r_valid,
+ output [1:0] io_masters_0_r_bits_resp,
+ output [63:0] io_masters_0_r_bits_data,
+ output io_masters_0_r_bits_last,
+ output [4:0] io_masters_0_r_bits_id,
+ output io_masters_0_r_bits_user,
+ input io_slaves_0_aw_ready,
+ output io_slaves_0_aw_valid,
+ output [31:0] io_slaves_0_aw_bits_addr,
+ output [7:0] io_slaves_0_aw_bits_len,
+ output [2:0] io_slaves_0_aw_bits_size,
+ output [1:0] io_slaves_0_aw_bits_burst,
+ output io_slaves_0_aw_bits_lock,
+ output [3:0] io_slaves_0_aw_bits_cache,
+ output [2:0] io_slaves_0_aw_bits_prot,
+ output [3:0] io_slaves_0_aw_bits_qos,
+ output [3:0] io_slaves_0_aw_bits_region,
+ output [4:0] io_slaves_0_aw_bits_id,
+ output io_slaves_0_aw_bits_user,
+ input io_slaves_0_w_ready,
+ output io_slaves_0_w_valid,
+ output [63:0] io_slaves_0_w_bits_data,
+ output io_slaves_0_w_bits_last,
+ output [7:0] io_slaves_0_w_bits_strb,
+ output io_slaves_0_w_bits_user,
+ output io_slaves_0_b_ready,
+ input io_slaves_0_b_valid,
+ input [1:0] io_slaves_0_b_bits_resp,
+ input [4:0] io_slaves_0_b_bits_id,
+ input io_slaves_0_b_bits_user,
+ input io_slaves_0_ar_ready,
+ output io_slaves_0_ar_valid,
+ output [31:0] io_slaves_0_ar_bits_addr,
+ output [7:0] io_slaves_0_ar_bits_len,
+ output [2:0] io_slaves_0_ar_bits_size,
+ output [1:0] io_slaves_0_ar_bits_burst,
+ output io_slaves_0_ar_bits_lock,
+ output [3:0] io_slaves_0_ar_bits_cache,
+ output [2:0] io_slaves_0_ar_bits_prot,
+ output [3:0] io_slaves_0_ar_bits_qos,
+ output [3:0] io_slaves_0_ar_bits_region,
+ output [4:0] io_slaves_0_ar_bits_id,
+ output io_slaves_0_ar_bits_user,
+ output io_slaves_0_r_ready,
+ input io_slaves_0_r_valid,
+ input [1:0] io_slaves_0_r_bits_resp,
+ input [63:0] io_slaves_0_r_bits_data,
+ input io_slaves_0_r_bits_last,
+ input [4:0] io_slaves_0_r_bits_id,
+ input io_slaves_0_r_bits_user,
+ input io_slaves_1_aw_ready,
+ output io_slaves_1_aw_valid,
+ output [31:0] io_slaves_1_aw_bits_addr,
+ output [7:0] io_slaves_1_aw_bits_len,
+ output [2:0] io_slaves_1_aw_bits_size,
+ output [1:0] io_slaves_1_aw_bits_burst,
+ output io_slaves_1_aw_bits_lock,
+ output [3:0] io_slaves_1_aw_bits_cache,
+ output [2:0] io_slaves_1_aw_bits_prot,
+ output [3:0] io_slaves_1_aw_bits_qos,
+ output [3:0] io_slaves_1_aw_bits_region,
+ output [4:0] io_slaves_1_aw_bits_id,
+ output io_slaves_1_aw_bits_user,
+ input io_slaves_1_w_ready,
+ output io_slaves_1_w_valid,
+ output [63:0] io_slaves_1_w_bits_data,
+ output io_slaves_1_w_bits_last,
+ output [7:0] io_slaves_1_w_bits_strb,
+ output io_slaves_1_w_bits_user,
+ output io_slaves_1_b_ready,
+ input io_slaves_1_b_valid,
+ input [1:0] io_slaves_1_b_bits_resp,
+ input [4:0] io_slaves_1_b_bits_id,
+ input io_slaves_1_b_bits_user,
+ input io_slaves_1_ar_ready,
+ output io_slaves_1_ar_valid,
+ output [31:0] io_slaves_1_ar_bits_addr,
+ output [7:0] io_slaves_1_ar_bits_len,
+ output [2:0] io_slaves_1_ar_bits_size,
+ output [1:0] io_slaves_1_ar_bits_burst,
+ output io_slaves_1_ar_bits_lock,
+ output [3:0] io_slaves_1_ar_bits_cache,
+ output [2:0] io_slaves_1_ar_bits_prot,
+ output [3:0] io_slaves_1_ar_bits_qos,
+ output [3:0] io_slaves_1_ar_bits_region,
+ output [4:0] io_slaves_1_ar_bits_id,
+ output io_slaves_1_ar_bits_user,
+ output io_slaves_1_r_ready,
+ input io_slaves_1_r_valid,
+ input [1:0] io_slaves_1_r_bits_resp,
+ input [63:0] io_slaves_1_r_bits_data,
+ input io_slaves_1_r_bits_last,
+ input [4:0] io_slaves_1_r_bits_id,
+ input io_slaves_1_r_bits_user,
+ input io_slaves_2_aw_ready,
+ output io_slaves_2_aw_valid,
+ output [31:0] io_slaves_2_aw_bits_addr,
+ output [7:0] io_slaves_2_aw_bits_len,
+ output [2:0] io_slaves_2_aw_bits_size,
+ output [1:0] io_slaves_2_aw_bits_burst,
+ output io_slaves_2_aw_bits_lock,
+ output [3:0] io_slaves_2_aw_bits_cache,
+ output [2:0] io_slaves_2_aw_bits_prot,
+ output [3:0] io_slaves_2_aw_bits_qos,
+ output [3:0] io_slaves_2_aw_bits_region,
+ output [4:0] io_slaves_2_aw_bits_id,
+ output io_slaves_2_aw_bits_user,
+ input io_slaves_2_w_ready,
+ output io_slaves_2_w_valid,
+ output [63:0] io_slaves_2_w_bits_data,
+ output io_slaves_2_w_bits_last,
+ output [7:0] io_slaves_2_w_bits_strb,
+ output io_slaves_2_w_bits_user,
+ output io_slaves_2_b_ready,
+ input io_slaves_2_b_valid,
+ input [1:0] io_slaves_2_b_bits_resp,
+ input [4:0] io_slaves_2_b_bits_id,
+ input io_slaves_2_b_bits_user,
+ input io_slaves_2_ar_ready,
+ output io_slaves_2_ar_valid,
+ output [31:0] io_slaves_2_ar_bits_addr,
+ output [7:0] io_slaves_2_ar_bits_len,
+ output [2:0] io_slaves_2_ar_bits_size,
+ output [1:0] io_slaves_2_ar_bits_burst,
+ output io_slaves_2_ar_bits_lock,
+ output [3:0] io_slaves_2_ar_bits_cache,
+ output [2:0] io_slaves_2_ar_bits_prot,
+ output [3:0] io_slaves_2_ar_bits_qos,
+ output [3:0] io_slaves_2_ar_bits_region,
+ output [4:0] io_slaves_2_ar_bits_id,
+ output io_slaves_2_ar_bits_user,
+ output io_slaves_2_r_ready,
+ input io_slaves_2_r_valid,
+ input [1:0] io_slaves_2_r_bits_resp,
+ input [63:0] io_slaves_2_r_bits_data,
+ input io_slaves_2_r_bits_last,
+ input [4:0] io_slaves_2_r_bits_id,
+ input io_slaves_2_r_bits_user
+);
+ wire xbar_clk;
+ wire xbar_reset;
+ wire xbar_io_masters_0_aw_ready;
+ wire xbar_io_masters_0_aw_valid;
+ wire [31:0] xbar_io_masters_0_aw_bits_addr;
+ wire [7:0] xbar_io_masters_0_aw_bits_len;
+ wire [2:0] xbar_io_masters_0_aw_bits_size;
+ wire [1:0] xbar_io_masters_0_aw_bits_burst;
+ wire xbar_io_masters_0_aw_bits_lock;
+ wire [3:0] xbar_io_masters_0_aw_bits_cache;
+ wire [2:0] xbar_io_masters_0_aw_bits_prot;
+ wire [3:0] xbar_io_masters_0_aw_bits_qos;
+ wire [3:0] xbar_io_masters_0_aw_bits_region;
+ wire [4:0] xbar_io_masters_0_aw_bits_id;
+ wire xbar_io_masters_0_aw_bits_user;
+ wire xbar_io_masters_0_w_ready;
+ wire xbar_io_masters_0_w_valid;
+ wire [63:0] xbar_io_masters_0_w_bits_data;
+ wire xbar_io_masters_0_w_bits_last;
+ wire [7:0] xbar_io_masters_0_w_bits_strb;
+ wire xbar_io_masters_0_w_bits_user;
+ wire xbar_io_masters_0_b_ready;
+ wire xbar_io_masters_0_b_valid;
+ wire [1:0] xbar_io_masters_0_b_bits_resp;
+ wire [4:0] xbar_io_masters_0_b_bits_id;
+ wire xbar_io_masters_0_b_bits_user;
+ wire xbar_io_masters_0_ar_ready;
+ wire xbar_io_masters_0_ar_valid;
+ wire [31:0] xbar_io_masters_0_ar_bits_addr;
+ wire [7:0] xbar_io_masters_0_ar_bits_len;
+ wire [2:0] xbar_io_masters_0_ar_bits_size;
+ wire [1:0] xbar_io_masters_0_ar_bits_burst;
+ wire xbar_io_masters_0_ar_bits_lock;
+ wire [3:0] xbar_io_masters_0_ar_bits_cache;
+ wire [2:0] xbar_io_masters_0_ar_bits_prot;
+ wire [3:0] xbar_io_masters_0_ar_bits_qos;
+ wire [3:0] xbar_io_masters_0_ar_bits_region;
+ wire [4:0] xbar_io_masters_0_ar_bits_id;
+ wire xbar_io_masters_0_ar_bits_user;
+ wire xbar_io_masters_0_r_ready;
+ wire xbar_io_masters_0_r_valid;
+ wire [1:0] xbar_io_masters_0_r_bits_resp;
+ wire [63:0] xbar_io_masters_0_r_bits_data;
+ wire xbar_io_masters_0_r_bits_last;
+ wire [4:0] xbar_io_masters_0_r_bits_id;
+ wire xbar_io_masters_0_r_bits_user;
+ wire xbar_io_slaves_0_aw_ready;
+ wire xbar_io_slaves_0_aw_valid;
+ wire [31:0] xbar_io_slaves_0_aw_bits_addr;
+ wire [7:0] xbar_io_slaves_0_aw_bits_len;
+ wire [2:0] xbar_io_slaves_0_aw_bits_size;
+ wire [1:0] xbar_io_slaves_0_aw_bits_burst;
+ wire xbar_io_slaves_0_aw_bits_lock;
+ wire [3:0] xbar_io_slaves_0_aw_bits_cache;
+ wire [2:0] xbar_io_slaves_0_aw_bits_prot;
+ wire [3:0] xbar_io_slaves_0_aw_bits_qos;
+ wire [3:0] xbar_io_slaves_0_aw_bits_region;
+ wire [4:0] xbar_io_slaves_0_aw_bits_id;
+ wire xbar_io_slaves_0_aw_bits_user;
+ wire xbar_io_slaves_0_w_ready;
+ wire xbar_io_slaves_0_w_valid;
+ wire [63:0] xbar_io_slaves_0_w_bits_data;
+ wire xbar_io_slaves_0_w_bits_last;
+ wire [7:0] xbar_io_slaves_0_w_bits_strb;
+ wire xbar_io_slaves_0_w_bits_user;
+ wire xbar_io_slaves_0_b_ready;
+ wire xbar_io_slaves_0_b_valid;
+ wire [1:0] xbar_io_slaves_0_b_bits_resp;
+ wire [4:0] xbar_io_slaves_0_b_bits_id;
+ wire xbar_io_slaves_0_b_bits_user;
+ wire xbar_io_slaves_0_ar_ready;
+ wire xbar_io_slaves_0_ar_valid;
+ wire [31:0] xbar_io_slaves_0_ar_bits_addr;
+ wire [7:0] xbar_io_slaves_0_ar_bits_len;
+ wire [2:0] xbar_io_slaves_0_ar_bits_size;
+ wire [1:0] xbar_io_slaves_0_ar_bits_burst;
+ wire xbar_io_slaves_0_ar_bits_lock;
+ wire [3:0] xbar_io_slaves_0_ar_bits_cache;
+ wire [2:0] xbar_io_slaves_0_ar_bits_prot;
+ wire [3:0] xbar_io_slaves_0_ar_bits_qos;
+ wire [3:0] xbar_io_slaves_0_ar_bits_region;
+ wire [4:0] xbar_io_slaves_0_ar_bits_id;
+ wire xbar_io_slaves_0_ar_bits_user;
+ wire xbar_io_slaves_0_r_ready;
+ wire xbar_io_slaves_0_r_valid;
+ wire [1:0] xbar_io_slaves_0_r_bits_resp;
+ wire [63:0] xbar_io_slaves_0_r_bits_data;
+ wire xbar_io_slaves_0_r_bits_last;
+ wire [4:0] xbar_io_slaves_0_r_bits_id;
+ wire xbar_io_slaves_0_r_bits_user;
+ wire xbar_io_slaves_1_aw_ready;
+ wire xbar_io_slaves_1_aw_valid;
+ wire [31:0] xbar_io_slaves_1_aw_bits_addr;
+ wire [7:0] xbar_io_slaves_1_aw_bits_len;
+ wire [2:0] xbar_io_slaves_1_aw_bits_size;
+ wire [1:0] xbar_io_slaves_1_aw_bits_burst;
+ wire xbar_io_slaves_1_aw_bits_lock;
+ wire [3:0] xbar_io_slaves_1_aw_bits_cache;
+ wire [2:0] xbar_io_slaves_1_aw_bits_prot;
+ wire [3:0] xbar_io_slaves_1_aw_bits_qos;
+ wire [3:0] xbar_io_slaves_1_aw_bits_region;
+ wire [4:0] xbar_io_slaves_1_aw_bits_id;
+ wire xbar_io_slaves_1_aw_bits_user;
+ wire xbar_io_slaves_1_w_ready;
+ wire xbar_io_slaves_1_w_valid;
+ wire [63:0] xbar_io_slaves_1_w_bits_data;
+ wire xbar_io_slaves_1_w_bits_last;
+ wire [7:0] xbar_io_slaves_1_w_bits_strb;
+ wire xbar_io_slaves_1_w_bits_user;
+ wire xbar_io_slaves_1_b_ready;
+ wire xbar_io_slaves_1_b_valid;
+ wire [1:0] xbar_io_slaves_1_b_bits_resp;
+ wire [4:0] xbar_io_slaves_1_b_bits_id;
+ wire xbar_io_slaves_1_b_bits_user;
+ wire xbar_io_slaves_1_ar_ready;
+ wire xbar_io_slaves_1_ar_valid;
+ wire [31:0] xbar_io_slaves_1_ar_bits_addr;
+ wire [7:0] xbar_io_slaves_1_ar_bits_len;
+ wire [2:0] xbar_io_slaves_1_ar_bits_size;
+ wire [1:0] xbar_io_slaves_1_ar_bits_burst;
+ wire xbar_io_slaves_1_ar_bits_lock;
+ wire [3:0] xbar_io_slaves_1_ar_bits_cache;
+ wire [2:0] xbar_io_slaves_1_ar_bits_prot;
+ wire [3:0] xbar_io_slaves_1_ar_bits_qos;
+ wire [3:0] xbar_io_slaves_1_ar_bits_region;
+ wire [4:0] xbar_io_slaves_1_ar_bits_id;
+ wire xbar_io_slaves_1_ar_bits_user;
+ wire xbar_io_slaves_1_r_ready;
+ wire xbar_io_slaves_1_r_valid;
+ wire [1:0] xbar_io_slaves_1_r_bits_resp;
+ wire [63:0] xbar_io_slaves_1_r_bits_data;
+ wire xbar_io_slaves_1_r_bits_last;
+ wire [4:0] xbar_io_slaves_1_r_bits_id;
+ wire xbar_io_slaves_1_r_bits_user;
+ wire xbar_io_slaves_2_aw_ready;
+ wire xbar_io_slaves_2_aw_valid;
+ wire [31:0] xbar_io_slaves_2_aw_bits_addr;
+ wire [7:0] xbar_io_slaves_2_aw_bits_len;
+ wire [2:0] xbar_io_slaves_2_aw_bits_size;
+ wire [1:0] xbar_io_slaves_2_aw_bits_burst;
+ wire xbar_io_slaves_2_aw_bits_lock;
+ wire [3:0] xbar_io_slaves_2_aw_bits_cache;
+ wire [2:0] xbar_io_slaves_2_aw_bits_prot;
+ wire [3:0] xbar_io_slaves_2_aw_bits_qos;
+ wire [3:0] xbar_io_slaves_2_aw_bits_region;
+ wire [4:0] xbar_io_slaves_2_aw_bits_id;
+ wire xbar_io_slaves_2_aw_bits_user;
+ wire xbar_io_slaves_2_w_ready;
+ wire xbar_io_slaves_2_w_valid;
+ wire [63:0] xbar_io_slaves_2_w_bits_data;
+ wire xbar_io_slaves_2_w_bits_last;
+ wire [7:0] xbar_io_slaves_2_w_bits_strb;
+ wire xbar_io_slaves_2_w_bits_user;
+ wire xbar_io_slaves_2_b_ready;
+ wire xbar_io_slaves_2_b_valid;
+ wire [1:0] xbar_io_slaves_2_b_bits_resp;
+ wire [4:0] xbar_io_slaves_2_b_bits_id;
+ wire xbar_io_slaves_2_b_bits_user;
+ wire xbar_io_slaves_2_ar_ready;
+ wire xbar_io_slaves_2_ar_valid;
+ wire [31:0] xbar_io_slaves_2_ar_bits_addr;
+ wire [7:0] xbar_io_slaves_2_ar_bits_len;
+ wire [2:0] xbar_io_slaves_2_ar_bits_size;
+ wire [1:0] xbar_io_slaves_2_ar_bits_burst;
+ wire xbar_io_slaves_2_ar_bits_lock;
+ wire [3:0] xbar_io_slaves_2_ar_bits_cache;
+ wire [2:0] xbar_io_slaves_2_ar_bits_prot;
+ wire [3:0] xbar_io_slaves_2_ar_bits_qos;
+ wire [3:0] xbar_io_slaves_2_ar_bits_region;
+ wire [4:0] xbar_io_slaves_2_ar_bits_id;
+ wire xbar_io_slaves_2_ar_bits_user;
+ wire xbar_io_slaves_2_r_ready;
+ wire xbar_io_slaves_2_r_valid;
+ wire [1:0] xbar_io_slaves_2_r_bits_resp;
+ wire [63:0] xbar_io_slaves_2_r_bits_data;
+ wire xbar_io_slaves_2_r_bits_last;
+ wire [4:0] xbar_io_slaves_2_r_bits_id;
+ wire xbar_io_slaves_2_r_bits_user;
+ NastiCrossbar_57 xbar (
+ .clk(xbar_clk),
+ .reset(xbar_reset),
+ .io_masters_0_aw_ready(xbar_io_masters_0_aw_ready),
+ .io_masters_0_aw_valid(xbar_io_masters_0_aw_valid),
+ .io_masters_0_aw_bits_addr(xbar_io_masters_0_aw_bits_addr),
+ .io_masters_0_aw_bits_len(xbar_io_masters_0_aw_bits_len),
+ .io_masters_0_aw_bits_size(xbar_io_masters_0_aw_bits_size),
+ .io_masters_0_aw_bits_burst(xbar_io_masters_0_aw_bits_burst),
+ .io_masters_0_aw_bits_lock(xbar_io_masters_0_aw_bits_lock),
+ .io_masters_0_aw_bits_cache(xbar_io_masters_0_aw_bits_cache),
+ .io_masters_0_aw_bits_prot(xbar_io_masters_0_aw_bits_prot),
+ .io_masters_0_aw_bits_qos(xbar_io_masters_0_aw_bits_qos),
+ .io_masters_0_aw_bits_region(xbar_io_masters_0_aw_bits_region),
+ .io_masters_0_aw_bits_id(xbar_io_masters_0_aw_bits_id),
+ .io_masters_0_aw_bits_user(xbar_io_masters_0_aw_bits_user),
+ .io_masters_0_w_ready(xbar_io_masters_0_w_ready),
+ .io_masters_0_w_valid(xbar_io_masters_0_w_valid),
+ .io_masters_0_w_bits_data(xbar_io_masters_0_w_bits_data),
+ .io_masters_0_w_bits_last(xbar_io_masters_0_w_bits_last),
+ .io_masters_0_w_bits_strb(xbar_io_masters_0_w_bits_strb),
+ .io_masters_0_w_bits_user(xbar_io_masters_0_w_bits_user),
+ .io_masters_0_b_ready(xbar_io_masters_0_b_ready),
+ .io_masters_0_b_valid(xbar_io_masters_0_b_valid),
+ .io_masters_0_b_bits_resp(xbar_io_masters_0_b_bits_resp),
+ .io_masters_0_b_bits_id(xbar_io_masters_0_b_bits_id),
+ .io_masters_0_b_bits_user(xbar_io_masters_0_b_bits_user),
+ .io_masters_0_ar_ready(xbar_io_masters_0_ar_ready),
+ .io_masters_0_ar_valid(xbar_io_masters_0_ar_valid),
+ .io_masters_0_ar_bits_addr(xbar_io_masters_0_ar_bits_addr),
+ .io_masters_0_ar_bits_len(xbar_io_masters_0_ar_bits_len),
+ .io_masters_0_ar_bits_size(xbar_io_masters_0_ar_bits_size),
+ .io_masters_0_ar_bits_burst(xbar_io_masters_0_ar_bits_burst),
+ .io_masters_0_ar_bits_lock(xbar_io_masters_0_ar_bits_lock),
+ .io_masters_0_ar_bits_cache(xbar_io_masters_0_ar_bits_cache),
+ .io_masters_0_ar_bits_prot(xbar_io_masters_0_ar_bits_prot),
+ .io_masters_0_ar_bits_qos(xbar_io_masters_0_ar_bits_qos),
+ .io_masters_0_ar_bits_region(xbar_io_masters_0_ar_bits_region),
+ .io_masters_0_ar_bits_id(xbar_io_masters_0_ar_bits_id),
+ .io_masters_0_ar_bits_user(xbar_io_masters_0_ar_bits_user),
+ .io_masters_0_r_ready(xbar_io_masters_0_r_ready),
+ .io_masters_0_r_valid(xbar_io_masters_0_r_valid),
+ .io_masters_0_r_bits_resp(xbar_io_masters_0_r_bits_resp),
+ .io_masters_0_r_bits_data(xbar_io_masters_0_r_bits_data),
+ .io_masters_0_r_bits_last(xbar_io_masters_0_r_bits_last),
+ .io_masters_0_r_bits_id(xbar_io_masters_0_r_bits_id),
+ .io_masters_0_r_bits_user(xbar_io_masters_0_r_bits_user),
+ .io_slaves_0_aw_ready(xbar_io_slaves_0_aw_ready),
+ .io_slaves_0_aw_valid(xbar_io_slaves_0_aw_valid),
+ .io_slaves_0_aw_bits_addr(xbar_io_slaves_0_aw_bits_addr),
+ .io_slaves_0_aw_bits_len(xbar_io_slaves_0_aw_bits_len),
+ .io_slaves_0_aw_bits_size(xbar_io_slaves_0_aw_bits_size),
+ .io_slaves_0_aw_bits_burst(xbar_io_slaves_0_aw_bits_burst),
+ .io_slaves_0_aw_bits_lock(xbar_io_slaves_0_aw_bits_lock),
+ .io_slaves_0_aw_bits_cache(xbar_io_slaves_0_aw_bits_cache),
+ .io_slaves_0_aw_bits_prot(xbar_io_slaves_0_aw_bits_prot),
+ .io_slaves_0_aw_bits_qos(xbar_io_slaves_0_aw_bits_qos),
+ .io_slaves_0_aw_bits_region(xbar_io_slaves_0_aw_bits_region),
+ .io_slaves_0_aw_bits_id(xbar_io_slaves_0_aw_bits_id),
+ .io_slaves_0_aw_bits_user(xbar_io_slaves_0_aw_bits_user),
+ .io_slaves_0_w_ready(xbar_io_slaves_0_w_ready),
+ .io_slaves_0_w_valid(xbar_io_slaves_0_w_valid),
+ .io_slaves_0_w_bits_data(xbar_io_slaves_0_w_bits_data),
+ .io_slaves_0_w_bits_last(xbar_io_slaves_0_w_bits_last),
+ .io_slaves_0_w_bits_strb(xbar_io_slaves_0_w_bits_strb),
+ .io_slaves_0_w_bits_user(xbar_io_slaves_0_w_bits_user),
+ .io_slaves_0_b_ready(xbar_io_slaves_0_b_ready),
+ .io_slaves_0_b_valid(xbar_io_slaves_0_b_valid),
+ .io_slaves_0_b_bits_resp(xbar_io_slaves_0_b_bits_resp),
+ .io_slaves_0_b_bits_id(xbar_io_slaves_0_b_bits_id),
+ .io_slaves_0_b_bits_user(xbar_io_slaves_0_b_bits_user),
+ .io_slaves_0_ar_ready(xbar_io_slaves_0_ar_ready),
+ .io_slaves_0_ar_valid(xbar_io_slaves_0_ar_valid),
+ .io_slaves_0_ar_bits_addr(xbar_io_slaves_0_ar_bits_addr),
+ .io_slaves_0_ar_bits_len(xbar_io_slaves_0_ar_bits_len),
+ .io_slaves_0_ar_bits_size(xbar_io_slaves_0_ar_bits_size),
+ .io_slaves_0_ar_bits_burst(xbar_io_slaves_0_ar_bits_burst),
+ .io_slaves_0_ar_bits_lock(xbar_io_slaves_0_ar_bits_lock),
+ .io_slaves_0_ar_bits_cache(xbar_io_slaves_0_ar_bits_cache),
+ .io_slaves_0_ar_bits_prot(xbar_io_slaves_0_ar_bits_prot),
+ .io_slaves_0_ar_bits_qos(xbar_io_slaves_0_ar_bits_qos),
+ .io_slaves_0_ar_bits_region(xbar_io_slaves_0_ar_bits_region),
+ .io_slaves_0_ar_bits_id(xbar_io_slaves_0_ar_bits_id),
+ .io_slaves_0_ar_bits_user(xbar_io_slaves_0_ar_bits_user),
+ .io_slaves_0_r_ready(xbar_io_slaves_0_r_ready),
+ .io_slaves_0_r_valid(xbar_io_slaves_0_r_valid),
+ .io_slaves_0_r_bits_resp(xbar_io_slaves_0_r_bits_resp),
+ .io_slaves_0_r_bits_data(xbar_io_slaves_0_r_bits_data),
+ .io_slaves_0_r_bits_last(xbar_io_slaves_0_r_bits_last),
+ .io_slaves_0_r_bits_id(xbar_io_slaves_0_r_bits_id),
+ .io_slaves_0_r_bits_user(xbar_io_slaves_0_r_bits_user),
+ .io_slaves_1_aw_ready(xbar_io_slaves_1_aw_ready),
+ .io_slaves_1_aw_valid(xbar_io_slaves_1_aw_valid),
+ .io_slaves_1_aw_bits_addr(xbar_io_slaves_1_aw_bits_addr),
+ .io_slaves_1_aw_bits_len(xbar_io_slaves_1_aw_bits_len),
+ .io_slaves_1_aw_bits_size(xbar_io_slaves_1_aw_bits_size),
+ .io_slaves_1_aw_bits_burst(xbar_io_slaves_1_aw_bits_burst),
+ .io_slaves_1_aw_bits_lock(xbar_io_slaves_1_aw_bits_lock),
+ .io_slaves_1_aw_bits_cache(xbar_io_slaves_1_aw_bits_cache),
+ .io_slaves_1_aw_bits_prot(xbar_io_slaves_1_aw_bits_prot),
+ .io_slaves_1_aw_bits_qos(xbar_io_slaves_1_aw_bits_qos),
+ .io_slaves_1_aw_bits_region(xbar_io_slaves_1_aw_bits_region),
+ .io_slaves_1_aw_bits_id(xbar_io_slaves_1_aw_bits_id),
+ .io_slaves_1_aw_bits_user(xbar_io_slaves_1_aw_bits_user),
+ .io_slaves_1_w_ready(xbar_io_slaves_1_w_ready),
+ .io_slaves_1_w_valid(xbar_io_slaves_1_w_valid),
+ .io_slaves_1_w_bits_data(xbar_io_slaves_1_w_bits_data),
+ .io_slaves_1_w_bits_last(xbar_io_slaves_1_w_bits_last),
+ .io_slaves_1_w_bits_strb(xbar_io_slaves_1_w_bits_strb),
+ .io_slaves_1_w_bits_user(xbar_io_slaves_1_w_bits_user),
+ .io_slaves_1_b_ready(xbar_io_slaves_1_b_ready),
+ .io_slaves_1_b_valid(xbar_io_slaves_1_b_valid),
+ .io_slaves_1_b_bits_resp(xbar_io_slaves_1_b_bits_resp),
+ .io_slaves_1_b_bits_id(xbar_io_slaves_1_b_bits_id),
+ .io_slaves_1_b_bits_user(xbar_io_slaves_1_b_bits_user),
+ .io_slaves_1_ar_ready(xbar_io_slaves_1_ar_ready),
+ .io_slaves_1_ar_valid(xbar_io_slaves_1_ar_valid),
+ .io_slaves_1_ar_bits_addr(xbar_io_slaves_1_ar_bits_addr),
+ .io_slaves_1_ar_bits_len(xbar_io_slaves_1_ar_bits_len),
+ .io_slaves_1_ar_bits_size(xbar_io_slaves_1_ar_bits_size),
+ .io_slaves_1_ar_bits_burst(xbar_io_slaves_1_ar_bits_burst),
+ .io_slaves_1_ar_bits_lock(xbar_io_slaves_1_ar_bits_lock),
+ .io_slaves_1_ar_bits_cache(xbar_io_slaves_1_ar_bits_cache),
+ .io_slaves_1_ar_bits_prot(xbar_io_slaves_1_ar_bits_prot),
+ .io_slaves_1_ar_bits_qos(xbar_io_slaves_1_ar_bits_qos),
+ .io_slaves_1_ar_bits_region(xbar_io_slaves_1_ar_bits_region),
+ .io_slaves_1_ar_bits_id(xbar_io_slaves_1_ar_bits_id),
+ .io_slaves_1_ar_bits_user(xbar_io_slaves_1_ar_bits_user),
+ .io_slaves_1_r_ready(xbar_io_slaves_1_r_ready),
+ .io_slaves_1_r_valid(xbar_io_slaves_1_r_valid),
+ .io_slaves_1_r_bits_resp(xbar_io_slaves_1_r_bits_resp),
+ .io_slaves_1_r_bits_data(xbar_io_slaves_1_r_bits_data),
+ .io_slaves_1_r_bits_last(xbar_io_slaves_1_r_bits_last),
+ .io_slaves_1_r_bits_id(xbar_io_slaves_1_r_bits_id),
+ .io_slaves_1_r_bits_user(xbar_io_slaves_1_r_bits_user),
+ .io_slaves_2_aw_ready(xbar_io_slaves_2_aw_ready),
+ .io_slaves_2_aw_valid(xbar_io_slaves_2_aw_valid),
+ .io_slaves_2_aw_bits_addr(xbar_io_slaves_2_aw_bits_addr),
+ .io_slaves_2_aw_bits_len(xbar_io_slaves_2_aw_bits_len),
+ .io_slaves_2_aw_bits_size(xbar_io_slaves_2_aw_bits_size),
+ .io_slaves_2_aw_bits_burst(xbar_io_slaves_2_aw_bits_burst),
+ .io_slaves_2_aw_bits_lock(xbar_io_slaves_2_aw_bits_lock),
+ .io_slaves_2_aw_bits_cache(xbar_io_slaves_2_aw_bits_cache),
+ .io_slaves_2_aw_bits_prot(xbar_io_slaves_2_aw_bits_prot),
+ .io_slaves_2_aw_bits_qos(xbar_io_slaves_2_aw_bits_qos),
+ .io_slaves_2_aw_bits_region(xbar_io_slaves_2_aw_bits_region),
+ .io_slaves_2_aw_bits_id(xbar_io_slaves_2_aw_bits_id),
+ .io_slaves_2_aw_bits_user(xbar_io_slaves_2_aw_bits_user),
+ .io_slaves_2_w_ready(xbar_io_slaves_2_w_ready),
+ .io_slaves_2_w_valid(xbar_io_slaves_2_w_valid),
+ .io_slaves_2_w_bits_data(xbar_io_slaves_2_w_bits_data),
+ .io_slaves_2_w_bits_last(xbar_io_slaves_2_w_bits_last),
+ .io_slaves_2_w_bits_strb(xbar_io_slaves_2_w_bits_strb),
+ .io_slaves_2_w_bits_user(xbar_io_slaves_2_w_bits_user),
+ .io_slaves_2_b_ready(xbar_io_slaves_2_b_ready),
+ .io_slaves_2_b_valid(xbar_io_slaves_2_b_valid),
+ .io_slaves_2_b_bits_resp(xbar_io_slaves_2_b_bits_resp),
+ .io_slaves_2_b_bits_id(xbar_io_slaves_2_b_bits_id),
+ .io_slaves_2_b_bits_user(xbar_io_slaves_2_b_bits_user),
+ .io_slaves_2_ar_ready(xbar_io_slaves_2_ar_ready),
+ .io_slaves_2_ar_valid(xbar_io_slaves_2_ar_valid),
+ .io_slaves_2_ar_bits_addr(xbar_io_slaves_2_ar_bits_addr),
+ .io_slaves_2_ar_bits_len(xbar_io_slaves_2_ar_bits_len),
+ .io_slaves_2_ar_bits_size(xbar_io_slaves_2_ar_bits_size),
+ .io_slaves_2_ar_bits_burst(xbar_io_slaves_2_ar_bits_burst),
+ .io_slaves_2_ar_bits_lock(xbar_io_slaves_2_ar_bits_lock),
+ .io_slaves_2_ar_bits_cache(xbar_io_slaves_2_ar_bits_cache),
+ .io_slaves_2_ar_bits_prot(xbar_io_slaves_2_ar_bits_prot),
+ .io_slaves_2_ar_bits_qos(xbar_io_slaves_2_ar_bits_qos),
+ .io_slaves_2_ar_bits_region(xbar_io_slaves_2_ar_bits_region),
+ .io_slaves_2_ar_bits_id(xbar_io_slaves_2_ar_bits_id),
+ .io_slaves_2_ar_bits_user(xbar_io_slaves_2_ar_bits_user),
+ .io_slaves_2_r_ready(xbar_io_slaves_2_r_ready),
+ .io_slaves_2_r_valid(xbar_io_slaves_2_r_valid),
+ .io_slaves_2_r_bits_resp(xbar_io_slaves_2_r_bits_resp),
+ .io_slaves_2_r_bits_data(xbar_io_slaves_2_r_bits_data),
+ .io_slaves_2_r_bits_last(xbar_io_slaves_2_r_bits_last),
+ .io_slaves_2_r_bits_id(xbar_io_slaves_2_r_bits_id),
+ .io_slaves_2_r_bits_user(xbar_io_slaves_2_r_bits_user)
+ );
+ assign io_masters_0_aw_ready = xbar_io_masters_0_aw_ready;
+ assign io_masters_0_w_ready = xbar_io_masters_0_w_ready;
+ assign io_masters_0_b_valid = xbar_io_masters_0_b_valid;
+ assign io_masters_0_b_bits_resp = xbar_io_masters_0_b_bits_resp;
+ assign io_masters_0_b_bits_id = xbar_io_masters_0_b_bits_id;
+ assign io_masters_0_b_bits_user = xbar_io_masters_0_b_bits_user;
+ assign io_masters_0_ar_ready = xbar_io_masters_0_ar_ready;
+ assign io_masters_0_r_valid = xbar_io_masters_0_r_valid;
+ assign io_masters_0_r_bits_resp = xbar_io_masters_0_r_bits_resp;
+ assign io_masters_0_r_bits_data = xbar_io_masters_0_r_bits_data;
+ assign io_masters_0_r_bits_last = xbar_io_masters_0_r_bits_last;
+ assign io_masters_0_r_bits_id = xbar_io_masters_0_r_bits_id;
+ assign io_masters_0_r_bits_user = xbar_io_masters_0_r_bits_user;
+ assign io_slaves_0_aw_valid = xbar_io_slaves_0_aw_valid;
+ assign io_slaves_0_aw_bits_addr = xbar_io_slaves_0_aw_bits_addr;
+ assign io_slaves_0_aw_bits_len = xbar_io_slaves_0_aw_bits_len;
+ assign io_slaves_0_aw_bits_size = xbar_io_slaves_0_aw_bits_size;
+ assign io_slaves_0_aw_bits_burst = xbar_io_slaves_0_aw_bits_burst;
+ assign io_slaves_0_aw_bits_lock = xbar_io_slaves_0_aw_bits_lock;
+ assign io_slaves_0_aw_bits_cache = xbar_io_slaves_0_aw_bits_cache;
+ assign io_slaves_0_aw_bits_prot = xbar_io_slaves_0_aw_bits_prot;
+ assign io_slaves_0_aw_bits_qos = xbar_io_slaves_0_aw_bits_qos;
+ assign io_slaves_0_aw_bits_region = xbar_io_slaves_0_aw_bits_region;
+ assign io_slaves_0_aw_bits_id = xbar_io_slaves_0_aw_bits_id;
+ assign io_slaves_0_aw_bits_user = xbar_io_slaves_0_aw_bits_user;
+ assign io_slaves_0_w_valid = xbar_io_slaves_0_w_valid;
+ assign io_slaves_0_w_bits_data = xbar_io_slaves_0_w_bits_data;
+ assign io_slaves_0_w_bits_last = xbar_io_slaves_0_w_bits_last;
+ assign io_slaves_0_w_bits_strb = xbar_io_slaves_0_w_bits_strb;
+ assign io_slaves_0_w_bits_user = xbar_io_slaves_0_w_bits_user;
+ assign io_slaves_0_b_ready = xbar_io_slaves_0_b_ready;
+ assign io_slaves_0_ar_valid = xbar_io_slaves_0_ar_valid;
+ assign io_slaves_0_ar_bits_addr = xbar_io_slaves_0_ar_bits_addr;
+ assign io_slaves_0_ar_bits_len = xbar_io_slaves_0_ar_bits_len;
+ assign io_slaves_0_ar_bits_size = xbar_io_slaves_0_ar_bits_size;
+ assign io_slaves_0_ar_bits_burst = xbar_io_slaves_0_ar_bits_burst;
+ assign io_slaves_0_ar_bits_lock = xbar_io_slaves_0_ar_bits_lock;
+ assign io_slaves_0_ar_bits_cache = xbar_io_slaves_0_ar_bits_cache;
+ assign io_slaves_0_ar_bits_prot = xbar_io_slaves_0_ar_bits_prot;
+ assign io_slaves_0_ar_bits_qos = xbar_io_slaves_0_ar_bits_qos;
+ assign io_slaves_0_ar_bits_region = xbar_io_slaves_0_ar_bits_region;
+ assign io_slaves_0_ar_bits_id = xbar_io_slaves_0_ar_bits_id;
+ assign io_slaves_0_ar_bits_user = xbar_io_slaves_0_ar_bits_user;
+ assign io_slaves_0_r_ready = xbar_io_slaves_0_r_ready;
+ assign io_slaves_1_aw_valid = xbar_io_slaves_1_aw_valid;
+ assign io_slaves_1_aw_bits_addr = xbar_io_slaves_1_aw_bits_addr;
+ assign io_slaves_1_aw_bits_len = xbar_io_slaves_1_aw_bits_len;
+ assign io_slaves_1_aw_bits_size = xbar_io_slaves_1_aw_bits_size;
+ assign io_slaves_1_aw_bits_burst = xbar_io_slaves_1_aw_bits_burst;
+ assign io_slaves_1_aw_bits_lock = xbar_io_slaves_1_aw_bits_lock;
+ assign io_slaves_1_aw_bits_cache = xbar_io_slaves_1_aw_bits_cache;
+ assign io_slaves_1_aw_bits_prot = xbar_io_slaves_1_aw_bits_prot;
+ assign io_slaves_1_aw_bits_qos = xbar_io_slaves_1_aw_bits_qos;
+ assign io_slaves_1_aw_bits_region = xbar_io_slaves_1_aw_bits_region;
+ assign io_slaves_1_aw_bits_id = xbar_io_slaves_1_aw_bits_id;
+ assign io_slaves_1_aw_bits_user = xbar_io_slaves_1_aw_bits_user;
+ assign io_slaves_1_w_valid = xbar_io_slaves_1_w_valid;
+ assign io_slaves_1_w_bits_data = xbar_io_slaves_1_w_bits_data;
+ assign io_slaves_1_w_bits_last = xbar_io_slaves_1_w_bits_last;
+ assign io_slaves_1_w_bits_strb = xbar_io_slaves_1_w_bits_strb;
+ assign io_slaves_1_w_bits_user = xbar_io_slaves_1_w_bits_user;
+ assign io_slaves_1_b_ready = xbar_io_slaves_1_b_ready;
+ assign io_slaves_1_ar_valid = xbar_io_slaves_1_ar_valid;
+ assign io_slaves_1_ar_bits_addr = xbar_io_slaves_1_ar_bits_addr;
+ assign io_slaves_1_ar_bits_len = xbar_io_slaves_1_ar_bits_len;
+ assign io_slaves_1_ar_bits_size = xbar_io_slaves_1_ar_bits_size;
+ assign io_slaves_1_ar_bits_burst = xbar_io_slaves_1_ar_bits_burst;
+ assign io_slaves_1_ar_bits_lock = xbar_io_slaves_1_ar_bits_lock;
+ assign io_slaves_1_ar_bits_cache = xbar_io_slaves_1_ar_bits_cache;
+ assign io_slaves_1_ar_bits_prot = xbar_io_slaves_1_ar_bits_prot;
+ assign io_slaves_1_ar_bits_qos = xbar_io_slaves_1_ar_bits_qos;
+ assign io_slaves_1_ar_bits_region = xbar_io_slaves_1_ar_bits_region;
+ assign io_slaves_1_ar_bits_id = xbar_io_slaves_1_ar_bits_id;
+ assign io_slaves_1_ar_bits_user = xbar_io_slaves_1_ar_bits_user;
+ assign io_slaves_1_r_ready = xbar_io_slaves_1_r_ready;
+ assign io_slaves_2_aw_valid = xbar_io_slaves_2_aw_valid;
+ assign io_slaves_2_aw_bits_addr = xbar_io_slaves_2_aw_bits_addr;
+ assign io_slaves_2_aw_bits_len = xbar_io_slaves_2_aw_bits_len;
+ assign io_slaves_2_aw_bits_size = xbar_io_slaves_2_aw_bits_size;
+ assign io_slaves_2_aw_bits_burst = xbar_io_slaves_2_aw_bits_burst;
+ assign io_slaves_2_aw_bits_lock = xbar_io_slaves_2_aw_bits_lock;
+ assign io_slaves_2_aw_bits_cache = xbar_io_slaves_2_aw_bits_cache;
+ assign io_slaves_2_aw_bits_prot = xbar_io_slaves_2_aw_bits_prot;
+ assign io_slaves_2_aw_bits_qos = xbar_io_slaves_2_aw_bits_qos;
+ assign io_slaves_2_aw_bits_region = xbar_io_slaves_2_aw_bits_region;
+ assign io_slaves_2_aw_bits_id = xbar_io_slaves_2_aw_bits_id;
+ assign io_slaves_2_aw_bits_user = xbar_io_slaves_2_aw_bits_user;
+ assign io_slaves_2_w_valid = xbar_io_slaves_2_w_valid;
+ assign io_slaves_2_w_bits_data = xbar_io_slaves_2_w_bits_data;
+ assign io_slaves_2_w_bits_last = xbar_io_slaves_2_w_bits_last;
+ assign io_slaves_2_w_bits_strb = xbar_io_slaves_2_w_bits_strb;
+ assign io_slaves_2_w_bits_user = xbar_io_slaves_2_w_bits_user;
+ assign io_slaves_2_b_ready = xbar_io_slaves_2_b_ready;
+ assign io_slaves_2_ar_valid = xbar_io_slaves_2_ar_valid;
+ assign io_slaves_2_ar_bits_addr = xbar_io_slaves_2_ar_bits_addr;
+ assign io_slaves_2_ar_bits_len = xbar_io_slaves_2_ar_bits_len;
+ assign io_slaves_2_ar_bits_size = xbar_io_slaves_2_ar_bits_size;
+ assign io_slaves_2_ar_bits_burst = xbar_io_slaves_2_ar_bits_burst;
+ assign io_slaves_2_ar_bits_lock = xbar_io_slaves_2_ar_bits_lock;
+ assign io_slaves_2_ar_bits_cache = xbar_io_slaves_2_ar_bits_cache;
+ assign io_slaves_2_ar_bits_prot = xbar_io_slaves_2_ar_bits_prot;
+ assign io_slaves_2_ar_bits_qos = xbar_io_slaves_2_ar_bits_qos;
+ assign io_slaves_2_ar_bits_region = xbar_io_slaves_2_ar_bits_region;
+ assign io_slaves_2_ar_bits_id = xbar_io_slaves_2_ar_bits_id;
+ assign io_slaves_2_ar_bits_user = xbar_io_slaves_2_ar_bits_user;
+ assign io_slaves_2_r_ready = xbar_io_slaves_2_r_ready;
+ assign xbar_clk = clk;
+ assign xbar_reset = reset;
+ assign xbar_io_masters_0_aw_valid = io_masters_0_aw_valid;
+ assign xbar_io_masters_0_aw_bits_addr = io_masters_0_aw_bits_addr;
+ assign xbar_io_masters_0_aw_bits_len = io_masters_0_aw_bits_len;
+ assign xbar_io_masters_0_aw_bits_size = io_masters_0_aw_bits_size;
+ assign xbar_io_masters_0_aw_bits_burst = io_masters_0_aw_bits_burst;
+ assign xbar_io_masters_0_aw_bits_lock = io_masters_0_aw_bits_lock;
+ assign xbar_io_masters_0_aw_bits_cache = io_masters_0_aw_bits_cache;
+ assign xbar_io_masters_0_aw_bits_prot = io_masters_0_aw_bits_prot;
+ assign xbar_io_masters_0_aw_bits_qos = io_masters_0_aw_bits_qos;
+ assign xbar_io_masters_0_aw_bits_region = io_masters_0_aw_bits_region;
+ assign xbar_io_masters_0_aw_bits_id = io_masters_0_aw_bits_id;
+ assign xbar_io_masters_0_aw_bits_user = io_masters_0_aw_bits_user;
+ assign xbar_io_masters_0_w_valid = io_masters_0_w_valid;
+ assign xbar_io_masters_0_w_bits_data = io_masters_0_w_bits_data;
+ assign xbar_io_masters_0_w_bits_last = io_masters_0_w_bits_last;
+ assign xbar_io_masters_0_w_bits_strb = io_masters_0_w_bits_strb;
+ assign xbar_io_masters_0_w_bits_user = io_masters_0_w_bits_user;
+ assign xbar_io_masters_0_b_ready = io_masters_0_b_ready;
+ assign xbar_io_masters_0_ar_valid = io_masters_0_ar_valid;
+ assign xbar_io_masters_0_ar_bits_addr = io_masters_0_ar_bits_addr;
+ assign xbar_io_masters_0_ar_bits_len = io_masters_0_ar_bits_len;
+ assign xbar_io_masters_0_ar_bits_size = io_masters_0_ar_bits_size;
+ assign xbar_io_masters_0_ar_bits_burst = io_masters_0_ar_bits_burst;
+ assign xbar_io_masters_0_ar_bits_lock = io_masters_0_ar_bits_lock;
+ assign xbar_io_masters_0_ar_bits_cache = io_masters_0_ar_bits_cache;
+ assign xbar_io_masters_0_ar_bits_prot = io_masters_0_ar_bits_prot;
+ assign xbar_io_masters_0_ar_bits_qos = io_masters_0_ar_bits_qos;
+ assign xbar_io_masters_0_ar_bits_region = io_masters_0_ar_bits_region;
+ assign xbar_io_masters_0_ar_bits_id = io_masters_0_ar_bits_id;
+ assign xbar_io_masters_0_ar_bits_user = io_masters_0_ar_bits_user;
+ assign xbar_io_masters_0_r_ready = io_masters_0_r_ready;
+ assign xbar_io_slaves_0_aw_ready = io_slaves_0_aw_ready;
+ assign xbar_io_slaves_0_w_ready = io_slaves_0_w_ready;
+ assign xbar_io_slaves_0_b_valid = io_slaves_0_b_valid;
+ assign xbar_io_slaves_0_b_bits_resp = io_slaves_0_b_bits_resp;
+ assign xbar_io_slaves_0_b_bits_id = io_slaves_0_b_bits_id;
+ assign xbar_io_slaves_0_b_bits_user = io_slaves_0_b_bits_user;
+ assign xbar_io_slaves_0_ar_ready = io_slaves_0_ar_ready;
+ assign xbar_io_slaves_0_r_valid = io_slaves_0_r_valid;
+ assign xbar_io_slaves_0_r_bits_resp = io_slaves_0_r_bits_resp;
+ assign xbar_io_slaves_0_r_bits_data = io_slaves_0_r_bits_data;
+ assign xbar_io_slaves_0_r_bits_last = io_slaves_0_r_bits_last;
+ assign xbar_io_slaves_0_r_bits_id = io_slaves_0_r_bits_id;
+ assign xbar_io_slaves_0_r_bits_user = io_slaves_0_r_bits_user;
+ assign xbar_io_slaves_1_aw_ready = io_slaves_1_aw_ready;
+ assign xbar_io_slaves_1_w_ready = io_slaves_1_w_ready;
+ assign xbar_io_slaves_1_b_valid = io_slaves_1_b_valid;
+ assign xbar_io_slaves_1_b_bits_resp = io_slaves_1_b_bits_resp;
+ assign xbar_io_slaves_1_b_bits_id = io_slaves_1_b_bits_id;
+ assign xbar_io_slaves_1_b_bits_user = io_slaves_1_b_bits_user;
+ assign xbar_io_slaves_1_ar_ready = io_slaves_1_ar_ready;
+ assign xbar_io_slaves_1_r_valid = io_slaves_1_r_valid;
+ assign xbar_io_slaves_1_r_bits_resp = io_slaves_1_r_bits_resp;
+ assign xbar_io_slaves_1_r_bits_data = io_slaves_1_r_bits_data;
+ assign xbar_io_slaves_1_r_bits_last = io_slaves_1_r_bits_last;
+ assign xbar_io_slaves_1_r_bits_id = io_slaves_1_r_bits_id;
+ assign xbar_io_slaves_1_r_bits_user = io_slaves_1_r_bits_user;
+ assign xbar_io_slaves_2_aw_ready = io_slaves_2_aw_ready;
+ assign xbar_io_slaves_2_w_ready = io_slaves_2_w_ready;
+ assign xbar_io_slaves_2_b_valid = io_slaves_2_b_valid;
+ assign xbar_io_slaves_2_b_bits_resp = io_slaves_2_b_bits_resp;
+ assign xbar_io_slaves_2_b_bits_id = io_slaves_2_b_bits_id;
+ assign xbar_io_slaves_2_b_bits_user = io_slaves_2_b_bits_user;
+ assign xbar_io_slaves_2_ar_ready = io_slaves_2_ar_ready;
+ assign xbar_io_slaves_2_r_valid = io_slaves_2_r_valid;
+ assign xbar_io_slaves_2_r_bits_resp = io_slaves_2_r_bits_resp;
+ assign xbar_io_slaves_2_r_bits_data = io_slaves_2_r_bits_data;
+ assign xbar_io_slaves_2_r_bits_last = io_slaves_2_r_bits_last;
+ assign xbar_io_slaves_2_r_bits_id = io_slaves_2_r_bits_id;
+ assign xbar_io_slaves_2_r_bits_user = io_slaves_2_r_bits_user;
+endmodule
+module NastiRecursiveInterconnect(
+ input clk,
+ input reset,
+ output io_masters_0_aw_ready,
+ input io_masters_0_aw_valid,
+ input [31:0] io_masters_0_aw_bits_addr,
+ input [7:0] io_masters_0_aw_bits_len,
+ input [2:0] io_masters_0_aw_bits_size,
+ input [1:0] io_masters_0_aw_bits_burst,
+ input io_masters_0_aw_bits_lock,
+ input [3:0] io_masters_0_aw_bits_cache,
+ input [2:0] io_masters_0_aw_bits_prot,
+ input [3:0] io_masters_0_aw_bits_qos,
+ input [3:0] io_masters_0_aw_bits_region,
+ input [4:0] io_masters_0_aw_bits_id,
+ input io_masters_0_aw_bits_user,
+ output io_masters_0_w_ready,
+ input io_masters_0_w_valid,
+ input [63:0] io_masters_0_w_bits_data,
+ input io_masters_0_w_bits_last,
+ input [7:0] io_masters_0_w_bits_strb,
+ input io_masters_0_w_bits_user,
+ input io_masters_0_b_ready,
+ output io_masters_0_b_valid,
+ output [1:0] io_masters_0_b_bits_resp,
+ output [4:0] io_masters_0_b_bits_id,
+ output io_masters_0_b_bits_user,
+ output io_masters_0_ar_ready,
+ input io_masters_0_ar_valid,
+ input [31:0] io_masters_0_ar_bits_addr,
+ input [7:0] io_masters_0_ar_bits_len,
+ input [2:0] io_masters_0_ar_bits_size,
+ input [1:0] io_masters_0_ar_bits_burst,
+ input io_masters_0_ar_bits_lock,
+ input [3:0] io_masters_0_ar_bits_cache,
+ input [2:0] io_masters_0_ar_bits_prot,
+ input [3:0] io_masters_0_ar_bits_qos,
+ input [3:0] io_masters_0_ar_bits_region,
+ input [4:0] io_masters_0_ar_bits_id,
+ input io_masters_0_ar_bits_user,
+ input io_masters_0_r_ready,
+ output io_masters_0_r_valid,
+ output [1:0] io_masters_0_r_bits_resp,
+ output [63:0] io_masters_0_r_bits_data,
+ output io_masters_0_r_bits_last,
+ output [4:0] io_masters_0_r_bits_id,
+ output io_masters_0_r_bits_user,
+ output io_masters_1_aw_ready,
+ input io_masters_1_aw_valid,
+ input [31:0] io_masters_1_aw_bits_addr,
+ input [7:0] io_masters_1_aw_bits_len,
+ input [2:0] io_masters_1_aw_bits_size,
+ input [1:0] io_masters_1_aw_bits_burst,
+ input io_masters_1_aw_bits_lock,
+ input [3:0] io_masters_1_aw_bits_cache,
+ input [2:0] io_masters_1_aw_bits_prot,
+ input [3:0] io_masters_1_aw_bits_qos,
+ input [3:0] io_masters_1_aw_bits_region,
+ input [4:0] io_masters_1_aw_bits_id,
+ input io_masters_1_aw_bits_user,
+ output io_masters_1_w_ready,
+ input io_masters_1_w_valid,
+ input [63:0] io_masters_1_w_bits_data,
+ input io_masters_1_w_bits_last,
+ input [7:0] io_masters_1_w_bits_strb,
+ input io_masters_1_w_bits_user,
+ input io_masters_1_b_ready,
+ output io_masters_1_b_valid,
+ output [1:0] io_masters_1_b_bits_resp,
+ output [4:0] io_masters_1_b_bits_id,
+ output io_masters_1_b_bits_user,
+ output io_masters_1_ar_ready,
+ input io_masters_1_ar_valid,
+ input [31:0] io_masters_1_ar_bits_addr,
+ input [7:0] io_masters_1_ar_bits_len,
+ input [2:0] io_masters_1_ar_bits_size,
+ input [1:0] io_masters_1_ar_bits_burst,
+ input io_masters_1_ar_bits_lock,
+ input [3:0] io_masters_1_ar_bits_cache,
+ input [2:0] io_masters_1_ar_bits_prot,
+ input [3:0] io_masters_1_ar_bits_qos,
+ input [3:0] io_masters_1_ar_bits_region,
+ input [4:0] io_masters_1_ar_bits_id,
+ input io_masters_1_ar_bits_user,
+ input io_masters_1_r_ready,
+ output io_masters_1_r_valid,
+ output [1:0] io_masters_1_r_bits_resp,
+ output [63:0] io_masters_1_r_bits_data,
+ output io_masters_1_r_bits_last,
+ output [4:0] io_masters_1_r_bits_id,
+ output io_masters_1_r_bits_user,
+ input io_slaves_0_aw_ready,
+ output io_slaves_0_aw_valid,
+ output [31:0] io_slaves_0_aw_bits_addr,
+ output [7:0] io_slaves_0_aw_bits_len,
+ output [2:0] io_slaves_0_aw_bits_size,
+ output [1:0] io_slaves_0_aw_bits_burst,
+ output io_slaves_0_aw_bits_lock,
+ output [3:0] io_slaves_0_aw_bits_cache,
+ output [2:0] io_slaves_0_aw_bits_prot,
+ output [3:0] io_slaves_0_aw_bits_qos,
+ output [3:0] io_slaves_0_aw_bits_region,
+ output [4:0] io_slaves_0_aw_bits_id,
+ output io_slaves_0_aw_bits_user,
+ input io_slaves_0_w_ready,
+ output io_slaves_0_w_valid,
+ output [63:0] io_slaves_0_w_bits_data,
+ output io_slaves_0_w_bits_last,
+ output [7:0] io_slaves_0_w_bits_strb,
+ output io_slaves_0_w_bits_user,
+ output io_slaves_0_b_ready,
+ input io_slaves_0_b_valid,
+ input [1:0] io_slaves_0_b_bits_resp,
+ input [4:0] io_slaves_0_b_bits_id,
+ input io_slaves_0_b_bits_user,
+ input io_slaves_0_ar_ready,
+ output io_slaves_0_ar_valid,
+ output [31:0] io_slaves_0_ar_bits_addr,
+ output [7:0] io_slaves_0_ar_bits_len,
+ output [2:0] io_slaves_0_ar_bits_size,
+ output [1:0] io_slaves_0_ar_bits_burst,
+ output io_slaves_0_ar_bits_lock,
+ output [3:0] io_slaves_0_ar_bits_cache,
+ output [2:0] io_slaves_0_ar_bits_prot,
+ output [3:0] io_slaves_0_ar_bits_qos,
+ output [3:0] io_slaves_0_ar_bits_region,
+ output [4:0] io_slaves_0_ar_bits_id,
+ output io_slaves_0_ar_bits_user,
+ output io_slaves_0_r_ready,
+ input io_slaves_0_r_valid,
+ input [1:0] io_slaves_0_r_bits_resp,
+ input [63:0] io_slaves_0_r_bits_data,
+ input io_slaves_0_r_bits_last,
+ input [4:0] io_slaves_0_r_bits_id,
+ input io_slaves_0_r_bits_user,
+ input io_slaves_1_aw_ready,
+ output io_slaves_1_aw_valid,
+ output [31:0] io_slaves_1_aw_bits_addr,
+ output [7:0] io_slaves_1_aw_bits_len,
+ output [2:0] io_slaves_1_aw_bits_size,
+ output [1:0] io_slaves_1_aw_bits_burst,
+ output io_slaves_1_aw_bits_lock,
+ output [3:0] io_slaves_1_aw_bits_cache,
+ output [2:0] io_slaves_1_aw_bits_prot,
+ output [3:0] io_slaves_1_aw_bits_qos,
+ output [3:0] io_slaves_1_aw_bits_region,
+ output [4:0] io_slaves_1_aw_bits_id,
+ output io_slaves_1_aw_bits_user,
+ input io_slaves_1_w_ready,
+ output io_slaves_1_w_valid,
+ output [63:0] io_slaves_1_w_bits_data,
+ output io_slaves_1_w_bits_last,
+ output [7:0] io_slaves_1_w_bits_strb,
+ output io_slaves_1_w_bits_user,
+ output io_slaves_1_b_ready,
+ input io_slaves_1_b_valid,
+ input [1:0] io_slaves_1_b_bits_resp,
+ input [4:0] io_slaves_1_b_bits_id,
+ input io_slaves_1_b_bits_user,
+ input io_slaves_1_ar_ready,
+ output io_slaves_1_ar_valid,
+ output [31:0] io_slaves_1_ar_bits_addr,
+ output [7:0] io_slaves_1_ar_bits_len,
+ output [2:0] io_slaves_1_ar_bits_size,
+ output [1:0] io_slaves_1_ar_bits_burst,
+ output io_slaves_1_ar_bits_lock,
+ output [3:0] io_slaves_1_ar_bits_cache,
+ output [2:0] io_slaves_1_ar_bits_prot,
+ output [3:0] io_slaves_1_ar_bits_qos,
+ output [3:0] io_slaves_1_ar_bits_region,
+ output [4:0] io_slaves_1_ar_bits_id,
+ output io_slaves_1_ar_bits_user,
+ output io_slaves_1_r_ready,
+ input io_slaves_1_r_valid,
+ input [1:0] io_slaves_1_r_bits_resp,
+ input [63:0] io_slaves_1_r_bits_data,
+ input io_slaves_1_r_bits_last,
+ input [4:0] io_slaves_1_r_bits_id,
+ input io_slaves_1_r_bits_user,
+ input io_slaves_2_aw_ready,
+ output io_slaves_2_aw_valid,
+ output [31:0] io_slaves_2_aw_bits_addr,
+ output [7:0] io_slaves_2_aw_bits_len,
+ output [2:0] io_slaves_2_aw_bits_size,
+ output [1:0] io_slaves_2_aw_bits_burst,
+ output io_slaves_2_aw_bits_lock,
+ output [3:0] io_slaves_2_aw_bits_cache,
+ output [2:0] io_slaves_2_aw_bits_prot,
+ output [3:0] io_slaves_2_aw_bits_qos,
+ output [3:0] io_slaves_2_aw_bits_region,
+ output [4:0] io_slaves_2_aw_bits_id,
+ output io_slaves_2_aw_bits_user,
+ input io_slaves_2_w_ready,
+ output io_slaves_2_w_valid,
+ output [63:0] io_slaves_2_w_bits_data,
+ output io_slaves_2_w_bits_last,
+ output [7:0] io_slaves_2_w_bits_strb,
+ output io_slaves_2_w_bits_user,
+ output io_slaves_2_b_ready,
+ input io_slaves_2_b_valid,
+ input [1:0] io_slaves_2_b_bits_resp,
+ input [4:0] io_slaves_2_b_bits_id,
+ input io_slaves_2_b_bits_user,
+ input io_slaves_2_ar_ready,
+ output io_slaves_2_ar_valid,
+ output [31:0] io_slaves_2_ar_bits_addr,
+ output [7:0] io_slaves_2_ar_bits_len,
+ output [2:0] io_slaves_2_ar_bits_size,
+ output [1:0] io_slaves_2_ar_bits_burst,
+ output io_slaves_2_ar_bits_lock,
+ output [3:0] io_slaves_2_ar_bits_cache,
+ output [2:0] io_slaves_2_ar_bits_prot,
+ output [3:0] io_slaves_2_ar_bits_qos,
+ output [3:0] io_slaves_2_ar_bits_region,
+ output [4:0] io_slaves_2_ar_bits_id,
+ output io_slaves_2_ar_bits_user,
+ output io_slaves_2_r_ready,
+ input io_slaves_2_r_valid,
+ input [1:0] io_slaves_2_r_bits_resp,
+ input [63:0] io_slaves_2_r_bits_data,
+ input io_slaves_2_r_bits_last,
+ input [4:0] io_slaves_2_r_bits_id,
+ input io_slaves_2_r_bits_user,
+ input io_slaves_3_aw_ready,
+ output io_slaves_3_aw_valid,
+ output [31:0] io_slaves_3_aw_bits_addr,
+ output [7:0] io_slaves_3_aw_bits_len,
+ output [2:0] io_slaves_3_aw_bits_size,
+ output [1:0] io_slaves_3_aw_bits_burst,
+ output io_slaves_3_aw_bits_lock,
+ output [3:0] io_slaves_3_aw_bits_cache,
+ output [2:0] io_slaves_3_aw_bits_prot,
+ output [3:0] io_slaves_3_aw_bits_qos,
+ output [3:0] io_slaves_3_aw_bits_region,
+ output [4:0] io_slaves_3_aw_bits_id,
+ output io_slaves_3_aw_bits_user,
+ input io_slaves_3_w_ready,
+ output io_slaves_3_w_valid,
+ output [63:0] io_slaves_3_w_bits_data,
+ output io_slaves_3_w_bits_last,
+ output [7:0] io_slaves_3_w_bits_strb,
+ output io_slaves_3_w_bits_user,
+ output io_slaves_3_b_ready,
+ input io_slaves_3_b_valid,
+ input [1:0] io_slaves_3_b_bits_resp,
+ input [4:0] io_slaves_3_b_bits_id,
+ input io_slaves_3_b_bits_user,
+ input io_slaves_3_ar_ready,
+ output io_slaves_3_ar_valid,
+ output [31:0] io_slaves_3_ar_bits_addr,
+ output [7:0] io_slaves_3_ar_bits_len,
+ output [2:0] io_slaves_3_ar_bits_size,
+ output [1:0] io_slaves_3_ar_bits_burst,
+ output io_slaves_3_ar_bits_lock,
+ output [3:0] io_slaves_3_ar_bits_cache,
+ output [2:0] io_slaves_3_ar_bits_prot,
+ output [3:0] io_slaves_3_ar_bits_qos,
+ output [3:0] io_slaves_3_ar_bits_region,
+ output [4:0] io_slaves_3_ar_bits_id,
+ output io_slaves_3_ar_bits_user,
+ output io_slaves_3_r_ready,
+ input io_slaves_3_r_valid,
+ input [1:0] io_slaves_3_r_bits_resp,
+ input [63:0] io_slaves_3_r_bits_data,
+ input io_slaves_3_r_bits_last,
+ input [4:0] io_slaves_3_r_bits_id,
+ input io_slaves_3_r_bits_user,
+ input io_slaves_4_aw_ready,
+ output io_slaves_4_aw_valid,
+ output [31:0] io_slaves_4_aw_bits_addr,
+ output [7:0] io_slaves_4_aw_bits_len,
+ output [2:0] io_slaves_4_aw_bits_size,
+ output [1:0] io_slaves_4_aw_bits_burst,
+ output io_slaves_4_aw_bits_lock,
+ output [3:0] io_slaves_4_aw_bits_cache,
+ output [2:0] io_slaves_4_aw_bits_prot,
+ output [3:0] io_slaves_4_aw_bits_qos,
+ output [3:0] io_slaves_4_aw_bits_region,
+ output [4:0] io_slaves_4_aw_bits_id,
+ output io_slaves_4_aw_bits_user,
+ input io_slaves_4_w_ready,
+ output io_slaves_4_w_valid,
+ output [63:0] io_slaves_4_w_bits_data,
+ output io_slaves_4_w_bits_last,
+ output [7:0] io_slaves_4_w_bits_strb,
+ output io_slaves_4_w_bits_user,
+ output io_slaves_4_b_ready,
+ input io_slaves_4_b_valid,
+ input [1:0] io_slaves_4_b_bits_resp,
+ input [4:0] io_slaves_4_b_bits_id,
+ input io_slaves_4_b_bits_user,
+ input io_slaves_4_ar_ready,
+ output io_slaves_4_ar_valid,
+ output [31:0] io_slaves_4_ar_bits_addr,
+ output [7:0] io_slaves_4_ar_bits_len,
+ output [2:0] io_slaves_4_ar_bits_size,
+ output [1:0] io_slaves_4_ar_bits_burst,
+ output io_slaves_4_ar_bits_lock,
+ output [3:0] io_slaves_4_ar_bits_cache,
+ output [2:0] io_slaves_4_ar_bits_prot,
+ output [3:0] io_slaves_4_ar_bits_qos,
+ output [3:0] io_slaves_4_ar_bits_region,
+ output [4:0] io_slaves_4_ar_bits_id,
+ output io_slaves_4_ar_bits_user,
+ output io_slaves_4_r_ready,
+ input io_slaves_4_r_valid,
+ input [1:0] io_slaves_4_r_bits_resp,
+ input [63:0] io_slaves_4_r_bits_data,
+ input io_slaves_4_r_bits_last,
+ input [4:0] io_slaves_4_r_bits_id,
+ input io_slaves_4_r_bits_user
+);
+ wire xbar_clk;
+ wire xbar_reset;
+ wire xbar_io_masters_0_aw_ready;
+ wire xbar_io_masters_0_aw_valid;
+ wire [31:0] xbar_io_masters_0_aw_bits_addr;
+ wire [7:0] xbar_io_masters_0_aw_bits_len;
+ wire [2:0] xbar_io_masters_0_aw_bits_size;
+ wire [1:0] xbar_io_masters_0_aw_bits_burst;
+ wire xbar_io_masters_0_aw_bits_lock;
+ wire [3:0] xbar_io_masters_0_aw_bits_cache;
+ wire [2:0] xbar_io_masters_0_aw_bits_prot;
+ wire [3:0] xbar_io_masters_0_aw_bits_qos;
+ wire [3:0] xbar_io_masters_0_aw_bits_region;
+ wire [4:0] xbar_io_masters_0_aw_bits_id;
+ wire xbar_io_masters_0_aw_bits_user;
+ wire xbar_io_masters_0_w_ready;
+ wire xbar_io_masters_0_w_valid;
+ wire [63:0] xbar_io_masters_0_w_bits_data;
+ wire xbar_io_masters_0_w_bits_last;
+ wire [7:0] xbar_io_masters_0_w_bits_strb;
+ wire xbar_io_masters_0_w_bits_user;
+ wire xbar_io_masters_0_b_ready;
+ wire xbar_io_masters_0_b_valid;
+ wire [1:0] xbar_io_masters_0_b_bits_resp;
+ wire [4:0] xbar_io_masters_0_b_bits_id;
+ wire xbar_io_masters_0_b_bits_user;
+ wire xbar_io_masters_0_ar_ready;
+ wire xbar_io_masters_0_ar_valid;
+ wire [31:0] xbar_io_masters_0_ar_bits_addr;
+ wire [7:0] xbar_io_masters_0_ar_bits_len;
+ wire [2:0] xbar_io_masters_0_ar_bits_size;
+ wire [1:0] xbar_io_masters_0_ar_bits_burst;
+ wire xbar_io_masters_0_ar_bits_lock;
+ wire [3:0] xbar_io_masters_0_ar_bits_cache;
+ wire [2:0] xbar_io_masters_0_ar_bits_prot;
+ wire [3:0] xbar_io_masters_0_ar_bits_qos;
+ wire [3:0] xbar_io_masters_0_ar_bits_region;
+ wire [4:0] xbar_io_masters_0_ar_bits_id;
+ wire xbar_io_masters_0_ar_bits_user;
+ wire xbar_io_masters_0_r_ready;
+ wire xbar_io_masters_0_r_valid;
+ wire [1:0] xbar_io_masters_0_r_bits_resp;
+ wire [63:0] xbar_io_masters_0_r_bits_data;
+ wire xbar_io_masters_0_r_bits_last;
+ wire [4:0] xbar_io_masters_0_r_bits_id;
+ wire xbar_io_masters_0_r_bits_user;
+ wire xbar_io_masters_1_aw_ready;
+ wire xbar_io_masters_1_aw_valid;
+ wire [31:0] xbar_io_masters_1_aw_bits_addr;
+ wire [7:0] xbar_io_masters_1_aw_bits_len;
+ wire [2:0] xbar_io_masters_1_aw_bits_size;
+ wire [1:0] xbar_io_masters_1_aw_bits_burst;
+ wire xbar_io_masters_1_aw_bits_lock;
+ wire [3:0] xbar_io_masters_1_aw_bits_cache;
+ wire [2:0] xbar_io_masters_1_aw_bits_prot;
+ wire [3:0] xbar_io_masters_1_aw_bits_qos;
+ wire [3:0] xbar_io_masters_1_aw_bits_region;
+ wire [4:0] xbar_io_masters_1_aw_bits_id;
+ wire xbar_io_masters_1_aw_bits_user;
+ wire xbar_io_masters_1_w_ready;
+ wire xbar_io_masters_1_w_valid;
+ wire [63:0] xbar_io_masters_1_w_bits_data;
+ wire xbar_io_masters_1_w_bits_last;
+ wire [7:0] xbar_io_masters_1_w_bits_strb;
+ wire xbar_io_masters_1_w_bits_user;
+ wire xbar_io_masters_1_b_ready;
+ wire xbar_io_masters_1_b_valid;
+ wire [1:0] xbar_io_masters_1_b_bits_resp;
+ wire [4:0] xbar_io_masters_1_b_bits_id;
+ wire xbar_io_masters_1_b_bits_user;
+ wire xbar_io_masters_1_ar_ready;
+ wire xbar_io_masters_1_ar_valid;
+ wire [31:0] xbar_io_masters_1_ar_bits_addr;
+ wire [7:0] xbar_io_masters_1_ar_bits_len;
+ wire [2:0] xbar_io_masters_1_ar_bits_size;
+ wire [1:0] xbar_io_masters_1_ar_bits_burst;
+ wire xbar_io_masters_1_ar_bits_lock;
+ wire [3:0] xbar_io_masters_1_ar_bits_cache;
+ wire [2:0] xbar_io_masters_1_ar_bits_prot;
+ wire [3:0] xbar_io_masters_1_ar_bits_qos;
+ wire [3:0] xbar_io_masters_1_ar_bits_region;
+ wire [4:0] xbar_io_masters_1_ar_bits_id;
+ wire xbar_io_masters_1_ar_bits_user;
+ wire xbar_io_masters_1_r_ready;
+ wire xbar_io_masters_1_r_valid;
+ wire [1:0] xbar_io_masters_1_r_bits_resp;
+ wire [63:0] xbar_io_masters_1_r_bits_data;
+ wire xbar_io_masters_1_r_bits_last;
+ wire [4:0] xbar_io_masters_1_r_bits_id;
+ wire xbar_io_masters_1_r_bits_user;
+ wire xbar_io_slaves_0_aw_ready;
+ wire xbar_io_slaves_0_aw_valid;
+ wire [31:0] xbar_io_slaves_0_aw_bits_addr;
+ wire [7:0] xbar_io_slaves_0_aw_bits_len;
+ wire [2:0] xbar_io_slaves_0_aw_bits_size;
+ wire [1:0] xbar_io_slaves_0_aw_bits_burst;
+ wire xbar_io_slaves_0_aw_bits_lock;
+ wire [3:0] xbar_io_slaves_0_aw_bits_cache;
+ wire [2:0] xbar_io_slaves_0_aw_bits_prot;
+ wire [3:0] xbar_io_slaves_0_aw_bits_qos;
+ wire [3:0] xbar_io_slaves_0_aw_bits_region;
+ wire [4:0] xbar_io_slaves_0_aw_bits_id;
+ wire xbar_io_slaves_0_aw_bits_user;
+ wire xbar_io_slaves_0_w_ready;
+ wire xbar_io_slaves_0_w_valid;
+ wire [63:0] xbar_io_slaves_0_w_bits_data;
+ wire xbar_io_slaves_0_w_bits_last;
+ wire [7:0] xbar_io_slaves_0_w_bits_strb;
+ wire xbar_io_slaves_0_w_bits_user;
+ wire xbar_io_slaves_0_b_ready;
+ wire xbar_io_slaves_0_b_valid;
+ wire [1:0] xbar_io_slaves_0_b_bits_resp;
+ wire [4:0] xbar_io_slaves_0_b_bits_id;
+ wire xbar_io_slaves_0_b_bits_user;
+ wire xbar_io_slaves_0_ar_ready;
+ wire xbar_io_slaves_0_ar_valid;
+ wire [31:0] xbar_io_slaves_0_ar_bits_addr;
+ wire [7:0] xbar_io_slaves_0_ar_bits_len;
+ wire [2:0] xbar_io_slaves_0_ar_bits_size;
+ wire [1:0] xbar_io_slaves_0_ar_bits_burst;
+ wire xbar_io_slaves_0_ar_bits_lock;
+ wire [3:0] xbar_io_slaves_0_ar_bits_cache;
+ wire [2:0] xbar_io_slaves_0_ar_bits_prot;
+ wire [3:0] xbar_io_slaves_0_ar_bits_qos;
+ wire [3:0] xbar_io_slaves_0_ar_bits_region;
+ wire [4:0] xbar_io_slaves_0_ar_bits_id;
+ wire xbar_io_slaves_0_ar_bits_user;
+ wire xbar_io_slaves_0_r_ready;
+ wire xbar_io_slaves_0_r_valid;
+ wire [1:0] xbar_io_slaves_0_r_bits_resp;
+ wire [63:0] xbar_io_slaves_0_r_bits_data;
+ wire xbar_io_slaves_0_r_bits_last;
+ wire [4:0] xbar_io_slaves_0_r_bits_id;
+ wire xbar_io_slaves_0_r_bits_user;
+ wire xbar_io_slaves_1_aw_ready;
+ wire xbar_io_slaves_1_aw_valid;
+ wire [31:0] xbar_io_slaves_1_aw_bits_addr;
+ wire [7:0] xbar_io_slaves_1_aw_bits_len;
+ wire [2:0] xbar_io_slaves_1_aw_bits_size;
+ wire [1:0] xbar_io_slaves_1_aw_bits_burst;
+ wire xbar_io_slaves_1_aw_bits_lock;
+ wire [3:0] xbar_io_slaves_1_aw_bits_cache;
+ wire [2:0] xbar_io_slaves_1_aw_bits_prot;
+ wire [3:0] xbar_io_slaves_1_aw_bits_qos;
+ wire [3:0] xbar_io_slaves_1_aw_bits_region;
+ wire [4:0] xbar_io_slaves_1_aw_bits_id;
+ wire xbar_io_slaves_1_aw_bits_user;
+ wire xbar_io_slaves_1_w_ready;
+ wire xbar_io_slaves_1_w_valid;
+ wire [63:0] xbar_io_slaves_1_w_bits_data;
+ wire xbar_io_slaves_1_w_bits_last;
+ wire [7:0] xbar_io_slaves_1_w_bits_strb;
+ wire xbar_io_slaves_1_w_bits_user;
+ wire xbar_io_slaves_1_b_ready;
+ wire xbar_io_slaves_1_b_valid;
+ wire [1:0] xbar_io_slaves_1_b_bits_resp;
+ wire [4:0] xbar_io_slaves_1_b_bits_id;
+ wire xbar_io_slaves_1_b_bits_user;
+ wire xbar_io_slaves_1_ar_ready;
+ wire xbar_io_slaves_1_ar_valid;
+ wire [31:0] xbar_io_slaves_1_ar_bits_addr;
+ wire [7:0] xbar_io_slaves_1_ar_bits_len;
+ wire [2:0] xbar_io_slaves_1_ar_bits_size;
+ wire [1:0] xbar_io_slaves_1_ar_bits_burst;
+ wire xbar_io_slaves_1_ar_bits_lock;
+ wire [3:0] xbar_io_slaves_1_ar_bits_cache;
+ wire [2:0] xbar_io_slaves_1_ar_bits_prot;
+ wire [3:0] xbar_io_slaves_1_ar_bits_qos;
+ wire [3:0] xbar_io_slaves_1_ar_bits_region;
+ wire [4:0] xbar_io_slaves_1_ar_bits_id;
+ wire xbar_io_slaves_1_ar_bits_user;
+ wire xbar_io_slaves_1_r_ready;
+ wire xbar_io_slaves_1_r_valid;
+ wire [1:0] xbar_io_slaves_1_r_bits_resp;
+ wire [63:0] xbar_io_slaves_1_r_bits_data;
+ wire xbar_io_slaves_1_r_bits_last;
+ wire [4:0] xbar_io_slaves_1_r_bits_id;
+ wire xbar_io_slaves_1_r_bits_user;
+ wire xbar_io_slaves_2_aw_ready;
+ wire xbar_io_slaves_2_aw_valid;
+ wire [31:0] xbar_io_slaves_2_aw_bits_addr;
+ wire [7:0] xbar_io_slaves_2_aw_bits_len;
+ wire [2:0] xbar_io_slaves_2_aw_bits_size;
+ wire [1:0] xbar_io_slaves_2_aw_bits_burst;
+ wire xbar_io_slaves_2_aw_bits_lock;
+ wire [3:0] xbar_io_slaves_2_aw_bits_cache;
+ wire [2:0] xbar_io_slaves_2_aw_bits_prot;
+ wire [3:0] xbar_io_slaves_2_aw_bits_qos;
+ wire [3:0] xbar_io_slaves_2_aw_bits_region;
+ wire [4:0] xbar_io_slaves_2_aw_bits_id;
+ wire xbar_io_slaves_2_aw_bits_user;
+ wire xbar_io_slaves_2_w_ready;
+ wire xbar_io_slaves_2_w_valid;
+ wire [63:0] xbar_io_slaves_2_w_bits_data;
+ wire xbar_io_slaves_2_w_bits_last;
+ wire [7:0] xbar_io_slaves_2_w_bits_strb;
+ wire xbar_io_slaves_2_w_bits_user;
+ wire xbar_io_slaves_2_b_ready;
+ wire xbar_io_slaves_2_b_valid;
+ wire [1:0] xbar_io_slaves_2_b_bits_resp;
+ wire [4:0] xbar_io_slaves_2_b_bits_id;
+ wire xbar_io_slaves_2_b_bits_user;
+ wire xbar_io_slaves_2_ar_ready;
+ wire xbar_io_slaves_2_ar_valid;
+ wire [31:0] xbar_io_slaves_2_ar_bits_addr;
+ wire [7:0] xbar_io_slaves_2_ar_bits_len;
+ wire [2:0] xbar_io_slaves_2_ar_bits_size;
+ wire [1:0] xbar_io_slaves_2_ar_bits_burst;
+ wire xbar_io_slaves_2_ar_bits_lock;
+ wire [3:0] xbar_io_slaves_2_ar_bits_cache;
+ wire [2:0] xbar_io_slaves_2_ar_bits_prot;
+ wire [3:0] xbar_io_slaves_2_ar_bits_qos;
+ wire [3:0] xbar_io_slaves_2_ar_bits_region;
+ wire [4:0] xbar_io_slaves_2_ar_bits_id;
+ wire xbar_io_slaves_2_ar_bits_user;
+ wire xbar_io_slaves_2_r_ready;
+ wire xbar_io_slaves_2_r_valid;
+ wire [1:0] xbar_io_slaves_2_r_bits_resp;
+ wire [63:0] xbar_io_slaves_2_r_bits_data;
+ wire xbar_io_slaves_2_r_bits_last;
+ wire [4:0] xbar_io_slaves_2_r_bits_id;
+ wire xbar_io_slaves_2_r_bits_user;
+ wire xbar_io_slaves_3_aw_ready;
+ wire xbar_io_slaves_3_aw_valid;
+ wire [31:0] xbar_io_slaves_3_aw_bits_addr;
+ wire [7:0] xbar_io_slaves_3_aw_bits_len;
+ wire [2:0] xbar_io_slaves_3_aw_bits_size;
+ wire [1:0] xbar_io_slaves_3_aw_bits_burst;
+ wire xbar_io_slaves_3_aw_bits_lock;
+ wire [3:0] xbar_io_slaves_3_aw_bits_cache;
+ wire [2:0] xbar_io_slaves_3_aw_bits_prot;
+ wire [3:0] xbar_io_slaves_3_aw_bits_qos;
+ wire [3:0] xbar_io_slaves_3_aw_bits_region;
+ wire [4:0] xbar_io_slaves_3_aw_bits_id;
+ wire xbar_io_slaves_3_aw_bits_user;
+ wire xbar_io_slaves_3_w_ready;
+ wire xbar_io_slaves_3_w_valid;
+ wire [63:0] xbar_io_slaves_3_w_bits_data;
+ wire xbar_io_slaves_3_w_bits_last;
+ wire [7:0] xbar_io_slaves_3_w_bits_strb;
+ wire xbar_io_slaves_3_w_bits_user;
+ wire xbar_io_slaves_3_b_ready;
+ wire xbar_io_slaves_3_b_valid;
+ wire [1:0] xbar_io_slaves_3_b_bits_resp;
+ wire [4:0] xbar_io_slaves_3_b_bits_id;
+ wire xbar_io_slaves_3_b_bits_user;
+ wire xbar_io_slaves_3_ar_ready;
+ wire xbar_io_slaves_3_ar_valid;
+ wire [31:0] xbar_io_slaves_3_ar_bits_addr;
+ wire [7:0] xbar_io_slaves_3_ar_bits_len;
+ wire [2:0] xbar_io_slaves_3_ar_bits_size;
+ wire [1:0] xbar_io_slaves_3_ar_bits_burst;
+ wire xbar_io_slaves_3_ar_bits_lock;
+ wire [3:0] xbar_io_slaves_3_ar_bits_cache;
+ wire [2:0] xbar_io_slaves_3_ar_bits_prot;
+ wire [3:0] xbar_io_slaves_3_ar_bits_qos;
+ wire [3:0] xbar_io_slaves_3_ar_bits_region;
+ wire [4:0] xbar_io_slaves_3_ar_bits_id;
+ wire xbar_io_slaves_3_ar_bits_user;
+ wire xbar_io_slaves_3_r_ready;
+ wire xbar_io_slaves_3_r_valid;
+ wire [1:0] xbar_io_slaves_3_r_bits_resp;
+ wire [63:0] xbar_io_slaves_3_r_bits_data;
+ wire xbar_io_slaves_3_r_bits_last;
+ wire [4:0] xbar_io_slaves_3_r_bits_id;
+ wire xbar_io_slaves_3_r_bits_user;
+ wire T_2869_clk;
+ wire T_2869_reset;
+ wire T_2869_io_masters_0_aw_ready;
+ wire T_2869_io_masters_0_aw_valid;
+ wire [31:0] T_2869_io_masters_0_aw_bits_addr;
+ wire [7:0] T_2869_io_masters_0_aw_bits_len;
+ wire [2:0] T_2869_io_masters_0_aw_bits_size;
+ wire [1:0] T_2869_io_masters_0_aw_bits_burst;
+ wire T_2869_io_masters_0_aw_bits_lock;
+ wire [3:0] T_2869_io_masters_0_aw_bits_cache;
+ wire [2:0] T_2869_io_masters_0_aw_bits_prot;
+ wire [3:0] T_2869_io_masters_0_aw_bits_qos;
+ wire [3:0] T_2869_io_masters_0_aw_bits_region;
+ wire [4:0] T_2869_io_masters_0_aw_bits_id;
+ wire T_2869_io_masters_0_aw_bits_user;
+ wire T_2869_io_masters_0_w_ready;
+ wire T_2869_io_masters_0_w_valid;
+ wire [63:0] T_2869_io_masters_0_w_bits_data;
+ wire T_2869_io_masters_0_w_bits_last;
+ wire [7:0] T_2869_io_masters_0_w_bits_strb;
+ wire T_2869_io_masters_0_w_bits_user;
+ wire T_2869_io_masters_0_b_ready;
+ wire T_2869_io_masters_0_b_valid;
+ wire [1:0] T_2869_io_masters_0_b_bits_resp;
+ wire [4:0] T_2869_io_masters_0_b_bits_id;
+ wire T_2869_io_masters_0_b_bits_user;
+ wire T_2869_io_masters_0_ar_ready;
+ wire T_2869_io_masters_0_ar_valid;
+ wire [31:0] T_2869_io_masters_0_ar_bits_addr;
+ wire [7:0] T_2869_io_masters_0_ar_bits_len;
+ wire [2:0] T_2869_io_masters_0_ar_bits_size;
+ wire [1:0] T_2869_io_masters_0_ar_bits_burst;
+ wire T_2869_io_masters_0_ar_bits_lock;
+ wire [3:0] T_2869_io_masters_0_ar_bits_cache;
+ wire [2:0] T_2869_io_masters_0_ar_bits_prot;
+ wire [3:0] T_2869_io_masters_0_ar_bits_qos;
+ wire [3:0] T_2869_io_masters_0_ar_bits_region;
+ wire [4:0] T_2869_io_masters_0_ar_bits_id;
+ wire T_2869_io_masters_0_ar_bits_user;
+ wire T_2869_io_masters_0_r_ready;
+ wire T_2869_io_masters_0_r_valid;
+ wire [1:0] T_2869_io_masters_0_r_bits_resp;
+ wire [63:0] T_2869_io_masters_0_r_bits_data;
+ wire T_2869_io_masters_0_r_bits_last;
+ wire [4:0] T_2869_io_masters_0_r_bits_id;
+ wire T_2869_io_masters_0_r_bits_user;
+ wire T_2869_io_slaves_0_aw_ready;
+ wire T_2869_io_slaves_0_aw_valid;
+ wire [31:0] T_2869_io_slaves_0_aw_bits_addr;
+ wire [7:0] T_2869_io_slaves_0_aw_bits_len;
+ wire [2:0] T_2869_io_slaves_0_aw_bits_size;
+ wire [1:0] T_2869_io_slaves_0_aw_bits_burst;
+ wire T_2869_io_slaves_0_aw_bits_lock;
+ wire [3:0] T_2869_io_slaves_0_aw_bits_cache;
+ wire [2:0] T_2869_io_slaves_0_aw_bits_prot;
+ wire [3:0] T_2869_io_slaves_0_aw_bits_qos;
+ wire [3:0] T_2869_io_slaves_0_aw_bits_region;
+ wire [4:0] T_2869_io_slaves_0_aw_bits_id;
+ wire T_2869_io_slaves_0_aw_bits_user;
+ wire T_2869_io_slaves_0_w_ready;
+ wire T_2869_io_slaves_0_w_valid;
+ wire [63:0] T_2869_io_slaves_0_w_bits_data;
+ wire T_2869_io_slaves_0_w_bits_last;
+ wire [7:0] T_2869_io_slaves_0_w_bits_strb;
+ wire T_2869_io_slaves_0_w_bits_user;
+ wire T_2869_io_slaves_0_b_ready;
+ wire T_2869_io_slaves_0_b_valid;
+ wire [1:0] T_2869_io_slaves_0_b_bits_resp;
+ wire [4:0] T_2869_io_slaves_0_b_bits_id;
+ wire T_2869_io_slaves_0_b_bits_user;
+ wire T_2869_io_slaves_0_ar_ready;
+ wire T_2869_io_slaves_0_ar_valid;
+ wire [31:0] T_2869_io_slaves_0_ar_bits_addr;
+ wire [7:0] T_2869_io_slaves_0_ar_bits_len;
+ wire [2:0] T_2869_io_slaves_0_ar_bits_size;
+ wire [1:0] T_2869_io_slaves_0_ar_bits_burst;
+ wire T_2869_io_slaves_0_ar_bits_lock;
+ wire [3:0] T_2869_io_slaves_0_ar_bits_cache;
+ wire [2:0] T_2869_io_slaves_0_ar_bits_prot;
+ wire [3:0] T_2869_io_slaves_0_ar_bits_qos;
+ wire [3:0] T_2869_io_slaves_0_ar_bits_region;
+ wire [4:0] T_2869_io_slaves_0_ar_bits_id;
+ wire T_2869_io_slaves_0_ar_bits_user;
+ wire T_2869_io_slaves_0_r_ready;
+ wire T_2869_io_slaves_0_r_valid;
+ wire [1:0] T_2869_io_slaves_0_r_bits_resp;
+ wire [63:0] T_2869_io_slaves_0_r_bits_data;
+ wire T_2869_io_slaves_0_r_bits_last;
+ wire [4:0] T_2869_io_slaves_0_r_bits_id;
+ wire T_2869_io_slaves_0_r_bits_user;
+ wire T_2869_io_slaves_1_aw_ready;
+ wire T_2869_io_slaves_1_aw_valid;
+ wire [31:0] T_2869_io_slaves_1_aw_bits_addr;
+ wire [7:0] T_2869_io_slaves_1_aw_bits_len;
+ wire [2:0] T_2869_io_slaves_1_aw_bits_size;
+ wire [1:0] T_2869_io_slaves_1_aw_bits_burst;
+ wire T_2869_io_slaves_1_aw_bits_lock;
+ wire [3:0] T_2869_io_slaves_1_aw_bits_cache;
+ wire [2:0] T_2869_io_slaves_1_aw_bits_prot;
+ wire [3:0] T_2869_io_slaves_1_aw_bits_qos;
+ wire [3:0] T_2869_io_slaves_1_aw_bits_region;
+ wire [4:0] T_2869_io_slaves_1_aw_bits_id;
+ wire T_2869_io_slaves_1_aw_bits_user;
+ wire T_2869_io_slaves_1_w_ready;
+ wire T_2869_io_slaves_1_w_valid;
+ wire [63:0] T_2869_io_slaves_1_w_bits_data;
+ wire T_2869_io_slaves_1_w_bits_last;
+ wire [7:0] T_2869_io_slaves_1_w_bits_strb;
+ wire T_2869_io_slaves_1_w_bits_user;
+ wire T_2869_io_slaves_1_b_ready;
+ wire T_2869_io_slaves_1_b_valid;
+ wire [1:0] T_2869_io_slaves_1_b_bits_resp;
+ wire [4:0] T_2869_io_slaves_1_b_bits_id;
+ wire T_2869_io_slaves_1_b_bits_user;
+ wire T_2869_io_slaves_1_ar_ready;
+ wire T_2869_io_slaves_1_ar_valid;
+ wire [31:0] T_2869_io_slaves_1_ar_bits_addr;
+ wire [7:0] T_2869_io_slaves_1_ar_bits_len;
+ wire [2:0] T_2869_io_slaves_1_ar_bits_size;
+ wire [1:0] T_2869_io_slaves_1_ar_bits_burst;
+ wire T_2869_io_slaves_1_ar_bits_lock;
+ wire [3:0] T_2869_io_slaves_1_ar_bits_cache;
+ wire [2:0] T_2869_io_slaves_1_ar_bits_prot;
+ wire [3:0] T_2869_io_slaves_1_ar_bits_qos;
+ wire [3:0] T_2869_io_slaves_1_ar_bits_region;
+ wire [4:0] T_2869_io_slaves_1_ar_bits_id;
+ wire T_2869_io_slaves_1_ar_bits_user;
+ wire T_2869_io_slaves_1_r_ready;
+ wire T_2869_io_slaves_1_r_valid;
+ wire [1:0] T_2869_io_slaves_1_r_bits_resp;
+ wire [63:0] T_2869_io_slaves_1_r_bits_data;
+ wire T_2869_io_slaves_1_r_bits_last;
+ wire [4:0] T_2869_io_slaves_1_r_bits_id;
+ wire T_2869_io_slaves_1_r_bits_user;
+ wire T_2869_io_slaves_2_aw_ready;
+ wire T_2869_io_slaves_2_aw_valid;
+ wire [31:0] T_2869_io_slaves_2_aw_bits_addr;
+ wire [7:0] T_2869_io_slaves_2_aw_bits_len;
+ wire [2:0] T_2869_io_slaves_2_aw_bits_size;
+ wire [1:0] T_2869_io_slaves_2_aw_bits_burst;
+ wire T_2869_io_slaves_2_aw_bits_lock;
+ wire [3:0] T_2869_io_slaves_2_aw_bits_cache;
+ wire [2:0] T_2869_io_slaves_2_aw_bits_prot;
+ wire [3:0] T_2869_io_slaves_2_aw_bits_qos;
+ wire [3:0] T_2869_io_slaves_2_aw_bits_region;
+ wire [4:0] T_2869_io_slaves_2_aw_bits_id;
+ wire T_2869_io_slaves_2_aw_bits_user;
+ wire T_2869_io_slaves_2_w_ready;
+ wire T_2869_io_slaves_2_w_valid;
+ wire [63:0] T_2869_io_slaves_2_w_bits_data;
+ wire T_2869_io_slaves_2_w_bits_last;
+ wire [7:0] T_2869_io_slaves_2_w_bits_strb;
+ wire T_2869_io_slaves_2_w_bits_user;
+ wire T_2869_io_slaves_2_b_ready;
+ wire T_2869_io_slaves_2_b_valid;
+ wire [1:0] T_2869_io_slaves_2_b_bits_resp;
+ wire [4:0] T_2869_io_slaves_2_b_bits_id;
+ wire T_2869_io_slaves_2_b_bits_user;
+ wire T_2869_io_slaves_2_ar_ready;
+ wire T_2869_io_slaves_2_ar_valid;
+ wire [31:0] T_2869_io_slaves_2_ar_bits_addr;
+ wire [7:0] T_2869_io_slaves_2_ar_bits_len;
+ wire [2:0] T_2869_io_slaves_2_ar_bits_size;
+ wire [1:0] T_2869_io_slaves_2_ar_bits_burst;
+ wire T_2869_io_slaves_2_ar_bits_lock;
+ wire [3:0] T_2869_io_slaves_2_ar_bits_cache;
+ wire [2:0] T_2869_io_slaves_2_ar_bits_prot;
+ wire [3:0] T_2869_io_slaves_2_ar_bits_qos;
+ wire [3:0] T_2869_io_slaves_2_ar_bits_region;
+ wire [4:0] T_2869_io_slaves_2_ar_bits_id;
+ wire T_2869_io_slaves_2_ar_bits_user;
+ wire T_2869_io_slaves_2_r_ready;
+ wire T_2869_io_slaves_2_r_valid;
+ wire [1:0] T_2869_io_slaves_2_r_bits_resp;
+ wire [63:0] T_2869_io_slaves_2_r_bits_data;
+ wire T_2869_io_slaves_2_r_bits_last;
+ wire [4:0] T_2869_io_slaves_2_r_bits_id;
+ wire T_2869_io_slaves_2_r_bits_user;
+ wire T_2870_clk;
+ wire T_2870_reset;
+ wire T_2870_io_aw_ready;
+ wire T_2870_io_aw_valid;
+ wire [31:0] T_2870_io_aw_bits_addr;
+ wire [7:0] T_2870_io_aw_bits_len;
+ wire [2:0] T_2870_io_aw_bits_size;
+ wire [1:0] T_2870_io_aw_bits_burst;
+ wire T_2870_io_aw_bits_lock;
+ wire [3:0] T_2870_io_aw_bits_cache;
+ wire [2:0] T_2870_io_aw_bits_prot;
+ wire [3:0] T_2870_io_aw_bits_qos;
+ wire [3:0] T_2870_io_aw_bits_region;
+ wire [4:0] T_2870_io_aw_bits_id;
+ wire T_2870_io_aw_bits_user;
+ wire T_2870_io_w_ready;
+ wire T_2870_io_w_valid;
+ wire [63:0] T_2870_io_w_bits_data;
+ wire T_2870_io_w_bits_last;
+ wire [7:0] T_2870_io_w_bits_strb;
+ wire T_2870_io_w_bits_user;
+ wire T_2870_io_b_ready;
+ wire T_2870_io_b_valid;
+ wire [1:0] T_2870_io_b_bits_resp;
+ wire [4:0] T_2870_io_b_bits_id;
+ wire T_2870_io_b_bits_user;
+ wire T_2870_io_ar_ready;
+ wire T_2870_io_ar_valid;
+ wire [31:0] T_2870_io_ar_bits_addr;
+ wire [7:0] T_2870_io_ar_bits_len;
+ wire [2:0] T_2870_io_ar_bits_size;
+ wire [1:0] T_2870_io_ar_bits_burst;
+ wire T_2870_io_ar_bits_lock;
+ wire [3:0] T_2870_io_ar_bits_cache;
+ wire [2:0] T_2870_io_ar_bits_prot;
+ wire [3:0] T_2870_io_ar_bits_qos;
+ wire [3:0] T_2870_io_ar_bits_region;
+ wire [4:0] T_2870_io_ar_bits_id;
+ wire T_2870_io_ar_bits_user;
+ wire T_2870_io_r_ready;
+ wire T_2870_io_r_valid;
+ wire [1:0] T_2870_io_r_bits_resp;
+ wire [63:0] T_2870_io_r_bits_data;
+ wire T_2870_io_r_bits_last;
+ wire [4:0] T_2870_io_r_bits_id;
+ wire T_2870_io_r_bits_user;
+ NastiCrossbar xbar (
+ .clk(xbar_clk),
+ .reset(xbar_reset),
+ .io_masters_0_aw_ready(xbar_io_masters_0_aw_ready),
+ .io_masters_0_aw_valid(xbar_io_masters_0_aw_valid),
+ .io_masters_0_aw_bits_addr(xbar_io_masters_0_aw_bits_addr),
+ .io_masters_0_aw_bits_len(xbar_io_masters_0_aw_bits_len),
+ .io_masters_0_aw_bits_size(xbar_io_masters_0_aw_bits_size),
+ .io_masters_0_aw_bits_burst(xbar_io_masters_0_aw_bits_burst),
+ .io_masters_0_aw_bits_lock(xbar_io_masters_0_aw_bits_lock),
+ .io_masters_0_aw_bits_cache(xbar_io_masters_0_aw_bits_cache),
+ .io_masters_0_aw_bits_prot(xbar_io_masters_0_aw_bits_prot),
+ .io_masters_0_aw_bits_qos(xbar_io_masters_0_aw_bits_qos),
+ .io_masters_0_aw_bits_region(xbar_io_masters_0_aw_bits_region),
+ .io_masters_0_aw_bits_id(xbar_io_masters_0_aw_bits_id),
+ .io_masters_0_aw_bits_user(xbar_io_masters_0_aw_bits_user),
+ .io_masters_0_w_ready(xbar_io_masters_0_w_ready),
+ .io_masters_0_w_valid(xbar_io_masters_0_w_valid),
+ .io_masters_0_w_bits_data(xbar_io_masters_0_w_bits_data),
+ .io_masters_0_w_bits_last(xbar_io_masters_0_w_bits_last),
+ .io_masters_0_w_bits_strb(xbar_io_masters_0_w_bits_strb),
+ .io_masters_0_w_bits_user(xbar_io_masters_0_w_bits_user),
+ .io_masters_0_b_ready(xbar_io_masters_0_b_ready),
+ .io_masters_0_b_valid(xbar_io_masters_0_b_valid),
+ .io_masters_0_b_bits_resp(xbar_io_masters_0_b_bits_resp),
+ .io_masters_0_b_bits_id(xbar_io_masters_0_b_bits_id),
+ .io_masters_0_b_bits_user(xbar_io_masters_0_b_bits_user),
+ .io_masters_0_ar_ready(xbar_io_masters_0_ar_ready),
+ .io_masters_0_ar_valid(xbar_io_masters_0_ar_valid),
+ .io_masters_0_ar_bits_addr(xbar_io_masters_0_ar_bits_addr),
+ .io_masters_0_ar_bits_len(xbar_io_masters_0_ar_bits_len),
+ .io_masters_0_ar_bits_size(xbar_io_masters_0_ar_bits_size),
+ .io_masters_0_ar_bits_burst(xbar_io_masters_0_ar_bits_burst),
+ .io_masters_0_ar_bits_lock(xbar_io_masters_0_ar_bits_lock),
+ .io_masters_0_ar_bits_cache(xbar_io_masters_0_ar_bits_cache),
+ .io_masters_0_ar_bits_prot(xbar_io_masters_0_ar_bits_prot),
+ .io_masters_0_ar_bits_qos(xbar_io_masters_0_ar_bits_qos),
+ .io_masters_0_ar_bits_region(xbar_io_masters_0_ar_bits_region),
+ .io_masters_0_ar_bits_id(xbar_io_masters_0_ar_bits_id),
+ .io_masters_0_ar_bits_user(xbar_io_masters_0_ar_bits_user),
+ .io_masters_0_r_ready(xbar_io_masters_0_r_ready),
+ .io_masters_0_r_valid(xbar_io_masters_0_r_valid),
+ .io_masters_0_r_bits_resp(xbar_io_masters_0_r_bits_resp),
+ .io_masters_0_r_bits_data(xbar_io_masters_0_r_bits_data),
+ .io_masters_0_r_bits_last(xbar_io_masters_0_r_bits_last),
+ .io_masters_0_r_bits_id(xbar_io_masters_0_r_bits_id),
+ .io_masters_0_r_bits_user(xbar_io_masters_0_r_bits_user),
+ .io_masters_1_aw_ready(xbar_io_masters_1_aw_ready),
+ .io_masters_1_aw_valid(xbar_io_masters_1_aw_valid),
+ .io_masters_1_aw_bits_addr(xbar_io_masters_1_aw_bits_addr),
+ .io_masters_1_aw_bits_len(xbar_io_masters_1_aw_bits_len),
+ .io_masters_1_aw_bits_size(xbar_io_masters_1_aw_bits_size),
+ .io_masters_1_aw_bits_burst(xbar_io_masters_1_aw_bits_burst),
+ .io_masters_1_aw_bits_lock(xbar_io_masters_1_aw_bits_lock),
+ .io_masters_1_aw_bits_cache(xbar_io_masters_1_aw_bits_cache),
+ .io_masters_1_aw_bits_prot(xbar_io_masters_1_aw_bits_prot),
+ .io_masters_1_aw_bits_qos(xbar_io_masters_1_aw_bits_qos),
+ .io_masters_1_aw_bits_region(xbar_io_masters_1_aw_bits_region),
+ .io_masters_1_aw_bits_id(xbar_io_masters_1_aw_bits_id),
+ .io_masters_1_aw_bits_user(xbar_io_masters_1_aw_bits_user),
+ .io_masters_1_w_ready(xbar_io_masters_1_w_ready),
+ .io_masters_1_w_valid(xbar_io_masters_1_w_valid),
+ .io_masters_1_w_bits_data(xbar_io_masters_1_w_bits_data),
+ .io_masters_1_w_bits_last(xbar_io_masters_1_w_bits_last),
+ .io_masters_1_w_bits_strb(xbar_io_masters_1_w_bits_strb),
+ .io_masters_1_w_bits_user(xbar_io_masters_1_w_bits_user),
+ .io_masters_1_b_ready(xbar_io_masters_1_b_ready),
+ .io_masters_1_b_valid(xbar_io_masters_1_b_valid),
+ .io_masters_1_b_bits_resp(xbar_io_masters_1_b_bits_resp),
+ .io_masters_1_b_bits_id(xbar_io_masters_1_b_bits_id),
+ .io_masters_1_b_bits_user(xbar_io_masters_1_b_bits_user),
+ .io_masters_1_ar_ready(xbar_io_masters_1_ar_ready),
+ .io_masters_1_ar_valid(xbar_io_masters_1_ar_valid),
+ .io_masters_1_ar_bits_addr(xbar_io_masters_1_ar_bits_addr),
+ .io_masters_1_ar_bits_len(xbar_io_masters_1_ar_bits_len),
+ .io_masters_1_ar_bits_size(xbar_io_masters_1_ar_bits_size),
+ .io_masters_1_ar_bits_burst(xbar_io_masters_1_ar_bits_burst),
+ .io_masters_1_ar_bits_lock(xbar_io_masters_1_ar_bits_lock),
+ .io_masters_1_ar_bits_cache(xbar_io_masters_1_ar_bits_cache),
+ .io_masters_1_ar_bits_prot(xbar_io_masters_1_ar_bits_prot),
+ .io_masters_1_ar_bits_qos(xbar_io_masters_1_ar_bits_qos),
+ .io_masters_1_ar_bits_region(xbar_io_masters_1_ar_bits_region),
+ .io_masters_1_ar_bits_id(xbar_io_masters_1_ar_bits_id),
+ .io_masters_1_ar_bits_user(xbar_io_masters_1_ar_bits_user),
+ .io_masters_1_r_ready(xbar_io_masters_1_r_ready),
+ .io_masters_1_r_valid(xbar_io_masters_1_r_valid),
+ .io_masters_1_r_bits_resp(xbar_io_masters_1_r_bits_resp),
+ .io_masters_1_r_bits_data(xbar_io_masters_1_r_bits_data),
+ .io_masters_1_r_bits_last(xbar_io_masters_1_r_bits_last),
+ .io_masters_1_r_bits_id(xbar_io_masters_1_r_bits_id),
+ .io_masters_1_r_bits_user(xbar_io_masters_1_r_bits_user),
+ .io_slaves_0_aw_ready(xbar_io_slaves_0_aw_ready),
+ .io_slaves_0_aw_valid(xbar_io_slaves_0_aw_valid),
+ .io_slaves_0_aw_bits_addr(xbar_io_slaves_0_aw_bits_addr),
+ .io_slaves_0_aw_bits_len(xbar_io_slaves_0_aw_bits_len),
+ .io_slaves_0_aw_bits_size(xbar_io_slaves_0_aw_bits_size),
+ .io_slaves_0_aw_bits_burst(xbar_io_slaves_0_aw_bits_burst),
+ .io_slaves_0_aw_bits_lock(xbar_io_slaves_0_aw_bits_lock),
+ .io_slaves_0_aw_bits_cache(xbar_io_slaves_0_aw_bits_cache),
+ .io_slaves_0_aw_bits_prot(xbar_io_slaves_0_aw_bits_prot),
+ .io_slaves_0_aw_bits_qos(xbar_io_slaves_0_aw_bits_qos),
+ .io_slaves_0_aw_bits_region(xbar_io_slaves_0_aw_bits_region),
+ .io_slaves_0_aw_bits_id(xbar_io_slaves_0_aw_bits_id),
+ .io_slaves_0_aw_bits_user(xbar_io_slaves_0_aw_bits_user),
+ .io_slaves_0_w_ready(xbar_io_slaves_0_w_ready),
+ .io_slaves_0_w_valid(xbar_io_slaves_0_w_valid),
+ .io_slaves_0_w_bits_data(xbar_io_slaves_0_w_bits_data),
+ .io_slaves_0_w_bits_last(xbar_io_slaves_0_w_bits_last),
+ .io_slaves_0_w_bits_strb(xbar_io_slaves_0_w_bits_strb),
+ .io_slaves_0_w_bits_user(xbar_io_slaves_0_w_bits_user),
+ .io_slaves_0_b_ready(xbar_io_slaves_0_b_ready),
+ .io_slaves_0_b_valid(xbar_io_slaves_0_b_valid),
+ .io_slaves_0_b_bits_resp(xbar_io_slaves_0_b_bits_resp),
+ .io_slaves_0_b_bits_id(xbar_io_slaves_0_b_bits_id),
+ .io_slaves_0_b_bits_user(xbar_io_slaves_0_b_bits_user),
+ .io_slaves_0_ar_ready(xbar_io_slaves_0_ar_ready),
+ .io_slaves_0_ar_valid(xbar_io_slaves_0_ar_valid),
+ .io_slaves_0_ar_bits_addr(xbar_io_slaves_0_ar_bits_addr),
+ .io_slaves_0_ar_bits_len(xbar_io_slaves_0_ar_bits_len),
+ .io_slaves_0_ar_bits_size(xbar_io_slaves_0_ar_bits_size),
+ .io_slaves_0_ar_bits_burst(xbar_io_slaves_0_ar_bits_burst),
+ .io_slaves_0_ar_bits_lock(xbar_io_slaves_0_ar_bits_lock),
+ .io_slaves_0_ar_bits_cache(xbar_io_slaves_0_ar_bits_cache),
+ .io_slaves_0_ar_bits_prot(xbar_io_slaves_0_ar_bits_prot),
+ .io_slaves_0_ar_bits_qos(xbar_io_slaves_0_ar_bits_qos),
+ .io_slaves_0_ar_bits_region(xbar_io_slaves_0_ar_bits_region),
+ .io_slaves_0_ar_bits_id(xbar_io_slaves_0_ar_bits_id),
+ .io_slaves_0_ar_bits_user(xbar_io_slaves_0_ar_bits_user),
+ .io_slaves_0_r_ready(xbar_io_slaves_0_r_ready),
+ .io_slaves_0_r_valid(xbar_io_slaves_0_r_valid),
+ .io_slaves_0_r_bits_resp(xbar_io_slaves_0_r_bits_resp),
+ .io_slaves_0_r_bits_data(xbar_io_slaves_0_r_bits_data),
+ .io_slaves_0_r_bits_last(xbar_io_slaves_0_r_bits_last),
+ .io_slaves_0_r_bits_id(xbar_io_slaves_0_r_bits_id),
+ .io_slaves_0_r_bits_user(xbar_io_slaves_0_r_bits_user),
+ .io_slaves_1_aw_ready(xbar_io_slaves_1_aw_ready),
+ .io_slaves_1_aw_valid(xbar_io_slaves_1_aw_valid),
+ .io_slaves_1_aw_bits_addr(xbar_io_slaves_1_aw_bits_addr),
+ .io_slaves_1_aw_bits_len(xbar_io_slaves_1_aw_bits_len),
+ .io_slaves_1_aw_bits_size(xbar_io_slaves_1_aw_bits_size),
+ .io_slaves_1_aw_bits_burst(xbar_io_slaves_1_aw_bits_burst),
+ .io_slaves_1_aw_bits_lock(xbar_io_slaves_1_aw_bits_lock),
+ .io_slaves_1_aw_bits_cache(xbar_io_slaves_1_aw_bits_cache),
+ .io_slaves_1_aw_bits_prot(xbar_io_slaves_1_aw_bits_prot),
+ .io_slaves_1_aw_bits_qos(xbar_io_slaves_1_aw_bits_qos),
+ .io_slaves_1_aw_bits_region(xbar_io_slaves_1_aw_bits_region),
+ .io_slaves_1_aw_bits_id(xbar_io_slaves_1_aw_bits_id),
+ .io_slaves_1_aw_bits_user(xbar_io_slaves_1_aw_bits_user),
+ .io_slaves_1_w_ready(xbar_io_slaves_1_w_ready),
+ .io_slaves_1_w_valid(xbar_io_slaves_1_w_valid),
+ .io_slaves_1_w_bits_data(xbar_io_slaves_1_w_bits_data),
+ .io_slaves_1_w_bits_last(xbar_io_slaves_1_w_bits_last),
+ .io_slaves_1_w_bits_strb(xbar_io_slaves_1_w_bits_strb),
+ .io_slaves_1_w_bits_user(xbar_io_slaves_1_w_bits_user),
+ .io_slaves_1_b_ready(xbar_io_slaves_1_b_ready),
+ .io_slaves_1_b_valid(xbar_io_slaves_1_b_valid),
+ .io_slaves_1_b_bits_resp(xbar_io_slaves_1_b_bits_resp),
+ .io_slaves_1_b_bits_id(xbar_io_slaves_1_b_bits_id),
+ .io_slaves_1_b_bits_user(xbar_io_slaves_1_b_bits_user),
+ .io_slaves_1_ar_ready(xbar_io_slaves_1_ar_ready),
+ .io_slaves_1_ar_valid(xbar_io_slaves_1_ar_valid),
+ .io_slaves_1_ar_bits_addr(xbar_io_slaves_1_ar_bits_addr),
+ .io_slaves_1_ar_bits_len(xbar_io_slaves_1_ar_bits_len),
+ .io_slaves_1_ar_bits_size(xbar_io_slaves_1_ar_bits_size),
+ .io_slaves_1_ar_bits_burst(xbar_io_slaves_1_ar_bits_burst),
+ .io_slaves_1_ar_bits_lock(xbar_io_slaves_1_ar_bits_lock),
+ .io_slaves_1_ar_bits_cache(xbar_io_slaves_1_ar_bits_cache),
+ .io_slaves_1_ar_bits_prot(xbar_io_slaves_1_ar_bits_prot),
+ .io_slaves_1_ar_bits_qos(xbar_io_slaves_1_ar_bits_qos),
+ .io_slaves_1_ar_bits_region(xbar_io_slaves_1_ar_bits_region),
+ .io_slaves_1_ar_bits_id(xbar_io_slaves_1_ar_bits_id),
+ .io_slaves_1_ar_bits_user(xbar_io_slaves_1_ar_bits_user),
+ .io_slaves_1_r_ready(xbar_io_slaves_1_r_ready),
+ .io_slaves_1_r_valid(xbar_io_slaves_1_r_valid),
+ .io_slaves_1_r_bits_resp(xbar_io_slaves_1_r_bits_resp),
+ .io_slaves_1_r_bits_data(xbar_io_slaves_1_r_bits_data),
+ .io_slaves_1_r_bits_last(xbar_io_slaves_1_r_bits_last),
+ .io_slaves_1_r_bits_id(xbar_io_slaves_1_r_bits_id),
+ .io_slaves_1_r_bits_user(xbar_io_slaves_1_r_bits_user),
+ .io_slaves_2_aw_ready(xbar_io_slaves_2_aw_ready),
+ .io_slaves_2_aw_valid(xbar_io_slaves_2_aw_valid),
+ .io_slaves_2_aw_bits_addr(xbar_io_slaves_2_aw_bits_addr),
+ .io_slaves_2_aw_bits_len(xbar_io_slaves_2_aw_bits_len),
+ .io_slaves_2_aw_bits_size(xbar_io_slaves_2_aw_bits_size),
+ .io_slaves_2_aw_bits_burst(xbar_io_slaves_2_aw_bits_burst),
+ .io_slaves_2_aw_bits_lock(xbar_io_slaves_2_aw_bits_lock),
+ .io_slaves_2_aw_bits_cache(xbar_io_slaves_2_aw_bits_cache),
+ .io_slaves_2_aw_bits_prot(xbar_io_slaves_2_aw_bits_prot),
+ .io_slaves_2_aw_bits_qos(xbar_io_slaves_2_aw_bits_qos),
+ .io_slaves_2_aw_bits_region(xbar_io_slaves_2_aw_bits_region),
+ .io_slaves_2_aw_bits_id(xbar_io_slaves_2_aw_bits_id),
+ .io_slaves_2_aw_bits_user(xbar_io_slaves_2_aw_bits_user),
+ .io_slaves_2_w_ready(xbar_io_slaves_2_w_ready),
+ .io_slaves_2_w_valid(xbar_io_slaves_2_w_valid),
+ .io_slaves_2_w_bits_data(xbar_io_slaves_2_w_bits_data),
+ .io_slaves_2_w_bits_last(xbar_io_slaves_2_w_bits_last),
+ .io_slaves_2_w_bits_strb(xbar_io_slaves_2_w_bits_strb),
+ .io_slaves_2_w_bits_user(xbar_io_slaves_2_w_bits_user),
+ .io_slaves_2_b_ready(xbar_io_slaves_2_b_ready),
+ .io_slaves_2_b_valid(xbar_io_slaves_2_b_valid),
+ .io_slaves_2_b_bits_resp(xbar_io_slaves_2_b_bits_resp),
+ .io_slaves_2_b_bits_id(xbar_io_slaves_2_b_bits_id),
+ .io_slaves_2_b_bits_user(xbar_io_slaves_2_b_bits_user),
+ .io_slaves_2_ar_ready(xbar_io_slaves_2_ar_ready),
+ .io_slaves_2_ar_valid(xbar_io_slaves_2_ar_valid),
+ .io_slaves_2_ar_bits_addr(xbar_io_slaves_2_ar_bits_addr),
+ .io_slaves_2_ar_bits_len(xbar_io_slaves_2_ar_bits_len),
+ .io_slaves_2_ar_bits_size(xbar_io_slaves_2_ar_bits_size),
+ .io_slaves_2_ar_bits_burst(xbar_io_slaves_2_ar_bits_burst),
+ .io_slaves_2_ar_bits_lock(xbar_io_slaves_2_ar_bits_lock),
+ .io_slaves_2_ar_bits_cache(xbar_io_slaves_2_ar_bits_cache),
+ .io_slaves_2_ar_bits_prot(xbar_io_slaves_2_ar_bits_prot),
+ .io_slaves_2_ar_bits_qos(xbar_io_slaves_2_ar_bits_qos),
+ .io_slaves_2_ar_bits_region(xbar_io_slaves_2_ar_bits_region),
+ .io_slaves_2_ar_bits_id(xbar_io_slaves_2_ar_bits_id),
+ .io_slaves_2_ar_bits_user(xbar_io_slaves_2_ar_bits_user),
+ .io_slaves_2_r_ready(xbar_io_slaves_2_r_ready),
+ .io_slaves_2_r_valid(xbar_io_slaves_2_r_valid),
+ .io_slaves_2_r_bits_resp(xbar_io_slaves_2_r_bits_resp),
+ .io_slaves_2_r_bits_data(xbar_io_slaves_2_r_bits_data),
+ .io_slaves_2_r_bits_last(xbar_io_slaves_2_r_bits_last),
+ .io_slaves_2_r_bits_id(xbar_io_slaves_2_r_bits_id),
+ .io_slaves_2_r_bits_user(xbar_io_slaves_2_r_bits_user),
+ .io_slaves_3_aw_ready(xbar_io_slaves_3_aw_ready),
+ .io_slaves_3_aw_valid(xbar_io_slaves_3_aw_valid),
+ .io_slaves_3_aw_bits_addr(xbar_io_slaves_3_aw_bits_addr),
+ .io_slaves_3_aw_bits_len(xbar_io_slaves_3_aw_bits_len),
+ .io_slaves_3_aw_bits_size(xbar_io_slaves_3_aw_bits_size),
+ .io_slaves_3_aw_bits_burst(xbar_io_slaves_3_aw_bits_burst),
+ .io_slaves_3_aw_bits_lock(xbar_io_slaves_3_aw_bits_lock),
+ .io_slaves_3_aw_bits_cache(xbar_io_slaves_3_aw_bits_cache),
+ .io_slaves_3_aw_bits_prot(xbar_io_slaves_3_aw_bits_prot),
+ .io_slaves_3_aw_bits_qos(xbar_io_slaves_3_aw_bits_qos),
+ .io_slaves_3_aw_bits_region(xbar_io_slaves_3_aw_bits_region),
+ .io_slaves_3_aw_bits_id(xbar_io_slaves_3_aw_bits_id),
+ .io_slaves_3_aw_bits_user(xbar_io_slaves_3_aw_bits_user),
+ .io_slaves_3_w_ready(xbar_io_slaves_3_w_ready),
+ .io_slaves_3_w_valid(xbar_io_slaves_3_w_valid),
+ .io_slaves_3_w_bits_data(xbar_io_slaves_3_w_bits_data),
+ .io_slaves_3_w_bits_last(xbar_io_slaves_3_w_bits_last),
+ .io_slaves_3_w_bits_strb(xbar_io_slaves_3_w_bits_strb),
+ .io_slaves_3_w_bits_user(xbar_io_slaves_3_w_bits_user),
+ .io_slaves_3_b_ready(xbar_io_slaves_3_b_ready),
+ .io_slaves_3_b_valid(xbar_io_slaves_3_b_valid),
+ .io_slaves_3_b_bits_resp(xbar_io_slaves_3_b_bits_resp),
+ .io_slaves_3_b_bits_id(xbar_io_slaves_3_b_bits_id),
+ .io_slaves_3_b_bits_user(xbar_io_slaves_3_b_bits_user),
+ .io_slaves_3_ar_ready(xbar_io_slaves_3_ar_ready),
+ .io_slaves_3_ar_valid(xbar_io_slaves_3_ar_valid),
+ .io_slaves_3_ar_bits_addr(xbar_io_slaves_3_ar_bits_addr),
+ .io_slaves_3_ar_bits_len(xbar_io_slaves_3_ar_bits_len),
+ .io_slaves_3_ar_bits_size(xbar_io_slaves_3_ar_bits_size),
+ .io_slaves_3_ar_bits_burst(xbar_io_slaves_3_ar_bits_burst),
+ .io_slaves_3_ar_bits_lock(xbar_io_slaves_3_ar_bits_lock),
+ .io_slaves_3_ar_bits_cache(xbar_io_slaves_3_ar_bits_cache),
+ .io_slaves_3_ar_bits_prot(xbar_io_slaves_3_ar_bits_prot),
+ .io_slaves_3_ar_bits_qos(xbar_io_slaves_3_ar_bits_qos),
+ .io_slaves_3_ar_bits_region(xbar_io_slaves_3_ar_bits_region),
+ .io_slaves_3_ar_bits_id(xbar_io_slaves_3_ar_bits_id),
+ .io_slaves_3_ar_bits_user(xbar_io_slaves_3_ar_bits_user),
+ .io_slaves_3_r_ready(xbar_io_slaves_3_r_ready),
+ .io_slaves_3_r_valid(xbar_io_slaves_3_r_valid),
+ .io_slaves_3_r_bits_resp(xbar_io_slaves_3_r_bits_resp),
+ .io_slaves_3_r_bits_data(xbar_io_slaves_3_r_bits_data),
+ .io_slaves_3_r_bits_last(xbar_io_slaves_3_r_bits_last),
+ .io_slaves_3_r_bits_id(xbar_io_slaves_3_r_bits_id),
+ .io_slaves_3_r_bits_user(xbar_io_slaves_3_r_bits_user)
+ );
+ NastiRecursiveInterconnect_56 T_2869 (
+ .clk(T_2869_clk),
+ .reset(T_2869_reset),
+ .io_masters_0_aw_ready(T_2869_io_masters_0_aw_ready),
+ .io_masters_0_aw_valid(T_2869_io_masters_0_aw_valid),
+ .io_masters_0_aw_bits_addr(T_2869_io_masters_0_aw_bits_addr),
+ .io_masters_0_aw_bits_len(T_2869_io_masters_0_aw_bits_len),
+ .io_masters_0_aw_bits_size(T_2869_io_masters_0_aw_bits_size),
+ .io_masters_0_aw_bits_burst(T_2869_io_masters_0_aw_bits_burst),
+ .io_masters_0_aw_bits_lock(T_2869_io_masters_0_aw_bits_lock),
+ .io_masters_0_aw_bits_cache(T_2869_io_masters_0_aw_bits_cache),
+ .io_masters_0_aw_bits_prot(T_2869_io_masters_0_aw_bits_prot),
+ .io_masters_0_aw_bits_qos(T_2869_io_masters_0_aw_bits_qos),
+ .io_masters_0_aw_bits_region(T_2869_io_masters_0_aw_bits_region),
+ .io_masters_0_aw_bits_id(T_2869_io_masters_0_aw_bits_id),
+ .io_masters_0_aw_bits_user(T_2869_io_masters_0_aw_bits_user),
+ .io_masters_0_w_ready(T_2869_io_masters_0_w_ready),
+ .io_masters_0_w_valid(T_2869_io_masters_0_w_valid),
+ .io_masters_0_w_bits_data(T_2869_io_masters_0_w_bits_data),
+ .io_masters_0_w_bits_last(T_2869_io_masters_0_w_bits_last),
+ .io_masters_0_w_bits_strb(T_2869_io_masters_0_w_bits_strb),
+ .io_masters_0_w_bits_user(T_2869_io_masters_0_w_bits_user),
+ .io_masters_0_b_ready(T_2869_io_masters_0_b_ready),
+ .io_masters_0_b_valid(T_2869_io_masters_0_b_valid),
+ .io_masters_0_b_bits_resp(T_2869_io_masters_0_b_bits_resp),
+ .io_masters_0_b_bits_id(T_2869_io_masters_0_b_bits_id),
+ .io_masters_0_b_bits_user(T_2869_io_masters_0_b_bits_user),
+ .io_masters_0_ar_ready(T_2869_io_masters_0_ar_ready),
+ .io_masters_0_ar_valid(T_2869_io_masters_0_ar_valid),
+ .io_masters_0_ar_bits_addr(T_2869_io_masters_0_ar_bits_addr),
+ .io_masters_0_ar_bits_len(T_2869_io_masters_0_ar_bits_len),
+ .io_masters_0_ar_bits_size(T_2869_io_masters_0_ar_bits_size),
+ .io_masters_0_ar_bits_burst(T_2869_io_masters_0_ar_bits_burst),
+ .io_masters_0_ar_bits_lock(T_2869_io_masters_0_ar_bits_lock),
+ .io_masters_0_ar_bits_cache(T_2869_io_masters_0_ar_bits_cache),
+ .io_masters_0_ar_bits_prot(T_2869_io_masters_0_ar_bits_prot),
+ .io_masters_0_ar_bits_qos(T_2869_io_masters_0_ar_bits_qos),
+ .io_masters_0_ar_bits_region(T_2869_io_masters_0_ar_bits_region),
+ .io_masters_0_ar_bits_id(T_2869_io_masters_0_ar_bits_id),
+ .io_masters_0_ar_bits_user(T_2869_io_masters_0_ar_bits_user),
+ .io_masters_0_r_ready(T_2869_io_masters_0_r_ready),
+ .io_masters_0_r_valid(T_2869_io_masters_0_r_valid),
+ .io_masters_0_r_bits_resp(T_2869_io_masters_0_r_bits_resp),
+ .io_masters_0_r_bits_data(T_2869_io_masters_0_r_bits_data),
+ .io_masters_0_r_bits_last(T_2869_io_masters_0_r_bits_last),
+ .io_masters_0_r_bits_id(T_2869_io_masters_0_r_bits_id),
+ .io_masters_0_r_bits_user(T_2869_io_masters_0_r_bits_user),
+ .io_slaves_0_aw_ready(T_2869_io_slaves_0_aw_ready),
+ .io_slaves_0_aw_valid(T_2869_io_slaves_0_aw_valid),
+ .io_slaves_0_aw_bits_addr(T_2869_io_slaves_0_aw_bits_addr),
+ .io_slaves_0_aw_bits_len(T_2869_io_slaves_0_aw_bits_len),
+ .io_slaves_0_aw_bits_size(T_2869_io_slaves_0_aw_bits_size),
+ .io_slaves_0_aw_bits_burst(T_2869_io_slaves_0_aw_bits_burst),
+ .io_slaves_0_aw_bits_lock(T_2869_io_slaves_0_aw_bits_lock),
+ .io_slaves_0_aw_bits_cache(T_2869_io_slaves_0_aw_bits_cache),
+ .io_slaves_0_aw_bits_prot(T_2869_io_slaves_0_aw_bits_prot),
+ .io_slaves_0_aw_bits_qos(T_2869_io_slaves_0_aw_bits_qos),
+ .io_slaves_0_aw_bits_region(T_2869_io_slaves_0_aw_bits_region),
+ .io_slaves_0_aw_bits_id(T_2869_io_slaves_0_aw_bits_id),
+ .io_slaves_0_aw_bits_user(T_2869_io_slaves_0_aw_bits_user),
+ .io_slaves_0_w_ready(T_2869_io_slaves_0_w_ready),
+ .io_slaves_0_w_valid(T_2869_io_slaves_0_w_valid),
+ .io_slaves_0_w_bits_data(T_2869_io_slaves_0_w_bits_data),
+ .io_slaves_0_w_bits_last(T_2869_io_slaves_0_w_bits_last),
+ .io_slaves_0_w_bits_strb(T_2869_io_slaves_0_w_bits_strb),
+ .io_slaves_0_w_bits_user(T_2869_io_slaves_0_w_bits_user),
+ .io_slaves_0_b_ready(T_2869_io_slaves_0_b_ready),
+ .io_slaves_0_b_valid(T_2869_io_slaves_0_b_valid),
+ .io_slaves_0_b_bits_resp(T_2869_io_slaves_0_b_bits_resp),
+ .io_slaves_0_b_bits_id(T_2869_io_slaves_0_b_bits_id),
+ .io_slaves_0_b_bits_user(T_2869_io_slaves_0_b_bits_user),
+ .io_slaves_0_ar_ready(T_2869_io_slaves_0_ar_ready),
+ .io_slaves_0_ar_valid(T_2869_io_slaves_0_ar_valid),
+ .io_slaves_0_ar_bits_addr(T_2869_io_slaves_0_ar_bits_addr),
+ .io_slaves_0_ar_bits_len(T_2869_io_slaves_0_ar_bits_len),
+ .io_slaves_0_ar_bits_size(T_2869_io_slaves_0_ar_bits_size),
+ .io_slaves_0_ar_bits_burst(T_2869_io_slaves_0_ar_bits_burst),
+ .io_slaves_0_ar_bits_lock(T_2869_io_slaves_0_ar_bits_lock),
+ .io_slaves_0_ar_bits_cache(T_2869_io_slaves_0_ar_bits_cache),
+ .io_slaves_0_ar_bits_prot(T_2869_io_slaves_0_ar_bits_prot),
+ .io_slaves_0_ar_bits_qos(T_2869_io_slaves_0_ar_bits_qos),
+ .io_slaves_0_ar_bits_region(T_2869_io_slaves_0_ar_bits_region),
+ .io_slaves_0_ar_bits_id(T_2869_io_slaves_0_ar_bits_id),
+ .io_slaves_0_ar_bits_user(T_2869_io_slaves_0_ar_bits_user),
+ .io_slaves_0_r_ready(T_2869_io_slaves_0_r_ready),
+ .io_slaves_0_r_valid(T_2869_io_slaves_0_r_valid),
+ .io_slaves_0_r_bits_resp(T_2869_io_slaves_0_r_bits_resp),
+ .io_slaves_0_r_bits_data(T_2869_io_slaves_0_r_bits_data),
+ .io_slaves_0_r_bits_last(T_2869_io_slaves_0_r_bits_last),
+ .io_slaves_0_r_bits_id(T_2869_io_slaves_0_r_bits_id),
+ .io_slaves_0_r_bits_user(T_2869_io_slaves_0_r_bits_user),
+ .io_slaves_1_aw_ready(T_2869_io_slaves_1_aw_ready),
+ .io_slaves_1_aw_valid(T_2869_io_slaves_1_aw_valid),
+ .io_slaves_1_aw_bits_addr(T_2869_io_slaves_1_aw_bits_addr),
+ .io_slaves_1_aw_bits_len(T_2869_io_slaves_1_aw_bits_len),
+ .io_slaves_1_aw_bits_size(T_2869_io_slaves_1_aw_bits_size),
+ .io_slaves_1_aw_bits_burst(T_2869_io_slaves_1_aw_bits_burst),
+ .io_slaves_1_aw_bits_lock(T_2869_io_slaves_1_aw_bits_lock),
+ .io_slaves_1_aw_bits_cache(T_2869_io_slaves_1_aw_bits_cache),
+ .io_slaves_1_aw_bits_prot(T_2869_io_slaves_1_aw_bits_prot),
+ .io_slaves_1_aw_bits_qos(T_2869_io_slaves_1_aw_bits_qos),
+ .io_slaves_1_aw_bits_region(T_2869_io_slaves_1_aw_bits_region),
+ .io_slaves_1_aw_bits_id(T_2869_io_slaves_1_aw_bits_id),
+ .io_slaves_1_aw_bits_user(T_2869_io_slaves_1_aw_bits_user),
+ .io_slaves_1_w_ready(T_2869_io_slaves_1_w_ready),
+ .io_slaves_1_w_valid(T_2869_io_slaves_1_w_valid),
+ .io_slaves_1_w_bits_data(T_2869_io_slaves_1_w_bits_data),
+ .io_slaves_1_w_bits_last(T_2869_io_slaves_1_w_bits_last),
+ .io_slaves_1_w_bits_strb(T_2869_io_slaves_1_w_bits_strb),
+ .io_slaves_1_w_bits_user(T_2869_io_slaves_1_w_bits_user),
+ .io_slaves_1_b_ready(T_2869_io_slaves_1_b_ready),
+ .io_slaves_1_b_valid(T_2869_io_slaves_1_b_valid),
+ .io_slaves_1_b_bits_resp(T_2869_io_slaves_1_b_bits_resp),
+ .io_slaves_1_b_bits_id(T_2869_io_slaves_1_b_bits_id),
+ .io_slaves_1_b_bits_user(T_2869_io_slaves_1_b_bits_user),
+ .io_slaves_1_ar_ready(T_2869_io_slaves_1_ar_ready),
+ .io_slaves_1_ar_valid(T_2869_io_slaves_1_ar_valid),
+ .io_slaves_1_ar_bits_addr(T_2869_io_slaves_1_ar_bits_addr),
+ .io_slaves_1_ar_bits_len(T_2869_io_slaves_1_ar_bits_len),
+ .io_slaves_1_ar_bits_size(T_2869_io_slaves_1_ar_bits_size),
+ .io_slaves_1_ar_bits_burst(T_2869_io_slaves_1_ar_bits_burst),
+ .io_slaves_1_ar_bits_lock(T_2869_io_slaves_1_ar_bits_lock),
+ .io_slaves_1_ar_bits_cache(T_2869_io_slaves_1_ar_bits_cache),
+ .io_slaves_1_ar_bits_prot(T_2869_io_slaves_1_ar_bits_prot),
+ .io_slaves_1_ar_bits_qos(T_2869_io_slaves_1_ar_bits_qos),
+ .io_slaves_1_ar_bits_region(T_2869_io_slaves_1_ar_bits_region),
+ .io_slaves_1_ar_bits_id(T_2869_io_slaves_1_ar_bits_id),
+ .io_slaves_1_ar_bits_user(T_2869_io_slaves_1_ar_bits_user),
+ .io_slaves_1_r_ready(T_2869_io_slaves_1_r_ready),
+ .io_slaves_1_r_valid(T_2869_io_slaves_1_r_valid),
+ .io_slaves_1_r_bits_resp(T_2869_io_slaves_1_r_bits_resp),
+ .io_slaves_1_r_bits_data(T_2869_io_slaves_1_r_bits_data),
+ .io_slaves_1_r_bits_last(T_2869_io_slaves_1_r_bits_last),
+ .io_slaves_1_r_bits_id(T_2869_io_slaves_1_r_bits_id),
+ .io_slaves_1_r_bits_user(T_2869_io_slaves_1_r_bits_user),
+ .io_slaves_2_aw_ready(T_2869_io_slaves_2_aw_ready),
+ .io_slaves_2_aw_valid(T_2869_io_slaves_2_aw_valid),
+ .io_slaves_2_aw_bits_addr(T_2869_io_slaves_2_aw_bits_addr),
+ .io_slaves_2_aw_bits_len(T_2869_io_slaves_2_aw_bits_len),
+ .io_slaves_2_aw_bits_size(T_2869_io_slaves_2_aw_bits_size),
+ .io_slaves_2_aw_bits_burst(T_2869_io_slaves_2_aw_bits_burst),
+ .io_slaves_2_aw_bits_lock(T_2869_io_slaves_2_aw_bits_lock),
+ .io_slaves_2_aw_bits_cache(T_2869_io_slaves_2_aw_bits_cache),
+ .io_slaves_2_aw_bits_prot(T_2869_io_slaves_2_aw_bits_prot),
+ .io_slaves_2_aw_bits_qos(T_2869_io_slaves_2_aw_bits_qos),
+ .io_slaves_2_aw_bits_region(T_2869_io_slaves_2_aw_bits_region),
+ .io_slaves_2_aw_bits_id(T_2869_io_slaves_2_aw_bits_id),
+ .io_slaves_2_aw_bits_user(T_2869_io_slaves_2_aw_bits_user),
+ .io_slaves_2_w_ready(T_2869_io_slaves_2_w_ready),
+ .io_slaves_2_w_valid(T_2869_io_slaves_2_w_valid),
+ .io_slaves_2_w_bits_data(T_2869_io_slaves_2_w_bits_data),
+ .io_slaves_2_w_bits_last(T_2869_io_slaves_2_w_bits_last),
+ .io_slaves_2_w_bits_strb(T_2869_io_slaves_2_w_bits_strb),
+ .io_slaves_2_w_bits_user(T_2869_io_slaves_2_w_bits_user),
+ .io_slaves_2_b_ready(T_2869_io_slaves_2_b_ready),
+ .io_slaves_2_b_valid(T_2869_io_slaves_2_b_valid),
+ .io_slaves_2_b_bits_resp(T_2869_io_slaves_2_b_bits_resp),
+ .io_slaves_2_b_bits_id(T_2869_io_slaves_2_b_bits_id),
+ .io_slaves_2_b_bits_user(T_2869_io_slaves_2_b_bits_user),
+ .io_slaves_2_ar_ready(T_2869_io_slaves_2_ar_ready),
+ .io_slaves_2_ar_valid(T_2869_io_slaves_2_ar_valid),
+ .io_slaves_2_ar_bits_addr(T_2869_io_slaves_2_ar_bits_addr),
+ .io_slaves_2_ar_bits_len(T_2869_io_slaves_2_ar_bits_len),
+ .io_slaves_2_ar_bits_size(T_2869_io_slaves_2_ar_bits_size),
+ .io_slaves_2_ar_bits_burst(T_2869_io_slaves_2_ar_bits_burst),
+ .io_slaves_2_ar_bits_lock(T_2869_io_slaves_2_ar_bits_lock),
+ .io_slaves_2_ar_bits_cache(T_2869_io_slaves_2_ar_bits_cache),
+ .io_slaves_2_ar_bits_prot(T_2869_io_slaves_2_ar_bits_prot),
+ .io_slaves_2_ar_bits_qos(T_2869_io_slaves_2_ar_bits_qos),
+ .io_slaves_2_ar_bits_region(T_2869_io_slaves_2_ar_bits_region),
+ .io_slaves_2_ar_bits_id(T_2869_io_slaves_2_ar_bits_id),
+ .io_slaves_2_ar_bits_user(T_2869_io_slaves_2_ar_bits_user),
+ .io_slaves_2_r_ready(T_2869_io_slaves_2_r_ready),
+ .io_slaves_2_r_valid(T_2869_io_slaves_2_r_valid),
+ .io_slaves_2_r_bits_resp(T_2869_io_slaves_2_r_bits_resp),
+ .io_slaves_2_r_bits_data(T_2869_io_slaves_2_r_bits_data),
+ .io_slaves_2_r_bits_last(T_2869_io_slaves_2_r_bits_last),
+ .io_slaves_2_r_bits_id(T_2869_io_slaves_2_r_bits_id),
+ .io_slaves_2_r_bits_user(T_2869_io_slaves_2_r_bits_user)
+ );
+ NastiErrorSlave_40 T_2870 (
+ .clk(T_2870_clk),
+ .reset(T_2870_reset),
+ .io_aw_ready(T_2870_io_aw_ready),
+ .io_aw_valid(T_2870_io_aw_valid),
+ .io_aw_bits_addr(T_2870_io_aw_bits_addr),
+ .io_aw_bits_len(T_2870_io_aw_bits_len),
+ .io_aw_bits_size(T_2870_io_aw_bits_size),
+ .io_aw_bits_burst(T_2870_io_aw_bits_burst),
+ .io_aw_bits_lock(T_2870_io_aw_bits_lock),
+ .io_aw_bits_cache(T_2870_io_aw_bits_cache),
+ .io_aw_bits_prot(T_2870_io_aw_bits_prot),
+ .io_aw_bits_qos(T_2870_io_aw_bits_qos),
+ .io_aw_bits_region(T_2870_io_aw_bits_region),
+ .io_aw_bits_id(T_2870_io_aw_bits_id),
+ .io_aw_bits_user(T_2870_io_aw_bits_user),
+ .io_w_ready(T_2870_io_w_ready),
+ .io_w_valid(T_2870_io_w_valid),
+ .io_w_bits_data(T_2870_io_w_bits_data),
+ .io_w_bits_last(T_2870_io_w_bits_last),
+ .io_w_bits_strb(T_2870_io_w_bits_strb),
+ .io_w_bits_user(T_2870_io_w_bits_user),
+ .io_b_ready(T_2870_io_b_ready),
+ .io_b_valid(T_2870_io_b_valid),
+ .io_b_bits_resp(T_2870_io_b_bits_resp),
+ .io_b_bits_id(T_2870_io_b_bits_id),
+ .io_b_bits_user(T_2870_io_b_bits_user),
+ .io_ar_ready(T_2870_io_ar_ready),
+ .io_ar_valid(T_2870_io_ar_valid),
+ .io_ar_bits_addr(T_2870_io_ar_bits_addr),
+ .io_ar_bits_len(T_2870_io_ar_bits_len),
+ .io_ar_bits_size(T_2870_io_ar_bits_size),
+ .io_ar_bits_burst(T_2870_io_ar_bits_burst),
+ .io_ar_bits_lock(T_2870_io_ar_bits_lock),
+ .io_ar_bits_cache(T_2870_io_ar_bits_cache),
+ .io_ar_bits_prot(T_2870_io_ar_bits_prot),
+ .io_ar_bits_qos(T_2870_io_ar_bits_qos),
+ .io_ar_bits_region(T_2870_io_ar_bits_region),
+ .io_ar_bits_id(T_2870_io_ar_bits_id),
+ .io_ar_bits_user(T_2870_io_ar_bits_user),
+ .io_r_ready(T_2870_io_r_ready),
+ .io_r_valid(T_2870_io_r_valid),
+ .io_r_bits_resp(T_2870_io_r_bits_resp),
+ .io_r_bits_data(T_2870_io_r_bits_data),
+ .io_r_bits_last(T_2870_io_r_bits_last),
+ .io_r_bits_id(T_2870_io_r_bits_id),
+ .io_r_bits_user(T_2870_io_r_bits_user)
+ );
+ assign io_masters_0_aw_ready = xbar_io_masters_0_aw_ready;
+ assign io_masters_0_w_ready = xbar_io_masters_0_w_ready;
+ assign io_masters_0_b_valid = xbar_io_masters_0_b_valid;
+ assign io_masters_0_b_bits_resp = xbar_io_masters_0_b_bits_resp;
+ assign io_masters_0_b_bits_id = xbar_io_masters_0_b_bits_id;
+ assign io_masters_0_b_bits_user = xbar_io_masters_0_b_bits_user;
+ assign io_masters_0_ar_ready = xbar_io_masters_0_ar_ready;
+ assign io_masters_0_r_valid = xbar_io_masters_0_r_valid;
+ assign io_masters_0_r_bits_resp = xbar_io_masters_0_r_bits_resp;
+ assign io_masters_0_r_bits_data = xbar_io_masters_0_r_bits_data;
+ assign io_masters_0_r_bits_last = xbar_io_masters_0_r_bits_last;
+ assign io_masters_0_r_bits_id = xbar_io_masters_0_r_bits_id;
+ assign io_masters_0_r_bits_user = xbar_io_masters_0_r_bits_user;
+ assign io_masters_1_aw_ready = xbar_io_masters_1_aw_ready;
+ assign io_masters_1_w_ready = xbar_io_masters_1_w_ready;
+ assign io_masters_1_b_valid = xbar_io_masters_1_b_valid;
+ assign io_masters_1_b_bits_resp = xbar_io_masters_1_b_bits_resp;
+ assign io_masters_1_b_bits_id = xbar_io_masters_1_b_bits_id;
+ assign io_masters_1_b_bits_user = xbar_io_masters_1_b_bits_user;
+ assign io_masters_1_ar_ready = xbar_io_masters_1_ar_ready;
+ assign io_masters_1_r_valid = xbar_io_masters_1_r_valid;
+ assign io_masters_1_r_bits_resp = xbar_io_masters_1_r_bits_resp;
+ assign io_masters_1_r_bits_data = xbar_io_masters_1_r_bits_data;
+ assign io_masters_1_r_bits_last = xbar_io_masters_1_r_bits_last;
+ assign io_masters_1_r_bits_id = xbar_io_masters_1_r_bits_id;
+ assign io_masters_1_r_bits_user = xbar_io_masters_1_r_bits_user;
+ assign io_slaves_0_aw_valid = xbar_io_slaves_0_aw_valid;
+ assign io_slaves_0_aw_bits_addr = xbar_io_slaves_0_aw_bits_addr;
+ assign io_slaves_0_aw_bits_len = xbar_io_slaves_0_aw_bits_len;
+ assign io_slaves_0_aw_bits_size = xbar_io_slaves_0_aw_bits_size;
+ assign io_slaves_0_aw_bits_burst = xbar_io_slaves_0_aw_bits_burst;
+ assign io_slaves_0_aw_bits_lock = xbar_io_slaves_0_aw_bits_lock;
+ assign io_slaves_0_aw_bits_cache = xbar_io_slaves_0_aw_bits_cache;
+ assign io_slaves_0_aw_bits_prot = xbar_io_slaves_0_aw_bits_prot;
+ assign io_slaves_0_aw_bits_qos = xbar_io_slaves_0_aw_bits_qos;
+ assign io_slaves_0_aw_bits_region = xbar_io_slaves_0_aw_bits_region;
+ assign io_slaves_0_aw_bits_id = xbar_io_slaves_0_aw_bits_id;
+ assign io_slaves_0_aw_bits_user = xbar_io_slaves_0_aw_bits_user;
+ assign io_slaves_0_w_valid = xbar_io_slaves_0_w_valid;
+ assign io_slaves_0_w_bits_data = xbar_io_slaves_0_w_bits_data;
+ assign io_slaves_0_w_bits_last = xbar_io_slaves_0_w_bits_last;
+ assign io_slaves_0_w_bits_strb = xbar_io_slaves_0_w_bits_strb;
+ assign io_slaves_0_w_bits_user = xbar_io_slaves_0_w_bits_user;
+ assign io_slaves_0_b_ready = xbar_io_slaves_0_b_ready;
+ assign io_slaves_0_ar_valid = xbar_io_slaves_0_ar_valid;
+ assign io_slaves_0_ar_bits_addr = xbar_io_slaves_0_ar_bits_addr;
+ assign io_slaves_0_ar_bits_len = xbar_io_slaves_0_ar_bits_len;
+ assign io_slaves_0_ar_bits_size = xbar_io_slaves_0_ar_bits_size;
+ assign io_slaves_0_ar_bits_burst = xbar_io_slaves_0_ar_bits_burst;
+ assign io_slaves_0_ar_bits_lock = xbar_io_slaves_0_ar_bits_lock;
+ assign io_slaves_0_ar_bits_cache = xbar_io_slaves_0_ar_bits_cache;
+ assign io_slaves_0_ar_bits_prot = xbar_io_slaves_0_ar_bits_prot;
+ assign io_slaves_0_ar_bits_qos = xbar_io_slaves_0_ar_bits_qos;
+ assign io_slaves_0_ar_bits_region = xbar_io_slaves_0_ar_bits_region;
+ assign io_slaves_0_ar_bits_id = xbar_io_slaves_0_ar_bits_id;
+ assign io_slaves_0_ar_bits_user = xbar_io_slaves_0_ar_bits_user;
+ assign io_slaves_0_r_ready = xbar_io_slaves_0_r_ready;
+ assign io_slaves_1_aw_valid = T_2869_io_slaves_0_aw_valid;
+ assign io_slaves_1_aw_bits_addr = T_2869_io_slaves_0_aw_bits_addr;
+ assign io_slaves_1_aw_bits_len = T_2869_io_slaves_0_aw_bits_len;
+ assign io_slaves_1_aw_bits_size = T_2869_io_slaves_0_aw_bits_size;
+ assign io_slaves_1_aw_bits_burst = T_2869_io_slaves_0_aw_bits_burst;
+ assign io_slaves_1_aw_bits_lock = T_2869_io_slaves_0_aw_bits_lock;
+ assign io_slaves_1_aw_bits_cache = T_2869_io_slaves_0_aw_bits_cache;
+ assign io_slaves_1_aw_bits_prot = T_2869_io_slaves_0_aw_bits_prot;
+ assign io_slaves_1_aw_bits_qos = T_2869_io_slaves_0_aw_bits_qos;
+ assign io_slaves_1_aw_bits_region = T_2869_io_slaves_0_aw_bits_region;
+ assign io_slaves_1_aw_bits_id = T_2869_io_slaves_0_aw_bits_id;
+ assign io_slaves_1_aw_bits_user = T_2869_io_slaves_0_aw_bits_user;
+ assign io_slaves_1_w_valid = T_2869_io_slaves_0_w_valid;
+ assign io_slaves_1_w_bits_data = T_2869_io_slaves_0_w_bits_data;
+ assign io_slaves_1_w_bits_last = T_2869_io_slaves_0_w_bits_last;
+ assign io_slaves_1_w_bits_strb = T_2869_io_slaves_0_w_bits_strb;
+ assign io_slaves_1_w_bits_user = T_2869_io_slaves_0_w_bits_user;
+ assign io_slaves_1_b_ready = T_2869_io_slaves_0_b_ready;
+ assign io_slaves_1_ar_valid = T_2869_io_slaves_0_ar_valid;
+ assign io_slaves_1_ar_bits_addr = T_2869_io_slaves_0_ar_bits_addr;
+ assign io_slaves_1_ar_bits_len = T_2869_io_slaves_0_ar_bits_len;
+ assign io_slaves_1_ar_bits_size = T_2869_io_slaves_0_ar_bits_size;
+ assign io_slaves_1_ar_bits_burst = T_2869_io_slaves_0_ar_bits_burst;
+ assign io_slaves_1_ar_bits_lock = T_2869_io_slaves_0_ar_bits_lock;
+ assign io_slaves_1_ar_bits_cache = T_2869_io_slaves_0_ar_bits_cache;
+ assign io_slaves_1_ar_bits_prot = T_2869_io_slaves_0_ar_bits_prot;
+ assign io_slaves_1_ar_bits_qos = T_2869_io_slaves_0_ar_bits_qos;
+ assign io_slaves_1_ar_bits_region = T_2869_io_slaves_0_ar_bits_region;
+ assign io_slaves_1_ar_bits_id = T_2869_io_slaves_0_ar_bits_id;
+ assign io_slaves_1_ar_bits_user = T_2869_io_slaves_0_ar_bits_user;
+ assign io_slaves_1_r_ready = T_2869_io_slaves_0_r_ready;
+ assign io_slaves_2_aw_valid = T_2869_io_slaves_1_aw_valid;
+ assign io_slaves_2_aw_bits_addr = T_2869_io_slaves_1_aw_bits_addr;
+ assign io_slaves_2_aw_bits_len = T_2869_io_slaves_1_aw_bits_len;
+ assign io_slaves_2_aw_bits_size = T_2869_io_slaves_1_aw_bits_size;
+ assign io_slaves_2_aw_bits_burst = T_2869_io_slaves_1_aw_bits_burst;
+ assign io_slaves_2_aw_bits_lock = T_2869_io_slaves_1_aw_bits_lock;
+ assign io_slaves_2_aw_bits_cache = T_2869_io_slaves_1_aw_bits_cache;
+ assign io_slaves_2_aw_bits_prot = T_2869_io_slaves_1_aw_bits_prot;
+ assign io_slaves_2_aw_bits_qos = T_2869_io_slaves_1_aw_bits_qos;
+ assign io_slaves_2_aw_bits_region = T_2869_io_slaves_1_aw_bits_region;
+ assign io_slaves_2_aw_bits_id = T_2869_io_slaves_1_aw_bits_id;
+ assign io_slaves_2_aw_bits_user = T_2869_io_slaves_1_aw_bits_user;
+ assign io_slaves_2_w_valid = T_2869_io_slaves_1_w_valid;
+ assign io_slaves_2_w_bits_data = T_2869_io_slaves_1_w_bits_data;
+ assign io_slaves_2_w_bits_last = T_2869_io_slaves_1_w_bits_last;
+ assign io_slaves_2_w_bits_strb = T_2869_io_slaves_1_w_bits_strb;
+ assign io_slaves_2_w_bits_user = T_2869_io_slaves_1_w_bits_user;
+ assign io_slaves_2_b_ready = T_2869_io_slaves_1_b_ready;
+ assign io_slaves_2_ar_valid = T_2869_io_slaves_1_ar_valid;
+ assign io_slaves_2_ar_bits_addr = T_2869_io_slaves_1_ar_bits_addr;
+ assign io_slaves_2_ar_bits_len = T_2869_io_slaves_1_ar_bits_len;
+ assign io_slaves_2_ar_bits_size = T_2869_io_slaves_1_ar_bits_size;
+ assign io_slaves_2_ar_bits_burst = T_2869_io_slaves_1_ar_bits_burst;
+ assign io_slaves_2_ar_bits_lock = T_2869_io_slaves_1_ar_bits_lock;
+ assign io_slaves_2_ar_bits_cache = T_2869_io_slaves_1_ar_bits_cache;
+ assign io_slaves_2_ar_bits_prot = T_2869_io_slaves_1_ar_bits_prot;
+ assign io_slaves_2_ar_bits_qos = T_2869_io_slaves_1_ar_bits_qos;
+ assign io_slaves_2_ar_bits_region = T_2869_io_slaves_1_ar_bits_region;
+ assign io_slaves_2_ar_bits_id = T_2869_io_slaves_1_ar_bits_id;
+ assign io_slaves_2_ar_bits_user = T_2869_io_slaves_1_ar_bits_user;
+ assign io_slaves_2_r_ready = T_2869_io_slaves_1_r_ready;
+ assign io_slaves_3_aw_valid = T_2869_io_slaves_2_aw_valid;
+ assign io_slaves_3_aw_bits_addr = T_2869_io_slaves_2_aw_bits_addr;
+ assign io_slaves_3_aw_bits_len = T_2869_io_slaves_2_aw_bits_len;
+ assign io_slaves_3_aw_bits_size = T_2869_io_slaves_2_aw_bits_size;
+ assign io_slaves_3_aw_bits_burst = T_2869_io_slaves_2_aw_bits_burst;
+ assign io_slaves_3_aw_bits_lock = T_2869_io_slaves_2_aw_bits_lock;
+ assign io_slaves_3_aw_bits_cache = T_2869_io_slaves_2_aw_bits_cache;
+ assign io_slaves_3_aw_bits_prot = T_2869_io_slaves_2_aw_bits_prot;
+ assign io_slaves_3_aw_bits_qos = T_2869_io_slaves_2_aw_bits_qos;
+ assign io_slaves_3_aw_bits_region = T_2869_io_slaves_2_aw_bits_region;
+ assign io_slaves_3_aw_bits_id = T_2869_io_slaves_2_aw_bits_id;
+ assign io_slaves_3_aw_bits_user = T_2869_io_slaves_2_aw_bits_user;
+ assign io_slaves_3_w_valid = T_2869_io_slaves_2_w_valid;
+ assign io_slaves_3_w_bits_data = T_2869_io_slaves_2_w_bits_data;
+ assign io_slaves_3_w_bits_last = T_2869_io_slaves_2_w_bits_last;
+ assign io_slaves_3_w_bits_strb = T_2869_io_slaves_2_w_bits_strb;
+ assign io_slaves_3_w_bits_user = T_2869_io_slaves_2_w_bits_user;
+ assign io_slaves_3_b_ready = T_2869_io_slaves_2_b_ready;
+ assign io_slaves_3_ar_valid = T_2869_io_slaves_2_ar_valid;
+ assign io_slaves_3_ar_bits_addr = T_2869_io_slaves_2_ar_bits_addr;
+ assign io_slaves_3_ar_bits_len = T_2869_io_slaves_2_ar_bits_len;
+ assign io_slaves_3_ar_bits_size = T_2869_io_slaves_2_ar_bits_size;
+ assign io_slaves_3_ar_bits_burst = T_2869_io_slaves_2_ar_bits_burst;
+ assign io_slaves_3_ar_bits_lock = T_2869_io_slaves_2_ar_bits_lock;
+ assign io_slaves_3_ar_bits_cache = T_2869_io_slaves_2_ar_bits_cache;
+ assign io_slaves_3_ar_bits_prot = T_2869_io_slaves_2_ar_bits_prot;
+ assign io_slaves_3_ar_bits_qos = T_2869_io_slaves_2_ar_bits_qos;
+ assign io_slaves_3_ar_bits_region = T_2869_io_slaves_2_ar_bits_region;
+ assign io_slaves_3_ar_bits_id = T_2869_io_slaves_2_ar_bits_id;
+ assign io_slaves_3_ar_bits_user = T_2869_io_slaves_2_ar_bits_user;
+ assign io_slaves_3_r_ready = T_2869_io_slaves_2_r_ready;
+ assign io_slaves_4_aw_valid = xbar_io_slaves_3_aw_valid;
+ assign io_slaves_4_aw_bits_addr = xbar_io_slaves_3_aw_bits_addr;
+ assign io_slaves_4_aw_bits_len = xbar_io_slaves_3_aw_bits_len;
+ assign io_slaves_4_aw_bits_size = xbar_io_slaves_3_aw_bits_size;
+ assign io_slaves_4_aw_bits_burst = xbar_io_slaves_3_aw_bits_burst;
+ assign io_slaves_4_aw_bits_lock = xbar_io_slaves_3_aw_bits_lock;
+ assign io_slaves_4_aw_bits_cache = xbar_io_slaves_3_aw_bits_cache;
+ assign io_slaves_4_aw_bits_prot = xbar_io_slaves_3_aw_bits_prot;
+ assign io_slaves_4_aw_bits_qos = xbar_io_slaves_3_aw_bits_qos;
+ assign io_slaves_4_aw_bits_region = xbar_io_slaves_3_aw_bits_region;
+ assign io_slaves_4_aw_bits_id = xbar_io_slaves_3_aw_bits_id;
+ assign io_slaves_4_aw_bits_user = xbar_io_slaves_3_aw_bits_user;
+ assign io_slaves_4_w_valid = xbar_io_slaves_3_w_valid;
+ assign io_slaves_4_w_bits_data = xbar_io_slaves_3_w_bits_data;
+ assign io_slaves_4_w_bits_last = xbar_io_slaves_3_w_bits_last;
+ assign io_slaves_4_w_bits_strb = xbar_io_slaves_3_w_bits_strb;
+ assign io_slaves_4_w_bits_user = xbar_io_slaves_3_w_bits_user;
+ assign io_slaves_4_b_ready = xbar_io_slaves_3_b_ready;
+ assign io_slaves_4_ar_valid = xbar_io_slaves_3_ar_valid;
+ assign io_slaves_4_ar_bits_addr = xbar_io_slaves_3_ar_bits_addr;
+ assign io_slaves_4_ar_bits_len = xbar_io_slaves_3_ar_bits_len;
+ assign io_slaves_4_ar_bits_size = xbar_io_slaves_3_ar_bits_size;
+ assign io_slaves_4_ar_bits_burst = xbar_io_slaves_3_ar_bits_burst;
+ assign io_slaves_4_ar_bits_lock = xbar_io_slaves_3_ar_bits_lock;
+ assign io_slaves_4_ar_bits_cache = xbar_io_slaves_3_ar_bits_cache;
+ assign io_slaves_4_ar_bits_prot = xbar_io_slaves_3_ar_bits_prot;
+ assign io_slaves_4_ar_bits_qos = xbar_io_slaves_3_ar_bits_qos;
+ assign io_slaves_4_ar_bits_region = xbar_io_slaves_3_ar_bits_region;
+ assign io_slaves_4_ar_bits_id = xbar_io_slaves_3_ar_bits_id;
+ assign io_slaves_4_ar_bits_user = xbar_io_slaves_3_ar_bits_user;
+ assign io_slaves_4_r_ready = xbar_io_slaves_3_r_ready;
+ assign xbar_clk = clk;
+ assign xbar_reset = reset;
+ assign xbar_io_masters_0_aw_valid = io_masters_0_aw_valid;
+ assign xbar_io_masters_0_aw_bits_addr = io_masters_0_aw_bits_addr;
+ assign xbar_io_masters_0_aw_bits_len = io_masters_0_aw_bits_len;
+ assign xbar_io_masters_0_aw_bits_size = io_masters_0_aw_bits_size;
+ assign xbar_io_masters_0_aw_bits_burst = io_masters_0_aw_bits_burst;
+ assign xbar_io_masters_0_aw_bits_lock = io_masters_0_aw_bits_lock;
+ assign xbar_io_masters_0_aw_bits_cache = io_masters_0_aw_bits_cache;
+ assign xbar_io_masters_0_aw_bits_prot = io_masters_0_aw_bits_prot;
+ assign xbar_io_masters_0_aw_bits_qos = io_masters_0_aw_bits_qos;
+ assign xbar_io_masters_0_aw_bits_region = io_masters_0_aw_bits_region;
+ assign xbar_io_masters_0_aw_bits_id = io_masters_0_aw_bits_id;
+ assign xbar_io_masters_0_aw_bits_user = io_masters_0_aw_bits_user;
+ assign xbar_io_masters_0_w_valid = io_masters_0_w_valid;
+ assign xbar_io_masters_0_w_bits_data = io_masters_0_w_bits_data;
+ assign xbar_io_masters_0_w_bits_last = io_masters_0_w_bits_last;
+ assign xbar_io_masters_0_w_bits_strb = io_masters_0_w_bits_strb;
+ assign xbar_io_masters_0_w_bits_user = io_masters_0_w_bits_user;
+ assign xbar_io_masters_0_b_ready = io_masters_0_b_ready;
+ assign xbar_io_masters_0_ar_valid = io_masters_0_ar_valid;
+ assign xbar_io_masters_0_ar_bits_addr = io_masters_0_ar_bits_addr;
+ assign xbar_io_masters_0_ar_bits_len = io_masters_0_ar_bits_len;
+ assign xbar_io_masters_0_ar_bits_size = io_masters_0_ar_bits_size;
+ assign xbar_io_masters_0_ar_bits_burst = io_masters_0_ar_bits_burst;
+ assign xbar_io_masters_0_ar_bits_lock = io_masters_0_ar_bits_lock;
+ assign xbar_io_masters_0_ar_bits_cache = io_masters_0_ar_bits_cache;
+ assign xbar_io_masters_0_ar_bits_prot = io_masters_0_ar_bits_prot;
+ assign xbar_io_masters_0_ar_bits_qos = io_masters_0_ar_bits_qos;
+ assign xbar_io_masters_0_ar_bits_region = io_masters_0_ar_bits_region;
+ assign xbar_io_masters_0_ar_bits_id = io_masters_0_ar_bits_id;
+ assign xbar_io_masters_0_ar_bits_user = io_masters_0_ar_bits_user;
+ assign xbar_io_masters_0_r_ready = io_masters_0_r_ready;
+ assign xbar_io_masters_1_aw_valid = io_masters_1_aw_valid;
+ assign xbar_io_masters_1_aw_bits_addr = io_masters_1_aw_bits_addr;
+ assign xbar_io_masters_1_aw_bits_len = io_masters_1_aw_bits_len;
+ assign xbar_io_masters_1_aw_bits_size = io_masters_1_aw_bits_size;
+ assign xbar_io_masters_1_aw_bits_burst = io_masters_1_aw_bits_burst;
+ assign xbar_io_masters_1_aw_bits_lock = io_masters_1_aw_bits_lock;
+ assign xbar_io_masters_1_aw_bits_cache = io_masters_1_aw_bits_cache;
+ assign xbar_io_masters_1_aw_bits_prot = io_masters_1_aw_bits_prot;
+ assign xbar_io_masters_1_aw_bits_qos = io_masters_1_aw_bits_qos;
+ assign xbar_io_masters_1_aw_bits_region = io_masters_1_aw_bits_region;
+ assign xbar_io_masters_1_aw_bits_id = io_masters_1_aw_bits_id;
+ assign xbar_io_masters_1_aw_bits_user = io_masters_1_aw_bits_user;
+ assign xbar_io_masters_1_w_valid = io_masters_1_w_valid;
+ assign xbar_io_masters_1_w_bits_data = io_masters_1_w_bits_data;
+ assign xbar_io_masters_1_w_bits_last = io_masters_1_w_bits_last;
+ assign xbar_io_masters_1_w_bits_strb = io_masters_1_w_bits_strb;
+ assign xbar_io_masters_1_w_bits_user = io_masters_1_w_bits_user;
+ assign xbar_io_masters_1_b_ready = io_masters_1_b_ready;
+ assign xbar_io_masters_1_ar_valid = io_masters_1_ar_valid;
+ assign xbar_io_masters_1_ar_bits_addr = io_masters_1_ar_bits_addr;
+ assign xbar_io_masters_1_ar_bits_len = io_masters_1_ar_bits_len;
+ assign xbar_io_masters_1_ar_bits_size = io_masters_1_ar_bits_size;
+ assign xbar_io_masters_1_ar_bits_burst = io_masters_1_ar_bits_burst;
+ assign xbar_io_masters_1_ar_bits_lock = io_masters_1_ar_bits_lock;
+ assign xbar_io_masters_1_ar_bits_cache = io_masters_1_ar_bits_cache;
+ assign xbar_io_masters_1_ar_bits_prot = io_masters_1_ar_bits_prot;
+ assign xbar_io_masters_1_ar_bits_qos = io_masters_1_ar_bits_qos;
+ assign xbar_io_masters_1_ar_bits_region = io_masters_1_ar_bits_region;
+ assign xbar_io_masters_1_ar_bits_id = io_masters_1_ar_bits_id;
+ assign xbar_io_masters_1_ar_bits_user = io_masters_1_ar_bits_user;
+ assign xbar_io_masters_1_r_ready = io_masters_1_r_ready;
+ assign xbar_io_slaves_0_aw_ready = io_slaves_0_aw_ready;
+ assign xbar_io_slaves_0_w_ready = io_slaves_0_w_ready;
+ assign xbar_io_slaves_0_b_valid = io_slaves_0_b_valid;
+ assign xbar_io_slaves_0_b_bits_resp = io_slaves_0_b_bits_resp;
+ assign xbar_io_slaves_0_b_bits_id = io_slaves_0_b_bits_id;
+ assign xbar_io_slaves_0_b_bits_user = io_slaves_0_b_bits_user;
+ assign xbar_io_slaves_0_ar_ready = io_slaves_0_ar_ready;
+ assign xbar_io_slaves_0_r_valid = io_slaves_0_r_valid;
+ assign xbar_io_slaves_0_r_bits_resp = io_slaves_0_r_bits_resp;
+ assign xbar_io_slaves_0_r_bits_data = io_slaves_0_r_bits_data;
+ assign xbar_io_slaves_0_r_bits_last = io_slaves_0_r_bits_last;
+ assign xbar_io_slaves_0_r_bits_id = io_slaves_0_r_bits_id;
+ assign xbar_io_slaves_0_r_bits_user = io_slaves_0_r_bits_user;
+ assign xbar_io_slaves_1_aw_ready = T_2869_io_masters_0_aw_ready;
+ assign xbar_io_slaves_1_w_ready = T_2869_io_masters_0_w_ready;
+ assign xbar_io_slaves_1_b_valid = T_2869_io_masters_0_b_valid;
+ assign xbar_io_slaves_1_b_bits_resp = T_2869_io_masters_0_b_bits_resp;
+ assign xbar_io_slaves_1_b_bits_id = T_2869_io_masters_0_b_bits_id;
+ assign xbar_io_slaves_1_b_bits_user = T_2869_io_masters_0_b_bits_user;
+ assign xbar_io_slaves_1_ar_ready = T_2869_io_masters_0_ar_ready;
+ assign xbar_io_slaves_1_r_valid = T_2869_io_masters_0_r_valid;
+ assign xbar_io_slaves_1_r_bits_resp = T_2869_io_masters_0_r_bits_resp;
+ assign xbar_io_slaves_1_r_bits_data = T_2869_io_masters_0_r_bits_data;
+ assign xbar_io_slaves_1_r_bits_last = T_2869_io_masters_0_r_bits_last;
+ assign xbar_io_slaves_1_r_bits_id = T_2869_io_masters_0_r_bits_id;
+ assign xbar_io_slaves_1_r_bits_user = T_2869_io_masters_0_r_bits_user;
+ assign xbar_io_slaves_2_aw_ready = T_2870_io_aw_ready;
+ assign xbar_io_slaves_2_w_ready = T_2870_io_w_ready;
+ assign xbar_io_slaves_2_b_valid = T_2870_io_b_valid;
+ assign xbar_io_slaves_2_b_bits_resp = T_2870_io_b_bits_resp;
+ assign xbar_io_slaves_2_b_bits_id = T_2870_io_b_bits_id;
+ assign xbar_io_slaves_2_b_bits_user = T_2870_io_b_bits_user;
+ assign xbar_io_slaves_2_ar_ready = T_2870_io_ar_ready;
+ assign xbar_io_slaves_2_r_valid = T_2870_io_r_valid;
+ assign xbar_io_slaves_2_r_bits_resp = T_2870_io_r_bits_resp;
+ assign xbar_io_slaves_2_r_bits_data = T_2870_io_r_bits_data;
+ assign xbar_io_slaves_2_r_bits_last = T_2870_io_r_bits_last;
+ assign xbar_io_slaves_2_r_bits_id = T_2870_io_r_bits_id;
+ assign xbar_io_slaves_2_r_bits_user = T_2870_io_r_bits_user;
+ assign xbar_io_slaves_3_aw_ready = io_slaves_4_aw_ready;
+ assign xbar_io_slaves_3_w_ready = io_slaves_4_w_ready;
+ assign xbar_io_slaves_3_b_valid = io_slaves_4_b_valid;
+ assign xbar_io_slaves_3_b_bits_resp = io_slaves_4_b_bits_resp;
+ assign xbar_io_slaves_3_b_bits_id = io_slaves_4_b_bits_id;
+ assign xbar_io_slaves_3_b_bits_user = io_slaves_4_b_bits_user;
+ assign xbar_io_slaves_3_ar_ready = io_slaves_4_ar_ready;
+ assign xbar_io_slaves_3_r_valid = io_slaves_4_r_valid;
+ assign xbar_io_slaves_3_r_bits_resp = io_slaves_4_r_bits_resp;
+ assign xbar_io_slaves_3_r_bits_data = io_slaves_4_r_bits_data;
+ assign xbar_io_slaves_3_r_bits_last = io_slaves_4_r_bits_last;
+ assign xbar_io_slaves_3_r_bits_id = io_slaves_4_r_bits_id;
+ assign xbar_io_slaves_3_r_bits_user = io_slaves_4_r_bits_user;
+ assign T_2869_clk = clk;
+ assign T_2869_reset = reset;
+ assign T_2869_io_masters_0_aw_valid = xbar_io_slaves_1_aw_valid;
+ assign T_2869_io_masters_0_aw_bits_addr = xbar_io_slaves_1_aw_bits_addr;
+ assign T_2869_io_masters_0_aw_bits_len = xbar_io_slaves_1_aw_bits_len;
+ assign T_2869_io_masters_0_aw_bits_size = xbar_io_slaves_1_aw_bits_size;
+ assign T_2869_io_masters_0_aw_bits_burst = xbar_io_slaves_1_aw_bits_burst;
+ assign T_2869_io_masters_0_aw_bits_lock = xbar_io_slaves_1_aw_bits_lock;
+ assign T_2869_io_masters_0_aw_bits_cache = xbar_io_slaves_1_aw_bits_cache;
+ assign T_2869_io_masters_0_aw_bits_prot = xbar_io_slaves_1_aw_bits_prot;
+ assign T_2869_io_masters_0_aw_bits_qos = xbar_io_slaves_1_aw_bits_qos;
+ assign T_2869_io_masters_0_aw_bits_region = xbar_io_slaves_1_aw_bits_region;
+ assign T_2869_io_masters_0_aw_bits_id = xbar_io_slaves_1_aw_bits_id;
+ assign T_2869_io_masters_0_aw_bits_user = xbar_io_slaves_1_aw_bits_user;
+ assign T_2869_io_masters_0_w_valid = xbar_io_slaves_1_w_valid;
+ assign T_2869_io_masters_0_w_bits_data = xbar_io_slaves_1_w_bits_data;
+ assign T_2869_io_masters_0_w_bits_last = xbar_io_slaves_1_w_bits_last;
+ assign T_2869_io_masters_0_w_bits_strb = xbar_io_slaves_1_w_bits_strb;
+ assign T_2869_io_masters_0_w_bits_user = xbar_io_slaves_1_w_bits_user;
+ assign T_2869_io_masters_0_b_ready = xbar_io_slaves_1_b_ready;
+ assign T_2869_io_masters_0_ar_valid = xbar_io_slaves_1_ar_valid;
+ assign T_2869_io_masters_0_ar_bits_addr = xbar_io_slaves_1_ar_bits_addr;
+ assign T_2869_io_masters_0_ar_bits_len = xbar_io_slaves_1_ar_bits_len;
+ assign T_2869_io_masters_0_ar_bits_size = xbar_io_slaves_1_ar_bits_size;
+ assign T_2869_io_masters_0_ar_bits_burst = xbar_io_slaves_1_ar_bits_burst;
+ assign T_2869_io_masters_0_ar_bits_lock = xbar_io_slaves_1_ar_bits_lock;
+ assign T_2869_io_masters_0_ar_bits_cache = xbar_io_slaves_1_ar_bits_cache;
+ assign T_2869_io_masters_0_ar_bits_prot = xbar_io_slaves_1_ar_bits_prot;
+ assign T_2869_io_masters_0_ar_bits_qos = xbar_io_slaves_1_ar_bits_qos;
+ assign T_2869_io_masters_0_ar_bits_region = xbar_io_slaves_1_ar_bits_region;
+ assign T_2869_io_masters_0_ar_bits_id = xbar_io_slaves_1_ar_bits_id;
+ assign T_2869_io_masters_0_ar_bits_user = xbar_io_slaves_1_ar_bits_user;
+ assign T_2869_io_masters_0_r_ready = xbar_io_slaves_1_r_ready;
+ assign T_2869_io_slaves_0_aw_ready = io_slaves_1_aw_ready;
+ assign T_2869_io_slaves_0_w_ready = io_slaves_1_w_ready;
+ assign T_2869_io_slaves_0_b_valid = io_slaves_1_b_valid;
+ assign T_2869_io_slaves_0_b_bits_resp = io_slaves_1_b_bits_resp;
+ assign T_2869_io_slaves_0_b_bits_id = io_slaves_1_b_bits_id;
+ assign T_2869_io_slaves_0_b_bits_user = io_slaves_1_b_bits_user;
+ assign T_2869_io_slaves_0_ar_ready = io_slaves_1_ar_ready;
+ assign T_2869_io_slaves_0_r_valid = io_slaves_1_r_valid;
+ assign T_2869_io_slaves_0_r_bits_resp = io_slaves_1_r_bits_resp;
+ assign T_2869_io_slaves_0_r_bits_data = io_slaves_1_r_bits_data;
+ assign T_2869_io_slaves_0_r_bits_last = io_slaves_1_r_bits_last;
+ assign T_2869_io_slaves_0_r_bits_id = io_slaves_1_r_bits_id;
+ assign T_2869_io_slaves_0_r_bits_user = io_slaves_1_r_bits_user;
+ assign T_2869_io_slaves_1_aw_ready = io_slaves_2_aw_ready;
+ assign T_2869_io_slaves_1_w_ready = io_slaves_2_w_ready;
+ assign T_2869_io_slaves_1_b_valid = io_slaves_2_b_valid;
+ assign T_2869_io_slaves_1_b_bits_resp = io_slaves_2_b_bits_resp;
+ assign T_2869_io_slaves_1_b_bits_id = io_slaves_2_b_bits_id;
+ assign T_2869_io_slaves_1_b_bits_user = io_slaves_2_b_bits_user;
+ assign T_2869_io_slaves_1_ar_ready = io_slaves_2_ar_ready;
+ assign T_2869_io_slaves_1_r_valid = io_slaves_2_r_valid;
+ assign T_2869_io_slaves_1_r_bits_resp = io_slaves_2_r_bits_resp;
+ assign T_2869_io_slaves_1_r_bits_data = io_slaves_2_r_bits_data;
+ assign T_2869_io_slaves_1_r_bits_last = io_slaves_2_r_bits_last;
+ assign T_2869_io_slaves_1_r_bits_id = io_slaves_2_r_bits_id;
+ assign T_2869_io_slaves_1_r_bits_user = io_slaves_2_r_bits_user;
+ assign T_2869_io_slaves_2_aw_ready = io_slaves_3_aw_ready;
+ assign T_2869_io_slaves_2_w_ready = io_slaves_3_w_ready;
+ assign T_2869_io_slaves_2_b_valid = io_slaves_3_b_valid;
+ assign T_2869_io_slaves_2_b_bits_resp = io_slaves_3_b_bits_resp;
+ assign T_2869_io_slaves_2_b_bits_id = io_slaves_3_b_bits_id;
+ assign T_2869_io_slaves_2_b_bits_user = io_slaves_3_b_bits_user;
+ assign T_2869_io_slaves_2_ar_ready = io_slaves_3_ar_ready;
+ assign T_2869_io_slaves_2_r_valid = io_slaves_3_r_valid;
+ assign T_2869_io_slaves_2_r_bits_resp = io_slaves_3_r_bits_resp;
+ assign T_2869_io_slaves_2_r_bits_data = io_slaves_3_r_bits_data;
+ assign T_2869_io_slaves_2_r_bits_last = io_slaves_3_r_bits_last;
+ assign T_2869_io_slaves_2_r_bits_id = io_slaves_3_r_bits_id;
+ assign T_2869_io_slaves_2_r_bits_user = io_slaves_3_r_bits_user;
+ assign T_2870_clk = clk;
+ assign T_2870_reset = reset;
+ assign T_2870_io_aw_valid = xbar_io_slaves_2_aw_valid;
+ assign T_2870_io_aw_bits_addr = xbar_io_slaves_2_aw_bits_addr;
+ assign T_2870_io_aw_bits_len = xbar_io_slaves_2_aw_bits_len;
+ assign T_2870_io_aw_bits_size = xbar_io_slaves_2_aw_bits_size;
+ assign T_2870_io_aw_bits_burst = xbar_io_slaves_2_aw_bits_burst;
+ assign T_2870_io_aw_bits_lock = xbar_io_slaves_2_aw_bits_lock;
+ assign T_2870_io_aw_bits_cache = xbar_io_slaves_2_aw_bits_cache;
+ assign T_2870_io_aw_bits_prot = xbar_io_slaves_2_aw_bits_prot;
+ assign T_2870_io_aw_bits_qos = xbar_io_slaves_2_aw_bits_qos;
+ assign T_2870_io_aw_bits_region = xbar_io_slaves_2_aw_bits_region;
+ assign T_2870_io_aw_bits_id = xbar_io_slaves_2_aw_bits_id;
+ assign T_2870_io_aw_bits_user = xbar_io_slaves_2_aw_bits_user;
+ assign T_2870_io_w_valid = xbar_io_slaves_2_w_valid;
+ assign T_2870_io_w_bits_data = xbar_io_slaves_2_w_bits_data;
+ assign T_2870_io_w_bits_last = xbar_io_slaves_2_w_bits_last;
+ assign T_2870_io_w_bits_strb = xbar_io_slaves_2_w_bits_strb;
+ assign T_2870_io_w_bits_user = xbar_io_slaves_2_w_bits_user;
+ assign T_2870_io_b_ready = xbar_io_slaves_2_b_ready;
+ assign T_2870_io_ar_valid = xbar_io_slaves_2_ar_valid;
+ assign T_2870_io_ar_bits_addr = xbar_io_slaves_2_ar_bits_addr;
+ assign T_2870_io_ar_bits_len = xbar_io_slaves_2_ar_bits_len;
+ assign T_2870_io_ar_bits_size = xbar_io_slaves_2_ar_bits_size;
+ assign T_2870_io_ar_bits_burst = xbar_io_slaves_2_ar_bits_burst;
+ assign T_2870_io_ar_bits_lock = xbar_io_slaves_2_ar_bits_lock;
+ assign T_2870_io_ar_bits_cache = xbar_io_slaves_2_ar_bits_cache;
+ assign T_2870_io_ar_bits_prot = xbar_io_slaves_2_ar_bits_prot;
+ assign T_2870_io_ar_bits_qos = xbar_io_slaves_2_ar_bits_qos;
+ assign T_2870_io_ar_bits_region = xbar_io_slaves_2_ar_bits_region;
+ assign T_2870_io_ar_bits_id = xbar_io_slaves_2_ar_bits_id;
+ assign T_2870_io_ar_bits_user = xbar_io_slaves_2_ar_bits_user;
+ assign T_2870_io_r_ready = xbar_io_slaves_2_r_ready;
+endmodule
+module LockingRRArbiter_67(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input [25:0] io_in_0_bits_addr_block,
+ input [3:0] io_in_0_bits_client_xact_id,
+ input [1:0] io_in_0_bits_addr_beat,
+ input io_in_0_bits_is_builtin_type,
+ input [2:0] io_in_0_bits_a_type,
+ input [16:0] io_in_0_bits_union,
+ input [127:0] io_in_0_bits_data,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input [25:0] io_in_1_bits_addr_block,
+ input [3:0] io_in_1_bits_client_xact_id,
+ input [1:0] io_in_1_bits_addr_beat,
+ input io_in_1_bits_is_builtin_type,
+ input [2:0] io_in_1_bits_a_type,
+ input [16:0] io_in_1_bits_union,
+ input [127:0] io_in_1_bits_data,
+ input io_out_ready,
+ output io_out_valid,
+ output [25:0] io_out_bits_addr_block,
+ output [3:0] io_out_bits_client_xact_id,
+ output [1:0] io_out_bits_addr_beat,
+ output io_out_bits_is_builtin_type,
+ output [2:0] io_out_bits_a_type,
+ output [16:0] io_out_bits_union,
+ output [127:0] io_out_bits_data,
+ output io_chosen
+);
+ reg T_656;
+ reg T_658;
+ wire T_660;
+ wire GEN_0;
+ wire [25:0] GEN_1;
+ wire [3:0] GEN_2;
+ wire [1:0] GEN_3;
+ wire GEN_4;
+ wire [2:0] GEN_5;
+ wire [16:0] GEN_6;
+ wire [127:0] GEN_7;
+ wire GEN_8;
+ reg last_grant;
+ wire T_842;
+ wire T_843;
+ wire T_845;
+ wire T_846;
+ wire T_849;
+ wire T_851;
+ wire T_853;
+ wire T_854;
+ wire T_856;
+ wire T_858;
+ wire T_859;
+ wire T_860;
+ wire T_862;
+ wire T_864;
+ wire T_865;
+ wire T_866;
+ wire T_868;
+ wire T_869;
+ wire T_870;
+ wire T_872;
+ wire T_873;
+ wire T_874;
+ wire T_876;
+ wire T_877;
+ wire T_878;
+ reg [1:0] T_880;
+ wire [2:0] T_882;
+ wire [1:0] T_883;
+ wire T_884;
+ wire T_886;
+ wire [2:0] T_889_0;
+ wire T_892;
+ wire T_894;
+ wire T_895;
+ wire T_897;
+ wire T_899;
+ wire T_900;
+ wire T_902_0;
+ wire T_902_1;
+ wire T_908;
+ wire T_910;
+ wire T_914;
+ wire T_916;
+ wire T_917;
+ wire choose;
+ wire T_920;
+ wire T_921;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ assign io_in_0_ready = T_874;
+ assign io_in_1_ready = T_878;
+ assign io_out_valid = GEN_0;
+ assign io_out_bits_addr_block = GEN_1;
+ assign io_out_bits_client_xact_id = GEN_2;
+ assign io_out_bits_addr_beat = GEN_3;
+ assign io_out_bits_is_builtin_type = GEN_4;
+ assign io_out_bits_a_type = GEN_5;
+ assign io_out_bits_union = GEN_6;
+ assign io_out_bits_data = GEN_7;
+ assign io_chosen = T_660;
+ assign T_660 = T_920;
+ assign GEN_0 = GEN_9 ? io_in_1_valid : io_in_0_valid;
+ assign GEN_1 = GEN_10 ? io_in_1_bits_addr_block : io_in_0_bits_addr_block;
+ assign GEN_2 = GEN_11 ? io_in_1_bits_client_xact_id : io_in_0_bits_client_xact_id;
+ assign GEN_3 = GEN_12 ? io_in_1_bits_addr_beat : io_in_0_bits_addr_beat;
+ assign GEN_4 = GEN_13 ? io_in_1_bits_is_builtin_type : io_in_0_bits_is_builtin_type;
+ assign GEN_5 = GEN_14 ? io_in_1_bits_a_type : io_in_0_bits_a_type;
+ assign GEN_6 = GEN_15 ? io_in_1_bits_union : io_in_0_bits_union;
+ assign GEN_7 = GEN_16 ? io_in_1_bits_data : io_in_0_bits_data;
+ assign GEN_8 = 1'h0;
+ assign T_842 = 1'h0 > last_grant;
+ assign T_843 = io_in_0_valid & T_842;
+ assign T_845 = 1'h1 > last_grant;
+ assign T_846 = io_in_1_valid & T_845;
+ assign T_849 = 1'h0 | T_843;
+ assign T_851 = T_849 == 1'h0;
+ assign T_853 = 1'h0 | T_843;
+ assign T_854 = T_853 | T_846;
+ assign T_856 = T_854 == 1'h0;
+ assign T_858 = 1'h0 | T_843;
+ assign T_859 = T_858 | T_846;
+ assign T_860 = T_859 | io_in_0_valid;
+ assign T_862 = T_860 == 1'h0;
+ assign T_864 = 1'h0 > last_grant;
+ assign T_865 = 1'h1 & T_864;
+ assign T_866 = T_865 | T_856;
+ assign T_868 = 1'h1 > last_grant;
+ assign T_869 = T_851 & T_868;
+ assign T_870 = T_869 | T_862;
+ assign T_872 = T_658 == 1'h0;
+ assign T_873 = T_656 ? T_872 : T_866;
+ assign T_874 = T_873 & io_out_ready;
+ assign T_876 = T_658 == 1'h1;
+ assign T_877 = T_656 ? T_876 : T_870;
+ assign T_878 = T_877 & io_out_ready;
+ assign T_882 = T_880 + 1'h1;
+ assign T_883 = T_882[1:0];
+ assign T_884 = io_out_ready & io_out_valid;
+ assign T_886 = 1'h1 & io_out_bits_is_builtin_type;
+ assign T_889_0 = 3'h3;
+ assign T_892 = T_889_0 == io_out_bits_a_type;
+ assign T_894 = 1'h0 | T_892;
+ assign T_895 = T_886 & T_894;
+ assign T_897 = T_656 == 1'h0;
+ assign T_899 = io_in_0_ready & io_in_0_valid;
+ assign T_900 = io_in_1_ready & io_in_1_valid;
+ assign T_902_0 = T_899;
+ assign T_902_1 = T_900;
+ assign T_908 = T_902_0 ? 1'h0 : 1'h1;
+ assign T_910 = T_883 == 1'h0;
+ assign T_914 = io_in_0_valid ? 1'h0 : 1'h1;
+ assign T_916 = 1'h1 > last_grant;
+ assign T_917 = io_in_1_valid & T_916;
+ assign choose = T_917 ? 1'h1 : T_914;
+ assign T_920 = T_656 ? T_658 : choose;
+ assign T_921 = io_out_ready & io_out_valid;
+ assign GEN_9 = 1'h1 == T_660;
+ assign GEN_10 = 1'h1 == T_660;
+ assign GEN_11 = 1'h1 == T_660;
+ assign GEN_12 = 1'h1 == T_660;
+ assign GEN_13 = 1'h1 == T_660;
+ assign GEN_14 = 1'h1 == T_660;
+ assign GEN_15 = 1'h1 == T_660;
+ assign GEN_16 = 1'h1 == T_660;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_656 = {1{$random}};
+ T_658 = {1{$random}};
+ last_grant = {1{$random}};
+ T_880 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ T_656 <= 1'h0;
+ end else begin
+ if(T_884) begin
+ if(T_910) begin
+ T_656 <= 1'h0;
+ end else begin
+ if(T_895) begin
+ if(T_897) begin
+ T_656 <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_658 <= 1'h1;
+ end else begin
+ if(T_884) begin
+ if(T_895) begin
+ if(T_897) begin
+ T_658 <= T_908;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ last_grant <= 1'h0;
+ end else begin
+ if(T_921) begin
+ last_grant <= T_660;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_880 <= 2'h0;
+ end else begin
+ if(T_884) begin
+ if(T_895) begin
+ T_880 <= T_883;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module ReorderQueue(
+ input clk,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input io_enq_bits_data,
+ input [3:0] io_enq_bits_tag,
+ input io_deq_valid,
+ input [3:0] io_deq_tag,
+ output io_deq_data,
+ output io_deq_matches
+);
+ reg roq_data_0;
+ reg roq_data_1;
+ reg roq_data_2;
+ reg roq_data_3;
+ reg roq_data_4;
+ reg roq_data_5;
+ reg roq_data_6;
+ reg roq_data_7;
+ reg roq_data_8;
+ reg [3:0] roq_tags_0;
+ reg [3:0] roq_tags_1;
+ reg [3:0] roq_tags_2;
+ reg [3:0] roq_tags_3;
+ reg [3:0] roq_tags_4;
+ reg [3:0] roq_tags_5;
+ reg [3:0] roq_tags_6;
+ reg [3:0] roq_tags_7;
+ reg [3:0] roq_tags_8;
+ wire T_96_0;
+ wire T_96_1;
+ wire T_96_2;
+ wire T_96_3;
+ wire T_96_4;
+ wire T_96_5;
+ wire T_96_6;
+ wire T_96_7;
+ wire T_96_8;
+ reg roq_free_0;
+ reg roq_free_1;
+ reg roq_free_2;
+ reg roq_free_3;
+ reg roq_free_4;
+ reg roq_free_5;
+ reg roq_free_6;
+ reg roq_free_7;
+ reg roq_free_8;
+ wire [3:0] T_129;
+ wire [3:0] T_130;
+ wire [3:0] T_131;
+ wire [3:0] T_132;
+ wire [3:0] T_133;
+ wire [3:0] T_134;
+ wire [3:0] T_135;
+ wire [3:0] roq_enq_addr;
+ wire T_137;
+ wire T_139;
+ wire T_140;
+ wire T_141;
+ wire T_143;
+ wire T_144;
+ wire T_145;
+ wire T_147;
+ wire T_148;
+ wire T_149;
+ wire T_151;
+ wire T_152;
+ wire T_153;
+ wire T_155;
+ wire T_156;
+ wire T_157;
+ wire T_159;
+ wire T_160;
+ wire T_161;
+ wire T_163;
+ wire T_164;
+ wire T_165;
+ wire T_167;
+ wire T_168;
+ wire T_169;
+ wire T_171;
+ wire T_172;
+ wire [3:0] T_182;
+ wire [3:0] T_183;
+ wire [3:0] T_184;
+ wire [3:0] T_185;
+ wire [3:0] T_186;
+ wire [3:0] T_187;
+ wire [3:0] T_188;
+ wire [3:0] roq_deq_addr;
+ wire T_190;
+ wire T_191;
+ wire T_192;
+ wire T_193;
+ wire T_194;
+ wire T_195;
+ wire T_196;
+ wire T_197;
+ wire GEN_0;
+ wire T_199;
+ wire T_200;
+ wire T_201;
+ wire T_202;
+ wire T_203;
+ wire T_204;
+ wire T_205;
+ wire T_206;
+ wire T_207;
+ wire GEN_1;
+ wire [3:0] GEN_2;
+ wire GEN_3;
+ wire GEN_4;
+ wire GEN_5;
+ wire GEN_6;
+ wire GEN_7;
+ wire GEN_8;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ wire GEN_17;
+ wire GEN_18;
+ wire GEN_19;
+ wire GEN_20;
+ wire GEN_21;
+ wire GEN_22;
+ wire GEN_23;
+ wire GEN_24;
+ wire GEN_25;
+ wire GEN_26;
+ wire GEN_27;
+ wire GEN_28;
+ wire GEN_29;
+ wire GEN_30;
+ wire GEN_31;
+ wire GEN_32;
+ wire GEN_33;
+ wire GEN_34;
+ wire GEN_35;
+ wire GEN_36;
+ wire GEN_37;
+ wire GEN_38;
+ wire GEN_39;
+ wire GEN_40;
+ wire GEN_41;
+ wire GEN_42;
+ wire GEN_43;
+ wire GEN_44;
+ wire GEN_45;
+ wire GEN_46;
+ wire GEN_47;
+ wire GEN_48;
+ wire GEN_49;
+ wire GEN_50;
+ wire GEN_51;
+ wire GEN_52;
+ wire GEN_53;
+ wire GEN_54;
+ wire GEN_55;
+ wire GEN_56;
+ wire GEN_57;
+ assign io_enq_ready = T_197;
+ assign io_deq_data = GEN_0;
+ assign io_deq_matches = T_206;
+ assign T_96_0 = 1'h1;
+ assign T_96_1 = 1'h1;
+ assign T_96_2 = 1'h1;
+ assign T_96_3 = 1'h1;
+ assign T_96_4 = 1'h1;
+ assign T_96_5 = 1'h1;
+ assign T_96_6 = 1'h1;
+ assign T_96_7 = 1'h1;
+ assign T_96_8 = 1'h1;
+ assign T_129 = roq_free_7 ? 3'h7 : 4'h8;
+ assign T_130 = roq_free_6 ? 3'h6 : T_129;
+ assign T_131 = roq_free_5 ? 3'h5 : T_130;
+ assign T_132 = roq_free_4 ? 3'h4 : T_131;
+ assign T_133 = roq_free_3 ? 2'h3 : T_132;
+ assign T_134 = roq_free_2 ? 2'h2 : T_133;
+ assign T_135 = roq_free_1 ? 1'h1 : T_134;
+ assign roq_enq_addr = roq_free_0 ? 1'h0 : T_135;
+ assign T_137 = roq_tags_0 == io_deq_tag;
+ assign T_139 = roq_free_0 == 1'h0;
+ assign T_140 = T_137 & T_139;
+ assign T_141 = roq_tags_1 == io_deq_tag;
+ assign T_143 = roq_free_1 == 1'h0;
+ assign T_144 = T_141 & T_143;
+ assign T_145 = roq_tags_2 == io_deq_tag;
+ assign T_147 = roq_free_2 == 1'h0;
+ assign T_148 = T_145 & T_147;
+ assign T_149 = roq_tags_3 == io_deq_tag;
+ assign T_151 = roq_free_3 == 1'h0;
+ assign T_152 = T_149 & T_151;
+ assign T_153 = roq_tags_4 == io_deq_tag;
+ assign T_155 = roq_free_4 == 1'h0;
+ assign T_156 = T_153 & T_155;
+ assign T_157 = roq_tags_5 == io_deq_tag;
+ assign T_159 = roq_free_5 == 1'h0;
+ assign T_160 = T_157 & T_159;
+ assign T_161 = roq_tags_6 == io_deq_tag;
+ assign T_163 = roq_free_6 == 1'h0;
+ assign T_164 = T_161 & T_163;
+ assign T_165 = roq_tags_7 == io_deq_tag;
+ assign T_167 = roq_free_7 == 1'h0;
+ assign T_168 = T_165 & T_167;
+ assign T_169 = roq_tags_8 == io_deq_tag;
+ assign T_171 = roq_free_8 == 1'h0;
+ assign T_172 = T_169 & T_171;
+ assign T_182 = T_168 ? 3'h7 : 4'h8;
+ assign T_183 = T_164 ? 3'h6 : T_182;
+ assign T_184 = T_160 ? 3'h5 : T_183;
+ assign T_185 = T_156 ? 3'h4 : T_184;
+ assign T_186 = T_152 ? 2'h3 : T_185;
+ assign T_187 = T_148 ? 2'h2 : T_186;
+ assign T_188 = T_144 ? 1'h1 : T_187;
+ assign roq_deq_addr = T_140 ? 1'h0 : T_188;
+ assign T_190 = roq_free_0 | roq_free_1;
+ assign T_191 = T_190 | roq_free_2;
+ assign T_192 = T_191 | roq_free_3;
+ assign T_193 = T_192 | roq_free_4;
+ assign T_194 = T_193 | roq_free_5;
+ assign T_195 = T_194 | roq_free_6;
+ assign T_196 = T_195 | roq_free_7;
+ assign T_197 = T_196 | roq_free_8;
+ assign GEN_0 = GEN_50 ? roq_data_8 : GEN_51 ? roq_data_7 : GEN_52 ? roq_data_6 : GEN_53 ? roq_data_5 : GEN_54 ? roq_data_4 : GEN_55 ? roq_data_3 : GEN_56 ? roq_data_2 : GEN_57 ? roq_data_1 : roq_data_0;
+ assign T_199 = T_140 | T_144;
+ assign T_200 = T_199 | T_148;
+ assign T_201 = T_200 | T_152;
+ assign T_202 = T_201 | T_156;
+ assign T_203 = T_202 | T_160;
+ assign T_204 = T_203 | T_164;
+ assign T_205 = T_204 | T_168;
+ assign T_206 = T_205 | T_172;
+ assign T_207 = io_enq_valid & io_enq_ready;
+ assign GEN_1 = io_enq_bits_data;
+ assign GEN_2 = io_enq_bits_tag;
+ assign GEN_3 = 1'h0;
+ assign GEN_4 = 1'h1;
+ assign GEN_5 = 1'h0 == roq_enq_addr;
+ assign GEN_6 = 1'h1 == roq_enq_addr;
+ assign GEN_7 = 2'h2 == roq_enq_addr;
+ assign GEN_8 = 2'h3 == roq_enq_addr;
+ assign GEN_9 = 3'h4 == roq_enq_addr;
+ assign GEN_10 = 3'h5 == roq_enq_addr;
+ assign GEN_11 = 3'h6 == roq_enq_addr;
+ assign GEN_12 = 3'h7 == roq_enq_addr;
+ assign GEN_13 = 4'h8 == roq_enq_addr;
+ assign GEN_14 = 1'h0 == roq_enq_addr;
+ assign GEN_15 = 1'h1 == roq_enq_addr;
+ assign GEN_16 = 2'h2 == roq_enq_addr;
+ assign GEN_17 = 2'h3 == roq_enq_addr;
+ assign GEN_18 = 3'h4 == roq_enq_addr;
+ assign GEN_19 = 3'h5 == roq_enq_addr;
+ assign GEN_20 = 3'h6 == roq_enq_addr;
+ assign GEN_21 = 3'h7 == roq_enq_addr;
+ assign GEN_22 = 4'h8 == roq_enq_addr;
+ assign GEN_23 = 1'h0 == roq_deq_addr;
+ assign GEN_24 = 1'h0 == roq_enq_addr;
+ assign GEN_25 = 1'h0 == roq_enq_addr;
+ assign GEN_26 = 1'h1 == roq_deq_addr;
+ assign GEN_27 = 1'h1 == roq_enq_addr;
+ assign GEN_28 = 1'h1 == roq_enq_addr;
+ assign GEN_29 = 2'h2 == roq_deq_addr;
+ assign GEN_30 = 2'h2 == roq_enq_addr;
+ assign GEN_31 = 2'h2 == roq_enq_addr;
+ assign GEN_32 = 2'h3 == roq_deq_addr;
+ assign GEN_33 = 2'h3 == roq_enq_addr;
+ assign GEN_34 = 2'h3 == roq_enq_addr;
+ assign GEN_35 = 3'h4 == roq_deq_addr;
+ assign GEN_36 = 3'h4 == roq_enq_addr;
+ assign GEN_37 = 3'h4 == roq_enq_addr;
+ assign GEN_38 = 3'h5 == roq_deq_addr;
+ assign GEN_39 = 3'h5 == roq_enq_addr;
+ assign GEN_40 = 3'h5 == roq_enq_addr;
+ assign GEN_41 = 3'h6 == roq_deq_addr;
+ assign GEN_42 = 3'h6 == roq_enq_addr;
+ assign GEN_43 = 3'h6 == roq_enq_addr;
+ assign GEN_44 = 3'h7 == roq_deq_addr;
+ assign GEN_45 = 3'h7 == roq_enq_addr;
+ assign GEN_46 = 3'h7 == roq_enq_addr;
+ assign GEN_47 = 4'h8 == roq_deq_addr;
+ assign GEN_48 = 4'h8 == roq_enq_addr;
+ assign GEN_49 = 4'h8 == roq_enq_addr;
+ assign GEN_50 = 4'h8 == roq_deq_addr;
+ assign GEN_51 = 3'h7 == roq_deq_addr;
+ assign GEN_52 = 3'h6 == roq_deq_addr;
+ assign GEN_53 = 3'h5 == roq_deq_addr;
+ assign GEN_54 = 3'h4 == roq_deq_addr;
+ assign GEN_55 = 2'h3 == roq_deq_addr;
+ assign GEN_56 = 2'h2 == roq_deq_addr;
+ assign GEN_57 = 1'h1 == roq_deq_addr;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ roq_data_0 = {1{$random}};
+ roq_data_1 = {1{$random}};
+ roq_data_2 = {1{$random}};
+ roq_data_3 = {1{$random}};
+ roq_data_4 = {1{$random}};
+ roq_data_5 = {1{$random}};
+ roq_data_6 = {1{$random}};
+ roq_data_7 = {1{$random}};
+ roq_data_8 = {1{$random}};
+ roq_tags_0 = {1{$random}};
+ roq_tags_1 = {1{$random}};
+ roq_tags_2 = {1{$random}};
+ roq_tags_3 = {1{$random}};
+ roq_tags_4 = {1{$random}};
+ roq_tags_5 = {1{$random}};
+ roq_tags_6 = {1{$random}};
+ roq_tags_7 = {1{$random}};
+ roq_tags_8 = {1{$random}};
+ roq_free_0 = {1{$random}};
+ roq_free_1 = {1{$random}};
+ roq_free_2 = {1{$random}};
+ roq_free_3 = {1{$random}};
+ roq_free_4 = {1{$random}};
+ roq_free_5 = {1{$random}};
+ roq_free_6 = {1{$random}};
+ roq_free_7 = {1{$random}};
+ roq_free_8 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_207) begin
+ if(GEN_5) begin
+ roq_data_0 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_207) begin
+ if(GEN_6) begin
+ roq_data_1 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_207) begin
+ if(GEN_7) begin
+ roq_data_2 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_207) begin
+ if(GEN_8) begin
+ roq_data_3 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_207) begin
+ if(GEN_9) begin
+ roq_data_4 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_207) begin
+ if(GEN_10) begin
+ roq_data_5 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_207) begin
+ if(GEN_11) begin
+ roq_data_6 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_207) begin
+ if(GEN_12) begin
+ roq_data_7 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_207) begin
+ if(GEN_13) begin
+ roq_data_8 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_207) begin
+ if(GEN_14) begin
+ roq_tags_0 <= GEN_2;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_207) begin
+ if(GEN_15) begin
+ roq_tags_1 <= GEN_2;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_207) begin
+ if(GEN_16) begin
+ roq_tags_2 <= GEN_2;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_207) begin
+ if(GEN_17) begin
+ roq_tags_3 <= GEN_2;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_207) begin
+ if(GEN_18) begin
+ roq_tags_4 <= GEN_2;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_207) begin
+ if(GEN_19) begin
+ roq_tags_5 <= GEN_2;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_207) begin
+ if(GEN_20) begin
+ roq_tags_6 <= GEN_2;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_207) begin
+ if(GEN_21) begin
+ roq_tags_7 <= GEN_2;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_207) begin
+ if(GEN_22) begin
+ roq_tags_8 <= GEN_2;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ roq_free_0 <= T_96_0;
+ end else begin
+ if(io_deq_valid) begin
+ if(GEN_23) begin
+ roq_free_0 <= GEN_4;
+ end else begin
+ if(T_207) begin
+ if(GEN_24) begin
+ roq_free_0 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_207) begin
+ if(GEN_25) begin
+ roq_free_0 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ roq_free_1 <= T_96_1;
+ end else begin
+ if(io_deq_valid) begin
+ if(GEN_26) begin
+ roq_free_1 <= GEN_4;
+ end else begin
+ if(T_207) begin
+ if(GEN_27) begin
+ roq_free_1 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_207) begin
+ if(GEN_28) begin
+ roq_free_1 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ roq_free_2 <= T_96_2;
+ end else begin
+ if(io_deq_valid) begin
+ if(GEN_29) begin
+ roq_free_2 <= GEN_4;
+ end else begin
+ if(T_207) begin
+ if(GEN_30) begin
+ roq_free_2 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_207) begin
+ if(GEN_31) begin
+ roq_free_2 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ roq_free_3 <= T_96_3;
+ end else begin
+ if(io_deq_valid) begin
+ if(GEN_32) begin
+ roq_free_3 <= GEN_4;
+ end else begin
+ if(T_207) begin
+ if(GEN_33) begin
+ roq_free_3 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_207) begin
+ if(GEN_34) begin
+ roq_free_3 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ roq_free_4 <= T_96_4;
+ end else begin
+ if(io_deq_valid) begin
+ if(GEN_35) begin
+ roq_free_4 <= GEN_4;
+ end else begin
+ if(T_207) begin
+ if(GEN_36) begin
+ roq_free_4 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_207) begin
+ if(GEN_37) begin
+ roq_free_4 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ roq_free_5 <= T_96_5;
+ end else begin
+ if(io_deq_valid) begin
+ if(GEN_38) begin
+ roq_free_5 <= GEN_4;
+ end else begin
+ if(T_207) begin
+ if(GEN_39) begin
+ roq_free_5 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_207) begin
+ if(GEN_40) begin
+ roq_free_5 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ roq_free_6 <= T_96_6;
+ end else begin
+ if(io_deq_valid) begin
+ if(GEN_41) begin
+ roq_free_6 <= GEN_4;
+ end else begin
+ if(T_207) begin
+ if(GEN_42) begin
+ roq_free_6 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_207) begin
+ if(GEN_43) begin
+ roq_free_6 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ roq_free_7 <= T_96_7;
+ end else begin
+ if(io_deq_valid) begin
+ if(GEN_44) begin
+ roq_free_7 <= GEN_4;
+ end else begin
+ if(T_207) begin
+ if(GEN_45) begin
+ roq_free_7 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_207) begin
+ if(GEN_46) begin
+ roq_free_7 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ roq_free_8 <= T_96_8;
+ end else begin
+ if(io_deq_valid) begin
+ if(GEN_47) begin
+ roq_free_8 <= GEN_4;
+ end else begin
+ if(T_207) begin
+ if(GEN_48) begin
+ roq_free_8 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_207) begin
+ if(GEN_49) begin
+ roq_free_8 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+endmodule
+module ClientTileLinkIOUnwrapper(
+ input clk,
+ input reset,
+ output io_in_acquire_ready,
+ input io_in_acquire_valid,
+ input [25:0] io_in_acquire_bits_addr_block,
+ input [3:0] io_in_acquire_bits_client_xact_id,
+ input [1:0] io_in_acquire_bits_addr_beat,
+ input io_in_acquire_bits_is_builtin_type,
+ input [2:0] io_in_acquire_bits_a_type,
+ input [16:0] io_in_acquire_bits_union,
+ input [127:0] io_in_acquire_bits_data,
+ input io_in_grant_ready,
+ output io_in_grant_valid,
+ output [1:0] io_in_grant_bits_addr_beat,
+ output [3:0] io_in_grant_bits_client_xact_id,
+ output io_in_grant_bits_manager_xact_id,
+ output io_in_grant_bits_is_builtin_type,
+ output [3:0] io_in_grant_bits_g_type,
+ output [127:0] io_in_grant_bits_data,
+ input io_in_probe_ready,
+ output io_in_probe_valid,
+ output [25:0] io_in_probe_bits_addr_block,
+ output [1:0] io_in_probe_bits_p_type,
+ output io_in_release_ready,
+ input io_in_release_valid,
+ input [1:0] io_in_release_bits_addr_beat,
+ input [25:0] io_in_release_bits_addr_block,
+ input [3:0] io_in_release_bits_client_xact_id,
+ input io_in_release_bits_voluntary,
+ input [2:0] io_in_release_bits_r_type,
+ input [127:0] io_in_release_bits_data,
+ input io_out_acquire_ready,
+ output io_out_acquire_valid,
+ output [25:0] io_out_acquire_bits_addr_block,
+ output [3:0] io_out_acquire_bits_client_xact_id,
+ output [1:0] io_out_acquire_bits_addr_beat,
+ output io_out_acquire_bits_is_builtin_type,
+ output [2:0] io_out_acquire_bits_a_type,
+ output [16:0] io_out_acquire_bits_union,
+ output [127:0] io_out_acquire_bits_data,
+ output io_out_grant_ready,
+ input io_out_grant_valid,
+ input [1:0] io_out_grant_bits_addr_beat,
+ input [3:0] io_out_grant_bits_client_xact_id,
+ input io_out_grant_bits_manager_xact_id,
+ input io_out_grant_bits_is_builtin_type,
+ input [3:0] io_out_grant_bits_g_type,
+ input [127:0] io_out_grant_bits_data
+);
+ wire acqArb_clk;
+ wire acqArb_reset;
+ wire acqArb_io_in_0_ready;
+ wire acqArb_io_in_0_valid;
+ wire [25:0] acqArb_io_in_0_bits_addr_block;
+ wire [3:0] acqArb_io_in_0_bits_client_xact_id;
+ wire [1:0] acqArb_io_in_0_bits_addr_beat;
+ wire acqArb_io_in_0_bits_is_builtin_type;
+ wire [2:0] acqArb_io_in_0_bits_a_type;
+ wire [16:0] acqArb_io_in_0_bits_union;
+ wire [127:0] acqArb_io_in_0_bits_data;
+ wire acqArb_io_in_1_ready;
+ wire acqArb_io_in_1_valid;
+ wire [25:0] acqArb_io_in_1_bits_addr_block;
+ wire [3:0] acqArb_io_in_1_bits_client_xact_id;
+ wire [1:0] acqArb_io_in_1_bits_addr_beat;
+ wire acqArb_io_in_1_bits_is_builtin_type;
+ wire [2:0] acqArb_io_in_1_bits_a_type;
+ wire [16:0] acqArb_io_in_1_bits_union;
+ wire [127:0] acqArb_io_in_1_bits_data;
+ wire acqArb_io_out_ready;
+ wire acqArb_io_out_valid;
+ wire [25:0] acqArb_io_out_bits_addr_block;
+ wire [3:0] acqArb_io_out_bits_client_xact_id;
+ wire [1:0] acqArb_io_out_bits_addr_beat;
+ wire acqArb_io_out_bits_is_builtin_type;
+ wire [2:0] acqArb_io_out_bits_a_type;
+ wire [16:0] acqArb_io_out_bits_union;
+ wire [127:0] acqArb_io_out_bits_data;
+ wire acqArb_io_chosen;
+ wire acqRoq_clk;
+ wire acqRoq_reset;
+ wire acqRoq_io_enq_ready;
+ wire acqRoq_io_enq_valid;
+ wire acqRoq_io_enq_bits_data;
+ wire [3:0] acqRoq_io_enq_bits_tag;
+ wire acqRoq_io_deq_valid;
+ wire [3:0] acqRoq_io_deq_tag;
+ wire acqRoq_io_deq_data;
+ wire acqRoq_io_deq_matches;
+ wire relRoq_clk;
+ wire relRoq_reset;
+ wire relRoq_io_enq_ready;
+ wire relRoq_io_enq_valid;
+ wire relRoq_io_enq_bits_data;
+ wire [3:0] relRoq_io_enq_bits_tag;
+ wire relRoq_io_deq_valid;
+ wire [3:0] relRoq_io_deq_tag;
+ wire relRoq_io_deq_data;
+ wire relRoq_io_deq_matches;
+ wire T_1215;
+ wire [2:0] T_1218_0;
+ wire T_1221;
+ wire T_1223;
+ wire T_1224;
+ wire T_1226;
+ wire T_1228;
+ wire acq_roq_enq;
+ wire [1:0] T_1232_0;
+ wire [1:0] T_1232_1;
+ wire [1:0] T_1232_2;
+ wire T_1237;
+ wire T_1238;
+ wire T_1239;
+ wire T_1241;
+ wire T_1242;
+ wire T_1243;
+ wire T_1244;
+ wire T_1246;
+ wire T_1248;
+ wire rel_roq_enq;
+ wire T_1251;
+ wire acq_roq_ready;
+ wire T_1254;
+ wire rel_roq_ready;
+ wire T_1256;
+ wire T_1257;
+ wire T_1258;
+ wire [2:0] T_1261;
+ wire [5:0] T_1263;
+ wire [8:0] T_1264;
+ wire [16:0] T_1265;
+ wire [25:0] T_1294_addr_block;
+ wire [3:0] T_1294_client_xact_id;
+ wire [1:0] T_1294_addr_beat;
+ wire T_1294_is_builtin_type;
+ wire [2:0] T_1294_a_type;
+ wire [16:0] T_1294_union;
+ wire [127:0] T_1294_data;
+ wire T_1322;
+ wire T_1323;
+ wire T_1324;
+ wire T_1325;
+ wire [15:0] GEN_0;
+ wire [15:0] T_1347;
+ wire [3:0] T_1355;
+ wire [1:0] T_1356;
+ wire [5:0] T_1357;
+ wire [1:0] T_1359;
+ wire [4:0] T_1360;
+ wire [16:0] T_1362;
+ wire [16:0] T_1364;
+ wire [3:0] T_1366;
+ wire [1:0] T_1367;
+ wire [5:0] T_1368;
+ wire [5:0] T_1370;
+ wire [5:0] T_1372;
+ wire T_1373;
+ wire [5:0] T_1374;
+ wire T_1375;
+ wire [5:0] T_1376;
+ wire T_1377;
+ wire [5:0] T_1378;
+ wire T_1379;
+ wire [16:0] T_1380;
+ wire T_1381;
+ wire [16:0] T_1382;
+ wire T_1383;
+ wire [16:0] T_1384;
+ wire T_1385;
+ wire [16:0] T_1386;
+ wire [25:0] T_1415_addr_block;
+ wire [3:0] T_1415_client_xact_id;
+ wire [1:0] T_1415_addr_beat;
+ wire T_1415_is_builtin_type;
+ wire [2:0] T_1415_a_type;
+ wire [16:0] T_1415_union;
+ wire [127:0] T_1415_data;
+ wire T_1443;
+ wire T_1444;
+ wire [2:0] T_1448_0;
+ wire T_1451;
+ wire T_1453;
+ wire T_1455_0;
+ wire T_1458;
+ wire T_1460;
+ wire T_1461;
+ wire T_1462;
+ wire T_1464;
+ wire T_1466;
+ wire T_1467;
+ wire T_1468;
+ wire T_1469;
+ wire [2:0] T_1473_0;
+ wire T_1476;
+ wire T_1478;
+ wire T_1480_0;
+ wire T_1483;
+ wire T_1485;
+ wire T_1486;
+ wire T_1487;
+ wire T_1489;
+ wire T_1491;
+ wire T_1492;
+ wire T_1493;
+ wire [3:0] T_1494;
+ wire [1:0] acq_grant_addr_beat;
+ wire [3:0] acq_grant_client_xact_id;
+ wire acq_grant_manager_xact_id;
+ wire acq_grant_is_builtin_type;
+ wire [3:0] acq_grant_g_type;
+ wire [127:0] acq_grant_data;
+ wire [3:0] T_1551;
+ wire [1:0] rel_grant_addr_beat;
+ wire [3:0] rel_grant_client_xact_id;
+ wire rel_grant_manager_xact_id;
+ wire rel_grant_is_builtin_type;
+ wire [3:0] rel_grant_g_type;
+ wire [127:0] rel_grant_data;
+ wire [1:0] T_1606_addr_beat;
+ wire [3:0] T_1606_client_xact_id;
+ wire T_1606_manager_xact_id;
+ wire T_1606_is_builtin_type;
+ wire [3:0] T_1606_g_type;
+ wire [127:0] T_1606_data;
+ reg [25:0] GEN_1;
+ reg [1:0] GEN_2;
+ LockingRRArbiter_67 acqArb (
+ .clk(acqArb_clk),
+ .reset(acqArb_reset),
+ .io_in_0_ready(acqArb_io_in_0_ready),
+ .io_in_0_valid(acqArb_io_in_0_valid),
+ .io_in_0_bits_addr_block(acqArb_io_in_0_bits_addr_block),
+ .io_in_0_bits_client_xact_id(acqArb_io_in_0_bits_client_xact_id),
+ .io_in_0_bits_addr_beat(acqArb_io_in_0_bits_addr_beat),
+ .io_in_0_bits_is_builtin_type(acqArb_io_in_0_bits_is_builtin_type),
+ .io_in_0_bits_a_type(acqArb_io_in_0_bits_a_type),
+ .io_in_0_bits_union(acqArb_io_in_0_bits_union),
+ .io_in_0_bits_data(acqArb_io_in_0_bits_data),
+ .io_in_1_ready(acqArb_io_in_1_ready),
+ .io_in_1_valid(acqArb_io_in_1_valid),
+ .io_in_1_bits_addr_block(acqArb_io_in_1_bits_addr_block),
+ .io_in_1_bits_client_xact_id(acqArb_io_in_1_bits_client_xact_id),
+ .io_in_1_bits_addr_beat(acqArb_io_in_1_bits_addr_beat),
+ .io_in_1_bits_is_builtin_type(acqArb_io_in_1_bits_is_builtin_type),
+ .io_in_1_bits_a_type(acqArb_io_in_1_bits_a_type),
+ .io_in_1_bits_union(acqArb_io_in_1_bits_union),
+ .io_in_1_bits_data(acqArb_io_in_1_bits_data),
+ .io_out_ready(acqArb_io_out_ready),
+ .io_out_valid(acqArb_io_out_valid),
+ .io_out_bits_addr_block(acqArb_io_out_bits_addr_block),
+ .io_out_bits_client_xact_id(acqArb_io_out_bits_client_xact_id),
+ .io_out_bits_addr_beat(acqArb_io_out_bits_addr_beat),
+ .io_out_bits_is_builtin_type(acqArb_io_out_bits_is_builtin_type),
+ .io_out_bits_a_type(acqArb_io_out_bits_a_type),
+ .io_out_bits_union(acqArb_io_out_bits_union),
+ .io_out_bits_data(acqArb_io_out_bits_data),
+ .io_chosen(acqArb_io_chosen)
+ );
+ ReorderQueue acqRoq (
+ .clk(acqRoq_clk),
+ .reset(acqRoq_reset),
+ .io_enq_ready(acqRoq_io_enq_ready),
+ .io_enq_valid(acqRoq_io_enq_valid),
+ .io_enq_bits_data(acqRoq_io_enq_bits_data),
+ .io_enq_bits_tag(acqRoq_io_enq_bits_tag),
+ .io_deq_valid(acqRoq_io_deq_valid),
+ .io_deq_tag(acqRoq_io_deq_tag),
+ .io_deq_data(acqRoq_io_deq_data),
+ .io_deq_matches(acqRoq_io_deq_matches)
+ );
+ ReorderQueue relRoq (
+ .clk(relRoq_clk),
+ .reset(relRoq_reset),
+ .io_enq_ready(relRoq_io_enq_ready),
+ .io_enq_valid(relRoq_io_enq_valid),
+ .io_enq_bits_data(relRoq_io_enq_bits_data),
+ .io_enq_bits_tag(relRoq_io_enq_bits_tag),
+ .io_deq_valid(relRoq_io_deq_valid),
+ .io_deq_tag(relRoq_io_deq_tag),
+ .io_deq_data(relRoq_io_deq_data),
+ .io_deq_matches(relRoq_io_deq_matches)
+ );
+ assign io_in_acquire_ready = T_1322;
+ assign io_in_grant_valid = io_out_grant_valid;
+ assign io_in_grant_bits_addr_beat = T_1606_addr_beat;
+ assign io_in_grant_bits_client_xact_id = T_1606_client_xact_id;
+ assign io_in_grant_bits_manager_xact_id = T_1606_manager_xact_id;
+ assign io_in_grant_bits_is_builtin_type = T_1606_is_builtin_type;
+ assign io_in_grant_bits_g_type = T_1606_g_type;
+ assign io_in_grant_bits_data = T_1606_data;
+ assign io_in_probe_valid = 1'h0;
+ assign io_in_probe_bits_addr_block = GEN_1;
+ assign io_in_probe_bits_p_type = GEN_2;
+ assign io_in_release_ready = T_1443;
+ assign io_out_acquire_valid = acqArb_io_out_valid;
+ assign io_out_acquire_bits_addr_block = acqArb_io_out_bits_addr_block;
+ assign io_out_acquire_bits_client_xact_id = acqArb_io_out_bits_client_xact_id;
+ assign io_out_acquire_bits_addr_beat = acqArb_io_out_bits_addr_beat;
+ assign io_out_acquire_bits_is_builtin_type = acqArb_io_out_bits_is_builtin_type;
+ assign io_out_acquire_bits_a_type = acqArb_io_out_bits_a_type;
+ assign io_out_acquire_bits_union = acqArb_io_out_bits_union;
+ assign io_out_acquire_bits_data = acqArb_io_out_bits_data;
+ assign io_out_grant_ready = io_in_grant_ready;
+ assign acqArb_clk = clk;
+ assign acqArb_reset = reset;
+ assign acqArb_io_in_0_valid = T_1258;
+ assign acqArb_io_in_0_bits_addr_block = T_1294_addr_block;
+ assign acqArb_io_in_0_bits_client_xact_id = T_1294_client_xact_id;
+ assign acqArb_io_in_0_bits_addr_beat = T_1294_addr_beat;
+ assign acqArb_io_in_0_bits_is_builtin_type = T_1294_is_builtin_type;
+ assign acqArb_io_in_0_bits_a_type = T_1294_a_type;
+ assign acqArb_io_in_0_bits_union = T_1294_union;
+ assign acqArb_io_in_0_bits_data = T_1294_data;
+ assign acqArb_io_in_1_valid = T_1325;
+ assign acqArb_io_in_1_bits_addr_block = T_1415_addr_block;
+ assign acqArb_io_in_1_bits_client_xact_id = T_1415_client_xact_id;
+ assign acqArb_io_in_1_bits_addr_beat = T_1415_addr_beat;
+ assign acqArb_io_in_1_bits_is_builtin_type = T_1415_is_builtin_type;
+ assign acqArb_io_in_1_bits_a_type = T_1415_a_type;
+ assign acqArb_io_in_1_bits_union = T_1415_union;
+ assign acqArb_io_in_1_bits_data = T_1415_data;
+ assign acqArb_io_out_ready = io_out_acquire_ready;
+ assign acqRoq_clk = clk;
+ assign acqRoq_reset = reset;
+ assign acqRoq_io_enq_valid = T_1257;
+ assign acqRoq_io_enq_bits_data = io_in_acquire_bits_is_builtin_type;
+ assign acqRoq_io_enq_bits_tag = io_in_acquire_bits_client_xact_id;
+ assign acqRoq_io_deq_valid = T_1468;
+ assign acqRoq_io_deq_tag = io_out_grant_bits_client_xact_id;
+ assign relRoq_clk = clk;
+ assign relRoq_reset = reset;
+ assign relRoq_io_enq_valid = T_1324;
+ assign relRoq_io_enq_bits_data = io_in_release_bits_voluntary;
+ assign relRoq_io_enq_bits_tag = io_in_release_bits_client_xact_id;
+ assign relRoq_io_deq_valid = T_1493;
+ assign relRoq_io_deq_tag = io_out_grant_bits_client_xact_id;
+ assign T_1215 = 1'h1 & io_in_acquire_bits_is_builtin_type;
+ assign T_1218_0 = 3'h3;
+ assign T_1221 = T_1218_0 == io_in_acquire_bits_a_type;
+ assign T_1223 = 1'h0 | T_1221;
+ assign T_1224 = T_1215 & T_1223;
+ assign T_1226 = T_1224 == 1'h0;
+ assign T_1228 = io_in_acquire_bits_addr_beat == 1'h0;
+ assign acq_roq_enq = T_1226 | T_1228;
+ assign T_1232_0 = 1'h0;
+ assign T_1232_1 = 1'h1;
+ assign T_1232_2 = 2'h2;
+ assign T_1237 = T_1232_0 == io_in_release_bits_r_type;
+ assign T_1238 = T_1232_1 == io_in_release_bits_r_type;
+ assign T_1239 = T_1232_2 == io_in_release_bits_r_type;
+ assign T_1241 = 1'h0 | T_1237;
+ assign T_1242 = T_1241 | T_1238;
+ assign T_1243 = T_1242 | T_1239;
+ assign T_1244 = 1'h1 & T_1243;
+ assign T_1246 = T_1244 == 1'h0;
+ assign T_1248 = io_in_release_bits_addr_beat == 1'h0;
+ assign rel_roq_enq = T_1246 | T_1248;
+ assign T_1251 = acq_roq_enq == 1'h0;
+ assign acq_roq_ready = T_1251 | acqRoq_io_enq_ready;
+ assign T_1254 = rel_roq_enq == 1'h0;
+ assign rel_roq_ready = T_1254 | relRoq_io_enq_ready;
+ assign T_1256 = io_in_acquire_valid & acqArb_io_in_0_ready;
+ assign T_1257 = T_1256 & acq_roq_enq;
+ assign T_1258 = io_in_acquire_valid & acq_roq_ready;
+ assign T_1261 = io_in_acquire_bits_is_builtin_type ? io_in_acquire_bits_a_type : 3'h1;
+ assign T_1263 = {5'h0,1'h1};
+ assign T_1264 = {3'h7,T_1263};
+ assign T_1265 = io_in_acquire_bits_is_builtin_type ? io_in_acquire_bits_union : T_1264;
+ assign T_1294_addr_block = io_in_acquire_bits_addr_block;
+ assign T_1294_client_xact_id = io_in_acquire_bits_client_xact_id;
+ assign T_1294_addr_beat = io_in_acquire_bits_addr_beat;
+ assign T_1294_is_builtin_type = 1'h1;
+ assign T_1294_a_type = T_1261;
+ assign T_1294_union = T_1265;
+ assign T_1294_data = io_in_acquire_bits_data;
+ assign T_1322 = acq_roq_ready & acqArb_io_in_0_ready;
+ assign T_1323 = io_in_release_valid & acqArb_io_in_1_ready;
+ assign T_1324 = T_1323 & rel_roq_enq;
+ assign T_1325 = io_in_release_valid & rel_roq_ready;
+ assign GEN_0 = $signed(16'hffff);
+ assign T_1347 = $unsigned(GEN_0);
+ assign T_1355 = {1'h0,3'h7};
+ assign T_1356 = {1'h0,1'h1};
+ assign T_1357 = {T_1355,T_1356};
+ assign T_1359 = {1'h0,1'h1};
+ assign T_1360 = {3'h7,T_1359};
+ assign T_1362 = {T_1347,1'h1};
+ assign T_1364 = {T_1347,1'h1};
+ assign T_1366 = {1'h0,3'h7};
+ assign T_1367 = {1'h0,1'h1};
+ assign T_1368 = {T_1366,T_1367};
+ assign T_1370 = {5'h0,1'h1};
+ assign T_1372 = {5'h1,1'h1};
+ assign T_1373 = 3'h6 == 3'h3;
+ assign T_1374 = T_1373 ? T_1372 : 1'h0;
+ assign T_1375 = 3'h5 == 3'h3;
+ assign T_1376 = T_1375 ? T_1370 : T_1374;
+ assign T_1377 = 3'h4 == 3'h3;
+ assign T_1378 = T_1377 ? T_1368 : T_1376;
+ assign T_1379 = 3'h3 == 3'h3;
+ assign T_1380 = T_1379 ? T_1364 : T_1378;
+ assign T_1381 = 3'h2 == 3'h3;
+ assign T_1382 = T_1381 ? T_1362 : T_1380;
+ assign T_1383 = 3'h1 == 3'h3;
+ assign T_1384 = T_1383 ? T_1360 : T_1382;
+ assign T_1385 = 3'h0 == 3'h3;
+ assign T_1386 = T_1385 ? T_1357 : T_1384;
+ assign T_1415_addr_block = io_in_release_bits_addr_block;
+ assign T_1415_client_xact_id = io_in_release_bits_client_xact_id;
+ assign T_1415_addr_beat = io_in_release_bits_addr_beat;
+ assign T_1415_is_builtin_type = 1'h1;
+ assign T_1415_a_type = 3'h3;
+ assign T_1415_union = T_1386;
+ assign T_1415_data = io_in_release_bits_data;
+ assign T_1443 = rel_roq_ready & acqArb_io_in_1_ready;
+ assign T_1444 = io_out_grant_ready & io_out_grant_valid;
+ assign T_1448_0 = 3'h5;
+ assign T_1451 = T_1448_0 == io_out_grant_bits_g_type;
+ assign T_1453 = 1'h0 | T_1451;
+ assign T_1455_0 = 1'h0;
+ assign T_1458 = T_1455_0 == io_out_grant_bits_g_type;
+ assign T_1460 = 1'h0 | T_1458;
+ assign T_1461 = io_out_grant_bits_is_builtin_type ? T_1453 : T_1460;
+ assign T_1462 = 1'h1 & T_1461;
+ assign T_1464 = T_1462 == 1'h0;
+ assign T_1466 = io_out_grant_bits_addr_beat == 2'h3;
+ assign T_1467 = T_1464 | T_1466;
+ assign T_1468 = T_1444 & T_1467;
+ assign T_1469 = io_out_grant_ready & io_out_grant_valid;
+ assign T_1473_0 = 3'h5;
+ assign T_1476 = T_1473_0 == io_out_grant_bits_g_type;
+ assign T_1478 = 1'h0 | T_1476;
+ assign T_1480_0 = 1'h0;
+ assign T_1483 = T_1480_0 == io_out_grant_bits_g_type;
+ assign T_1485 = 1'h0 | T_1483;
+ assign T_1486 = io_out_grant_bits_is_builtin_type ? T_1478 : T_1485;
+ assign T_1487 = 1'h1 & T_1486;
+ assign T_1489 = T_1487 == 1'h0;
+ assign T_1491 = io_out_grant_bits_addr_beat == 2'h3;
+ assign T_1492 = T_1489 | T_1491;
+ assign T_1493 = T_1469 & T_1492;
+ assign T_1494 = acqRoq_io_deq_data ? io_out_grant_bits_g_type : 1'h0;
+ assign acq_grant_addr_beat = io_out_grant_bits_addr_beat;
+ assign acq_grant_client_xact_id = io_out_grant_bits_client_xact_id;
+ assign acq_grant_manager_xact_id = io_out_grant_bits_manager_xact_id;
+ assign acq_grant_is_builtin_type = acqRoq_io_deq_data;
+ assign acq_grant_g_type = T_1494;
+ assign acq_grant_data = io_out_grant_bits_data;
+ assign T_1551 = relRoq_io_deq_data ? 3'h0 : io_out_grant_bits_g_type;
+ assign rel_grant_addr_beat = io_out_grant_bits_addr_beat;
+ assign rel_grant_client_xact_id = io_out_grant_bits_client_xact_id;
+ assign rel_grant_manager_xact_id = io_out_grant_bits_manager_xact_id;
+ assign rel_grant_is_builtin_type = 1'h1;
+ assign rel_grant_g_type = T_1551;
+ assign rel_grant_data = io_out_grant_bits_data;
+ assign T_1606_addr_beat = acqRoq_io_deq_matches ? acq_grant_addr_beat : rel_grant_addr_beat;
+ assign T_1606_client_xact_id = acqRoq_io_deq_matches ? acq_grant_client_xact_id : rel_grant_client_xact_id;
+ assign T_1606_manager_xact_id = acqRoq_io_deq_matches ? acq_grant_manager_xact_id : rel_grant_manager_xact_id;
+ assign T_1606_is_builtin_type = acqRoq_io_deq_matches ? acq_grant_is_builtin_type : rel_grant_is_builtin_type;
+ assign T_1606_g_type = acqRoq_io_deq_matches ? acq_grant_g_type : rel_grant_g_type;
+ assign T_1606_data = acqRoq_io_deq_matches ? acq_grant_data : rel_grant_data;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ GEN_1 = {1{$random}};
+ GEN_2 = {1{$random}};
+ end
+`endif
+endmodule
+module TileLinkIONarrower(
+ input clk,
+ input reset,
+ output io_in_acquire_ready,
+ input io_in_acquire_valid,
+ input [25:0] io_in_acquire_bits_addr_block,
+ input [3:0] io_in_acquire_bits_client_xact_id,
+ input [1:0] io_in_acquire_bits_addr_beat,
+ input io_in_acquire_bits_is_builtin_type,
+ input [2:0] io_in_acquire_bits_a_type,
+ input [16:0] io_in_acquire_bits_union,
+ input [127:0] io_in_acquire_bits_data,
+ input io_in_grant_ready,
+ output io_in_grant_valid,
+ output [1:0] io_in_grant_bits_addr_beat,
+ output [3:0] io_in_grant_bits_client_xact_id,
+ output io_in_grant_bits_manager_xact_id,
+ output io_in_grant_bits_is_builtin_type,
+ output [3:0] io_in_grant_bits_g_type,
+ output [127:0] io_in_grant_bits_data,
+ input io_out_acquire_ready,
+ output io_out_acquire_valid,
+ output [25:0] io_out_acquire_bits_addr_block,
+ output [3:0] io_out_acquire_bits_client_xact_id,
+ output [2:0] io_out_acquire_bits_addr_beat,
+ output io_out_acquire_bits_is_builtin_type,
+ output [2:0] io_out_acquire_bits_a_type,
+ output [11:0] io_out_acquire_bits_union,
+ output [63:0] io_out_acquire_bits_data,
+ output io_out_grant_ready,
+ input io_out_grant_valid,
+ input [2:0] io_out_grant_bits_addr_beat,
+ input [3:0] io_out_grant_bits_client_xact_id,
+ input io_out_grant_bits_manager_xact_id,
+ input io_out_grant_bits_is_builtin_type,
+ input [3:0] io_out_grant_bits_g_type,
+ input [63:0] io_out_grant_bits_data
+);
+ wire T_815;
+ wire T_817;
+ wire T_819;
+ wire T_821;
+ reg [127:0] T_823;
+ reg [15:0] T_825;
+ reg [3:0] T_826;
+ reg [25:0] T_827;
+ reg [1:0] T_828;
+ reg T_830;
+ wire [3:0] T_831;
+ wire [5:0] T_832;
+ wire [31:0] T_833;
+ wire T_834;
+ wire [3:0] T_835;
+ wire [5:0] T_836;
+ wire [31:0] T_837;
+ wire [2:0] T_838;
+ wire [3:0] T_839;
+ wire [5:0] T_840;
+ wire [31:0] T_841;
+ wire [2:0] T_842;
+ wire [3:0] T_843;
+ wire T_844;
+ wire [1:0] T_846;
+ wire T_848;
+ wire T_849;
+ wire T_850;
+ wire T_851;
+ wire T_853_0;
+ wire T_853_1;
+ wire [8:0] T_858;
+ wire [7:0] T_859;
+ wire [8:0] T_861;
+ wire [7:0] T_862;
+ wire [7:0] T_864_0;
+ wire [7:0] T_864_1;
+ wire [15:0] T_868;
+ wire T_870;
+ wire T_871;
+ wire T_873;
+ wire T_874;
+ wire T_875;
+ wire [15:0] T_876;
+ wire [15:0] T_878;
+ wire [15:0] T_879;
+ wire [7:0] T_880;
+ wire [3:0] T_881;
+ wire T_882;
+ wire [1:0] T_884;
+ wire T_886;
+ wire T_887;
+ wire T_888;
+ wire T_889;
+ wire T_891_0;
+ wire T_891_1;
+ wire [8:0] T_896;
+ wire [7:0] T_897;
+ wire [8:0] T_899;
+ wire [7:0] T_900;
+ wire [7:0] T_902_0;
+ wire [7:0] T_902_1;
+ wire [15:0] T_906;
+ wire T_908;
+ wire T_909;
+ wire T_911;
+ wire T_912;
+ wire T_913;
+ wire [15:0] T_914;
+ wire [15:0] T_916;
+ wire [15:0] T_917;
+ wire [7:0] T_918;
+ wire [7:0] T_920_0;
+ wire [7:0] T_920_1;
+ wire [63:0] T_924;
+ wire [63:0] T_925;
+ wire [63:0] T_927_0;
+ wire [63:0] T_927_1;
+ wire T_932;
+ wire T_934;
+ wire [1:0] T_935;
+ wire T_936;
+ wire T_937;
+ wire [63:0] T_939;
+ wire [63:0] T_941;
+ wire [63:0] T_943;
+ wire [63:0] T_944;
+ wire T_945;
+ wire T_946;
+ wire [7:0] T_948;
+ wire [7:0] T_950;
+ wire [7:0] T_952;
+ wire [7:0] T_953;
+ wire T_954;
+ wire T_955;
+ wire T_957_0;
+ wire T_957_1;
+ wire T_963;
+ wire [2:0] T_964;
+ wire T_966;
+ wire T_968;
+ wire T_969;
+ wire T_970;
+ wire T_971;
+ wire [1:0] T_973;
+ wire [2:0] T_974;
+ wire [1:0] T_975;
+ wire T_977;
+ wire T_978;
+ wire T_980;
+ wire T_982;
+ wire T_984;
+ wire [2:0] T_985;
+ wire T_994;
+ wire T_995;
+ wire T_996;
+ wire T_997;
+ wire T_998;
+ wire T_999;
+ wire T_1000;
+ wire T_1001;
+ wire T_1002;
+ wire T_1003;
+ wire T_1004;
+ wire T_1005;
+ wire T_1006;
+ wire T_1007;
+ wire T_1009;
+ wire T_1011;
+ wire T_1012;
+ wire T_1013;
+ wire T_1015;
+ wire T_1017;
+ wire T_1019;
+ wire T_1020;
+ wire [3:0] T_1029;
+ wire [5:0] T_1030;
+ wire [9:0] T_1031;
+ wire [5:0] T_1033;
+ wire [8:0] T_1034;
+ wire [1:0] T_1036;
+ wire [1:0] T_1038;
+ wire [3:0] T_1040;
+ wire [5:0] T_1041;
+ wire [9:0] T_1042;
+ wire [5:0] T_1044;
+ wire [5:0] T_1046;
+ wire T_1047;
+ wire [5:0] T_1048;
+ wire T_1049;
+ wire [5:0] T_1050;
+ wire T_1051;
+ wire [9:0] T_1052;
+ wire T_1053;
+ wire [9:0] T_1054;
+ wire T_1055;
+ wire [9:0] T_1056;
+ wire T_1057;
+ wire [9:0] T_1058;
+ wire T_1059;
+ wire [9:0] T_1060;
+ wire [25:0] T_1089_addr_block;
+ wire [3:0] T_1089_client_xact_id;
+ wire [2:0] T_1089_addr_beat;
+ wire T_1089_is_builtin_type;
+ wire [2:0] T_1089_a_type;
+ wire [11:0] T_1089_union;
+ wire [63:0] T_1089_data;
+ wire [2:0] T_1117;
+ wire [63:0] T_1118;
+ wire [7:0] T_1119;
+ wire [3:0] T_1127;
+ wire [1:0] T_1128;
+ wire [5:0] T_1129;
+ wire [1:0] T_1131;
+ wire [4:0] T_1132;
+ wire [8:0] T_1134;
+ wire [8:0] T_1136;
+ wire [3:0] T_1138;
+ wire [1:0] T_1139;
+ wire [5:0] T_1140;
+ wire [5:0] T_1142;
+ wire [5:0] T_1144;
+ wire T_1145;
+ wire [5:0] T_1146;
+ wire T_1147;
+ wire [5:0] T_1148;
+ wire T_1149;
+ wire [5:0] T_1150;
+ wire T_1151;
+ wire [8:0] T_1152;
+ wire T_1153;
+ wire [8:0] T_1154;
+ wire T_1155;
+ wire [8:0] T_1156;
+ wire T_1157;
+ wire [8:0] T_1158;
+ wire [25:0] T_1187_addr_block;
+ wire [3:0] T_1187_client_xact_id;
+ wire [2:0] T_1187_addr_beat;
+ wire T_1187_is_builtin_type;
+ wire [2:0] T_1187_a_type;
+ wire [11:0] T_1187_union;
+ wire [63:0] T_1187_data;
+ wire [2:0] T_1215;
+ wire T_1216;
+ wire [5:0] T_1223;
+ wire [5:0] T_1224;
+ wire [11:0] T_1225;
+ wire [5:0] T_1227;
+ wire [8:0] T_1228;
+ wire [1:0] T_1230;
+ wire [1:0] T_1232;
+ wire [5:0] T_1234;
+ wire [5:0] T_1235;
+ wire [11:0] T_1236;
+ wire [5:0] T_1238;
+ wire [5:0] T_1240;
+ wire T_1241;
+ wire [5:0] T_1242;
+ wire T_1243;
+ wire [5:0] T_1244;
+ wire T_1245;
+ wire [11:0] T_1246;
+ wire T_1247;
+ wire [11:0] T_1248;
+ wire T_1249;
+ wire [11:0] T_1250;
+ wire T_1251;
+ wire [11:0] T_1252;
+ wire T_1253;
+ wire [11:0] T_1254;
+ wire [25:0] T_1283_addr_block;
+ wire [3:0] T_1283_client_xact_id;
+ wire [2:0] T_1283_addr_beat;
+ wire T_1283_is_builtin_type;
+ wire [2:0] T_1283_a_type;
+ wire [11:0] T_1283_union;
+ wire [63:0] T_1283_data;
+ wire [3:0] T_1318;
+ wire [1:0] T_1319;
+ wire [5:0] T_1320;
+ wire [1:0] T_1322;
+ wire [4:0] T_1323;
+ wire [8:0] T_1325;
+ wire [8:0] T_1327;
+ wire [3:0] T_1329;
+ wire [1:0] T_1330;
+ wire [5:0] T_1331;
+ wire [5:0] T_1333;
+ wire [5:0] T_1335;
+ wire T_1336;
+ wire [5:0] T_1337;
+ wire T_1338;
+ wire [5:0] T_1339;
+ wire T_1340;
+ wire [5:0] T_1341;
+ wire T_1342;
+ wire [8:0] T_1343;
+ wire T_1344;
+ wire [8:0] T_1345;
+ wire T_1346;
+ wire [8:0] T_1347;
+ wire T_1348;
+ wire [8:0] T_1349;
+ wire [25:0] T_1378_addr_block;
+ wire [3:0] T_1378_client_xact_id;
+ wire [2:0] T_1378_addr_beat;
+ wire T_1378_is_builtin_type;
+ wire [2:0] T_1378_a_type;
+ wire [11:0] T_1378_union;
+ wire [63:0] T_1378_data;
+ reg T_1407;
+ wire T_1409;
+ wire T_1410;
+ wire T_1412;
+ wire T_1413;
+ wire T_1414;
+ wire T_1415_clk;
+ wire T_1415_reset;
+ wire T_1415_io_enq_ready;
+ wire T_1415_io_enq_valid;
+ wire T_1415_io_enq_bits_data;
+ wire [3:0] T_1415_io_enq_bits_tag;
+ wire T_1415_io_deq_valid;
+ wire [3:0] T_1415_io_deq_tag;
+ wire T_1415_io_deq_data;
+ wire T_1415_io_deq_matches;
+ wire T_1417;
+ wire T_1418;
+ wire T_1419;
+ wire [25:0] T_1420_addr_block;
+ wire [3:0] T_1420_client_xact_id;
+ wire [2:0] T_1420_addr_beat;
+ wire T_1420_is_builtin_type;
+ wire [2:0] T_1420_a_type;
+ wire [11:0] T_1420_union;
+ wire [63:0] T_1420_data;
+ wire [25:0] T_1448_addr_block;
+ wire [3:0] T_1448_client_xact_id;
+ wire [2:0] T_1448_addr_beat;
+ wire T_1448_is_builtin_type;
+ wire [2:0] T_1448_a_type;
+ wire [11:0] T_1448_union;
+ wire [63:0] T_1448_data;
+ wire [25:0] T_1476_addr_block;
+ wire [3:0] T_1476_client_xact_id;
+ wire [2:0] T_1476_addr_beat;
+ wire T_1476_is_builtin_type;
+ wire [2:0] T_1476_a_type;
+ wire [11:0] T_1476_union;
+ wire [63:0] T_1476_data;
+ wire [25:0] T_1504_addr_block;
+ wire [3:0] T_1504_client_xact_id;
+ wire [2:0] T_1504_addr_beat;
+ wire T_1504_is_builtin_type;
+ wire [2:0] T_1504_a_type;
+ wire [11:0] T_1504_union;
+ wire [63:0] T_1504_data;
+ wire [25:0] T_1532_addr_block;
+ wire [3:0] T_1532_client_xact_id;
+ wire [2:0] T_1532_addr_beat;
+ wire T_1532_is_builtin_type;
+ wire [2:0] T_1532_a_type;
+ wire [11:0] T_1532_union;
+ wire [63:0] T_1532_data;
+ wire T_1560;
+ wire T_1561;
+ wire T_1562;
+ wire T_1564;
+ wire T_1566;
+ wire T_1567;
+ wire T_1568;
+ wire T_1569;
+ wire T_1570;
+ wire T_1571;
+ wire T_1572;
+ wire T_1573;
+ wire [3:0] T_1574;
+ wire T_1575;
+ wire [1:0] T_1577;
+ wire T_1579;
+ wire T_1580;
+ wire T_1581;
+ wire T_1582;
+ wire T_1584_0;
+ wire T_1584_1;
+ wire [8:0] T_1589;
+ wire [7:0] T_1590;
+ wire [8:0] T_1592;
+ wire [7:0] T_1593;
+ wire [7:0] T_1595_0;
+ wire [7:0] T_1595_1;
+ wire [15:0] T_1599;
+ wire T_1601;
+ wire T_1602;
+ wire T_1604;
+ wire T_1605;
+ wire T_1606;
+ wire [15:0] T_1607;
+ wire [15:0] T_1609;
+ wire [15:0] T_1610;
+ wire T_1612;
+ wire [63:0] T_1613;
+ wire [7:0] T_1614;
+ wire T_1616;
+ wire T_1618;
+ wire [1:0] T_1621;
+ wire T_1622;
+ wire T_1623;
+ wire [2:0] T_1628_0;
+ wire T_1631;
+ wire T_1633;
+ wire T_1635_0;
+ wire T_1638;
+ wire T_1640;
+ wire T_1641;
+ wire T_1642;
+ reg [63:0] T_1651_0;
+ reg [63:0] T_1651_1;
+ reg [3:0] T_1655;
+ reg T_1656;
+ reg [1:0] T_1658;
+ reg T_1660;
+ reg T_1662;
+ wire [127:0] T_1665;
+ wire [1:0] T_1693_addr_beat;
+ wire [3:0] T_1693_client_xact_id;
+ wire T_1693_manager_xact_id;
+ wire T_1693_is_builtin_type;
+ wire [3:0] T_1693_g_type;
+ wire [127:0] T_1693_data;
+ wire T_1721;
+ wire [6:0] T_1723;
+ wire T_1724;
+ wire T_1725;
+ wire [2:0] T_1729;
+ wire [190:0] T_1730;
+ wire [1:0] T_1758_addr_beat;
+ wire [3:0] T_1758_client_xact_id;
+ wire T_1758_manager_xact_id;
+ wire T_1758_is_builtin_type;
+ wire [3:0] T_1758_g_type;
+ wire [127:0] T_1758_data;
+ wire T_1786;
+ wire T_1787;
+ wire T_1788;
+ wire T_1790;
+ wire T_1791;
+ wire T_1792;
+ wire [1:0] T_1793_addr_beat;
+ wire [3:0] T_1793_client_xact_id;
+ wire T_1793_manager_xact_id;
+ wire T_1793_is_builtin_type;
+ wire [3:0] T_1793_g_type;
+ wire [127:0] T_1793_data;
+ wire [1:0] T_1820_addr_beat;
+ wire [3:0] T_1820_client_xact_id;
+ wire T_1820_manager_xact_id;
+ wire T_1820_is_builtin_type;
+ wire [3:0] T_1820_g_type;
+ wire [127:0] T_1820_data;
+ wire [1:0] T_1847_addr_beat;
+ wire [3:0] T_1847_client_xact_id;
+ wire T_1847_manager_xact_id;
+ wire T_1847_is_builtin_type;
+ wire [3:0] T_1847_g_type;
+ wire [127:0] T_1847_data;
+ wire T_1874;
+ wire T_1876;
+ wire T_1877;
+ wire [63:0] GEN_0;
+ wire T_1880;
+ wire T_1882;
+ wire [1:0] T_1885;
+ wire T_1886;
+ wire T_1887;
+ wire T_1889;
+ wire T_1891;
+ wire T_1893;
+ wire [2:0] T_1896;
+ wire [1:0] T_1897;
+ wire [1:0] T_1898;
+ wire GEN_1;
+ wire GEN_2;
+ wire GEN_3;
+ wire GEN_4;
+ ReorderQueue T_1415 (
+ .clk(T_1415_clk),
+ .reset(T_1415_reset),
+ .io_enq_ready(T_1415_io_enq_ready),
+ .io_enq_valid(T_1415_io_enq_valid),
+ .io_enq_bits_data(T_1415_io_enq_bits_data),
+ .io_enq_bits_tag(T_1415_io_enq_bits_tag),
+ .io_deq_valid(T_1415_io_deq_valid),
+ .io_deq_tag(T_1415_io_deq_tag),
+ .io_deq_data(T_1415_io_deq_data),
+ .io_deq_matches(T_1415_io_deq_matches)
+ );
+ assign io_in_acquire_ready = T_1571;
+ assign io_in_grant_valid = T_1788;
+ assign io_in_grant_bits_addr_beat = T_1847_addr_beat;
+ assign io_in_grant_bits_client_xact_id = T_1847_client_xact_id;
+ assign io_in_grant_bits_manager_xact_id = T_1847_manager_xact_id;
+ assign io_in_grant_bits_is_builtin_type = T_1847_is_builtin_type;
+ assign io_in_grant_bits_g_type = T_1847_g_type;
+ assign io_in_grant_bits_data = T_1847_data;
+ assign io_out_acquire_valid = T_1562;
+ assign io_out_acquire_bits_addr_block = T_1532_addr_block;
+ assign io_out_acquire_bits_client_xact_id = T_1532_client_xact_id;
+ assign io_out_acquire_bits_addr_beat = T_1532_addr_beat;
+ assign io_out_acquire_bits_is_builtin_type = T_1532_is_builtin_type;
+ assign io_out_acquire_bits_a_type = T_1532_a_type;
+ assign io_out_acquire_bits_union = T_1532_union;
+ assign io_out_acquire_bits_data = T_1532_data;
+ assign io_out_grant_ready = T_1792;
+ assign T_815 = io_in_acquire_bits_a_type == 3'h3;
+ assign T_817 = io_in_acquire_bits_a_type == 3'h1;
+ assign T_819 = io_in_acquire_bits_a_type == 3'h2;
+ assign T_821 = io_in_acquire_bits_a_type == 3'h0;
+ assign T_831 = io_in_acquire_bits_union[12:9];
+ assign T_832 = {io_in_acquire_bits_addr_beat,T_831};
+ assign T_833 = {io_in_acquire_bits_addr_block,T_832};
+ assign T_834 = T_833[3];
+ assign T_835 = io_in_acquire_bits_union[12:9];
+ assign T_836 = {io_in_acquire_bits_addr_beat,T_835};
+ assign T_837 = {io_in_acquire_bits_addr_block,T_836};
+ assign T_838 = T_837[5:3];
+ assign T_839 = io_in_acquire_bits_union[12:9];
+ assign T_840 = {io_in_acquire_bits_addr_beat,T_839};
+ assign T_841 = {io_in_acquire_bits_addr_block,T_840};
+ assign T_842 = T_841[2:0];
+ assign T_843 = io_in_acquire_bits_union[12:9];
+ assign T_844 = T_843[3];
+ assign T_846 = 1'h1 << T_844;
+ assign T_848 = io_in_acquire_bits_a_type == 3'h4;
+ assign T_849 = io_in_acquire_bits_is_builtin_type & T_848;
+ assign T_850 = T_846[0];
+ assign T_851 = T_846[1];
+ assign T_853_0 = T_850;
+ assign T_853_1 = T_851;
+ assign T_858 = 8'h0 - T_853_0;
+ assign T_859 = T_858[7:0];
+ assign T_861 = 8'h0 - T_853_1;
+ assign T_862 = T_861[7:0];
+ assign T_864_0 = T_859;
+ assign T_864_1 = T_862;
+ assign T_868 = {T_864_1,T_864_0};
+ assign T_870 = io_in_acquire_bits_a_type == 3'h3;
+ assign T_871 = io_in_acquire_bits_is_builtin_type & T_870;
+ assign T_873 = io_in_acquire_bits_a_type == 3'h2;
+ assign T_874 = io_in_acquire_bits_is_builtin_type & T_873;
+ assign T_875 = T_871 | T_874;
+ assign T_876 = io_in_acquire_bits_union[16:1];
+ assign T_878 = T_875 ? T_876 : 16'h0;
+ assign T_879 = T_849 ? T_868 : T_878;
+ assign T_880 = T_879[7:0];
+ assign T_881 = io_in_acquire_bits_union[12:9];
+ assign T_882 = T_881[3];
+ assign T_884 = 1'h1 << T_882;
+ assign T_886 = io_in_acquire_bits_a_type == 3'h4;
+ assign T_887 = io_in_acquire_bits_is_builtin_type & T_886;
+ assign T_888 = T_884[0];
+ assign T_889 = T_884[1];
+ assign T_891_0 = T_888;
+ assign T_891_1 = T_889;
+ assign T_896 = 8'h0 - T_891_0;
+ assign T_897 = T_896[7:0];
+ assign T_899 = 8'h0 - T_891_1;
+ assign T_900 = T_899[7:0];
+ assign T_902_0 = T_897;
+ assign T_902_1 = T_900;
+ assign T_906 = {T_902_1,T_902_0};
+ assign T_908 = io_in_acquire_bits_a_type == 3'h3;
+ assign T_909 = io_in_acquire_bits_is_builtin_type & T_908;
+ assign T_911 = io_in_acquire_bits_a_type == 3'h2;
+ assign T_912 = io_in_acquire_bits_is_builtin_type & T_911;
+ assign T_913 = T_909 | T_912;
+ assign T_914 = io_in_acquire_bits_union[16:1];
+ assign T_916 = T_913 ? T_914 : 16'h0;
+ assign T_917 = T_887 ? T_906 : T_916;
+ assign T_918 = T_917[15:8];
+ assign T_920_0 = T_880;
+ assign T_920_1 = T_918;
+ assign T_924 = io_in_acquire_bits_data[63:0];
+ assign T_925 = io_in_acquire_bits_data[127:64];
+ assign T_927_0 = T_924;
+ assign T_927_1 = T_925;
+ assign T_932 = T_920_0 != 1'h0;
+ assign T_934 = T_920_1 != 1'h0;
+ assign T_935 = {T_934,T_932};
+ assign T_936 = T_935[0];
+ assign T_937 = T_935[1];
+ assign T_939 = T_936 ? T_927_0 : 1'h0;
+ assign T_941 = T_937 ? T_927_1 : 1'h0;
+ assign T_943 = T_939 | T_941;
+ assign T_944 = T_943;
+ assign T_945 = T_935[0];
+ assign T_946 = T_935[1];
+ assign T_948 = T_945 ? T_920_0 : 1'h0;
+ assign T_950 = T_946 ? T_920_1 : 1'h0;
+ assign T_952 = T_948 | T_950;
+ assign T_953 = T_952;
+ assign T_954 = T_935[0];
+ assign T_955 = T_935[1];
+ assign T_957_0 = T_954;
+ assign T_957_1 = T_955;
+ assign T_963 = T_957_0 ? 1'h0 : 1'h1;
+ assign T_964 = {io_in_acquire_bits_addr_beat,T_963};
+ assign T_966 = io_in_acquire_valid == 1'h0;
+ assign T_968 = T_819 == 1'h0;
+ assign T_969 = T_966 | T_968;
+ assign T_970 = T_935[0];
+ assign T_971 = T_935[1];
+ assign T_973 = {1'h0,T_971};
+ assign T_974 = T_970 + T_973;
+ assign T_975 = T_974[1:0];
+ assign T_977 = T_975 <= 1'h1;
+ assign T_978 = T_969 | T_977;
+ assign T_980 = reset == 1'h0;
+ assign T_982 = T_978 == 1'h0;
+ assign T_984 = reset == 1'h0;
+ assign T_985 = io_in_acquire_bits_union[8:6];
+ assign T_994 = 3'h7 == T_985;
+ assign T_995 = T_994 ? 1'h0 : 1'h0;
+ assign T_996 = 3'h3 == T_985;
+ assign T_997 = T_996 ? 1'h1 : T_995;
+ assign T_998 = 3'h2 == T_985;
+ assign T_999 = T_998 ? 1'h1 : T_997;
+ assign T_1000 = 3'h5 == T_985;
+ assign T_1001 = T_1000 ? 1'h1 : T_999;
+ assign T_1002 = 3'h1 == T_985;
+ assign T_1003 = T_1002 ? 1'h1 : T_1001;
+ assign T_1004 = 3'h4 == T_985;
+ assign T_1005 = T_1004 ? 1'h1 : T_1003;
+ assign T_1006 = 3'h0 == T_985;
+ assign T_1007 = T_1006 ? 1'h1 : T_1005;
+ assign T_1009 = io_in_acquire_valid == 1'h0;
+ assign T_1011 = T_821 == 1'h0;
+ assign T_1012 = T_1009 | T_1011;
+ assign T_1013 = T_1012 | T_1007;
+ assign T_1015 = reset == 1'h0;
+ assign T_1017 = T_1013 == 1'h0;
+ assign T_1019 = reset == 1'h0;
+ assign T_1020 = io_in_acquire_bits_union[0];
+ assign T_1029 = {1'h0,3'h7};
+ assign T_1030 = {5'h0,T_1020};
+ assign T_1031 = {T_1029,T_1030};
+ assign T_1033 = {5'h0,T_1020};
+ assign T_1034 = {3'h7,T_1033};
+ assign T_1036 = {1'h0,T_1020};
+ assign T_1038 = {1'h0,T_1020};
+ assign T_1040 = {1'h0,3'h7};
+ assign T_1041 = {5'h0,T_1020};
+ assign T_1042 = {T_1040,T_1041};
+ assign T_1044 = {5'h0,T_1020};
+ assign T_1046 = {5'h1,T_1020};
+ assign T_1047 = 3'h6 == 3'h1;
+ assign T_1048 = T_1047 ? T_1046 : 1'h0;
+ assign T_1049 = 3'h5 == 3'h1;
+ assign T_1050 = T_1049 ? T_1044 : T_1048;
+ assign T_1051 = 3'h4 == 3'h1;
+ assign T_1052 = T_1051 ? T_1042 : T_1050;
+ assign T_1053 = 3'h3 == 3'h1;
+ assign T_1054 = T_1053 ? T_1038 : T_1052;
+ assign T_1055 = 3'h2 == 3'h1;
+ assign T_1056 = T_1055 ? T_1036 : T_1054;
+ assign T_1057 = 3'h1 == 3'h1;
+ assign T_1058 = T_1057 ? T_1034 : T_1056;
+ assign T_1059 = 3'h0 == 3'h1;
+ assign T_1060 = T_1059 ? T_1031 : T_1058;
+ assign T_1089_addr_block = io_in_acquire_bits_addr_block;
+ assign T_1089_client_xact_id = io_in_acquire_bits_client_xact_id;
+ assign T_1089_addr_beat = 1'h0;
+ assign T_1089_is_builtin_type = 1'h1;
+ assign T_1089_a_type = 3'h1;
+ assign T_1089_union = T_1060;
+ assign T_1089_data = 1'h0;
+ assign T_1117 = {T_828,T_830};
+ assign T_1118 = T_823[63:0];
+ assign T_1119 = T_825[7:0];
+ assign T_1127 = {1'h0,3'h7};
+ assign T_1128 = {1'h0,1'h1};
+ assign T_1129 = {T_1127,T_1128};
+ assign T_1131 = {1'h0,1'h1};
+ assign T_1132 = {3'h7,T_1131};
+ assign T_1134 = {T_1119,1'h1};
+ assign T_1136 = {T_1119,1'h1};
+ assign T_1138 = {1'h0,3'h7};
+ assign T_1139 = {1'h0,1'h1};
+ assign T_1140 = {T_1138,T_1139};
+ assign T_1142 = {5'h0,1'h1};
+ assign T_1144 = {5'h1,1'h1};
+ assign T_1145 = 3'h6 == 3'h3;
+ assign T_1146 = T_1145 ? T_1144 : 1'h0;
+ assign T_1147 = 3'h5 == 3'h3;
+ assign T_1148 = T_1147 ? T_1142 : T_1146;
+ assign T_1149 = 3'h4 == 3'h3;
+ assign T_1150 = T_1149 ? T_1140 : T_1148;
+ assign T_1151 = 3'h3 == 3'h3;
+ assign T_1152 = T_1151 ? T_1136 : T_1150;
+ assign T_1153 = 3'h2 == 3'h3;
+ assign T_1154 = T_1153 ? T_1134 : T_1152;
+ assign T_1155 = 3'h1 == 3'h3;
+ assign T_1156 = T_1155 ? T_1132 : T_1154;
+ assign T_1157 = 3'h0 == 3'h3;
+ assign T_1158 = T_1157 ? T_1129 : T_1156;
+ assign T_1187_addr_block = T_827;
+ assign T_1187_client_xact_id = T_826;
+ assign T_1187_addr_beat = T_1117;
+ assign T_1187_is_builtin_type = 1'h1;
+ assign T_1187_a_type = 3'h3;
+ assign T_1187_union = T_1158;
+ assign T_1187_data = T_1118;
+ assign T_1215 = io_in_acquire_bits_union[8:6];
+ assign T_1216 = io_in_acquire_bits_union[0];
+ assign T_1223 = {T_842,T_1215};
+ assign T_1224 = {5'h0,T_1216};
+ assign T_1225 = {T_1223,T_1224};
+ assign T_1227 = {5'h0,T_1216};
+ assign T_1228 = {T_1215,T_1227};
+ assign T_1230 = {1'h0,T_1216};
+ assign T_1232 = {1'h0,T_1216};
+ assign T_1234 = {T_842,T_1215};
+ assign T_1235 = {5'h0,T_1216};
+ assign T_1236 = {T_1234,T_1235};
+ assign T_1238 = {5'h0,T_1216};
+ assign T_1240 = {5'h1,T_1216};
+ assign T_1241 = 3'h6 == 3'h0;
+ assign T_1242 = T_1241 ? T_1240 : 1'h0;
+ assign T_1243 = 3'h5 == 3'h0;
+ assign T_1244 = T_1243 ? T_1238 : T_1242;
+ assign T_1245 = 3'h4 == 3'h0;
+ assign T_1246 = T_1245 ? T_1236 : T_1244;
+ assign T_1247 = 3'h3 == 3'h0;
+ assign T_1248 = T_1247 ? T_1232 : T_1246;
+ assign T_1249 = 3'h2 == 3'h0;
+ assign T_1250 = T_1249 ? T_1230 : T_1248;
+ assign T_1251 = 3'h1 == 3'h0;
+ assign T_1252 = T_1251 ? T_1228 : T_1250;
+ assign T_1253 = 3'h0 == 3'h0;
+ assign T_1254 = T_1253 ? T_1225 : T_1252;
+ assign T_1283_addr_block = io_in_acquire_bits_addr_block;
+ assign T_1283_client_xact_id = io_in_acquire_bits_client_xact_id;
+ assign T_1283_addr_beat = T_838;
+ assign T_1283_is_builtin_type = 1'h1;
+ assign T_1283_a_type = 3'h0;
+ assign T_1283_union = T_1254;
+ assign T_1283_data = 1'h0;
+ assign T_1318 = {1'h0,3'h7};
+ assign T_1319 = {1'h0,1'h1};
+ assign T_1320 = {T_1318,T_1319};
+ assign T_1322 = {1'h0,1'h1};
+ assign T_1323 = {3'h7,T_1322};
+ assign T_1325 = {T_953,1'h1};
+ assign T_1327 = {T_953,1'h1};
+ assign T_1329 = {1'h0,3'h7};
+ assign T_1330 = {1'h0,1'h1};
+ assign T_1331 = {T_1329,T_1330};
+ assign T_1333 = {5'h0,1'h1};
+ assign T_1335 = {5'h1,1'h1};
+ assign T_1336 = 3'h6 == 3'h2;
+ assign T_1337 = T_1336 ? T_1335 : 1'h0;
+ assign T_1338 = 3'h5 == 3'h2;
+ assign T_1339 = T_1338 ? T_1333 : T_1337;
+ assign T_1340 = 3'h4 == 3'h2;
+ assign T_1341 = T_1340 ? T_1331 : T_1339;
+ assign T_1342 = 3'h3 == 3'h2;
+ assign T_1343 = T_1342 ? T_1327 : T_1341;
+ assign T_1344 = 3'h2 == 3'h2;
+ assign T_1345 = T_1344 ? T_1325 : T_1343;
+ assign T_1346 = 3'h1 == 3'h2;
+ assign T_1347 = T_1346 ? T_1323 : T_1345;
+ assign T_1348 = 3'h0 == 3'h2;
+ assign T_1349 = T_1348 ? T_1320 : T_1347;
+ assign T_1378_addr_block = io_in_acquire_bits_addr_block;
+ assign T_1378_client_xact_id = io_in_acquire_bits_client_xact_id;
+ assign T_1378_addr_beat = T_964;
+ assign T_1378_is_builtin_type = 1'h1;
+ assign T_1378_a_type = 3'h2;
+ assign T_1378_union = T_1349;
+ assign T_1378_data = T_944;
+ assign T_1409 = T_815 == 1'h0;
+ assign T_1410 = io_in_acquire_valid & T_1409;
+ assign T_1412 = T_821 == 1'h0;
+ assign T_1413 = T_1410 & T_1412;
+ assign T_1414 = T_821 & io_in_acquire_valid;
+ assign T_1415_clk = clk;
+ assign T_1415_reset = reset;
+ assign T_1415_io_enq_valid = T_1419;
+ assign T_1415_io_enq_bits_data = T_834;
+ assign T_1415_io_enq_bits_tag = io_in_acquire_bits_client_xact_id;
+ assign T_1415_io_deq_valid = T_1725;
+ assign T_1415_io_deq_tag = io_out_grant_bits_client_xact_id;
+ assign T_1417 = T_1407 == 1'h0;
+ assign T_1418 = T_1414 & io_out_acquire_ready;
+ assign T_1419 = T_1418 & T_1417;
+ assign T_1420_addr_block = io_in_acquire_bits_addr_block;
+ assign T_1420_client_xact_id = io_in_acquire_bits_client_xact_id;
+ assign T_1420_addr_beat = io_in_acquire_bits_addr_beat;
+ assign T_1420_is_builtin_type = io_in_acquire_bits_is_builtin_type;
+ assign T_1420_a_type = io_in_acquire_bits_a_type;
+ assign T_1420_union = io_in_acquire_bits_union;
+ assign T_1420_data = io_in_acquire_bits_data;
+ assign T_1448_addr_block = T_821 ? T_1283_addr_block : T_1420_addr_block;
+ assign T_1448_client_xact_id = T_821 ? T_1283_client_xact_id : T_1420_client_xact_id;
+ assign T_1448_addr_beat = T_821 ? T_1283_addr_beat : T_1420_addr_beat;
+ assign T_1448_is_builtin_type = T_821 ? T_1283_is_builtin_type : T_1420_is_builtin_type;
+ assign T_1448_a_type = T_821 ? T_1283_a_type : T_1420_a_type;
+ assign T_1448_union = T_821 ? T_1283_union : T_1420_union;
+ assign T_1448_data = T_821 ? T_1283_data : T_1420_data;
+ assign T_1476_addr_block = T_819 ? T_1378_addr_block : T_1448_addr_block;
+ assign T_1476_client_xact_id = T_819 ? T_1378_client_xact_id : T_1448_client_xact_id;
+ assign T_1476_addr_beat = T_819 ? T_1378_addr_beat : T_1448_addr_beat;
+ assign T_1476_is_builtin_type = T_819 ? T_1378_is_builtin_type : T_1448_is_builtin_type;
+ assign T_1476_a_type = T_819 ? T_1378_a_type : T_1448_a_type;
+ assign T_1476_union = T_819 ? T_1378_union : T_1448_union;
+ assign T_1476_data = T_819 ? T_1378_data : T_1448_data;
+ assign T_1504_addr_block = T_817 ? T_1089_addr_block : T_1476_addr_block;
+ assign T_1504_client_xact_id = T_817 ? T_1089_client_xact_id : T_1476_client_xact_id;
+ assign T_1504_addr_beat = T_817 ? T_1089_addr_beat : T_1476_addr_beat;
+ assign T_1504_is_builtin_type = T_817 ? T_1089_is_builtin_type : T_1476_is_builtin_type;
+ assign T_1504_a_type = T_817 ? T_1089_a_type : T_1476_a_type;
+ assign T_1504_union = T_817 ? T_1089_union : T_1476_union;
+ assign T_1504_data = T_817 ? T_1089_data : T_1476_data;
+ assign T_1532_addr_block = T_1407 ? T_1187_addr_block : T_1504_addr_block;
+ assign T_1532_client_xact_id = T_1407 ? T_1187_client_xact_id : T_1504_client_xact_id;
+ assign T_1532_addr_beat = T_1407 ? T_1187_addr_beat : T_1504_addr_beat;
+ assign T_1532_is_builtin_type = T_1407 ? T_1187_is_builtin_type : T_1504_is_builtin_type;
+ assign T_1532_a_type = T_1407 ? T_1187_a_type : T_1504_a_type;
+ assign T_1532_union = T_1407 ? T_1187_union : T_1504_union;
+ assign T_1532_data = T_1407 ? T_1187_data : T_1504_data;
+ assign T_1560 = T_1407 | T_1413;
+ assign T_1561 = T_1414 & T_1415_io_enq_ready;
+ assign T_1562 = T_1560 | T_1561;
+ assign T_1564 = T_1407 == 1'h0;
+ assign T_1566 = T_821 == 1'h0;
+ assign T_1567 = T_1566 & io_out_acquire_ready;
+ assign T_1568 = T_815 | T_1567;
+ assign T_1569 = T_1415_io_enq_ready & io_out_acquire_ready;
+ assign T_1570 = T_1568 | T_1569;
+ assign T_1571 = T_1564 & T_1570;
+ assign T_1572 = io_in_acquire_ready & io_in_acquire_valid;
+ assign T_1573 = T_1572 & T_815;
+ assign T_1574 = io_in_acquire_bits_union[12:9];
+ assign T_1575 = T_1574[3];
+ assign T_1577 = 1'h1 << T_1575;
+ assign T_1579 = io_in_acquire_bits_a_type == 3'h4;
+ assign T_1580 = io_in_acquire_bits_is_builtin_type & T_1579;
+ assign T_1581 = T_1577[0];
+ assign T_1582 = T_1577[1];
+ assign T_1584_0 = T_1581;
+ assign T_1584_1 = T_1582;
+ assign T_1589 = 8'h0 - T_1584_0;
+ assign T_1590 = T_1589[7:0];
+ assign T_1592 = 8'h0 - T_1584_1;
+ assign T_1593 = T_1592[7:0];
+ assign T_1595_0 = T_1590;
+ assign T_1595_1 = T_1593;
+ assign T_1599 = {T_1595_1,T_1595_0};
+ assign T_1601 = io_in_acquire_bits_a_type == 3'h3;
+ assign T_1602 = io_in_acquire_bits_is_builtin_type & T_1601;
+ assign T_1604 = io_in_acquire_bits_a_type == 3'h2;
+ assign T_1605 = io_in_acquire_bits_is_builtin_type & T_1604;
+ assign T_1606 = T_1602 | T_1605;
+ assign T_1607 = io_in_acquire_bits_union[16:1];
+ assign T_1609 = T_1606 ? T_1607 : 16'h0;
+ assign T_1610 = T_1580 ? T_1599 : T_1609;
+ assign T_1612 = T_1407 & io_out_acquire_ready;
+ assign T_1613 = T_823[127:64];
+ assign T_1614 = T_825[15:8];
+ assign T_1616 = T_830 == 1'h1;
+ assign T_1618 = 1'h0 & T_1616;
+ assign T_1621 = T_830 + 1'h1;
+ assign T_1622 = T_1621[0:0];
+ assign T_1623 = T_1618 ? 1'h0 : T_1622;
+ assign T_1628_0 = 3'h5;
+ assign T_1631 = T_1628_0 == io_out_grant_bits_g_type;
+ assign T_1633 = 1'h0 | T_1631;
+ assign T_1635_0 = 1'h0;
+ assign T_1638 = T_1635_0 == io_out_grant_bits_g_type;
+ assign T_1640 = 1'h0 | T_1638;
+ assign T_1641 = io_out_grant_bits_is_builtin_type ? T_1633 : T_1640;
+ assign T_1642 = 1'h1 & T_1641;
+ assign T_1665 = {T_1651_1,T_1651_0};
+ assign T_1693_addr_beat = T_1658;
+ assign T_1693_client_xact_id = T_1655;
+ assign T_1693_manager_xact_id = T_1656;
+ assign T_1693_is_builtin_type = 1'h1;
+ assign T_1693_g_type = 3'h5;
+ assign T_1693_data = T_1665;
+ assign T_1721 = io_out_grant_bits_g_type == 3'h4;
+ assign T_1723 = {T_1415_io_deq_data,6'h0};
+ assign T_1724 = io_out_grant_ready & io_out_grant_valid;
+ assign T_1725 = T_1724 & T_1721;
+ assign T_1729 = io_out_grant_bits_addr_beat >> 1'h1;
+ assign T_1730 = io_out_grant_bits_data << T_1723;
+ assign T_1758_addr_beat = T_1729;
+ assign T_1758_client_xact_id = io_out_grant_bits_client_xact_id;
+ assign T_1758_manager_xact_id = io_out_grant_bits_manager_xact_id;
+ assign T_1758_is_builtin_type = 1'h1;
+ assign T_1758_g_type = 3'h4;
+ assign T_1758_data = T_1730;
+ assign T_1786 = T_1642 == 1'h0;
+ assign T_1787 = io_out_grant_valid & T_1786;
+ assign T_1788 = T_1662 | T_1787;
+ assign T_1790 = T_1662 == 1'h0;
+ assign T_1791 = T_1642 | io_in_grant_ready;
+ assign T_1792 = T_1790 & T_1791;
+ assign T_1793_addr_beat = io_out_grant_bits_addr_beat;
+ assign T_1793_client_xact_id = io_out_grant_bits_client_xact_id;
+ assign T_1793_manager_xact_id = io_out_grant_bits_manager_xact_id;
+ assign T_1793_is_builtin_type = io_out_grant_bits_is_builtin_type;
+ assign T_1793_g_type = io_out_grant_bits_g_type;
+ assign T_1793_data = io_out_grant_bits_data;
+ assign T_1820_addr_beat = T_1721 ? T_1758_addr_beat : T_1793_addr_beat;
+ assign T_1820_client_xact_id = T_1721 ? T_1758_client_xact_id : T_1793_client_xact_id;
+ assign T_1820_manager_xact_id = T_1721 ? T_1758_manager_xact_id : T_1793_manager_xact_id;
+ assign T_1820_is_builtin_type = T_1721 ? T_1758_is_builtin_type : T_1793_is_builtin_type;
+ assign T_1820_g_type = T_1721 ? T_1758_g_type : T_1793_g_type;
+ assign T_1820_data = T_1721 ? T_1758_data : T_1793_data;
+ assign T_1847_addr_beat = T_1662 ? T_1693_addr_beat : T_1820_addr_beat;
+ assign T_1847_client_xact_id = T_1662 ? T_1693_client_xact_id : T_1820_client_xact_id;
+ assign T_1847_manager_xact_id = T_1662 ? T_1693_manager_xact_id : T_1820_manager_xact_id;
+ assign T_1847_is_builtin_type = T_1662 ? T_1693_is_builtin_type : T_1820_is_builtin_type;
+ assign T_1847_g_type = T_1662 ? T_1693_g_type : T_1820_g_type;
+ assign T_1847_data = T_1662 ? T_1693_data : T_1820_data;
+ assign T_1874 = io_out_grant_valid & T_1642;
+ assign T_1876 = T_1662 == 1'h0;
+ assign T_1877 = T_1874 & T_1876;
+ assign GEN_0 = io_out_grant_bits_data;
+ assign T_1880 = T_1660 == 1'h1;
+ assign T_1882 = 1'h0 & T_1880;
+ assign T_1885 = T_1660 + 1'h1;
+ assign T_1886 = T_1885[0:0];
+ assign T_1887 = T_1882 ? 1'h0 : T_1886;
+ assign T_1889 = io_in_grant_ready & T_1662;
+ assign T_1891 = T_1658 == 2'h3;
+ assign T_1893 = 1'h0 & T_1891;
+ assign T_1896 = T_1658 + 1'h1;
+ assign T_1897 = T_1896[1:0];
+ assign T_1898 = T_1893 ? 1'h0 : T_1897;
+ assign GEN_1 = T_980 & T_982;
+ assign GEN_2 = T_1015 & T_1017;
+ assign GEN_3 = 1'h0 == T_1660;
+ assign GEN_4 = 1'h1 == T_1660;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_823 = {4{$random}};
+ T_825 = {1{$random}};
+ T_826 = {1{$random}};
+ T_827 = {1{$random}};
+ T_828 = {1{$random}};
+ T_830 = {1{$random}};
+ T_1407 = {1{$random}};
+ T_1651_0 = {2{$random}};
+ T_1651_1 = {2{$random}};
+ T_1655 = {1{$random}};
+ T_1656 = {1{$random}};
+ T_1658 = {1{$random}};
+ T_1660 = {1{$random}};
+ T_1662 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1612) begin
+ T_823 <= T_1613;
+ end else begin
+ if(T_1573) begin
+ T_823 <= io_in_acquire_bits_data;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1612) begin
+ T_825 <= T_1614;
+ end else begin
+ if(T_1573) begin
+ T_825 <= T_1610;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1573) begin
+ T_826 <= io_in_acquire_bits_client_xact_id;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1573) begin
+ T_827 <= io_in_acquire_bits_addr_block;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1573) begin
+ T_828 <= io_in_acquire_bits_addr_beat;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_830 <= 1'h0;
+ end else begin
+ if(T_1612) begin
+ T_830 <= T_1623;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_1407 <= 1'h0;
+ end else begin
+ if(T_1612) begin
+ if(T_1616) begin
+ T_1407 <= 1'h0;
+ end else begin
+ if(T_1573) begin
+ T_1407 <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1573) begin
+ T_1407 <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1877) begin
+ if(GEN_3) begin
+ T_1651_0 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1877) begin
+ if(GEN_4) begin
+ T_1651_1 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1877) begin
+ if(T_1880) begin
+ T_1655 <= io_out_grant_bits_client_xact_id;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1877) begin
+ if(T_1880) begin
+ T_1656 <= io_out_grant_bits_manager_xact_id;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_1658 <= 2'h0;
+ end else begin
+ if(T_1889) begin
+ T_1658 <= T_1898;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_1660 <= 1'h0;
+ end else begin
+ if(T_1877) begin
+ T_1660 <= T_1887;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_1662 <= 1'h0;
+ end else begin
+ if(T_1889) begin
+ T_1662 <= 1'h0;
+ end else begin
+ if(T_1877) begin
+ if(T_1880) begin
+ T_1662 <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ `ifndef SYNTHESIS
+ if(GEN_1 & T_984) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Can't perform Put wider than outer width");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_980 & T_982) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_2 & T_1019) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Can't perform Get wider than outer width");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_1015 & T_1017) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ end
+endmodule
+module ReorderQueue_70(
+ input clk,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [2:0] io_enq_bits_data_addr_beat,
+ input [2:0] io_enq_bits_data_byteOff,
+ input io_enq_bits_data_subblock,
+ input [4:0] io_enq_bits_tag,
+ input io_deq_valid,
+ input [4:0] io_deq_tag,
+ output [2:0] io_deq_data_addr_beat,
+ output [2:0] io_deq_data_byteOff,
+ output io_deq_data_subblock,
+ output io_deq_matches
+);
+ reg [2:0] roq_data_0_addr_beat;
+ reg [2:0] roq_data_0_byteOff;
+ reg roq_data_0_subblock;
+ reg [2:0] roq_data_1_addr_beat;
+ reg [2:0] roq_data_1_byteOff;
+ reg roq_data_1_subblock;
+ reg [2:0] roq_data_2_addr_beat;
+ reg [2:0] roq_data_2_byteOff;
+ reg roq_data_2_subblock;
+ reg [2:0] roq_data_3_addr_beat;
+ reg [2:0] roq_data_3_byteOff;
+ reg roq_data_3_subblock;
+ reg [2:0] roq_data_4_addr_beat;
+ reg [2:0] roq_data_4_byteOff;
+ reg roq_data_4_subblock;
+ reg [2:0] roq_data_5_addr_beat;
+ reg [2:0] roq_data_5_byteOff;
+ reg roq_data_5_subblock;
+ reg [2:0] roq_data_6_addr_beat;
+ reg [2:0] roq_data_6_byteOff;
+ reg roq_data_6_subblock;
+ reg [2:0] roq_data_7_addr_beat;
+ reg [2:0] roq_data_7_byteOff;
+ reg roq_data_7_subblock;
+ reg [2:0] roq_data_8_addr_beat;
+ reg [2:0] roq_data_8_byteOff;
+ reg roq_data_8_subblock;
+ reg [4:0] roq_tags_0;
+ reg [4:0] roq_tags_1;
+ reg [4:0] roq_tags_2;
+ reg [4:0] roq_tags_3;
+ reg [4:0] roq_tags_4;
+ reg [4:0] roq_tags_5;
+ reg [4:0] roq_tags_6;
+ reg [4:0] roq_tags_7;
+ reg [4:0] roq_tags_8;
+ wire T_832_0;
+ wire T_832_1;
+ wire T_832_2;
+ wire T_832_3;
+ wire T_832_4;
+ wire T_832_5;
+ wire T_832_6;
+ wire T_832_7;
+ wire T_832_8;
+ reg roq_free_0;
+ reg roq_free_1;
+ reg roq_free_2;
+ reg roq_free_3;
+ reg roq_free_4;
+ reg roq_free_5;
+ reg roq_free_6;
+ reg roq_free_7;
+ reg roq_free_8;
+ wire [3:0] T_865;
+ wire [3:0] T_866;
+ wire [3:0] T_867;
+ wire [3:0] T_868;
+ wire [3:0] T_869;
+ wire [3:0] T_870;
+ wire [3:0] T_871;
+ wire [3:0] roq_enq_addr;
+ wire T_873;
+ wire T_875;
+ wire T_876;
+ wire T_877;
+ wire T_879;
+ wire T_880;
+ wire T_881;
+ wire T_883;
+ wire T_884;
+ wire T_885;
+ wire T_887;
+ wire T_888;
+ wire T_889;
+ wire T_891;
+ wire T_892;
+ wire T_893;
+ wire T_895;
+ wire T_896;
+ wire T_897;
+ wire T_899;
+ wire T_900;
+ wire T_901;
+ wire T_903;
+ wire T_904;
+ wire T_905;
+ wire T_907;
+ wire T_908;
+ wire [3:0] T_918;
+ wire [3:0] T_919;
+ wire [3:0] T_920;
+ wire [3:0] T_921;
+ wire [3:0] T_922;
+ wire [3:0] T_923;
+ wire [3:0] T_924;
+ wire [3:0] roq_deq_addr;
+ wire T_926;
+ wire T_927;
+ wire T_928;
+ wire T_929;
+ wire T_930;
+ wire T_931;
+ wire T_932;
+ wire T_933;
+ wire [2:0] GEN_0;
+ wire [2:0] GEN_1;
+ wire GEN_2;
+ wire T_958;
+ wire T_959;
+ wire T_960;
+ wire T_961;
+ wire T_962;
+ wire T_963;
+ wire T_964;
+ wire T_965;
+ wire T_966;
+ wire [2:0] GEN_3;
+ wire [2:0] GEN_4;
+ wire GEN_5;
+ wire [4:0] GEN_6;
+ wire GEN_7;
+ wire GEN_8;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ wire GEN_17;
+ wire GEN_18;
+ wire GEN_19;
+ wire GEN_20;
+ wire GEN_21;
+ wire GEN_22;
+ wire GEN_23;
+ wire GEN_24;
+ wire GEN_25;
+ wire GEN_26;
+ wire GEN_27;
+ wire GEN_28;
+ wire GEN_29;
+ wire GEN_30;
+ wire GEN_31;
+ wire GEN_32;
+ wire GEN_33;
+ wire GEN_34;
+ wire GEN_35;
+ wire GEN_36;
+ wire GEN_37;
+ wire GEN_38;
+ wire GEN_39;
+ wire GEN_40;
+ wire GEN_41;
+ wire GEN_42;
+ wire GEN_43;
+ wire GEN_44;
+ wire GEN_45;
+ wire GEN_46;
+ wire GEN_47;
+ wire GEN_48;
+ wire GEN_49;
+ wire GEN_50;
+ wire GEN_51;
+ wire GEN_52;
+ wire GEN_53;
+ wire GEN_54;
+ wire GEN_55;
+ wire GEN_56;
+ wire GEN_57;
+ wire GEN_58;
+ wire GEN_59;
+ wire GEN_60;
+ wire GEN_61;
+ wire GEN_62;
+ wire GEN_63;
+ wire GEN_64;
+ wire GEN_65;
+ wire GEN_66;
+ wire GEN_67;
+ wire GEN_68;
+ wire GEN_69;
+ wire GEN_70;
+ wire GEN_71;
+ wire GEN_72;
+ wire GEN_73;
+ wire GEN_74;
+ wire GEN_75;
+ wire GEN_76;
+ wire GEN_77;
+ wire GEN_78;
+ wire GEN_79;
+ wire GEN_80;
+ wire GEN_81;
+ wire GEN_82;
+ wire GEN_83;
+ wire GEN_84;
+ wire GEN_85;
+ wire GEN_86;
+ wire GEN_87;
+ wire GEN_88;
+ wire GEN_89;
+ wire GEN_90;
+ wire GEN_91;
+ wire GEN_92;
+ wire GEN_93;
+ wire GEN_94;
+ wire GEN_95;
+ assign io_enq_ready = T_933;
+ assign io_deq_data_addr_beat = GEN_0;
+ assign io_deq_data_byteOff = GEN_1;
+ assign io_deq_data_subblock = GEN_2;
+ assign io_deq_matches = T_965;
+ assign T_832_0 = 1'h1;
+ assign T_832_1 = 1'h1;
+ assign T_832_2 = 1'h1;
+ assign T_832_3 = 1'h1;
+ assign T_832_4 = 1'h1;
+ assign T_832_5 = 1'h1;
+ assign T_832_6 = 1'h1;
+ assign T_832_7 = 1'h1;
+ assign T_832_8 = 1'h1;
+ assign T_865 = roq_free_7 ? 3'h7 : 4'h8;
+ assign T_866 = roq_free_6 ? 3'h6 : T_865;
+ assign T_867 = roq_free_5 ? 3'h5 : T_866;
+ assign T_868 = roq_free_4 ? 3'h4 : T_867;
+ assign T_869 = roq_free_3 ? 2'h3 : T_868;
+ assign T_870 = roq_free_2 ? 2'h2 : T_869;
+ assign T_871 = roq_free_1 ? 1'h1 : T_870;
+ assign roq_enq_addr = roq_free_0 ? 1'h0 : T_871;
+ assign T_873 = roq_tags_0 == io_deq_tag;
+ assign T_875 = roq_free_0 == 1'h0;
+ assign T_876 = T_873 & T_875;
+ assign T_877 = roq_tags_1 == io_deq_tag;
+ assign T_879 = roq_free_1 == 1'h0;
+ assign T_880 = T_877 & T_879;
+ assign T_881 = roq_tags_2 == io_deq_tag;
+ assign T_883 = roq_free_2 == 1'h0;
+ assign T_884 = T_881 & T_883;
+ assign T_885 = roq_tags_3 == io_deq_tag;
+ assign T_887 = roq_free_3 == 1'h0;
+ assign T_888 = T_885 & T_887;
+ assign T_889 = roq_tags_4 == io_deq_tag;
+ assign T_891 = roq_free_4 == 1'h0;
+ assign T_892 = T_889 & T_891;
+ assign T_893 = roq_tags_5 == io_deq_tag;
+ assign T_895 = roq_free_5 == 1'h0;
+ assign T_896 = T_893 & T_895;
+ assign T_897 = roq_tags_6 == io_deq_tag;
+ assign T_899 = roq_free_6 == 1'h0;
+ assign T_900 = T_897 & T_899;
+ assign T_901 = roq_tags_7 == io_deq_tag;
+ assign T_903 = roq_free_7 == 1'h0;
+ assign T_904 = T_901 & T_903;
+ assign T_905 = roq_tags_8 == io_deq_tag;
+ assign T_907 = roq_free_8 == 1'h0;
+ assign T_908 = T_905 & T_907;
+ assign T_918 = T_904 ? 3'h7 : 4'h8;
+ assign T_919 = T_900 ? 3'h6 : T_918;
+ assign T_920 = T_896 ? 3'h5 : T_919;
+ assign T_921 = T_892 ? 3'h4 : T_920;
+ assign T_922 = T_888 ? 2'h3 : T_921;
+ assign T_923 = T_884 ? 2'h2 : T_922;
+ assign T_924 = T_880 ? 1'h1 : T_923;
+ assign roq_deq_addr = T_876 ? 1'h0 : T_924;
+ assign T_926 = roq_free_0 | roq_free_1;
+ assign T_927 = T_926 | roq_free_2;
+ assign T_928 = T_927 | roq_free_3;
+ assign T_929 = T_928 | roq_free_4;
+ assign T_930 = T_929 | roq_free_5;
+ assign T_931 = T_930 | roq_free_6;
+ assign T_932 = T_931 | roq_free_7;
+ assign T_933 = T_932 | roq_free_8;
+ assign GEN_0 = GEN_72 ? roq_data_8_addr_beat : GEN_73 ? roq_data_7_addr_beat : GEN_74 ? roq_data_6_addr_beat : GEN_75 ? roq_data_5_addr_beat : GEN_76 ? roq_data_4_addr_beat : GEN_77 ? roq_data_3_addr_beat : GEN_78 ? roq_data_2_addr_beat : GEN_79 ? roq_data_1_addr_beat : roq_data_0_addr_beat;
+ assign GEN_1 = GEN_80 ? roq_data_8_byteOff : GEN_81 ? roq_data_7_byteOff : GEN_82 ? roq_data_6_byteOff : GEN_83 ? roq_data_5_byteOff : GEN_84 ? roq_data_4_byteOff : GEN_85 ? roq_data_3_byteOff : GEN_86 ? roq_data_2_byteOff : GEN_87 ? roq_data_1_byteOff : roq_data_0_byteOff;
+ assign GEN_2 = GEN_88 ? roq_data_8_subblock : GEN_89 ? roq_data_7_subblock : GEN_90 ? roq_data_6_subblock : GEN_91 ? roq_data_5_subblock : GEN_92 ? roq_data_4_subblock : GEN_93 ? roq_data_3_subblock : GEN_94 ? roq_data_2_subblock : GEN_95 ? roq_data_1_subblock : roq_data_0_subblock;
+ assign T_958 = T_876 | T_880;
+ assign T_959 = T_958 | T_884;
+ assign T_960 = T_959 | T_888;
+ assign T_961 = T_960 | T_892;
+ assign T_962 = T_961 | T_896;
+ assign T_963 = T_962 | T_900;
+ assign T_964 = T_963 | T_904;
+ assign T_965 = T_964 | T_908;
+ assign T_966 = io_enq_valid & io_enq_ready;
+ assign GEN_3 = io_enq_bits_data_addr_beat;
+ assign GEN_4 = io_enq_bits_data_byteOff;
+ assign GEN_5 = io_enq_bits_data_subblock;
+ assign GEN_6 = io_enq_bits_tag;
+ assign GEN_7 = 1'h0;
+ assign GEN_8 = 1'h1;
+ assign GEN_9 = 1'h0 == roq_enq_addr;
+ assign GEN_10 = 1'h0 == roq_enq_addr;
+ assign GEN_11 = 1'h0 == roq_enq_addr;
+ assign GEN_12 = 1'h1 == roq_enq_addr;
+ assign GEN_13 = 1'h1 == roq_enq_addr;
+ assign GEN_14 = 1'h1 == roq_enq_addr;
+ assign GEN_15 = 2'h2 == roq_enq_addr;
+ assign GEN_16 = 2'h2 == roq_enq_addr;
+ assign GEN_17 = 2'h2 == roq_enq_addr;
+ assign GEN_18 = 2'h3 == roq_enq_addr;
+ assign GEN_19 = 2'h3 == roq_enq_addr;
+ assign GEN_20 = 2'h3 == roq_enq_addr;
+ assign GEN_21 = 3'h4 == roq_enq_addr;
+ assign GEN_22 = 3'h4 == roq_enq_addr;
+ assign GEN_23 = 3'h4 == roq_enq_addr;
+ assign GEN_24 = 3'h5 == roq_enq_addr;
+ assign GEN_25 = 3'h5 == roq_enq_addr;
+ assign GEN_26 = 3'h5 == roq_enq_addr;
+ assign GEN_27 = 3'h6 == roq_enq_addr;
+ assign GEN_28 = 3'h6 == roq_enq_addr;
+ assign GEN_29 = 3'h6 == roq_enq_addr;
+ assign GEN_30 = 3'h7 == roq_enq_addr;
+ assign GEN_31 = 3'h7 == roq_enq_addr;
+ assign GEN_32 = 3'h7 == roq_enq_addr;
+ assign GEN_33 = 4'h8 == roq_enq_addr;
+ assign GEN_34 = 4'h8 == roq_enq_addr;
+ assign GEN_35 = 4'h8 == roq_enq_addr;
+ assign GEN_36 = 1'h0 == roq_enq_addr;
+ assign GEN_37 = 1'h1 == roq_enq_addr;
+ assign GEN_38 = 2'h2 == roq_enq_addr;
+ assign GEN_39 = 2'h3 == roq_enq_addr;
+ assign GEN_40 = 3'h4 == roq_enq_addr;
+ assign GEN_41 = 3'h5 == roq_enq_addr;
+ assign GEN_42 = 3'h6 == roq_enq_addr;
+ assign GEN_43 = 3'h7 == roq_enq_addr;
+ assign GEN_44 = 4'h8 == roq_enq_addr;
+ assign GEN_45 = 1'h0 == roq_deq_addr;
+ assign GEN_46 = 1'h0 == roq_enq_addr;
+ assign GEN_47 = 1'h0 == roq_enq_addr;
+ assign GEN_48 = 1'h1 == roq_deq_addr;
+ assign GEN_49 = 1'h1 == roq_enq_addr;
+ assign GEN_50 = 1'h1 == roq_enq_addr;
+ assign GEN_51 = 2'h2 == roq_deq_addr;
+ assign GEN_52 = 2'h2 == roq_enq_addr;
+ assign GEN_53 = 2'h2 == roq_enq_addr;
+ assign GEN_54 = 2'h3 == roq_deq_addr;
+ assign GEN_55 = 2'h3 == roq_enq_addr;
+ assign GEN_56 = 2'h3 == roq_enq_addr;
+ assign GEN_57 = 3'h4 == roq_deq_addr;
+ assign GEN_58 = 3'h4 == roq_enq_addr;
+ assign GEN_59 = 3'h4 == roq_enq_addr;
+ assign GEN_60 = 3'h5 == roq_deq_addr;
+ assign GEN_61 = 3'h5 == roq_enq_addr;
+ assign GEN_62 = 3'h5 == roq_enq_addr;
+ assign GEN_63 = 3'h6 == roq_deq_addr;
+ assign GEN_64 = 3'h6 == roq_enq_addr;
+ assign GEN_65 = 3'h6 == roq_enq_addr;
+ assign GEN_66 = 3'h7 == roq_deq_addr;
+ assign GEN_67 = 3'h7 == roq_enq_addr;
+ assign GEN_68 = 3'h7 == roq_enq_addr;
+ assign GEN_69 = 4'h8 == roq_deq_addr;
+ assign GEN_70 = 4'h8 == roq_enq_addr;
+ assign GEN_71 = 4'h8 == roq_enq_addr;
+ assign GEN_72 = 4'h8 == roq_deq_addr;
+ assign GEN_73 = 3'h7 == roq_deq_addr;
+ assign GEN_74 = 3'h6 == roq_deq_addr;
+ assign GEN_75 = 3'h5 == roq_deq_addr;
+ assign GEN_76 = 3'h4 == roq_deq_addr;
+ assign GEN_77 = 2'h3 == roq_deq_addr;
+ assign GEN_78 = 2'h2 == roq_deq_addr;
+ assign GEN_79 = 1'h1 == roq_deq_addr;
+ assign GEN_80 = 4'h8 == roq_deq_addr;
+ assign GEN_81 = 3'h7 == roq_deq_addr;
+ assign GEN_82 = 3'h6 == roq_deq_addr;
+ assign GEN_83 = 3'h5 == roq_deq_addr;
+ assign GEN_84 = 3'h4 == roq_deq_addr;
+ assign GEN_85 = 2'h3 == roq_deq_addr;
+ assign GEN_86 = 2'h2 == roq_deq_addr;
+ assign GEN_87 = 1'h1 == roq_deq_addr;
+ assign GEN_88 = 4'h8 == roq_deq_addr;
+ assign GEN_89 = 3'h7 == roq_deq_addr;
+ assign GEN_90 = 3'h6 == roq_deq_addr;
+ assign GEN_91 = 3'h5 == roq_deq_addr;
+ assign GEN_92 = 3'h4 == roq_deq_addr;
+ assign GEN_93 = 2'h3 == roq_deq_addr;
+ assign GEN_94 = 2'h2 == roq_deq_addr;
+ assign GEN_95 = 1'h1 == roq_deq_addr;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ roq_data_0_addr_beat = {1{$random}};
+ roq_data_0_byteOff = {1{$random}};
+ roq_data_0_subblock = {1{$random}};
+ roq_data_1_addr_beat = {1{$random}};
+ roq_data_1_byteOff = {1{$random}};
+ roq_data_1_subblock = {1{$random}};
+ roq_data_2_addr_beat = {1{$random}};
+ roq_data_2_byteOff = {1{$random}};
+ roq_data_2_subblock = {1{$random}};
+ roq_data_3_addr_beat = {1{$random}};
+ roq_data_3_byteOff = {1{$random}};
+ roq_data_3_subblock = {1{$random}};
+ roq_data_4_addr_beat = {1{$random}};
+ roq_data_4_byteOff = {1{$random}};
+ roq_data_4_subblock = {1{$random}};
+ roq_data_5_addr_beat = {1{$random}};
+ roq_data_5_byteOff = {1{$random}};
+ roq_data_5_subblock = {1{$random}};
+ roq_data_6_addr_beat = {1{$random}};
+ roq_data_6_byteOff = {1{$random}};
+ roq_data_6_subblock = {1{$random}};
+ roq_data_7_addr_beat = {1{$random}};
+ roq_data_7_byteOff = {1{$random}};
+ roq_data_7_subblock = {1{$random}};
+ roq_data_8_addr_beat = {1{$random}};
+ roq_data_8_byteOff = {1{$random}};
+ roq_data_8_subblock = {1{$random}};
+ roq_tags_0 = {1{$random}};
+ roq_tags_1 = {1{$random}};
+ roq_tags_2 = {1{$random}};
+ roq_tags_3 = {1{$random}};
+ roq_tags_4 = {1{$random}};
+ roq_tags_5 = {1{$random}};
+ roq_tags_6 = {1{$random}};
+ roq_tags_7 = {1{$random}};
+ roq_tags_8 = {1{$random}};
+ roq_free_0 = {1{$random}};
+ roq_free_1 = {1{$random}};
+ roq_free_2 = {1{$random}};
+ roq_free_3 = {1{$random}};
+ roq_free_4 = {1{$random}};
+ roq_free_5 = {1{$random}};
+ roq_free_6 = {1{$random}};
+ roq_free_7 = {1{$random}};
+ roq_free_8 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_9) begin
+ roq_data_0_addr_beat <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_10) begin
+ roq_data_0_byteOff <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_11) begin
+ roq_data_0_subblock <= GEN_5;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_12) begin
+ roq_data_1_addr_beat <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_13) begin
+ roq_data_1_byteOff <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_14) begin
+ roq_data_1_subblock <= GEN_5;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_15) begin
+ roq_data_2_addr_beat <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_16) begin
+ roq_data_2_byteOff <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_17) begin
+ roq_data_2_subblock <= GEN_5;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_18) begin
+ roq_data_3_addr_beat <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_19) begin
+ roq_data_3_byteOff <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_20) begin
+ roq_data_3_subblock <= GEN_5;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_21) begin
+ roq_data_4_addr_beat <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_22) begin
+ roq_data_4_byteOff <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_23) begin
+ roq_data_4_subblock <= GEN_5;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_24) begin
+ roq_data_5_addr_beat <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_25) begin
+ roq_data_5_byteOff <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_26) begin
+ roq_data_5_subblock <= GEN_5;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_27) begin
+ roq_data_6_addr_beat <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_28) begin
+ roq_data_6_byteOff <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_29) begin
+ roq_data_6_subblock <= GEN_5;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_30) begin
+ roq_data_7_addr_beat <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_31) begin
+ roq_data_7_byteOff <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_32) begin
+ roq_data_7_subblock <= GEN_5;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_33) begin
+ roq_data_8_addr_beat <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_34) begin
+ roq_data_8_byteOff <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_35) begin
+ roq_data_8_subblock <= GEN_5;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_36) begin
+ roq_tags_0 <= GEN_6;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_37) begin
+ roq_tags_1 <= GEN_6;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_38) begin
+ roq_tags_2 <= GEN_6;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_39) begin
+ roq_tags_3 <= GEN_6;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_40) begin
+ roq_tags_4 <= GEN_6;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_41) begin
+ roq_tags_5 <= GEN_6;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_42) begin
+ roq_tags_6 <= GEN_6;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_43) begin
+ roq_tags_7 <= GEN_6;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_966) begin
+ if(GEN_44) begin
+ roq_tags_8 <= GEN_6;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ roq_free_0 <= T_832_0;
+ end else begin
+ if(io_deq_valid) begin
+ if(GEN_45) begin
+ roq_free_0 <= GEN_8;
+ end else begin
+ if(T_966) begin
+ if(GEN_46) begin
+ roq_free_0 <= GEN_7;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_966) begin
+ if(GEN_47) begin
+ roq_free_0 <= GEN_7;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ roq_free_1 <= T_832_1;
+ end else begin
+ if(io_deq_valid) begin
+ if(GEN_48) begin
+ roq_free_1 <= GEN_8;
+ end else begin
+ if(T_966) begin
+ if(GEN_49) begin
+ roq_free_1 <= GEN_7;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_966) begin
+ if(GEN_50) begin
+ roq_free_1 <= GEN_7;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ roq_free_2 <= T_832_2;
+ end else begin
+ if(io_deq_valid) begin
+ if(GEN_51) begin
+ roq_free_2 <= GEN_8;
+ end else begin
+ if(T_966) begin
+ if(GEN_52) begin
+ roq_free_2 <= GEN_7;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_966) begin
+ if(GEN_53) begin
+ roq_free_2 <= GEN_7;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ roq_free_3 <= T_832_3;
+ end else begin
+ if(io_deq_valid) begin
+ if(GEN_54) begin
+ roq_free_3 <= GEN_8;
+ end else begin
+ if(T_966) begin
+ if(GEN_55) begin
+ roq_free_3 <= GEN_7;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_966) begin
+ if(GEN_56) begin
+ roq_free_3 <= GEN_7;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ roq_free_4 <= T_832_4;
+ end else begin
+ if(io_deq_valid) begin
+ if(GEN_57) begin
+ roq_free_4 <= GEN_8;
+ end else begin
+ if(T_966) begin
+ if(GEN_58) begin
+ roq_free_4 <= GEN_7;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_966) begin
+ if(GEN_59) begin
+ roq_free_4 <= GEN_7;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ roq_free_5 <= T_832_5;
+ end else begin
+ if(io_deq_valid) begin
+ if(GEN_60) begin
+ roq_free_5 <= GEN_8;
+ end else begin
+ if(T_966) begin
+ if(GEN_61) begin
+ roq_free_5 <= GEN_7;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_966) begin
+ if(GEN_62) begin
+ roq_free_5 <= GEN_7;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ roq_free_6 <= T_832_6;
+ end else begin
+ if(io_deq_valid) begin
+ if(GEN_63) begin
+ roq_free_6 <= GEN_8;
+ end else begin
+ if(T_966) begin
+ if(GEN_64) begin
+ roq_free_6 <= GEN_7;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_966) begin
+ if(GEN_65) begin
+ roq_free_6 <= GEN_7;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ roq_free_7 <= T_832_7;
+ end else begin
+ if(io_deq_valid) begin
+ if(GEN_66) begin
+ roq_free_7 <= GEN_8;
+ end else begin
+ if(T_966) begin
+ if(GEN_67) begin
+ roq_free_7 <= GEN_7;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_966) begin
+ if(GEN_68) begin
+ roq_free_7 <= GEN_7;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ roq_free_8 <= T_832_8;
+ end else begin
+ if(io_deq_valid) begin
+ if(GEN_69) begin
+ roq_free_8 <= GEN_8;
+ end else begin
+ if(T_966) begin
+ if(GEN_70) begin
+ roq_free_8 <= GEN_7;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_966) begin
+ if(GEN_71) begin
+ roq_free_8 <= GEN_7;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+endmodule
+module Arbiter(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input [2:0] io_in_0_bits_addr_beat,
+ input [3:0] io_in_0_bits_client_xact_id,
+ input io_in_0_bits_manager_xact_id,
+ input io_in_0_bits_is_builtin_type,
+ input [3:0] io_in_0_bits_g_type,
+ input [63:0] io_in_0_bits_data,
+ input io_in_0_bits_client_id,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input [2:0] io_in_1_bits_addr_beat,
+ input [3:0] io_in_1_bits_client_xact_id,
+ input io_in_1_bits_manager_xact_id,
+ input io_in_1_bits_is_builtin_type,
+ input [3:0] io_in_1_bits_g_type,
+ input [63:0] io_in_1_bits_data,
+ input io_in_1_bits_client_id,
+ input io_out_ready,
+ output io_out_valid,
+ output [2:0] io_out_bits_addr_beat,
+ output [3:0] io_out_bits_client_xact_id,
+ output io_out_bits_manager_xact_id,
+ output io_out_bits_is_builtin_type,
+ output [3:0] io_out_bits_g_type,
+ output [63:0] io_out_bits_data,
+ output io_out_bits_client_id,
+ output io_chosen
+);
+ wire T_658;
+ wire GEN_0;
+ wire [2:0] GEN_1;
+ wire [3:0] GEN_2;
+ wire GEN_3;
+ wire GEN_4;
+ wire [3:0] GEN_5;
+ wire [63:0] GEN_6;
+ wire GEN_7;
+ wire GEN_8;
+ wire T_839;
+ wire T_841;
+ wire T_843;
+ wire T_844;
+ wire T_845;
+ wire T_847;
+ wire T_848;
+ wire T_849;
+ wire T_852;
+ wire T_853;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ assign io_in_0_ready = T_845;
+ assign io_in_1_ready = T_849;
+ assign io_out_valid = GEN_0;
+ assign io_out_bits_addr_beat = GEN_1;
+ assign io_out_bits_client_xact_id = GEN_2;
+ assign io_out_bits_manager_xact_id = GEN_3;
+ assign io_out_bits_is_builtin_type = GEN_4;
+ assign io_out_bits_g_type = GEN_5;
+ assign io_out_bits_data = GEN_6;
+ assign io_out_bits_client_id = GEN_7;
+ assign io_chosen = T_658;
+ assign T_658 = T_853;
+ assign GEN_0 = GEN_9 ? io_in_1_valid : io_in_0_valid;
+ assign GEN_1 = GEN_10 ? io_in_1_bits_addr_beat : io_in_0_bits_addr_beat;
+ assign GEN_2 = GEN_11 ? io_in_1_bits_client_xact_id : io_in_0_bits_client_xact_id;
+ assign GEN_3 = GEN_12 ? io_in_1_bits_manager_xact_id : io_in_0_bits_manager_xact_id;
+ assign GEN_4 = GEN_13 ? io_in_1_bits_is_builtin_type : io_in_0_bits_is_builtin_type;
+ assign GEN_5 = GEN_14 ? io_in_1_bits_g_type : io_in_0_bits_g_type;
+ assign GEN_6 = GEN_15 ? io_in_1_bits_data : io_in_0_bits_data;
+ assign GEN_7 = GEN_16 ? io_in_1_bits_client_id : io_in_0_bits_client_id;
+ assign GEN_8 = 1'h0;
+ assign T_839 = 1'h0 | io_in_0_valid;
+ assign T_841 = T_839 == 1'h0;
+ assign T_843 = 1'h1 == 1'h0;
+ assign T_844 = 1'h0 ? T_843 : 1'h1;
+ assign T_845 = T_844 & io_out_ready;
+ assign T_847 = 1'h1 == 1'h1;
+ assign T_848 = 1'h0 ? T_847 : T_841;
+ assign T_849 = T_848 & io_out_ready;
+ assign T_852 = io_in_0_valid ? 1'h0 : 1'h1;
+ assign T_853 = 1'h0 ? 1'h1 : T_852;
+ assign GEN_9 = 1'h1 == T_658;
+ assign GEN_10 = 1'h1 == T_658;
+ assign GEN_11 = 1'h1 == T_658;
+ assign GEN_12 = 1'h1 == T_658;
+ assign GEN_13 = 1'h1 == T_658;
+ assign GEN_14 = 1'h1 == T_658;
+ assign GEN_15 = 1'h1 == T_658;
+ assign GEN_16 = 1'h1 == T_658;
+endmodule
+module NastiIOTileLinkIOConverter(
+ input clk,
+ input reset,
+ output io_tl_acquire_ready,
+ input io_tl_acquire_valid,
+ input [25:0] io_tl_acquire_bits_addr_block,
+ input [3:0] io_tl_acquire_bits_client_xact_id,
+ input [2:0] io_tl_acquire_bits_addr_beat,
+ input io_tl_acquire_bits_is_builtin_type,
+ input [2:0] io_tl_acquire_bits_a_type,
+ input [11:0] io_tl_acquire_bits_union,
+ input [63:0] io_tl_acquire_bits_data,
+ input io_tl_grant_ready,
+ output io_tl_grant_valid,
+ output [2:0] io_tl_grant_bits_addr_beat,
+ output [3:0] io_tl_grant_bits_client_xact_id,
+ output io_tl_grant_bits_manager_xact_id,
+ output io_tl_grant_bits_is_builtin_type,
+ output [3:0] io_tl_grant_bits_g_type,
+ output [63:0] io_tl_grant_bits_data,
+ input io_nasti_aw_ready,
+ output io_nasti_aw_valid,
+ output [31:0] io_nasti_aw_bits_addr,
+ output [7:0] io_nasti_aw_bits_len,
+ output [2:0] io_nasti_aw_bits_size,
+ output [1:0] io_nasti_aw_bits_burst,
+ output io_nasti_aw_bits_lock,
+ output [3:0] io_nasti_aw_bits_cache,
+ output [2:0] io_nasti_aw_bits_prot,
+ output [3:0] io_nasti_aw_bits_qos,
+ output [3:0] io_nasti_aw_bits_region,
+ output [4:0] io_nasti_aw_bits_id,
+ output io_nasti_aw_bits_user,
+ input io_nasti_w_ready,
+ output io_nasti_w_valid,
+ output [63:0] io_nasti_w_bits_data,
+ output io_nasti_w_bits_last,
+ output [7:0] io_nasti_w_bits_strb,
+ output io_nasti_w_bits_user,
+ output io_nasti_b_ready,
+ input io_nasti_b_valid,
+ input [1:0] io_nasti_b_bits_resp,
+ input [4:0] io_nasti_b_bits_id,
+ input io_nasti_b_bits_user,
+ input io_nasti_ar_ready,
+ output io_nasti_ar_valid,
+ output [31:0] io_nasti_ar_bits_addr,
+ output [7:0] io_nasti_ar_bits_len,
+ output [2:0] io_nasti_ar_bits_size,
+ output [1:0] io_nasti_ar_bits_burst,
+ output io_nasti_ar_bits_lock,
+ output [3:0] io_nasti_ar_bits_cache,
+ output [2:0] io_nasti_ar_bits_prot,
+ output [3:0] io_nasti_ar_bits_qos,
+ output [3:0] io_nasti_ar_bits_region,
+ output [4:0] io_nasti_ar_bits_id,
+ output io_nasti_ar_bits_user,
+ output io_nasti_r_ready,
+ input io_nasti_r_valid,
+ input [1:0] io_nasti_r_bits_resp,
+ input [63:0] io_nasti_r_bits_data,
+ input io_nasti_r_bits_last,
+ input [4:0] io_nasti_r_bits_id,
+ input io_nasti_r_bits_user
+);
+ wire [2:0] T_685_0;
+ wire [2:0] T_685_1;
+ wire [2:0] T_685_2;
+ wire T_690;
+ wire T_691;
+ wire T_692;
+ wire T_694;
+ wire T_695;
+ wire T_696;
+ wire has_data;
+ wire [2:0] T_702_0;
+ wire [2:0] T_702_1;
+ wire [2:0] T_702_2;
+ wire T_707;
+ wire T_708;
+ wire T_709;
+ wire T_711;
+ wire T_712;
+ wire T_713;
+ wire is_subblock;
+ wire T_716;
+ wire [2:0] T_719_0;
+ wire T_722;
+ wire T_724;
+ wire is_multibeat;
+ wire T_726;
+ wire T_727;
+ reg [2:0] tl_cnt_out;
+ wire T_731;
+ wire T_733;
+ wire [3:0] T_736;
+ wire [2:0] T_737;
+ wire [2:0] T_738;
+ wire tl_wrap_out;
+ wire T_741;
+ wire get_valid;
+ wire put_valid;
+ wire roq_clk;
+ wire roq_reset;
+ wire roq_io_enq_ready;
+ wire roq_io_enq_valid;
+ wire [2:0] roq_io_enq_bits_data_addr_beat;
+ wire [2:0] roq_io_enq_bits_data_byteOff;
+ wire roq_io_enq_bits_data_subblock;
+ wire [4:0] roq_io_enq_bits_tag;
+ wire roq_io_deq_valid;
+ wire [4:0] roq_io_deq_tag;
+ wire [2:0] roq_io_deq_data_addr_beat;
+ wire [2:0] roq_io_deq_data_byteOff;
+ wire roq_io_deq_data_subblock;
+ wire roq_io_deq_matches;
+ reg w_inflight;
+ wire aw_ready;
+ wire T_772;
+ wire T_774;
+ wire T_775;
+ reg [2:0] nasti_cnt_out;
+ wire T_779;
+ wire T_781;
+ wire [3:0] T_784;
+ wire [2:0] T_785;
+ wire [2:0] T_786;
+ wire nasti_wrap_out;
+ wire T_788;
+ wire [2:0] T_789;
+ wire T_790;
+ wire T_791;
+ wire T_792;
+ wire T_793;
+ wire [2:0] T_794;
+ wire [5:0] T_795;
+ wire [31:0] T_796;
+ wire [2:0] T_797;
+ wire T_806;
+ wire [2:0] T_807;
+ wire T_808;
+ wire [2:0] T_809;
+ wire T_810;
+ wire [2:0] T_811;
+ wire T_812;
+ wire [2:0] T_813;
+ wire T_814;
+ wire [2:0] T_815;
+ wire T_816;
+ wire [2:0] T_817;
+ wire T_818;
+ wire [2:0] T_819;
+ wire [2:0] T_821;
+ wire [2:0] T_824;
+ wire [31:0] T_837_addr;
+ wire [7:0] T_837_len;
+ wire [2:0] T_837_size;
+ wire [1:0] T_837_burst;
+ wire T_837_lock;
+ wire [3:0] T_837_cache;
+ wire [2:0] T_837_prot;
+ wire [3:0] T_837_qos;
+ wire [3:0] T_837_region;
+ wire [4:0] T_837_id;
+ wire T_837_user;
+ wire T_856;
+ wire T_857;
+ wire T_858;
+ wire [2:0] T_859;
+ wire [5:0] T_860;
+ wire [31:0] T_861;
+ wire [2:0] T_865;
+ wire [31:0] T_878_addr;
+ wire [7:0] T_878_len;
+ wire [2:0] T_878_size;
+ wire [1:0] T_878_burst;
+ wire T_878_lock;
+ wire [3:0] T_878_cache;
+ wire [2:0] T_878_prot;
+ wire [3:0] T_878_qos;
+ wire [3:0] T_878_region;
+ wire [4:0] T_878_id;
+ wire T_878_user;
+ wire T_896;
+ wire T_899;
+ wire T_900;
+ wire T_903_0;
+ wire [8:0] T_907;
+ wire [7:0] T_908;
+ wire [7:0] T_910_0;
+ wire T_914;
+ wire T_915;
+ wire T_917;
+ wire T_918;
+ wire T_919;
+ wire [7:0] T_920;
+ wire [7:0] T_922;
+ wire [7:0] T_923;
+ wire T_924;
+ wire T_925;
+ wire T_926;
+ wire [63:0] T_932_data;
+ wire T_932_last;
+ wire [7:0] T_932_strb;
+ wire T_932_user;
+ wire [1:0] T_938;
+ wire [3:0] T_939;
+ wire [7:0] T_940;
+ wire T_942;
+ wire T_943;
+ wire T_944;
+ wire T_946;
+ wire T_947;
+ wire T_948;
+ wire T_949;
+ wire T_952;
+ wire [2:0] T_956_0;
+ wire T_959;
+ wire T_961;
+ wire T_963_0;
+ wire T_966;
+ wire T_968;
+ wire T_969;
+ wire T_970;
+ wire T_971;
+ reg [2:0] tl_cnt_in;
+ wire T_975;
+ wire T_977;
+ wire [3:0] T_980;
+ wire [2:0] T_981;
+ wire [2:0] T_982;
+ wire tl_wrap_in;
+ wire gnt_arb_clk;
+ wire gnt_arb_reset;
+ wire gnt_arb_io_in_0_ready;
+ wire gnt_arb_io_in_0_valid;
+ wire [2:0] gnt_arb_io_in_0_bits_addr_beat;
+ wire [3:0] gnt_arb_io_in_0_bits_client_xact_id;
+ wire gnt_arb_io_in_0_bits_manager_xact_id;
+ wire gnt_arb_io_in_0_bits_is_builtin_type;
+ wire [3:0] gnt_arb_io_in_0_bits_g_type;
+ wire [63:0] gnt_arb_io_in_0_bits_data;
+ wire gnt_arb_io_in_0_bits_client_id;
+ wire gnt_arb_io_in_1_ready;
+ wire gnt_arb_io_in_1_valid;
+ wire [2:0] gnt_arb_io_in_1_bits_addr_beat;
+ wire [3:0] gnt_arb_io_in_1_bits_client_xact_id;
+ wire gnt_arb_io_in_1_bits_manager_xact_id;
+ wire gnt_arb_io_in_1_bits_is_builtin_type;
+ wire [3:0] gnt_arb_io_in_1_bits_g_type;
+ wire [63:0] gnt_arb_io_in_1_bits_data;
+ wire gnt_arb_io_in_1_bits_client_id;
+ wire gnt_arb_io_out_ready;
+ wire gnt_arb_io_out_valid;
+ wire [2:0] gnt_arb_io_out_bits_addr_beat;
+ wire [3:0] gnt_arb_io_out_bits_client_xact_id;
+ wire gnt_arb_io_out_bits_manager_xact_id;
+ wire gnt_arb_io_out_bits_is_builtin_type;
+ wire [3:0] gnt_arb_io_out_bits_g_type;
+ wire [63:0] gnt_arb_io_out_bits_data;
+ wire gnt_arb_io_out_bits_client_id;
+ wire gnt_arb_io_chosen;
+ wire [5:0] T_1014;
+ wire [126:0] T_1015;
+ wire [126:0] r_aligned_data;
+ wire [2:0] T_1020;
+ wire [2:0] T_1022;
+ wire [2:0] T_1050_addr_beat;
+ wire [3:0] T_1050_client_xact_id;
+ wire T_1050_manager_xact_id;
+ wire T_1050_is_builtin_type;
+ wire [3:0] T_1050_g_type;
+ wire [63:0] T_1050_data;
+ wire [2:0] T_1109_addr_beat;
+ wire [3:0] T_1109_client_xact_id;
+ wire T_1109_manager_xact_id;
+ wire T_1109_is_builtin_type;
+ wire [3:0] T_1109_g_type;
+ wire [63:0] T_1109_data;
+ wire T_1137;
+ wire T_1139;
+ wire T_1140;
+ wire T_1142;
+ wire T_1144;
+ wire T_1146;
+ wire T_1148;
+ wire T_1150;
+ wire T_1151;
+ wire T_1153;
+ wire T_1155;
+ wire T_1157;
+ wire GEN_0;
+ wire GEN_1;
+ reg GEN_2;
+ reg GEN_3;
+ ReorderQueue_70 roq (
+ .clk(roq_clk),
+ .reset(roq_reset),
+ .io_enq_ready(roq_io_enq_ready),
+ .io_enq_valid(roq_io_enq_valid),
+ .io_enq_bits_data_addr_beat(roq_io_enq_bits_data_addr_beat),
+ .io_enq_bits_data_byteOff(roq_io_enq_bits_data_byteOff),
+ .io_enq_bits_data_subblock(roq_io_enq_bits_data_subblock),
+ .io_enq_bits_tag(roq_io_enq_bits_tag),
+ .io_deq_valid(roq_io_deq_valid),
+ .io_deq_tag(roq_io_deq_tag),
+ .io_deq_data_addr_beat(roq_io_deq_data_addr_beat),
+ .io_deq_data_byteOff(roq_io_deq_data_byteOff),
+ .io_deq_data_subblock(roq_io_deq_data_subblock),
+ .io_deq_matches(roq_io_deq_matches)
+ );
+ Arbiter gnt_arb (
+ .clk(gnt_arb_clk),
+ .reset(gnt_arb_reset),
+ .io_in_0_ready(gnt_arb_io_in_0_ready),
+ .io_in_0_valid(gnt_arb_io_in_0_valid),
+ .io_in_0_bits_addr_beat(gnt_arb_io_in_0_bits_addr_beat),
+ .io_in_0_bits_client_xact_id(gnt_arb_io_in_0_bits_client_xact_id),
+ .io_in_0_bits_manager_xact_id(gnt_arb_io_in_0_bits_manager_xact_id),
+ .io_in_0_bits_is_builtin_type(gnt_arb_io_in_0_bits_is_builtin_type),
+ .io_in_0_bits_g_type(gnt_arb_io_in_0_bits_g_type),
+ .io_in_0_bits_data(gnt_arb_io_in_0_bits_data),
+ .io_in_0_bits_client_id(gnt_arb_io_in_0_bits_client_id),
+ .io_in_1_ready(gnt_arb_io_in_1_ready),
+ .io_in_1_valid(gnt_arb_io_in_1_valid),
+ .io_in_1_bits_addr_beat(gnt_arb_io_in_1_bits_addr_beat),
+ .io_in_1_bits_client_xact_id(gnt_arb_io_in_1_bits_client_xact_id),
+ .io_in_1_bits_manager_xact_id(gnt_arb_io_in_1_bits_manager_xact_id),
+ .io_in_1_bits_is_builtin_type(gnt_arb_io_in_1_bits_is_builtin_type),
+ .io_in_1_bits_g_type(gnt_arb_io_in_1_bits_g_type),
+ .io_in_1_bits_data(gnt_arb_io_in_1_bits_data),
+ .io_in_1_bits_client_id(gnt_arb_io_in_1_bits_client_id),
+ .io_out_ready(gnt_arb_io_out_ready),
+ .io_out_valid(gnt_arb_io_out_valid),
+ .io_out_bits_addr_beat(gnt_arb_io_out_bits_addr_beat),
+ .io_out_bits_client_xact_id(gnt_arb_io_out_bits_client_xact_id),
+ .io_out_bits_manager_xact_id(gnt_arb_io_out_bits_manager_xact_id),
+ .io_out_bits_is_builtin_type(gnt_arb_io_out_bits_is_builtin_type),
+ .io_out_bits_g_type(gnt_arb_io_out_bits_g_type),
+ .io_out_bits_data(gnt_arb_io_out_bits_data),
+ .io_out_bits_client_id(gnt_arb_io_out_bits_client_id),
+ .io_chosen(gnt_arb_io_chosen)
+ );
+ assign io_tl_acquire_ready = T_944;
+ assign io_tl_grant_valid = gnt_arb_io_out_valid;
+ assign io_tl_grant_bits_addr_beat = gnt_arb_io_out_bits_addr_beat;
+ assign io_tl_grant_bits_client_xact_id = gnt_arb_io_out_bits_client_xact_id;
+ assign io_tl_grant_bits_manager_xact_id = gnt_arb_io_out_bits_manager_xact_id;
+ assign io_tl_grant_bits_is_builtin_type = gnt_arb_io_out_bits_is_builtin_type;
+ assign io_tl_grant_bits_g_type = gnt_arb_io_out_bits_g_type;
+ assign io_tl_grant_bits_data = gnt_arb_io_out_bits_data;
+ assign io_nasti_aw_valid = T_858;
+ assign io_nasti_aw_bits_addr = T_878_addr;
+ assign io_nasti_aw_bits_len = T_878_len;
+ assign io_nasti_aw_bits_size = T_878_size;
+ assign io_nasti_aw_bits_burst = T_878_burst;
+ assign io_nasti_aw_bits_lock = T_878_lock;
+ assign io_nasti_aw_bits_cache = T_878_cache;
+ assign io_nasti_aw_bits_prot = T_878_prot;
+ assign io_nasti_aw_bits_qos = T_878_qos;
+ assign io_nasti_aw_bits_region = T_878_region;
+ assign io_nasti_aw_bits_id = T_878_id;
+ assign io_nasti_aw_bits_user = T_878_user;
+ assign io_nasti_w_valid = T_896;
+ assign io_nasti_w_bits_data = T_932_data;
+ assign io_nasti_w_bits_last = T_932_last;
+ assign io_nasti_w_bits_strb = T_932_strb;
+ assign io_nasti_w_bits_user = T_932_user;
+ assign io_nasti_b_ready = gnt_arb_io_in_1_ready;
+ assign io_nasti_ar_valid = T_793;
+ assign io_nasti_ar_bits_addr = T_837_addr;
+ assign io_nasti_ar_bits_len = T_837_len;
+ assign io_nasti_ar_bits_size = T_837_size;
+ assign io_nasti_ar_bits_burst = T_837_burst;
+ assign io_nasti_ar_bits_lock = T_837_lock;
+ assign io_nasti_ar_bits_cache = T_837_cache;
+ assign io_nasti_ar_bits_prot = T_837_prot;
+ assign io_nasti_ar_bits_qos = T_837_qos;
+ assign io_nasti_ar_bits_region = T_837_region;
+ assign io_nasti_ar_bits_id = T_837_id;
+ assign io_nasti_ar_bits_user = T_837_user;
+ assign io_nasti_r_ready = gnt_arb_io_in_0_ready;
+ assign T_685_0 = 3'h2;
+ assign T_685_1 = 3'h3;
+ assign T_685_2 = 3'h4;
+ assign T_690 = T_685_0 == io_tl_acquire_bits_a_type;
+ assign T_691 = T_685_1 == io_tl_acquire_bits_a_type;
+ assign T_692 = T_685_2 == io_tl_acquire_bits_a_type;
+ assign T_694 = 1'h0 | T_690;
+ assign T_695 = T_694 | T_691;
+ assign T_696 = T_695 | T_692;
+ assign has_data = io_tl_acquire_bits_is_builtin_type & T_696;
+ assign T_702_0 = 3'h2;
+ assign T_702_1 = 3'h0;
+ assign T_702_2 = 3'h4;
+ assign T_707 = T_702_0 == io_tl_acquire_bits_a_type;
+ assign T_708 = T_702_1 == io_tl_acquire_bits_a_type;
+ assign T_709 = T_702_2 == io_tl_acquire_bits_a_type;
+ assign T_711 = 1'h0 | T_707;
+ assign T_712 = T_711 | T_708;
+ assign T_713 = T_712 | T_709;
+ assign is_subblock = io_tl_acquire_bits_is_builtin_type & T_713;
+ assign T_716 = 1'h1 & io_tl_acquire_bits_is_builtin_type;
+ assign T_719_0 = 3'h3;
+ assign T_722 = T_719_0 == io_tl_acquire_bits_a_type;
+ assign T_724 = 1'h0 | T_722;
+ assign is_multibeat = T_716 & T_724;
+ assign T_726 = io_tl_acquire_ready & io_tl_acquire_valid;
+ assign T_727 = T_726 & is_multibeat;
+ assign T_731 = tl_cnt_out == 3'h7;
+ assign T_733 = 1'h0 & T_731;
+ assign T_736 = tl_cnt_out + 1'h1;
+ assign T_737 = T_736[2:0];
+ assign T_738 = T_733 ? 1'h0 : T_737;
+ assign tl_wrap_out = T_727 & T_731;
+ assign T_741 = has_data == 1'h0;
+ assign get_valid = io_tl_acquire_valid & T_741;
+ assign put_valid = io_tl_acquire_valid & has_data;
+ assign roq_clk = clk;
+ assign roq_reset = reset;
+ assign roq_io_enq_valid = T_788;
+ assign roq_io_enq_bits_data_addr_beat = io_tl_acquire_bits_addr_beat;
+ assign roq_io_enq_bits_data_byteOff = T_789;
+ assign roq_io_enq_bits_data_subblock = is_subblock;
+ assign roq_io_enq_bits_tag = io_nasti_ar_bits_id;
+ assign roq_io_deq_valid = T_792;
+ assign roq_io_deq_tag = io_nasti_r_bits_id;
+ assign aw_ready = w_inflight | io_nasti_aw_ready;
+ assign T_772 = io_nasti_r_ready & io_nasti_r_valid;
+ assign T_774 = roq_io_deq_data_subblock == 1'h0;
+ assign T_775 = T_772 & T_774;
+ assign T_779 = nasti_cnt_out == 3'h7;
+ assign T_781 = 1'h0 & T_779;
+ assign T_784 = nasti_cnt_out + 1'h1;
+ assign T_785 = T_784[2:0];
+ assign T_786 = T_781 ? 1'h0 : T_785;
+ assign nasti_wrap_out = T_775 & T_779;
+ assign T_788 = get_valid & io_nasti_ar_ready;
+ assign T_789 = io_tl_acquire_bits_union[11:9];
+ assign T_790 = io_nasti_r_ready & io_nasti_r_valid;
+ assign T_791 = nasti_wrap_out | roq_io_deq_data_subblock;
+ assign T_792 = T_790 & T_791;
+ assign T_793 = get_valid & roq_io_enq_ready;
+ assign T_794 = io_tl_acquire_bits_union[11:9];
+ assign T_795 = {io_tl_acquire_bits_addr_beat,T_794};
+ assign T_796 = {io_tl_acquire_bits_addr_block,T_795};
+ assign T_797 = io_tl_acquire_bits_union[8:6];
+ assign T_806 = 3'h7 == T_797;
+ assign T_807 = T_806 ? 2'h3 : 3'h7;
+ assign T_808 = 3'h3 == T_797;
+ assign T_809 = T_808 ? 2'h3 : T_807;
+ assign T_810 = 3'h2 == T_797;
+ assign T_811 = T_810 ? 2'h2 : T_809;
+ assign T_812 = 3'h5 == T_797;
+ assign T_813 = T_812 ? 1'h1 : T_811;
+ assign T_814 = 3'h1 == T_797;
+ assign T_815 = T_814 ? 1'h1 : T_813;
+ assign T_816 = 3'h4 == T_797;
+ assign T_817 = T_816 ? 1'h0 : T_815;
+ assign T_818 = 3'h0 == T_797;
+ assign T_819 = T_818 ? 1'h0 : T_817;
+ assign T_821 = is_subblock ? T_819 : 2'h3;
+ assign T_824 = is_subblock ? 1'h0 : 3'h7;
+ assign T_837_addr = T_796;
+ assign T_837_len = T_824;
+ assign T_837_size = T_821;
+ assign T_837_burst = 2'h1;
+ assign T_837_lock = 1'h0;
+ assign T_837_cache = 1'h0;
+ assign T_837_prot = 1'h0;
+ assign T_837_qos = 1'h0;
+ assign T_837_region = 1'h0;
+ assign T_837_id = io_tl_acquire_bits_client_xact_id;
+ assign T_837_user = 1'h0;
+ assign T_856 = w_inflight == 1'h0;
+ assign T_857 = put_valid & io_nasti_w_ready;
+ assign T_858 = T_857 & T_856;
+ assign T_859 = io_tl_acquire_bits_union[11:9];
+ assign T_860 = {io_tl_acquire_bits_addr_beat,T_859};
+ assign T_861 = {io_tl_acquire_bits_addr_block,T_860};
+ assign T_865 = is_multibeat ? 3'h7 : 1'h0;
+ assign T_878_addr = T_861;
+ assign T_878_len = T_865;
+ assign T_878_size = 2'h3;
+ assign T_878_burst = 2'h1;
+ assign T_878_lock = 1'h0;
+ assign T_878_cache = 4'h0;
+ assign T_878_prot = 3'h0;
+ assign T_878_qos = 4'h0;
+ assign T_878_region = 4'h0;
+ assign T_878_id = io_tl_acquire_bits_client_xact_id;
+ assign T_878_user = 1'h0;
+ assign T_896 = put_valid & aw_ready;
+ assign T_899 = io_tl_acquire_bits_a_type == 3'h4;
+ assign T_900 = io_tl_acquire_bits_is_builtin_type & T_899;
+ assign T_903_0 = 1'h1;
+ assign T_907 = 8'h0 - T_903_0;
+ assign T_908 = T_907[7:0];
+ assign T_910_0 = T_908;
+ assign T_914 = io_tl_acquire_bits_a_type == 3'h3;
+ assign T_915 = io_tl_acquire_bits_is_builtin_type & T_914;
+ assign T_917 = io_tl_acquire_bits_a_type == 3'h2;
+ assign T_918 = io_tl_acquire_bits_is_builtin_type & T_917;
+ assign T_919 = T_915 | T_918;
+ assign T_920 = io_tl_acquire_bits_union[8:1];
+ assign T_922 = T_919 ? T_920 : 8'h0;
+ assign T_923 = T_900 ? T_910_0 : T_922;
+ assign T_924 = io_tl_acquire_ready & io_tl_acquire_valid;
+ assign T_925 = T_924 & is_subblock;
+ assign T_926 = tl_wrap_out | T_925;
+ assign T_932_data = io_tl_acquire_bits_data;
+ assign T_932_last = T_926;
+ assign T_932_strb = T_923;
+ assign T_932_user = 1'h0;
+ assign T_938 = {1'h1,1'h1};
+ assign T_939 = {T_938,T_938};
+ assign T_940 = {T_939,T_939};
+ assign T_942 = aw_ready & io_nasti_w_ready;
+ assign T_943 = roq_io_enq_ready & io_nasti_ar_ready;
+ assign T_944 = has_data ? T_942 : T_943;
+ assign T_946 = w_inflight == 1'h0;
+ assign T_947 = io_tl_acquire_ready & io_tl_acquire_valid;
+ assign T_948 = T_946 & T_947;
+ assign T_949 = T_948 & is_multibeat;
+ assign T_952 = io_tl_grant_ready & io_tl_grant_valid;
+ assign T_956_0 = 3'h5;
+ assign T_959 = T_956_0 == io_tl_grant_bits_g_type;
+ assign T_961 = 1'h0 | T_959;
+ assign T_963_0 = 1'h0;
+ assign T_966 = T_963_0 == io_tl_grant_bits_g_type;
+ assign T_968 = 1'h0 | T_966;
+ assign T_969 = io_tl_grant_bits_is_builtin_type ? T_961 : T_968;
+ assign T_970 = 1'h1 & T_969;
+ assign T_971 = T_952 & T_970;
+ assign T_975 = tl_cnt_in == 3'h7;
+ assign T_977 = 1'h0 & T_975;
+ assign T_980 = tl_cnt_in + 1'h1;
+ assign T_981 = T_980[2:0];
+ assign T_982 = T_977 ? 1'h0 : T_981;
+ assign tl_wrap_in = T_971 & T_975;
+ assign gnt_arb_clk = clk;
+ assign gnt_arb_reset = reset;
+ assign gnt_arb_io_in_0_valid = io_nasti_r_valid;
+ assign gnt_arb_io_in_0_bits_addr_beat = T_1050_addr_beat;
+ assign gnt_arb_io_in_0_bits_client_xact_id = T_1050_client_xact_id;
+ assign gnt_arb_io_in_0_bits_manager_xact_id = T_1050_manager_xact_id;
+ assign gnt_arb_io_in_0_bits_is_builtin_type = T_1050_is_builtin_type;
+ assign gnt_arb_io_in_0_bits_g_type = T_1050_g_type;
+ assign gnt_arb_io_in_0_bits_data = T_1050_data;
+ assign gnt_arb_io_in_0_bits_client_id = GEN_2;
+ assign gnt_arb_io_in_1_valid = io_nasti_b_valid;
+ assign gnt_arb_io_in_1_bits_addr_beat = T_1109_addr_beat;
+ assign gnt_arb_io_in_1_bits_client_xact_id = T_1109_client_xact_id;
+ assign gnt_arb_io_in_1_bits_manager_xact_id = T_1109_manager_xact_id;
+ assign gnt_arb_io_in_1_bits_is_builtin_type = T_1109_is_builtin_type;
+ assign gnt_arb_io_in_1_bits_g_type = T_1109_g_type;
+ assign gnt_arb_io_in_1_bits_data = T_1109_data;
+ assign gnt_arb_io_in_1_bits_client_id = GEN_3;
+ assign gnt_arb_io_out_ready = io_tl_grant_ready;
+ assign T_1014 = {roq_io_deq_data_byteOff,3'h0};
+ assign T_1015 = io_nasti_r_bits_data << T_1014;
+ assign r_aligned_data = roq_io_deq_data_subblock ? T_1015 : io_nasti_r_bits_data;
+ assign T_1020 = roq_io_deq_data_subblock ? 3'h4 : 3'h5;
+ assign T_1022 = roq_io_deq_data_subblock ? roq_io_deq_data_addr_beat : tl_cnt_in;
+ assign T_1050_addr_beat = T_1022;
+ assign T_1050_client_xact_id = io_nasti_r_bits_id;
+ assign T_1050_manager_xact_id = 1'h0;
+ assign T_1050_is_builtin_type = 1'h1;
+ assign T_1050_g_type = T_1020;
+ assign T_1050_data = r_aligned_data;
+ assign T_1109_addr_beat = 1'h0;
+ assign T_1109_client_xact_id = io_nasti_b_bits_id;
+ assign T_1109_manager_xact_id = 1'h0;
+ assign T_1109_is_builtin_type = 1'h1;
+ assign T_1109_g_type = 3'h3;
+ assign T_1109_data = 1'h0;
+ assign T_1137 = io_nasti_r_valid == 1'h0;
+ assign T_1139 = io_nasti_r_bits_resp == 1'h0;
+ assign T_1140 = T_1137 | T_1139;
+ assign T_1142 = reset == 1'h0;
+ assign T_1144 = T_1140 == 1'h0;
+ assign T_1146 = reset == 1'h0;
+ assign T_1148 = io_nasti_b_valid == 1'h0;
+ assign T_1150 = io_nasti_b_bits_resp == 1'h0;
+ assign T_1151 = T_1148 | T_1150;
+ assign T_1153 = reset == 1'h0;
+ assign T_1155 = T_1151 == 1'h0;
+ assign T_1157 = reset == 1'h0;
+ assign GEN_0 = T_1142 & T_1144;
+ assign GEN_1 = T_1153 & T_1155;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ tl_cnt_out = {1{$random}};
+ w_inflight = {1{$random}};
+ nasti_cnt_out = {1{$random}};
+ tl_cnt_in = {1{$random}};
+ GEN_2 = {1{$random}};
+ GEN_3 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ tl_cnt_out <= 3'h0;
+ end else begin
+ if(T_727) begin
+ tl_cnt_out <= T_738;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ w_inflight <= 1'h0;
+ end else begin
+ if(w_inflight) begin
+ if(tl_wrap_out) begin
+ w_inflight <= 1'h0;
+ end else begin
+ if(T_949) begin
+ w_inflight <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_949) begin
+ w_inflight <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ nasti_cnt_out <= 3'h0;
+ end else begin
+ if(T_775) begin
+ nasti_cnt_out <= T_786;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ tl_cnt_in <= 3'h0;
+ end else begin
+ if(T_971) begin
+ tl_cnt_in <= T_982;
+ end else begin
+ ;
+ end
+ end
+ `ifndef SYNTHESIS
+ if(GEN_0 & T_1146) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): NASTI read error");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_1142 & T_1144) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_1 & T_1157) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): NASTI write error");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_1153 & T_1155) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ end
+endmodule
+module ClientTileLinkIOWrapper_71(
+ input clk,
+ input reset,
+ output io_in_acquire_ready,
+ input io_in_acquire_valid,
+ input [25:0] io_in_acquire_bits_addr_block,
+ input [3:0] io_in_acquire_bits_client_xact_id,
+ input [1:0] io_in_acquire_bits_addr_beat,
+ input io_in_acquire_bits_is_builtin_type,
+ input [2:0] io_in_acquire_bits_a_type,
+ input [16:0] io_in_acquire_bits_union,
+ input [127:0] io_in_acquire_bits_data,
+ input io_in_grant_ready,
+ output io_in_grant_valid,
+ output [1:0] io_in_grant_bits_addr_beat,
+ output [3:0] io_in_grant_bits_client_xact_id,
+ output io_in_grant_bits_manager_xact_id,
+ output io_in_grant_bits_is_builtin_type,
+ output [3:0] io_in_grant_bits_g_type,
+ output [127:0] io_in_grant_bits_data,
+ input io_out_acquire_ready,
+ output io_out_acquire_valid,
+ output [25:0] io_out_acquire_bits_addr_block,
+ output [3:0] io_out_acquire_bits_client_xact_id,
+ output [1:0] io_out_acquire_bits_addr_beat,
+ output io_out_acquire_bits_is_builtin_type,
+ output [2:0] io_out_acquire_bits_a_type,
+ output [16:0] io_out_acquire_bits_union,
+ output [127:0] io_out_acquire_bits_data,
+ output io_out_grant_ready,
+ input io_out_grant_valid,
+ input [1:0] io_out_grant_bits_addr_beat,
+ input [3:0] io_out_grant_bits_client_xact_id,
+ input io_out_grant_bits_manager_xact_id,
+ input io_out_grant_bits_is_builtin_type,
+ input [3:0] io_out_grant_bits_g_type,
+ input [127:0] io_out_grant_bits_data,
+ output io_out_probe_ready,
+ input io_out_probe_valid,
+ input [25:0] io_out_probe_bits_addr_block,
+ input [1:0] io_out_probe_bits_p_type,
+ input io_out_release_ready,
+ output io_out_release_valid,
+ output [1:0] io_out_release_bits_addr_beat,
+ output [25:0] io_out_release_bits_addr_block,
+ output [3:0] io_out_release_bits_client_xact_id,
+ output io_out_release_bits_voluntary,
+ output [2:0] io_out_release_bits_r_type,
+ output [127:0] io_out_release_bits_data
+);
+ reg [1:0] GEN_0;
+ reg [25:0] GEN_1;
+ reg [3:0] GEN_2;
+ reg GEN_3;
+ reg [2:0] GEN_4;
+ reg [127:0] GEN_5;
+ assign io_in_acquire_ready = io_out_acquire_ready;
+ assign io_in_grant_valid = io_out_grant_valid;
+ assign io_in_grant_bits_addr_beat = io_out_grant_bits_addr_beat;
+ assign io_in_grant_bits_client_xact_id = io_out_grant_bits_client_xact_id;
+ assign io_in_grant_bits_manager_xact_id = io_out_grant_bits_manager_xact_id;
+ assign io_in_grant_bits_is_builtin_type = io_out_grant_bits_is_builtin_type;
+ assign io_in_grant_bits_g_type = io_out_grant_bits_g_type;
+ assign io_in_grant_bits_data = io_out_grant_bits_data;
+ assign io_out_acquire_valid = io_in_acquire_valid;
+ assign io_out_acquire_bits_addr_block = io_in_acquire_bits_addr_block;
+ assign io_out_acquire_bits_client_xact_id = io_in_acquire_bits_client_xact_id;
+ assign io_out_acquire_bits_addr_beat = io_in_acquire_bits_addr_beat;
+ assign io_out_acquire_bits_is_builtin_type = io_in_acquire_bits_is_builtin_type;
+ assign io_out_acquire_bits_a_type = io_in_acquire_bits_a_type;
+ assign io_out_acquire_bits_union = io_in_acquire_bits_union;
+ assign io_out_acquire_bits_data = io_in_acquire_bits_data;
+ assign io_out_grant_ready = io_in_grant_ready;
+ assign io_out_probe_ready = 1'h1;
+ assign io_out_release_valid = 1'h0;
+ assign io_out_release_bits_addr_beat = GEN_0;
+ assign io_out_release_bits_addr_block = GEN_1;
+ assign io_out_release_bits_client_xact_id = GEN_2;
+ assign io_out_release_bits_voluntary = GEN_3;
+ assign io_out_release_bits_r_type = GEN_4;
+ assign io_out_release_bits_data = GEN_5;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ GEN_0 = {1{$random}};
+ GEN_1 = {1{$random}};
+ GEN_2 = {1{$random}};
+ GEN_3 = {1{$random}};
+ GEN_4 = {1{$random}};
+ GEN_5 = {4{$random}};
+ end
+`endif
+endmodule
+module ClientTileLinkEnqueuer(
+ input clk,
+ input reset,
+ output io_inner_acquire_ready,
+ input io_inner_acquire_valid,
+ input [25:0] io_inner_acquire_bits_addr_block,
+ input [3:0] io_inner_acquire_bits_client_xact_id,
+ input [1:0] io_inner_acquire_bits_addr_beat,
+ input io_inner_acquire_bits_is_builtin_type,
+ input [2:0] io_inner_acquire_bits_a_type,
+ input [16:0] io_inner_acquire_bits_union,
+ input [127:0] io_inner_acquire_bits_data,
+ input io_inner_grant_ready,
+ output io_inner_grant_valid,
+ output [1:0] io_inner_grant_bits_addr_beat,
+ output [3:0] io_inner_grant_bits_client_xact_id,
+ output io_inner_grant_bits_manager_xact_id,
+ output io_inner_grant_bits_is_builtin_type,
+ output [3:0] io_inner_grant_bits_g_type,
+ output [127:0] io_inner_grant_bits_data,
+ input io_inner_probe_ready,
+ output io_inner_probe_valid,
+ output [25:0] io_inner_probe_bits_addr_block,
+ output [1:0] io_inner_probe_bits_p_type,
+ output io_inner_release_ready,
+ input io_inner_release_valid,
+ input [1:0] io_inner_release_bits_addr_beat,
+ input [25:0] io_inner_release_bits_addr_block,
+ input [3:0] io_inner_release_bits_client_xact_id,
+ input io_inner_release_bits_voluntary,
+ input [2:0] io_inner_release_bits_r_type,
+ input [127:0] io_inner_release_bits_data,
+ input io_outer_acquire_ready,
+ output io_outer_acquire_valid,
+ output [25:0] io_outer_acquire_bits_addr_block,
+ output [3:0] io_outer_acquire_bits_client_xact_id,
+ output [1:0] io_outer_acquire_bits_addr_beat,
+ output io_outer_acquire_bits_is_builtin_type,
+ output [2:0] io_outer_acquire_bits_a_type,
+ output [16:0] io_outer_acquire_bits_union,
+ output [127:0] io_outer_acquire_bits_data,
+ output io_outer_grant_ready,
+ input io_outer_grant_valid,
+ input [1:0] io_outer_grant_bits_addr_beat,
+ input [3:0] io_outer_grant_bits_client_xact_id,
+ input io_outer_grant_bits_manager_xact_id,
+ input io_outer_grant_bits_is_builtin_type,
+ input [3:0] io_outer_grant_bits_g_type,
+ input [127:0] io_outer_grant_bits_data,
+ output io_outer_probe_ready,
+ input io_outer_probe_valid,
+ input [25:0] io_outer_probe_bits_addr_block,
+ input [1:0] io_outer_probe_bits_p_type,
+ input io_outer_release_ready,
+ output io_outer_release_valid,
+ output [1:0] io_outer_release_bits_addr_beat,
+ output [25:0] io_outer_release_bits_addr_block,
+ output [3:0] io_outer_release_bits_client_xact_id,
+ output io_outer_release_bits_voluntary,
+ output [2:0] io_outer_release_bits_r_type,
+ output [127:0] io_outer_release_bits_data
+);
+ assign io_inner_acquire_ready = io_outer_acquire_ready;
+ assign io_inner_grant_valid = io_outer_grant_valid;
+ assign io_inner_grant_bits_addr_beat = io_outer_grant_bits_addr_beat;
+ assign io_inner_grant_bits_client_xact_id = io_outer_grant_bits_client_xact_id;
+ assign io_inner_grant_bits_manager_xact_id = io_outer_grant_bits_manager_xact_id;
+ assign io_inner_grant_bits_is_builtin_type = io_outer_grant_bits_is_builtin_type;
+ assign io_inner_grant_bits_g_type = io_outer_grant_bits_g_type;
+ assign io_inner_grant_bits_data = io_outer_grant_bits_data;
+ assign io_inner_probe_valid = io_outer_probe_valid;
+ assign io_inner_probe_bits_addr_block = io_outer_probe_bits_addr_block;
+ assign io_inner_probe_bits_p_type = io_outer_probe_bits_p_type;
+ assign io_inner_release_ready = io_outer_release_ready;
+ assign io_outer_acquire_valid = io_inner_acquire_valid;
+ assign io_outer_acquire_bits_addr_block = io_inner_acquire_bits_addr_block;
+ assign io_outer_acquire_bits_client_xact_id = io_inner_acquire_bits_client_xact_id;
+ assign io_outer_acquire_bits_addr_beat = io_inner_acquire_bits_addr_beat;
+ assign io_outer_acquire_bits_is_builtin_type = io_inner_acquire_bits_is_builtin_type;
+ assign io_outer_acquire_bits_a_type = io_inner_acquire_bits_a_type;
+ assign io_outer_acquire_bits_union = io_inner_acquire_bits_union;
+ assign io_outer_acquire_bits_data = io_inner_acquire_bits_data;
+ assign io_outer_grant_ready = io_inner_grant_ready;
+ assign io_outer_probe_ready = io_inner_probe_ready;
+ assign io_outer_release_valid = io_inner_release_valid;
+ assign io_outer_release_bits_addr_beat = io_inner_release_bits_addr_beat;
+ assign io_outer_release_bits_addr_block = io_inner_release_bits_addr_block;
+ assign io_outer_release_bits_client_xact_id = io_inner_release_bits_client_xact_id;
+ assign io_outer_release_bits_voluntary = io_inner_release_bits_voluntary;
+ assign io_outer_release_bits_r_type = io_inner_release_bits_r_type;
+ assign io_outer_release_bits_data = io_inner_release_bits_data;
+endmodule
+module Queue_74(
+ input clk,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [63:0] io_enq_bits_data,
+ input io_enq_bits_last,
+ input [7:0] io_enq_bits_strb,
+ input io_enq_bits_user,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [63:0] io_deq_bits_data,
+ output io_deq_bits_last,
+ output [7:0] io_deq_bits_strb,
+ output io_deq_bits_user,
+ output [3:0] io_count
+);
+ reg [63:0] ram_data [0:7];
+ wire [63:0] ram_data_T_117_data;
+ wire [2:0] ram_data_T_117_addr;
+ wire ram_data_T_117_en;
+ wire ram_data_T_117_clk;
+ wire [63:0] ram_data_T_83_data;
+ wire [2:0] ram_data_T_83_addr;
+ wire ram_data_T_83_mask;
+ wire ram_data_T_83_en;
+ wire ram_data_T_83_clk;
+ reg ram_last [0:7];
+ wire ram_last_T_117_data;
+ wire [2:0] ram_last_T_117_addr;
+ wire ram_last_T_117_en;
+ wire ram_last_T_117_clk;
+ wire ram_last_T_83_data;
+ wire [2:0] ram_last_T_83_addr;
+ wire ram_last_T_83_mask;
+ wire ram_last_T_83_en;
+ wire ram_last_T_83_clk;
+ reg [7:0] ram_strb [0:7];
+ wire [7:0] ram_strb_T_117_data;
+ wire [2:0] ram_strb_T_117_addr;
+ wire ram_strb_T_117_en;
+ wire ram_strb_T_117_clk;
+ wire [7:0] ram_strb_T_83_data;
+ wire [2:0] ram_strb_T_83_addr;
+ wire ram_strb_T_83_mask;
+ wire ram_strb_T_83_en;
+ wire ram_strb_T_83_clk;
+ reg ram_user [0:7];
+ wire ram_user_T_117_data;
+ wire [2:0] ram_user_T_117_addr;
+ wire ram_user_T_117_en;
+ wire ram_user_T_117_clk;
+ wire ram_user_T_83_data;
+ wire [2:0] ram_user_T_83_addr;
+ wire ram_user_T_83_mask;
+ wire ram_user_T_83_en;
+ wire ram_user_T_83_clk;
+ reg [2:0] T_62;
+ reg [2:0] T_64;
+ reg maybe_full;
+ wire ptr_match;
+ wire T_69;
+ wire empty;
+ wire full;
+ wire maybe_flow;
+ wire do_flow;
+ wire T_75;
+ wire T_77;
+ wire do_enq;
+ wire T_79;
+ wire T_81;
+ wire do_deq;
+ wire T_89;
+ wire T_91;
+ wire [3:0] T_94;
+ wire [2:0] T_95;
+ wire [2:0] T_96;
+ wire T_98;
+ wire T_100;
+ wire [3:0] T_103;
+ wire [2:0] T_104;
+ wire [2:0] T_105;
+ wire T_106;
+ wire T_108;
+ wire T_110;
+ wire T_111;
+ wire T_113;
+ wire T_115;
+ wire T_116;
+ wire [63:0] T_122_data;
+ wire T_122_last;
+ wire [7:0] T_122_strb;
+ wire T_122_user;
+ wire [3:0] T_127;
+ wire [2:0] ptr_diff;
+ wire T_129;
+ wire [3:0] T_130;
+ assign io_enq_ready = T_116;
+ assign io_deq_valid = T_111;
+ assign io_deq_bits_data = T_122_data;
+ assign io_deq_bits_last = T_122_last;
+ assign io_deq_bits_strb = T_122_strb;
+ assign io_deq_bits_user = T_122_user;
+ assign io_count = T_130;
+ assign ram_data_T_117_addr = T_64;
+ assign ram_data_T_117_en = 1'h1;
+ assign ram_data_T_117_clk = clk;
+ assign ram_data_T_117_data = ram_data[ram_data_T_117_addr];
+ assign ram_data_T_83_data = io_enq_bits_data;
+ assign ram_data_T_83_addr = T_62;
+ assign ram_data_T_83_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_data_T_83_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_data_T_83_clk = clk;
+ assign ram_last_T_117_addr = T_64;
+ assign ram_last_T_117_en = 1'h1;
+ assign ram_last_T_117_clk = clk;
+ assign ram_last_T_117_data = ram_last[ram_last_T_117_addr];
+ assign ram_last_T_83_data = io_enq_bits_last;
+ assign ram_last_T_83_addr = T_62;
+ assign ram_last_T_83_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_last_T_83_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_last_T_83_clk = clk;
+ assign ram_strb_T_117_addr = T_64;
+ assign ram_strb_T_117_en = 1'h1;
+ assign ram_strb_T_117_clk = clk;
+ assign ram_strb_T_117_data = ram_strb[ram_strb_T_117_addr];
+ assign ram_strb_T_83_data = io_enq_bits_strb;
+ assign ram_strb_T_83_addr = T_62;
+ assign ram_strb_T_83_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_strb_T_83_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_strb_T_83_clk = clk;
+ assign ram_user_T_117_addr = T_64;
+ assign ram_user_T_117_en = 1'h1;
+ assign ram_user_T_117_clk = clk;
+ assign ram_user_T_117_data = ram_user[ram_user_T_117_addr];
+ assign ram_user_T_83_data = io_enq_bits_user;
+ assign ram_user_T_83_addr = T_62;
+ assign ram_user_T_83_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_user_T_83_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_user_T_83_clk = clk;
+ assign ptr_match = T_62 == T_64;
+ assign T_69 = maybe_full == 1'h0;
+ assign empty = ptr_match & T_69;
+ assign full = ptr_match & maybe_full;
+ assign maybe_flow = 1'h0 & empty;
+ assign do_flow = maybe_flow & io_deq_ready;
+ assign T_75 = io_enq_ready & io_enq_valid;
+ assign T_77 = do_flow == 1'h0;
+ assign do_enq = T_75 & T_77;
+ assign T_79 = io_deq_ready & io_deq_valid;
+ assign T_81 = do_flow == 1'h0;
+ assign do_deq = T_79 & T_81;
+ assign T_89 = T_62 == 3'h7;
+ assign T_91 = 1'h0 & T_89;
+ assign T_94 = T_62 + 1'h1;
+ assign T_95 = T_94[2:0];
+ assign T_96 = T_91 ? 1'h0 : T_95;
+ assign T_98 = T_64 == 3'h7;
+ assign T_100 = 1'h0 & T_98;
+ assign T_103 = T_64 + 1'h1;
+ assign T_104 = T_103[2:0];
+ assign T_105 = T_100 ? 1'h0 : T_104;
+ assign T_106 = do_enq != do_deq;
+ assign T_108 = empty == 1'h0;
+ assign T_110 = 1'h0 & io_enq_valid;
+ assign T_111 = T_108 | T_110;
+ assign T_113 = full == 1'h0;
+ assign T_115 = 1'h0 & io_deq_ready;
+ assign T_116 = T_113 | T_115;
+ assign T_122_data = maybe_flow ? io_enq_bits_data : ram_data_T_117_data;
+ assign T_122_last = maybe_flow ? io_enq_bits_last : ram_last_T_117_data;
+ assign T_122_strb = maybe_flow ? io_enq_bits_strb : ram_strb_T_117_data;
+ assign T_122_user = maybe_flow ? io_enq_bits_user : ram_user_T_117_data;
+ assign T_127 = T_62 - T_64;
+ assign ptr_diff = T_127[2:0];
+ assign T_129 = maybe_full & ptr_match;
+ assign T_130 = {T_129,ptr_diff};
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ for (initvar = 0; initvar < 8; initvar = initvar+1)
+ ram_data[initvar] = {2{$random}};
+ for (initvar = 0; initvar < 8; initvar = initvar+1)
+ ram_last[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 8; initvar = initvar+1)
+ ram_strb[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 8; initvar = initvar+1)
+ ram_user[initvar] = {1{$random}};
+ T_62 = {1{$random}};
+ T_64 = {1{$random}};
+ maybe_full = {1{$random}};
+ end
+`endif
+ always @(posedge ram_data_T_83_clk) begin
+ if(ram_data_T_83_en & ram_data_T_83_mask) begin
+ ram_data[ram_data_T_83_addr] <= ram_data_T_83_data;
+ end
+ end
+ always @(posedge ram_last_T_83_clk) begin
+ if(ram_last_T_83_en & ram_last_T_83_mask) begin
+ ram_last[ram_last_T_83_addr] <= ram_last_T_83_data;
+ end
+ end
+ always @(posedge ram_strb_T_83_clk) begin
+ if(ram_strb_T_83_en & ram_strb_T_83_mask) begin
+ ram_strb[ram_strb_T_83_addr] <= ram_strb_T_83_data;
+ end
+ end
+ always @(posedge ram_user_T_83_clk) begin
+ if(ram_user_T_83_en & ram_user_T_83_mask) begin
+ ram_user[ram_user_T_83_addr] <= ram_user_T_83_data;
+ end
+ end
+ always @(posedge clk) begin
+ if(reset) begin
+ T_62 <= 3'h0;
+ end else begin
+ if(do_enq) begin
+ T_62 <= T_96;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_64 <= 3'h0;
+ end else begin
+ if(do_deq) begin
+ T_64 <= T_105;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ maybe_full <= 1'h0;
+ end else begin
+ if(T_106) begin
+ maybe_full <= do_enq;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module Queue_75(
+ input clk,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [1:0] io_enq_bits_resp,
+ input [63:0] io_enq_bits_data,
+ input io_enq_bits_last,
+ input [4:0] io_enq_bits_id,
+ input io_enq_bits_user,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [1:0] io_deq_bits_resp,
+ output [63:0] io_deq_bits_data,
+ output io_deq_bits_last,
+ output [4:0] io_deq_bits_id,
+ output io_deq_bits_user,
+ output [3:0] io_count
+);
+ reg [1:0] ram_resp [0:7];
+ wire [1:0] ram_resp_T_127_data;
+ wire [2:0] ram_resp_T_127_addr;
+ wire ram_resp_T_127_en;
+ wire ram_resp_T_127_clk;
+ wire [1:0] ram_resp_T_92_data;
+ wire [2:0] ram_resp_T_92_addr;
+ wire ram_resp_T_92_mask;
+ wire ram_resp_T_92_en;
+ wire ram_resp_T_92_clk;
+ reg [63:0] ram_data [0:7];
+ wire [63:0] ram_data_T_127_data;
+ wire [2:0] ram_data_T_127_addr;
+ wire ram_data_T_127_en;
+ wire ram_data_T_127_clk;
+ wire [63:0] ram_data_T_92_data;
+ wire [2:0] ram_data_T_92_addr;
+ wire ram_data_T_92_mask;
+ wire ram_data_T_92_en;
+ wire ram_data_T_92_clk;
+ reg ram_last [0:7];
+ wire ram_last_T_127_data;
+ wire [2:0] ram_last_T_127_addr;
+ wire ram_last_T_127_en;
+ wire ram_last_T_127_clk;
+ wire ram_last_T_92_data;
+ wire [2:0] ram_last_T_92_addr;
+ wire ram_last_T_92_mask;
+ wire ram_last_T_92_en;
+ wire ram_last_T_92_clk;
+ reg [4:0] ram_id [0:7];
+ wire [4:0] ram_id_T_127_data;
+ wire [2:0] ram_id_T_127_addr;
+ wire ram_id_T_127_en;
+ wire ram_id_T_127_clk;
+ wire [4:0] ram_id_T_92_data;
+ wire [2:0] ram_id_T_92_addr;
+ wire ram_id_T_92_mask;
+ wire ram_id_T_92_en;
+ wire ram_id_T_92_clk;
+ reg ram_user [0:7];
+ wire ram_user_T_127_data;
+ wire [2:0] ram_user_T_127_addr;
+ wire ram_user_T_127_en;
+ wire ram_user_T_127_clk;
+ wire ram_user_T_92_data;
+ wire [2:0] ram_user_T_92_addr;
+ wire ram_user_T_92_mask;
+ wire ram_user_T_92_en;
+ wire ram_user_T_92_clk;
+ reg [2:0] T_71;
+ reg [2:0] T_73;
+ reg maybe_full;
+ wire ptr_match;
+ wire T_78;
+ wire empty;
+ wire full;
+ wire maybe_flow;
+ wire do_flow;
+ wire T_84;
+ wire T_86;
+ wire do_enq;
+ wire T_88;
+ wire T_90;
+ wire do_deq;
+ wire T_99;
+ wire T_101;
+ wire [3:0] T_104;
+ wire [2:0] T_105;
+ wire [2:0] T_106;
+ wire T_108;
+ wire T_110;
+ wire [3:0] T_113;
+ wire [2:0] T_114;
+ wire [2:0] T_115;
+ wire T_116;
+ wire T_118;
+ wire T_120;
+ wire T_121;
+ wire T_123;
+ wire T_125;
+ wire T_126;
+ wire [1:0] T_133_resp;
+ wire [63:0] T_133_data;
+ wire T_133_last;
+ wire [4:0] T_133_id;
+ wire T_133_user;
+ wire [3:0] T_139;
+ wire [2:0] ptr_diff;
+ wire T_141;
+ wire [3:0] T_142;
+ assign io_enq_ready = T_126;
+ assign io_deq_valid = T_121;
+ assign io_deq_bits_resp = T_133_resp;
+ assign io_deq_bits_data = T_133_data;
+ assign io_deq_bits_last = T_133_last;
+ assign io_deq_bits_id = T_133_id;
+ assign io_deq_bits_user = T_133_user;
+ assign io_count = T_142;
+ assign ram_resp_T_127_addr = T_73;
+ assign ram_resp_T_127_en = 1'h1;
+ assign ram_resp_T_127_clk = clk;
+ assign ram_resp_T_127_data = ram_resp[ram_resp_T_127_addr];
+ assign ram_resp_T_92_data = io_enq_bits_resp;
+ assign ram_resp_T_92_addr = T_71;
+ assign ram_resp_T_92_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_resp_T_92_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_resp_T_92_clk = clk;
+ assign ram_data_T_127_addr = T_73;
+ assign ram_data_T_127_en = 1'h1;
+ assign ram_data_T_127_clk = clk;
+ assign ram_data_T_127_data = ram_data[ram_data_T_127_addr];
+ assign ram_data_T_92_data = io_enq_bits_data;
+ assign ram_data_T_92_addr = T_71;
+ assign ram_data_T_92_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_data_T_92_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_data_T_92_clk = clk;
+ assign ram_last_T_127_addr = T_73;
+ assign ram_last_T_127_en = 1'h1;
+ assign ram_last_T_127_clk = clk;
+ assign ram_last_T_127_data = ram_last[ram_last_T_127_addr];
+ assign ram_last_T_92_data = io_enq_bits_last;
+ assign ram_last_T_92_addr = T_71;
+ assign ram_last_T_92_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_last_T_92_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_last_T_92_clk = clk;
+ assign ram_id_T_127_addr = T_73;
+ assign ram_id_T_127_en = 1'h1;
+ assign ram_id_T_127_clk = clk;
+ assign ram_id_T_127_data = ram_id[ram_id_T_127_addr];
+ assign ram_id_T_92_data = io_enq_bits_id;
+ assign ram_id_T_92_addr = T_71;
+ assign ram_id_T_92_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_id_T_92_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_id_T_92_clk = clk;
+ assign ram_user_T_127_addr = T_73;
+ assign ram_user_T_127_en = 1'h1;
+ assign ram_user_T_127_clk = clk;
+ assign ram_user_T_127_data = ram_user[ram_user_T_127_addr];
+ assign ram_user_T_92_data = io_enq_bits_user;
+ assign ram_user_T_92_addr = T_71;
+ assign ram_user_T_92_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_user_T_92_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_user_T_92_clk = clk;
+ assign ptr_match = T_71 == T_73;
+ assign T_78 = maybe_full == 1'h0;
+ assign empty = ptr_match & T_78;
+ assign full = ptr_match & maybe_full;
+ assign maybe_flow = 1'h0 & empty;
+ assign do_flow = maybe_flow & io_deq_ready;
+ assign T_84 = io_enq_ready & io_enq_valid;
+ assign T_86 = do_flow == 1'h0;
+ assign do_enq = T_84 & T_86;
+ assign T_88 = io_deq_ready & io_deq_valid;
+ assign T_90 = do_flow == 1'h0;
+ assign do_deq = T_88 & T_90;
+ assign T_99 = T_71 == 3'h7;
+ assign T_101 = 1'h0 & T_99;
+ assign T_104 = T_71 + 1'h1;
+ assign T_105 = T_104[2:0];
+ assign T_106 = T_101 ? 1'h0 : T_105;
+ assign T_108 = T_73 == 3'h7;
+ assign T_110 = 1'h0 & T_108;
+ assign T_113 = T_73 + 1'h1;
+ assign T_114 = T_113[2:0];
+ assign T_115 = T_110 ? 1'h0 : T_114;
+ assign T_116 = do_enq != do_deq;
+ assign T_118 = empty == 1'h0;
+ assign T_120 = 1'h0 & io_enq_valid;
+ assign T_121 = T_118 | T_120;
+ assign T_123 = full == 1'h0;
+ assign T_125 = 1'h0 & io_deq_ready;
+ assign T_126 = T_123 | T_125;
+ assign T_133_resp = maybe_flow ? io_enq_bits_resp : ram_resp_T_127_data;
+ assign T_133_data = maybe_flow ? io_enq_bits_data : ram_data_T_127_data;
+ assign T_133_last = maybe_flow ? io_enq_bits_last : ram_last_T_127_data;
+ assign T_133_id = maybe_flow ? io_enq_bits_id : ram_id_T_127_data;
+ assign T_133_user = maybe_flow ? io_enq_bits_user : ram_user_T_127_data;
+ assign T_139 = T_71 - T_73;
+ assign ptr_diff = T_139[2:0];
+ assign T_141 = maybe_full & ptr_match;
+ assign T_142 = {T_141,ptr_diff};
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ for (initvar = 0; initvar < 8; initvar = initvar+1)
+ ram_resp[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 8; initvar = initvar+1)
+ ram_data[initvar] = {2{$random}};
+ for (initvar = 0; initvar < 8; initvar = initvar+1)
+ ram_last[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 8; initvar = initvar+1)
+ ram_id[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 8; initvar = initvar+1)
+ ram_user[initvar] = {1{$random}};
+ T_71 = {1{$random}};
+ T_73 = {1{$random}};
+ maybe_full = {1{$random}};
+ end
+`endif
+ always @(posedge ram_resp_T_92_clk) begin
+ if(ram_resp_T_92_en & ram_resp_T_92_mask) begin
+ ram_resp[ram_resp_T_92_addr] <= ram_resp_T_92_data;
+ end
+ end
+ always @(posedge ram_data_T_92_clk) begin
+ if(ram_data_T_92_en & ram_data_T_92_mask) begin
+ ram_data[ram_data_T_92_addr] <= ram_data_T_92_data;
+ end
+ end
+ always @(posedge ram_last_T_92_clk) begin
+ if(ram_last_T_92_en & ram_last_T_92_mask) begin
+ ram_last[ram_last_T_92_addr] <= ram_last_T_92_data;
+ end
+ end
+ always @(posedge ram_id_T_92_clk) begin
+ if(ram_id_T_92_en & ram_id_T_92_mask) begin
+ ram_id[ram_id_T_92_addr] <= ram_id_T_92_data;
+ end
+ end
+ always @(posedge ram_user_T_92_clk) begin
+ if(ram_user_T_92_en & ram_user_T_92_mask) begin
+ ram_user[ram_user_T_92_addr] <= ram_user_T_92_data;
+ end
+ end
+ always @(posedge clk) begin
+ if(reset) begin
+ T_71 <= 3'h0;
+ end else begin
+ if(do_enq) begin
+ T_71 <= T_106;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_73 <= 3'h0;
+ end else begin
+ if(do_deq) begin
+ T_73 <= T_115;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ maybe_full <= 1'h0;
+ end else begin
+ if(T_116) begin
+ maybe_full <= do_enq;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module Queue_76(
+ input clk,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [1:0] io_enq_bits_resp,
+ input [4:0] io_enq_bits_id,
+ input io_enq_bits_user,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [1:0] io_deq_bits_resp,
+ output [4:0] io_deq_bits_id,
+ output io_deq_bits_user,
+ output [1:0] io_count
+);
+ reg [1:0] ram_resp [0:1];
+ wire [1:0] ram_resp_T_107_data;
+ wire ram_resp_T_107_addr;
+ wire ram_resp_T_107_en;
+ wire ram_resp_T_107_clk;
+ wire [1:0] ram_resp_T_74_data;
+ wire ram_resp_T_74_addr;
+ wire ram_resp_T_74_mask;
+ wire ram_resp_T_74_en;
+ wire ram_resp_T_74_clk;
+ reg [4:0] ram_id [0:1];
+ wire [4:0] ram_id_T_107_data;
+ wire ram_id_T_107_addr;
+ wire ram_id_T_107_en;
+ wire ram_id_T_107_clk;
+ wire [4:0] ram_id_T_74_data;
+ wire ram_id_T_74_addr;
+ wire ram_id_T_74_mask;
+ wire ram_id_T_74_en;
+ wire ram_id_T_74_clk;
+ reg ram_user [0:1];
+ wire ram_user_T_107_data;
+ wire ram_user_T_107_addr;
+ wire ram_user_T_107_en;
+ wire ram_user_T_107_clk;
+ wire ram_user_T_74_data;
+ wire ram_user_T_74_addr;
+ wire ram_user_T_74_mask;
+ wire ram_user_T_74_en;
+ wire ram_user_T_74_clk;
+ reg T_53;
+ reg T_55;
+ reg maybe_full;
+ wire ptr_match;
+ wire T_60;
+ wire empty;
+ wire full;
+ wire maybe_flow;
+ wire do_flow;
+ wire T_66;
+ wire T_68;
+ wire do_enq;
+ wire T_70;
+ wire T_72;
+ wire do_deq;
+ wire T_79;
+ wire T_81;
+ wire [1:0] T_84;
+ wire T_85;
+ wire T_86;
+ wire T_88;
+ wire T_90;
+ wire [1:0] T_93;
+ wire T_94;
+ wire T_95;
+ wire T_96;
+ wire T_98;
+ wire T_100;
+ wire T_101;
+ wire T_103;
+ wire T_105;
+ wire T_106;
+ wire [1:0] T_111_resp;
+ wire [4:0] T_111_id;
+ wire T_111_user;
+ wire [1:0] T_115;
+ wire ptr_diff;
+ wire T_117;
+ wire [1:0] T_118;
+ assign io_enq_ready = T_106;
+ assign io_deq_valid = T_101;
+ assign io_deq_bits_resp = T_111_resp;
+ assign io_deq_bits_id = T_111_id;
+ assign io_deq_bits_user = T_111_user;
+ assign io_count = T_118;
+ assign ram_resp_T_107_addr = T_55;
+ assign ram_resp_T_107_en = 1'h1;
+ assign ram_resp_T_107_clk = clk;
+ assign ram_resp_T_107_data = ram_resp[ram_resp_T_107_addr];
+ assign ram_resp_T_74_data = io_enq_bits_resp;
+ assign ram_resp_T_74_addr = T_53;
+ assign ram_resp_T_74_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_resp_T_74_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_resp_T_74_clk = clk;
+ assign ram_id_T_107_addr = T_55;
+ assign ram_id_T_107_en = 1'h1;
+ assign ram_id_T_107_clk = clk;
+ assign ram_id_T_107_data = ram_id[ram_id_T_107_addr];
+ assign ram_id_T_74_data = io_enq_bits_id;
+ assign ram_id_T_74_addr = T_53;
+ assign ram_id_T_74_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_id_T_74_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_id_T_74_clk = clk;
+ assign ram_user_T_107_addr = T_55;
+ assign ram_user_T_107_en = 1'h1;
+ assign ram_user_T_107_clk = clk;
+ assign ram_user_T_107_data = ram_user[ram_user_T_107_addr];
+ assign ram_user_T_74_data = io_enq_bits_user;
+ assign ram_user_T_74_addr = T_53;
+ assign ram_user_T_74_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_user_T_74_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_user_T_74_clk = clk;
+ assign ptr_match = T_53 == T_55;
+ assign T_60 = maybe_full == 1'h0;
+ assign empty = ptr_match & T_60;
+ assign full = ptr_match & maybe_full;
+ assign maybe_flow = 1'h0 & empty;
+ assign do_flow = maybe_flow & io_deq_ready;
+ assign T_66 = io_enq_ready & io_enq_valid;
+ assign T_68 = do_flow == 1'h0;
+ assign do_enq = T_66 & T_68;
+ assign T_70 = io_deq_ready & io_deq_valid;
+ assign T_72 = do_flow == 1'h0;
+ assign do_deq = T_70 & T_72;
+ assign T_79 = T_53 == 1'h1;
+ assign T_81 = 1'h0 & T_79;
+ assign T_84 = T_53 + 1'h1;
+ assign T_85 = T_84[0:0];
+ assign T_86 = T_81 ? 1'h0 : T_85;
+ assign T_88 = T_55 == 1'h1;
+ assign T_90 = 1'h0 & T_88;
+ assign T_93 = T_55 + 1'h1;
+ assign T_94 = T_93[0:0];
+ assign T_95 = T_90 ? 1'h0 : T_94;
+ assign T_96 = do_enq != do_deq;
+ assign T_98 = empty == 1'h0;
+ assign T_100 = 1'h0 & io_enq_valid;
+ assign T_101 = T_98 | T_100;
+ assign T_103 = full == 1'h0;
+ assign T_105 = 1'h0 & io_deq_ready;
+ assign T_106 = T_103 | T_105;
+ assign T_111_resp = maybe_flow ? io_enq_bits_resp : ram_resp_T_107_data;
+ assign T_111_id = maybe_flow ? io_enq_bits_id : ram_id_T_107_data;
+ assign T_111_user = maybe_flow ? io_enq_bits_user : ram_user_T_107_data;
+ assign T_115 = T_53 - T_55;
+ assign ptr_diff = T_115[0:0];
+ assign T_117 = maybe_full & ptr_match;
+ assign T_118 = {T_117,ptr_diff};
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_resp[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_id[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_user[initvar] = {1{$random}};
+ T_53 = {1{$random}};
+ T_55 = {1{$random}};
+ maybe_full = {1{$random}};
+ end
+`endif
+ always @(posedge ram_resp_T_74_clk) begin
+ if(ram_resp_T_74_en & ram_resp_T_74_mask) begin
+ ram_resp[ram_resp_T_74_addr] <= ram_resp_T_74_data;
+ end
+ end
+ always @(posedge ram_id_T_74_clk) begin
+ if(ram_id_T_74_en & ram_id_T_74_mask) begin
+ ram_id[ram_id_T_74_addr] <= ram_id_T_74_data;
+ end
+ end
+ always @(posedge ram_user_T_74_clk) begin
+ if(ram_user_T_74_en & ram_user_T_74_mask) begin
+ ram_user[ram_user_T_74_addr] <= ram_user_T_74_data;
+ end
+ end
+ always @(posedge clk) begin
+ if(reset) begin
+ T_53 <= 1'h0;
+ end else begin
+ if(do_enq) begin
+ T_53 <= T_86;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_55 <= 1'h0;
+ end else begin
+ if(do_deq) begin
+ T_55 <= T_95;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ maybe_full <= 1'h0;
+ end else begin
+ if(T_96) begin
+ maybe_full <= do_enq;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module RTC(
+ input clk,
+ input reset,
+ input io_aw_ready,
+ output io_aw_valid,
+ output [31:0] io_aw_bits_addr,
+ output [7:0] io_aw_bits_len,
+ output [2:0] io_aw_bits_size,
+ output [1:0] io_aw_bits_burst,
+ output io_aw_bits_lock,
+ output [3:0] io_aw_bits_cache,
+ output [2:0] io_aw_bits_prot,
+ output [3:0] io_aw_bits_qos,
+ output [3:0] io_aw_bits_region,
+ output [4:0] io_aw_bits_id,
+ output io_aw_bits_user,
+ input io_w_ready,
+ output io_w_valid,
+ output [63:0] io_w_bits_data,
+ output io_w_bits_last,
+ output [7:0] io_w_bits_strb,
+ output io_w_bits_user,
+ output io_b_ready,
+ input io_b_valid,
+ input [1:0] io_b_bits_resp,
+ input [4:0] io_b_bits_id,
+ input io_b_bits_user,
+ input io_ar_ready,
+ output io_ar_valid,
+ output [31:0] io_ar_bits_addr,
+ output [7:0] io_ar_bits_len,
+ output [2:0] io_ar_bits_size,
+ output [1:0] io_ar_bits_burst,
+ output io_ar_bits_lock,
+ output [3:0] io_ar_bits_cache,
+ output [2:0] io_ar_bits_prot,
+ output [3:0] io_ar_bits_qos,
+ output [3:0] io_ar_bits_region,
+ output [4:0] io_ar_bits_id,
+ output io_ar_bits_user,
+ output io_r_ready,
+ input io_r_valid,
+ input [1:0] io_r_bits_resp,
+ input [63:0] io_r_bits_data,
+ input io_r_bits_last,
+ input [4:0] io_r_bits_id,
+ input io_r_bits_user
+);
+ wire [30:0] addrTable_0;
+ reg [63:0] rtc;
+ reg [6:0] T_217;
+ wire rtc_tick;
+ wire T_221;
+ wire [7:0] T_224;
+ wire [6:0] T_225;
+ wire [6:0] T_226;
+ reg sending_addr;
+ reg sending_data;
+ wire T_233_0;
+ reg send_acked_0;
+ wire coreId;
+ wire [64:0] T_244;
+ wire [63:0] T_245;
+ wire T_248_0;
+ wire T_253;
+ wire T_255;
+ wire T_258;
+ wire GEN_0;
+ wire [31:0] T_276_addr;
+ wire [7:0] T_276_len;
+ wire [2:0] T_276_size;
+ wire [1:0] T_276_burst;
+ wire T_276_lock;
+ wire [3:0] T_276_cache;
+ wire [2:0] T_276_prot;
+ wire [3:0] T_276_qos;
+ wire [3:0] T_276_region;
+ wire [4:0] T_276_id;
+ wire T_276_user;
+ wire [30:0] GEN_1;
+ wire [63:0] T_300_data;
+ wire T_300_last;
+ wire [7:0] T_300_strb;
+ wire T_300_user;
+ wire [1:0] T_306;
+ wire [3:0] T_307;
+ wire [7:0] T_308;
+ wire T_314;
+ wire T_315;
+ wire T_317;
+ wire T_319;
+ wire T_321;
+ wire GEN_2;
+ wire GEN_3;
+ reg [31:0] GEN_4;
+ reg [7:0] GEN_5;
+ reg [2:0] GEN_6;
+ reg [1:0] GEN_7;
+ reg GEN_8;
+ reg [3:0] GEN_9;
+ reg [2:0] GEN_10;
+ reg [3:0] GEN_11;
+ reg [3:0] GEN_12;
+ reg [4:0] GEN_13;
+ reg GEN_14;
+ assign io_aw_valid = sending_addr;
+ assign io_aw_bits_addr = T_276_addr;
+ assign io_aw_bits_len = T_276_len;
+ assign io_aw_bits_size = T_276_size;
+ assign io_aw_bits_burst = T_276_burst;
+ assign io_aw_bits_lock = T_276_lock;
+ assign io_aw_bits_cache = T_276_cache;
+ assign io_aw_bits_prot = T_276_prot;
+ assign io_aw_bits_qos = T_276_qos;
+ assign io_aw_bits_region = T_276_region;
+ assign io_aw_bits_id = T_276_id;
+ assign io_aw_bits_user = T_276_user;
+ assign io_w_valid = sending_data;
+ assign io_w_bits_data = T_300_data;
+ assign io_w_bits_last = T_300_last;
+ assign io_w_bits_strb = T_300_strb;
+ assign io_w_bits_user = T_300_user;
+ assign io_b_ready = 1'h1;
+ assign io_ar_valid = 1'h0;
+ assign io_ar_bits_addr = GEN_4;
+ assign io_ar_bits_len = GEN_5;
+ assign io_ar_bits_size = GEN_6;
+ assign io_ar_bits_burst = GEN_7;
+ assign io_ar_bits_lock = GEN_8;
+ assign io_ar_bits_cache = GEN_9;
+ assign io_ar_bits_prot = GEN_10;
+ assign io_ar_bits_qos = GEN_11;
+ assign io_ar_bits_region = GEN_12;
+ assign io_ar_bits_id = GEN_13;
+ assign io_ar_bits_user = GEN_14;
+ assign io_r_ready = 1'h0;
+ assign addrTable_0 = 31'h4000b808;
+ assign rtc_tick = T_217 == 7'h63;
+ assign T_221 = 1'h1 & rtc_tick;
+ assign T_224 = T_217 + 1'h1;
+ assign T_225 = T_224[6:0];
+ assign T_226 = T_221 ? 1'h0 : T_225;
+ assign T_233_0 = 1'h1;
+ assign coreId = 1'h0;
+ assign T_244 = rtc + 1'h1;
+ assign T_245 = T_244[63:0];
+ assign T_248_0 = 1'h0;
+ assign T_253 = io_aw_ready & io_aw_valid;
+ assign T_255 = io_w_ready & io_w_valid;
+ assign T_258 = io_b_ready & io_b_valid;
+ assign GEN_0 = 1'h1;
+ assign T_276_addr = GEN_1;
+ assign T_276_len = 1'h0;
+ assign T_276_size = 2'h3;
+ assign T_276_burst = 2'h1;
+ assign T_276_lock = 1'h0;
+ assign T_276_cache = 4'h0;
+ assign T_276_prot = 3'h0;
+ assign T_276_qos = 4'h0;
+ assign T_276_region = 4'h0;
+ assign T_276_id = coreId;
+ assign T_276_user = 1'h0;
+ assign GEN_1 = addrTable_0;
+ assign T_300_data = rtc;
+ assign T_300_last = 1'h1;
+ assign T_300_strb = T_308;
+ assign T_300_user = 1'h0;
+ assign T_306 = {1'h1,1'h1};
+ assign T_307 = {T_306,T_306};
+ assign T_308 = {T_307,T_307};
+ assign T_314 = rtc_tick == 1'h0;
+ assign T_315 = T_314 | send_acked_0;
+ assign T_317 = reset == 1'h0;
+ assign T_319 = T_315 == 1'h0;
+ assign T_321 = reset == 1'h0;
+ assign GEN_2 = T_317 & T_319;
+ assign GEN_3 = 1'h0 == io_b_bits_id;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ rtc = {2{$random}};
+ T_217 = {1{$random}};
+ sending_addr = {1{$random}};
+ sending_data = {1{$random}};
+ send_acked_0 = {1{$random}};
+ GEN_4 = {1{$random}};
+ GEN_5 = {1{$random}};
+ GEN_6 = {1{$random}};
+ GEN_7 = {1{$random}};
+ GEN_8 = {1{$random}};
+ GEN_9 = {1{$random}};
+ GEN_10 = {1{$random}};
+ GEN_11 = {1{$random}};
+ GEN_12 = {1{$random}};
+ GEN_13 = {1{$random}};
+ GEN_14 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ rtc <= 64'h0;
+ end else begin
+ if(rtc_tick) begin
+ rtc <= T_245;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_217 <= 7'h0;
+ end else begin
+ T_217 <= T_226;
+ end
+ if(reset) begin
+ sending_addr <= 1'h0;
+ end else begin
+ if(T_255) begin
+ sending_addr <= 1'h0;
+ end else begin
+ if(T_253) begin
+ sending_addr <= 1'h0;
+ end else begin
+ if(rtc_tick) begin
+ sending_addr <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ if(reset) begin
+ sending_data <= 1'h0;
+ end else begin
+ if(rtc_tick) begin
+ sending_data <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ send_acked_0 <= T_233_0;
+ end else begin
+ if(T_258) begin
+ if(GEN_3) begin
+ send_acked_0 <= GEN_0;
+ end else begin
+ if(rtc_tick) begin
+ send_acked_0 <= T_248_0;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(rtc_tick) begin
+ send_acked_0 <= T_248_0;
+ end else begin
+ ;
+ end
+ end
+ end
+ `ifndef SYNTHESIS
+ if(GEN_2 & T_321) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Not all clocks were updated for rtc tick");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_317 & T_319) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ end
+endmodule
+module SmiIONastiReadIOConverter(
+ input clk,
+ input reset,
+ output io_ar_ready,
+ input io_ar_valid,
+ input [31:0] io_ar_bits_addr,
+ input [7:0] io_ar_bits_len,
+ input [2:0] io_ar_bits_size,
+ input [1:0] io_ar_bits_burst,
+ input io_ar_bits_lock,
+ input [3:0] io_ar_bits_cache,
+ input [2:0] io_ar_bits_prot,
+ input [3:0] io_ar_bits_qos,
+ input [3:0] io_ar_bits_region,
+ input [4:0] io_ar_bits_id,
+ input io_ar_bits_user,
+ input io_r_ready,
+ output io_r_valid,
+ output [1:0] io_r_bits_resp,
+ output [63:0] io_r_bits_data,
+ output io_r_bits_last,
+ output [4:0] io_r_bits_id,
+ output io_r_bits_user,
+ input io_smi_req_ready,
+ output io_smi_req_valid,
+ output io_smi_req_bits_rw,
+ output [11:0] io_smi_req_bits_addr,
+ output [63:0] io_smi_req_bits_data,
+ output io_smi_resp_ready,
+ input io_smi_resp_valid,
+ input [63:0] io_smi_resp_bits
+);
+ reg [1:0] state;
+ reg nWords;
+ reg [7:0] nBeats;
+ reg [11:0] addr;
+ reg [4:0] id;
+ reg [2:0] byteOff;
+ reg sendInd;
+ reg recvInd;
+ reg sendDone;
+ wire [63:0] T_141_0;
+ reg [63:0] buffer_0;
+ wire T_149;
+ wire T_150;
+ wire T_152;
+ wire T_153;
+ wire T_155;
+ wire T_156;
+ wire T_158;
+ wire [1:0] T_166_resp;
+ wire [63:0] T_166_data;
+ wire T_166_last;
+ wire [4:0] T_166_id;
+ wire T_166_user;
+ wire T_173;
+ wire T_175;
+ wire [2:0] T_177;
+ wire T_179;
+ wire [3:0] T_182;
+ wire [2:0] T_183;
+ wire [7:0] T_184;
+ wire [8:0] T_186;
+ wire [7:0] T_187;
+ wire [11:0] T_189;
+ wire T_190;
+ wire [12:0] T_192;
+ wire [11:0] T_193;
+ wire [1:0] T_195;
+ wire T_196;
+ wire T_197;
+ wire T_198;
+ wire [1:0] T_200;
+ wire T_201;
+ wire [5:0] T_204;
+ wire [63:0] T_205;
+ wire [63:0] GEN_0;
+ wire T_206;
+ wire T_207;
+ wire [8:0] T_213;
+ wire [7:0] T_214;
+ wire T_215;
+ wire GEN_1;
+ reg [63:0] GEN_2;
+ assign io_ar_ready = T_149;
+ assign io_r_valid = T_156;
+ assign io_r_bits_resp = T_166_resp;
+ assign io_r_bits_data = T_166_data;
+ assign io_r_bits_last = T_166_last;
+ assign io_r_bits_id = T_166_id;
+ assign io_r_bits_user = T_166_user;
+ assign io_smi_req_valid = T_153;
+ assign io_smi_req_bits_rw = 1'h0;
+ assign io_smi_req_bits_addr = addr;
+ assign io_smi_req_bits_data = GEN_2;
+ assign io_smi_resp_ready = T_155;
+ assign T_141_0 = 64'h0;
+ assign T_149 = state == 1'h0;
+ assign T_150 = state == 1'h1;
+ assign T_152 = sendDone == 1'h0;
+ assign T_153 = T_150 & T_152;
+ assign T_155 = state == 1'h1;
+ assign T_156 = state == 2'h2;
+ assign T_158 = nBeats == 1'h0;
+ assign T_166_resp = 1'h0;
+ assign T_166_data = buffer_0;
+ assign T_166_last = T_158;
+ assign T_166_id = id;
+ assign T_166_user = 1'h0;
+ assign T_173 = io_ar_ready & io_ar_valid;
+ assign T_175 = io_ar_bits_size < 2'h3;
+ assign T_177 = io_ar_bits_addr[2:0];
+ assign T_179 = T_175 == 1'h0;
+ assign T_182 = io_ar_bits_size - 2'h3;
+ assign T_183 = T_182[2:0];
+ assign T_184 = 1'h1 << T_183;
+ assign T_186 = T_184 - 1'h1;
+ assign T_187 = T_186[7:0];
+ assign T_189 = io_ar_bits_addr[14:3];
+ assign T_190 = io_smi_req_ready & io_smi_req_valid;
+ assign T_192 = addr + 1'h1;
+ assign T_193 = T_192[11:0];
+ assign T_195 = sendInd + 1'h1;
+ assign T_196 = T_195[0:0];
+ assign T_197 = sendInd == nWords;
+ assign T_198 = io_smi_resp_ready & io_smi_resp_valid;
+ assign T_200 = recvInd + 1'h1;
+ assign T_201 = T_200[0:0];
+ assign T_204 = {byteOff,3'h0};
+ assign T_205 = io_smi_resp_bits >> T_204;
+ assign GEN_0 = T_205;
+ assign T_206 = recvInd == nWords;
+ assign T_207 = io_r_ready & io_r_valid;
+ assign T_213 = nBeats - 1'h1;
+ assign T_214 = T_213[7:0];
+ assign T_215 = io_r_bits_last ? 1'h0 : 1'h1;
+ assign GEN_1 = 1'h0 == recvInd;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ state = {1{$random}};
+ nWords = {1{$random}};
+ nBeats = {1{$random}};
+ addr = {1{$random}};
+ id = {1{$random}};
+ byteOff = {1{$random}};
+ sendInd = {1{$random}};
+ recvInd = {1{$random}};
+ sendDone = {1{$random}};
+ buffer_0 = {2{$random}};
+ GEN_2 = {2{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ state <= 1'h0;
+ end else begin
+ if(T_207) begin
+ state <= T_215;
+ end else begin
+ if(T_198) begin
+ if(T_206) begin
+ state <= 2'h2;
+ end else begin
+ if(T_173) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_173) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_173) begin
+ if(T_179) begin
+ nWords <= T_187;
+ end else begin
+ if(T_175) begin
+ nWords <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_207) begin
+ nBeats <= T_214;
+ end else begin
+ if(T_173) begin
+ nBeats <= io_ar_bits_len;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_190) begin
+ addr <= T_193;
+ end else begin
+ if(T_173) begin
+ addr <= T_189;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_173) begin
+ id <= io_ar_bits_id;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_173) begin
+ if(T_179) begin
+ byteOff <= 1'h0;
+ end else begin
+ if(T_175) begin
+ byteOff <= T_177;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ sendInd <= 1'h0;
+ end else begin
+ if(T_207) begin
+ sendInd <= 1'h0;
+ end else begin
+ if(T_190) begin
+ sendInd <= T_196;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ recvInd <= 1'h0;
+ end else begin
+ if(T_207) begin
+ recvInd <= 1'h0;
+ end else begin
+ if(T_198) begin
+ recvInd <= T_201;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ sendDone <= 1'h0;
+ end else begin
+ if(T_207) begin
+ sendDone <= 1'h0;
+ end else begin
+ if(T_190) begin
+ sendDone <= T_197;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ buffer_0 <= T_141_0;
+ end else begin
+ if(T_207) begin
+ buffer_0 <= 1'h0;
+ end else begin
+ if(T_198) begin
+ if(GEN_1) begin
+ buffer_0 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+endmodule
+module SmiIONastiWriteIOConverter(
+ input clk,
+ input reset,
+ output io_aw_ready,
+ input io_aw_valid,
+ input [31:0] io_aw_bits_addr,
+ input [7:0] io_aw_bits_len,
+ input [2:0] io_aw_bits_size,
+ input [1:0] io_aw_bits_burst,
+ input io_aw_bits_lock,
+ input [3:0] io_aw_bits_cache,
+ input [2:0] io_aw_bits_prot,
+ input [3:0] io_aw_bits_qos,
+ input [3:0] io_aw_bits_region,
+ input [4:0] io_aw_bits_id,
+ input io_aw_bits_user,
+ output io_w_ready,
+ input io_w_valid,
+ input [63:0] io_w_bits_data,
+ input io_w_bits_last,
+ input [7:0] io_w_bits_strb,
+ input io_w_bits_user,
+ input io_b_ready,
+ output io_b_valid,
+ output [1:0] io_b_bits_resp,
+ output [4:0] io_b_bits_id,
+ output io_b_bits_user,
+ input io_smi_req_ready,
+ output io_smi_req_valid,
+ output io_smi_req_bits_rw,
+ output [11:0] io_smi_req_bits_addr,
+ output [63:0] io_smi_req_bits_data,
+ output io_smi_resp_ready,
+ input io_smi_resp_valid,
+ input [63:0] io_smi_resp_bits
+);
+ wire T_144;
+ wire T_146;
+ wire T_147;
+ wire T_149;
+ wire T_151;
+ wire T_153;
+ reg [4:0] id;
+ reg [11:0] addr;
+ reg [2:0] size;
+ reg strb;
+ reg [63:0] data;
+ reg last;
+ reg [2:0] state;
+ wire T_173;
+ wire T_174;
+ wire T_175;
+ wire T_176;
+ wire T_177;
+ wire [63:0] T_179;
+ wire T_180;
+ wire T_181;
+ wire [1:0] T_187_resp;
+ wire [4:0] T_187_id;
+ wire T_187_user;
+ wire T_193;
+ wire [11:0] T_194;
+ wire T_196;
+ wire [7:0] T_199;
+ wire [255:0] T_200;
+ wire [256:0] T_202;
+ wire [255:0] T_203;
+ wire [255:0] T_204;
+ wire T_205;
+ wire T_207_0;
+ wire T_210;
+ wire T_212;
+ wire [1:0] T_213;
+ wire T_214;
+ wire T_216;
+ wire T_217;
+ wire T_219;
+ wire T_220;
+ wire T_221;
+ wire [6:0] T_223;
+ wire [63:0] T_224;
+ wire [12:0] T_225;
+ wire [11:0] T_226;
+ wire T_227;
+ wire T_228;
+ wire GEN_0;
+ assign io_aw_ready = T_173;
+ assign io_w_ready = T_174;
+ assign io_b_valid = T_181;
+ assign io_b_bits_resp = T_187_resp;
+ assign io_b_bits_id = T_187_id;
+ assign io_b_bits_user = T_187_user;
+ assign io_smi_req_valid = T_177;
+ assign io_smi_req_bits_rw = 1'h1;
+ assign io_smi_req_bits_addr = addr;
+ assign io_smi_req_bits_data = T_179;
+ assign io_smi_resp_ready = T_180;
+ assign T_144 = io_aw_valid == 1'h0;
+ assign T_146 = io_aw_bits_size >= 2'h3;
+ assign T_147 = T_144 | T_146;
+ assign T_149 = reset == 1'h0;
+ assign T_151 = T_147 == 1'h0;
+ assign T_153 = reset == 1'h0;
+ assign T_173 = state == 1'h0;
+ assign T_174 = state == 1'h1;
+ assign T_175 = state == 2'h2;
+ assign T_176 = strb;
+ assign T_177 = T_175 & T_176;
+ assign T_179 = data;
+ assign T_180 = state == 2'h3;
+ assign T_181 = state == 3'h4;
+ assign T_187_resp = 1'h0;
+ assign T_187_id = id;
+ assign T_187_user = 1'h0;
+ assign T_193 = io_aw_ready & io_aw_valid;
+ assign T_194 = io_aw_bits_addr[14:3];
+ assign T_196 = io_w_ready & io_w_valid;
+ assign T_199 = 1'h1 << size;
+ assign T_200 = 1'h1 << T_199;
+ assign T_202 = T_200 - 1'h1;
+ assign T_203 = T_202[255:0];
+ assign T_204 = T_203 & io_w_bits_strb;
+ assign T_205 = T_204[0];
+ assign T_207_0 = T_205;
+ assign T_210 = state == 2'h2;
+ assign T_212 = strb == 1'h0;
+ assign T_213 = last ? 2'h3 : 1'h1;
+ assign T_214 = strb;
+ assign T_216 = T_214 == 1'h0;
+ assign T_217 = io_smi_req_ready | T_216;
+ assign T_219 = T_212 == 1'h0;
+ assign T_220 = T_219 & T_217;
+ assign T_221 = strb >> 1'h1;
+ assign T_223 = {1'h1,6'h0};
+ assign T_224 = data >> T_223;
+ assign T_225 = addr + 1'h1;
+ assign T_226 = T_225[11:0];
+ assign T_227 = io_smi_resp_ready & io_smi_resp_valid;
+ assign T_228 = io_b_ready & io_b_valid;
+ assign GEN_0 = T_149 & T_151;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ id = {1{$random}};
+ addr = {1{$random}};
+ size = {1{$random}};
+ strb = {1{$random}};
+ data = {2{$random}};
+ last = {1{$random}};
+ state = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_193) begin
+ id <= io_aw_bits_id;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_210) begin
+ if(T_220) begin
+ addr <= T_226;
+ end else begin
+ if(T_193) begin
+ addr <= T_194;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_193) begin
+ addr <= T_194;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_193) begin
+ size <= io_aw_bits_size;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_210) begin
+ if(T_220) begin
+ strb <= T_221;
+ end else begin
+ if(T_196) begin
+ strb <= T_207_0;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_196) begin
+ strb <= T_207_0;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_210) begin
+ if(T_220) begin
+ data <= T_224;
+ end else begin
+ if(T_196) begin
+ data <= io_w_bits_data;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_196) begin
+ data <= io_w_bits_data;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_196) begin
+ last <= io_w_bits_last;
+ end else begin
+ if(T_193) begin
+ last <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ state <= 1'h0;
+ end else begin
+ if(T_228) begin
+ state <= 1'h0;
+ end else begin
+ if(T_227) begin
+ state <= 3'h4;
+ end else begin
+ if(T_210) begin
+ if(T_212) begin
+ state <= T_213;
+ end else begin
+ if(T_196) begin
+ state <= 2'h2;
+ end else begin
+ if(T_193) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_196) begin
+ state <= 2'h2;
+ end else begin
+ if(T_193) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ `ifndef SYNTHESIS
+ if(GEN_0 & T_153) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Nasti size must be >= Smi size");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_149 & T_151) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ end
+endmodule
+module RRArbiter_77(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input io_in_0_bits_rw,
+ input [11:0] io_in_0_bits_addr,
+ input [63:0] io_in_0_bits_data,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input io_in_1_bits_rw,
+ input [11:0] io_in_1_bits_addr,
+ input [63:0] io_in_1_bits_data,
+ input io_out_ready,
+ output io_out_valid,
+ output io_out_bits_rw,
+ output [11:0] io_out_bits_addr,
+ output [63:0] io_out_bits_data,
+ output io_chosen
+);
+ wire T_130;
+ wire GEN_0;
+ wire GEN_1;
+ wire [11:0] GEN_2;
+ wire [63:0] GEN_3;
+ wire GEN_4;
+ reg T_167;
+ wire T_168;
+ wire T_169;
+ wire T_171;
+ wire T_172;
+ wire T_175;
+ wire T_177;
+ wire T_179;
+ wire T_180;
+ wire T_182;
+ wire T_184;
+ wire T_185;
+ wire T_186;
+ wire T_188;
+ wire T_190;
+ wire T_191;
+ wire T_192;
+ wire T_194;
+ wire T_195;
+ wire T_196;
+ wire T_198;
+ wire T_199;
+ wire T_200;
+ wire T_202;
+ wire T_203;
+ wire T_204;
+ wire T_207;
+ wire T_209;
+ wire T_210;
+ wire T_212;
+ wire T_213;
+ wire T_214;
+ wire GEN_5;
+ wire GEN_6;
+ wire GEN_7;
+ wire GEN_8;
+ assign io_in_0_ready = T_200;
+ assign io_in_1_ready = T_204;
+ assign io_out_valid = GEN_0;
+ assign io_out_bits_rw = GEN_1;
+ assign io_out_bits_addr = GEN_2;
+ assign io_out_bits_data = GEN_3;
+ assign io_chosen = T_130;
+ assign T_130 = T_213;
+ assign GEN_0 = GEN_5 ? io_in_1_valid : io_in_0_valid;
+ assign GEN_1 = GEN_6 ? io_in_1_bits_rw : io_in_0_bits_rw;
+ assign GEN_2 = GEN_7 ? io_in_1_bits_addr : io_in_0_bits_addr;
+ assign GEN_3 = GEN_8 ? io_in_1_bits_data : io_in_0_bits_data;
+ assign GEN_4 = 1'h0;
+ assign T_168 = 1'h0 > T_167;
+ assign T_169 = io_in_0_valid & T_168;
+ assign T_171 = 1'h1 > T_167;
+ assign T_172 = io_in_1_valid & T_171;
+ assign T_175 = 1'h0 | T_169;
+ assign T_177 = T_175 == 1'h0;
+ assign T_179 = 1'h0 | T_169;
+ assign T_180 = T_179 | T_172;
+ assign T_182 = T_180 == 1'h0;
+ assign T_184 = 1'h0 | T_169;
+ assign T_185 = T_184 | T_172;
+ assign T_186 = T_185 | io_in_0_valid;
+ assign T_188 = T_186 == 1'h0;
+ assign T_190 = 1'h0 > T_167;
+ assign T_191 = 1'h1 & T_190;
+ assign T_192 = T_191 | T_182;
+ assign T_194 = 1'h1 > T_167;
+ assign T_195 = T_177 & T_194;
+ assign T_196 = T_195 | T_188;
+ assign T_198 = 1'h1 == 1'h0;
+ assign T_199 = 1'h0 ? T_198 : T_192;
+ assign T_200 = T_199 & io_out_ready;
+ assign T_202 = 1'h1 == 1'h1;
+ assign T_203 = 1'h0 ? T_202 : T_196;
+ assign T_204 = T_203 & io_out_ready;
+ assign T_207 = io_in_0_valid ? 1'h0 : 1'h1;
+ assign T_209 = 1'h1 > T_167;
+ assign T_210 = io_in_1_valid & T_209;
+ assign T_212 = T_210 ? 1'h1 : T_207;
+ assign T_213 = 1'h0 ? 1'h1 : T_212;
+ assign T_214 = io_out_ready & io_out_valid;
+ assign GEN_5 = 1'h1 == T_130;
+ assign GEN_6 = 1'h1 == T_130;
+ assign GEN_7 = 1'h1 == T_130;
+ assign GEN_8 = 1'h1 == T_130;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_167 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ T_167 <= 1'h0;
+ end else begin
+ if(T_214) begin
+ T_167 <= T_130;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module SmiArbiter(
+ input clk,
+ input reset,
+ output io_in_0_req_ready,
+ input io_in_0_req_valid,
+ input io_in_0_req_bits_rw,
+ input [11:0] io_in_0_req_bits_addr,
+ input [63:0] io_in_0_req_bits_data,
+ input io_in_0_resp_ready,
+ output io_in_0_resp_valid,
+ output [63:0] io_in_0_resp_bits,
+ output io_in_1_req_ready,
+ input io_in_1_req_valid,
+ input io_in_1_req_bits_rw,
+ input [11:0] io_in_1_req_bits_addr,
+ input [63:0] io_in_1_req_bits_data,
+ input io_in_1_resp_ready,
+ output io_in_1_resp_valid,
+ output [63:0] io_in_1_resp_bits,
+ input io_out_req_ready,
+ output io_out_req_valid,
+ output io_out_req_bits_rw,
+ output [11:0] io_out_req_bits_addr,
+ output [63:0] io_out_req_bits_data,
+ output io_out_resp_ready,
+ input io_out_resp_valid,
+ input [63:0] io_out_resp_bits
+);
+ reg wait_resp;
+ reg choice;
+ wire req_arb_clk;
+ wire req_arb_reset;
+ wire req_arb_io_in_0_ready;
+ wire req_arb_io_in_0_valid;
+ wire req_arb_io_in_0_bits_rw;
+ wire [11:0] req_arb_io_in_0_bits_addr;
+ wire [63:0] req_arb_io_in_0_bits_data;
+ wire req_arb_io_in_1_ready;
+ wire req_arb_io_in_1_valid;
+ wire req_arb_io_in_1_bits_rw;
+ wire [11:0] req_arb_io_in_1_bits_addr;
+ wire [63:0] req_arb_io_in_1_bits_data;
+ wire req_arb_io_out_ready;
+ wire req_arb_io_out_valid;
+ wire req_arb_io_out_bits_rw;
+ wire [11:0] req_arb_io_out_bits_addr;
+ wire [63:0] req_arb_io_out_bits_data;
+ wire req_arb_io_chosen;
+ wire T_313;
+ wire T_314;
+ wire T_316;
+ wire T_317;
+ wire T_318;
+ wire T_320;
+ wire T_323;
+ wire T_324;
+ wire T_326;
+ wire T_327;
+ wire GEN_0;
+ wire GEN_1;
+ RRArbiter_77 req_arb (
+ .clk(req_arb_clk),
+ .reset(req_arb_reset),
+ .io_in_0_ready(req_arb_io_in_0_ready),
+ .io_in_0_valid(req_arb_io_in_0_valid),
+ .io_in_0_bits_rw(req_arb_io_in_0_bits_rw),
+ .io_in_0_bits_addr(req_arb_io_in_0_bits_addr),
+ .io_in_0_bits_data(req_arb_io_in_0_bits_data),
+ .io_in_1_ready(req_arb_io_in_1_ready),
+ .io_in_1_valid(req_arb_io_in_1_valid),
+ .io_in_1_bits_rw(req_arb_io_in_1_bits_rw),
+ .io_in_1_bits_addr(req_arb_io_in_1_bits_addr),
+ .io_in_1_bits_data(req_arb_io_in_1_bits_data),
+ .io_out_ready(req_arb_io_out_ready),
+ .io_out_valid(req_arb_io_out_valid),
+ .io_out_bits_rw(req_arb_io_out_bits_rw),
+ .io_out_bits_addr(req_arb_io_out_bits_addr),
+ .io_out_bits_data(req_arb_io_out_bits_data),
+ .io_chosen(req_arb_io_chosen)
+ );
+ assign io_in_0_req_ready = req_arb_io_in_0_ready;
+ assign io_in_0_resp_valid = T_324;
+ assign io_in_0_resp_bits = io_out_resp_bits;
+ assign io_in_1_req_ready = req_arb_io_in_1_ready;
+ assign io_in_1_resp_valid = T_327;
+ assign io_in_1_resp_bits = io_out_resp_bits;
+ assign io_out_req_valid = T_317;
+ assign io_out_req_bits_rw = req_arb_io_out_bits_rw;
+ assign io_out_req_bits_addr = req_arb_io_out_bits_addr;
+ assign io_out_req_bits_data = req_arb_io_out_bits_data;
+ assign io_out_resp_ready = GEN_0;
+ assign req_arb_clk = clk;
+ assign req_arb_reset = reset;
+ assign req_arb_io_in_0_valid = io_in_0_req_valid;
+ assign req_arb_io_in_0_bits_rw = io_in_0_req_bits_rw;
+ assign req_arb_io_in_0_bits_addr = io_in_0_req_bits_addr;
+ assign req_arb_io_in_0_bits_data = io_in_0_req_bits_data;
+ assign req_arb_io_in_1_valid = io_in_1_req_valid;
+ assign req_arb_io_in_1_bits_rw = io_in_1_req_bits_rw;
+ assign req_arb_io_in_1_bits_addr = io_in_1_req_bits_addr;
+ assign req_arb_io_in_1_bits_data = io_in_1_req_bits_data;
+ assign req_arb_io_out_ready = T_314;
+ assign T_313 = wait_resp == 1'h0;
+ assign T_314 = io_out_req_ready & T_313;
+ assign T_316 = wait_resp == 1'h0;
+ assign T_317 = req_arb_io_out_valid & T_316;
+ assign T_318 = io_out_req_ready & io_out_req_valid;
+ assign T_320 = io_out_resp_ready & io_out_resp_valid;
+ assign T_323 = choice == 1'h0;
+ assign T_324 = io_out_resp_valid & T_323;
+ assign T_326 = choice == 1'h1;
+ assign T_327 = io_out_resp_valid & T_326;
+ assign GEN_0 = GEN_1 ? io_in_1_resp_ready : io_in_0_resp_ready;
+ assign GEN_1 = 1'h1 == choice;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ wait_resp = {1{$random}};
+ choice = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ wait_resp <= 1'h0;
+ end else begin
+ if(T_320) begin
+ wait_resp <= 1'h0;
+ end else begin
+ if(T_318) begin
+ wait_resp <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_318) begin
+ choice <= req_arb_io_chosen;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module SmiIONastiIOConverter(
+ input clk,
+ input reset,
+ output io_nasti_aw_ready,
+ input io_nasti_aw_valid,
+ input [31:0] io_nasti_aw_bits_addr,
+ input [7:0] io_nasti_aw_bits_len,
+ input [2:0] io_nasti_aw_bits_size,
+ input [1:0] io_nasti_aw_bits_burst,
+ input io_nasti_aw_bits_lock,
+ input [3:0] io_nasti_aw_bits_cache,
+ input [2:0] io_nasti_aw_bits_prot,
+ input [3:0] io_nasti_aw_bits_qos,
+ input [3:0] io_nasti_aw_bits_region,
+ input [4:0] io_nasti_aw_bits_id,
+ input io_nasti_aw_bits_user,
+ output io_nasti_w_ready,
+ input io_nasti_w_valid,
+ input [63:0] io_nasti_w_bits_data,
+ input io_nasti_w_bits_last,
+ input [7:0] io_nasti_w_bits_strb,
+ input io_nasti_w_bits_user,
+ input io_nasti_b_ready,
+ output io_nasti_b_valid,
+ output [1:0] io_nasti_b_bits_resp,
+ output [4:0] io_nasti_b_bits_id,
+ output io_nasti_b_bits_user,
+ output io_nasti_ar_ready,
+ input io_nasti_ar_valid,
+ input [31:0] io_nasti_ar_bits_addr,
+ input [7:0] io_nasti_ar_bits_len,
+ input [2:0] io_nasti_ar_bits_size,
+ input [1:0] io_nasti_ar_bits_burst,
+ input io_nasti_ar_bits_lock,
+ input [3:0] io_nasti_ar_bits_cache,
+ input [2:0] io_nasti_ar_bits_prot,
+ input [3:0] io_nasti_ar_bits_qos,
+ input [3:0] io_nasti_ar_bits_region,
+ input [4:0] io_nasti_ar_bits_id,
+ input io_nasti_ar_bits_user,
+ input io_nasti_r_ready,
+ output io_nasti_r_valid,
+ output [1:0] io_nasti_r_bits_resp,
+ output [63:0] io_nasti_r_bits_data,
+ output io_nasti_r_bits_last,
+ output [4:0] io_nasti_r_bits_id,
+ output io_nasti_r_bits_user,
+ input io_smi_req_ready,
+ output io_smi_req_valid,
+ output io_smi_req_bits_rw,
+ output [11:0] io_smi_req_bits_addr,
+ output [63:0] io_smi_req_bits_data,
+ output io_smi_resp_ready,
+ input io_smi_resp_valid,
+ input [63:0] io_smi_resp_bits
+);
+ wire reader_clk;
+ wire reader_reset;
+ wire reader_io_ar_ready;
+ wire reader_io_ar_valid;
+ wire [31:0] reader_io_ar_bits_addr;
+ wire [7:0] reader_io_ar_bits_len;
+ wire [2:0] reader_io_ar_bits_size;
+ wire [1:0] reader_io_ar_bits_burst;
+ wire reader_io_ar_bits_lock;
+ wire [3:0] reader_io_ar_bits_cache;
+ wire [2:0] reader_io_ar_bits_prot;
+ wire [3:0] reader_io_ar_bits_qos;
+ wire [3:0] reader_io_ar_bits_region;
+ wire [4:0] reader_io_ar_bits_id;
+ wire reader_io_ar_bits_user;
+ wire reader_io_r_ready;
+ wire reader_io_r_valid;
+ wire [1:0] reader_io_r_bits_resp;
+ wire [63:0] reader_io_r_bits_data;
+ wire reader_io_r_bits_last;
+ wire [4:0] reader_io_r_bits_id;
+ wire reader_io_r_bits_user;
+ wire reader_io_smi_req_ready;
+ wire reader_io_smi_req_valid;
+ wire reader_io_smi_req_bits_rw;
+ wire [11:0] reader_io_smi_req_bits_addr;
+ wire [63:0] reader_io_smi_req_bits_data;
+ wire reader_io_smi_resp_ready;
+ wire reader_io_smi_resp_valid;
+ wire [63:0] reader_io_smi_resp_bits;
+ wire writer_clk;
+ wire writer_reset;
+ wire writer_io_aw_ready;
+ wire writer_io_aw_valid;
+ wire [31:0] writer_io_aw_bits_addr;
+ wire [7:0] writer_io_aw_bits_len;
+ wire [2:0] writer_io_aw_bits_size;
+ wire [1:0] writer_io_aw_bits_burst;
+ wire writer_io_aw_bits_lock;
+ wire [3:0] writer_io_aw_bits_cache;
+ wire [2:0] writer_io_aw_bits_prot;
+ wire [3:0] writer_io_aw_bits_qos;
+ wire [3:0] writer_io_aw_bits_region;
+ wire [4:0] writer_io_aw_bits_id;
+ wire writer_io_aw_bits_user;
+ wire writer_io_w_ready;
+ wire writer_io_w_valid;
+ wire [63:0] writer_io_w_bits_data;
+ wire writer_io_w_bits_last;
+ wire [7:0] writer_io_w_bits_strb;
+ wire writer_io_w_bits_user;
+ wire writer_io_b_ready;
+ wire writer_io_b_valid;
+ wire [1:0] writer_io_b_bits_resp;
+ wire [4:0] writer_io_b_bits_id;
+ wire writer_io_b_bits_user;
+ wire writer_io_smi_req_ready;
+ wire writer_io_smi_req_valid;
+ wire writer_io_smi_req_bits_rw;
+ wire [11:0] writer_io_smi_req_bits_addr;
+ wire [63:0] writer_io_smi_req_bits_data;
+ wire writer_io_smi_resp_ready;
+ wire writer_io_smi_resp_valid;
+ wire [63:0] writer_io_smi_resp_bits;
+ wire arb_clk;
+ wire arb_reset;
+ wire arb_io_in_0_req_ready;
+ wire arb_io_in_0_req_valid;
+ wire arb_io_in_0_req_bits_rw;
+ wire [11:0] arb_io_in_0_req_bits_addr;
+ wire [63:0] arb_io_in_0_req_bits_data;
+ wire arb_io_in_0_resp_ready;
+ wire arb_io_in_0_resp_valid;
+ wire [63:0] arb_io_in_0_resp_bits;
+ wire arb_io_in_1_req_ready;
+ wire arb_io_in_1_req_valid;
+ wire arb_io_in_1_req_bits_rw;
+ wire [11:0] arb_io_in_1_req_bits_addr;
+ wire [63:0] arb_io_in_1_req_bits_data;
+ wire arb_io_in_1_resp_ready;
+ wire arb_io_in_1_resp_valid;
+ wire [63:0] arb_io_in_1_resp_bits;
+ wire arb_io_out_req_ready;
+ wire arb_io_out_req_valid;
+ wire arb_io_out_req_bits_rw;
+ wire [11:0] arb_io_out_req_bits_addr;
+ wire [63:0] arb_io_out_req_bits_data;
+ wire arb_io_out_resp_ready;
+ wire arb_io_out_resp_valid;
+ wire [63:0] arb_io_out_resp_bits;
+ SmiIONastiReadIOConverter reader (
+ .clk(reader_clk),
+ .reset(reader_reset),
+ .io_ar_ready(reader_io_ar_ready),
+ .io_ar_valid(reader_io_ar_valid),
+ .io_ar_bits_addr(reader_io_ar_bits_addr),
+ .io_ar_bits_len(reader_io_ar_bits_len),
+ .io_ar_bits_size(reader_io_ar_bits_size),
+ .io_ar_bits_burst(reader_io_ar_bits_burst),
+ .io_ar_bits_lock(reader_io_ar_bits_lock),
+ .io_ar_bits_cache(reader_io_ar_bits_cache),
+ .io_ar_bits_prot(reader_io_ar_bits_prot),
+ .io_ar_bits_qos(reader_io_ar_bits_qos),
+ .io_ar_bits_region(reader_io_ar_bits_region),
+ .io_ar_bits_id(reader_io_ar_bits_id),
+ .io_ar_bits_user(reader_io_ar_bits_user),
+ .io_r_ready(reader_io_r_ready),
+ .io_r_valid(reader_io_r_valid),
+ .io_r_bits_resp(reader_io_r_bits_resp),
+ .io_r_bits_data(reader_io_r_bits_data),
+ .io_r_bits_last(reader_io_r_bits_last),
+ .io_r_bits_id(reader_io_r_bits_id),
+ .io_r_bits_user(reader_io_r_bits_user),
+ .io_smi_req_ready(reader_io_smi_req_ready),
+ .io_smi_req_valid(reader_io_smi_req_valid),
+ .io_smi_req_bits_rw(reader_io_smi_req_bits_rw),
+ .io_smi_req_bits_addr(reader_io_smi_req_bits_addr),
+ .io_smi_req_bits_data(reader_io_smi_req_bits_data),
+ .io_smi_resp_ready(reader_io_smi_resp_ready),
+ .io_smi_resp_valid(reader_io_smi_resp_valid),
+ .io_smi_resp_bits(reader_io_smi_resp_bits)
+ );
+ SmiIONastiWriteIOConverter writer (
+ .clk(writer_clk),
+ .reset(writer_reset),
+ .io_aw_ready(writer_io_aw_ready),
+ .io_aw_valid(writer_io_aw_valid),
+ .io_aw_bits_addr(writer_io_aw_bits_addr),
+ .io_aw_bits_len(writer_io_aw_bits_len),
+ .io_aw_bits_size(writer_io_aw_bits_size),
+ .io_aw_bits_burst(writer_io_aw_bits_burst),
+ .io_aw_bits_lock(writer_io_aw_bits_lock),
+ .io_aw_bits_cache(writer_io_aw_bits_cache),
+ .io_aw_bits_prot(writer_io_aw_bits_prot),
+ .io_aw_bits_qos(writer_io_aw_bits_qos),
+ .io_aw_bits_region(writer_io_aw_bits_region),
+ .io_aw_bits_id(writer_io_aw_bits_id),
+ .io_aw_bits_user(writer_io_aw_bits_user),
+ .io_w_ready(writer_io_w_ready),
+ .io_w_valid(writer_io_w_valid),
+ .io_w_bits_data(writer_io_w_bits_data),
+ .io_w_bits_last(writer_io_w_bits_last),
+ .io_w_bits_strb(writer_io_w_bits_strb),
+ .io_w_bits_user(writer_io_w_bits_user),
+ .io_b_ready(writer_io_b_ready),
+ .io_b_valid(writer_io_b_valid),
+ .io_b_bits_resp(writer_io_b_bits_resp),
+ .io_b_bits_id(writer_io_b_bits_id),
+ .io_b_bits_user(writer_io_b_bits_user),
+ .io_smi_req_ready(writer_io_smi_req_ready),
+ .io_smi_req_valid(writer_io_smi_req_valid),
+ .io_smi_req_bits_rw(writer_io_smi_req_bits_rw),
+ .io_smi_req_bits_addr(writer_io_smi_req_bits_addr),
+ .io_smi_req_bits_data(writer_io_smi_req_bits_data),
+ .io_smi_resp_ready(writer_io_smi_resp_ready),
+ .io_smi_resp_valid(writer_io_smi_resp_valid),
+ .io_smi_resp_bits(writer_io_smi_resp_bits)
+ );
+ SmiArbiter arb (
+ .clk(arb_clk),
+ .reset(arb_reset),
+ .io_in_0_req_ready(arb_io_in_0_req_ready),
+ .io_in_0_req_valid(arb_io_in_0_req_valid),
+ .io_in_0_req_bits_rw(arb_io_in_0_req_bits_rw),
+ .io_in_0_req_bits_addr(arb_io_in_0_req_bits_addr),
+ .io_in_0_req_bits_data(arb_io_in_0_req_bits_data),
+ .io_in_0_resp_ready(arb_io_in_0_resp_ready),
+ .io_in_0_resp_valid(arb_io_in_0_resp_valid),
+ .io_in_0_resp_bits(arb_io_in_0_resp_bits),
+ .io_in_1_req_ready(arb_io_in_1_req_ready),
+ .io_in_1_req_valid(arb_io_in_1_req_valid),
+ .io_in_1_req_bits_rw(arb_io_in_1_req_bits_rw),
+ .io_in_1_req_bits_addr(arb_io_in_1_req_bits_addr),
+ .io_in_1_req_bits_data(arb_io_in_1_req_bits_data),
+ .io_in_1_resp_ready(arb_io_in_1_resp_ready),
+ .io_in_1_resp_valid(arb_io_in_1_resp_valid),
+ .io_in_1_resp_bits(arb_io_in_1_resp_bits),
+ .io_out_req_ready(arb_io_out_req_ready),
+ .io_out_req_valid(arb_io_out_req_valid),
+ .io_out_req_bits_rw(arb_io_out_req_bits_rw),
+ .io_out_req_bits_addr(arb_io_out_req_bits_addr),
+ .io_out_req_bits_data(arb_io_out_req_bits_data),
+ .io_out_resp_ready(arb_io_out_resp_ready),
+ .io_out_resp_valid(arb_io_out_resp_valid),
+ .io_out_resp_bits(arb_io_out_resp_bits)
+ );
+ assign io_nasti_aw_ready = writer_io_aw_ready;
+ assign io_nasti_w_ready = writer_io_w_ready;
+ assign io_nasti_b_valid = writer_io_b_valid;
+ assign io_nasti_b_bits_resp = writer_io_b_bits_resp;
+ assign io_nasti_b_bits_id = writer_io_b_bits_id;
+ assign io_nasti_b_bits_user = writer_io_b_bits_user;
+ assign io_nasti_ar_ready = reader_io_ar_ready;
+ assign io_nasti_r_valid = reader_io_r_valid;
+ assign io_nasti_r_bits_resp = reader_io_r_bits_resp;
+ assign io_nasti_r_bits_data = reader_io_r_bits_data;
+ assign io_nasti_r_bits_last = reader_io_r_bits_last;
+ assign io_nasti_r_bits_id = reader_io_r_bits_id;
+ assign io_nasti_r_bits_user = reader_io_r_bits_user;
+ assign io_smi_req_valid = arb_io_out_req_valid;
+ assign io_smi_req_bits_rw = arb_io_out_req_bits_rw;
+ assign io_smi_req_bits_addr = arb_io_out_req_bits_addr;
+ assign io_smi_req_bits_data = arb_io_out_req_bits_data;
+ assign io_smi_resp_ready = arb_io_out_resp_ready;
+ assign reader_clk = clk;
+ assign reader_reset = reset;
+ assign reader_io_ar_valid = io_nasti_ar_valid;
+ assign reader_io_ar_bits_addr = io_nasti_ar_bits_addr;
+ assign reader_io_ar_bits_len = io_nasti_ar_bits_len;
+ assign reader_io_ar_bits_size = io_nasti_ar_bits_size;
+ assign reader_io_ar_bits_burst = io_nasti_ar_bits_burst;
+ assign reader_io_ar_bits_lock = io_nasti_ar_bits_lock;
+ assign reader_io_ar_bits_cache = io_nasti_ar_bits_cache;
+ assign reader_io_ar_bits_prot = io_nasti_ar_bits_prot;
+ assign reader_io_ar_bits_qos = io_nasti_ar_bits_qos;
+ assign reader_io_ar_bits_region = io_nasti_ar_bits_region;
+ assign reader_io_ar_bits_id = io_nasti_ar_bits_id;
+ assign reader_io_ar_bits_user = io_nasti_ar_bits_user;
+ assign reader_io_r_ready = io_nasti_r_ready;
+ assign reader_io_smi_req_ready = arb_io_in_0_req_ready;
+ assign reader_io_smi_resp_valid = arb_io_in_0_resp_valid;
+ assign reader_io_smi_resp_bits = arb_io_in_0_resp_bits;
+ assign writer_clk = clk;
+ assign writer_reset = reset;
+ assign writer_io_aw_valid = io_nasti_aw_valid;
+ assign writer_io_aw_bits_addr = io_nasti_aw_bits_addr;
+ assign writer_io_aw_bits_len = io_nasti_aw_bits_len;
+ assign writer_io_aw_bits_size = io_nasti_aw_bits_size;
+ assign writer_io_aw_bits_burst = io_nasti_aw_bits_burst;
+ assign writer_io_aw_bits_lock = io_nasti_aw_bits_lock;
+ assign writer_io_aw_bits_cache = io_nasti_aw_bits_cache;
+ assign writer_io_aw_bits_prot = io_nasti_aw_bits_prot;
+ assign writer_io_aw_bits_qos = io_nasti_aw_bits_qos;
+ assign writer_io_aw_bits_region = io_nasti_aw_bits_region;
+ assign writer_io_aw_bits_id = io_nasti_aw_bits_id;
+ assign writer_io_aw_bits_user = io_nasti_aw_bits_user;
+ assign writer_io_w_valid = io_nasti_w_valid;
+ assign writer_io_w_bits_data = io_nasti_w_bits_data;
+ assign writer_io_w_bits_last = io_nasti_w_bits_last;
+ assign writer_io_w_bits_strb = io_nasti_w_bits_strb;
+ assign writer_io_w_bits_user = io_nasti_w_bits_user;
+ assign writer_io_b_ready = io_nasti_b_ready;
+ assign writer_io_smi_req_ready = arb_io_in_1_req_ready;
+ assign writer_io_smi_resp_valid = arb_io_in_1_resp_valid;
+ assign writer_io_smi_resp_bits = arb_io_in_1_resp_bits;
+ assign arb_clk = clk;
+ assign arb_reset = reset;
+ assign arb_io_in_0_req_valid = reader_io_smi_req_valid;
+ assign arb_io_in_0_req_bits_rw = reader_io_smi_req_bits_rw;
+ assign arb_io_in_0_req_bits_addr = reader_io_smi_req_bits_addr;
+ assign arb_io_in_0_req_bits_data = reader_io_smi_req_bits_data;
+ assign arb_io_in_0_resp_ready = reader_io_smi_resp_ready;
+ assign arb_io_in_1_req_valid = writer_io_smi_req_valid;
+ assign arb_io_in_1_req_bits_rw = writer_io_smi_req_bits_rw;
+ assign arb_io_in_1_req_bits_addr = writer_io_smi_req_bits_addr;
+ assign arb_io_in_1_req_bits_data = writer_io_smi_req_bits_data;
+ assign arb_io_in_1_resp_ready = writer_io_smi_resp_ready;
+ assign arb_io_out_req_ready = io_smi_req_ready;
+ assign arb_io_out_resp_valid = io_smi_resp_valid;
+ assign arb_io_out_resp_bits = io_smi_resp_bits;
+endmodule
+module SmiIONastiReadIOConverter_79(
+ input clk,
+ input reset,
+ output io_ar_ready,
+ input io_ar_valid,
+ input [31:0] io_ar_bits_addr,
+ input [7:0] io_ar_bits_len,
+ input [2:0] io_ar_bits_size,
+ input [1:0] io_ar_bits_burst,
+ input io_ar_bits_lock,
+ input [3:0] io_ar_bits_cache,
+ input [2:0] io_ar_bits_prot,
+ input [3:0] io_ar_bits_qos,
+ input [3:0] io_ar_bits_region,
+ input [4:0] io_ar_bits_id,
+ input io_ar_bits_user,
+ input io_r_ready,
+ output io_r_valid,
+ output [1:0] io_r_bits_resp,
+ output [63:0] io_r_bits_data,
+ output io_r_bits_last,
+ output [4:0] io_r_bits_id,
+ output io_r_bits_user,
+ input io_smi_req_ready,
+ output io_smi_req_valid,
+ output io_smi_req_bits_rw,
+ output [5:0] io_smi_req_bits_addr,
+ output [63:0] io_smi_req_bits_data,
+ output io_smi_resp_ready,
+ input io_smi_resp_valid,
+ input [63:0] io_smi_resp_bits
+);
+ reg [1:0] state;
+ reg nWords;
+ reg [7:0] nBeats;
+ reg [5:0] addr;
+ reg [4:0] id;
+ reg [2:0] byteOff;
+ reg sendInd;
+ reg recvInd;
+ reg sendDone;
+ wire [63:0] T_141_0;
+ reg [63:0] buffer_0;
+ wire T_149;
+ wire T_150;
+ wire T_152;
+ wire T_153;
+ wire T_155;
+ wire T_156;
+ wire T_158;
+ wire [1:0] T_166_resp;
+ wire [63:0] T_166_data;
+ wire T_166_last;
+ wire [4:0] T_166_id;
+ wire T_166_user;
+ wire T_173;
+ wire T_175;
+ wire [2:0] T_177;
+ wire T_179;
+ wire [3:0] T_182;
+ wire [2:0] T_183;
+ wire [7:0] T_184;
+ wire [8:0] T_186;
+ wire [7:0] T_187;
+ wire [5:0] T_189;
+ wire T_190;
+ wire [6:0] T_192;
+ wire [5:0] T_193;
+ wire [1:0] T_195;
+ wire T_196;
+ wire T_197;
+ wire T_198;
+ wire [1:0] T_200;
+ wire T_201;
+ wire [5:0] T_204;
+ wire [63:0] T_205;
+ wire [63:0] GEN_0;
+ wire T_206;
+ wire T_207;
+ wire [8:0] T_213;
+ wire [7:0] T_214;
+ wire T_215;
+ wire GEN_1;
+ reg [63:0] GEN_2;
+ assign io_ar_ready = T_149;
+ assign io_r_valid = T_156;
+ assign io_r_bits_resp = T_166_resp;
+ assign io_r_bits_data = T_166_data;
+ assign io_r_bits_last = T_166_last;
+ assign io_r_bits_id = T_166_id;
+ assign io_r_bits_user = T_166_user;
+ assign io_smi_req_valid = T_153;
+ assign io_smi_req_bits_rw = 1'h0;
+ assign io_smi_req_bits_addr = addr;
+ assign io_smi_req_bits_data = GEN_2;
+ assign io_smi_resp_ready = T_155;
+ assign T_141_0 = 64'h0;
+ assign T_149 = state == 1'h0;
+ assign T_150 = state == 1'h1;
+ assign T_152 = sendDone == 1'h0;
+ assign T_153 = T_150 & T_152;
+ assign T_155 = state == 1'h1;
+ assign T_156 = state == 2'h2;
+ assign T_158 = nBeats == 1'h0;
+ assign T_166_resp = 1'h0;
+ assign T_166_data = buffer_0;
+ assign T_166_last = T_158;
+ assign T_166_id = id;
+ assign T_166_user = 1'h0;
+ assign T_173 = io_ar_ready & io_ar_valid;
+ assign T_175 = io_ar_bits_size < 2'h3;
+ assign T_177 = io_ar_bits_addr[2:0];
+ assign T_179 = T_175 == 1'h0;
+ assign T_182 = io_ar_bits_size - 2'h3;
+ assign T_183 = T_182[2:0];
+ assign T_184 = 1'h1 << T_183;
+ assign T_186 = T_184 - 1'h1;
+ assign T_187 = T_186[7:0];
+ assign T_189 = io_ar_bits_addr[8:3];
+ assign T_190 = io_smi_req_ready & io_smi_req_valid;
+ assign T_192 = addr + 1'h1;
+ assign T_193 = T_192[5:0];
+ assign T_195 = sendInd + 1'h1;
+ assign T_196 = T_195[0:0];
+ assign T_197 = sendInd == nWords;
+ assign T_198 = io_smi_resp_ready & io_smi_resp_valid;
+ assign T_200 = recvInd + 1'h1;
+ assign T_201 = T_200[0:0];
+ assign T_204 = {byteOff,3'h0};
+ assign T_205 = io_smi_resp_bits >> T_204;
+ assign GEN_0 = T_205;
+ assign T_206 = recvInd == nWords;
+ assign T_207 = io_r_ready & io_r_valid;
+ assign T_213 = nBeats - 1'h1;
+ assign T_214 = T_213[7:0];
+ assign T_215 = io_r_bits_last ? 1'h0 : 1'h1;
+ assign GEN_1 = 1'h0 == recvInd;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ state = {1{$random}};
+ nWords = {1{$random}};
+ nBeats = {1{$random}};
+ addr = {1{$random}};
+ id = {1{$random}};
+ byteOff = {1{$random}};
+ sendInd = {1{$random}};
+ recvInd = {1{$random}};
+ sendDone = {1{$random}};
+ buffer_0 = {2{$random}};
+ GEN_2 = {2{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ state <= 1'h0;
+ end else begin
+ if(T_207) begin
+ state <= T_215;
+ end else begin
+ if(T_198) begin
+ if(T_206) begin
+ state <= 2'h2;
+ end else begin
+ if(T_173) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_173) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_173) begin
+ if(T_179) begin
+ nWords <= T_187;
+ end else begin
+ if(T_175) begin
+ nWords <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_207) begin
+ nBeats <= T_214;
+ end else begin
+ if(T_173) begin
+ nBeats <= io_ar_bits_len;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_190) begin
+ addr <= T_193;
+ end else begin
+ if(T_173) begin
+ addr <= T_189;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_173) begin
+ id <= io_ar_bits_id;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_173) begin
+ if(T_179) begin
+ byteOff <= 1'h0;
+ end else begin
+ if(T_175) begin
+ byteOff <= T_177;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ sendInd <= 1'h0;
+ end else begin
+ if(T_207) begin
+ sendInd <= 1'h0;
+ end else begin
+ if(T_190) begin
+ sendInd <= T_196;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ recvInd <= 1'h0;
+ end else begin
+ if(T_207) begin
+ recvInd <= 1'h0;
+ end else begin
+ if(T_198) begin
+ recvInd <= T_201;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ sendDone <= 1'h0;
+ end else begin
+ if(T_207) begin
+ sendDone <= 1'h0;
+ end else begin
+ if(T_190) begin
+ sendDone <= T_197;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ buffer_0 <= T_141_0;
+ end else begin
+ if(T_207) begin
+ buffer_0 <= 1'h0;
+ end else begin
+ if(T_198) begin
+ if(GEN_1) begin
+ buffer_0 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+endmodule
+module SmiIONastiWriteIOConverter_80(
+ input clk,
+ input reset,
+ output io_aw_ready,
+ input io_aw_valid,
+ input [31:0] io_aw_bits_addr,
+ input [7:0] io_aw_bits_len,
+ input [2:0] io_aw_bits_size,
+ input [1:0] io_aw_bits_burst,
+ input io_aw_bits_lock,
+ input [3:0] io_aw_bits_cache,
+ input [2:0] io_aw_bits_prot,
+ input [3:0] io_aw_bits_qos,
+ input [3:0] io_aw_bits_region,
+ input [4:0] io_aw_bits_id,
+ input io_aw_bits_user,
+ output io_w_ready,
+ input io_w_valid,
+ input [63:0] io_w_bits_data,
+ input io_w_bits_last,
+ input [7:0] io_w_bits_strb,
+ input io_w_bits_user,
+ input io_b_ready,
+ output io_b_valid,
+ output [1:0] io_b_bits_resp,
+ output [4:0] io_b_bits_id,
+ output io_b_bits_user,
+ input io_smi_req_ready,
+ output io_smi_req_valid,
+ output io_smi_req_bits_rw,
+ output [5:0] io_smi_req_bits_addr,
+ output [63:0] io_smi_req_bits_data,
+ output io_smi_resp_ready,
+ input io_smi_resp_valid,
+ input [63:0] io_smi_resp_bits
+);
+ wire T_144;
+ wire T_146;
+ wire T_147;
+ wire T_149;
+ wire T_151;
+ wire T_153;
+ reg [4:0] id;
+ reg [5:0] addr;
+ reg [2:0] size;
+ reg strb;
+ reg [63:0] data;
+ reg last;
+ reg [2:0] state;
+ wire T_173;
+ wire T_174;
+ wire T_175;
+ wire T_176;
+ wire T_177;
+ wire [63:0] T_179;
+ wire T_180;
+ wire T_181;
+ wire [1:0] T_187_resp;
+ wire [4:0] T_187_id;
+ wire T_187_user;
+ wire T_193;
+ wire [5:0] T_194;
+ wire T_196;
+ wire [7:0] T_199;
+ wire [255:0] T_200;
+ wire [256:0] T_202;
+ wire [255:0] T_203;
+ wire [255:0] T_204;
+ wire T_205;
+ wire T_207_0;
+ wire T_210;
+ wire T_212;
+ wire [1:0] T_213;
+ wire T_214;
+ wire T_216;
+ wire T_217;
+ wire T_219;
+ wire T_220;
+ wire T_221;
+ wire [6:0] T_223;
+ wire [63:0] T_224;
+ wire [6:0] T_225;
+ wire [5:0] T_226;
+ wire T_227;
+ wire T_228;
+ wire GEN_0;
+ assign io_aw_ready = T_173;
+ assign io_w_ready = T_174;
+ assign io_b_valid = T_181;
+ assign io_b_bits_resp = T_187_resp;
+ assign io_b_bits_id = T_187_id;
+ assign io_b_bits_user = T_187_user;
+ assign io_smi_req_valid = T_177;
+ assign io_smi_req_bits_rw = 1'h1;
+ assign io_smi_req_bits_addr = addr;
+ assign io_smi_req_bits_data = T_179;
+ assign io_smi_resp_ready = T_180;
+ assign T_144 = io_aw_valid == 1'h0;
+ assign T_146 = io_aw_bits_size >= 2'h3;
+ assign T_147 = T_144 | T_146;
+ assign T_149 = reset == 1'h0;
+ assign T_151 = T_147 == 1'h0;
+ assign T_153 = reset == 1'h0;
+ assign T_173 = state == 1'h0;
+ assign T_174 = state == 1'h1;
+ assign T_175 = state == 2'h2;
+ assign T_176 = strb;
+ assign T_177 = T_175 & T_176;
+ assign T_179 = data;
+ assign T_180 = state == 2'h3;
+ assign T_181 = state == 3'h4;
+ assign T_187_resp = 1'h0;
+ assign T_187_id = id;
+ assign T_187_user = 1'h0;
+ assign T_193 = io_aw_ready & io_aw_valid;
+ assign T_194 = io_aw_bits_addr[8:3];
+ assign T_196 = io_w_ready & io_w_valid;
+ assign T_199 = 1'h1 << size;
+ assign T_200 = 1'h1 << T_199;
+ assign T_202 = T_200 - 1'h1;
+ assign T_203 = T_202[255:0];
+ assign T_204 = T_203 & io_w_bits_strb;
+ assign T_205 = T_204[0];
+ assign T_207_0 = T_205;
+ assign T_210 = state == 2'h2;
+ assign T_212 = strb == 1'h0;
+ assign T_213 = last ? 2'h3 : 1'h1;
+ assign T_214 = strb;
+ assign T_216 = T_214 == 1'h0;
+ assign T_217 = io_smi_req_ready | T_216;
+ assign T_219 = T_212 == 1'h0;
+ assign T_220 = T_219 & T_217;
+ assign T_221 = strb >> 1'h1;
+ assign T_223 = {1'h1,6'h0};
+ assign T_224 = data >> T_223;
+ assign T_225 = addr + 1'h1;
+ assign T_226 = T_225[5:0];
+ assign T_227 = io_smi_resp_ready & io_smi_resp_valid;
+ assign T_228 = io_b_ready & io_b_valid;
+ assign GEN_0 = T_149 & T_151;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ id = {1{$random}};
+ addr = {1{$random}};
+ size = {1{$random}};
+ strb = {1{$random}};
+ data = {2{$random}};
+ last = {1{$random}};
+ state = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_193) begin
+ id <= io_aw_bits_id;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_210) begin
+ if(T_220) begin
+ addr <= T_226;
+ end else begin
+ if(T_193) begin
+ addr <= T_194;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_193) begin
+ addr <= T_194;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_193) begin
+ size <= io_aw_bits_size;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_210) begin
+ if(T_220) begin
+ strb <= T_221;
+ end else begin
+ if(T_196) begin
+ strb <= T_207_0;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_196) begin
+ strb <= T_207_0;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_210) begin
+ if(T_220) begin
+ data <= T_224;
+ end else begin
+ if(T_196) begin
+ data <= io_w_bits_data;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_196) begin
+ data <= io_w_bits_data;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_196) begin
+ last <= io_w_bits_last;
+ end else begin
+ if(T_193) begin
+ last <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ state <= 1'h0;
+ end else begin
+ if(T_228) begin
+ state <= 1'h0;
+ end else begin
+ if(T_227) begin
+ state <= 3'h4;
+ end else begin
+ if(T_210) begin
+ if(T_212) begin
+ state <= T_213;
+ end else begin
+ if(T_196) begin
+ state <= 2'h2;
+ end else begin
+ if(T_193) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_196) begin
+ state <= 2'h2;
+ end else begin
+ if(T_193) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ `ifndef SYNTHESIS
+ if(GEN_0 & T_153) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Nasti size must be >= Smi size");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_149 & T_151) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ end
+endmodule
+module RRArbiter_82(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input io_in_0_bits_rw,
+ input [5:0] io_in_0_bits_addr,
+ input [63:0] io_in_0_bits_data,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input io_in_1_bits_rw,
+ input [5:0] io_in_1_bits_addr,
+ input [63:0] io_in_1_bits_data,
+ input io_out_ready,
+ output io_out_valid,
+ output io_out_bits_rw,
+ output [5:0] io_out_bits_addr,
+ output [63:0] io_out_bits_data,
+ output io_chosen
+);
+ wire T_130;
+ wire GEN_0;
+ wire GEN_1;
+ wire [5:0] GEN_2;
+ wire [63:0] GEN_3;
+ wire GEN_4;
+ reg T_167;
+ wire T_168;
+ wire T_169;
+ wire T_171;
+ wire T_172;
+ wire T_175;
+ wire T_177;
+ wire T_179;
+ wire T_180;
+ wire T_182;
+ wire T_184;
+ wire T_185;
+ wire T_186;
+ wire T_188;
+ wire T_190;
+ wire T_191;
+ wire T_192;
+ wire T_194;
+ wire T_195;
+ wire T_196;
+ wire T_198;
+ wire T_199;
+ wire T_200;
+ wire T_202;
+ wire T_203;
+ wire T_204;
+ wire T_207;
+ wire T_209;
+ wire T_210;
+ wire T_212;
+ wire T_213;
+ wire T_214;
+ wire GEN_5;
+ wire GEN_6;
+ wire GEN_7;
+ wire GEN_8;
+ assign io_in_0_ready = T_200;
+ assign io_in_1_ready = T_204;
+ assign io_out_valid = GEN_0;
+ assign io_out_bits_rw = GEN_1;
+ assign io_out_bits_addr = GEN_2;
+ assign io_out_bits_data = GEN_3;
+ assign io_chosen = T_130;
+ assign T_130 = T_213;
+ assign GEN_0 = GEN_5 ? io_in_1_valid : io_in_0_valid;
+ assign GEN_1 = GEN_6 ? io_in_1_bits_rw : io_in_0_bits_rw;
+ assign GEN_2 = GEN_7 ? io_in_1_bits_addr : io_in_0_bits_addr;
+ assign GEN_3 = GEN_8 ? io_in_1_bits_data : io_in_0_bits_data;
+ assign GEN_4 = 1'h0;
+ assign T_168 = 1'h0 > T_167;
+ assign T_169 = io_in_0_valid & T_168;
+ assign T_171 = 1'h1 > T_167;
+ assign T_172 = io_in_1_valid & T_171;
+ assign T_175 = 1'h0 | T_169;
+ assign T_177 = T_175 == 1'h0;
+ assign T_179 = 1'h0 | T_169;
+ assign T_180 = T_179 | T_172;
+ assign T_182 = T_180 == 1'h0;
+ assign T_184 = 1'h0 | T_169;
+ assign T_185 = T_184 | T_172;
+ assign T_186 = T_185 | io_in_0_valid;
+ assign T_188 = T_186 == 1'h0;
+ assign T_190 = 1'h0 > T_167;
+ assign T_191 = 1'h1 & T_190;
+ assign T_192 = T_191 | T_182;
+ assign T_194 = 1'h1 > T_167;
+ assign T_195 = T_177 & T_194;
+ assign T_196 = T_195 | T_188;
+ assign T_198 = 1'h1 == 1'h0;
+ assign T_199 = 1'h0 ? T_198 : T_192;
+ assign T_200 = T_199 & io_out_ready;
+ assign T_202 = 1'h1 == 1'h1;
+ assign T_203 = 1'h0 ? T_202 : T_196;
+ assign T_204 = T_203 & io_out_ready;
+ assign T_207 = io_in_0_valid ? 1'h0 : 1'h1;
+ assign T_209 = 1'h1 > T_167;
+ assign T_210 = io_in_1_valid & T_209;
+ assign T_212 = T_210 ? 1'h1 : T_207;
+ assign T_213 = 1'h0 ? 1'h1 : T_212;
+ assign T_214 = io_out_ready & io_out_valid;
+ assign GEN_5 = 1'h1 == T_130;
+ assign GEN_6 = 1'h1 == T_130;
+ assign GEN_7 = 1'h1 == T_130;
+ assign GEN_8 = 1'h1 == T_130;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_167 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ T_167 <= 1'h0;
+ end else begin
+ if(T_214) begin
+ T_167 <= T_130;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module SmiArbiter_81(
+ input clk,
+ input reset,
+ output io_in_0_req_ready,
+ input io_in_0_req_valid,
+ input io_in_0_req_bits_rw,
+ input [5:0] io_in_0_req_bits_addr,
+ input [63:0] io_in_0_req_bits_data,
+ input io_in_0_resp_ready,
+ output io_in_0_resp_valid,
+ output [63:0] io_in_0_resp_bits,
+ output io_in_1_req_ready,
+ input io_in_1_req_valid,
+ input io_in_1_req_bits_rw,
+ input [5:0] io_in_1_req_bits_addr,
+ input [63:0] io_in_1_req_bits_data,
+ input io_in_1_resp_ready,
+ output io_in_1_resp_valid,
+ output [63:0] io_in_1_resp_bits,
+ input io_out_req_ready,
+ output io_out_req_valid,
+ output io_out_req_bits_rw,
+ output [5:0] io_out_req_bits_addr,
+ output [63:0] io_out_req_bits_data,
+ output io_out_resp_ready,
+ input io_out_resp_valid,
+ input [63:0] io_out_resp_bits
+);
+ reg wait_resp;
+ reg choice;
+ wire req_arb_clk;
+ wire req_arb_reset;
+ wire req_arb_io_in_0_ready;
+ wire req_arb_io_in_0_valid;
+ wire req_arb_io_in_0_bits_rw;
+ wire [5:0] req_arb_io_in_0_bits_addr;
+ wire [63:0] req_arb_io_in_0_bits_data;
+ wire req_arb_io_in_1_ready;
+ wire req_arb_io_in_1_valid;
+ wire req_arb_io_in_1_bits_rw;
+ wire [5:0] req_arb_io_in_1_bits_addr;
+ wire [63:0] req_arb_io_in_1_bits_data;
+ wire req_arb_io_out_ready;
+ wire req_arb_io_out_valid;
+ wire req_arb_io_out_bits_rw;
+ wire [5:0] req_arb_io_out_bits_addr;
+ wire [63:0] req_arb_io_out_bits_data;
+ wire req_arb_io_chosen;
+ wire T_313;
+ wire T_314;
+ wire T_316;
+ wire T_317;
+ wire T_318;
+ wire T_320;
+ wire T_323;
+ wire T_324;
+ wire T_326;
+ wire T_327;
+ wire GEN_0;
+ wire GEN_1;
+ RRArbiter_82 req_arb (
+ .clk(req_arb_clk),
+ .reset(req_arb_reset),
+ .io_in_0_ready(req_arb_io_in_0_ready),
+ .io_in_0_valid(req_arb_io_in_0_valid),
+ .io_in_0_bits_rw(req_arb_io_in_0_bits_rw),
+ .io_in_0_bits_addr(req_arb_io_in_0_bits_addr),
+ .io_in_0_bits_data(req_arb_io_in_0_bits_data),
+ .io_in_1_ready(req_arb_io_in_1_ready),
+ .io_in_1_valid(req_arb_io_in_1_valid),
+ .io_in_1_bits_rw(req_arb_io_in_1_bits_rw),
+ .io_in_1_bits_addr(req_arb_io_in_1_bits_addr),
+ .io_in_1_bits_data(req_arb_io_in_1_bits_data),
+ .io_out_ready(req_arb_io_out_ready),
+ .io_out_valid(req_arb_io_out_valid),
+ .io_out_bits_rw(req_arb_io_out_bits_rw),
+ .io_out_bits_addr(req_arb_io_out_bits_addr),
+ .io_out_bits_data(req_arb_io_out_bits_data),
+ .io_chosen(req_arb_io_chosen)
+ );
+ assign io_in_0_req_ready = req_arb_io_in_0_ready;
+ assign io_in_0_resp_valid = T_324;
+ assign io_in_0_resp_bits = io_out_resp_bits;
+ assign io_in_1_req_ready = req_arb_io_in_1_ready;
+ assign io_in_1_resp_valid = T_327;
+ assign io_in_1_resp_bits = io_out_resp_bits;
+ assign io_out_req_valid = T_317;
+ assign io_out_req_bits_rw = req_arb_io_out_bits_rw;
+ assign io_out_req_bits_addr = req_arb_io_out_bits_addr;
+ assign io_out_req_bits_data = req_arb_io_out_bits_data;
+ assign io_out_resp_ready = GEN_0;
+ assign req_arb_clk = clk;
+ assign req_arb_reset = reset;
+ assign req_arb_io_in_0_valid = io_in_0_req_valid;
+ assign req_arb_io_in_0_bits_rw = io_in_0_req_bits_rw;
+ assign req_arb_io_in_0_bits_addr = io_in_0_req_bits_addr;
+ assign req_arb_io_in_0_bits_data = io_in_0_req_bits_data;
+ assign req_arb_io_in_1_valid = io_in_1_req_valid;
+ assign req_arb_io_in_1_bits_rw = io_in_1_req_bits_rw;
+ assign req_arb_io_in_1_bits_addr = io_in_1_req_bits_addr;
+ assign req_arb_io_in_1_bits_data = io_in_1_req_bits_data;
+ assign req_arb_io_out_ready = T_314;
+ assign T_313 = wait_resp == 1'h0;
+ assign T_314 = io_out_req_ready & T_313;
+ assign T_316 = wait_resp == 1'h0;
+ assign T_317 = req_arb_io_out_valid & T_316;
+ assign T_318 = io_out_req_ready & io_out_req_valid;
+ assign T_320 = io_out_resp_ready & io_out_resp_valid;
+ assign T_323 = choice == 1'h0;
+ assign T_324 = io_out_resp_valid & T_323;
+ assign T_326 = choice == 1'h1;
+ assign T_327 = io_out_resp_valid & T_326;
+ assign GEN_0 = GEN_1 ? io_in_1_resp_ready : io_in_0_resp_ready;
+ assign GEN_1 = 1'h1 == choice;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ wait_resp = {1{$random}};
+ choice = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ wait_resp <= 1'h0;
+ end else begin
+ if(T_320) begin
+ wait_resp <= 1'h0;
+ end else begin
+ if(T_318) begin
+ wait_resp <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_318) begin
+ choice <= req_arb_io_chosen;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module SmiIONastiIOConverter_78(
+ input clk,
+ input reset,
+ output io_nasti_aw_ready,
+ input io_nasti_aw_valid,
+ input [31:0] io_nasti_aw_bits_addr,
+ input [7:0] io_nasti_aw_bits_len,
+ input [2:0] io_nasti_aw_bits_size,
+ input [1:0] io_nasti_aw_bits_burst,
+ input io_nasti_aw_bits_lock,
+ input [3:0] io_nasti_aw_bits_cache,
+ input [2:0] io_nasti_aw_bits_prot,
+ input [3:0] io_nasti_aw_bits_qos,
+ input [3:0] io_nasti_aw_bits_region,
+ input [4:0] io_nasti_aw_bits_id,
+ input io_nasti_aw_bits_user,
+ output io_nasti_w_ready,
+ input io_nasti_w_valid,
+ input [63:0] io_nasti_w_bits_data,
+ input io_nasti_w_bits_last,
+ input [7:0] io_nasti_w_bits_strb,
+ input io_nasti_w_bits_user,
+ input io_nasti_b_ready,
+ output io_nasti_b_valid,
+ output [1:0] io_nasti_b_bits_resp,
+ output [4:0] io_nasti_b_bits_id,
+ output io_nasti_b_bits_user,
+ output io_nasti_ar_ready,
+ input io_nasti_ar_valid,
+ input [31:0] io_nasti_ar_bits_addr,
+ input [7:0] io_nasti_ar_bits_len,
+ input [2:0] io_nasti_ar_bits_size,
+ input [1:0] io_nasti_ar_bits_burst,
+ input io_nasti_ar_bits_lock,
+ input [3:0] io_nasti_ar_bits_cache,
+ input [2:0] io_nasti_ar_bits_prot,
+ input [3:0] io_nasti_ar_bits_qos,
+ input [3:0] io_nasti_ar_bits_region,
+ input [4:0] io_nasti_ar_bits_id,
+ input io_nasti_ar_bits_user,
+ input io_nasti_r_ready,
+ output io_nasti_r_valid,
+ output [1:0] io_nasti_r_bits_resp,
+ output [63:0] io_nasti_r_bits_data,
+ output io_nasti_r_bits_last,
+ output [4:0] io_nasti_r_bits_id,
+ output io_nasti_r_bits_user,
+ input io_smi_req_ready,
+ output io_smi_req_valid,
+ output io_smi_req_bits_rw,
+ output [5:0] io_smi_req_bits_addr,
+ output [63:0] io_smi_req_bits_data,
+ output io_smi_resp_ready,
+ input io_smi_resp_valid,
+ input [63:0] io_smi_resp_bits
+);
+ wire reader_clk;
+ wire reader_reset;
+ wire reader_io_ar_ready;
+ wire reader_io_ar_valid;
+ wire [31:0] reader_io_ar_bits_addr;
+ wire [7:0] reader_io_ar_bits_len;
+ wire [2:0] reader_io_ar_bits_size;
+ wire [1:0] reader_io_ar_bits_burst;
+ wire reader_io_ar_bits_lock;
+ wire [3:0] reader_io_ar_bits_cache;
+ wire [2:0] reader_io_ar_bits_prot;
+ wire [3:0] reader_io_ar_bits_qos;
+ wire [3:0] reader_io_ar_bits_region;
+ wire [4:0] reader_io_ar_bits_id;
+ wire reader_io_ar_bits_user;
+ wire reader_io_r_ready;
+ wire reader_io_r_valid;
+ wire [1:0] reader_io_r_bits_resp;
+ wire [63:0] reader_io_r_bits_data;
+ wire reader_io_r_bits_last;
+ wire [4:0] reader_io_r_bits_id;
+ wire reader_io_r_bits_user;
+ wire reader_io_smi_req_ready;
+ wire reader_io_smi_req_valid;
+ wire reader_io_smi_req_bits_rw;
+ wire [5:0] reader_io_smi_req_bits_addr;
+ wire [63:0] reader_io_smi_req_bits_data;
+ wire reader_io_smi_resp_ready;
+ wire reader_io_smi_resp_valid;
+ wire [63:0] reader_io_smi_resp_bits;
+ wire writer_clk;
+ wire writer_reset;
+ wire writer_io_aw_ready;
+ wire writer_io_aw_valid;
+ wire [31:0] writer_io_aw_bits_addr;
+ wire [7:0] writer_io_aw_bits_len;
+ wire [2:0] writer_io_aw_bits_size;
+ wire [1:0] writer_io_aw_bits_burst;
+ wire writer_io_aw_bits_lock;
+ wire [3:0] writer_io_aw_bits_cache;
+ wire [2:0] writer_io_aw_bits_prot;
+ wire [3:0] writer_io_aw_bits_qos;
+ wire [3:0] writer_io_aw_bits_region;
+ wire [4:0] writer_io_aw_bits_id;
+ wire writer_io_aw_bits_user;
+ wire writer_io_w_ready;
+ wire writer_io_w_valid;
+ wire [63:0] writer_io_w_bits_data;
+ wire writer_io_w_bits_last;
+ wire [7:0] writer_io_w_bits_strb;
+ wire writer_io_w_bits_user;
+ wire writer_io_b_ready;
+ wire writer_io_b_valid;
+ wire [1:0] writer_io_b_bits_resp;
+ wire [4:0] writer_io_b_bits_id;
+ wire writer_io_b_bits_user;
+ wire writer_io_smi_req_ready;
+ wire writer_io_smi_req_valid;
+ wire writer_io_smi_req_bits_rw;
+ wire [5:0] writer_io_smi_req_bits_addr;
+ wire [63:0] writer_io_smi_req_bits_data;
+ wire writer_io_smi_resp_ready;
+ wire writer_io_smi_resp_valid;
+ wire [63:0] writer_io_smi_resp_bits;
+ wire arb_clk;
+ wire arb_reset;
+ wire arb_io_in_0_req_ready;
+ wire arb_io_in_0_req_valid;
+ wire arb_io_in_0_req_bits_rw;
+ wire [5:0] arb_io_in_0_req_bits_addr;
+ wire [63:0] arb_io_in_0_req_bits_data;
+ wire arb_io_in_0_resp_ready;
+ wire arb_io_in_0_resp_valid;
+ wire [63:0] arb_io_in_0_resp_bits;
+ wire arb_io_in_1_req_ready;
+ wire arb_io_in_1_req_valid;
+ wire arb_io_in_1_req_bits_rw;
+ wire [5:0] arb_io_in_1_req_bits_addr;
+ wire [63:0] arb_io_in_1_req_bits_data;
+ wire arb_io_in_1_resp_ready;
+ wire arb_io_in_1_resp_valid;
+ wire [63:0] arb_io_in_1_resp_bits;
+ wire arb_io_out_req_ready;
+ wire arb_io_out_req_valid;
+ wire arb_io_out_req_bits_rw;
+ wire [5:0] arb_io_out_req_bits_addr;
+ wire [63:0] arb_io_out_req_bits_data;
+ wire arb_io_out_resp_ready;
+ wire arb_io_out_resp_valid;
+ wire [63:0] arb_io_out_resp_bits;
+ SmiIONastiReadIOConverter_79 reader (
+ .clk(reader_clk),
+ .reset(reader_reset),
+ .io_ar_ready(reader_io_ar_ready),
+ .io_ar_valid(reader_io_ar_valid),
+ .io_ar_bits_addr(reader_io_ar_bits_addr),
+ .io_ar_bits_len(reader_io_ar_bits_len),
+ .io_ar_bits_size(reader_io_ar_bits_size),
+ .io_ar_bits_burst(reader_io_ar_bits_burst),
+ .io_ar_bits_lock(reader_io_ar_bits_lock),
+ .io_ar_bits_cache(reader_io_ar_bits_cache),
+ .io_ar_bits_prot(reader_io_ar_bits_prot),
+ .io_ar_bits_qos(reader_io_ar_bits_qos),
+ .io_ar_bits_region(reader_io_ar_bits_region),
+ .io_ar_bits_id(reader_io_ar_bits_id),
+ .io_ar_bits_user(reader_io_ar_bits_user),
+ .io_r_ready(reader_io_r_ready),
+ .io_r_valid(reader_io_r_valid),
+ .io_r_bits_resp(reader_io_r_bits_resp),
+ .io_r_bits_data(reader_io_r_bits_data),
+ .io_r_bits_last(reader_io_r_bits_last),
+ .io_r_bits_id(reader_io_r_bits_id),
+ .io_r_bits_user(reader_io_r_bits_user),
+ .io_smi_req_ready(reader_io_smi_req_ready),
+ .io_smi_req_valid(reader_io_smi_req_valid),
+ .io_smi_req_bits_rw(reader_io_smi_req_bits_rw),
+ .io_smi_req_bits_addr(reader_io_smi_req_bits_addr),
+ .io_smi_req_bits_data(reader_io_smi_req_bits_data),
+ .io_smi_resp_ready(reader_io_smi_resp_ready),
+ .io_smi_resp_valid(reader_io_smi_resp_valid),
+ .io_smi_resp_bits(reader_io_smi_resp_bits)
+ );
+ SmiIONastiWriteIOConverter_80 writer (
+ .clk(writer_clk),
+ .reset(writer_reset),
+ .io_aw_ready(writer_io_aw_ready),
+ .io_aw_valid(writer_io_aw_valid),
+ .io_aw_bits_addr(writer_io_aw_bits_addr),
+ .io_aw_bits_len(writer_io_aw_bits_len),
+ .io_aw_bits_size(writer_io_aw_bits_size),
+ .io_aw_bits_burst(writer_io_aw_bits_burst),
+ .io_aw_bits_lock(writer_io_aw_bits_lock),
+ .io_aw_bits_cache(writer_io_aw_bits_cache),
+ .io_aw_bits_prot(writer_io_aw_bits_prot),
+ .io_aw_bits_qos(writer_io_aw_bits_qos),
+ .io_aw_bits_region(writer_io_aw_bits_region),
+ .io_aw_bits_id(writer_io_aw_bits_id),
+ .io_aw_bits_user(writer_io_aw_bits_user),
+ .io_w_ready(writer_io_w_ready),
+ .io_w_valid(writer_io_w_valid),
+ .io_w_bits_data(writer_io_w_bits_data),
+ .io_w_bits_last(writer_io_w_bits_last),
+ .io_w_bits_strb(writer_io_w_bits_strb),
+ .io_w_bits_user(writer_io_w_bits_user),
+ .io_b_ready(writer_io_b_ready),
+ .io_b_valid(writer_io_b_valid),
+ .io_b_bits_resp(writer_io_b_bits_resp),
+ .io_b_bits_id(writer_io_b_bits_id),
+ .io_b_bits_user(writer_io_b_bits_user),
+ .io_smi_req_ready(writer_io_smi_req_ready),
+ .io_smi_req_valid(writer_io_smi_req_valid),
+ .io_smi_req_bits_rw(writer_io_smi_req_bits_rw),
+ .io_smi_req_bits_addr(writer_io_smi_req_bits_addr),
+ .io_smi_req_bits_data(writer_io_smi_req_bits_data),
+ .io_smi_resp_ready(writer_io_smi_resp_ready),
+ .io_smi_resp_valid(writer_io_smi_resp_valid),
+ .io_smi_resp_bits(writer_io_smi_resp_bits)
+ );
+ SmiArbiter_81 arb (
+ .clk(arb_clk),
+ .reset(arb_reset),
+ .io_in_0_req_ready(arb_io_in_0_req_ready),
+ .io_in_0_req_valid(arb_io_in_0_req_valid),
+ .io_in_0_req_bits_rw(arb_io_in_0_req_bits_rw),
+ .io_in_0_req_bits_addr(arb_io_in_0_req_bits_addr),
+ .io_in_0_req_bits_data(arb_io_in_0_req_bits_data),
+ .io_in_0_resp_ready(arb_io_in_0_resp_ready),
+ .io_in_0_resp_valid(arb_io_in_0_resp_valid),
+ .io_in_0_resp_bits(arb_io_in_0_resp_bits),
+ .io_in_1_req_ready(arb_io_in_1_req_ready),
+ .io_in_1_req_valid(arb_io_in_1_req_valid),
+ .io_in_1_req_bits_rw(arb_io_in_1_req_bits_rw),
+ .io_in_1_req_bits_addr(arb_io_in_1_req_bits_addr),
+ .io_in_1_req_bits_data(arb_io_in_1_req_bits_data),
+ .io_in_1_resp_ready(arb_io_in_1_resp_ready),
+ .io_in_1_resp_valid(arb_io_in_1_resp_valid),
+ .io_in_1_resp_bits(arb_io_in_1_resp_bits),
+ .io_out_req_ready(arb_io_out_req_ready),
+ .io_out_req_valid(arb_io_out_req_valid),
+ .io_out_req_bits_rw(arb_io_out_req_bits_rw),
+ .io_out_req_bits_addr(arb_io_out_req_bits_addr),
+ .io_out_req_bits_data(arb_io_out_req_bits_data),
+ .io_out_resp_ready(arb_io_out_resp_ready),
+ .io_out_resp_valid(arb_io_out_resp_valid),
+ .io_out_resp_bits(arb_io_out_resp_bits)
+ );
+ assign io_nasti_aw_ready = writer_io_aw_ready;
+ assign io_nasti_w_ready = writer_io_w_ready;
+ assign io_nasti_b_valid = writer_io_b_valid;
+ assign io_nasti_b_bits_resp = writer_io_b_bits_resp;
+ assign io_nasti_b_bits_id = writer_io_b_bits_id;
+ assign io_nasti_b_bits_user = writer_io_b_bits_user;
+ assign io_nasti_ar_ready = reader_io_ar_ready;
+ assign io_nasti_r_valid = reader_io_r_valid;
+ assign io_nasti_r_bits_resp = reader_io_r_bits_resp;
+ assign io_nasti_r_bits_data = reader_io_r_bits_data;
+ assign io_nasti_r_bits_last = reader_io_r_bits_last;
+ assign io_nasti_r_bits_id = reader_io_r_bits_id;
+ assign io_nasti_r_bits_user = reader_io_r_bits_user;
+ assign io_smi_req_valid = arb_io_out_req_valid;
+ assign io_smi_req_bits_rw = arb_io_out_req_bits_rw;
+ assign io_smi_req_bits_addr = arb_io_out_req_bits_addr;
+ assign io_smi_req_bits_data = arb_io_out_req_bits_data;
+ assign io_smi_resp_ready = arb_io_out_resp_ready;
+ assign reader_clk = clk;
+ assign reader_reset = reset;
+ assign reader_io_ar_valid = io_nasti_ar_valid;
+ assign reader_io_ar_bits_addr = io_nasti_ar_bits_addr;
+ assign reader_io_ar_bits_len = io_nasti_ar_bits_len;
+ assign reader_io_ar_bits_size = io_nasti_ar_bits_size;
+ assign reader_io_ar_bits_burst = io_nasti_ar_bits_burst;
+ assign reader_io_ar_bits_lock = io_nasti_ar_bits_lock;
+ assign reader_io_ar_bits_cache = io_nasti_ar_bits_cache;
+ assign reader_io_ar_bits_prot = io_nasti_ar_bits_prot;
+ assign reader_io_ar_bits_qos = io_nasti_ar_bits_qos;
+ assign reader_io_ar_bits_region = io_nasti_ar_bits_region;
+ assign reader_io_ar_bits_id = io_nasti_ar_bits_id;
+ assign reader_io_ar_bits_user = io_nasti_ar_bits_user;
+ assign reader_io_r_ready = io_nasti_r_ready;
+ assign reader_io_smi_req_ready = arb_io_in_0_req_ready;
+ assign reader_io_smi_resp_valid = arb_io_in_0_resp_valid;
+ assign reader_io_smi_resp_bits = arb_io_in_0_resp_bits;
+ assign writer_clk = clk;
+ assign writer_reset = reset;
+ assign writer_io_aw_valid = io_nasti_aw_valid;
+ assign writer_io_aw_bits_addr = io_nasti_aw_bits_addr;
+ assign writer_io_aw_bits_len = io_nasti_aw_bits_len;
+ assign writer_io_aw_bits_size = io_nasti_aw_bits_size;
+ assign writer_io_aw_bits_burst = io_nasti_aw_bits_burst;
+ assign writer_io_aw_bits_lock = io_nasti_aw_bits_lock;
+ assign writer_io_aw_bits_cache = io_nasti_aw_bits_cache;
+ assign writer_io_aw_bits_prot = io_nasti_aw_bits_prot;
+ assign writer_io_aw_bits_qos = io_nasti_aw_bits_qos;
+ assign writer_io_aw_bits_region = io_nasti_aw_bits_region;
+ assign writer_io_aw_bits_id = io_nasti_aw_bits_id;
+ assign writer_io_aw_bits_user = io_nasti_aw_bits_user;
+ assign writer_io_w_valid = io_nasti_w_valid;
+ assign writer_io_w_bits_data = io_nasti_w_bits_data;
+ assign writer_io_w_bits_last = io_nasti_w_bits_last;
+ assign writer_io_w_bits_strb = io_nasti_w_bits_strb;
+ assign writer_io_w_bits_user = io_nasti_w_bits_user;
+ assign writer_io_b_ready = io_nasti_b_ready;
+ assign writer_io_smi_req_ready = arb_io_in_1_req_ready;
+ assign writer_io_smi_resp_valid = arb_io_in_1_resp_valid;
+ assign writer_io_smi_resp_bits = arb_io_in_1_resp_bits;
+ assign arb_clk = clk;
+ assign arb_reset = reset;
+ assign arb_io_in_0_req_valid = reader_io_smi_req_valid;
+ assign arb_io_in_0_req_bits_rw = reader_io_smi_req_bits_rw;
+ assign arb_io_in_0_req_bits_addr = reader_io_smi_req_bits_addr;
+ assign arb_io_in_0_req_bits_data = reader_io_smi_req_bits_data;
+ assign arb_io_in_0_resp_ready = reader_io_smi_resp_ready;
+ assign arb_io_in_1_req_valid = writer_io_smi_req_valid;
+ assign arb_io_in_1_req_bits_rw = writer_io_smi_req_bits_rw;
+ assign arb_io_in_1_req_bits_addr = writer_io_smi_req_bits_addr;
+ assign arb_io_in_1_req_bits_data = writer_io_smi_req_bits_data;
+ assign arb_io_in_1_resp_ready = writer_io_smi_resp_ready;
+ assign arb_io_out_req_ready = io_smi_req_ready;
+ assign arb_io_out_resp_valid = io_smi_resp_valid;
+ assign arb_io_out_resp_bits = io_smi_resp_bits;
+endmodule
+module NastiArbiter_83(
+ input clk,
+ input reset,
+ output io_master_0_aw_ready,
+ input io_master_0_aw_valid,
+ input [31:0] io_master_0_aw_bits_addr,
+ input [7:0] io_master_0_aw_bits_len,
+ input [2:0] io_master_0_aw_bits_size,
+ input [1:0] io_master_0_aw_bits_burst,
+ input io_master_0_aw_bits_lock,
+ input [3:0] io_master_0_aw_bits_cache,
+ input [2:0] io_master_0_aw_bits_prot,
+ input [3:0] io_master_0_aw_bits_qos,
+ input [3:0] io_master_0_aw_bits_region,
+ input [4:0] io_master_0_aw_bits_id,
+ input io_master_0_aw_bits_user,
+ output io_master_0_w_ready,
+ input io_master_0_w_valid,
+ input [63:0] io_master_0_w_bits_data,
+ input io_master_0_w_bits_last,
+ input [7:0] io_master_0_w_bits_strb,
+ input io_master_0_w_bits_user,
+ input io_master_0_b_ready,
+ output io_master_0_b_valid,
+ output [1:0] io_master_0_b_bits_resp,
+ output [4:0] io_master_0_b_bits_id,
+ output io_master_0_b_bits_user,
+ output io_master_0_ar_ready,
+ input io_master_0_ar_valid,
+ input [31:0] io_master_0_ar_bits_addr,
+ input [7:0] io_master_0_ar_bits_len,
+ input [2:0] io_master_0_ar_bits_size,
+ input [1:0] io_master_0_ar_bits_burst,
+ input io_master_0_ar_bits_lock,
+ input [3:0] io_master_0_ar_bits_cache,
+ input [2:0] io_master_0_ar_bits_prot,
+ input [3:0] io_master_0_ar_bits_qos,
+ input [3:0] io_master_0_ar_bits_region,
+ input [4:0] io_master_0_ar_bits_id,
+ input io_master_0_ar_bits_user,
+ input io_master_0_r_ready,
+ output io_master_0_r_valid,
+ output [1:0] io_master_0_r_bits_resp,
+ output [63:0] io_master_0_r_bits_data,
+ output io_master_0_r_bits_last,
+ output [4:0] io_master_0_r_bits_id,
+ output io_master_0_r_bits_user,
+ input io_slave_aw_ready,
+ output io_slave_aw_valid,
+ output [31:0] io_slave_aw_bits_addr,
+ output [7:0] io_slave_aw_bits_len,
+ output [2:0] io_slave_aw_bits_size,
+ output [1:0] io_slave_aw_bits_burst,
+ output io_slave_aw_bits_lock,
+ output [3:0] io_slave_aw_bits_cache,
+ output [2:0] io_slave_aw_bits_prot,
+ output [3:0] io_slave_aw_bits_qos,
+ output [3:0] io_slave_aw_bits_region,
+ output [4:0] io_slave_aw_bits_id,
+ output io_slave_aw_bits_user,
+ input io_slave_w_ready,
+ output io_slave_w_valid,
+ output [63:0] io_slave_w_bits_data,
+ output io_slave_w_bits_last,
+ output [7:0] io_slave_w_bits_strb,
+ output io_slave_w_bits_user,
+ output io_slave_b_ready,
+ input io_slave_b_valid,
+ input [1:0] io_slave_b_bits_resp,
+ input [4:0] io_slave_b_bits_id,
+ input io_slave_b_bits_user,
+ input io_slave_ar_ready,
+ output io_slave_ar_valid,
+ output [31:0] io_slave_ar_bits_addr,
+ output [7:0] io_slave_ar_bits_len,
+ output [2:0] io_slave_ar_bits_size,
+ output [1:0] io_slave_ar_bits_burst,
+ output io_slave_ar_bits_lock,
+ output [3:0] io_slave_ar_bits_cache,
+ output [2:0] io_slave_ar_bits_prot,
+ output [3:0] io_slave_ar_bits_qos,
+ output [3:0] io_slave_ar_bits_region,
+ output [4:0] io_slave_ar_bits_id,
+ output io_slave_ar_bits_user,
+ output io_slave_r_ready,
+ input io_slave_r_valid,
+ input [1:0] io_slave_r_bits_resp,
+ input [63:0] io_slave_r_bits_data,
+ input io_slave_r_bits_last,
+ input [4:0] io_slave_r_bits_id,
+ input io_slave_r_bits_user
+);
+ assign io_master_0_aw_ready = io_slave_aw_ready;
+ assign io_master_0_w_ready = io_slave_w_ready;
+ assign io_master_0_b_valid = io_slave_b_valid;
+ assign io_master_0_b_bits_resp = io_slave_b_bits_resp;
+ assign io_master_0_b_bits_id = io_slave_b_bits_id;
+ assign io_master_0_b_bits_user = io_slave_b_bits_user;
+ assign io_master_0_ar_ready = io_slave_ar_ready;
+ assign io_master_0_r_valid = io_slave_r_valid;
+ assign io_master_0_r_bits_resp = io_slave_r_bits_resp;
+ assign io_master_0_r_bits_data = io_slave_r_bits_data;
+ assign io_master_0_r_bits_last = io_slave_r_bits_last;
+ assign io_master_0_r_bits_id = io_slave_r_bits_id;
+ assign io_master_0_r_bits_user = io_slave_r_bits_user;
+ assign io_slave_aw_valid = io_master_0_aw_valid;
+ assign io_slave_aw_bits_addr = io_master_0_aw_bits_addr;
+ assign io_slave_aw_bits_len = io_master_0_aw_bits_len;
+ assign io_slave_aw_bits_size = io_master_0_aw_bits_size;
+ assign io_slave_aw_bits_burst = io_master_0_aw_bits_burst;
+ assign io_slave_aw_bits_lock = io_master_0_aw_bits_lock;
+ assign io_slave_aw_bits_cache = io_master_0_aw_bits_cache;
+ assign io_slave_aw_bits_prot = io_master_0_aw_bits_prot;
+ assign io_slave_aw_bits_qos = io_master_0_aw_bits_qos;
+ assign io_slave_aw_bits_region = io_master_0_aw_bits_region;
+ assign io_slave_aw_bits_id = io_master_0_aw_bits_id;
+ assign io_slave_aw_bits_user = io_master_0_aw_bits_user;
+ assign io_slave_w_valid = io_master_0_w_valid;
+ assign io_slave_w_bits_data = io_master_0_w_bits_data;
+ assign io_slave_w_bits_last = io_master_0_w_bits_last;
+ assign io_slave_w_bits_strb = io_master_0_w_bits_strb;
+ assign io_slave_w_bits_user = io_master_0_w_bits_user;
+ assign io_slave_b_ready = io_master_0_b_ready;
+ assign io_slave_ar_valid = io_master_0_ar_valid;
+ assign io_slave_ar_bits_addr = io_master_0_ar_bits_addr;
+ assign io_slave_ar_bits_len = io_master_0_ar_bits_len;
+ assign io_slave_ar_bits_size = io_master_0_ar_bits_size;
+ assign io_slave_ar_bits_burst = io_master_0_ar_bits_burst;
+ assign io_slave_ar_bits_lock = io_master_0_ar_bits_lock;
+ assign io_slave_ar_bits_cache = io_master_0_ar_bits_cache;
+ assign io_slave_ar_bits_prot = io_master_0_ar_bits_prot;
+ assign io_slave_ar_bits_qos = io_master_0_ar_bits_qos;
+ assign io_slave_ar_bits_region = io_master_0_ar_bits_region;
+ assign io_slave_ar_bits_id = io_master_0_ar_bits_id;
+ assign io_slave_ar_bits_user = io_master_0_ar_bits_user;
+ assign io_slave_r_ready = io_master_0_r_ready;
+endmodule
+module MemIONastiIOConverter(
+ input clk,
+ input reset,
+ output io_nasti_aw_ready,
+ input io_nasti_aw_valid,
+ input [31:0] io_nasti_aw_bits_addr,
+ input [7:0] io_nasti_aw_bits_len,
+ input [2:0] io_nasti_aw_bits_size,
+ input [1:0] io_nasti_aw_bits_burst,
+ input io_nasti_aw_bits_lock,
+ input [3:0] io_nasti_aw_bits_cache,
+ input [2:0] io_nasti_aw_bits_prot,
+ input [3:0] io_nasti_aw_bits_qos,
+ input [3:0] io_nasti_aw_bits_region,
+ input [4:0] io_nasti_aw_bits_id,
+ input io_nasti_aw_bits_user,
+ output io_nasti_w_ready,
+ input io_nasti_w_valid,
+ input [63:0] io_nasti_w_bits_data,
+ input io_nasti_w_bits_last,
+ input [7:0] io_nasti_w_bits_strb,
+ input io_nasti_w_bits_user,
+ input io_nasti_b_ready,
+ output io_nasti_b_valid,
+ output [1:0] io_nasti_b_bits_resp,
+ output [4:0] io_nasti_b_bits_id,
+ output io_nasti_b_bits_user,
+ output io_nasti_ar_ready,
+ input io_nasti_ar_valid,
+ input [31:0] io_nasti_ar_bits_addr,
+ input [7:0] io_nasti_ar_bits_len,
+ input [2:0] io_nasti_ar_bits_size,
+ input [1:0] io_nasti_ar_bits_burst,
+ input io_nasti_ar_bits_lock,
+ input [3:0] io_nasti_ar_bits_cache,
+ input [2:0] io_nasti_ar_bits_prot,
+ input [3:0] io_nasti_ar_bits_qos,
+ input [3:0] io_nasti_ar_bits_region,
+ input [4:0] io_nasti_ar_bits_id,
+ input io_nasti_ar_bits_user,
+ input io_nasti_r_ready,
+ output io_nasti_r_valid,
+ output [1:0] io_nasti_r_bits_resp,
+ output [63:0] io_nasti_r_bits_data,
+ output io_nasti_r_bits_last,
+ output [4:0] io_nasti_r_bits_id,
+ output io_nasti_r_bits_user,
+ input io_mem_req_cmd_ready,
+ output io_mem_req_cmd_valid,
+ output [25:0] io_mem_req_cmd_bits_addr,
+ output [4:0] io_mem_req_cmd_bits_tag,
+ output io_mem_req_cmd_bits_rw,
+ input io_mem_req_data_ready,
+ output io_mem_req_data_valid,
+ output [63:0] io_mem_req_data_bits_data,
+ output io_mem_resp_ready,
+ input io_mem_resp_valid,
+ input [63:0] io_mem_resp_bits_data,
+ input [4:0] io_mem_resp_bits_tag
+);
+ wire T_368;
+ reg [2:0] mif_cnt_out;
+ wire T_372;
+ wire T_374;
+ wire [3:0] T_377;
+ wire [2:0] T_378;
+ wire [2:0] T_379;
+ wire mif_wrap_out;
+ wire T_382;
+ wire T_384;
+ wire T_385;
+ wire T_387;
+ wire T_389;
+ wire T_391;
+ wire T_393;
+ wire T_395;
+ wire T_396;
+ wire T_398;
+ wire T_400;
+ wire T_402;
+ wire T_404;
+ wire T_406;
+ wire T_407;
+ wire T_409;
+ wire T_411;
+ wire T_413;
+ wire T_415;
+ wire T_417;
+ wire T_418;
+ wire T_420;
+ wire T_422;
+ wire T_424;
+ reg b_ok;
+ wire T_427;
+ wire T_429;
+ wire T_430;
+ wire id_q_clk;
+ wire id_q_reset;
+ wire id_q_io_enq_ready;
+ wire id_q_io_enq_valid;
+ wire [4:0] id_q_io_enq_bits;
+ wire id_q_io_deq_ready;
+ wire id_q_io_deq_valid;
+ wire [4:0] id_q_io_deq_bits;
+ wire [1:0] id_q_io_count;
+ wire T_434;
+ wire T_435;
+ wire [31:0] T_436;
+ wire [31:0] T_438;
+ wire [4:0] T_439;
+ wire T_440;
+ wire T_441;
+ wire T_443;
+ wire T_444;
+ wire T_445;
+ wire T_446;
+ wire T_449;
+ wire [7:0] T_450;
+ wire T_452;
+ wire T_453;
+ wire T_455;
+ wire T_457;
+ wire T_459;
+ wire GEN_0;
+ wire GEN_1;
+ wire GEN_2;
+ wire GEN_3;
+ wire GEN_4;
+ reg GEN_5;
+ reg GEN_6;
+ Queue_37 id_q (
+ .clk(id_q_clk),
+ .reset(id_q_reset),
+ .io_enq_ready(id_q_io_enq_ready),
+ .io_enq_valid(id_q_io_enq_valid),
+ .io_enq_bits(id_q_io_enq_bits),
+ .io_deq_ready(id_q_io_deq_ready),
+ .io_deq_valid(id_q_io_deq_valid),
+ .io_deq_bits(id_q_io_deq_bits),
+ .io_count(id_q_io_count)
+ );
+ assign io_nasti_aw_ready = T_445;
+ assign io_nasti_w_ready = io_mem_req_data_ready;
+ assign io_nasti_b_valid = T_446;
+ assign io_nasti_b_bits_resp = 1'h0;
+ assign io_nasti_b_bits_id = id_q_io_deq_bits;
+ assign io_nasti_b_bits_user = GEN_5;
+ assign io_nasti_ar_ready = T_444;
+ assign io_nasti_r_valid = io_mem_resp_valid;
+ assign io_nasti_r_bits_resp = 1'h0;
+ assign io_nasti_r_bits_data = io_mem_resp_bits_data;
+ assign io_nasti_r_bits_last = mif_wrap_out;
+ assign io_nasti_r_bits_id = io_mem_resp_bits_tag;
+ assign io_nasti_r_bits_user = GEN_6;
+ assign io_mem_req_cmd_valid = T_441;
+ assign io_mem_req_cmd_bits_addr = T_438;
+ assign io_mem_req_cmd_bits_tag = T_439;
+ assign io_mem_req_cmd_bits_rw = io_nasti_aw_valid;
+ assign io_mem_req_data_valid = io_nasti_w_valid;
+ assign io_mem_req_data_bits_data = io_nasti_w_bits_data;
+ assign io_mem_resp_ready = io_nasti_r_ready;
+ assign T_368 = io_mem_resp_ready & io_mem_resp_valid;
+ assign T_372 = mif_cnt_out == 3'h7;
+ assign T_374 = 1'h0 & T_372;
+ assign T_377 = mif_cnt_out + 1'h1;
+ assign T_378 = T_377[2:0];
+ assign T_379 = T_374 ? 1'h0 : T_378;
+ assign mif_wrap_out = T_368 & T_372;
+ assign T_382 = io_nasti_aw_valid == 1'h0;
+ assign T_384 = io_nasti_aw_bits_size == 2'h3;
+ assign T_385 = T_382 | T_384;
+ assign T_387 = reset == 1'h0;
+ assign T_389 = T_385 == 1'h0;
+ assign T_391 = reset == 1'h0;
+ assign T_393 = io_nasti_ar_valid == 1'h0;
+ assign T_395 = io_nasti_ar_bits_size == 2'h3;
+ assign T_396 = T_393 | T_395;
+ assign T_398 = reset == 1'h0;
+ assign T_400 = T_396 == 1'h0;
+ assign T_402 = reset == 1'h0;
+ assign T_404 = io_nasti_aw_valid == 1'h0;
+ assign T_406 = io_nasti_aw_bits_len == 3'h7;
+ assign T_407 = T_404 | T_406;
+ assign T_409 = reset == 1'h0;
+ assign T_411 = T_407 == 1'h0;
+ assign T_413 = reset == 1'h0;
+ assign T_415 = io_nasti_ar_valid == 1'h0;
+ assign T_417 = io_nasti_ar_bits_len == 3'h7;
+ assign T_418 = T_415 | T_417;
+ assign T_420 = reset == 1'h0;
+ assign T_422 = T_418 == 1'h0;
+ assign T_424 = reset == 1'h0;
+ assign T_427 = io_nasti_aw_ready & io_nasti_aw_valid;
+ assign T_429 = io_nasti_w_ready & io_nasti_w_valid;
+ assign T_430 = T_429 & io_nasti_w_bits_last;
+ assign id_q_clk = clk;
+ assign id_q_reset = reset;
+ assign id_q_io_enq_valid = T_434;
+ assign id_q_io_enq_bits = io_nasti_aw_bits_id;
+ assign id_q_io_deq_ready = T_435;
+ assign T_434 = io_nasti_aw_valid & io_mem_req_cmd_ready;
+ assign T_435 = io_nasti_b_ready & b_ok;
+ assign T_436 = io_nasti_aw_valid ? io_nasti_aw_bits_addr : io_nasti_ar_bits_addr;
+ assign T_438 = T_436 >> 3'h6;
+ assign T_439 = io_nasti_aw_valid ? io_nasti_aw_bits_id : io_nasti_ar_bits_id;
+ assign T_440 = io_nasti_aw_valid & id_q_io_enq_ready;
+ assign T_441 = T_440 | io_nasti_ar_valid;
+ assign T_443 = io_nasti_aw_valid == 1'h0;
+ assign T_444 = io_mem_req_cmd_ready & T_443;
+ assign T_445 = io_mem_req_cmd_ready & id_q_io_enq_ready;
+ assign T_446 = id_q_io_deq_valid & b_ok;
+ assign T_449 = io_nasti_w_valid == 1'h0;
+ assign T_450 = ~ io_nasti_w_bits_strb;
+ assign T_452 = T_450 == 1'h0;
+ assign T_453 = T_449 | T_452;
+ assign T_455 = reset == 1'h0;
+ assign T_457 = T_453 == 1'h0;
+ assign T_459 = reset == 1'h0;
+ assign GEN_0 = T_387 & T_389;
+ assign GEN_1 = T_398 & T_400;
+ assign GEN_2 = T_409 & T_411;
+ assign GEN_3 = T_420 & T_422;
+ assign GEN_4 = T_455 & T_457;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ mif_cnt_out = {1{$random}};
+ b_ok = {1{$random}};
+ GEN_5 = {1{$random}};
+ GEN_6 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ mif_cnt_out <= 3'h0;
+ end else begin
+ if(T_368) begin
+ mif_cnt_out <= T_379;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ b_ok <= 1'h1;
+ end else begin
+ if(T_430) begin
+ b_ok <= 1'h1;
+ end else begin
+ if(T_427) begin
+ b_ok <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end
+ `ifndef SYNTHESIS
+ if(GEN_0 & T_391) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Nasti data size does not match MemIO data size");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_387 & T_389) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_1 & T_402) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Nasti data size does not match MemIO data size");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_398 & T_400) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_2 & T_413) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Nasti length does not match number of MemIO beats");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_409 & T_411) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_3 & T_424) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Nasti length does not match number of MemIO beats");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_420 & T_422) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_4 & T_459) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): MemIO must write full cache line");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_455 & T_457) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ end
+endmodule
+module MemSerdes(
+ input clk,
+ input reset,
+ output io_wide_req_cmd_ready,
+ input io_wide_req_cmd_valid,
+ input [25:0] io_wide_req_cmd_bits_addr,
+ input [4:0] io_wide_req_cmd_bits_tag,
+ input io_wide_req_cmd_bits_rw,
+ output io_wide_req_data_ready,
+ input io_wide_req_data_valid,
+ input [63:0] io_wide_req_data_bits_data,
+ input io_wide_resp_ready,
+ output io_wide_resp_valid,
+ output [63:0] io_wide_resp_bits_data,
+ output [4:0] io_wide_resp_bits_tag,
+ input io_narrow_req_ready,
+ output io_narrow_req_valid,
+ output [15:0] io_narrow_req_bits,
+ input io_narrow_resp_valid,
+ input [15:0] io_narrow_resp_bits
+);
+ wire [5:0] T_112;
+ wire [31:0] T_113;
+ reg [63:0] out_buf;
+ reg [79:0] in_buf;
+ reg [2:0] state;
+ reg [1:0] send_cnt;
+ reg [2:0] data_send_cnt;
+ wire T_130;
+ wire adone;
+ wire T_133;
+ wire ddone;
+ wire T_135;
+ wire [2:0] T_137;
+ wire [1:0] T_138;
+ wire [63:0] T_140;
+ wire T_141;
+ wire [5:0] T_142;
+ wire [31:0] T_143;
+ wire T_144;
+ wire T_145;
+ wire T_146;
+ wire T_147;
+ wire T_148;
+ wire T_149;
+ wire T_150;
+ wire T_151;
+ wire T_152;
+ wire T_153;
+ wire [1:0] T_154;
+ wire T_155;
+ wire T_156;
+ wire T_158;
+ wire T_159;
+ wire T_161;
+ wire T_162;
+ wire T_163;
+ wire T_164;
+ wire [3:0] T_166;
+ wire [2:0] T_167;
+ wire T_169;
+ wire [1:0] T_170;
+ reg [2:0] recv_cnt;
+ reg [2:0] data_recv_cnt;
+ reg resp_val;
+ wire [3:0] T_180;
+ wire [2:0] T_181;
+ wire T_183;
+ wire [3:0] T_186;
+ wire [2:0] T_187;
+ wire [63:0] T_189;
+ wire [79:0] T_190;
+ wire [63:0] T_194_data;
+ wire [4:0] T_194_tag;
+ wire [4:0] T_197;
+ wire [63:0] T_198;
+ assign io_wide_req_cmd_ready = T_145;
+ assign io_wide_req_data_ready = T_146;
+ assign io_wide_resp_valid = resp_val;
+ assign io_wide_resp_bits_data = T_194_data;
+ assign io_wide_resp_bits_tag = T_194_tag;
+ assign io_narrow_req_valid = T_151;
+ assign io_narrow_req_bits = out_buf;
+ assign T_112 = {io_wide_req_cmd_bits_tag,io_wide_req_cmd_bits_rw};
+ assign T_113 = {io_wide_req_cmd_bits_addr,T_112};
+ assign T_130 = send_cnt == 1'h1;
+ assign adone = io_narrow_req_ready & T_130;
+ assign T_133 = send_cnt == 2'h3;
+ assign ddone = io_narrow_req_ready & T_133;
+ assign T_135 = io_narrow_req_valid & io_narrow_req_ready;
+ assign T_137 = send_cnt + 1'h1;
+ assign T_138 = T_137[1:0];
+ assign T_140 = out_buf >> 5'h10;
+ assign T_141 = io_wide_req_cmd_valid & io_wide_req_cmd_ready;
+ assign T_142 = {io_wide_req_cmd_bits_tag,io_wide_req_cmd_bits_rw};
+ assign T_143 = {io_wide_req_cmd_bits_addr,T_142};
+ assign T_144 = io_wide_req_data_valid & io_wide_req_data_ready;
+ assign T_145 = state == 1'h0;
+ assign T_146 = state == 2'h3;
+ assign T_147 = state == 1'h1;
+ assign T_148 = state == 2'h2;
+ assign T_149 = T_147 | T_148;
+ assign T_150 = state == 3'h4;
+ assign T_151 = T_149 | T_150;
+ assign T_152 = state == 1'h0;
+ assign T_153 = T_152 & io_wide_req_cmd_valid;
+ assign T_154 = io_wide_req_cmd_bits_rw ? 2'h2 : 1'h1;
+ assign T_155 = state == 1'h1;
+ assign T_156 = T_155 & adone;
+ assign T_158 = state == 2'h2;
+ assign T_159 = T_158 & adone;
+ assign T_161 = state == 2'h3;
+ assign T_162 = T_161 & io_wide_req_data_valid;
+ assign T_163 = state == 3'h4;
+ assign T_164 = T_163 & ddone;
+ assign T_166 = data_send_cnt + 1'h1;
+ assign T_167 = T_166[2:0];
+ assign T_169 = data_send_cnt == 3'h7;
+ assign T_170 = T_169 ? 1'h0 : 2'h3;
+ assign T_180 = recv_cnt + 1'h1;
+ assign T_181 = T_180[2:0];
+ assign T_183 = recv_cnt == 3'h4;
+ assign T_186 = data_recv_cnt + 1'h1;
+ assign T_187 = T_186[2:0];
+ assign T_189 = in_buf[79:16];
+ assign T_190 = {io_narrow_resp_bits,T_189};
+ assign T_194_data = T_198;
+ assign T_194_tag = T_197;
+ assign T_197 = in_buf[4:0];
+ assign T_198 = in_buf[68:5];
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ out_buf = {2{$random}};
+ in_buf = {3{$random}};
+ state = {1{$random}};
+ send_cnt = {1{$random}};
+ data_send_cnt = {1{$random}};
+ recv_cnt = {1{$random}};
+ data_recv_cnt = {1{$random}};
+ resp_val = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_144) begin
+ out_buf <= io_wide_req_data_bits_data;
+ end else begin
+ if(T_141) begin
+ out_buf <= T_143;
+ end else begin
+ if(T_135) begin
+ out_buf <= T_140;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_narrow_resp_valid) begin
+ in_buf <= T_190;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ state <= 1'h0;
+ end else begin
+ if(T_164) begin
+ state <= T_170;
+ end else begin
+ if(T_162) begin
+ state <= 3'h4;
+ end else begin
+ if(T_159) begin
+ state <= 2'h3;
+ end else begin
+ if(T_156) begin
+ state <= 1'h0;
+ end else begin
+ if(T_153) begin
+ state <= T_154;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ if(reset) begin
+ send_cnt <= 2'h0;
+ end else begin
+ if(T_164) begin
+ send_cnt <= 1'h0;
+ end else begin
+ if(T_159) begin
+ send_cnt <= 1'h0;
+ end else begin
+ if(T_156) begin
+ send_cnt <= 1'h0;
+ end else begin
+ if(T_135) begin
+ send_cnt <= T_138;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ if(reset) begin
+ data_send_cnt <= 3'h0;
+ end else begin
+ if(T_164) begin
+ data_send_cnt <= T_167;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ recv_cnt <= 3'h0;
+ end else begin
+ if(io_narrow_resp_valid) begin
+ if(T_183) begin
+ recv_cnt <= 1'h0;
+ end else begin
+ recv_cnt <= T_181;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ data_recv_cnt <= 3'h0;
+ end else begin
+ if(io_narrow_resp_valid) begin
+ if(T_183) begin
+ data_recv_cnt <= T_187;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ resp_val <= 1'h0;
+ end else begin
+ if(io_narrow_resp_valid) begin
+ if(T_183) begin
+ resp_val <= 1'h1;
+ end else begin
+ resp_val <= 1'h0;
+ end
+ end else begin
+ resp_val <= 1'h0;
+ end
+ end
+ end
+endmodule
+module OuterMemorySystem(
+ input clk,
+ input reset,
+ output io_tiles_cached_0_acquire_ready,
+ input io_tiles_cached_0_acquire_valid,
+ input [25:0] io_tiles_cached_0_acquire_bits_addr_block,
+ input [1:0] io_tiles_cached_0_acquire_bits_client_xact_id,
+ input [1:0] io_tiles_cached_0_acquire_bits_addr_beat,
+ input io_tiles_cached_0_acquire_bits_is_builtin_type,
+ input [2:0] io_tiles_cached_0_acquire_bits_a_type,
+ input [16:0] io_tiles_cached_0_acquire_bits_union,
+ input [127:0] io_tiles_cached_0_acquire_bits_data,
+ input io_tiles_cached_0_grant_ready,
+ output io_tiles_cached_0_grant_valid,
+ output [1:0] io_tiles_cached_0_grant_bits_addr_beat,
+ output [1:0] io_tiles_cached_0_grant_bits_client_xact_id,
+ output [3:0] io_tiles_cached_0_grant_bits_manager_xact_id,
+ output io_tiles_cached_0_grant_bits_is_builtin_type,
+ output [3:0] io_tiles_cached_0_grant_bits_g_type,
+ output [127:0] io_tiles_cached_0_grant_bits_data,
+ input io_tiles_cached_0_probe_ready,
+ output io_tiles_cached_0_probe_valid,
+ output [25:0] io_tiles_cached_0_probe_bits_addr_block,
+ output [1:0] io_tiles_cached_0_probe_bits_p_type,
+ output io_tiles_cached_0_release_ready,
+ input io_tiles_cached_0_release_valid,
+ input [1:0] io_tiles_cached_0_release_bits_addr_beat,
+ input [25:0] io_tiles_cached_0_release_bits_addr_block,
+ input [1:0] io_tiles_cached_0_release_bits_client_xact_id,
+ input io_tiles_cached_0_release_bits_voluntary,
+ input [2:0] io_tiles_cached_0_release_bits_r_type,
+ input [127:0] io_tiles_cached_0_release_bits_data,
+ output io_tiles_uncached_0_acquire_ready,
+ input io_tiles_uncached_0_acquire_valid,
+ input [25:0] io_tiles_uncached_0_acquire_bits_addr_block,
+ input [1:0] io_tiles_uncached_0_acquire_bits_client_xact_id,
+ input [1:0] io_tiles_uncached_0_acquire_bits_addr_beat,
+ input io_tiles_uncached_0_acquire_bits_is_builtin_type,
+ input [2:0] io_tiles_uncached_0_acquire_bits_a_type,
+ input [16:0] io_tiles_uncached_0_acquire_bits_union,
+ input [127:0] io_tiles_uncached_0_acquire_bits_data,
+ input io_tiles_uncached_0_grant_ready,
+ output io_tiles_uncached_0_grant_valid,
+ output [1:0] io_tiles_uncached_0_grant_bits_addr_beat,
+ output [1:0] io_tiles_uncached_0_grant_bits_client_xact_id,
+ output [3:0] io_tiles_uncached_0_grant_bits_manager_xact_id,
+ output io_tiles_uncached_0_grant_bits_is_builtin_type,
+ output [3:0] io_tiles_uncached_0_grant_bits_g_type,
+ output [127:0] io_tiles_uncached_0_grant_bits_data,
+ output io_htif_uncached_acquire_ready,
+ input io_htif_uncached_acquire_valid,
+ input [25:0] io_htif_uncached_acquire_bits_addr_block,
+ input [1:0] io_htif_uncached_acquire_bits_client_xact_id,
+ input [1:0] io_htif_uncached_acquire_bits_addr_beat,
+ input io_htif_uncached_acquire_bits_is_builtin_type,
+ input [2:0] io_htif_uncached_acquire_bits_a_type,
+ input [16:0] io_htif_uncached_acquire_bits_union,
+ input [127:0] io_htif_uncached_acquire_bits_data,
+ input io_htif_uncached_grant_ready,
+ output io_htif_uncached_grant_valid,
+ output [1:0] io_htif_uncached_grant_bits_addr_beat,
+ output [1:0] io_htif_uncached_grant_bits_client_xact_id,
+ output [3:0] io_htif_uncached_grant_bits_manager_xact_id,
+ output io_htif_uncached_grant_bits_is_builtin_type,
+ output [3:0] io_htif_uncached_grant_bits_g_type,
+ output [127:0] io_htif_uncached_grant_bits_data,
+ input io_incoherent_0,
+ input io_mem_0_aw_ready,
+ output io_mem_0_aw_valid,
+ output [31:0] io_mem_0_aw_bits_addr,
+ output [7:0] io_mem_0_aw_bits_len,
+ output [2:0] io_mem_0_aw_bits_size,
+ output [1:0] io_mem_0_aw_bits_burst,
+ output io_mem_0_aw_bits_lock,
+ output [3:0] io_mem_0_aw_bits_cache,
+ output [2:0] io_mem_0_aw_bits_prot,
+ output [3:0] io_mem_0_aw_bits_qos,
+ output [3:0] io_mem_0_aw_bits_region,
+ output [4:0] io_mem_0_aw_bits_id,
+ output io_mem_0_aw_bits_user,
+ input io_mem_0_w_ready,
+ output io_mem_0_w_valid,
+ output [63:0] io_mem_0_w_bits_data,
+ output io_mem_0_w_bits_last,
+ output [7:0] io_mem_0_w_bits_strb,
+ output io_mem_0_w_bits_user,
+ output io_mem_0_b_ready,
+ input io_mem_0_b_valid,
+ input [1:0] io_mem_0_b_bits_resp,
+ input [4:0] io_mem_0_b_bits_id,
+ input io_mem_0_b_bits_user,
+ input io_mem_0_ar_ready,
+ output io_mem_0_ar_valid,
+ output [31:0] io_mem_0_ar_bits_addr,
+ output [7:0] io_mem_0_ar_bits_len,
+ output [2:0] io_mem_0_ar_bits_size,
+ output [1:0] io_mem_0_ar_bits_burst,
+ output io_mem_0_ar_bits_lock,
+ output [3:0] io_mem_0_ar_bits_cache,
+ output [2:0] io_mem_0_ar_bits_prot,
+ output [3:0] io_mem_0_ar_bits_qos,
+ output [3:0] io_mem_0_ar_bits_region,
+ output [4:0] io_mem_0_ar_bits_id,
+ output io_mem_0_ar_bits_user,
+ output io_mem_0_r_ready,
+ input io_mem_0_r_valid,
+ input [1:0] io_mem_0_r_bits_resp,
+ input [63:0] io_mem_0_r_bits_data,
+ input io_mem_0_r_bits_last,
+ input [4:0] io_mem_0_r_bits_id,
+ input io_mem_0_r_bits_user,
+ input io_mem_backup_req_ready,
+ output io_mem_backup_req_valid,
+ output [15:0] io_mem_backup_req_bits,
+ input io_mem_backup_resp_valid,
+ input [15:0] io_mem_backup_resp_bits,
+ input io_mem_backup_en,
+ input io_csr_0_req_ready,
+ output io_csr_0_req_valid,
+ output io_csr_0_req_bits_rw,
+ output [11:0] io_csr_0_req_bits_addr,
+ output [63:0] io_csr_0_req_bits_data,
+ output io_csr_0_resp_ready,
+ input io_csr_0_resp_valid,
+ input [63:0] io_csr_0_resp_bits,
+ input io_scr_req_ready,
+ output io_scr_req_valid,
+ output io_scr_req_bits_rw,
+ output [5:0] io_scr_req_bits_addr,
+ output [63:0] io_scr_req_bits_data,
+ output io_scr_resp_ready,
+ input io_scr_resp_valid,
+ input [63:0] io_scr_resp_bits,
+ input io_mmio_aw_ready,
+ output io_mmio_aw_valid,
+ output [31:0] io_mmio_aw_bits_addr,
+ output [7:0] io_mmio_aw_bits_len,
+ output [2:0] io_mmio_aw_bits_size,
+ output [1:0] io_mmio_aw_bits_burst,
+ output io_mmio_aw_bits_lock,
+ output [3:0] io_mmio_aw_bits_cache,
+ output [2:0] io_mmio_aw_bits_prot,
+ output [3:0] io_mmio_aw_bits_qos,
+ output [3:0] io_mmio_aw_bits_region,
+ output [4:0] io_mmio_aw_bits_id,
+ output io_mmio_aw_bits_user,
+ input io_mmio_w_ready,
+ output io_mmio_w_valid,
+ output [63:0] io_mmio_w_bits_data,
+ output io_mmio_w_bits_last,
+ output [7:0] io_mmio_w_bits_strb,
+ output io_mmio_w_bits_user,
+ output io_mmio_b_ready,
+ input io_mmio_b_valid,
+ input [1:0] io_mmio_b_bits_resp,
+ input [4:0] io_mmio_b_bits_id,
+ input io_mmio_b_bits_user,
+ input io_mmio_ar_ready,
+ output io_mmio_ar_valid,
+ output [31:0] io_mmio_ar_bits_addr,
+ output [7:0] io_mmio_ar_bits_len,
+ output [2:0] io_mmio_ar_bits_size,
+ output [1:0] io_mmio_ar_bits_burst,
+ output io_mmio_ar_bits_lock,
+ output [3:0] io_mmio_ar_bits_cache,
+ output [2:0] io_mmio_ar_bits_prot,
+ output [3:0] io_mmio_ar_bits_qos,
+ output [3:0] io_mmio_ar_bits_region,
+ output [4:0] io_mmio_ar_bits_id,
+ output io_mmio_ar_bits_user,
+ output io_mmio_r_ready,
+ input io_mmio_r_valid,
+ input [1:0] io_mmio_r_bits_resp,
+ input [63:0] io_mmio_r_bits_data,
+ input io_mmio_r_bits_last,
+ input [4:0] io_mmio_r_bits_id,
+ input io_mmio_r_bits_user,
+ input io_deviceTree_aw_ready,
+ output io_deviceTree_aw_valid,
+ output [31:0] io_deviceTree_aw_bits_addr,
+ output [7:0] io_deviceTree_aw_bits_len,
+ output [2:0] io_deviceTree_aw_bits_size,
+ output [1:0] io_deviceTree_aw_bits_burst,
+ output io_deviceTree_aw_bits_lock,
+ output [3:0] io_deviceTree_aw_bits_cache,
+ output [2:0] io_deviceTree_aw_bits_prot,
+ output [3:0] io_deviceTree_aw_bits_qos,
+ output [3:0] io_deviceTree_aw_bits_region,
+ output [4:0] io_deviceTree_aw_bits_id,
+ output io_deviceTree_aw_bits_user,
+ input io_deviceTree_w_ready,
+ output io_deviceTree_w_valid,
+ output [63:0] io_deviceTree_w_bits_data,
+ output io_deviceTree_w_bits_last,
+ output [7:0] io_deviceTree_w_bits_strb,
+ output io_deviceTree_w_bits_user,
+ output io_deviceTree_b_ready,
+ input io_deviceTree_b_valid,
+ input [1:0] io_deviceTree_b_bits_resp,
+ input [4:0] io_deviceTree_b_bits_id,
+ input io_deviceTree_b_bits_user,
+ input io_deviceTree_ar_ready,
+ output io_deviceTree_ar_valid,
+ output [31:0] io_deviceTree_ar_bits_addr,
+ output [7:0] io_deviceTree_ar_bits_len,
+ output [2:0] io_deviceTree_ar_bits_size,
+ output [1:0] io_deviceTree_ar_bits_burst,
+ output io_deviceTree_ar_bits_lock,
+ output [3:0] io_deviceTree_ar_bits_cache,
+ output [2:0] io_deviceTree_ar_bits_prot,
+ output [3:0] io_deviceTree_ar_bits_qos,
+ output [3:0] io_deviceTree_ar_bits_region,
+ output [4:0] io_deviceTree_ar_bits_id,
+ output io_deviceTree_ar_bits_user,
+ output io_deviceTree_r_ready,
+ input io_deviceTree_r_valid,
+ input [1:0] io_deviceTree_r_bits_resp,
+ input [63:0] io_deviceTree_r_bits_data,
+ input io_deviceTree_r_bits_last,
+ input [4:0] io_deviceTree_r_bits_id,
+ input io_deviceTree_r_bits_user,
+ output io_dma_req_ready,
+ input io_dma_req_valid,
+ input [1:0] io_dma_req_bits_client_xact_id,
+ input [2:0] io_dma_req_bits_cmd,
+ input [31:0] io_dma_req_bits_source,
+ input [31:0] io_dma_req_bits_dest,
+ input [31:0] io_dma_req_bits_length,
+ input [1:0] io_dma_req_bits_size,
+ input io_dma_resp_ready,
+ output io_dma_resp_valid,
+ output [1:0] io_dma_resp_bits_client_xact_id,
+ output [1:0] io_dma_resp_bits_status
+);
+ wire T_8064_clk;
+ wire T_8064_reset;
+ wire T_8064_io_in_acquire_ready;
+ wire T_8064_io_in_acquire_valid;
+ wire [25:0] T_8064_io_in_acquire_bits_addr_block;
+ wire [1:0] T_8064_io_in_acquire_bits_client_xact_id;
+ wire [1:0] T_8064_io_in_acquire_bits_addr_beat;
+ wire T_8064_io_in_acquire_bits_is_builtin_type;
+ wire [2:0] T_8064_io_in_acquire_bits_a_type;
+ wire [16:0] T_8064_io_in_acquire_bits_union;
+ wire [127:0] T_8064_io_in_acquire_bits_data;
+ wire T_8064_io_in_grant_ready;
+ wire T_8064_io_in_grant_valid;
+ wire [1:0] T_8064_io_in_grant_bits_addr_beat;
+ wire [1:0] T_8064_io_in_grant_bits_client_xact_id;
+ wire [3:0] T_8064_io_in_grant_bits_manager_xact_id;
+ wire T_8064_io_in_grant_bits_is_builtin_type;
+ wire [3:0] T_8064_io_in_grant_bits_g_type;
+ wire [127:0] T_8064_io_in_grant_bits_data;
+ wire T_8064_io_out_acquire_ready;
+ wire T_8064_io_out_acquire_valid;
+ wire [25:0] T_8064_io_out_acquire_bits_addr_block;
+ wire [1:0] T_8064_io_out_acquire_bits_client_xact_id;
+ wire [1:0] T_8064_io_out_acquire_bits_addr_beat;
+ wire T_8064_io_out_acquire_bits_is_builtin_type;
+ wire [2:0] T_8064_io_out_acquire_bits_a_type;
+ wire [16:0] T_8064_io_out_acquire_bits_union;
+ wire [127:0] T_8064_io_out_acquire_bits_data;
+ wire T_8064_io_out_grant_ready;
+ wire T_8064_io_out_grant_valid;
+ wire [1:0] T_8064_io_out_grant_bits_addr_beat;
+ wire [1:0] T_8064_io_out_grant_bits_client_xact_id;
+ wire [3:0] T_8064_io_out_grant_bits_manager_xact_id;
+ wire T_8064_io_out_grant_bits_is_builtin_type;
+ wire [3:0] T_8064_io_out_grant_bits_g_type;
+ wire [127:0] T_8064_io_out_grant_bits_data;
+ wire T_8064_io_out_probe_ready;
+ wire T_8064_io_out_probe_valid;
+ wire [25:0] T_8064_io_out_probe_bits_addr_block;
+ wire [1:0] T_8064_io_out_probe_bits_p_type;
+ wire T_8064_io_out_release_ready;
+ wire T_8064_io_out_release_valid;
+ wire [1:0] T_8064_io_out_release_bits_addr_beat;
+ wire [25:0] T_8064_io_out_release_bits_addr_block;
+ wire [1:0] T_8064_io_out_release_bits_client_xact_id;
+ wire T_8064_io_out_release_bits_voluntary;
+ wire [2:0] T_8064_io_out_release_bits_r_type;
+ wire [127:0] T_8064_io_out_release_bits_data;
+ wire T_8065_clk;
+ wire T_8065_reset;
+ wire T_8065_io_in_acquire_ready;
+ wire T_8065_io_in_acquire_valid;
+ wire [25:0] T_8065_io_in_acquire_bits_addr_block;
+ wire [1:0] T_8065_io_in_acquire_bits_client_xact_id;
+ wire [1:0] T_8065_io_in_acquire_bits_addr_beat;
+ wire T_8065_io_in_acquire_bits_is_builtin_type;
+ wire [2:0] T_8065_io_in_acquire_bits_a_type;
+ wire [16:0] T_8065_io_in_acquire_bits_union;
+ wire [127:0] T_8065_io_in_acquire_bits_data;
+ wire T_8065_io_in_grant_ready;
+ wire T_8065_io_in_grant_valid;
+ wire [1:0] T_8065_io_in_grant_bits_addr_beat;
+ wire [1:0] T_8065_io_in_grant_bits_client_xact_id;
+ wire [3:0] T_8065_io_in_grant_bits_manager_xact_id;
+ wire T_8065_io_in_grant_bits_is_builtin_type;
+ wire [3:0] T_8065_io_in_grant_bits_g_type;
+ wire [127:0] T_8065_io_in_grant_bits_data;
+ wire T_8065_io_out_acquire_ready;
+ wire T_8065_io_out_acquire_valid;
+ wire [25:0] T_8065_io_out_acquire_bits_addr_block;
+ wire [1:0] T_8065_io_out_acquire_bits_client_xact_id;
+ wire [1:0] T_8065_io_out_acquire_bits_addr_beat;
+ wire T_8065_io_out_acquire_bits_is_builtin_type;
+ wire [2:0] T_8065_io_out_acquire_bits_a_type;
+ wire [16:0] T_8065_io_out_acquire_bits_union;
+ wire [127:0] T_8065_io_out_acquire_bits_data;
+ wire T_8065_io_out_grant_ready;
+ wire T_8065_io_out_grant_valid;
+ wire [1:0] T_8065_io_out_grant_bits_addr_beat;
+ wire [1:0] T_8065_io_out_grant_bits_client_xact_id;
+ wire [3:0] T_8065_io_out_grant_bits_manager_xact_id;
+ wire T_8065_io_out_grant_bits_is_builtin_type;
+ wire [3:0] T_8065_io_out_grant_bits_g_type;
+ wire [127:0] T_8065_io_out_grant_bits_data;
+ wire T_8065_io_out_probe_ready;
+ wire T_8065_io_out_probe_valid;
+ wire [25:0] T_8065_io_out_probe_bits_addr_block;
+ wire [1:0] T_8065_io_out_probe_bits_p_type;
+ wire T_8065_io_out_release_ready;
+ wire T_8065_io_out_release_valid;
+ wire [1:0] T_8065_io_out_release_bits_addr_beat;
+ wire [25:0] T_8065_io_out_release_bits_addr_block;
+ wire [1:0] T_8065_io_out_release_bits_client_xact_id;
+ wire T_8065_io_out_release_bits_voluntary;
+ wire [2:0] T_8065_io_out_release_bits_r_type;
+ wire [127:0] T_8065_io_out_release_bits_data;
+ wire l1tol2net_clk;
+ wire l1tol2net_reset;
+ wire l1tol2net_io_clients_0_acquire_ready;
+ wire l1tol2net_io_clients_0_acquire_valid;
+ wire [25:0] l1tol2net_io_clients_0_acquire_bits_addr_block;
+ wire [1:0] l1tol2net_io_clients_0_acquire_bits_client_xact_id;
+ wire [1:0] l1tol2net_io_clients_0_acquire_bits_addr_beat;
+ wire l1tol2net_io_clients_0_acquire_bits_is_builtin_type;
+ wire [2:0] l1tol2net_io_clients_0_acquire_bits_a_type;
+ wire [16:0] l1tol2net_io_clients_0_acquire_bits_union;
+ wire [127:0] l1tol2net_io_clients_0_acquire_bits_data;
+ wire l1tol2net_io_clients_0_grant_ready;
+ wire l1tol2net_io_clients_0_grant_valid;
+ wire [1:0] l1tol2net_io_clients_0_grant_bits_addr_beat;
+ wire [1:0] l1tol2net_io_clients_0_grant_bits_client_xact_id;
+ wire [3:0] l1tol2net_io_clients_0_grant_bits_manager_xact_id;
+ wire l1tol2net_io_clients_0_grant_bits_is_builtin_type;
+ wire [3:0] l1tol2net_io_clients_0_grant_bits_g_type;
+ wire [127:0] l1tol2net_io_clients_0_grant_bits_data;
+ wire l1tol2net_io_clients_0_probe_ready;
+ wire l1tol2net_io_clients_0_probe_valid;
+ wire [25:0] l1tol2net_io_clients_0_probe_bits_addr_block;
+ wire [1:0] l1tol2net_io_clients_0_probe_bits_p_type;
+ wire l1tol2net_io_clients_0_release_ready;
+ wire l1tol2net_io_clients_0_release_valid;
+ wire [1:0] l1tol2net_io_clients_0_release_bits_addr_beat;
+ wire [25:0] l1tol2net_io_clients_0_release_bits_addr_block;
+ wire [1:0] l1tol2net_io_clients_0_release_bits_client_xact_id;
+ wire l1tol2net_io_clients_0_release_bits_voluntary;
+ wire [2:0] l1tol2net_io_clients_0_release_bits_r_type;
+ wire [127:0] l1tol2net_io_clients_0_release_bits_data;
+ wire l1tol2net_io_clients_1_acquire_ready;
+ wire l1tol2net_io_clients_1_acquire_valid;
+ wire [25:0] l1tol2net_io_clients_1_acquire_bits_addr_block;
+ wire [1:0] l1tol2net_io_clients_1_acquire_bits_client_xact_id;
+ wire [1:0] l1tol2net_io_clients_1_acquire_bits_addr_beat;
+ wire l1tol2net_io_clients_1_acquire_bits_is_builtin_type;
+ wire [2:0] l1tol2net_io_clients_1_acquire_bits_a_type;
+ wire [16:0] l1tol2net_io_clients_1_acquire_bits_union;
+ wire [127:0] l1tol2net_io_clients_1_acquire_bits_data;
+ wire l1tol2net_io_clients_1_grant_ready;
+ wire l1tol2net_io_clients_1_grant_valid;
+ wire [1:0] l1tol2net_io_clients_1_grant_bits_addr_beat;
+ wire [1:0] l1tol2net_io_clients_1_grant_bits_client_xact_id;
+ wire [3:0] l1tol2net_io_clients_1_grant_bits_manager_xact_id;
+ wire l1tol2net_io_clients_1_grant_bits_is_builtin_type;
+ wire [3:0] l1tol2net_io_clients_1_grant_bits_g_type;
+ wire [127:0] l1tol2net_io_clients_1_grant_bits_data;
+ wire l1tol2net_io_clients_1_probe_ready;
+ wire l1tol2net_io_clients_1_probe_valid;
+ wire [25:0] l1tol2net_io_clients_1_probe_bits_addr_block;
+ wire [1:0] l1tol2net_io_clients_1_probe_bits_p_type;
+ wire l1tol2net_io_clients_1_release_ready;
+ wire l1tol2net_io_clients_1_release_valid;
+ wire [1:0] l1tol2net_io_clients_1_release_bits_addr_beat;
+ wire [25:0] l1tol2net_io_clients_1_release_bits_addr_block;
+ wire [1:0] l1tol2net_io_clients_1_release_bits_client_xact_id;
+ wire l1tol2net_io_clients_1_release_bits_voluntary;
+ wire [2:0] l1tol2net_io_clients_1_release_bits_r_type;
+ wire [127:0] l1tol2net_io_clients_1_release_bits_data;
+ wire l1tol2net_io_clients_2_acquire_ready;
+ wire l1tol2net_io_clients_2_acquire_valid;
+ wire [25:0] l1tol2net_io_clients_2_acquire_bits_addr_block;
+ wire [1:0] l1tol2net_io_clients_2_acquire_bits_client_xact_id;
+ wire [1:0] l1tol2net_io_clients_2_acquire_bits_addr_beat;
+ wire l1tol2net_io_clients_2_acquire_bits_is_builtin_type;
+ wire [2:0] l1tol2net_io_clients_2_acquire_bits_a_type;
+ wire [16:0] l1tol2net_io_clients_2_acquire_bits_union;
+ wire [127:0] l1tol2net_io_clients_2_acquire_bits_data;
+ wire l1tol2net_io_clients_2_grant_ready;
+ wire l1tol2net_io_clients_2_grant_valid;
+ wire [1:0] l1tol2net_io_clients_2_grant_bits_addr_beat;
+ wire [1:0] l1tol2net_io_clients_2_grant_bits_client_xact_id;
+ wire [3:0] l1tol2net_io_clients_2_grant_bits_manager_xact_id;
+ wire l1tol2net_io_clients_2_grant_bits_is_builtin_type;
+ wire [3:0] l1tol2net_io_clients_2_grant_bits_g_type;
+ wire [127:0] l1tol2net_io_clients_2_grant_bits_data;
+ wire l1tol2net_io_clients_2_probe_ready;
+ wire l1tol2net_io_clients_2_probe_valid;
+ wire [25:0] l1tol2net_io_clients_2_probe_bits_addr_block;
+ wire [1:0] l1tol2net_io_clients_2_probe_bits_p_type;
+ wire l1tol2net_io_clients_2_release_ready;
+ wire l1tol2net_io_clients_2_release_valid;
+ wire [1:0] l1tol2net_io_clients_2_release_bits_addr_beat;
+ wire [25:0] l1tol2net_io_clients_2_release_bits_addr_block;
+ wire [1:0] l1tol2net_io_clients_2_release_bits_client_xact_id;
+ wire l1tol2net_io_clients_2_release_bits_voluntary;
+ wire [2:0] l1tol2net_io_clients_2_release_bits_r_type;
+ wire [127:0] l1tol2net_io_clients_2_release_bits_data;
+ wire l1tol2net_io_managers_0_acquire_ready;
+ wire l1tol2net_io_managers_0_acquire_valid;
+ wire [25:0] l1tol2net_io_managers_0_acquire_bits_addr_block;
+ wire [1:0] l1tol2net_io_managers_0_acquire_bits_client_xact_id;
+ wire [1:0] l1tol2net_io_managers_0_acquire_bits_addr_beat;
+ wire l1tol2net_io_managers_0_acquire_bits_is_builtin_type;
+ wire [2:0] l1tol2net_io_managers_0_acquire_bits_a_type;
+ wire [16:0] l1tol2net_io_managers_0_acquire_bits_union;
+ wire [127:0] l1tol2net_io_managers_0_acquire_bits_data;
+ wire [1:0] l1tol2net_io_managers_0_acquire_bits_client_id;
+ wire l1tol2net_io_managers_0_grant_ready;
+ wire l1tol2net_io_managers_0_grant_valid;
+ wire [1:0] l1tol2net_io_managers_0_grant_bits_addr_beat;
+ wire [1:0] l1tol2net_io_managers_0_grant_bits_client_xact_id;
+ wire [3:0] l1tol2net_io_managers_0_grant_bits_manager_xact_id;
+ wire l1tol2net_io_managers_0_grant_bits_is_builtin_type;
+ wire [3:0] l1tol2net_io_managers_0_grant_bits_g_type;
+ wire [127:0] l1tol2net_io_managers_0_grant_bits_data;
+ wire [1:0] l1tol2net_io_managers_0_grant_bits_client_id;
+ wire l1tol2net_io_managers_0_finish_ready;
+ wire l1tol2net_io_managers_0_finish_valid;
+ wire [3:0] l1tol2net_io_managers_0_finish_bits_manager_xact_id;
+ wire l1tol2net_io_managers_0_probe_ready;
+ wire l1tol2net_io_managers_0_probe_valid;
+ wire [25:0] l1tol2net_io_managers_0_probe_bits_addr_block;
+ wire [1:0] l1tol2net_io_managers_0_probe_bits_p_type;
+ wire [1:0] l1tol2net_io_managers_0_probe_bits_client_id;
+ wire l1tol2net_io_managers_0_release_ready;
+ wire l1tol2net_io_managers_0_release_valid;
+ wire [1:0] l1tol2net_io_managers_0_release_bits_addr_beat;
+ wire [25:0] l1tol2net_io_managers_0_release_bits_addr_block;
+ wire [1:0] l1tol2net_io_managers_0_release_bits_client_xact_id;
+ wire l1tol2net_io_managers_0_release_bits_voluntary;
+ wire [2:0] l1tol2net_io_managers_0_release_bits_r_type;
+ wire [127:0] l1tol2net_io_managers_0_release_bits_data;
+ wire [1:0] l1tol2net_io_managers_0_release_bits_client_id;
+ wire T_8067_clk;
+ wire T_8067_reset;
+ wire T_8067_io_inner_acquire_ready;
+ wire T_8067_io_inner_acquire_valid;
+ wire [25:0] T_8067_io_inner_acquire_bits_addr_block;
+ wire [1:0] T_8067_io_inner_acquire_bits_client_xact_id;
+ wire [1:0] T_8067_io_inner_acquire_bits_addr_beat;
+ wire T_8067_io_inner_acquire_bits_is_builtin_type;
+ wire [2:0] T_8067_io_inner_acquire_bits_a_type;
+ wire [16:0] T_8067_io_inner_acquire_bits_union;
+ wire [127:0] T_8067_io_inner_acquire_bits_data;
+ wire [1:0] T_8067_io_inner_acquire_bits_client_id;
+ wire T_8067_io_inner_grant_ready;
+ wire T_8067_io_inner_grant_valid;
+ wire [1:0] T_8067_io_inner_grant_bits_addr_beat;
+ wire [1:0] T_8067_io_inner_grant_bits_client_xact_id;
+ wire [3:0] T_8067_io_inner_grant_bits_manager_xact_id;
+ wire T_8067_io_inner_grant_bits_is_builtin_type;
+ wire [3:0] T_8067_io_inner_grant_bits_g_type;
+ wire [127:0] T_8067_io_inner_grant_bits_data;
+ wire [1:0] T_8067_io_inner_grant_bits_client_id;
+ wire T_8067_io_inner_finish_ready;
+ wire T_8067_io_inner_finish_valid;
+ wire [3:0] T_8067_io_inner_finish_bits_manager_xact_id;
+ wire T_8067_io_inner_probe_ready;
+ wire T_8067_io_inner_probe_valid;
+ wire [25:0] T_8067_io_inner_probe_bits_addr_block;
+ wire [1:0] T_8067_io_inner_probe_bits_p_type;
+ wire [1:0] T_8067_io_inner_probe_bits_client_id;
+ wire T_8067_io_inner_release_ready;
+ wire T_8067_io_inner_release_valid;
+ wire [1:0] T_8067_io_inner_release_bits_addr_beat;
+ wire [25:0] T_8067_io_inner_release_bits_addr_block;
+ wire [1:0] T_8067_io_inner_release_bits_client_xact_id;
+ wire T_8067_io_inner_release_bits_voluntary;
+ wire [2:0] T_8067_io_inner_release_bits_r_type;
+ wire [127:0] T_8067_io_inner_release_bits_data;
+ wire [1:0] T_8067_io_inner_release_bits_client_id;
+ wire T_8067_io_incoherent_0;
+ wire T_8067_io_outer_acquire_ready;
+ wire T_8067_io_outer_acquire_valid;
+ wire [25:0] T_8067_io_outer_acquire_bits_addr_block;
+ wire [3:0] T_8067_io_outer_acquire_bits_client_xact_id;
+ wire [1:0] T_8067_io_outer_acquire_bits_addr_beat;
+ wire T_8067_io_outer_acquire_bits_is_builtin_type;
+ wire [2:0] T_8067_io_outer_acquire_bits_a_type;
+ wire [16:0] T_8067_io_outer_acquire_bits_union;
+ wire [127:0] T_8067_io_outer_acquire_bits_data;
+ wire T_8067_io_outer_grant_ready;
+ wire T_8067_io_outer_grant_valid;
+ wire [1:0] T_8067_io_outer_grant_bits_addr_beat;
+ wire [3:0] T_8067_io_outer_grant_bits_client_xact_id;
+ wire T_8067_io_outer_grant_bits_manager_xact_id;
+ wire T_8067_io_outer_grant_bits_is_builtin_type;
+ wire [3:0] T_8067_io_outer_grant_bits_g_type;
+ wire [127:0] T_8067_io_outer_grant_bits_data;
+ wire interconnect$_clk;
+ wire interconnect$_reset;
+ wire interconnect$_io_masters_0_aw_ready;
+ wire interconnect$_io_masters_0_aw_valid;
+ wire [31:0] interconnect$_io_masters_0_aw_bits_addr;
+ wire [7:0] interconnect$_io_masters_0_aw_bits_len;
+ wire [2:0] interconnect$_io_masters_0_aw_bits_size;
+ wire [1:0] interconnect$_io_masters_0_aw_bits_burst;
+ wire interconnect$_io_masters_0_aw_bits_lock;
+ wire [3:0] interconnect$_io_masters_0_aw_bits_cache;
+ wire [2:0] interconnect$_io_masters_0_aw_bits_prot;
+ wire [3:0] interconnect$_io_masters_0_aw_bits_qos;
+ wire [3:0] interconnect$_io_masters_0_aw_bits_region;
+ wire [4:0] interconnect$_io_masters_0_aw_bits_id;
+ wire interconnect$_io_masters_0_aw_bits_user;
+ wire interconnect$_io_masters_0_w_ready;
+ wire interconnect$_io_masters_0_w_valid;
+ wire [63:0] interconnect$_io_masters_0_w_bits_data;
+ wire interconnect$_io_masters_0_w_bits_last;
+ wire [7:0] interconnect$_io_masters_0_w_bits_strb;
+ wire interconnect$_io_masters_0_w_bits_user;
+ wire interconnect$_io_masters_0_b_ready;
+ wire interconnect$_io_masters_0_b_valid;
+ wire [1:0] interconnect$_io_masters_0_b_bits_resp;
+ wire [4:0] interconnect$_io_masters_0_b_bits_id;
+ wire interconnect$_io_masters_0_b_bits_user;
+ wire interconnect$_io_masters_0_ar_ready;
+ wire interconnect$_io_masters_0_ar_valid;
+ wire [31:0] interconnect$_io_masters_0_ar_bits_addr;
+ wire [7:0] interconnect$_io_masters_0_ar_bits_len;
+ wire [2:0] interconnect$_io_masters_0_ar_bits_size;
+ wire [1:0] interconnect$_io_masters_0_ar_bits_burst;
+ wire interconnect$_io_masters_0_ar_bits_lock;
+ wire [3:0] interconnect$_io_masters_0_ar_bits_cache;
+ wire [2:0] interconnect$_io_masters_0_ar_bits_prot;
+ wire [3:0] interconnect$_io_masters_0_ar_bits_qos;
+ wire [3:0] interconnect$_io_masters_0_ar_bits_region;
+ wire [4:0] interconnect$_io_masters_0_ar_bits_id;
+ wire interconnect$_io_masters_0_ar_bits_user;
+ wire interconnect$_io_masters_0_r_ready;
+ wire interconnect$_io_masters_0_r_valid;
+ wire [1:0] interconnect$_io_masters_0_r_bits_resp;
+ wire [63:0] interconnect$_io_masters_0_r_bits_data;
+ wire interconnect$_io_masters_0_r_bits_last;
+ wire [4:0] interconnect$_io_masters_0_r_bits_id;
+ wire interconnect$_io_masters_0_r_bits_user;
+ wire interconnect$_io_masters_1_aw_ready;
+ wire interconnect$_io_masters_1_aw_valid;
+ wire [31:0] interconnect$_io_masters_1_aw_bits_addr;
+ wire [7:0] interconnect$_io_masters_1_aw_bits_len;
+ wire [2:0] interconnect$_io_masters_1_aw_bits_size;
+ wire [1:0] interconnect$_io_masters_1_aw_bits_burst;
+ wire interconnect$_io_masters_1_aw_bits_lock;
+ wire [3:0] interconnect$_io_masters_1_aw_bits_cache;
+ wire [2:0] interconnect$_io_masters_1_aw_bits_prot;
+ wire [3:0] interconnect$_io_masters_1_aw_bits_qos;
+ wire [3:0] interconnect$_io_masters_1_aw_bits_region;
+ wire [4:0] interconnect$_io_masters_1_aw_bits_id;
+ wire interconnect$_io_masters_1_aw_bits_user;
+ wire interconnect$_io_masters_1_w_ready;
+ wire interconnect$_io_masters_1_w_valid;
+ wire [63:0] interconnect$_io_masters_1_w_bits_data;
+ wire interconnect$_io_masters_1_w_bits_last;
+ wire [7:0] interconnect$_io_masters_1_w_bits_strb;
+ wire interconnect$_io_masters_1_w_bits_user;
+ wire interconnect$_io_masters_1_b_ready;
+ wire interconnect$_io_masters_1_b_valid;
+ wire [1:0] interconnect$_io_masters_1_b_bits_resp;
+ wire [4:0] interconnect$_io_masters_1_b_bits_id;
+ wire interconnect$_io_masters_1_b_bits_user;
+ wire interconnect$_io_masters_1_ar_ready;
+ wire interconnect$_io_masters_1_ar_valid;
+ wire [31:0] interconnect$_io_masters_1_ar_bits_addr;
+ wire [7:0] interconnect$_io_masters_1_ar_bits_len;
+ wire [2:0] interconnect$_io_masters_1_ar_bits_size;
+ wire [1:0] interconnect$_io_masters_1_ar_bits_burst;
+ wire interconnect$_io_masters_1_ar_bits_lock;
+ wire [3:0] interconnect$_io_masters_1_ar_bits_cache;
+ wire [2:0] interconnect$_io_masters_1_ar_bits_prot;
+ wire [3:0] interconnect$_io_masters_1_ar_bits_qos;
+ wire [3:0] interconnect$_io_masters_1_ar_bits_region;
+ wire [4:0] interconnect$_io_masters_1_ar_bits_id;
+ wire interconnect$_io_masters_1_ar_bits_user;
+ wire interconnect$_io_masters_1_r_ready;
+ wire interconnect$_io_masters_1_r_valid;
+ wire [1:0] interconnect$_io_masters_1_r_bits_resp;
+ wire [63:0] interconnect$_io_masters_1_r_bits_data;
+ wire interconnect$_io_masters_1_r_bits_last;
+ wire [4:0] interconnect$_io_masters_1_r_bits_id;
+ wire interconnect$_io_masters_1_r_bits_user;
+ wire interconnect$_io_slaves_0_aw_ready;
+ wire interconnect$_io_slaves_0_aw_valid;
+ wire [31:0] interconnect$_io_slaves_0_aw_bits_addr;
+ wire [7:0] interconnect$_io_slaves_0_aw_bits_len;
+ wire [2:0] interconnect$_io_slaves_0_aw_bits_size;
+ wire [1:0] interconnect$_io_slaves_0_aw_bits_burst;
+ wire interconnect$_io_slaves_0_aw_bits_lock;
+ wire [3:0] interconnect$_io_slaves_0_aw_bits_cache;
+ wire [2:0] interconnect$_io_slaves_0_aw_bits_prot;
+ wire [3:0] interconnect$_io_slaves_0_aw_bits_qos;
+ wire [3:0] interconnect$_io_slaves_0_aw_bits_region;
+ wire [4:0] interconnect$_io_slaves_0_aw_bits_id;
+ wire interconnect$_io_slaves_0_aw_bits_user;
+ wire interconnect$_io_slaves_0_w_ready;
+ wire interconnect$_io_slaves_0_w_valid;
+ wire [63:0] interconnect$_io_slaves_0_w_bits_data;
+ wire interconnect$_io_slaves_0_w_bits_last;
+ wire [7:0] interconnect$_io_slaves_0_w_bits_strb;
+ wire interconnect$_io_slaves_0_w_bits_user;
+ wire interconnect$_io_slaves_0_b_ready;
+ wire interconnect$_io_slaves_0_b_valid;
+ wire [1:0] interconnect$_io_slaves_0_b_bits_resp;
+ wire [4:0] interconnect$_io_slaves_0_b_bits_id;
+ wire interconnect$_io_slaves_0_b_bits_user;
+ wire interconnect$_io_slaves_0_ar_ready;
+ wire interconnect$_io_slaves_0_ar_valid;
+ wire [31:0] interconnect$_io_slaves_0_ar_bits_addr;
+ wire [7:0] interconnect$_io_slaves_0_ar_bits_len;
+ wire [2:0] interconnect$_io_slaves_0_ar_bits_size;
+ wire [1:0] interconnect$_io_slaves_0_ar_bits_burst;
+ wire interconnect$_io_slaves_0_ar_bits_lock;
+ wire [3:0] interconnect$_io_slaves_0_ar_bits_cache;
+ wire [2:0] interconnect$_io_slaves_0_ar_bits_prot;
+ wire [3:0] interconnect$_io_slaves_0_ar_bits_qos;
+ wire [3:0] interconnect$_io_slaves_0_ar_bits_region;
+ wire [4:0] interconnect$_io_slaves_0_ar_bits_id;
+ wire interconnect$_io_slaves_0_ar_bits_user;
+ wire interconnect$_io_slaves_0_r_ready;
+ wire interconnect$_io_slaves_0_r_valid;
+ wire [1:0] interconnect$_io_slaves_0_r_bits_resp;
+ wire [63:0] interconnect$_io_slaves_0_r_bits_data;
+ wire interconnect$_io_slaves_0_r_bits_last;
+ wire [4:0] interconnect$_io_slaves_0_r_bits_id;
+ wire interconnect$_io_slaves_0_r_bits_user;
+ wire interconnect$_io_slaves_1_aw_ready;
+ wire interconnect$_io_slaves_1_aw_valid;
+ wire [31:0] interconnect$_io_slaves_1_aw_bits_addr;
+ wire [7:0] interconnect$_io_slaves_1_aw_bits_len;
+ wire [2:0] interconnect$_io_slaves_1_aw_bits_size;
+ wire [1:0] interconnect$_io_slaves_1_aw_bits_burst;
+ wire interconnect$_io_slaves_1_aw_bits_lock;
+ wire [3:0] interconnect$_io_slaves_1_aw_bits_cache;
+ wire [2:0] interconnect$_io_slaves_1_aw_bits_prot;
+ wire [3:0] interconnect$_io_slaves_1_aw_bits_qos;
+ wire [3:0] interconnect$_io_slaves_1_aw_bits_region;
+ wire [4:0] interconnect$_io_slaves_1_aw_bits_id;
+ wire interconnect$_io_slaves_1_aw_bits_user;
+ wire interconnect$_io_slaves_1_w_ready;
+ wire interconnect$_io_slaves_1_w_valid;
+ wire [63:0] interconnect$_io_slaves_1_w_bits_data;
+ wire interconnect$_io_slaves_1_w_bits_last;
+ wire [7:0] interconnect$_io_slaves_1_w_bits_strb;
+ wire interconnect$_io_slaves_1_w_bits_user;
+ wire interconnect$_io_slaves_1_b_ready;
+ wire interconnect$_io_slaves_1_b_valid;
+ wire [1:0] interconnect$_io_slaves_1_b_bits_resp;
+ wire [4:0] interconnect$_io_slaves_1_b_bits_id;
+ wire interconnect$_io_slaves_1_b_bits_user;
+ wire interconnect$_io_slaves_1_ar_ready;
+ wire interconnect$_io_slaves_1_ar_valid;
+ wire [31:0] interconnect$_io_slaves_1_ar_bits_addr;
+ wire [7:0] interconnect$_io_slaves_1_ar_bits_len;
+ wire [2:0] interconnect$_io_slaves_1_ar_bits_size;
+ wire [1:0] interconnect$_io_slaves_1_ar_bits_burst;
+ wire interconnect$_io_slaves_1_ar_bits_lock;
+ wire [3:0] interconnect$_io_slaves_1_ar_bits_cache;
+ wire [2:0] interconnect$_io_slaves_1_ar_bits_prot;
+ wire [3:0] interconnect$_io_slaves_1_ar_bits_qos;
+ wire [3:0] interconnect$_io_slaves_1_ar_bits_region;
+ wire [4:0] interconnect$_io_slaves_1_ar_bits_id;
+ wire interconnect$_io_slaves_1_ar_bits_user;
+ wire interconnect$_io_slaves_1_r_ready;
+ wire interconnect$_io_slaves_1_r_valid;
+ wire [1:0] interconnect$_io_slaves_1_r_bits_resp;
+ wire [63:0] interconnect$_io_slaves_1_r_bits_data;
+ wire interconnect$_io_slaves_1_r_bits_last;
+ wire [4:0] interconnect$_io_slaves_1_r_bits_id;
+ wire interconnect$_io_slaves_1_r_bits_user;
+ wire interconnect$_io_slaves_2_aw_ready;
+ wire interconnect$_io_slaves_2_aw_valid;
+ wire [31:0] interconnect$_io_slaves_2_aw_bits_addr;
+ wire [7:0] interconnect$_io_slaves_2_aw_bits_len;
+ wire [2:0] interconnect$_io_slaves_2_aw_bits_size;
+ wire [1:0] interconnect$_io_slaves_2_aw_bits_burst;
+ wire interconnect$_io_slaves_2_aw_bits_lock;
+ wire [3:0] interconnect$_io_slaves_2_aw_bits_cache;
+ wire [2:0] interconnect$_io_slaves_2_aw_bits_prot;
+ wire [3:0] interconnect$_io_slaves_2_aw_bits_qos;
+ wire [3:0] interconnect$_io_slaves_2_aw_bits_region;
+ wire [4:0] interconnect$_io_slaves_2_aw_bits_id;
+ wire interconnect$_io_slaves_2_aw_bits_user;
+ wire interconnect$_io_slaves_2_w_ready;
+ wire interconnect$_io_slaves_2_w_valid;
+ wire [63:0] interconnect$_io_slaves_2_w_bits_data;
+ wire interconnect$_io_slaves_2_w_bits_last;
+ wire [7:0] interconnect$_io_slaves_2_w_bits_strb;
+ wire interconnect$_io_slaves_2_w_bits_user;
+ wire interconnect$_io_slaves_2_b_ready;
+ wire interconnect$_io_slaves_2_b_valid;
+ wire [1:0] interconnect$_io_slaves_2_b_bits_resp;
+ wire [4:0] interconnect$_io_slaves_2_b_bits_id;
+ wire interconnect$_io_slaves_2_b_bits_user;
+ wire interconnect$_io_slaves_2_ar_ready;
+ wire interconnect$_io_slaves_2_ar_valid;
+ wire [31:0] interconnect$_io_slaves_2_ar_bits_addr;
+ wire [7:0] interconnect$_io_slaves_2_ar_bits_len;
+ wire [2:0] interconnect$_io_slaves_2_ar_bits_size;
+ wire [1:0] interconnect$_io_slaves_2_ar_bits_burst;
+ wire interconnect$_io_slaves_2_ar_bits_lock;
+ wire [3:0] interconnect$_io_slaves_2_ar_bits_cache;
+ wire [2:0] interconnect$_io_slaves_2_ar_bits_prot;
+ wire [3:0] interconnect$_io_slaves_2_ar_bits_qos;
+ wire [3:0] interconnect$_io_slaves_2_ar_bits_region;
+ wire [4:0] interconnect$_io_slaves_2_ar_bits_id;
+ wire interconnect$_io_slaves_2_ar_bits_user;
+ wire interconnect$_io_slaves_2_r_ready;
+ wire interconnect$_io_slaves_2_r_valid;
+ wire [1:0] interconnect$_io_slaves_2_r_bits_resp;
+ wire [63:0] interconnect$_io_slaves_2_r_bits_data;
+ wire interconnect$_io_slaves_2_r_bits_last;
+ wire [4:0] interconnect$_io_slaves_2_r_bits_id;
+ wire interconnect$_io_slaves_2_r_bits_user;
+ wire interconnect$_io_slaves_3_aw_ready;
+ wire interconnect$_io_slaves_3_aw_valid;
+ wire [31:0] interconnect$_io_slaves_3_aw_bits_addr;
+ wire [7:0] interconnect$_io_slaves_3_aw_bits_len;
+ wire [2:0] interconnect$_io_slaves_3_aw_bits_size;
+ wire [1:0] interconnect$_io_slaves_3_aw_bits_burst;
+ wire interconnect$_io_slaves_3_aw_bits_lock;
+ wire [3:0] interconnect$_io_slaves_3_aw_bits_cache;
+ wire [2:0] interconnect$_io_slaves_3_aw_bits_prot;
+ wire [3:0] interconnect$_io_slaves_3_aw_bits_qos;
+ wire [3:0] interconnect$_io_slaves_3_aw_bits_region;
+ wire [4:0] interconnect$_io_slaves_3_aw_bits_id;
+ wire interconnect$_io_slaves_3_aw_bits_user;
+ wire interconnect$_io_slaves_3_w_ready;
+ wire interconnect$_io_slaves_3_w_valid;
+ wire [63:0] interconnect$_io_slaves_3_w_bits_data;
+ wire interconnect$_io_slaves_3_w_bits_last;
+ wire [7:0] interconnect$_io_slaves_3_w_bits_strb;
+ wire interconnect$_io_slaves_3_w_bits_user;
+ wire interconnect$_io_slaves_3_b_ready;
+ wire interconnect$_io_slaves_3_b_valid;
+ wire [1:0] interconnect$_io_slaves_3_b_bits_resp;
+ wire [4:0] interconnect$_io_slaves_3_b_bits_id;
+ wire interconnect$_io_slaves_3_b_bits_user;
+ wire interconnect$_io_slaves_3_ar_ready;
+ wire interconnect$_io_slaves_3_ar_valid;
+ wire [31:0] interconnect$_io_slaves_3_ar_bits_addr;
+ wire [7:0] interconnect$_io_slaves_3_ar_bits_len;
+ wire [2:0] interconnect$_io_slaves_3_ar_bits_size;
+ wire [1:0] interconnect$_io_slaves_3_ar_bits_burst;
+ wire interconnect$_io_slaves_3_ar_bits_lock;
+ wire [3:0] interconnect$_io_slaves_3_ar_bits_cache;
+ wire [2:0] interconnect$_io_slaves_3_ar_bits_prot;
+ wire [3:0] interconnect$_io_slaves_3_ar_bits_qos;
+ wire [3:0] interconnect$_io_slaves_3_ar_bits_region;
+ wire [4:0] interconnect$_io_slaves_3_ar_bits_id;
+ wire interconnect$_io_slaves_3_ar_bits_user;
+ wire interconnect$_io_slaves_3_r_ready;
+ wire interconnect$_io_slaves_3_r_valid;
+ wire [1:0] interconnect$_io_slaves_3_r_bits_resp;
+ wire [63:0] interconnect$_io_slaves_3_r_bits_data;
+ wire interconnect$_io_slaves_3_r_bits_last;
+ wire [4:0] interconnect$_io_slaves_3_r_bits_id;
+ wire interconnect$_io_slaves_3_r_bits_user;
+ wire interconnect$_io_slaves_4_aw_ready;
+ wire interconnect$_io_slaves_4_aw_valid;
+ wire [31:0] interconnect$_io_slaves_4_aw_bits_addr;
+ wire [7:0] interconnect$_io_slaves_4_aw_bits_len;
+ wire [2:0] interconnect$_io_slaves_4_aw_bits_size;
+ wire [1:0] interconnect$_io_slaves_4_aw_bits_burst;
+ wire interconnect$_io_slaves_4_aw_bits_lock;
+ wire [3:0] interconnect$_io_slaves_4_aw_bits_cache;
+ wire [2:0] interconnect$_io_slaves_4_aw_bits_prot;
+ wire [3:0] interconnect$_io_slaves_4_aw_bits_qos;
+ wire [3:0] interconnect$_io_slaves_4_aw_bits_region;
+ wire [4:0] interconnect$_io_slaves_4_aw_bits_id;
+ wire interconnect$_io_slaves_4_aw_bits_user;
+ wire interconnect$_io_slaves_4_w_ready;
+ wire interconnect$_io_slaves_4_w_valid;
+ wire [63:0] interconnect$_io_slaves_4_w_bits_data;
+ wire interconnect$_io_slaves_4_w_bits_last;
+ wire [7:0] interconnect$_io_slaves_4_w_bits_strb;
+ wire interconnect$_io_slaves_4_w_bits_user;
+ wire interconnect$_io_slaves_4_b_ready;
+ wire interconnect$_io_slaves_4_b_valid;
+ wire [1:0] interconnect$_io_slaves_4_b_bits_resp;
+ wire [4:0] interconnect$_io_slaves_4_b_bits_id;
+ wire interconnect$_io_slaves_4_b_bits_user;
+ wire interconnect$_io_slaves_4_ar_ready;
+ wire interconnect$_io_slaves_4_ar_valid;
+ wire [31:0] interconnect$_io_slaves_4_ar_bits_addr;
+ wire [7:0] interconnect$_io_slaves_4_ar_bits_len;
+ wire [2:0] interconnect$_io_slaves_4_ar_bits_size;
+ wire [1:0] interconnect$_io_slaves_4_ar_bits_burst;
+ wire interconnect$_io_slaves_4_ar_bits_lock;
+ wire [3:0] interconnect$_io_slaves_4_ar_bits_cache;
+ wire [2:0] interconnect$_io_slaves_4_ar_bits_prot;
+ wire [3:0] interconnect$_io_slaves_4_ar_bits_qos;
+ wire [3:0] interconnect$_io_slaves_4_ar_bits_region;
+ wire [4:0] interconnect$_io_slaves_4_ar_bits_id;
+ wire interconnect$_io_slaves_4_ar_bits_user;
+ wire interconnect$_io_slaves_4_r_ready;
+ wire interconnect$_io_slaves_4_r_valid;
+ wire [1:0] interconnect$_io_slaves_4_r_bits_resp;
+ wire [63:0] interconnect$_io_slaves_4_r_bits_data;
+ wire interconnect$_io_slaves_4_r_bits_last;
+ wire [4:0] interconnect$_io_slaves_4_r_bits_id;
+ wire interconnect$_io_slaves_4_r_bits_user;
+ wire T_8069_clk;
+ wire T_8069_reset;
+ wire T_8069_io_in_acquire_ready;
+ wire T_8069_io_in_acquire_valid;
+ wire [25:0] T_8069_io_in_acquire_bits_addr_block;
+ wire [3:0] T_8069_io_in_acquire_bits_client_xact_id;
+ wire [1:0] T_8069_io_in_acquire_bits_addr_beat;
+ wire T_8069_io_in_acquire_bits_is_builtin_type;
+ wire [2:0] T_8069_io_in_acquire_bits_a_type;
+ wire [16:0] T_8069_io_in_acquire_bits_union;
+ wire [127:0] T_8069_io_in_acquire_bits_data;
+ wire T_8069_io_in_grant_ready;
+ wire T_8069_io_in_grant_valid;
+ wire [1:0] T_8069_io_in_grant_bits_addr_beat;
+ wire [3:0] T_8069_io_in_grant_bits_client_xact_id;
+ wire T_8069_io_in_grant_bits_manager_xact_id;
+ wire T_8069_io_in_grant_bits_is_builtin_type;
+ wire [3:0] T_8069_io_in_grant_bits_g_type;
+ wire [127:0] T_8069_io_in_grant_bits_data;
+ wire T_8069_io_in_probe_ready;
+ wire T_8069_io_in_probe_valid;
+ wire [25:0] T_8069_io_in_probe_bits_addr_block;
+ wire [1:0] T_8069_io_in_probe_bits_p_type;
+ wire T_8069_io_in_release_ready;
+ wire T_8069_io_in_release_valid;
+ wire [1:0] T_8069_io_in_release_bits_addr_beat;
+ wire [25:0] T_8069_io_in_release_bits_addr_block;
+ wire [3:0] T_8069_io_in_release_bits_client_xact_id;
+ wire T_8069_io_in_release_bits_voluntary;
+ wire [2:0] T_8069_io_in_release_bits_r_type;
+ wire [127:0] T_8069_io_in_release_bits_data;
+ wire T_8069_io_out_acquire_ready;
+ wire T_8069_io_out_acquire_valid;
+ wire [25:0] T_8069_io_out_acquire_bits_addr_block;
+ wire [3:0] T_8069_io_out_acquire_bits_client_xact_id;
+ wire [1:0] T_8069_io_out_acquire_bits_addr_beat;
+ wire T_8069_io_out_acquire_bits_is_builtin_type;
+ wire [2:0] T_8069_io_out_acquire_bits_a_type;
+ wire [16:0] T_8069_io_out_acquire_bits_union;
+ wire [127:0] T_8069_io_out_acquire_bits_data;
+ wire T_8069_io_out_grant_ready;
+ wire T_8069_io_out_grant_valid;
+ wire [1:0] T_8069_io_out_grant_bits_addr_beat;
+ wire [3:0] T_8069_io_out_grant_bits_client_xact_id;
+ wire T_8069_io_out_grant_bits_manager_xact_id;
+ wire T_8069_io_out_grant_bits_is_builtin_type;
+ wire [3:0] T_8069_io_out_grant_bits_g_type;
+ wire [127:0] T_8069_io_out_grant_bits_data;
+ wire T_8070_clk;
+ wire T_8070_reset;
+ wire T_8070_io_in_acquire_ready;
+ wire T_8070_io_in_acquire_valid;
+ wire [25:0] T_8070_io_in_acquire_bits_addr_block;
+ wire [3:0] T_8070_io_in_acquire_bits_client_xact_id;
+ wire [1:0] T_8070_io_in_acquire_bits_addr_beat;
+ wire T_8070_io_in_acquire_bits_is_builtin_type;
+ wire [2:0] T_8070_io_in_acquire_bits_a_type;
+ wire [16:0] T_8070_io_in_acquire_bits_union;
+ wire [127:0] T_8070_io_in_acquire_bits_data;
+ wire T_8070_io_in_grant_ready;
+ wire T_8070_io_in_grant_valid;
+ wire [1:0] T_8070_io_in_grant_bits_addr_beat;
+ wire [3:0] T_8070_io_in_grant_bits_client_xact_id;
+ wire T_8070_io_in_grant_bits_manager_xact_id;
+ wire T_8070_io_in_grant_bits_is_builtin_type;
+ wire [3:0] T_8070_io_in_grant_bits_g_type;
+ wire [127:0] T_8070_io_in_grant_bits_data;
+ wire T_8070_io_out_acquire_ready;
+ wire T_8070_io_out_acquire_valid;
+ wire [25:0] T_8070_io_out_acquire_bits_addr_block;
+ wire [3:0] T_8070_io_out_acquire_bits_client_xact_id;
+ wire [2:0] T_8070_io_out_acquire_bits_addr_beat;
+ wire T_8070_io_out_acquire_bits_is_builtin_type;
+ wire [2:0] T_8070_io_out_acquire_bits_a_type;
+ wire [11:0] T_8070_io_out_acquire_bits_union;
+ wire [63:0] T_8070_io_out_acquire_bits_data;
+ wire T_8070_io_out_grant_ready;
+ wire T_8070_io_out_grant_valid;
+ wire [2:0] T_8070_io_out_grant_bits_addr_beat;
+ wire [3:0] T_8070_io_out_grant_bits_client_xact_id;
+ wire T_8070_io_out_grant_bits_manager_xact_id;
+ wire T_8070_io_out_grant_bits_is_builtin_type;
+ wire [3:0] T_8070_io_out_grant_bits_g_type;
+ wire [63:0] T_8070_io_out_grant_bits_data;
+ wire T_8071_clk;
+ wire T_8071_reset;
+ wire T_8071_io_tl_acquire_ready;
+ wire T_8071_io_tl_acquire_valid;
+ wire [25:0] T_8071_io_tl_acquire_bits_addr_block;
+ wire [3:0] T_8071_io_tl_acquire_bits_client_xact_id;
+ wire [2:0] T_8071_io_tl_acquire_bits_addr_beat;
+ wire T_8071_io_tl_acquire_bits_is_builtin_type;
+ wire [2:0] T_8071_io_tl_acquire_bits_a_type;
+ wire [11:0] T_8071_io_tl_acquire_bits_union;
+ wire [63:0] T_8071_io_tl_acquire_bits_data;
+ wire T_8071_io_tl_grant_ready;
+ wire T_8071_io_tl_grant_valid;
+ wire [2:0] T_8071_io_tl_grant_bits_addr_beat;
+ wire [3:0] T_8071_io_tl_grant_bits_client_xact_id;
+ wire T_8071_io_tl_grant_bits_manager_xact_id;
+ wire T_8071_io_tl_grant_bits_is_builtin_type;
+ wire [3:0] T_8071_io_tl_grant_bits_g_type;
+ wire [63:0] T_8071_io_tl_grant_bits_data;
+ wire T_8071_io_nasti_aw_ready;
+ wire T_8071_io_nasti_aw_valid;
+ wire [31:0] T_8071_io_nasti_aw_bits_addr;
+ wire [7:0] T_8071_io_nasti_aw_bits_len;
+ wire [2:0] T_8071_io_nasti_aw_bits_size;
+ wire [1:0] T_8071_io_nasti_aw_bits_burst;
+ wire T_8071_io_nasti_aw_bits_lock;
+ wire [3:0] T_8071_io_nasti_aw_bits_cache;
+ wire [2:0] T_8071_io_nasti_aw_bits_prot;
+ wire [3:0] T_8071_io_nasti_aw_bits_qos;
+ wire [3:0] T_8071_io_nasti_aw_bits_region;
+ wire [4:0] T_8071_io_nasti_aw_bits_id;
+ wire T_8071_io_nasti_aw_bits_user;
+ wire T_8071_io_nasti_w_ready;
+ wire T_8071_io_nasti_w_valid;
+ wire [63:0] T_8071_io_nasti_w_bits_data;
+ wire T_8071_io_nasti_w_bits_last;
+ wire [7:0] T_8071_io_nasti_w_bits_strb;
+ wire T_8071_io_nasti_w_bits_user;
+ wire T_8071_io_nasti_b_ready;
+ wire T_8071_io_nasti_b_valid;
+ wire [1:0] T_8071_io_nasti_b_bits_resp;
+ wire [4:0] T_8071_io_nasti_b_bits_id;
+ wire T_8071_io_nasti_b_bits_user;
+ wire T_8071_io_nasti_ar_ready;
+ wire T_8071_io_nasti_ar_valid;
+ wire [31:0] T_8071_io_nasti_ar_bits_addr;
+ wire [7:0] T_8071_io_nasti_ar_bits_len;
+ wire [2:0] T_8071_io_nasti_ar_bits_size;
+ wire [1:0] T_8071_io_nasti_ar_bits_burst;
+ wire T_8071_io_nasti_ar_bits_lock;
+ wire [3:0] T_8071_io_nasti_ar_bits_cache;
+ wire [2:0] T_8071_io_nasti_ar_bits_prot;
+ wire [3:0] T_8071_io_nasti_ar_bits_qos;
+ wire [3:0] T_8071_io_nasti_ar_bits_region;
+ wire [4:0] T_8071_io_nasti_ar_bits_id;
+ wire T_8071_io_nasti_ar_bits_user;
+ wire T_8071_io_nasti_r_ready;
+ wire T_8071_io_nasti_r_valid;
+ wire [1:0] T_8071_io_nasti_r_bits_resp;
+ wire [63:0] T_8071_io_nasti_r_bits_data;
+ wire T_8071_io_nasti_r_bits_last;
+ wire [4:0] T_8071_io_nasti_r_bits_id;
+ wire T_8071_io_nasti_r_bits_user;
+ wire T_8072_clk;
+ wire T_8072_reset;
+ wire T_8072_io_in_acquire_ready;
+ wire T_8072_io_in_acquire_valid;
+ wire [25:0] T_8072_io_in_acquire_bits_addr_block;
+ wire [3:0] T_8072_io_in_acquire_bits_client_xact_id;
+ wire [1:0] T_8072_io_in_acquire_bits_addr_beat;
+ wire T_8072_io_in_acquire_bits_is_builtin_type;
+ wire [2:0] T_8072_io_in_acquire_bits_a_type;
+ wire [16:0] T_8072_io_in_acquire_bits_union;
+ wire [127:0] T_8072_io_in_acquire_bits_data;
+ wire T_8072_io_in_grant_ready;
+ wire T_8072_io_in_grant_valid;
+ wire [1:0] T_8072_io_in_grant_bits_addr_beat;
+ wire [3:0] T_8072_io_in_grant_bits_client_xact_id;
+ wire T_8072_io_in_grant_bits_manager_xact_id;
+ wire T_8072_io_in_grant_bits_is_builtin_type;
+ wire [3:0] T_8072_io_in_grant_bits_g_type;
+ wire [127:0] T_8072_io_in_grant_bits_data;
+ wire T_8072_io_out_acquire_ready;
+ wire T_8072_io_out_acquire_valid;
+ wire [25:0] T_8072_io_out_acquire_bits_addr_block;
+ wire [3:0] T_8072_io_out_acquire_bits_client_xact_id;
+ wire [1:0] T_8072_io_out_acquire_bits_addr_beat;
+ wire T_8072_io_out_acquire_bits_is_builtin_type;
+ wire [2:0] T_8072_io_out_acquire_bits_a_type;
+ wire [16:0] T_8072_io_out_acquire_bits_union;
+ wire [127:0] T_8072_io_out_acquire_bits_data;
+ wire T_8072_io_out_grant_ready;
+ wire T_8072_io_out_grant_valid;
+ wire [1:0] T_8072_io_out_grant_bits_addr_beat;
+ wire [3:0] T_8072_io_out_grant_bits_client_xact_id;
+ wire T_8072_io_out_grant_bits_manager_xact_id;
+ wire T_8072_io_out_grant_bits_is_builtin_type;
+ wire [3:0] T_8072_io_out_grant_bits_g_type;
+ wire [127:0] T_8072_io_out_grant_bits_data;
+ wire T_8072_io_out_probe_ready;
+ wire T_8072_io_out_probe_valid;
+ wire [25:0] T_8072_io_out_probe_bits_addr_block;
+ wire [1:0] T_8072_io_out_probe_bits_p_type;
+ wire T_8072_io_out_release_ready;
+ wire T_8072_io_out_release_valid;
+ wire [1:0] T_8072_io_out_release_bits_addr_beat;
+ wire [25:0] T_8072_io_out_release_bits_addr_block;
+ wire [3:0] T_8072_io_out_release_bits_client_xact_id;
+ wire T_8072_io_out_release_bits_voluntary;
+ wire [2:0] T_8072_io_out_release_bits_r_type;
+ wire [127:0] T_8072_io_out_release_bits_data;
+ wire T_8073_clk;
+ wire T_8073_reset;
+ wire T_8073_io_inner_acquire_ready;
+ wire T_8073_io_inner_acquire_valid;
+ wire [25:0] T_8073_io_inner_acquire_bits_addr_block;
+ wire [3:0] T_8073_io_inner_acquire_bits_client_xact_id;
+ wire [1:0] T_8073_io_inner_acquire_bits_addr_beat;
+ wire T_8073_io_inner_acquire_bits_is_builtin_type;
+ wire [2:0] T_8073_io_inner_acquire_bits_a_type;
+ wire [16:0] T_8073_io_inner_acquire_bits_union;
+ wire [127:0] T_8073_io_inner_acquire_bits_data;
+ wire T_8073_io_inner_grant_ready;
+ wire T_8073_io_inner_grant_valid;
+ wire [1:0] T_8073_io_inner_grant_bits_addr_beat;
+ wire [3:0] T_8073_io_inner_grant_bits_client_xact_id;
+ wire T_8073_io_inner_grant_bits_manager_xact_id;
+ wire T_8073_io_inner_grant_bits_is_builtin_type;
+ wire [3:0] T_8073_io_inner_grant_bits_g_type;
+ wire [127:0] T_8073_io_inner_grant_bits_data;
+ wire T_8073_io_inner_probe_ready;
+ wire T_8073_io_inner_probe_valid;
+ wire [25:0] T_8073_io_inner_probe_bits_addr_block;
+ wire [1:0] T_8073_io_inner_probe_bits_p_type;
+ wire T_8073_io_inner_release_ready;
+ wire T_8073_io_inner_release_valid;
+ wire [1:0] T_8073_io_inner_release_bits_addr_beat;
+ wire [25:0] T_8073_io_inner_release_bits_addr_block;
+ wire [3:0] T_8073_io_inner_release_bits_client_xact_id;
+ wire T_8073_io_inner_release_bits_voluntary;
+ wire [2:0] T_8073_io_inner_release_bits_r_type;
+ wire [127:0] T_8073_io_inner_release_bits_data;
+ wire T_8073_io_outer_acquire_ready;
+ wire T_8073_io_outer_acquire_valid;
+ wire [25:0] T_8073_io_outer_acquire_bits_addr_block;
+ wire [3:0] T_8073_io_outer_acquire_bits_client_xact_id;
+ wire [1:0] T_8073_io_outer_acquire_bits_addr_beat;
+ wire T_8073_io_outer_acquire_bits_is_builtin_type;
+ wire [2:0] T_8073_io_outer_acquire_bits_a_type;
+ wire [16:0] T_8073_io_outer_acquire_bits_union;
+ wire [127:0] T_8073_io_outer_acquire_bits_data;
+ wire T_8073_io_outer_grant_ready;
+ wire T_8073_io_outer_grant_valid;
+ wire [1:0] T_8073_io_outer_grant_bits_addr_beat;
+ wire [3:0] T_8073_io_outer_grant_bits_client_xact_id;
+ wire T_8073_io_outer_grant_bits_manager_xact_id;
+ wire T_8073_io_outer_grant_bits_is_builtin_type;
+ wire [3:0] T_8073_io_outer_grant_bits_g_type;
+ wire [127:0] T_8073_io_outer_grant_bits_data;
+ wire T_8073_io_outer_probe_ready;
+ wire T_8073_io_outer_probe_valid;
+ wire [25:0] T_8073_io_outer_probe_bits_addr_block;
+ wire [1:0] T_8073_io_outer_probe_bits_p_type;
+ wire T_8073_io_outer_release_ready;
+ wire T_8073_io_outer_release_valid;
+ wire [1:0] T_8073_io_outer_release_bits_addr_beat;
+ wire [25:0] T_8073_io_outer_release_bits_addr_block;
+ wire [3:0] T_8073_io_outer_release_bits_client_xact_id;
+ wire T_8073_io_outer_release_bits_voluntary;
+ wire [2:0] T_8073_io_outer_release_bits_r_type;
+ wire [127:0] T_8073_io_outer_release_bits_data;
+ wire T_8086_clk;
+ wire T_8086_reset;
+ wire T_8086_io_enq_ready;
+ wire T_8086_io_enq_valid;
+ wire [31:0] T_8086_io_enq_bits_addr;
+ wire [7:0] T_8086_io_enq_bits_len;
+ wire [2:0] T_8086_io_enq_bits_size;
+ wire [1:0] T_8086_io_enq_bits_burst;
+ wire T_8086_io_enq_bits_lock;
+ wire [3:0] T_8086_io_enq_bits_cache;
+ wire [2:0] T_8086_io_enq_bits_prot;
+ wire [3:0] T_8086_io_enq_bits_qos;
+ wire [3:0] T_8086_io_enq_bits_region;
+ wire [4:0] T_8086_io_enq_bits_id;
+ wire T_8086_io_enq_bits_user;
+ wire T_8086_io_deq_ready;
+ wire T_8086_io_deq_valid;
+ wire [31:0] T_8086_io_deq_bits_addr;
+ wire [7:0] T_8086_io_deq_bits_len;
+ wire [2:0] T_8086_io_deq_bits_size;
+ wire [1:0] T_8086_io_deq_bits_burst;
+ wire T_8086_io_deq_bits_lock;
+ wire [3:0] T_8086_io_deq_bits_cache;
+ wire [2:0] T_8086_io_deq_bits_prot;
+ wire [3:0] T_8086_io_deq_bits_qos;
+ wire [3:0] T_8086_io_deq_bits_region;
+ wire [4:0] T_8086_io_deq_bits_id;
+ wire T_8086_io_deq_bits_user;
+ wire [1:0] T_8086_io_count;
+ wire T_8099_clk;
+ wire T_8099_reset;
+ wire T_8099_io_enq_ready;
+ wire T_8099_io_enq_valid;
+ wire [31:0] T_8099_io_enq_bits_addr;
+ wire [7:0] T_8099_io_enq_bits_len;
+ wire [2:0] T_8099_io_enq_bits_size;
+ wire [1:0] T_8099_io_enq_bits_burst;
+ wire T_8099_io_enq_bits_lock;
+ wire [3:0] T_8099_io_enq_bits_cache;
+ wire [2:0] T_8099_io_enq_bits_prot;
+ wire [3:0] T_8099_io_enq_bits_qos;
+ wire [3:0] T_8099_io_enq_bits_region;
+ wire [4:0] T_8099_io_enq_bits_id;
+ wire T_8099_io_enq_bits_user;
+ wire T_8099_io_deq_ready;
+ wire T_8099_io_deq_valid;
+ wire [31:0] T_8099_io_deq_bits_addr;
+ wire [7:0] T_8099_io_deq_bits_len;
+ wire [2:0] T_8099_io_deq_bits_size;
+ wire [1:0] T_8099_io_deq_bits_burst;
+ wire T_8099_io_deq_bits_lock;
+ wire [3:0] T_8099_io_deq_bits_cache;
+ wire [2:0] T_8099_io_deq_bits_prot;
+ wire [3:0] T_8099_io_deq_bits_qos;
+ wire [3:0] T_8099_io_deq_bits_region;
+ wire [4:0] T_8099_io_deq_bits_id;
+ wire T_8099_io_deq_bits_user;
+ wire [1:0] T_8099_io_count;
+ wire T_8105_clk;
+ wire T_8105_reset;
+ wire T_8105_io_enq_ready;
+ wire T_8105_io_enq_valid;
+ wire [63:0] T_8105_io_enq_bits_data;
+ wire T_8105_io_enq_bits_last;
+ wire [7:0] T_8105_io_enq_bits_strb;
+ wire T_8105_io_enq_bits_user;
+ wire T_8105_io_deq_ready;
+ wire T_8105_io_deq_valid;
+ wire [63:0] T_8105_io_deq_bits_data;
+ wire T_8105_io_deq_bits_last;
+ wire [7:0] T_8105_io_deq_bits_strb;
+ wire T_8105_io_deq_bits_user;
+ wire [3:0] T_8105_io_count;
+ wire T_8112_clk;
+ wire T_8112_reset;
+ wire T_8112_io_enq_ready;
+ wire T_8112_io_enq_valid;
+ wire [1:0] T_8112_io_enq_bits_resp;
+ wire [63:0] T_8112_io_enq_bits_data;
+ wire T_8112_io_enq_bits_last;
+ wire [4:0] T_8112_io_enq_bits_id;
+ wire T_8112_io_enq_bits_user;
+ wire T_8112_io_deq_ready;
+ wire T_8112_io_deq_valid;
+ wire [1:0] T_8112_io_deq_bits_resp;
+ wire [63:0] T_8112_io_deq_bits_data;
+ wire T_8112_io_deq_bits_last;
+ wire [4:0] T_8112_io_deq_bits_id;
+ wire T_8112_io_deq_bits_user;
+ wire [3:0] T_8112_io_count;
+ wire T_8117_clk;
+ wire T_8117_reset;
+ wire T_8117_io_enq_ready;
+ wire T_8117_io_enq_valid;
+ wire [1:0] T_8117_io_enq_bits_resp;
+ wire [4:0] T_8117_io_enq_bits_id;
+ wire T_8117_io_enq_bits_user;
+ wire T_8117_io_deq_ready;
+ wire T_8117_io_deq_valid;
+ wire [1:0] T_8117_io_deq_bits_resp;
+ wire [4:0] T_8117_io_deq_bits_id;
+ wire T_8117_io_deq_bits_user;
+ wire [1:0] T_8117_io_count;
+ wire rtc_clk;
+ wire rtc_reset;
+ wire rtc_io_aw_ready;
+ wire rtc_io_aw_valid;
+ wire [31:0] rtc_io_aw_bits_addr;
+ wire [7:0] rtc_io_aw_bits_len;
+ wire [2:0] rtc_io_aw_bits_size;
+ wire [1:0] rtc_io_aw_bits_burst;
+ wire rtc_io_aw_bits_lock;
+ wire [3:0] rtc_io_aw_bits_cache;
+ wire [2:0] rtc_io_aw_bits_prot;
+ wire [3:0] rtc_io_aw_bits_qos;
+ wire [3:0] rtc_io_aw_bits_region;
+ wire [4:0] rtc_io_aw_bits_id;
+ wire rtc_io_aw_bits_user;
+ wire rtc_io_w_ready;
+ wire rtc_io_w_valid;
+ wire [63:0] rtc_io_w_bits_data;
+ wire rtc_io_w_bits_last;
+ wire [7:0] rtc_io_w_bits_strb;
+ wire rtc_io_w_bits_user;
+ wire rtc_io_b_ready;
+ wire rtc_io_b_valid;
+ wire [1:0] rtc_io_b_bits_resp;
+ wire [4:0] rtc_io_b_bits_id;
+ wire rtc_io_b_bits_user;
+ wire rtc_io_ar_ready;
+ wire rtc_io_ar_valid;
+ wire [31:0] rtc_io_ar_bits_addr;
+ wire [7:0] rtc_io_ar_bits_len;
+ wire [2:0] rtc_io_ar_bits_size;
+ wire [1:0] rtc_io_ar_bits_burst;
+ wire rtc_io_ar_bits_lock;
+ wire [3:0] rtc_io_ar_bits_cache;
+ wire [2:0] rtc_io_ar_bits_prot;
+ wire [3:0] rtc_io_ar_bits_qos;
+ wire [3:0] rtc_io_ar_bits_region;
+ wire [4:0] rtc_io_ar_bits_id;
+ wire rtc_io_ar_bits_user;
+ wire rtc_io_r_ready;
+ wire rtc_io_r_valid;
+ wire [1:0] rtc_io_r_bits_resp;
+ wire [63:0] rtc_io_r_bits_data;
+ wire rtc_io_r_bits_last;
+ wire [4:0] rtc_io_r_bits_id;
+ wire rtc_io_r_bits_user;
+ wire T_8119_clk;
+ wire T_8119_reset;
+ wire T_8119_io_nasti_aw_ready;
+ wire T_8119_io_nasti_aw_valid;
+ wire [31:0] T_8119_io_nasti_aw_bits_addr;
+ wire [7:0] T_8119_io_nasti_aw_bits_len;
+ wire [2:0] T_8119_io_nasti_aw_bits_size;
+ wire [1:0] T_8119_io_nasti_aw_bits_burst;
+ wire T_8119_io_nasti_aw_bits_lock;
+ wire [3:0] T_8119_io_nasti_aw_bits_cache;
+ wire [2:0] T_8119_io_nasti_aw_bits_prot;
+ wire [3:0] T_8119_io_nasti_aw_bits_qos;
+ wire [3:0] T_8119_io_nasti_aw_bits_region;
+ wire [4:0] T_8119_io_nasti_aw_bits_id;
+ wire T_8119_io_nasti_aw_bits_user;
+ wire T_8119_io_nasti_w_ready;
+ wire T_8119_io_nasti_w_valid;
+ wire [63:0] T_8119_io_nasti_w_bits_data;
+ wire T_8119_io_nasti_w_bits_last;
+ wire [7:0] T_8119_io_nasti_w_bits_strb;
+ wire T_8119_io_nasti_w_bits_user;
+ wire T_8119_io_nasti_b_ready;
+ wire T_8119_io_nasti_b_valid;
+ wire [1:0] T_8119_io_nasti_b_bits_resp;
+ wire [4:0] T_8119_io_nasti_b_bits_id;
+ wire T_8119_io_nasti_b_bits_user;
+ wire T_8119_io_nasti_ar_ready;
+ wire T_8119_io_nasti_ar_valid;
+ wire [31:0] T_8119_io_nasti_ar_bits_addr;
+ wire [7:0] T_8119_io_nasti_ar_bits_len;
+ wire [2:0] T_8119_io_nasti_ar_bits_size;
+ wire [1:0] T_8119_io_nasti_ar_bits_burst;
+ wire T_8119_io_nasti_ar_bits_lock;
+ wire [3:0] T_8119_io_nasti_ar_bits_cache;
+ wire [2:0] T_8119_io_nasti_ar_bits_prot;
+ wire [3:0] T_8119_io_nasti_ar_bits_qos;
+ wire [3:0] T_8119_io_nasti_ar_bits_region;
+ wire [4:0] T_8119_io_nasti_ar_bits_id;
+ wire T_8119_io_nasti_ar_bits_user;
+ wire T_8119_io_nasti_r_ready;
+ wire T_8119_io_nasti_r_valid;
+ wire [1:0] T_8119_io_nasti_r_bits_resp;
+ wire [63:0] T_8119_io_nasti_r_bits_data;
+ wire T_8119_io_nasti_r_bits_last;
+ wire [4:0] T_8119_io_nasti_r_bits_id;
+ wire T_8119_io_nasti_r_bits_user;
+ wire T_8119_io_smi_req_ready;
+ wire T_8119_io_smi_req_valid;
+ wire T_8119_io_smi_req_bits_rw;
+ wire [11:0] T_8119_io_smi_req_bits_addr;
+ wire [63:0] T_8119_io_smi_req_bits_data;
+ wire T_8119_io_smi_resp_ready;
+ wire T_8119_io_smi_resp_valid;
+ wire [63:0] T_8119_io_smi_resp_bits;
+ wire src_conv_clk;
+ wire src_conv_reset;
+ wire src_conv_io_nasti_aw_ready;
+ wire src_conv_io_nasti_aw_valid;
+ wire [31:0] src_conv_io_nasti_aw_bits_addr;
+ wire [7:0] src_conv_io_nasti_aw_bits_len;
+ wire [2:0] src_conv_io_nasti_aw_bits_size;
+ wire [1:0] src_conv_io_nasti_aw_bits_burst;
+ wire src_conv_io_nasti_aw_bits_lock;
+ wire [3:0] src_conv_io_nasti_aw_bits_cache;
+ wire [2:0] src_conv_io_nasti_aw_bits_prot;
+ wire [3:0] src_conv_io_nasti_aw_bits_qos;
+ wire [3:0] src_conv_io_nasti_aw_bits_region;
+ wire [4:0] src_conv_io_nasti_aw_bits_id;
+ wire src_conv_io_nasti_aw_bits_user;
+ wire src_conv_io_nasti_w_ready;
+ wire src_conv_io_nasti_w_valid;
+ wire [63:0] src_conv_io_nasti_w_bits_data;
+ wire src_conv_io_nasti_w_bits_last;
+ wire [7:0] src_conv_io_nasti_w_bits_strb;
+ wire src_conv_io_nasti_w_bits_user;
+ wire src_conv_io_nasti_b_ready;
+ wire src_conv_io_nasti_b_valid;
+ wire [1:0] src_conv_io_nasti_b_bits_resp;
+ wire [4:0] src_conv_io_nasti_b_bits_id;
+ wire src_conv_io_nasti_b_bits_user;
+ wire src_conv_io_nasti_ar_ready;
+ wire src_conv_io_nasti_ar_valid;
+ wire [31:0] src_conv_io_nasti_ar_bits_addr;
+ wire [7:0] src_conv_io_nasti_ar_bits_len;
+ wire [2:0] src_conv_io_nasti_ar_bits_size;
+ wire [1:0] src_conv_io_nasti_ar_bits_burst;
+ wire src_conv_io_nasti_ar_bits_lock;
+ wire [3:0] src_conv_io_nasti_ar_bits_cache;
+ wire [2:0] src_conv_io_nasti_ar_bits_prot;
+ wire [3:0] src_conv_io_nasti_ar_bits_qos;
+ wire [3:0] src_conv_io_nasti_ar_bits_region;
+ wire [4:0] src_conv_io_nasti_ar_bits_id;
+ wire src_conv_io_nasti_ar_bits_user;
+ wire src_conv_io_nasti_r_ready;
+ wire src_conv_io_nasti_r_valid;
+ wire [1:0] src_conv_io_nasti_r_bits_resp;
+ wire [63:0] src_conv_io_nasti_r_bits_data;
+ wire src_conv_io_nasti_r_bits_last;
+ wire [4:0] src_conv_io_nasti_r_bits_id;
+ wire src_conv_io_nasti_r_bits_user;
+ wire src_conv_io_smi_req_ready;
+ wire src_conv_io_smi_req_valid;
+ wire src_conv_io_smi_req_bits_rw;
+ wire [5:0] src_conv_io_smi_req_bits_addr;
+ wire [63:0] src_conv_io_smi_req_bits_data;
+ wire src_conv_io_smi_resp_ready;
+ wire src_conv_io_smi_resp_valid;
+ wire [63:0] src_conv_io_smi_resp_bits;
+ wire T_8121_clk;
+ wire T_8121_reset;
+ wire T_8121_io_master_0_aw_ready;
+ wire T_8121_io_master_0_aw_valid;
+ wire [31:0] T_8121_io_master_0_aw_bits_addr;
+ wire [7:0] T_8121_io_master_0_aw_bits_len;
+ wire [2:0] T_8121_io_master_0_aw_bits_size;
+ wire [1:0] T_8121_io_master_0_aw_bits_burst;
+ wire T_8121_io_master_0_aw_bits_lock;
+ wire [3:0] T_8121_io_master_0_aw_bits_cache;
+ wire [2:0] T_8121_io_master_0_aw_bits_prot;
+ wire [3:0] T_8121_io_master_0_aw_bits_qos;
+ wire [3:0] T_8121_io_master_0_aw_bits_region;
+ wire [4:0] T_8121_io_master_0_aw_bits_id;
+ wire T_8121_io_master_0_aw_bits_user;
+ wire T_8121_io_master_0_w_ready;
+ wire T_8121_io_master_0_w_valid;
+ wire [63:0] T_8121_io_master_0_w_bits_data;
+ wire T_8121_io_master_0_w_bits_last;
+ wire [7:0] T_8121_io_master_0_w_bits_strb;
+ wire T_8121_io_master_0_w_bits_user;
+ wire T_8121_io_master_0_b_ready;
+ wire T_8121_io_master_0_b_valid;
+ wire [1:0] T_8121_io_master_0_b_bits_resp;
+ wire [4:0] T_8121_io_master_0_b_bits_id;
+ wire T_8121_io_master_0_b_bits_user;
+ wire T_8121_io_master_0_ar_ready;
+ wire T_8121_io_master_0_ar_valid;
+ wire [31:0] T_8121_io_master_0_ar_bits_addr;
+ wire [7:0] T_8121_io_master_0_ar_bits_len;
+ wire [2:0] T_8121_io_master_0_ar_bits_size;
+ wire [1:0] T_8121_io_master_0_ar_bits_burst;
+ wire T_8121_io_master_0_ar_bits_lock;
+ wire [3:0] T_8121_io_master_0_ar_bits_cache;
+ wire [2:0] T_8121_io_master_0_ar_bits_prot;
+ wire [3:0] T_8121_io_master_0_ar_bits_qos;
+ wire [3:0] T_8121_io_master_0_ar_bits_region;
+ wire [4:0] T_8121_io_master_0_ar_bits_id;
+ wire T_8121_io_master_0_ar_bits_user;
+ wire T_8121_io_master_0_r_ready;
+ wire T_8121_io_master_0_r_valid;
+ wire [1:0] T_8121_io_master_0_r_bits_resp;
+ wire [63:0] T_8121_io_master_0_r_bits_data;
+ wire T_8121_io_master_0_r_bits_last;
+ wire [4:0] T_8121_io_master_0_r_bits_id;
+ wire T_8121_io_master_0_r_bits_user;
+ wire T_8121_io_slave_aw_ready;
+ wire T_8121_io_slave_aw_valid;
+ wire [31:0] T_8121_io_slave_aw_bits_addr;
+ wire [7:0] T_8121_io_slave_aw_bits_len;
+ wire [2:0] T_8121_io_slave_aw_bits_size;
+ wire [1:0] T_8121_io_slave_aw_bits_burst;
+ wire T_8121_io_slave_aw_bits_lock;
+ wire [3:0] T_8121_io_slave_aw_bits_cache;
+ wire [2:0] T_8121_io_slave_aw_bits_prot;
+ wire [3:0] T_8121_io_slave_aw_bits_qos;
+ wire [3:0] T_8121_io_slave_aw_bits_region;
+ wire [4:0] T_8121_io_slave_aw_bits_id;
+ wire T_8121_io_slave_aw_bits_user;
+ wire T_8121_io_slave_w_ready;
+ wire T_8121_io_slave_w_valid;
+ wire [63:0] T_8121_io_slave_w_bits_data;
+ wire T_8121_io_slave_w_bits_last;
+ wire [7:0] T_8121_io_slave_w_bits_strb;
+ wire T_8121_io_slave_w_bits_user;
+ wire T_8121_io_slave_b_ready;
+ wire T_8121_io_slave_b_valid;
+ wire [1:0] T_8121_io_slave_b_bits_resp;
+ wire [4:0] T_8121_io_slave_b_bits_id;
+ wire T_8121_io_slave_b_bits_user;
+ wire T_8121_io_slave_ar_ready;
+ wire T_8121_io_slave_ar_valid;
+ wire [31:0] T_8121_io_slave_ar_bits_addr;
+ wire [7:0] T_8121_io_slave_ar_bits_len;
+ wire [2:0] T_8121_io_slave_ar_bits_size;
+ wire [1:0] T_8121_io_slave_ar_bits_burst;
+ wire T_8121_io_slave_ar_bits_lock;
+ wire [3:0] T_8121_io_slave_ar_bits_cache;
+ wire [2:0] T_8121_io_slave_ar_bits_prot;
+ wire [3:0] T_8121_io_slave_ar_bits_qos;
+ wire [3:0] T_8121_io_slave_ar_bits_region;
+ wire [4:0] T_8121_io_slave_ar_bits_id;
+ wire T_8121_io_slave_ar_bits_user;
+ wire T_8121_io_slave_r_ready;
+ wire T_8121_io_slave_r_valid;
+ wire [1:0] T_8121_io_slave_r_bits_resp;
+ wire [63:0] T_8121_io_slave_r_bits_data;
+ wire T_8121_io_slave_r_bits_last;
+ wire [4:0] T_8121_io_slave_r_bits_id;
+ wire T_8121_io_slave_r_bits_user;
+ wire T_8122_clk;
+ wire T_8122_reset;
+ wire T_8122_io_nasti_aw_ready;
+ wire T_8122_io_nasti_aw_valid;
+ wire [31:0] T_8122_io_nasti_aw_bits_addr;
+ wire [7:0] T_8122_io_nasti_aw_bits_len;
+ wire [2:0] T_8122_io_nasti_aw_bits_size;
+ wire [1:0] T_8122_io_nasti_aw_bits_burst;
+ wire T_8122_io_nasti_aw_bits_lock;
+ wire [3:0] T_8122_io_nasti_aw_bits_cache;
+ wire [2:0] T_8122_io_nasti_aw_bits_prot;
+ wire [3:0] T_8122_io_nasti_aw_bits_qos;
+ wire [3:0] T_8122_io_nasti_aw_bits_region;
+ wire [4:0] T_8122_io_nasti_aw_bits_id;
+ wire T_8122_io_nasti_aw_bits_user;
+ wire T_8122_io_nasti_w_ready;
+ wire T_8122_io_nasti_w_valid;
+ wire [63:0] T_8122_io_nasti_w_bits_data;
+ wire T_8122_io_nasti_w_bits_last;
+ wire [7:0] T_8122_io_nasti_w_bits_strb;
+ wire T_8122_io_nasti_w_bits_user;
+ wire T_8122_io_nasti_b_ready;
+ wire T_8122_io_nasti_b_valid;
+ wire [1:0] T_8122_io_nasti_b_bits_resp;
+ wire [4:0] T_8122_io_nasti_b_bits_id;
+ wire T_8122_io_nasti_b_bits_user;
+ wire T_8122_io_nasti_ar_ready;
+ wire T_8122_io_nasti_ar_valid;
+ wire [31:0] T_8122_io_nasti_ar_bits_addr;
+ wire [7:0] T_8122_io_nasti_ar_bits_len;
+ wire [2:0] T_8122_io_nasti_ar_bits_size;
+ wire [1:0] T_8122_io_nasti_ar_bits_burst;
+ wire T_8122_io_nasti_ar_bits_lock;
+ wire [3:0] T_8122_io_nasti_ar_bits_cache;
+ wire [2:0] T_8122_io_nasti_ar_bits_prot;
+ wire [3:0] T_8122_io_nasti_ar_bits_qos;
+ wire [3:0] T_8122_io_nasti_ar_bits_region;
+ wire [4:0] T_8122_io_nasti_ar_bits_id;
+ wire T_8122_io_nasti_ar_bits_user;
+ wire T_8122_io_nasti_r_ready;
+ wire T_8122_io_nasti_r_valid;
+ wire [1:0] T_8122_io_nasti_r_bits_resp;
+ wire [63:0] T_8122_io_nasti_r_bits_data;
+ wire T_8122_io_nasti_r_bits_last;
+ wire [4:0] T_8122_io_nasti_r_bits_id;
+ wire T_8122_io_nasti_r_bits_user;
+ wire T_8122_io_mem_req_cmd_ready;
+ wire T_8122_io_mem_req_cmd_valid;
+ wire [25:0] T_8122_io_mem_req_cmd_bits_addr;
+ wire [4:0] T_8122_io_mem_req_cmd_bits_tag;
+ wire T_8122_io_mem_req_cmd_bits_rw;
+ wire T_8122_io_mem_req_data_ready;
+ wire T_8122_io_mem_req_data_valid;
+ wire [63:0] T_8122_io_mem_req_data_bits_data;
+ wire T_8122_io_mem_resp_ready;
+ wire T_8122_io_mem_resp_valid;
+ wire [63:0] T_8122_io_mem_resp_bits_data;
+ wire [4:0] T_8122_io_mem_resp_bits_tag;
+ wire T_8123_clk;
+ wire T_8123_reset;
+ wire T_8123_io_wide_req_cmd_ready;
+ wire T_8123_io_wide_req_cmd_valid;
+ wire [25:0] T_8123_io_wide_req_cmd_bits_addr;
+ wire [4:0] T_8123_io_wide_req_cmd_bits_tag;
+ wire T_8123_io_wide_req_cmd_bits_rw;
+ wire T_8123_io_wide_req_data_ready;
+ wire T_8123_io_wide_req_data_valid;
+ wire [63:0] T_8123_io_wide_req_data_bits_data;
+ wire T_8123_io_wide_resp_ready;
+ wire T_8123_io_wide_resp_valid;
+ wire [63:0] T_8123_io_wide_resp_bits_data;
+ wire [4:0] T_8123_io_wide_resp_bits_tag;
+ wire T_8123_io_narrow_req_ready;
+ wire T_8123_io_narrow_req_valid;
+ wire [15:0] T_8123_io_narrow_req_bits;
+ wire T_8123_io_narrow_resp_valid;
+ wire [15:0] T_8123_io_narrow_resp_bits;
+ wire T_8124;
+ wire T_8126;
+ wire T_8127;
+ wire T_8128;
+ wire T_8129;
+ wire T_8131;
+ wire T_8132;
+ wire T_8133;
+ wire T_8134;
+ wire T_8136;
+ wire T_8137;
+ wire T_8138;
+ wire T_8139;
+ wire [1:0] T_8140_resp;
+ wire [4:0] T_8140_id;
+ wire T_8140_user;
+ wire T_8145;
+ wire T_8146;
+ wire T_8147;
+ wire T_8148;
+ wire [1:0] T_8149_resp;
+ wire [63:0] T_8149_data;
+ wire T_8149_last;
+ wire [4:0] T_8149_id;
+ wire T_8149_user;
+ wire T_8156;
+ wire T_8157;
+ wire T_8158;
+ reg GEN_0;
+ reg GEN_1;
+ reg [1:0] GEN_2;
+ reg [1:0] GEN_3;
+ ClientTileLinkIOWrapper T_8064 (
+ .clk(T_8064_clk),
+ .reset(T_8064_reset),
+ .io_in_acquire_ready(T_8064_io_in_acquire_ready),
+ .io_in_acquire_valid(T_8064_io_in_acquire_valid),
+ .io_in_acquire_bits_addr_block(T_8064_io_in_acquire_bits_addr_block),
+ .io_in_acquire_bits_client_xact_id(T_8064_io_in_acquire_bits_client_xact_id),
+ .io_in_acquire_bits_addr_beat(T_8064_io_in_acquire_bits_addr_beat),
+ .io_in_acquire_bits_is_builtin_type(T_8064_io_in_acquire_bits_is_builtin_type),
+ .io_in_acquire_bits_a_type(T_8064_io_in_acquire_bits_a_type),
+ .io_in_acquire_bits_union(T_8064_io_in_acquire_bits_union),
+ .io_in_acquire_bits_data(T_8064_io_in_acquire_bits_data),
+ .io_in_grant_ready(T_8064_io_in_grant_ready),
+ .io_in_grant_valid(T_8064_io_in_grant_valid),
+ .io_in_grant_bits_addr_beat(T_8064_io_in_grant_bits_addr_beat),
+ .io_in_grant_bits_client_xact_id(T_8064_io_in_grant_bits_client_xact_id),
+ .io_in_grant_bits_manager_xact_id(T_8064_io_in_grant_bits_manager_xact_id),
+ .io_in_grant_bits_is_builtin_type(T_8064_io_in_grant_bits_is_builtin_type),
+ .io_in_grant_bits_g_type(T_8064_io_in_grant_bits_g_type),
+ .io_in_grant_bits_data(T_8064_io_in_grant_bits_data),
+ .io_out_acquire_ready(T_8064_io_out_acquire_ready),
+ .io_out_acquire_valid(T_8064_io_out_acquire_valid),
+ .io_out_acquire_bits_addr_block(T_8064_io_out_acquire_bits_addr_block),
+ .io_out_acquire_bits_client_xact_id(T_8064_io_out_acquire_bits_client_xact_id),
+ .io_out_acquire_bits_addr_beat(T_8064_io_out_acquire_bits_addr_beat),
+ .io_out_acquire_bits_is_builtin_type(T_8064_io_out_acquire_bits_is_builtin_type),
+ .io_out_acquire_bits_a_type(T_8064_io_out_acquire_bits_a_type),
+ .io_out_acquire_bits_union(T_8064_io_out_acquire_bits_union),
+ .io_out_acquire_bits_data(T_8064_io_out_acquire_bits_data),
+ .io_out_grant_ready(T_8064_io_out_grant_ready),
+ .io_out_grant_valid(T_8064_io_out_grant_valid),
+ .io_out_grant_bits_addr_beat(T_8064_io_out_grant_bits_addr_beat),
+ .io_out_grant_bits_client_xact_id(T_8064_io_out_grant_bits_client_xact_id),
+ .io_out_grant_bits_manager_xact_id(T_8064_io_out_grant_bits_manager_xact_id),
+ .io_out_grant_bits_is_builtin_type(T_8064_io_out_grant_bits_is_builtin_type),
+ .io_out_grant_bits_g_type(T_8064_io_out_grant_bits_g_type),
+ .io_out_grant_bits_data(T_8064_io_out_grant_bits_data),
+ .io_out_probe_ready(T_8064_io_out_probe_ready),
+ .io_out_probe_valid(T_8064_io_out_probe_valid),
+ .io_out_probe_bits_addr_block(T_8064_io_out_probe_bits_addr_block),
+ .io_out_probe_bits_p_type(T_8064_io_out_probe_bits_p_type),
+ .io_out_release_ready(T_8064_io_out_release_ready),
+ .io_out_release_valid(T_8064_io_out_release_valid),
+ .io_out_release_bits_addr_beat(T_8064_io_out_release_bits_addr_beat),
+ .io_out_release_bits_addr_block(T_8064_io_out_release_bits_addr_block),
+ .io_out_release_bits_client_xact_id(T_8064_io_out_release_bits_client_xact_id),
+ .io_out_release_bits_voluntary(T_8064_io_out_release_bits_voluntary),
+ .io_out_release_bits_r_type(T_8064_io_out_release_bits_r_type),
+ .io_out_release_bits_data(T_8064_io_out_release_bits_data)
+ );
+ ClientTileLinkIOWrapper T_8065 (
+ .clk(T_8065_clk),
+ .reset(T_8065_reset),
+ .io_in_acquire_ready(T_8065_io_in_acquire_ready),
+ .io_in_acquire_valid(T_8065_io_in_acquire_valid),
+ .io_in_acquire_bits_addr_block(T_8065_io_in_acquire_bits_addr_block),
+ .io_in_acquire_bits_client_xact_id(T_8065_io_in_acquire_bits_client_xact_id),
+ .io_in_acquire_bits_addr_beat(T_8065_io_in_acquire_bits_addr_beat),
+ .io_in_acquire_bits_is_builtin_type(T_8065_io_in_acquire_bits_is_builtin_type),
+ .io_in_acquire_bits_a_type(T_8065_io_in_acquire_bits_a_type),
+ .io_in_acquire_bits_union(T_8065_io_in_acquire_bits_union),
+ .io_in_acquire_bits_data(T_8065_io_in_acquire_bits_data),
+ .io_in_grant_ready(T_8065_io_in_grant_ready),
+ .io_in_grant_valid(T_8065_io_in_grant_valid),
+ .io_in_grant_bits_addr_beat(T_8065_io_in_grant_bits_addr_beat),
+ .io_in_grant_bits_client_xact_id(T_8065_io_in_grant_bits_client_xact_id),
+ .io_in_grant_bits_manager_xact_id(T_8065_io_in_grant_bits_manager_xact_id),
+ .io_in_grant_bits_is_builtin_type(T_8065_io_in_grant_bits_is_builtin_type),
+ .io_in_grant_bits_g_type(T_8065_io_in_grant_bits_g_type),
+ .io_in_grant_bits_data(T_8065_io_in_grant_bits_data),
+ .io_out_acquire_ready(T_8065_io_out_acquire_ready),
+ .io_out_acquire_valid(T_8065_io_out_acquire_valid),
+ .io_out_acquire_bits_addr_block(T_8065_io_out_acquire_bits_addr_block),
+ .io_out_acquire_bits_client_xact_id(T_8065_io_out_acquire_bits_client_xact_id),
+ .io_out_acquire_bits_addr_beat(T_8065_io_out_acquire_bits_addr_beat),
+ .io_out_acquire_bits_is_builtin_type(T_8065_io_out_acquire_bits_is_builtin_type),
+ .io_out_acquire_bits_a_type(T_8065_io_out_acquire_bits_a_type),
+ .io_out_acquire_bits_union(T_8065_io_out_acquire_bits_union),
+ .io_out_acquire_bits_data(T_8065_io_out_acquire_bits_data),
+ .io_out_grant_ready(T_8065_io_out_grant_ready),
+ .io_out_grant_valid(T_8065_io_out_grant_valid),
+ .io_out_grant_bits_addr_beat(T_8065_io_out_grant_bits_addr_beat),
+ .io_out_grant_bits_client_xact_id(T_8065_io_out_grant_bits_client_xact_id),
+ .io_out_grant_bits_manager_xact_id(T_8065_io_out_grant_bits_manager_xact_id),
+ .io_out_grant_bits_is_builtin_type(T_8065_io_out_grant_bits_is_builtin_type),
+ .io_out_grant_bits_g_type(T_8065_io_out_grant_bits_g_type),
+ .io_out_grant_bits_data(T_8065_io_out_grant_bits_data),
+ .io_out_probe_ready(T_8065_io_out_probe_ready),
+ .io_out_probe_valid(T_8065_io_out_probe_valid),
+ .io_out_probe_bits_addr_block(T_8065_io_out_probe_bits_addr_block),
+ .io_out_probe_bits_p_type(T_8065_io_out_probe_bits_p_type),
+ .io_out_release_ready(T_8065_io_out_release_ready),
+ .io_out_release_valid(T_8065_io_out_release_valid),
+ .io_out_release_bits_addr_beat(T_8065_io_out_release_bits_addr_beat),
+ .io_out_release_bits_addr_block(T_8065_io_out_release_bits_addr_block),
+ .io_out_release_bits_client_xact_id(T_8065_io_out_release_bits_client_xact_id),
+ .io_out_release_bits_voluntary(T_8065_io_out_release_bits_voluntary),
+ .io_out_release_bits_r_type(T_8065_io_out_release_bits_r_type),
+ .io_out_release_bits_data(T_8065_io_out_release_bits_data)
+ );
+ RocketChipTileLinkArbiter l1tol2net (
+ .clk(l1tol2net_clk),
+ .reset(l1tol2net_reset),
+ .io_clients_0_acquire_ready(l1tol2net_io_clients_0_acquire_ready),
+ .io_clients_0_acquire_valid(l1tol2net_io_clients_0_acquire_valid),
+ .io_clients_0_acquire_bits_addr_block(l1tol2net_io_clients_0_acquire_bits_addr_block),
+ .io_clients_0_acquire_bits_client_xact_id(l1tol2net_io_clients_0_acquire_bits_client_xact_id),
+ .io_clients_0_acquire_bits_addr_beat(l1tol2net_io_clients_0_acquire_bits_addr_beat),
+ .io_clients_0_acquire_bits_is_builtin_type(l1tol2net_io_clients_0_acquire_bits_is_builtin_type),
+ .io_clients_0_acquire_bits_a_type(l1tol2net_io_clients_0_acquire_bits_a_type),
+ .io_clients_0_acquire_bits_union(l1tol2net_io_clients_0_acquire_bits_union),
+ .io_clients_0_acquire_bits_data(l1tol2net_io_clients_0_acquire_bits_data),
+ .io_clients_0_grant_ready(l1tol2net_io_clients_0_grant_ready),
+ .io_clients_0_grant_valid(l1tol2net_io_clients_0_grant_valid),
+ .io_clients_0_grant_bits_addr_beat(l1tol2net_io_clients_0_grant_bits_addr_beat),
+ .io_clients_0_grant_bits_client_xact_id(l1tol2net_io_clients_0_grant_bits_client_xact_id),
+ .io_clients_0_grant_bits_manager_xact_id(l1tol2net_io_clients_0_grant_bits_manager_xact_id),
+ .io_clients_0_grant_bits_is_builtin_type(l1tol2net_io_clients_0_grant_bits_is_builtin_type),
+ .io_clients_0_grant_bits_g_type(l1tol2net_io_clients_0_grant_bits_g_type),
+ .io_clients_0_grant_bits_data(l1tol2net_io_clients_0_grant_bits_data),
+ .io_clients_0_probe_ready(l1tol2net_io_clients_0_probe_ready),
+ .io_clients_0_probe_valid(l1tol2net_io_clients_0_probe_valid),
+ .io_clients_0_probe_bits_addr_block(l1tol2net_io_clients_0_probe_bits_addr_block),
+ .io_clients_0_probe_bits_p_type(l1tol2net_io_clients_0_probe_bits_p_type),
+ .io_clients_0_release_ready(l1tol2net_io_clients_0_release_ready),
+ .io_clients_0_release_valid(l1tol2net_io_clients_0_release_valid),
+ .io_clients_0_release_bits_addr_beat(l1tol2net_io_clients_0_release_bits_addr_beat),
+ .io_clients_0_release_bits_addr_block(l1tol2net_io_clients_0_release_bits_addr_block),
+ .io_clients_0_release_bits_client_xact_id(l1tol2net_io_clients_0_release_bits_client_xact_id),
+ .io_clients_0_release_bits_voluntary(l1tol2net_io_clients_0_release_bits_voluntary),
+ .io_clients_0_release_bits_r_type(l1tol2net_io_clients_0_release_bits_r_type),
+ .io_clients_0_release_bits_data(l1tol2net_io_clients_0_release_bits_data),
+ .io_clients_1_acquire_ready(l1tol2net_io_clients_1_acquire_ready),
+ .io_clients_1_acquire_valid(l1tol2net_io_clients_1_acquire_valid),
+ .io_clients_1_acquire_bits_addr_block(l1tol2net_io_clients_1_acquire_bits_addr_block),
+ .io_clients_1_acquire_bits_client_xact_id(l1tol2net_io_clients_1_acquire_bits_client_xact_id),
+ .io_clients_1_acquire_bits_addr_beat(l1tol2net_io_clients_1_acquire_bits_addr_beat),
+ .io_clients_1_acquire_bits_is_builtin_type(l1tol2net_io_clients_1_acquire_bits_is_builtin_type),
+ .io_clients_1_acquire_bits_a_type(l1tol2net_io_clients_1_acquire_bits_a_type),
+ .io_clients_1_acquire_bits_union(l1tol2net_io_clients_1_acquire_bits_union),
+ .io_clients_1_acquire_bits_data(l1tol2net_io_clients_1_acquire_bits_data),
+ .io_clients_1_grant_ready(l1tol2net_io_clients_1_grant_ready),
+ .io_clients_1_grant_valid(l1tol2net_io_clients_1_grant_valid),
+ .io_clients_1_grant_bits_addr_beat(l1tol2net_io_clients_1_grant_bits_addr_beat),
+ .io_clients_1_grant_bits_client_xact_id(l1tol2net_io_clients_1_grant_bits_client_xact_id),
+ .io_clients_1_grant_bits_manager_xact_id(l1tol2net_io_clients_1_grant_bits_manager_xact_id),
+ .io_clients_1_grant_bits_is_builtin_type(l1tol2net_io_clients_1_grant_bits_is_builtin_type),
+ .io_clients_1_grant_bits_g_type(l1tol2net_io_clients_1_grant_bits_g_type),
+ .io_clients_1_grant_bits_data(l1tol2net_io_clients_1_grant_bits_data),
+ .io_clients_1_probe_ready(l1tol2net_io_clients_1_probe_ready),
+ .io_clients_1_probe_valid(l1tol2net_io_clients_1_probe_valid),
+ .io_clients_1_probe_bits_addr_block(l1tol2net_io_clients_1_probe_bits_addr_block),
+ .io_clients_1_probe_bits_p_type(l1tol2net_io_clients_1_probe_bits_p_type),
+ .io_clients_1_release_ready(l1tol2net_io_clients_1_release_ready),
+ .io_clients_1_release_valid(l1tol2net_io_clients_1_release_valid),
+ .io_clients_1_release_bits_addr_beat(l1tol2net_io_clients_1_release_bits_addr_beat),
+ .io_clients_1_release_bits_addr_block(l1tol2net_io_clients_1_release_bits_addr_block),
+ .io_clients_1_release_bits_client_xact_id(l1tol2net_io_clients_1_release_bits_client_xact_id),
+ .io_clients_1_release_bits_voluntary(l1tol2net_io_clients_1_release_bits_voluntary),
+ .io_clients_1_release_bits_r_type(l1tol2net_io_clients_1_release_bits_r_type),
+ .io_clients_1_release_bits_data(l1tol2net_io_clients_1_release_bits_data),
+ .io_clients_2_acquire_ready(l1tol2net_io_clients_2_acquire_ready),
+ .io_clients_2_acquire_valid(l1tol2net_io_clients_2_acquire_valid),
+ .io_clients_2_acquire_bits_addr_block(l1tol2net_io_clients_2_acquire_bits_addr_block),
+ .io_clients_2_acquire_bits_client_xact_id(l1tol2net_io_clients_2_acquire_bits_client_xact_id),
+ .io_clients_2_acquire_bits_addr_beat(l1tol2net_io_clients_2_acquire_bits_addr_beat),
+ .io_clients_2_acquire_bits_is_builtin_type(l1tol2net_io_clients_2_acquire_bits_is_builtin_type),
+ .io_clients_2_acquire_bits_a_type(l1tol2net_io_clients_2_acquire_bits_a_type),
+ .io_clients_2_acquire_bits_union(l1tol2net_io_clients_2_acquire_bits_union),
+ .io_clients_2_acquire_bits_data(l1tol2net_io_clients_2_acquire_bits_data),
+ .io_clients_2_grant_ready(l1tol2net_io_clients_2_grant_ready),
+ .io_clients_2_grant_valid(l1tol2net_io_clients_2_grant_valid),
+ .io_clients_2_grant_bits_addr_beat(l1tol2net_io_clients_2_grant_bits_addr_beat),
+ .io_clients_2_grant_bits_client_xact_id(l1tol2net_io_clients_2_grant_bits_client_xact_id),
+ .io_clients_2_grant_bits_manager_xact_id(l1tol2net_io_clients_2_grant_bits_manager_xact_id),
+ .io_clients_2_grant_bits_is_builtin_type(l1tol2net_io_clients_2_grant_bits_is_builtin_type),
+ .io_clients_2_grant_bits_g_type(l1tol2net_io_clients_2_grant_bits_g_type),
+ .io_clients_2_grant_bits_data(l1tol2net_io_clients_2_grant_bits_data),
+ .io_clients_2_probe_ready(l1tol2net_io_clients_2_probe_ready),
+ .io_clients_2_probe_valid(l1tol2net_io_clients_2_probe_valid),
+ .io_clients_2_probe_bits_addr_block(l1tol2net_io_clients_2_probe_bits_addr_block),
+ .io_clients_2_probe_bits_p_type(l1tol2net_io_clients_2_probe_bits_p_type),
+ .io_clients_2_release_ready(l1tol2net_io_clients_2_release_ready),
+ .io_clients_2_release_valid(l1tol2net_io_clients_2_release_valid),
+ .io_clients_2_release_bits_addr_beat(l1tol2net_io_clients_2_release_bits_addr_beat),
+ .io_clients_2_release_bits_addr_block(l1tol2net_io_clients_2_release_bits_addr_block),
+ .io_clients_2_release_bits_client_xact_id(l1tol2net_io_clients_2_release_bits_client_xact_id),
+ .io_clients_2_release_bits_voluntary(l1tol2net_io_clients_2_release_bits_voluntary),
+ .io_clients_2_release_bits_r_type(l1tol2net_io_clients_2_release_bits_r_type),
+ .io_clients_2_release_bits_data(l1tol2net_io_clients_2_release_bits_data),
+ .io_managers_0_acquire_ready(l1tol2net_io_managers_0_acquire_ready),
+ .io_managers_0_acquire_valid(l1tol2net_io_managers_0_acquire_valid),
+ .io_managers_0_acquire_bits_addr_block(l1tol2net_io_managers_0_acquire_bits_addr_block),
+ .io_managers_0_acquire_bits_client_xact_id(l1tol2net_io_managers_0_acquire_bits_client_xact_id),
+ .io_managers_0_acquire_bits_addr_beat(l1tol2net_io_managers_0_acquire_bits_addr_beat),
+ .io_managers_0_acquire_bits_is_builtin_type(l1tol2net_io_managers_0_acquire_bits_is_builtin_type),
+ .io_managers_0_acquire_bits_a_type(l1tol2net_io_managers_0_acquire_bits_a_type),
+ .io_managers_0_acquire_bits_union(l1tol2net_io_managers_0_acquire_bits_union),
+ .io_managers_0_acquire_bits_data(l1tol2net_io_managers_0_acquire_bits_data),
+ .io_managers_0_acquire_bits_client_id(l1tol2net_io_managers_0_acquire_bits_client_id),
+ .io_managers_0_grant_ready(l1tol2net_io_managers_0_grant_ready),
+ .io_managers_0_grant_valid(l1tol2net_io_managers_0_grant_valid),
+ .io_managers_0_grant_bits_addr_beat(l1tol2net_io_managers_0_grant_bits_addr_beat),
+ .io_managers_0_grant_bits_client_xact_id(l1tol2net_io_managers_0_grant_bits_client_xact_id),
+ .io_managers_0_grant_bits_manager_xact_id(l1tol2net_io_managers_0_grant_bits_manager_xact_id),
+ .io_managers_0_grant_bits_is_builtin_type(l1tol2net_io_managers_0_grant_bits_is_builtin_type),
+ .io_managers_0_grant_bits_g_type(l1tol2net_io_managers_0_grant_bits_g_type),
+ .io_managers_0_grant_bits_data(l1tol2net_io_managers_0_grant_bits_data),
+ .io_managers_0_grant_bits_client_id(l1tol2net_io_managers_0_grant_bits_client_id),
+ .io_managers_0_finish_ready(l1tol2net_io_managers_0_finish_ready),
+ .io_managers_0_finish_valid(l1tol2net_io_managers_0_finish_valid),
+ .io_managers_0_finish_bits_manager_xact_id(l1tol2net_io_managers_0_finish_bits_manager_xact_id),
+ .io_managers_0_probe_ready(l1tol2net_io_managers_0_probe_ready),
+ .io_managers_0_probe_valid(l1tol2net_io_managers_0_probe_valid),
+ .io_managers_0_probe_bits_addr_block(l1tol2net_io_managers_0_probe_bits_addr_block),
+ .io_managers_0_probe_bits_p_type(l1tol2net_io_managers_0_probe_bits_p_type),
+ .io_managers_0_probe_bits_client_id(l1tol2net_io_managers_0_probe_bits_client_id),
+ .io_managers_0_release_ready(l1tol2net_io_managers_0_release_ready),
+ .io_managers_0_release_valid(l1tol2net_io_managers_0_release_valid),
+ .io_managers_0_release_bits_addr_beat(l1tol2net_io_managers_0_release_bits_addr_beat),
+ .io_managers_0_release_bits_addr_block(l1tol2net_io_managers_0_release_bits_addr_block),
+ .io_managers_0_release_bits_client_xact_id(l1tol2net_io_managers_0_release_bits_client_xact_id),
+ .io_managers_0_release_bits_voluntary(l1tol2net_io_managers_0_release_bits_voluntary),
+ .io_managers_0_release_bits_r_type(l1tol2net_io_managers_0_release_bits_r_type),
+ .io_managers_0_release_bits_data(l1tol2net_io_managers_0_release_bits_data),
+ .io_managers_0_release_bits_client_id(l1tol2net_io_managers_0_release_bits_client_id)
+ );
+ L2BroadcastHub T_8067 (
+ .clk(T_8067_clk),
+ .reset(T_8067_reset),
+ .io_inner_acquire_ready(T_8067_io_inner_acquire_ready),
+ .io_inner_acquire_valid(T_8067_io_inner_acquire_valid),
+ .io_inner_acquire_bits_addr_block(T_8067_io_inner_acquire_bits_addr_block),
+ .io_inner_acquire_bits_client_xact_id(T_8067_io_inner_acquire_bits_client_xact_id),
+ .io_inner_acquire_bits_addr_beat(T_8067_io_inner_acquire_bits_addr_beat),
+ .io_inner_acquire_bits_is_builtin_type(T_8067_io_inner_acquire_bits_is_builtin_type),
+ .io_inner_acquire_bits_a_type(T_8067_io_inner_acquire_bits_a_type),
+ .io_inner_acquire_bits_union(T_8067_io_inner_acquire_bits_union),
+ .io_inner_acquire_bits_data(T_8067_io_inner_acquire_bits_data),
+ .io_inner_acquire_bits_client_id(T_8067_io_inner_acquire_bits_client_id),
+ .io_inner_grant_ready(T_8067_io_inner_grant_ready),
+ .io_inner_grant_valid(T_8067_io_inner_grant_valid),
+ .io_inner_grant_bits_addr_beat(T_8067_io_inner_grant_bits_addr_beat),
+ .io_inner_grant_bits_client_xact_id(T_8067_io_inner_grant_bits_client_xact_id),
+ .io_inner_grant_bits_manager_xact_id(T_8067_io_inner_grant_bits_manager_xact_id),
+ .io_inner_grant_bits_is_builtin_type(T_8067_io_inner_grant_bits_is_builtin_type),
+ .io_inner_grant_bits_g_type(T_8067_io_inner_grant_bits_g_type),
+ .io_inner_grant_bits_data(T_8067_io_inner_grant_bits_data),
+ .io_inner_grant_bits_client_id(T_8067_io_inner_grant_bits_client_id),
+ .io_inner_finish_ready(T_8067_io_inner_finish_ready),
+ .io_inner_finish_valid(T_8067_io_inner_finish_valid),
+ .io_inner_finish_bits_manager_xact_id(T_8067_io_inner_finish_bits_manager_xact_id),
+ .io_inner_probe_ready(T_8067_io_inner_probe_ready),
+ .io_inner_probe_valid(T_8067_io_inner_probe_valid),
+ .io_inner_probe_bits_addr_block(T_8067_io_inner_probe_bits_addr_block),
+ .io_inner_probe_bits_p_type(T_8067_io_inner_probe_bits_p_type),
+ .io_inner_probe_bits_client_id(T_8067_io_inner_probe_bits_client_id),
+ .io_inner_release_ready(T_8067_io_inner_release_ready),
+ .io_inner_release_valid(T_8067_io_inner_release_valid),
+ .io_inner_release_bits_addr_beat(T_8067_io_inner_release_bits_addr_beat),
+ .io_inner_release_bits_addr_block(T_8067_io_inner_release_bits_addr_block),
+ .io_inner_release_bits_client_xact_id(T_8067_io_inner_release_bits_client_xact_id),
+ .io_inner_release_bits_voluntary(T_8067_io_inner_release_bits_voluntary),
+ .io_inner_release_bits_r_type(T_8067_io_inner_release_bits_r_type),
+ .io_inner_release_bits_data(T_8067_io_inner_release_bits_data),
+ .io_inner_release_bits_client_id(T_8067_io_inner_release_bits_client_id),
+ .io_incoherent_0(T_8067_io_incoherent_0),
+ .io_outer_acquire_ready(T_8067_io_outer_acquire_ready),
+ .io_outer_acquire_valid(T_8067_io_outer_acquire_valid),
+ .io_outer_acquire_bits_addr_block(T_8067_io_outer_acquire_bits_addr_block),
+ .io_outer_acquire_bits_client_xact_id(T_8067_io_outer_acquire_bits_client_xact_id),
+ .io_outer_acquire_bits_addr_beat(T_8067_io_outer_acquire_bits_addr_beat),
+ .io_outer_acquire_bits_is_builtin_type(T_8067_io_outer_acquire_bits_is_builtin_type),
+ .io_outer_acquire_bits_a_type(T_8067_io_outer_acquire_bits_a_type),
+ .io_outer_acquire_bits_union(T_8067_io_outer_acquire_bits_union),
+ .io_outer_acquire_bits_data(T_8067_io_outer_acquire_bits_data),
+ .io_outer_grant_ready(T_8067_io_outer_grant_ready),
+ .io_outer_grant_valid(T_8067_io_outer_grant_valid),
+ .io_outer_grant_bits_addr_beat(T_8067_io_outer_grant_bits_addr_beat),
+ .io_outer_grant_bits_client_xact_id(T_8067_io_outer_grant_bits_client_xact_id),
+ .io_outer_grant_bits_manager_xact_id(T_8067_io_outer_grant_bits_manager_xact_id),
+ .io_outer_grant_bits_is_builtin_type(T_8067_io_outer_grant_bits_is_builtin_type),
+ .io_outer_grant_bits_g_type(T_8067_io_outer_grant_bits_g_type),
+ .io_outer_grant_bits_data(T_8067_io_outer_grant_bits_data)
+ );
+ NastiRecursiveInterconnect interconnect$ (
+ .clk(interconnect$_clk),
+ .reset(interconnect$_reset),
+ .io_masters_0_aw_ready(interconnect$_io_masters_0_aw_ready),
+ .io_masters_0_aw_valid(interconnect$_io_masters_0_aw_valid),
+ .io_masters_0_aw_bits_addr(interconnect$_io_masters_0_aw_bits_addr),
+ .io_masters_0_aw_bits_len(interconnect$_io_masters_0_aw_bits_len),
+ .io_masters_0_aw_bits_size(interconnect$_io_masters_0_aw_bits_size),
+ .io_masters_0_aw_bits_burst(interconnect$_io_masters_0_aw_bits_burst),
+ .io_masters_0_aw_bits_lock(interconnect$_io_masters_0_aw_bits_lock),
+ .io_masters_0_aw_bits_cache(interconnect$_io_masters_0_aw_bits_cache),
+ .io_masters_0_aw_bits_prot(interconnect$_io_masters_0_aw_bits_prot),
+ .io_masters_0_aw_bits_qos(interconnect$_io_masters_0_aw_bits_qos),
+ .io_masters_0_aw_bits_region(interconnect$_io_masters_0_aw_bits_region),
+ .io_masters_0_aw_bits_id(interconnect$_io_masters_0_aw_bits_id),
+ .io_masters_0_aw_bits_user(interconnect$_io_masters_0_aw_bits_user),
+ .io_masters_0_w_ready(interconnect$_io_masters_0_w_ready),
+ .io_masters_0_w_valid(interconnect$_io_masters_0_w_valid),
+ .io_masters_0_w_bits_data(interconnect$_io_masters_0_w_bits_data),
+ .io_masters_0_w_bits_last(interconnect$_io_masters_0_w_bits_last),
+ .io_masters_0_w_bits_strb(interconnect$_io_masters_0_w_bits_strb),
+ .io_masters_0_w_bits_user(interconnect$_io_masters_0_w_bits_user),
+ .io_masters_0_b_ready(interconnect$_io_masters_0_b_ready),
+ .io_masters_0_b_valid(interconnect$_io_masters_0_b_valid),
+ .io_masters_0_b_bits_resp(interconnect$_io_masters_0_b_bits_resp),
+ .io_masters_0_b_bits_id(interconnect$_io_masters_0_b_bits_id),
+ .io_masters_0_b_bits_user(interconnect$_io_masters_0_b_bits_user),
+ .io_masters_0_ar_ready(interconnect$_io_masters_0_ar_ready),
+ .io_masters_0_ar_valid(interconnect$_io_masters_0_ar_valid),
+ .io_masters_0_ar_bits_addr(interconnect$_io_masters_0_ar_bits_addr),
+ .io_masters_0_ar_bits_len(interconnect$_io_masters_0_ar_bits_len),
+ .io_masters_0_ar_bits_size(interconnect$_io_masters_0_ar_bits_size),
+ .io_masters_0_ar_bits_burst(interconnect$_io_masters_0_ar_bits_burst),
+ .io_masters_0_ar_bits_lock(interconnect$_io_masters_0_ar_bits_lock),
+ .io_masters_0_ar_bits_cache(interconnect$_io_masters_0_ar_bits_cache),
+ .io_masters_0_ar_bits_prot(interconnect$_io_masters_0_ar_bits_prot),
+ .io_masters_0_ar_bits_qos(interconnect$_io_masters_0_ar_bits_qos),
+ .io_masters_0_ar_bits_region(interconnect$_io_masters_0_ar_bits_region),
+ .io_masters_0_ar_bits_id(interconnect$_io_masters_0_ar_bits_id),
+ .io_masters_0_ar_bits_user(interconnect$_io_masters_0_ar_bits_user),
+ .io_masters_0_r_ready(interconnect$_io_masters_0_r_ready),
+ .io_masters_0_r_valid(interconnect$_io_masters_0_r_valid),
+ .io_masters_0_r_bits_resp(interconnect$_io_masters_0_r_bits_resp),
+ .io_masters_0_r_bits_data(interconnect$_io_masters_0_r_bits_data),
+ .io_masters_0_r_bits_last(interconnect$_io_masters_0_r_bits_last),
+ .io_masters_0_r_bits_id(interconnect$_io_masters_0_r_bits_id),
+ .io_masters_0_r_bits_user(interconnect$_io_masters_0_r_bits_user),
+ .io_masters_1_aw_ready(interconnect$_io_masters_1_aw_ready),
+ .io_masters_1_aw_valid(interconnect$_io_masters_1_aw_valid),
+ .io_masters_1_aw_bits_addr(interconnect$_io_masters_1_aw_bits_addr),
+ .io_masters_1_aw_bits_len(interconnect$_io_masters_1_aw_bits_len),
+ .io_masters_1_aw_bits_size(interconnect$_io_masters_1_aw_bits_size),
+ .io_masters_1_aw_bits_burst(interconnect$_io_masters_1_aw_bits_burst),
+ .io_masters_1_aw_bits_lock(interconnect$_io_masters_1_aw_bits_lock),
+ .io_masters_1_aw_bits_cache(interconnect$_io_masters_1_aw_bits_cache),
+ .io_masters_1_aw_bits_prot(interconnect$_io_masters_1_aw_bits_prot),
+ .io_masters_1_aw_bits_qos(interconnect$_io_masters_1_aw_bits_qos),
+ .io_masters_1_aw_bits_region(interconnect$_io_masters_1_aw_bits_region),
+ .io_masters_1_aw_bits_id(interconnect$_io_masters_1_aw_bits_id),
+ .io_masters_1_aw_bits_user(interconnect$_io_masters_1_aw_bits_user),
+ .io_masters_1_w_ready(interconnect$_io_masters_1_w_ready),
+ .io_masters_1_w_valid(interconnect$_io_masters_1_w_valid),
+ .io_masters_1_w_bits_data(interconnect$_io_masters_1_w_bits_data),
+ .io_masters_1_w_bits_last(interconnect$_io_masters_1_w_bits_last),
+ .io_masters_1_w_bits_strb(interconnect$_io_masters_1_w_bits_strb),
+ .io_masters_1_w_bits_user(interconnect$_io_masters_1_w_bits_user),
+ .io_masters_1_b_ready(interconnect$_io_masters_1_b_ready),
+ .io_masters_1_b_valid(interconnect$_io_masters_1_b_valid),
+ .io_masters_1_b_bits_resp(interconnect$_io_masters_1_b_bits_resp),
+ .io_masters_1_b_bits_id(interconnect$_io_masters_1_b_bits_id),
+ .io_masters_1_b_bits_user(interconnect$_io_masters_1_b_bits_user),
+ .io_masters_1_ar_ready(interconnect$_io_masters_1_ar_ready),
+ .io_masters_1_ar_valid(interconnect$_io_masters_1_ar_valid),
+ .io_masters_1_ar_bits_addr(interconnect$_io_masters_1_ar_bits_addr),
+ .io_masters_1_ar_bits_len(interconnect$_io_masters_1_ar_bits_len),
+ .io_masters_1_ar_bits_size(interconnect$_io_masters_1_ar_bits_size),
+ .io_masters_1_ar_bits_burst(interconnect$_io_masters_1_ar_bits_burst),
+ .io_masters_1_ar_bits_lock(interconnect$_io_masters_1_ar_bits_lock),
+ .io_masters_1_ar_bits_cache(interconnect$_io_masters_1_ar_bits_cache),
+ .io_masters_1_ar_bits_prot(interconnect$_io_masters_1_ar_bits_prot),
+ .io_masters_1_ar_bits_qos(interconnect$_io_masters_1_ar_bits_qos),
+ .io_masters_1_ar_bits_region(interconnect$_io_masters_1_ar_bits_region),
+ .io_masters_1_ar_bits_id(interconnect$_io_masters_1_ar_bits_id),
+ .io_masters_1_ar_bits_user(interconnect$_io_masters_1_ar_bits_user),
+ .io_masters_1_r_ready(interconnect$_io_masters_1_r_ready),
+ .io_masters_1_r_valid(interconnect$_io_masters_1_r_valid),
+ .io_masters_1_r_bits_resp(interconnect$_io_masters_1_r_bits_resp),
+ .io_masters_1_r_bits_data(interconnect$_io_masters_1_r_bits_data),
+ .io_masters_1_r_bits_last(interconnect$_io_masters_1_r_bits_last),
+ .io_masters_1_r_bits_id(interconnect$_io_masters_1_r_bits_id),
+ .io_masters_1_r_bits_user(interconnect$_io_masters_1_r_bits_user),
+ .io_slaves_0_aw_ready(interconnect$_io_slaves_0_aw_ready),
+ .io_slaves_0_aw_valid(interconnect$_io_slaves_0_aw_valid),
+ .io_slaves_0_aw_bits_addr(interconnect$_io_slaves_0_aw_bits_addr),
+ .io_slaves_0_aw_bits_len(interconnect$_io_slaves_0_aw_bits_len),
+ .io_slaves_0_aw_bits_size(interconnect$_io_slaves_0_aw_bits_size),
+ .io_slaves_0_aw_bits_burst(interconnect$_io_slaves_0_aw_bits_burst),
+ .io_slaves_0_aw_bits_lock(interconnect$_io_slaves_0_aw_bits_lock),
+ .io_slaves_0_aw_bits_cache(interconnect$_io_slaves_0_aw_bits_cache),
+ .io_slaves_0_aw_bits_prot(interconnect$_io_slaves_0_aw_bits_prot),
+ .io_slaves_0_aw_bits_qos(interconnect$_io_slaves_0_aw_bits_qos),
+ .io_slaves_0_aw_bits_region(interconnect$_io_slaves_0_aw_bits_region),
+ .io_slaves_0_aw_bits_id(interconnect$_io_slaves_0_aw_bits_id),
+ .io_slaves_0_aw_bits_user(interconnect$_io_slaves_0_aw_bits_user),
+ .io_slaves_0_w_ready(interconnect$_io_slaves_0_w_ready),
+ .io_slaves_0_w_valid(interconnect$_io_slaves_0_w_valid),
+ .io_slaves_0_w_bits_data(interconnect$_io_slaves_0_w_bits_data),
+ .io_slaves_0_w_bits_last(interconnect$_io_slaves_0_w_bits_last),
+ .io_slaves_0_w_bits_strb(interconnect$_io_slaves_0_w_bits_strb),
+ .io_slaves_0_w_bits_user(interconnect$_io_slaves_0_w_bits_user),
+ .io_slaves_0_b_ready(interconnect$_io_slaves_0_b_ready),
+ .io_slaves_0_b_valid(interconnect$_io_slaves_0_b_valid),
+ .io_slaves_0_b_bits_resp(interconnect$_io_slaves_0_b_bits_resp),
+ .io_slaves_0_b_bits_id(interconnect$_io_slaves_0_b_bits_id),
+ .io_slaves_0_b_bits_user(interconnect$_io_slaves_0_b_bits_user),
+ .io_slaves_0_ar_ready(interconnect$_io_slaves_0_ar_ready),
+ .io_slaves_0_ar_valid(interconnect$_io_slaves_0_ar_valid),
+ .io_slaves_0_ar_bits_addr(interconnect$_io_slaves_0_ar_bits_addr),
+ .io_slaves_0_ar_bits_len(interconnect$_io_slaves_0_ar_bits_len),
+ .io_slaves_0_ar_bits_size(interconnect$_io_slaves_0_ar_bits_size),
+ .io_slaves_0_ar_bits_burst(interconnect$_io_slaves_0_ar_bits_burst),
+ .io_slaves_0_ar_bits_lock(interconnect$_io_slaves_0_ar_bits_lock),
+ .io_slaves_0_ar_bits_cache(interconnect$_io_slaves_0_ar_bits_cache),
+ .io_slaves_0_ar_bits_prot(interconnect$_io_slaves_0_ar_bits_prot),
+ .io_slaves_0_ar_bits_qos(interconnect$_io_slaves_0_ar_bits_qos),
+ .io_slaves_0_ar_bits_region(interconnect$_io_slaves_0_ar_bits_region),
+ .io_slaves_0_ar_bits_id(interconnect$_io_slaves_0_ar_bits_id),
+ .io_slaves_0_ar_bits_user(interconnect$_io_slaves_0_ar_bits_user),
+ .io_slaves_0_r_ready(interconnect$_io_slaves_0_r_ready),
+ .io_slaves_0_r_valid(interconnect$_io_slaves_0_r_valid),
+ .io_slaves_0_r_bits_resp(interconnect$_io_slaves_0_r_bits_resp),
+ .io_slaves_0_r_bits_data(interconnect$_io_slaves_0_r_bits_data),
+ .io_slaves_0_r_bits_last(interconnect$_io_slaves_0_r_bits_last),
+ .io_slaves_0_r_bits_id(interconnect$_io_slaves_0_r_bits_id),
+ .io_slaves_0_r_bits_user(interconnect$_io_slaves_0_r_bits_user),
+ .io_slaves_1_aw_ready(interconnect$_io_slaves_1_aw_ready),
+ .io_slaves_1_aw_valid(interconnect$_io_slaves_1_aw_valid),
+ .io_slaves_1_aw_bits_addr(interconnect$_io_slaves_1_aw_bits_addr),
+ .io_slaves_1_aw_bits_len(interconnect$_io_slaves_1_aw_bits_len),
+ .io_slaves_1_aw_bits_size(interconnect$_io_slaves_1_aw_bits_size),
+ .io_slaves_1_aw_bits_burst(interconnect$_io_slaves_1_aw_bits_burst),
+ .io_slaves_1_aw_bits_lock(interconnect$_io_slaves_1_aw_bits_lock),
+ .io_slaves_1_aw_bits_cache(interconnect$_io_slaves_1_aw_bits_cache),
+ .io_slaves_1_aw_bits_prot(interconnect$_io_slaves_1_aw_bits_prot),
+ .io_slaves_1_aw_bits_qos(interconnect$_io_slaves_1_aw_bits_qos),
+ .io_slaves_1_aw_bits_region(interconnect$_io_slaves_1_aw_bits_region),
+ .io_slaves_1_aw_bits_id(interconnect$_io_slaves_1_aw_bits_id),
+ .io_slaves_1_aw_bits_user(interconnect$_io_slaves_1_aw_bits_user),
+ .io_slaves_1_w_ready(interconnect$_io_slaves_1_w_ready),
+ .io_slaves_1_w_valid(interconnect$_io_slaves_1_w_valid),
+ .io_slaves_1_w_bits_data(interconnect$_io_slaves_1_w_bits_data),
+ .io_slaves_1_w_bits_last(interconnect$_io_slaves_1_w_bits_last),
+ .io_slaves_1_w_bits_strb(interconnect$_io_slaves_1_w_bits_strb),
+ .io_slaves_1_w_bits_user(interconnect$_io_slaves_1_w_bits_user),
+ .io_slaves_1_b_ready(interconnect$_io_slaves_1_b_ready),
+ .io_slaves_1_b_valid(interconnect$_io_slaves_1_b_valid),
+ .io_slaves_1_b_bits_resp(interconnect$_io_slaves_1_b_bits_resp),
+ .io_slaves_1_b_bits_id(interconnect$_io_slaves_1_b_bits_id),
+ .io_slaves_1_b_bits_user(interconnect$_io_slaves_1_b_bits_user),
+ .io_slaves_1_ar_ready(interconnect$_io_slaves_1_ar_ready),
+ .io_slaves_1_ar_valid(interconnect$_io_slaves_1_ar_valid),
+ .io_slaves_1_ar_bits_addr(interconnect$_io_slaves_1_ar_bits_addr),
+ .io_slaves_1_ar_bits_len(interconnect$_io_slaves_1_ar_bits_len),
+ .io_slaves_1_ar_bits_size(interconnect$_io_slaves_1_ar_bits_size),
+ .io_slaves_1_ar_bits_burst(interconnect$_io_slaves_1_ar_bits_burst),
+ .io_slaves_1_ar_bits_lock(interconnect$_io_slaves_1_ar_bits_lock),
+ .io_slaves_1_ar_bits_cache(interconnect$_io_slaves_1_ar_bits_cache),
+ .io_slaves_1_ar_bits_prot(interconnect$_io_slaves_1_ar_bits_prot),
+ .io_slaves_1_ar_bits_qos(interconnect$_io_slaves_1_ar_bits_qos),
+ .io_slaves_1_ar_bits_region(interconnect$_io_slaves_1_ar_bits_region),
+ .io_slaves_1_ar_bits_id(interconnect$_io_slaves_1_ar_bits_id),
+ .io_slaves_1_ar_bits_user(interconnect$_io_slaves_1_ar_bits_user),
+ .io_slaves_1_r_ready(interconnect$_io_slaves_1_r_ready),
+ .io_slaves_1_r_valid(interconnect$_io_slaves_1_r_valid),
+ .io_slaves_1_r_bits_resp(interconnect$_io_slaves_1_r_bits_resp),
+ .io_slaves_1_r_bits_data(interconnect$_io_slaves_1_r_bits_data),
+ .io_slaves_1_r_bits_last(interconnect$_io_slaves_1_r_bits_last),
+ .io_slaves_1_r_bits_id(interconnect$_io_slaves_1_r_bits_id),
+ .io_slaves_1_r_bits_user(interconnect$_io_slaves_1_r_bits_user),
+ .io_slaves_2_aw_ready(interconnect$_io_slaves_2_aw_ready),
+ .io_slaves_2_aw_valid(interconnect$_io_slaves_2_aw_valid),
+ .io_slaves_2_aw_bits_addr(interconnect$_io_slaves_2_aw_bits_addr),
+ .io_slaves_2_aw_bits_len(interconnect$_io_slaves_2_aw_bits_len),
+ .io_slaves_2_aw_bits_size(interconnect$_io_slaves_2_aw_bits_size),
+ .io_slaves_2_aw_bits_burst(interconnect$_io_slaves_2_aw_bits_burst),
+ .io_slaves_2_aw_bits_lock(interconnect$_io_slaves_2_aw_bits_lock),
+ .io_slaves_2_aw_bits_cache(interconnect$_io_slaves_2_aw_bits_cache),
+ .io_slaves_2_aw_bits_prot(interconnect$_io_slaves_2_aw_bits_prot),
+ .io_slaves_2_aw_bits_qos(interconnect$_io_slaves_2_aw_bits_qos),
+ .io_slaves_2_aw_bits_region(interconnect$_io_slaves_2_aw_bits_region),
+ .io_slaves_2_aw_bits_id(interconnect$_io_slaves_2_aw_bits_id),
+ .io_slaves_2_aw_bits_user(interconnect$_io_slaves_2_aw_bits_user),
+ .io_slaves_2_w_ready(interconnect$_io_slaves_2_w_ready),
+ .io_slaves_2_w_valid(interconnect$_io_slaves_2_w_valid),
+ .io_slaves_2_w_bits_data(interconnect$_io_slaves_2_w_bits_data),
+ .io_slaves_2_w_bits_last(interconnect$_io_slaves_2_w_bits_last),
+ .io_slaves_2_w_bits_strb(interconnect$_io_slaves_2_w_bits_strb),
+ .io_slaves_2_w_bits_user(interconnect$_io_slaves_2_w_bits_user),
+ .io_slaves_2_b_ready(interconnect$_io_slaves_2_b_ready),
+ .io_slaves_2_b_valid(interconnect$_io_slaves_2_b_valid),
+ .io_slaves_2_b_bits_resp(interconnect$_io_slaves_2_b_bits_resp),
+ .io_slaves_2_b_bits_id(interconnect$_io_slaves_2_b_bits_id),
+ .io_slaves_2_b_bits_user(interconnect$_io_slaves_2_b_bits_user),
+ .io_slaves_2_ar_ready(interconnect$_io_slaves_2_ar_ready),
+ .io_slaves_2_ar_valid(interconnect$_io_slaves_2_ar_valid),
+ .io_slaves_2_ar_bits_addr(interconnect$_io_slaves_2_ar_bits_addr),
+ .io_slaves_2_ar_bits_len(interconnect$_io_slaves_2_ar_bits_len),
+ .io_slaves_2_ar_bits_size(interconnect$_io_slaves_2_ar_bits_size),
+ .io_slaves_2_ar_bits_burst(interconnect$_io_slaves_2_ar_bits_burst),
+ .io_slaves_2_ar_bits_lock(interconnect$_io_slaves_2_ar_bits_lock),
+ .io_slaves_2_ar_bits_cache(interconnect$_io_slaves_2_ar_bits_cache),
+ .io_slaves_2_ar_bits_prot(interconnect$_io_slaves_2_ar_bits_prot),
+ .io_slaves_2_ar_bits_qos(interconnect$_io_slaves_2_ar_bits_qos),
+ .io_slaves_2_ar_bits_region(interconnect$_io_slaves_2_ar_bits_region),
+ .io_slaves_2_ar_bits_id(interconnect$_io_slaves_2_ar_bits_id),
+ .io_slaves_2_ar_bits_user(interconnect$_io_slaves_2_ar_bits_user),
+ .io_slaves_2_r_ready(interconnect$_io_slaves_2_r_ready),
+ .io_slaves_2_r_valid(interconnect$_io_slaves_2_r_valid),
+ .io_slaves_2_r_bits_resp(interconnect$_io_slaves_2_r_bits_resp),
+ .io_slaves_2_r_bits_data(interconnect$_io_slaves_2_r_bits_data),
+ .io_slaves_2_r_bits_last(interconnect$_io_slaves_2_r_bits_last),
+ .io_slaves_2_r_bits_id(interconnect$_io_slaves_2_r_bits_id),
+ .io_slaves_2_r_bits_user(interconnect$_io_slaves_2_r_bits_user),
+ .io_slaves_3_aw_ready(interconnect$_io_slaves_3_aw_ready),
+ .io_slaves_3_aw_valid(interconnect$_io_slaves_3_aw_valid),
+ .io_slaves_3_aw_bits_addr(interconnect$_io_slaves_3_aw_bits_addr),
+ .io_slaves_3_aw_bits_len(interconnect$_io_slaves_3_aw_bits_len),
+ .io_slaves_3_aw_bits_size(interconnect$_io_slaves_3_aw_bits_size),
+ .io_slaves_3_aw_bits_burst(interconnect$_io_slaves_3_aw_bits_burst),
+ .io_slaves_3_aw_bits_lock(interconnect$_io_slaves_3_aw_bits_lock),
+ .io_slaves_3_aw_bits_cache(interconnect$_io_slaves_3_aw_bits_cache),
+ .io_slaves_3_aw_bits_prot(interconnect$_io_slaves_3_aw_bits_prot),
+ .io_slaves_3_aw_bits_qos(interconnect$_io_slaves_3_aw_bits_qos),
+ .io_slaves_3_aw_bits_region(interconnect$_io_slaves_3_aw_bits_region),
+ .io_slaves_3_aw_bits_id(interconnect$_io_slaves_3_aw_bits_id),
+ .io_slaves_3_aw_bits_user(interconnect$_io_slaves_3_aw_bits_user),
+ .io_slaves_3_w_ready(interconnect$_io_slaves_3_w_ready),
+ .io_slaves_3_w_valid(interconnect$_io_slaves_3_w_valid),
+ .io_slaves_3_w_bits_data(interconnect$_io_slaves_3_w_bits_data),
+ .io_slaves_3_w_bits_last(interconnect$_io_slaves_3_w_bits_last),
+ .io_slaves_3_w_bits_strb(interconnect$_io_slaves_3_w_bits_strb),
+ .io_slaves_3_w_bits_user(interconnect$_io_slaves_3_w_bits_user),
+ .io_slaves_3_b_ready(interconnect$_io_slaves_3_b_ready),
+ .io_slaves_3_b_valid(interconnect$_io_slaves_3_b_valid),
+ .io_slaves_3_b_bits_resp(interconnect$_io_slaves_3_b_bits_resp),
+ .io_slaves_3_b_bits_id(interconnect$_io_slaves_3_b_bits_id),
+ .io_slaves_3_b_bits_user(interconnect$_io_slaves_3_b_bits_user),
+ .io_slaves_3_ar_ready(interconnect$_io_slaves_3_ar_ready),
+ .io_slaves_3_ar_valid(interconnect$_io_slaves_3_ar_valid),
+ .io_slaves_3_ar_bits_addr(interconnect$_io_slaves_3_ar_bits_addr),
+ .io_slaves_3_ar_bits_len(interconnect$_io_slaves_3_ar_bits_len),
+ .io_slaves_3_ar_bits_size(interconnect$_io_slaves_3_ar_bits_size),
+ .io_slaves_3_ar_bits_burst(interconnect$_io_slaves_3_ar_bits_burst),
+ .io_slaves_3_ar_bits_lock(interconnect$_io_slaves_3_ar_bits_lock),
+ .io_slaves_3_ar_bits_cache(interconnect$_io_slaves_3_ar_bits_cache),
+ .io_slaves_3_ar_bits_prot(interconnect$_io_slaves_3_ar_bits_prot),
+ .io_slaves_3_ar_bits_qos(interconnect$_io_slaves_3_ar_bits_qos),
+ .io_slaves_3_ar_bits_region(interconnect$_io_slaves_3_ar_bits_region),
+ .io_slaves_3_ar_bits_id(interconnect$_io_slaves_3_ar_bits_id),
+ .io_slaves_3_ar_bits_user(interconnect$_io_slaves_3_ar_bits_user),
+ .io_slaves_3_r_ready(interconnect$_io_slaves_3_r_ready),
+ .io_slaves_3_r_valid(interconnect$_io_slaves_3_r_valid),
+ .io_slaves_3_r_bits_resp(interconnect$_io_slaves_3_r_bits_resp),
+ .io_slaves_3_r_bits_data(interconnect$_io_slaves_3_r_bits_data),
+ .io_slaves_3_r_bits_last(interconnect$_io_slaves_3_r_bits_last),
+ .io_slaves_3_r_bits_id(interconnect$_io_slaves_3_r_bits_id),
+ .io_slaves_3_r_bits_user(interconnect$_io_slaves_3_r_bits_user),
+ .io_slaves_4_aw_ready(interconnect$_io_slaves_4_aw_ready),
+ .io_slaves_4_aw_valid(interconnect$_io_slaves_4_aw_valid),
+ .io_slaves_4_aw_bits_addr(interconnect$_io_slaves_4_aw_bits_addr),
+ .io_slaves_4_aw_bits_len(interconnect$_io_slaves_4_aw_bits_len),
+ .io_slaves_4_aw_bits_size(interconnect$_io_slaves_4_aw_bits_size),
+ .io_slaves_4_aw_bits_burst(interconnect$_io_slaves_4_aw_bits_burst),
+ .io_slaves_4_aw_bits_lock(interconnect$_io_slaves_4_aw_bits_lock),
+ .io_slaves_4_aw_bits_cache(interconnect$_io_slaves_4_aw_bits_cache),
+ .io_slaves_4_aw_bits_prot(interconnect$_io_slaves_4_aw_bits_prot),
+ .io_slaves_4_aw_bits_qos(interconnect$_io_slaves_4_aw_bits_qos),
+ .io_slaves_4_aw_bits_region(interconnect$_io_slaves_4_aw_bits_region),
+ .io_slaves_4_aw_bits_id(interconnect$_io_slaves_4_aw_bits_id),
+ .io_slaves_4_aw_bits_user(interconnect$_io_slaves_4_aw_bits_user),
+ .io_slaves_4_w_ready(interconnect$_io_slaves_4_w_ready),
+ .io_slaves_4_w_valid(interconnect$_io_slaves_4_w_valid),
+ .io_slaves_4_w_bits_data(interconnect$_io_slaves_4_w_bits_data),
+ .io_slaves_4_w_bits_last(interconnect$_io_slaves_4_w_bits_last),
+ .io_slaves_4_w_bits_strb(interconnect$_io_slaves_4_w_bits_strb),
+ .io_slaves_4_w_bits_user(interconnect$_io_slaves_4_w_bits_user),
+ .io_slaves_4_b_ready(interconnect$_io_slaves_4_b_ready),
+ .io_slaves_4_b_valid(interconnect$_io_slaves_4_b_valid),
+ .io_slaves_4_b_bits_resp(interconnect$_io_slaves_4_b_bits_resp),
+ .io_slaves_4_b_bits_id(interconnect$_io_slaves_4_b_bits_id),
+ .io_slaves_4_b_bits_user(interconnect$_io_slaves_4_b_bits_user),
+ .io_slaves_4_ar_ready(interconnect$_io_slaves_4_ar_ready),
+ .io_slaves_4_ar_valid(interconnect$_io_slaves_4_ar_valid),
+ .io_slaves_4_ar_bits_addr(interconnect$_io_slaves_4_ar_bits_addr),
+ .io_slaves_4_ar_bits_len(interconnect$_io_slaves_4_ar_bits_len),
+ .io_slaves_4_ar_bits_size(interconnect$_io_slaves_4_ar_bits_size),
+ .io_slaves_4_ar_bits_burst(interconnect$_io_slaves_4_ar_bits_burst),
+ .io_slaves_4_ar_bits_lock(interconnect$_io_slaves_4_ar_bits_lock),
+ .io_slaves_4_ar_bits_cache(interconnect$_io_slaves_4_ar_bits_cache),
+ .io_slaves_4_ar_bits_prot(interconnect$_io_slaves_4_ar_bits_prot),
+ .io_slaves_4_ar_bits_qos(interconnect$_io_slaves_4_ar_bits_qos),
+ .io_slaves_4_ar_bits_region(interconnect$_io_slaves_4_ar_bits_region),
+ .io_slaves_4_ar_bits_id(interconnect$_io_slaves_4_ar_bits_id),
+ .io_slaves_4_ar_bits_user(interconnect$_io_slaves_4_ar_bits_user),
+ .io_slaves_4_r_ready(interconnect$_io_slaves_4_r_ready),
+ .io_slaves_4_r_valid(interconnect$_io_slaves_4_r_valid),
+ .io_slaves_4_r_bits_resp(interconnect$_io_slaves_4_r_bits_resp),
+ .io_slaves_4_r_bits_data(interconnect$_io_slaves_4_r_bits_data),
+ .io_slaves_4_r_bits_last(interconnect$_io_slaves_4_r_bits_last),
+ .io_slaves_4_r_bits_id(interconnect$_io_slaves_4_r_bits_id),
+ .io_slaves_4_r_bits_user(interconnect$_io_slaves_4_r_bits_user)
+ );
+ ClientTileLinkIOUnwrapper T_8069 (
+ .clk(T_8069_clk),
+ .reset(T_8069_reset),
+ .io_in_acquire_ready(T_8069_io_in_acquire_ready),
+ .io_in_acquire_valid(T_8069_io_in_acquire_valid),
+ .io_in_acquire_bits_addr_block(T_8069_io_in_acquire_bits_addr_block),
+ .io_in_acquire_bits_client_xact_id(T_8069_io_in_acquire_bits_client_xact_id),
+ .io_in_acquire_bits_addr_beat(T_8069_io_in_acquire_bits_addr_beat),
+ .io_in_acquire_bits_is_builtin_type(T_8069_io_in_acquire_bits_is_builtin_type),
+ .io_in_acquire_bits_a_type(T_8069_io_in_acquire_bits_a_type),
+ .io_in_acquire_bits_union(T_8069_io_in_acquire_bits_union),
+ .io_in_acquire_bits_data(T_8069_io_in_acquire_bits_data),
+ .io_in_grant_ready(T_8069_io_in_grant_ready),
+ .io_in_grant_valid(T_8069_io_in_grant_valid),
+ .io_in_grant_bits_addr_beat(T_8069_io_in_grant_bits_addr_beat),
+ .io_in_grant_bits_client_xact_id(T_8069_io_in_grant_bits_client_xact_id),
+ .io_in_grant_bits_manager_xact_id(T_8069_io_in_grant_bits_manager_xact_id),
+ .io_in_grant_bits_is_builtin_type(T_8069_io_in_grant_bits_is_builtin_type),
+ .io_in_grant_bits_g_type(T_8069_io_in_grant_bits_g_type),
+ .io_in_grant_bits_data(T_8069_io_in_grant_bits_data),
+ .io_in_probe_ready(T_8069_io_in_probe_ready),
+ .io_in_probe_valid(T_8069_io_in_probe_valid),
+ .io_in_probe_bits_addr_block(T_8069_io_in_probe_bits_addr_block),
+ .io_in_probe_bits_p_type(T_8069_io_in_probe_bits_p_type),
+ .io_in_release_ready(T_8069_io_in_release_ready),
+ .io_in_release_valid(T_8069_io_in_release_valid),
+ .io_in_release_bits_addr_beat(T_8069_io_in_release_bits_addr_beat),
+ .io_in_release_bits_addr_block(T_8069_io_in_release_bits_addr_block),
+ .io_in_release_bits_client_xact_id(T_8069_io_in_release_bits_client_xact_id),
+ .io_in_release_bits_voluntary(T_8069_io_in_release_bits_voluntary),
+ .io_in_release_bits_r_type(T_8069_io_in_release_bits_r_type),
+ .io_in_release_bits_data(T_8069_io_in_release_bits_data),
+ .io_out_acquire_ready(T_8069_io_out_acquire_ready),
+ .io_out_acquire_valid(T_8069_io_out_acquire_valid),
+ .io_out_acquire_bits_addr_block(T_8069_io_out_acquire_bits_addr_block),
+ .io_out_acquire_bits_client_xact_id(T_8069_io_out_acquire_bits_client_xact_id),
+ .io_out_acquire_bits_addr_beat(T_8069_io_out_acquire_bits_addr_beat),
+ .io_out_acquire_bits_is_builtin_type(T_8069_io_out_acquire_bits_is_builtin_type),
+ .io_out_acquire_bits_a_type(T_8069_io_out_acquire_bits_a_type),
+ .io_out_acquire_bits_union(T_8069_io_out_acquire_bits_union),
+ .io_out_acquire_bits_data(T_8069_io_out_acquire_bits_data),
+ .io_out_grant_ready(T_8069_io_out_grant_ready),
+ .io_out_grant_valid(T_8069_io_out_grant_valid),
+ .io_out_grant_bits_addr_beat(T_8069_io_out_grant_bits_addr_beat),
+ .io_out_grant_bits_client_xact_id(T_8069_io_out_grant_bits_client_xact_id),
+ .io_out_grant_bits_manager_xact_id(T_8069_io_out_grant_bits_manager_xact_id),
+ .io_out_grant_bits_is_builtin_type(T_8069_io_out_grant_bits_is_builtin_type),
+ .io_out_grant_bits_g_type(T_8069_io_out_grant_bits_g_type),
+ .io_out_grant_bits_data(T_8069_io_out_grant_bits_data)
+ );
+ TileLinkIONarrower T_8070 (
+ .clk(T_8070_clk),
+ .reset(T_8070_reset),
+ .io_in_acquire_ready(T_8070_io_in_acquire_ready),
+ .io_in_acquire_valid(T_8070_io_in_acquire_valid),
+ .io_in_acquire_bits_addr_block(T_8070_io_in_acquire_bits_addr_block),
+ .io_in_acquire_bits_client_xact_id(T_8070_io_in_acquire_bits_client_xact_id),
+ .io_in_acquire_bits_addr_beat(T_8070_io_in_acquire_bits_addr_beat),
+ .io_in_acquire_bits_is_builtin_type(T_8070_io_in_acquire_bits_is_builtin_type),
+ .io_in_acquire_bits_a_type(T_8070_io_in_acquire_bits_a_type),
+ .io_in_acquire_bits_union(T_8070_io_in_acquire_bits_union),
+ .io_in_acquire_bits_data(T_8070_io_in_acquire_bits_data),
+ .io_in_grant_ready(T_8070_io_in_grant_ready),
+ .io_in_grant_valid(T_8070_io_in_grant_valid),
+ .io_in_grant_bits_addr_beat(T_8070_io_in_grant_bits_addr_beat),
+ .io_in_grant_bits_client_xact_id(T_8070_io_in_grant_bits_client_xact_id),
+ .io_in_grant_bits_manager_xact_id(T_8070_io_in_grant_bits_manager_xact_id),
+ .io_in_grant_bits_is_builtin_type(T_8070_io_in_grant_bits_is_builtin_type),
+ .io_in_grant_bits_g_type(T_8070_io_in_grant_bits_g_type),
+ .io_in_grant_bits_data(T_8070_io_in_grant_bits_data),
+ .io_out_acquire_ready(T_8070_io_out_acquire_ready),
+ .io_out_acquire_valid(T_8070_io_out_acquire_valid),
+ .io_out_acquire_bits_addr_block(T_8070_io_out_acquire_bits_addr_block),
+ .io_out_acquire_bits_client_xact_id(T_8070_io_out_acquire_bits_client_xact_id),
+ .io_out_acquire_bits_addr_beat(T_8070_io_out_acquire_bits_addr_beat),
+ .io_out_acquire_bits_is_builtin_type(T_8070_io_out_acquire_bits_is_builtin_type),
+ .io_out_acquire_bits_a_type(T_8070_io_out_acquire_bits_a_type),
+ .io_out_acquire_bits_union(T_8070_io_out_acquire_bits_union),
+ .io_out_acquire_bits_data(T_8070_io_out_acquire_bits_data),
+ .io_out_grant_ready(T_8070_io_out_grant_ready),
+ .io_out_grant_valid(T_8070_io_out_grant_valid),
+ .io_out_grant_bits_addr_beat(T_8070_io_out_grant_bits_addr_beat),
+ .io_out_grant_bits_client_xact_id(T_8070_io_out_grant_bits_client_xact_id),
+ .io_out_grant_bits_manager_xact_id(T_8070_io_out_grant_bits_manager_xact_id),
+ .io_out_grant_bits_is_builtin_type(T_8070_io_out_grant_bits_is_builtin_type),
+ .io_out_grant_bits_g_type(T_8070_io_out_grant_bits_g_type),
+ .io_out_grant_bits_data(T_8070_io_out_grant_bits_data)
+ );
+ NastiIOTileLinkIOConverter T_8071 (
+ .clk(T_8071_clk),
+ .reset(T_8071_reset),
+ .io_tl_acquire_ready(T_8071_io_tl_acquire_ready),
+ .io_tl_acquire_valid(T_8071_io_tl_acquire_valid),
+ .io_tl_acquire_bits_addr_block(T_8071_io_tl_acquire_bits_addr_block),
+ .io_tl_acquire_bits_client_xact_id(T_8071_io_tl_acquire_bits_client_xact_id),
+ .io_tl_acquire_bits_addr_beat(T_8071_io_tl_acquire_bits_addr_beat),
+ .io_tl_acquire_bits_is_builtin_type(T_8071_io_tl_acquire_bits_is_builtin_type),
+ .io_tl_acquire_bits_a_type(T_8071_io_tl_acquire_bits_a_type),
+ .io_tl_acquire_bits_union(T_8071_io_tl_acquire_bits_union),
+ .io_tl_acquire_bits_data(T_8071_io_tl_acquire_bits_data),
+ .io_tl_grant_ready(T_8071_io_tl_grant_ready),
+ .io_tl_grant_valid(T_8071_io_tl_grant_valid),
+ .io_tl_grant_bits_addr_beat(T_8071_io_tl_grant_bits_addr_beat),
+ .io_tl_grant_bits_client_xact_id(T_8071_io_tl_grant_bits_client_xact_id),
+ .io_tl_grant_bits_manager_xact_id(T_8071_io_tl_grant_bits_manager_xact_id),
+ .io_tl_grant_bits_is_builtin_type(T_8071_io_tl_grant_bits_is_builtin_type),
+ .io_tl_grant_bits_g_type(T_8071_io_tl_grant_bits_g_type),
+ .io_tl_grant_bits_data(T_8071_io_tl_grant_bits_data),
+ .io_nasti_aw_ready(T_8071_io_nasti_aw_ready),
+ .io_nasti_aw_valid(T_8071_io_nasti_aw_valid),
+ .io_nasti_aw_bits_addr(T_8071_io_nasti_aw_bits_addr),
+ .io_nasti_aw_bits_len(T_8071_io_nasti_aw_bits_len),
+ .io_nasti_aw_bits_size(T_8071_io_nasti_aw_bits_size),
+ .io_nasti_aw_bits_burst(T_8071_io_nasti_aw_bits_burst),
+ .io_nasti_aw_bits_lock(T_8071_io_nasti_aw_bits_lock),
+ .io_nasti_aw_bits_cache(T_8071_io_nasti_aw_bits_cache),
+ .io_nasti_aw_bits_prot(T_8071_io_nasti_aw_bits_prot),
+ .io_nasti_aw_bits_qos(T_8071_io_nasti_aw_bits_qos),
+ .io_nasti_aw_bits_region(T_8071_io_nasti_aw_bits_region),
+ .io_nasti_aw_bits_id(T_8071_io_nasti_aw_bits_id),
+ .io_nasti_aw_bits_user(T_8071_io_nasti_aw_bits_user),
+ .io_nasti_w_ready(T_8071_io_nasti_w_ready),
+ .io_nasti_w_valid(T_8071_io_nasti_w_valid),
+ .io_nasti_w_bits_data(T_8071_io_nasti_w_bits_data),
+ .io_nasti_w_bits_last(T_8071_io_nasti_w_bits_last),
+ .io_nasti_w_bits_strb(T_8071_io_nasti_w_bits_strb),
+ .io_nasti_w_bits_user(T_8071_io_nasti_w_bits_user),
+ .io_nasti_b_ready(T_8071_io_nasti_b_ready),
+ .io_nasti_b_valid(T_8071_io_nasti_b_valid),
+ .io_nasti_b_bits_resp(T_8071_io_nasti_b_bits_resp),
+ .io_nasti_b_bits_id(T_8071_io_nasti_b_bits_id),
+ .io_nasti_b_bits_user(T_8071_io_nasti_b_bits_user),
+ .io_nasti_ar_ready(T_8071_io_nasti_ar_ready),
+ .io_nasti_ar_valid(T_8071_io_nasti_ar_valid),
+ .io_nasti_ar_bits_addr(T_8071_io_nasti_ar_bits_addr),
+ .io_nasti_ar_bits_len(T_8071_io_nasti_ar_bits_len),
+ .io_nasti_ar_bits_size(T_8071_io_nasti_ar_bits_size),
+ .io_nasti_ar_bits_burst(T_8071_io_nasti_ar_bits_burst),
+ .io_nasti_ar_bits_lock(T_8071_io_nasti_ar_bits_lock),
+ .io_nasti_ar_bits_cache(T_8071_io_nasti_ar_bits_cache),
+ .io_nasti_ar_bits_prot(T_8071_io_nasti_ar_bits_prot),
+ .io_nasti_ar_bits_qos(T_8071_io_nasti_ar_bits_qos),
+ .io_nasti_ar_bits_region(T_8071_io_nasti_ar_bits_region),
+ .io_nasti_ar_bits_id(T_8071_io_nasti_ar_bits_id),
+ .io_nasti_ar_bits_user(T_8071_io_nasti_ar_bits_user),
+ .io_nasti_r_ready(T_8071_io_nasti_r_ready),
+ .io_nasti_r_valid(T_8071_io_nasti_r_valid),
+ .io_nasti_r_bits_resp(T_8071_io_nasti_r_bits_resp),
+ .io_nasti_r_bits_data(T_8071_io_nasti_r_bits_data),
+ .io_nasti_r_bits_last(T_8071_io_nasti_r_bits_last),
+ .io_nasti_r_bits_id(T_8071_io_nasti_r_bits_id),
+ .io_nasti_r_bits_user(T_8071_io_nasti_r_bits_user)
+ );
+ ClientTileLinkIOWrapper_71 T_8072 (
+ .clk(T_8072_clk),
+ .reset(T_8072_reset),
+ .io_in_acquire_ready(T_8072_io_in_acquire_ready),
+ .io_in_acquire_valid(T_8072_io_in_acquire_valid),
+ .io_in_acquire_bits_addr_block(T_8072_io_in_acquire_bits_addr_block),
+ .io_in_acquire_bits_client_xact_id(T_8072_io_in_acquire_bits_client_xact_id),
+ .io_in_acquire_bits_addr_beat(T_8072_io_in_acquire_bits_addr_beat),
+ .io_in_acquire_bits_is_builtin_type(T_8072_io_in_acquire_bits_is_builtin_type),
+ .io_in_acquire_bits_a_type(T_8072_io_in_acquire_bits_a_type),
+ .io_in_acquire_bits_union(T_8072_io_in_acquire_bits_union),
+ .io_in_acquire_bits_data(T_8072_io_in_acquire_bits_data),
+ .io_in_grant_ready(T_8072_io_in_grant_ready),
+ .io_in_grant_valid(T_8072_io_in_grant_valid),
+ .io_in_grant_bits_addr_beat(T_8072_io_in_grant_bits_addr_beat),
+ .io_in_grant_bits_client_xact_id(T_8072_io_in_grant_bits_client_xact_id),
+ .io_in_grant_bits_manager_xact_id(T_8072_io_in_grant_bits_manager_xact_id),
+ .io_in_grant_bits_is_builtin_type(T_8072_io_in_grant_bits_is_builtin_type),
+ .io_in_grant_bits_g_type(T_8072_io_in_grant_bits_g_type),
+ .io_in_grant_bits_data(T_8072_io_in_grant_bits_data),
+ .io_out_acquire_ready(T_8072_io_out_acquire_ready),
+ .io_out_acquire_valid(T_8072_io_out_acquire_valid),
+ .io_out_acquire_bits_addr_block(T_8072_io_out_acquire_bits_addr_block),
+ .io_out_acquire_bits_client_xact_id(T_8072_io_out_acquire_bits_client_xact_id),
+ .io_out_acquire_bits_addr_beat(T_8072_io_out_acquire_bits_addr_beat),
+ .io_out_acquire_bits_is_builtin_type(T_8072_io_out_acquire_bits_is_builtin_type),
+ .io_out_acquire_bits_a_type(T_8072_io_out_acquire_bits_a_type),
+ .io_out_acquire_bits_union(T_8072_io_out_acquire_bits_union),
+ .io_out_acquire_bits_data(T_8072_io_out_acquire_bits_data),
+ .io_out_grant_ready(T_8072_io_out_grant_ready),
+ .io_out_grant_valid(T_8072_io_out_grant_valid),
+ .io_out_grant_bits_addr_beat(T_8072_io_out_grant_bits_addr_beat),
+ .io_out_grant_bits_client_xact_id(T_8072_io_out_grant_bits_client_xact_id),
+ .io_out_grant_bits_manager_xact_id(T_8072_io_out_grant_bits_manager_xact_id),
+ .io_out_grant_bits_is_builtin_type(T_8072_io_out_grant_bits_is_builtin_type),
+ .io_out_grant_bits_g_type(T_8072_io_out_grant_bits_g_type),
+ .io_out_grant_bits_data(T_8072_io_out_grant_bits_data),
+ .io_out_probe_ready(T_8072_io_out_probe_ready),
+ .io_out_probe_valid(T_8072_io_out_probe_valid),
+ .io_out_probe_bits_addr_block(T_8072_io_out_probe_bits_addr_block),
+ .io_out_probe_bits_p_type(T_8072_io_out_probe_bits_p_type),
+ .io_out_release_ready(T_8072_io_out_release_ready),
+ .io_out_release_valid(T_8072_io_out_release_valid),
+ .io_out_release_bits_addr_beat(T_8072_io_out_release_bits_addr_beat),
+ .io_out_release_bits_addr_block(T_8072_io_out_release_bits_addr_block),
+ .io_out_release_bits_client_xact_id(T_8072_io_out_release_bits_client_xact_id),
+ .io_out_release_bits_voluntary(T_8072_io_out_release_bits_voluntary),
+ .io_out_release_bits_r_type(T_8072_io_out_release_bits_r_type),
+ .io_out_release_bits_data(T_8072_io_out_release_bits_data)
+ );
+ ClientTileLinkEnqueuer T_8073 (
+ .clk(T_8073_clk),
+ .reset(T_8073_reset),
+ .io_inner_acquire_ready(T_8073_io_inner_acquire_ready),
+ .io_inner_acquire_valid(T_8073_io_inner_acquire_valid),
+ .io_inner_acquire_bits_addr_block(T_8073_io_inner_acquire_bits_addr_block),
+ .io_inner_acquire_bits_client_xact_id(T_8073_io_inner_acquire_bits_client_xact_id),
+ .io_inner_acquire_bits_addr_beat(T_8073_io_inner_acquire_bits_addr_beat),
+ .io_inner_acquire_bits_is_builtin_type(T_8073_io_inner_acquire_bits_is_builtin_type),
+ .io_inner_acquire_bits_a_type(T_8073_io_inner_acquire_bits_a_type),
+ .io_inner_acquire_bits_union(T_8073_io_inner_acquire_bits_union),
+ .io_inner_acquire_bits_data(T_8073_io_inner_acquire_bits_data),
+ .io_inner_grant_ready(T_8073_io_inner_grant_ready),
+ .io_inner_grant_valid(T_8073_io_inner_grant_valid),
+ .io_inner_grant_bits_addr_beat(T_8073_io_inner_grant_bits_addr_beat),
+ .io_inner_grant_bits_client_xact_id(T_8073_io_inner_grant_bits_client_xact_id),
+ .io_inner_grant_bits_manager_xact_id(T_8073_io_inner_grant_bits_manager_xact_id),
+ .io_inner_grant_bits_is_builtin_type(T_8073_io_inner_grant_bits_is_builtin_type),
+ .io_inner_grant_bits_g_type(T_8073_io_inner_grant_bits_g_type),
+ .io_inner_grant_bits_data(T_8073_io_inner_grant_bits_data),
+ .io_inner_probe_ready(T_8073_io_inner_probe_ready),
+ .io_inner_probe_valid(T_8073_io_inner_probe_valid),
+ .io_inner_probe_bits_addr_block(T_8073_io_inner_probe_bits_addr_block),
+ .io_inner_probe_bits_p_type(T_8073_io_inner_probe_bits_p_type),
+ .io_inner_release_ready(T_8073_io_inner_release_ready),
+ .io_inner_release_valid(T_8073_io_inner_release_valid),
+ .io_inner_release_bits_addr_beat(T_8073_io_inner_release_bits_addr_beat),
+ .io_inner_release_bits_addr_block(T_8073_io_inner_release_bits_addr_block),
+ .io_inner_release_bits_client_xact_id(T_8073_io_inner_release_bits_client_xact_id),
+ .io_inner_release_bits_voluntary(T_8073_io_inner_release_bits_voluntary),
+ .io_inner_release_bits_r_type(T_8073_io_inner_release_bits_r_type),
+ .io_inner_release_bits_data(T_8073_io_inner_release_bits_data),
+ .io_outer_acquire_ready(T_8073_io_outer_acquire_ready),
+ .io_outer_acquire_valid(T_8073_io_outer_acquire_valid),
+ .io_outer_acquire_bits_addr_block(T_8073_io_outer_acquire_bits_addr_block),
+ .io_outer_acquire_bits_client_xact_id(T_8073_io_outer_acquire_bits_client_xact_id),
+ .io_outer_acquire_bits_addr_beat(T_8073_io_outer_acquire_bits_addr_beat),
+ .io_outer_acquire_bits_is_builtin_type(T_8073_io_outer_acquire_bits_is_builtin_type),
+ .io_outer_acquire_bits_a_type(T_8073_io_outer_acquire_bits_a_type),
+ .io_outer_acquire_bits_union(T_8073_io_outer_acquire_bits_union),
+ .io_outer_acquire_bits_data(T_8073_io_outer_acquire_bits_data),
+ .io_outer_grant_ready(T_8073_io_outer_grant_ready),
+ .io_outer_grant_valid(T_8073_io_outer_grant_valid),
+ .io_outer_grant_bits_addr_beat(T_8073_io_outer_grant_bits_addr_beat),
+ .io_outer_grant_bits_client_xact_id(T_8073_io_outer_grant_bits_client_xact_id),
+ .io_outer_grant_bits_manager_xact_id(T_8073_io_outer_grant_bits_manager_xact_id),
+ .io_outer_grant_bits_is_builtin_type(T_8073_io_outer_grant_bits_is_builtin_type),
+ .io_outer_grant_bits_g_type(T_8073_io_outer_grant_bits_g_type),
+ .io_outer_grant_bits_data(T_8073_io_outer_grant_bits_data),
+ .io_outer_probe_ready(T_8073_io_outer_probe_ready),
+ .io_outer_probe_valid(T_8073_io_outer_probe_valid),
+ .io_outer_probe_bits_addr_block(T_8073_io_outer_probe_bits_addr_block),
+ .io_outer_probe_bits_p_type(T_8073_io_outer_probe_bits_p_type),
+ .io_outer_release_ready(T_8073_io_outer_release_ready),
+ .io_outer_release_valid(T_8073_io_outer_release_valid),
+ .io_outer_release_bits_addr_beat(T_8073_io_outer_release_bits_addr_beat),
+ .io_outer_release_bits_addr_block(T_8073_io_outer_release_bits_addr_block),
+ .io_outer_release_bits_client_xact_id(T_8073_io_outer_release_bits_client_xact_id),
+ .io_outer_release_bits_voluntary(T_8073_io_outer_release_bits_voluntary),
+ .io_outer_release_bits_r_type(T_8073_io_outer_release_bits_r_type),
+ .io_outer_release_bits_data(T_8073_io_outer_release_bits_data)
+ );
+ Queue_36 T_8086 (
+ .clk(T_8086_clk),
+ .reset(T_8086_reset),
+ .io_enq_ready(T_8086_io_enq_ready),
+ .io_enq_valid(T_8086_io_enq_valid),
+ .io_enq_bits_addr(T_8086_io_enq_bits_addr),
+ .io_enq_bits_len(T_8086_io_enq_bits_len),
+ .io_enq_bits_size(T_8086_io_enq_bits_size),
+ .io_enq_bits_burst(T_8086_io_enq_bits_burst),
+ .io_enq_bits_lock(T_8086_io_enq_bits_lock),
+ .io_enq_bits_cache(T_8086_io_enq_bits_cache),
+ .io_enq_bits_prot(T_8086_io_enq_bits_prot),
+ .io_enq_bits_qos(T_8086_io_enq_bits_qos),
+ .io_enq_bits_region(T_8086_io_enq_bits_region),
+ .io_enq_bits_id(T_8086_io_enq_bits_id),
+ .io_enq_bits_user(T_8086_io_enq_bits_user),
+ .io_deq_ready(T_8086_io_deq_ready),
+ .io_deq_valid(T_8086_io_deq_valid),
+ .io_deq_bits_addr(T_8086_io_deq_bits_addr),
+ .io_deq_bits_len(T_8086_io_deq_bits_len),
+ .io_deq_bits_size(T_8086_io_deq_bits_size),
+ .io_deq_bits_burst(T_8086_io_deq_bits_burst),
+ .io_deq_bits_lock(T_8086_io_deq_bits_lock),
+ .io_deq_bits_cache(T_8086_io_deq_bits_cache),
+ .io_deq_bits_prot(T_8086_io_deq_bits_prot),
+ .io_deq_bits_qos(T_8086_io_deq_bits_qos),
+ .io_deq_bits_region(T_8086_io_deq_bits_region),
+ .io_deq_bits_id(T_8086_io_deq_bits_id),
+ .io_deq_bits_user(T_8086_io_deq_bits_user),
+ .io_count(T_8086_io_count)
+ );
+ Queue_36 T_8099 (
+ .clk(T_8099_clk),
+ .reset(T_8099_reset),
+ .io_enq_ready(T_8099_io_enq_ready),
+ .io_enq_valid(T_8099_io_enq_valid),
+ .io_enq_bits_addr(T_8099_io_enq_bits_addr),
+ .io_enq_bits_len(T_8099_io_enq_bits_len),
+ .io_enq_bits_size(T_8099_io_enq_bits_size),
+ .io_enq_bits_burst(T_8099_io_enq_bits_burst),
+ .io_enq_bits_lock(T_8099_io_enq_bits_lock),
+ .io_enq_bits_cache(T_8099_io_enq_bits_cache),
+ .io_enq_bits_prot(T_8099_io_enq_bits_prot),
+ .io_enq_bits_qos(T_8099_io_enq_bits_qos),
+ .io_enq_bits_region(T_8099_io_enq_bits_region),
+ .io_enq_bits_id(T_8099_io_enq_bits_id),
+ .io_enq_bits_user(T_8099_io_enq_bits_user),
+ .io_deq_ready(T_8099_io_deq_ready),
+ .io_deq_valid(T_8099_io_deq_valid),
+ .io_deq_bits_addr(T_8099_io_deq_bits_addr),
+ .io_deq_bits_len(T_8099_io_deq_bits_len),
+ .io_deq_bits_size(T_8099_io_deq_bits_size),
+ .io_deq_bits_burst(T_8099_io_deq_bits_burst),
+ .io_deq_bits_lock(T_8099_io_deq_bits_lock),
+ .io_deq_bits_cache(T_8099_io_deq_bits_cache),
+ .io_deq_bits_prot(T_8099_io_deq_bits_prot),
+ .io_deq_bits_qos(T_8099_io_deq_bits_qos),
+ .io_deq_bits_region(T_8099_io_deq_bits_region),
+ .io_deq_bits_id(T_8099_io_deq_bits_id),
+ .io_deq_bits_user(T_8099_io_deq_bits_user),
+ .io_count(T_8099_io_count)
+ );
+ Queue_74 T_8105 (
+ .clk(T_8105_clk),
+ .reset(T_8105_reset),
+ .io_enq_ready(T_8105_io_enq_ready),
+ .io_enq_valid(T_8105_io_enq_valid),
+ .io_enq_bits_data(T_8105_io_enq_bits_data),
+ .io_enq_bits_last(T_8105_io_enq_bits_last),
+ .io_enq_bits_strb(T_8105_io_enq_bits_strb),
+ .io_enq_bits_user(T_8105_io_enq_bits_user),
+ .io_deq_ready(T_8105_io_deq_ready),
+ .io_deq_valid(T_8105_io_deq_valid),
+ .io_deq_bits_data(T_8105_io_deq_bits_data),
+ .io_deq_bits_last(T_8105_io_deq_bits_last),
+ .io_deq_bits_strb(T_8105_io_deq_bits_strb),
+ .io_deq_bits_user(T_8105_io_deq_bits_user),
+ .io_count(T_8105_io_count)
+ );
+ Queue_75 T_8112 (
+ .clk(T_8112_clk),
+ .reset(T_8112_reset),
+ .io_enq_ready(T_8112_io_enq_ready),
+ .io_enq_valid(T_8112_io_enq_valid),
+ .io_enq_bits_resp(T_8112_io_enq_bits_resp),
+ .io_enq_bits_data(T_8112_io_enq_bits_data),
+ .io_enq_bits_last(T_8112_io_enq_bits_last),
+ .io_enq_bits_id(T_8112_io_enq_bits_id),
+ .io_enq_bits_user(T_8112_io_enq_bits_user),
+ .io_deq_ready(T_8112_io_deq_ready),
+ .io_deq_valid(T_8112_io_deq_valid),
+ .io_deq_bits_resp(T_8112_io_deq_bits_resp),
+ .io_deq_bits_data(T_8112_io_deq_bits_data),
+ .io_deq_bits_last(T_8112_io_deq_bits_last),
+ .io_deq_bits_id(T_8112_io_deq_bits_id),
+ .io_deq_bits_user(T_8112_io_deq_bits_user),
+ .io_count(T_8112_io_count)
+ );
+ Queue_76 T_8117 (
+ .clk(T_8117_clk),
+ .reset(T_8117_reset),
+ .io_enq_ready(T_8117_io_enq_ready),
+ .io_enq_valid(T_8117_io_enq_valid),
+ .io_enq_bits_resp(T_8117_io_enq_bits_resp),
+ .io_enq_bits_id(T_8117_io_enq_bits_id),
+ .io_enq_bits_user(T_8117_io_enq_bits_user),
+ .io_deq_ready(T_8117_io_deq_ready),
+ .io_deq_valid(T_8117_io_deq_valid),
+ .io_deq_bits_resp(T_8117_io_deq_bits_resp),
+ .io_deq_bits_id(T_8117_io_deq_bits_id),
+ .io_deq_bits_user(T_8117_io_deq_bits_user),
+ .io_count(T_8117_io_count)
+ );
+ RTC rtc (
+ .clk(rtc_clk),
+ .reset(rtc_reset),
+ .io_aw_ready(rtc_io_aw_ready),
+ .io_aw_valid(rtc_io_aw_valid),
+ .io_aw_bits_addr(rtc_io_aw_bits_addr),
+ .io_aw_bits_len(rtc_io_aw_bits_len),
+ .io_aw_bits_size(rtc_io_aw_bits_size),
+ .io_aw_bits_burst(rtc_io_aw_bits_burst),
+ .io_aw_bits_lock(rtc_io_aw_bits_lock),
+ .io_aw_bits_cache(rtc_io_aw_bits_cache),
+ .io_aw_bits_prot(rtc_io_aw_bits_prot),
+ .io_aw_bits_qos(rtc_io_aw_bits_qos),
+ .io_aw_bits_region(rtc_io_aw_bits_region),
+ .io_aw_bits_id(rtc_io_aw_bits_id),
+ .io_aw_bits_user(rtc_io_aw_bits_user),
+ .io_w_ready(rtc_io_w_ready),
+ .io_w_valid(rtc_io_w_valid),
+ .io_w_bits_data(rtc_io_w_bits_data),
+ .io_w_bits_last(rtc_io_w_bits_last),
+ .io_w_bits_strb(rtc_io_w_bits_strb),
+ .io_w_bits_user(rtc_io_w_bits_user),
+ .io_b_ready(rtc_io_b_ready),
+ .io_b_valid(rtc_io_b_valid),
+ .io_b_bits_resp(rtc_io_b_bits_resp),
+ .io_b_bits_id(rtc_io_b_bits_id),
+ .io_b_bits_user(rtc_io_b_bits_user),
+ .io_ar_ready(rtc_io_ar_ready),
+ .io_ar_valid(rtc_io_ar_valid),
+ .io_ar_bits_addr(rtc_io_ar_bits_addr),
+ .io_ar_bits_len(rtc_io_ar_bits_len),
+ .io_ar_bits_size(rtc_io_ar_bits_size),
+ .io_ar_bits_burst(rtc_io_ar_bits_burst),
+ .io_ar_bits_lock(rtc_io_ar_bits_lock),
+ .io_ar_bits_cache(rtc_io_ar_bits_cache),
+ .io_ar_bits_prot(rtc_io_ar_bits_prot),
+ .io_ar_bits_qos(rtc_io_ar_bits_qos),
+ .io_ar_bits_region(rtc_io_ar_bits_region),
+ .io_ar_bits_id(rtc_io_ar_bits_id),
+ .io_ar_bits_user(rtc_io_ar_bits_user),
+ .io_r_ready(rtc_io_r_ready),
+ .io_r_valid(rtc_io_r_valid),
+ .io_r_bits_resp(rtc_io_r_bits_resp),
+ .io_r_bits_data(rtc_io_r_bits_data),
+ .io_r_bits_last(rtc_io_r_bits_last),
+ .io_r_bits_id(rtc_io_r_bits_id),
+ .io_r_bits_user(rtc_io_r_bits_user)
+ );
+ SmiIONastiIOConverter T_8119 (
+ .clk(T_8119_clk),
+ .reset(T_8119_reset),
+ .io_nasti_aw_ready(T_8119_io_nasti_aw_ready),
+ .io_nasti_aw_valid(T_8119_io_nasti_aw_valid),
+ .io_nasti_aw_bits_addr(T_8119_io_nasti_aw_bits_addr),
+ .io_nasti_aw_bits_len(T_8119_io_nasti_aw_bits_len),
+ .io_nasti_aw_bits_size(T_8119_io_nasti_aw_bits_size),
+ .io_nasti_aw_bits_burst(T_8119_io_nasti_aw_bits_burst),
+ .io_nasti_aw_bits_lock(T_8119_io_nasti_aw_bits_lock),
+ .io_nasti_aw_bits_cache(T_8119_io_nasti_aw_bits_cache),
+ .io_nasti_aw_bits_prot(T_8119_io_nasti_aw_bits_prot),
+ .io_nasti_aw_bits_qos(T_8119_io_nasti_aw_bits_qos),
+ .io_nasti_aw_bits_region(T_8119_io_nasti_aw_bits_region),
+ .io_nasti_aw_bits_id(T_8119_io_nasti_aw_bits_id),
+ .io_nasti_aw_bits_user(T_8119_io_nasti_aw_bits_user),
+ .io_nasti_w_ready(T_8119_io_nasti_w_ready),
+ .io_nasti_w_valid(T_8119_io_nasti_w_valid),
+ .io_nasti_w_bits_data(T_8119_io_nasti_w_bits_data),
+ .io_nasti_w_bits_last(T_8119_io_nasti_w_bits_last),
+ .io_nasti_w_bits_strb(T_8119_io_nasti_w_bits_strb),
+ .io_nasti_w_bits_user(T_8119_io_nasti_w_bits_user),
+ .io_nasti_b_ready(T_8119_io_nasti_b_ready),
+ .io_nasti_b_valid(T_8119_io_nasti_b_valid),
+ .io_nasti_b_bits_resp(T_8119_io_nasti_b_bits_resp),
+ .io_nasti_b_bits_id(T_8119_io_nasti_b_bits_id),
+ .io_nasti_b_bits_user(T_8119_io_nasti_b_bits_user),
+ .io_nasti_ar_ready(T_8119_io_nasti_ar_ready),
+ .io_nasti_ar_valid(T_8119_io_nasti_ar_valid),
+ .io_nasti_ar_bits_addr(T_8119_io_nasti_ar_bits_addr),
+ .io_nasti_ar_bits_len(T_8119_io_nasti_ar_bits_len),
+ .io_nasti_ar_bits_size(T_8119_io_nasti_ar_bits_size),
+ .io_nasti_ar_bits_burst(T_8119_io_nasti_ar_bits_burst),
+ .io_nasti_ar_bits_lock(T_8119_io_nasti_ar_bits_lock),
+ .io_nasti_ar_bits_cache(T_8119_io_nasti_ar_bits_cache),
+ .io_nasti_ar_bits_prot(T_8119_io_nasti_ar_bits_prot),
+ .io_nasti_ar_bits_qos(T_8119_io_nasti_ar_bits_qos),
+ .io_nasti_ar_bits_region(T_8119_io_nasti_ar_bits_region),
+ .io_nasti_ar_bits_id(T_8119_io_nasti_ar_bits_id),
+ .io_nasti_ar_bits_user(T_8119_io_nasti_ar_bits_user),
+ .io_nasti_r_ready(T_8119_io_nasti_r_ready),
+ .io_nasti_r_valid(T_8119_io_nasti_r_valid),
+ .io_nasti_r_bits_resp(T_8119_io_nasti_r_bits_resp),
+ .io_nasti_r_bits_data(T_8119_io_nasti_r_bits_data),
+ .io_nasti_r_bits_last(T_8119_io_nasti_r_bits_last),
+ .io_nasti_r_bits_id(T_8119_io_nasti_r_bits_id),
+ .io_nasti_r_bits_user(T_8119_io_nasti_r_bits_user),
+ .io_smi_req_ready(T_8119_io_smi_req_ready),
+ .io_smi_req_valid(T_8119_io_smi_req_valid),
+ .io_smi_req_bits_rw(T_8119_io_smi_req_bits_rw),
+ .io_smi_req_bits_addr(T_8119_io_smi_req_bits_addr),
+ .io_smi_req_bits_data(T_8119_io_smi_req_bits_data),
+ .io_smi_resp_ready(T_8119_io_smi_resp_ready),
+ .io_smi_resp_valid(T_8119_io_smi_resp_valid),
+ .io_smi_resp_bits(T_8119_io_smi_resp_bits)
+ );
+ SmiIONastiIOConverter_78 src_conv (
+ .clk(src_conv_clk),
+ .reset(src_conv_reset),
+ .io_nasti_aw_ready(src_conv_io_nasti_aw_ready),
+ .io_nasti_aw_valid(src_conv_io_nasti_aw_valid),
+ .io_nasti_aw_bits_addr(src_conv_io_nasti_aw_bits_addr),
+ .io_nasti_aw_bits_len(src_conv_io_nasti_aw_bits_len),
+ .io_nasti_aw_bits_size(src_conv_io_nasti_aw_bits_size),
+ .io_nasti_aw_bits_burst(src_conv_io_nasti_aw_bits_burst),
+ .io_nasti_aw_bits_lock(src_conv_io_nasti_aw_bits_lock),
+ .io_nasti_aw_bits_cache(src_conv_io_nasti_aw_bits_cache),
+ .io_nasti_aw_bits_prot(src_conv_io_nasti_aw_bits_prot),
+ .io_nasti_aw_bits_qos(src_conv_io_nasti_aw_bits_qos),
+ .io_nasti_aw_bits_region(src_conv_io_nasti_aw_bits_region),
+ .io_nasti_aw_bits_id(src_conv_io_nasti_aw_bits_id),
+ .io_nasti_aw_bits_user(src_conv_io_nasti_aw_bits_user),
+ .io_nasti_w_ready(src_conv_io_nasti_w_ready),
+ .io_nasti_w_valid(src_conv_io_nasti_w_valid),
+ .io_nasti_w_bits_data(src_conv_io_nasti_w_bits_data),
+ .io_nasti_w_bits_last(src_conv_io_nasti_w_bits_last),
+ .io_nasti_w_bits_strb(src_conv_io_nasti_w_bits_strb),
+ .io_nasti_w_bits_user(src_conv_io_nasti_w_bits_user),
+ .io_nasti_b_ready(src_conv_io_nasti_b_ready),
+ .io_nasti_b_valid(src_conv_io_nasti_b_valid),
+ .io_nasti_b_bits_resp(src_conv_io_nasti_b_bits_resp),
+ .io_nasti_b_bits_id(src_conv_io_nasti_b_bits_id),
+ .io_nasti_b_bits_user(src_conv_io_nasti_b_bits_user),
+ .io_nasti_ar_ready(src_conv_io_nasti_ar_ready),
+ .io_nasti_ar_valid(src_conv_io_nasti_ar_valid),
+ .io_nasti_ar_bits_addr(src_conv_io_nasti_ar_bits_addr),
+ .io_nasti_ar_bits_len(src_conv_io_nasti_ar_bits_len),
+ .io_nasti_ar_bits_size(src_conv_io_nasti_ar_bits_size),
+ .io_nasti_ar_bits_burst(src_conv_io_nasti_ar_bits_burst),
+ .io_nasti_ar_bits_lock(src_conv_io_nasti_ar_bits_lock),
+ .io_nasti_ar_bits_cache(src_conv_io_nasti_ar_bits_cache),
+ .io_nasti_ar_bits_prot(src_conv_io_nasti_ar_bits_prot),
+ .io_nasti_ar_bits_qos(src_conv_io_nasti_ar_bits_qos),
+ .io_nasti_ar_bits_region(src_conv_io_nasti_ar_bits_region),
+ .io_nasti_ar_bits_id(src_conv_io_nasti_ar_bits_id),
+ .io_nasti_ar_bits_user(src_conv_io_nasti_ar_bits_user),
+ .io_nasti_r_ready(src_conv_io_nasti_r_ready),
+ .io_nasti_r_valid(src_conv_io_nasti_r_valid),
+ .io_nasti_r_bits_resp(src_conv_io_nasti_r_bits_resp),
+ .io_nasti_r_bits_data(src_conv_io_nasti_r_bits_data),
+ .io_nasti_r_bits_last(src_conv_io_nasti_r_bits_last),
+ .io_nasti_r_bits_id(src_conv_io_nasti_r_bits_id),
+ .io_nasti_r_bits_user(src_conv_io_nasti_r_bits_user),
+ .io_smi_req_ready(src_conv_io_smi_req_ready),
+ .io_smi_req_valid(src_conv_io_smi_req_valid),
+ .io_smi_req_bits_rw(src_conv_io_smi_req_bits_rw),
+ .io_smi_req_bits_addr(src_conv_io_smi_req_bits_addr),
+ .io_smi_req_bits_data(src_conv_io_smi_req_bits_data),
+ .io_smi_resp_ready(src_conv_io_smi_resp_ready),
+ .io_smi_resp_valid(src_conv_io_smi_resp_valid),
+ .io_smi_resp_bits(src_conv_io_smi_resp_bits)
+ );
+ NastiArbiter_83 T_8121 (
+ .clk(T_8121_clk),
+ .reset(T_8121_reset),
+ .io_master_0_aw_ready(T_8121_io_master_0_aw_ready),
+ .io_master_0_aw_valid(T_8121_io_master_0_aw_valid),
+ .io_master_0_aw_bits_addr(T_8121_io_master_0_aw_bits_addr),
+ .io_master_0_aw_bits_len(T_8121_io_master_0_aw_bits_len),
+ .io_master_0_aw_bits_size(T_8121_io_master_0_aw_bits_size),
+ .io_master_0_aw_bits_burst(T_8121_io_master_0_aw_bits_burst),
+ .io_master_0_aw_bits_lock(T_8121_io_master_0_aw_bits_lock),
+ .io_master_0_aw_bits_cache(T_8121_io_master_0_aw_bits_cache),
+ .io_master_0_aw_bits_prot(T_8121_io_master_0_aw_bits_prot),
+ .io_master_0_aw_bits_qos(T_8121_io_master_0_aw_bits_qos),
+ .io_master_0_aw_bits_region(T_8121_io_master_0_aw_bits_region),
+ .io_master_0_aw_bits_id(T_8121_io_master_0_aw_bits_id),
+ .io_master_0_aw_bits_user(T_8121_io_master_0_aw_bits_user),
+ .io_master_0_w_ready(T_8121_io_master_0_w_ready),
+ .io_master_0_w_valid(T_8121_io_master_0_w_valid),
+ .io_master_0_w_bits_data(T_8121_io_master_0_w_bits_data),
+ .io_master_0_w_bits_last(T_8121_io_master_0_w_bits_last),
+ .io_master_0_w_bits_strb(T_8121_io_master_0_w_bits_strb),
+ .io_master_0_w_bits_user(T_8121_io_master_0_w_bits_user),
+ .io_master_0_b_ready(T_8121_io_master_0_b_ready),
+ .io_master_0_b_valid(T_8121_io_master_0_b_valid),
+ .io_master_0_b_bits_resp(T_8121_io_master_0_b_bits_resp),
+ .io_master_0_b_bits_id(T_8121_io_master_0_b_bits_id),
+ .io_master_0_b_bits_user(T_8121_io_master_0_b_bits_user),
+ .io_master_0_ar_ready(T_8121_io_master_0_ar_ready),
+ .io_master_0_ar_valid(T_8121_io_master_0_ar_valid),
+ .io_master_0_ar_bits_addr(T_8121_io_master_0_ar_bits_addr),
+ .io_master_0_ar_bits_len(T_8121_io_master_0_ar_bits_len),
+ .io_master_0_ar_bits_size(T_8121_io_master_0_ar_bits_size),
+ .io_master_0_ar_bits_burst(T_8121_io_master_0_ar_bits_burst),
+ .io_master_0_ar_bits_lock(T_8121_io_master_0_ar_bits_lock),
+ .io_master_0_ar_bits_cache(T_8121_io_master_0_ar_bits_cache),
+ .io_master_0_ar_bits_prot(T_8121_io_master_0_ar_bits_prot),
+ .io_master_0_ar_bits_qos(T_8121_io_master_0_ar_bits_qos),
+ .io_master_0_ar_bits_region(T_8121_io_master_0_ar_bits_region),
+ .io_master_0_ar_bits_id(T_8121_io_master_0_ar_bits_id),
+ .io_master_0_ar_bits_user(T_8121_io_master_0_ar_bits_user),
+ .io_master_0_r_ready(T_8121_io_master_0_r_ready),
+ .io_master_0_r_valid(T_8121_io_master_0_r_valid),
+ .io_master_0_r_bits_resp(T_8121_io_master_0_r_bits_resp),
+ .io_master_0_r_bits_data(T_8121_io_master_0_r_bits_data),
+ .io_master_0_r_bits_last(T_8121_io_master_0_r_bits_last),
+ .io_master_0_r_bits_id(T_8121_io_master_0_r_bits_id),
+ .io_master_0_r_bits_user(T_8121_io_master_0_r_bits_user),
+ .io_slave_aw_ready(T_8121_io_slave_aw_ready),
+ .io_slave_aw_valid(T_8121_io_slave_aw_valid),
+ .io_slave_aw_bits_addr(T_8121_io_slave_aw_bits_addr),
+ .io_slave_aw_bits_len(T_8121_io_slave_aw_bits_len),
+ .io_slave_aw_bits_size(T_8121_io_slave_aw_bits_size),
+ .io_slave_aw_bits_burst(T_8121_io_slave_aw_bits_burst),
+ .io_slave_aw_bits_lock(T_8121_io_slave_aw_bits_lock),
+ .io_slave_aw_bits_cache(T_8121_io_slave_aw_bits_cache),
+ .io_slave_aw_bits_prot(T_8121_io_slave_aw_bits_prot),
+ .io_slave_aw_bits_qos(T_8121_io_slave_aw_bits_qos),
+ .io_slave_aw_bits_region(T_8121_io_slave_aw_bits_region),
+ .io_slave_aw_bits_id(T_8121_io_slave_aw_bits_id),
+ .io_slave_aw_bits_user(T_8121_io_slave_aw_bits_user),
+ .io_slave_w_ready(T_8121_io_slave_w_ready),
+ .io_slave_w_valid(T_8121_io_slave_w_valid),
+ .io_slave_w_bits_data(T_8121_io_slave_w_bits_data),
+ .io_slave_w_bits_last(T_8121_io_slave_w_bits_last),
+ .io_slave_w_bits_strb(T_8121_io_slave_w_bits_strb),
+ .io_slave_w_bits_user(T_8121_io_slave_w_bits_user),
+ .io_slave_b_ready(T_8121_io_slave_b_ready),
+ .io_slave_b_valid(T_8121_io_slave_b_valid),
+ .io_slave_b_bits_resp(T_8121_io_slave_b_bits_resp),
+ .io_slave_b_bits_id(T_8121_io_slave_b_bits_id),
+ .io_slave_b_bits_user(T_8121_io_slave_b_bits_user),
+ .io_slave_ar_ready(T_8121_io_slave_ar_ready),
+ .io_slave_ar_valid(T_8121_io_slave_ar_valid),
+ .io_slave_ar_bits_addr(T_8121_io_slave_ar_bits_addr),
+ .io_slave_ar_bits_len(T_8121_io_slave_ar_bits_len),
+ .io_slave_ar_bits_size(T_8121_io_slave_ar_bits_size),
+ .io_slave_ar_bits_burst(T_8121_io_slave_ar_bits_burst),
+ .io_slave_ar_bits_lock(T_8121_io_slave_ar_bits_lock),
+ .io_slave_ar_bits_cache(T_8121_io_slave_ar_bits_cache),
+ .io_slave_ar_bits_prot(T_8121_io_slave_ar_bits_prot),
+ .io_slave_ar_bits_qos(T_8121_io_slave_ar_bits_qos),
+ .io_slave_ar_bits_region(T_8121_io_slave_ar_bits_region),
+ .io_slave_ar_bits_id(T_8121_io_slave_ar_bits_id),
+ .io_slave_ar_bits_user(T_8121_io_slave_ar_bits_user),
+ .io_slave_r_ready(T_8121_io_slave_r_ready),
+ .io_slave_r_valid(T_8121_io_slave_r_valid),
+ .io_slave_r_bits_resp(T_8121_io_slave_r_bits_resp),
+ .io_slave_r_bits_data(T_8121_io_slave_r_bits_data),
+ .io_slave_r_bits_last(T_8121_io_slave_r_bits_last),
+ .io_slave_r_bits_id(T_8121_io_slave_r_bits_id),
+ .io_slave_r_bits_user(T_8121_io_slave_r_bits_user)
+ );
+ MemIONastiIOConverter T_8122 (
+ .clk(T_8122_clk),
+ .reset(T_8122_reset),
+ .io_nasti_aw_ready(T_8122_io_nasti_aw_ready),
+ .io_nasti_aw_valid(T_8122_io_nasti_aw_valid),
+ .io_nasti_aw_bits_addr(T_8122_io_nasti_aw_bits_addr),
+ .io_nasti_aw_bits_len(T_8122_io_nasti_aw_bits_len),
+ .io_nasti_aw_bits_size(T_8122_io_nasti_aw_bits_size),
+ .io_nasti_aw_bits_burst(T_8122_io_nasti_aw_bits_burst),
+ .io_nasti_aw_bits_lock(T_8122_io_nasti_aw_bits_lock),
+ .io_nasti_aw_bits_cache(T_8122_io_nasti_aw_bits_cache),
+ .io_nasti_aw_bits_prot(T_8122_io_nasti_aw_bits_prot),
+ .io_nasti_aw_bits_qos(T_8122_io_nasti_aw_bits_qos),
+ .io_nasti_aw_bits_region(T_8122_io_nasti_aw_bits_region),
+ .io_nasti_aw_bits_id(T_8122_io_nasti_aw_bits_id),
+ .io_nasti_aw_bits_user(T_8122_io_nasti_aw_bits_user),
+ .io_nasti_w_ready(T_8122_io_nasti_w_ready),
+ .io_nasti_w_valid(T_8122_io_nasti_w_valid),
+ .io_nasti_w_bits_data(T_8122_io_nasti_w_bits_data),
+ .io_nasti_w_bits_last(T_8122_io_nasti_w_bits_last),
+ .io_nasti_w_bits_strb(T_8122_io_nasti_w_bits_strb),
+ .io_nasti_w_bits_user(T_8122_io_nasti_w_bits_user),
+ .io_nasti_b_ready(T_8122_io_nasti_b_ready),
+ .io_nasti_b_valid(T_8122_io_nasti_b_valid),
+ .io_nasti_b_bits_resp(T_8122_io_nasti_b_bits_resp),
+ .io_nasti_b_bits_id(T_8122_io_nasti_b_bits_id),
+ .io_nasti_b_bits_user(T_8122_io_nasti_b_bits_user),
+ .io_nasti_ar_ready(T_8122_io_nasti_ar_ready),
+ .io_nasti_ar_valid(T_8122_io_nasti_ar_valid),
+ .io_nasti_ar_bits_addr(T_8122_io_nasti_ar_bits_addr),
+ .io_nasti_ar_bits_len(T_8122_io_nasti_ar_bits_len),
+ .io_nasti_ar_bits_size(T_8122_io_nasti_ar_bits_size),
+ .io_nasti_ar_bits_burst(T_8122_io_nasti_ar_bits_burst),
+ .io_nasti_ar_bits_lock(T_8122_io_nasti_ar_bits_lock),
+ .io_nasti_ar_bits_cache(T_8122_io_nasti_ar_bits_cache),
+ .io_nasti_ar_bits_prot(T_8122_io_nasti_ar_bits_prot),
+ .io_nasti_ar_bits_qos(T_8122_io_nasti_ar_bits_qos),
+ .io_nasti_ar_bits_region(T_8122_io_nasti_ar_bits_region),
+ .io_nasti_ar_bits_id(T_8122_io_nasti_ar_bits_id),
+ .io_nasti_ar_bits_user(T_8122_io_nasti_ar_bits_user),
+ .io_nasti_r_ready(T_8122_io_nasti_r_ready),
+ .io_nasti_r_valid(T_8122_io_nasti_r_valid),
+ .io_nasti_r_bits_resp(T_8122_io_nasti_r_bits_resp),
+ .io_nasti_r_bits_data(T_8122_io_nasti_r_bits_data),
+ .io_nasti_r_bits_last(T_8122_io_nasti_r_bits_last),
+ .io_nasti_r_bits_id(T_8122_io_nasti_r_bits_id),
+ .io_nasti_r_bits_user(T_8122_io_nasti_r_bits_user),
+ .io_mem_req_cmd_ready(T_8122_io_mem_req_cmd_ready),
+ .io_mem_req_cmd_valid(T_8122_io_mem_req_cmd_valid),
+ .io_mem_req_cmd_bits_addr(T_8122_io_mem_req_cmd_bits_addr),
+ .io_mem_req_cmd_bits_tag(T_8122_io_mem_req_cmd_bits_tag),
+ .io_mem_req_cmd_bits_rw(T_8122_io_mem_req_cmd_bits_rw),
+ .io_mem_req_data_ready(T_8122_io_mem_req_data_ready),
+ .io_mem_req_data_valid(T_8122_io_mem_req_data_valid),
+ .io_mem_req_data_bits_data(T_8122_io_mem_req_data_bits_data),
+ .io_mem_resp_ready(T_8122_io_mem_resp_ready),
+ .io_mem_resp_valid(T_8122_io_mem_resp_valid),
+ .io_mem_resp_bits_data(T_8122_io_mem_resp_bits_data),
+ .io_mem_resp_bits_tag(T_8122_io_mem_resp_bits_tag)
+ );
+ MemSerdes T_8123 (
+ .clk(T_8123_clk),
+ .reset(T_8123_reset),
+ .io_wide_req_cmd_ready(T_8123_io_wide_req_cmd_ready),
+ .io_wide_req_cmd_valid(T_8123_io_wide_req_cmd_valid),
+ .io_wide_req_cmd_bits_addr(T_8123_io_wide_req_cmd_bits_addr),
+ .io_wide_req_cmd_bits_tag(T_8123_io_wide_req_cmd_bits_tag),
+ .io_wide_req_cmd_bits_rw(T_8123_io_wide_req_cmd_bits_rw),
+ .io_wide_req_data_ready(T_8123_io_wide_req_data_ready),
+ .io_wide_req_data_valid(T_8123_io_wide_req_data_valid),
+ .io_wide_req_data_bits_data(T_8123_io_wide_req_data_bits_data),
+ .io_wide_resp_ready(T_8123_io_wide_resp_ready),
+ .io_wide_resp_valid(T_8123_io_wide_resp_valid),
+ .io_wide_resp_bits_data(T_8123_io_wide_resp_bits_data),
+ .io_wide_resp_bits_tag(T_8123_io_wide_resp_bits_tag),
+ .io_narrow_req_ready(T_8123_io_narrow_req_ready),
+ .io_narrow_req_valid(T_8123_io_narrow_req_valid),
+ .io_narrow_req_bits(T_8123_io_narrow_req_bits),
+ .io_narrow_resp_valid(T_8123_io_narrow_resp_valid),
+ .io_narrow_resp_bits(T_8123_io_narrow_resp_bits)
+ );
+ assign io_tiles_cached_0_acquire_ready = l1tol2net_io_clients_0_acquire_ready;
+ assign io_tiles_cached_0_grant_valid = l1tol2net_io_clients_0_grant_valid;
+ assign io_tiles_cached_0_grant_bits_addr_beat = l1tol2net_io_clients_0_grant_bits_addr_beat;
+ assign io_tiles_cached_0_grant_bits_client_xact_id = l1tol2net_io_clients_0_grant_bits_client_xact_id;
+ assign io_tiles_cached_0_grant_bits_manager_xact_id = l1tol2net_io_clients_0_grant_bits_manager_xact_id;
+ assign io_tiles_cached_0_grant_bits_is_builtin_type = l1tol2net_io_clients_0_grant_bits_is_builtin_type;
+ assign io_tiles_cached_0_grant_bits_g_type = l1tol2net_io_clients_0_grant_bits_g_type;
+ assign io_tiles_cached_0_grant_bits_data = l1tol2net_io_clients_0_grant_bits_data;
+ assign io_tiles_cached_0_probe_valid = l1tol2net_io_clients_0_probe_valid;
+ assign io_tiles_cached_0_probe_bits_addr_block = l1tol2net_io_clients_0_probe_bits_addr_block;
+ assign io_tiles_cached_0_probe_bits_p_type = l1tol2net_io_clients_0_probe_bits_p_type;
+ assign io_tiles_cached_0_release_ready = l1tol2net_io_clients_0_release_ready;
+ assign io_tiles_uncached_0_acquire_ready = T_8064_io_in_acquire_ready;
+ assign io_tiles_uncached_0_grant_valid = T_8064_io_in_grant_valid;
+ assign io_tiles_uncached_0_grant_bits_addr_beat = T_8064_io_in_grant_bits_addr_beat;
+ assign io_tiles_uncached_0_grant_bits_client_xact_id = T_8064_io_in_grant_bits_client_xact_id;
+ assign io_tiles_uncached_0_grant_bits_manager_xact_id = T_8064_io_in_grant_bits_manager_xact_id;
+ assign io_tiles_uncached_0_grant_bits_is_builtin_type = T_8064_io_in_grant_bits_is_builtin_type;
+ assign io_tiles_uncached_0_grant_bits_g_type = T_8064_io_in_grant_bits_g_type;
+ assign io_tiles_uncached_0_grant_bits_data = T_8064_io_in_grant_bits_data;
+ assign io_htif_uncached_acquire_ready = T_8065_io_in_acquire_ready;
+ assign io_htif_uncached_grant_valid = T_8065_io_in_grant_valid;
+ assign io_htif_uncached_grant_bits_addr_beat = T_8065_io_in_grant_bits_addr_beat;
+ assign io_htif_uncached_grant_bits_client_xact_id = T_8065_io_in_grant_bits_client_xact_id;
+ assign io_htif_uncached_grant_bits_manager_xact_id = T_8065_io_in_grant_bits_manager_xact_id;
+ assign io_htif_uncached_grant_bits_is_builtin_type = T_8065_io_in_grant_bits_is_builtin_type;
+ assign io_htif_uncached_grant_bits_g_type = T_8065_io_in_grant_bits_g_type;
+ assign io_htif_uncached_grant_bits_data = T_8065_io_in_grant_bits_data;
+ assign io_mem_0_aw_valid = T_8132;
+ assign io_mem_0_aw_bits_addr = interconnect$_io_slaves_0_aw_bits_addr;
+ assign io_mem_0_aw_bits_len = interconnect$_io_slaves_0_aw_bits_len;
+ assign io_mem_0_aw_bits_size = interconnect$_io_slaves_0_aw_bits_size;
+ assign io_mem_0_aw_bits_burst = interconnect$_io_slaves_0_aw_bits_burst;
+ assign io_mem_0_aw_bits_lock = interconnect$_io_slaves_0_aw_bits_lock;
+ assign io_mem_0_aw_bits_cache = interconnect$_io_slaves_0_aw_bits_cache;
+ assign io_mem_0_aw_bits_prot = interconnect$_io_slaves_0_aw_bits_prot;
+ assign io_mem_0_aw_bits_qos = interconnect$_io_slaves_0_aw_bits_qos;
+ assign io_mem_0_aw_bits_region = interconnect$_io_slaves_0_aw_bits_region;
+ assign io_mem_0_aw_bits_id = interconnect$_io_slaves_0_aw_bits_id;
+ assign io_mem_0_aw_bits_user = interconnect$_io_slaves_0_aw_bits_user;
+ assign io_mem_0_w_valid = T_8137;
+ assign io_mem_0_w_bits_data = interconnect$_io_slaves_0_w_bits_data;
+ assign io_mem_0_w_bits_last = interconnect$_io_slaves_0_w_bits_last;
+ assign io_mem_0_w_bits_strb = interconnect$_io_slaves_0_w_bits_strb;
+ assign io_mem_0_w_bits_user = interconnect$_io_slaves_0_w_bits_user;
+ assign io_mem_0_b_ready = T_8146;
+ assign io_mem_0_ar_valid = T_8127;
+ assign io_mem_0_ar_bits_addr = interconnect$_io_slaves_0_ar_bits_addr;
+ assign io_mem_0_ar_bits_len = interconnect$_io_slaves_0_ar_bits_len;
+ assign io_mem_0_ar_bits_size = interconnect$_io_slaves_0_ar_bits_size;
+ assign io_mem_0_ar_bits_burst = interconnect$_io_slaves_0_ar_bits_burst;
+ assign io_mem_0_ar_bits_lock = interconnect$_io_slaves_0_ar_bits_lock;
+ assign io_mem_0_ar_bits_cache = interconnect$_io_slaves_0_ar_bits_cache;
+ assign io_mem_0_ar_bits_prot = interconnect$_io_slaves_0_ar_bits_prot;
+ assign io_mem_0_ar_bits_qos = interconnect$_io_slaves_0_ar_bits_qos;
+ assign io_mem_0_ar_bits_region = interconnect$_io_slaves_0_ar_bits_region;
+ assign io_mem_0_ar_bits_id = interconnect$_io_slaves_0_ar_bits_id;
+ assign io_mem_0_ar_bits_user = interconnect$_io_slaves_0_ar_bits_user;
+ assign io_mem_0_r_ready = T_8157;
+ assign io_mem_backup_req_valid = T_8123_io_narrow_req_valid;
+ assign io_mem_backup_req_bits = T_8123_io_narrow_req_bits;
+ assign io_csr_0_req_valid = T_8119_io_smi_req_valid;
+ assign io_csr_0_req_bits_rw = T_8119_io_smi_req_bits_rw;
+ assign io_csr_0_req_bits_addr = T_8119_io_smi_req_bits_addr;
+ assign io_csr_0_req_bits_data = T_8119_io_smi_req_bits_data;
+ assign io_csr_0_resp_ready = T_8119_io_smi_resp_ready;
+ assign io_scr_req_valid = src_conv_io_smi_req_valid;
+ assign io_scr_req_bits_rw = src_conv_io_smi_req_bits_rw;
+ assign io_scr_req_bits_addr = src_conv_io_smi_req_bits_addr;
+ assign io_scr_req_bits_data = src_conv_io_smi_req_bits_data;
+ assign io_scr_resp_ready = src_conv_io_smi_resp_ready;
+ assign io_mmio_aw_valid = interconnect$_io_slaves_4_aw_valid;
+ assign io_mmio_aw_bits_addr = interconnect$_io_slaves_4_aw_bits_addr;
+ assign io_mmio_aw_bits_len = interconnect$_io_slaves_4_aw_bits_len;
+ assign io_mmio_aw_bits_size = interconnect$_io_slaves_4_aw_bits_size;
+ assign io_mmio_aw_bits_burst = interconnect$_io_slaves_4_aw_bits_burst;
+ assign io_mmio_aw_bits_lock = interconnect$_io_slaves_4_aw_bits_lock;
+ assign io_mmio_aw_bits_cache = interconnect$_io_slaves_4_aw_bits_cache;
+ assign io_mmio_aw_bits_prot = interconnect$_io_slaves_4_aw_bits_prot;
+ assign io_mmio_aw_bits_qos = interconnect$_io_slaves_4_aw_bits_qos;
+ assign io_mmio_aw_bits_region = interconnect$_io_slaves_4_aw_bits_region;
+ assign io_mmio_aw_bits_id = interconnect$_io_slaves_4_aw_bits_id;
+ assign io_mmio_aw_bits_user = interconnect$_io_slaves_4_aw_bits_user;
+ assign io_mmio_w_valid = interconnect$_io_slaves_4_w_valid;
+ assign io_mmio_w_bits_data = interconnect$_io_slaves_4_w_bits_data;
+ assign io_mmio_w_bits_last = interconnect$_io_slaves_4_w_bits_last;
+ assign io_mmio_w_bits_strb = interconnect$_io_slaves_4_w_bits_strb;
+ assign io_mmio_w_bits_user = interconnect$_io_slaves_4_w_bits_user;
+ assign io_mmio_b_ready = interconnect$_io_slaves_4_b_ready;
+ assign io_mmio_ar_valid = interconnect$_io_slaves_4_ar_valid;
+ assign io_mmio_ar_bits_addr = interconnect$_io_slaves_4_ar_bits_addr;
+ assign io_mmio_ar_bits_len = interconnect$_io_slaves_4_ar_bits_len;
+ assign io_mmio_ar_bits_size = interconnect$_io_slaves_4_ar_bits_size;
+ assign io_mmio_ar_bits_burst = interconnect$_io_slaves_4_ar_bits_burst;
+ assign io_mmio_ar_bits_lock = interconnect$_io_slaves_4_ar_bits_lock;
+ assign io_mmio_ar_bits_cache = interconnect$_io_slaves_4_ar_bits_cache;
+ assign io_mmio_ar_bits_prot = interconnect$_io_slaves_4_ar_bits_prot;
+ assign io_mmio_ar_bits_qos = interconnect$_io_slaves_4_ar_bits_qos;
+ assign io_mmio_ar_bits_region = interconnect$_io_slaves_4_ar_bits_region;
+ assign io_mmio_ar_bits_id = interconnect$_io_slaves_4_ar_bits_id;
+ assign io_mmio_ar_bits_user = interconnect$_io_slaves_4_ar_bits_user;
+ assign io_mmio_r_ready = interconnect$_io_slaves_4_r_ready;
+ assign io_deviceTree_aw_valid = interconnect$_io_slaves_1_aw_valid;
+ assign io_deviceTree_aw_bits_addr = interconnect$_io_slaves_1_aw_bits_addr;
+ assign io_deviceTree_aw_bits_len = interconnect$_io_slaves_1_aw_bits_len;
+ assign io_deviceTree_aw_bits_size = interconnect$_io_slaves_1_aw_bits_size;
+ assign io_deviceTree_aw_bits_burst = interconnect$_io_slaves_1_aw_bits_burst;
+ assign io_deviceTree_aw_bits_lock = interconnect$_io_slaves_1_aw_bits_lock;
+ assign io_deviceTree_aw_bits_cache = interconnect$_io_slaves_1_aw_bits_cache;
+ assign io_deviceTree_aw_bits_prot = interconnect$_io_slaves_1_aw_bits_prot;
+ assign io_deviceTree_aw_bits_qos = interconnect$_io_slaves_1_aw_bits_qos;
+ assign io_deviceTree_aw_bits_region = interconnect$_io_slaves_1_aw_bits_region;
+ assign io_deviceTree_aw_bits_id = interconnect$_io_slaves_1_aw_bits_id;
+ assign io_deviceTree_aw_bits_user = interconnect$_io_slaves_1_aw_bits_user;
+ assign io_deviceTree_w_valid = interconnect$_io_slaves_1_w_valid;
+ assign io_deviceTree_w_bits_data = interconnect$_io_slaves_1_w_bits_data;
+ assign io_deviceTree_w_bits_last = interconnect$_io_slaves_1_w_bits_last;
+ assign io_deviceTree_w_bits_strb = interconnect$_io_slaves_1_w_bits_strb;
+ assign io_deviceTree_w_bits_user = interconnect$_io_slaves_1_w_bits_user;
+ assign io_deviceTree_b_ready = interconnect$_io_slaves_1_b_ready;
+ assign io_deviceTree_ar_valid = interconnect$_io_slaves_1_ar_valid;
+ assign io_deviceTree_ar_bits_addr = interconnect$_io_slaves_1_ar_bits_addr;
+ assign io_deviceTree_ar_bits_len = interconnect$_io_slaves_1_ar_bits_len;
+ assign io_deviceTree_ar_bits_size = interconnect$_io_slaves_1_ar_bits_size;
+ assign io_deviceTree_ar_bits_burst = interconnect$_io_slaves_1_ar_bits_burst;
+ assign io_deviceTree_ar_bits_lock = interconnect$_io_slaves_1_ar_bits_lock;
+ assign io_deviceTree_ar_bits_cache = interconnect$_io_slaves_1_ar_bits_cache;
+ assign io_deviceTree_ar_bits_prot = interconnect$_io_slaves_1_ar_bits_prot;
+ assign io_deviceTree_ar_bits_qos = interconnect$_io_slaves_1_ar_bits_qos;
+ assign io_deviceTree_ar_bits_region = interconnect$_io_slaves_1_ar_bits_region;
+ assign io_deviceTree_ar_bits_id = interconnect$_io_slaves_1_ar_bits_id;
+ assign io_deviceTree_ar_bits_user = interconnect$_io_slaves_1_ar_bits_user;
+ assign io_deviceTree_r_ready = interconnect$_io_slaves_1_r_ready;
+ assign io_dma_req_ready = GEN_0;
+ assign io_dma_resp_valid = GEN_1;
+ assign io_dma_resp_bits_client_xact_id = GEN_2;
+ assign io_dma_resp_bits_status = GEN_3;
+ assign T_8064_clk = clk;
+ assign T_8064_reset = reset;
+ assign T_8064_io_in_acquire_valid = io_tiles_uncached_0_acquire_valid;
+ assign T_8064_io_in_acquire_bits_addr_block = io_tiles_uncached_0_acquire_bits_addr_block;
+ assign T_8064_io_in_acquire_bits_client_xact_id = io_tiles_uncached_0_acquire_bits_client_xact_id;
+ assign T_8064_io_in_acquire_bits_addr_beat = io_tiles_uncached_0_acquire_bits_addr_beat;
+ assign T_8064_io_in_acquire_bits_is_builtin_type = io_tiles_uncached_0_acquire_bits_is_builtin_type;
+ assign T_8064_io_in_acquire_bits_a_type = io_tiles_uncached_0_acquire_bits_a_type;
+ assign T_8064_io_in_acquire_bits_union = io_tiles_uncached_0_acquire_bits_union;
+ assign T_8064_io_in_acquire_bits_data = io_tiles_uncached_0_acquire_bits_data;
+ assign T_8064_io_in_grant_ready = io_tiles_uncached_0_grant_ready;
+ assign T_8064_io_out_acquire_ready = l1tol2net_io_clients_1_acquire_ready;
+ assign T_8064_io_out_grant_valid = l1tol2net_io_clients_1_grant_valid;
+ assign T_8064_io_out_grant_bits_addr_beat = l1tol2net_io_clients_1_grant_bits_addr_beat;
+ assign T_8064_io_out_grant_bits_client_xact_id = l1tol2net_io_clients_1_grant_bits_client_xact_id;
+ assign T_8064_io_out_grant_bits_manager_xact_id = l1tol2net_io_clients_1_grant_bits_manager_xact_id;
+ assign T_8064_io_out_grant_bits_is_builtin_type = l1tol2net_io_clients_1_grant_bits_is_builtin_type;
+ assign T_8064_io_out_grant_bits_g_type = l1tol2net_io_clients_1_grant_bits_g_type;
+ assign T_8064_io_out_grant_bits_data = l1tol2net_io_clients_1_grant_bits_data;
+ assign T_8064_io_out_probe_valid = l1tol2net_io_clients_1_probe_valid;
+ assign T_8064_io_out_probe_bits_addr_block = l1tol2net_io_clients_1_probe_bits_addr_block;
+ assign T_8064_io_out_probe_bits_p_type = l1tol2net_io_clients_1_probe_bits_p_type;
+ assign T_8064_io_out_release_ready = l1tol2net_io_clients_1_release_ready;
+ assign T_8065_clk = clk;
+ assign T_8065_reset = reset;
+ assign T_8065_io_in_acquire_valid = io_htif_uncached_acquire_valid;
+ assign T_8065_io_in_acquire_bits_addr_block = io_htif_uncached_acquire_bits_addr_block;
+ assign T_8065_io_in_acquire_bits_client_xact_id = io_htif_uncached_acquire_bits_client_xact_id;
+ assign T_8065_io_in_acquire_bits_addr_beat = io_htif_uncached_acquire_bits_addr_beat;
+ assign T_8065_io_in_acquire_bits_is_builtin_type = io_htif_uncached_acquire_bits_is_builtin_type;
+ assign T_8065_io_in_acquire_bits_a_type = io_htif_uncached_acquire_bits_a_type;
+ assign T_8065_io_in_acquire_bits_union = io_htif_uncached_acquire_bits_union;
+ assign T_8065_io_in_acquire_bits_data = io_htif_uncached_acquire_bits_data;
+ assign T_8065_io_in_grant_ready = io_htif_uncached_grant_ready;
+ assign T_8065_io_out_acquire_ready = l1tol2net_io_clients_2_acquire_ready;
+ assign T_8065_io_out_grant_valid = l1tol2net_io_clients_2_grant_valid;
+ assign T_8065_io_out_grant_bits_addr_beat = l1tol2net_io_clients_2_grant_bits_addr_beat;
+ assign T_8065_io_out_grant_bits_client_xact_id = l1tol2net_io_clients_2_grant_bits_client_xact_id;
+ assign T_8065_io_out_grant_bits_manager_xact_id = l1tol2net_io_clients_2_grant_bits_manager_xact_id;
+ assign T_8065_io_out_grant_bits_is_builtin_type = l1tol2net_io_clients_2_grant_bits_is_builtin_type;
+ assign T_8065_io_out_grant_bits_g_type = l1tol2net_io_clients_2_grant_bits_g_type;
+ assign T_8065_io_out_grant_bits_data = l1tol2net_io_clients_2_grant_bits_data;
+ assign T_8065_io_out_probe_valid = l1tol2net_io_clients_2_probe_valid;
+ assign T_8065_io_out_probe_bits_addr_block = l1tol2net_io_clients_2_probe_bits_addr_block;
+ assign T_8065_io_out_probe_bits_p_type = l1tol2net_io_clients_2_probe_bits_p_type;
+ assign T_8065_io_out_release_ready = l1tol2net_io_clients_2_release_ready;
+ assign l1tol2net_clk = clk;
+ assign l1tol2net_reset = reset;
+ assign l1tol2net_io_clients_0_acquire_valid = io_tiles_cached_0_acquire_valid;
+ assign l1tol2net_io_clients_0_acquire_bits_addr_block = io_tiles_cached_0_acquire_bits_addr_block;
+ assign l1tol2net_io_clients_0_acquire_bits_client_xact_id = io_tiles_cached_0_acquire_bits_client_xact_id;
+ assign l1tol2net_io_clients_0_acquire_bits_addr_beat = io_tiles_cached_0_acquire_bits_addr_beat;
+ assign l1tol2net_io_clients_0_acquire_bits_is_builtin_type = io_tiles_cached_0_acquire_bits_is_builtin_type;
+ assign l1tol2net_io_clients_0_acquire_bits_a_type = io_tiles_cached_0_acquire_bits_a_type;
+ assign l1tol2net_io_clients_0_acquire_bits_union = io_tiles_cached_0_acquire_bits_union;
+ assign l1tol2net_io_clients_0_acquire_bits_data = io_tiles_cached_0_acquire_bits_data;
+ assign l1tol2net_io_clients_0_grant_ready = io_tiles_cached_0_grant_ready;
+ assign l1tol2net_io_clients_0_probe_ready = io_tiles_cached_0_probe_ready;
+ assign l1tol2net_io_clients_0_release_valid = io_tiles_cached_0_release_valid;
+ assign l1tol2net_io_clients_0_release_bits_addr_beat = io_tiles_cached_0_release_bits_addr_beat;
+ assign l1tol2net_io_clients_0_release_bits_addr_block = io_tiles_cached_0_release_bits_addr_block;
+ assign l1tol2net_io_clients_0_release_bits_client_xact_id = io_tiles_cached_0_release_bits_client_xact_id;
+ assign l1tol2net_io_clients_0_release_bits_voluntary = io_tiles_cached_0_release_bits_voluntary;
+ assign l1tol2net_io_clients_0_release_bits_r_type = io_tiles_cached_0_release_bits_r_type;
+ assign l1tol2net_io_clients_0_release_bits_data = io_tiles_cached_0_release_bits_data;
+ assign l1tol2net_io_clients_1_acquire_valid = T_8064_io_out_acquire_valid;
+ assign l1tol2net_io_clients_1_acquire_bits_addr_block = T_8064_io_out_acquire_bits_addr_block;
+ assign l1tol2net_io_clients_1_acquire_bits_client_xact_id = T_8064_io_out_acquire_bits_client_xact_id;
+ assign l1tol2net_io_clients_1_acquire_bits_addr_beat = T_8064_io_out_acquire_bits_addr_beat;
+ assign l1tol2net_io_clients_1_acquire_bits_is_builtin_type = T_8064_io_out_acquire_bits_is_builtin_type;
+ assign l1tol2net_io_clients_1_acquire_bits_a_type = T_8064_io_out_acquire_bits_a_type;
+ assign l1tol2net_io_clients_1_acquire_bits_union = T_8064_io_out_acquire_bits_union;
+ assign l1tol2net_io_clients_1_acquire_bits_data = T_8064_io_out_acquire_bits_data;
+ assign l1tol2net_io_clients_1_grant_ready = T_8064_io_out_grant_ready;
+ assign l1tol2net_io_clients_1_probe_ready = T_8064_io_out_probe_ready;
+ assign l1tol2net_io_clients_1_release_valid = T_8064_io_out_release_valid;
+ assign l1tol2net_io_clients_1_release_bits_addr_beat = T_8064_io_out_release_bits_addr_beat;
+ assign l1tol2net_io_clients_1_release_bits_addr_block = T_8064_io_out_release_bits_addr_block;
+ assign l1tol2net_io_clients_1_release_bits_client_xact_id = T_8064_io_out_release_bits_client_xact_id;
+ assign l1tol2net_io_clients_1_release_bits_voluntary = T_8064_io_out_release_bits_voluntary;
+ assign l1tol2net_io_clients_1_release_bits_r_type = T_8064_io_out_release_bits_r_type;
+ assign l1tol2net_io_clients_1_release_bits_data = T_8064_io_out_release_bits_data;
+ assign l1tol2net_io_clients_2_acquire_valid = T_8065_io_out_acquire_valid;
+ assign l1tol2net_io_clients_2_acquire_bits_addr_block = T_8065_io_out_acquire_bits_addr_block;
+ assign l1tol2net_io_clients_2_acquire_bits_client_xact_id = T_8065_io_out_acquire_bits_client_xact_id;
+ assign l1tol2net_io_clients_2_acquire_bits_addr_beat = T_8065_io_out_acquire_bits_addr_beat;
+ assign l1tol2net_io_clients_2_acquire_bits_is_builtin_type = T_8065_io_out_acquire_bits_is_builtin_type;
+ assign l1tol2net_io_clients_2_acquire_bits_a_type = T_8065_io_out_acquire_bits_a_type;
+ assign l1tol2net_io_clients_2_acquire_bits_union = T_8065_io_out_acquire_bits_union;
+ assign l1tol2net_io_clients_2_acquire_bits_data = T_8065_io_out_acquire_bits_data;
+ assign l1tol2net_io_clients_2_grant_ready = T_8065_io_out_grant_ready;
+ assign l1tol2net_io_clients_2_probe_ready = T_8065_io_out_probe_ready;
+ assign l1tol2net_io_clients_2_release_valid = T_8065_io_out_release_valid;
+ assign l1tol2net_io_clients_2_release_bits_addr_beat = T_8065_io_out_release_bits_addr_beat;
+ assign l1tol2net_io_clients_2_release_bits_addr_block = T_8065_io_out_release_bits_addr_block;
+ assign l1tol2net_io_clients_2_release_bits_client_xact_id = T_8065_io_out_release_bits_client_xact_id;
+ assign l1tol2net_io_clients_2_release_bits_voluntary = T_8065_io_out_release_bits_voluntary;
+ assign l1tol2net_io_clients_2_release_bits_r_type = T_8065_io_out_release_bits_r_type;
+ assign l1tol2net_io_clients_2_release_bits_data = T_8065_io_out_release_bits_data;
+ assign l1tol2net_io_managers_0_acquire_ready = T_8067_io_inner_acquire_ready;
+ assign l1tol2net_io_managers_0_grant_valid = T_8067_io_inner_grant_valid;
+ assign l1tol2net_io_managers_0_grant_bits_addr_beat = T_8067_io_inner_grant_bits_addr_beat;
+ assign l1tol2net_io_managers_0_grant_bits_client_xact_id = T_8067_io_inner_grant_bits_client_xact_id;
+ assign l1tol2net_io_managers_0_grant_bits_manager_xact_id = T_8067_io_inner_grant_bits_manager_xact_id;
+ assign l1tol2net_io_managers_0_grant_bits_is_builtin_type = T_8067_io_inner_grant_bits_is_builtin_type;
+ assign l1tol2net_io_managers_0_grant_bits_g_type = T_8067_io_inner_grant_bits_g_type;
+ assign l1tol2net_io_managers_0_grant_bits_data = T_8067_io_inner_grant_bits_data;
+ assign l1tol2net_io_managers_0_grant_bits_client_id = T_8067_io_inner_grant_bits_client_id;
+ assign l1tol2net_io_managers_0_finish_ready = T_8067_io_inner_finish_ready;
+ assign l1tol2net_io_managers_0_probe_valid = T_8067_io_inner_probe_valid;
+ assign l1tol2net_io_managers_0_probe_bits_addr_block = T_8067_io_inner_probe_bits_addr_block;
+ assign l1tol2net_io_managers_0_probe_bits_p_type = T_8067_io_inner_probe_bits_p_type;
+ assign l1tol2net_io_managers_0_probe_bits_client_id = T_8067_io_inner_probe_bits_client_id;
+ assign l1tol2net_io_managers_0_release_ready = T_8067_io_inner_release_ready;
+ assign T_8067_clk = clk;
+ assign T_8067_reset = reset;
+ assign T_8067_io_inner_acquire_valid = l1tol2net_io_managers_0_acquire_valid;
+ assign T_8067_io_inner_acquire_bits_addr_block = l1tol2net_io_managers_0_acquire_bits_addr_block;
+ assign T_8067_io_inner_acquire_bits_client_xact_id = l1tol2net_io_managers_0_acquire_bits_client_xact_id;
+ assign T_8067_io_inner_acquire_bits_addr_beat = l1tol2net_io_managers_0_acquire_bits_addr_beat;
+ assign T_8067_io_inner_acquire_bits_is_builtin_type = l1tol2net_io_managers_0_acquire_bits_is_builtin_type;
+ assign T_8067_io_inner_acquire_bits_a_type = l1tol2net_io_managers_0_acquire_bits_a_type;
+ assign T_8067_io_inner_acquire_bits_union = l1tol2net_io_managers_0_acquire_bits_union;
+ assign T_8067_io_inner_acquire_bits_data = l1tol2net_io_managers_0_acquire_bits_data;
+ assign T_8067_io_inner_acquire_bits_client_id = l1tol2net_io_managers_0_acquire_bits_client_id;
+ assign T_8067_io_inner_grant_ready = l1tol2net_io_managers_0_grant_ready;
+ assign T_8067_io_inner_finish_valid = l1tol2net_io_managers_0_finish_valid;
+ assign T_8067_io_inner_finish_bits_manager_xact_id = l1tol2net_io_managers_0_finish_bits_manager_xact_id;
+ assign T_8067_io_inner_probe_ready = l1tol2net_io_managers_0_probe_ready;
+ assign T_8067_io_inner_release_valid = l1tol2net_io_managers_0_release_valid;
+ assign T_8067_io_inner_release_bits_addr_beat = l1tol2net_io_managers_0_release_bits_addr_beat;
+ assign T_8067_io_inner_release_bits_addr_block = l1tol2net_io_managers_0_release_bits_addr_block;
+ assign T_8067_io_inner_release_bits_client_xact_id = l1tol2net_io_managers_0_release_bits_client_xact_id;
+ assign T_8067_io_inner_release_bits_voluntary = l1tol2net_io_managers_0_release_bits_voluntary;
+ assign T_8067_io_inner_release_bits_r_type = l1tol2net_io_managers_0_release_bits_r_type;
+ assign T_8067_io_inner_release_bits_data = l1tol2net_io_managers_0_release_bits_data;
+ assign T_8067_io_inner_release_bits_client_id = l1tol2net_io_managers_0_release_bits_client_id;
+ assign T_8067_io_incoherent_0 = io_incoherent_0;
+ assign T_8067_io_outer_acquire_ready = T_8072_io_in_acquire_ready;
+ assign T_8067_io_outer_grant_valid = T_8072_io_in_grant_valid;
+ assign T_8067_io_outer_grant_bits_addr_beat = T_8072_io_in_grant_bits_addr_beat;
+ assign T_8067_io_outer_grant_bits_client_xact_id = T_8072_io_in_grant_bits_client_xact_id;
+ assign T_8067_io_outer_grant_bits_manager_xact_id = T_8072_io_in_grant_bits_manager_xact_id;
+ assign T_8067_io_outer_grant_bits_is_builtin_type = T_8072_io_in_grant_bits_is_builtin_type;
+ assign T_8067_io_outer_grant_bits_g_type = T_8072_io_in_grant_bits_g_type;
+ assign T_8067_io_outer_grant_bits_data = T_8072_io_in_grant_bits_data;
+ assign interconnect$_clk = clk;
+ assign interconnect$_reset = reset;
+ assign interconnect$_io_masters_0_aw_valid = T_8099_io_deq_valid;
+ assign interconnect$_io_masters_0_aw_bits_addr = T_8099_io_deq_bits_addr;
+ assign interconnect$_io_masters_0_aw_bits_len = T_8099_io_deq_bits_len;
+ assign interconnect$_io_masters_0_aw_bits_size = T_8099_io_deq_bits_size;
+ assign interconnect$_io_masters_0_aw_bits_burst = T_8099_io_deq_bits_burst;
+ assign interconnect$_io_masters_0_aw_bits_lock = T_8099_io_deq_bits_lock;
+ assign interconnect$_io_masters_0_aw_bits_cache = T_8099_io_deq_bits_cache;
+ assign interconnect$_io_masters_0_aw_bits_prot = T_8099_io_deq_bits_prot;
+ assign interconnect$_io_masters_0_aw_bits_qos = T_8099_io_deq_bits_qos;
+ assign interconnect$_io_masters_0_aw_bits_region = T_8099_io_deq_bits_region;
+ assign interconnect$_io_masters_0_aw_bits_id = T_8099_io_deq_bits_id;
+ assign interconnect$_io_masters_0_aw_bits_user = T_8099_io_deq_bits_user;
+ assign interconnect$_io_masters_0_w_valid = T_8105_io_deq_valid;
+ assign interconnect$_io_masters_0_w_bits_data = T_8105_io_deq_bits_data;
+ assign interconnect$_io_masters_0_w_bits_last = T_8105_io_deq_bits_last;
+ assign interconnect$_io_masters_0_w_bits_strb = T_8105_io_deq_bits_strb;
+ assign interconnect$_io_masters_0_w_bits_user = T_8105_io_deq_bits_user;
+ assign interconnect$_io_masters_0_b_ready = T_8117_io_enq_ready;
+ assign interconnect$_io_masters_0_ar_valid = T_8086_io_deq_valid;
+ assign interconnect$_io_masters_0_ar_bits_addr = T_8086_io_deq_bits_addr;
+ assign interconnect$_io_masters_0_ar_bits_len = T_8086_io_deq_bits_len;
+ assign interconnect$_io_masters_0_ar_bits_size = T_8086_io_deq_bits_size;
+ assign interconnect$_io_masters_0_ar_bits_burst = T_8086_io_deq_bits_burst;
+ assign interconnect$_io_masters_0_ar_bits_lock = T_8086_io_deq_bits_lock;
+ assign interconnect$_io_masters_0_ar_bits_cache = T_8086_io_deq_bits_cache;
+ assign interconnect$_io_masters_0_ar_bits_prot = T_8086_io_deq_bits_prot;
+ assign interconnect$_io_masters_0_ar_bits_qos = T_8086_io_deq_bits_qos;
+ assign interconnect$_io_masters_0_ar_bits_region = T_8086_io_deq_bits_region;
+ assign interconnect$_io_masters_0_ar_bits_id = T_8086_io_deq_bits_id;
+ assign interconnect$_io_masters_0_ar_bits_user = T_8086_io_deq_bits_user;
+ assign interconnect$_io_masters_0_r_ready = T_8112_io_enq_ready;
+ assign interconnect$_io_masters_1_aw_valid = rtc_io_aw_valid;
+ assign interconnect$_io_masters_1_aw_bits_addr = rtc_io_aw_bits_addr;
+ assign interconnect$_io_masters_1_aw_bits_len = rtc_io_aw_bits_len;
+ assign interconnect$_io_masters_1_aw_bits_size = rtc_io_aw_bits_size;
+ assign interconnect$_io_masters_1_aw_bits_burst = rtc_io_aw_bits_burst;
+ assign interconnect$_io_masters_1_aw_bits_lock = rtc_io_aw_bits_lock;
+ assign interconnect$_io_masters_1_aw_bits_cache = rtc_io_aw_bits_cache;
+ assign interconnect$_io_masters_1_aw_bits_prot = rtc_io_aw_bits_prot;
+ assign interconnect$_io_masters_1_aw_bits_qos = rtc_io_aw_bits_qos;
+ assign interconnect$_io_masters_1_aw_bits_region = rtc_io_aw_bits_region;
+ assign interconnect$_io_masters_1_aw_bits_id = rtc_io_aw_bits_id;
+ assign interconnect$_io_masters_1_aw_bits_user = rtc_io_aw_bits_user;
+ assign interconnect$_io_masters_1_w_valid = rtc_io_w_valid;
+ assign interconnect$_io_masters_1_w_bits_data = rtc_io_w_bits_data;
+ assign interconnect$_io_masters_1_w_bits_last = rtc_io_w_bits_last;
+ assign interconnect$_io_masters_1_w_bits_strb = rtc_io_w_bits_strb;
+ assign interconnect$_io_masters_1_w_bits_user = rtc_io_w_bits_user;
+ assign interconnect$_io_masters_1_b_ready = rtc_io_b_ready;
+ assign interconnect$_io_masters_1_ar_valid = rtc_io_ar_valid;
+ assign interconnect$_io_masters_1_ar_bits_addr = rtc_io_ar_bits_addr;
+ assign interconnect$_io_masters_1_ar_bits_len = rtc_io_ar_bits_len;
+ assign interconnect$_io_masters_1_ar_bits_size = rtc_io_ar_bits_size;
+ assign interconnect$_io_masters_1_ar_bits_burst = rtc_io_ar_bits_burst;
+ assign interconnect$_io_masters_1_ar_bits_lock = rtc_io_ar_bits_lock;
+ assign interconnect$_io_masters_1_ar_bits_cache = rtc_io_ar_bits_cache;
+ assign interconnect$_io_masters_1_ar_bits_prot = rtc_io_ar_bits_prot;
+ assign interconnect$_io_masters_1_ar_bits_qos = rtc_io_ar_bits_qos;
+ assign interconnect$_io_masters_1_ar_bits_region = rtc_io_ar_bits_region;
+ assign interconnect$_io_masters_1_ar_bits_id = rtc_io_ar_bits_id;
+ assign interconnect$_io_masters_1_ar_bits_user = rtc_io_ar_bits_user;
+ assign interconnect$_io_masters_1_r_ready = rtc_io_r_ready;
+ assign interconnect$_io_slaves_0_aw_ready = T_8129;
+ assign interconnect$_io_slaves_0_w_ready = T_8134;
+ assign interconnect$_io_slaves_0_b_valid = T_8139;
+ assign interconnect$_io_slaves_0_b_bits_resp = T_8140_resp;
+ assign interconnect$_io_slaves_0_b_bits_id = T_8140_id;
+ assign interconnect$_io_slaves_0_b_bits_user = T_8140_user;
+ assign interconnect$_io_slaves_0_ar_ready = T_8124;
+ assign interconnect$_io_slaves_0_r_valid = T_8148;
+ assign interconnect$_io_slaves_0_r_bits_resp = T_8149_resp;
+ assign interconnect$_io_slaves_0_r_bits_data = T_8149_data;
+ assign interconnect$_io_slaves_0_r_bits_last = T_8149_last;
+ assign interconnect$_io_slaves_0_r_bits_id = T_8149_id;
+ assign interconnect$_io_slaves_0_r_bits_user = T_8149_user;
+ assign interconnect$_io_slaves_1_aw_ready = io_deviceTree_aw_ready;
+ assign interconnect$_io_slaves_1_w_ready = io_deviceTree_w_ready;
+ assign interconnect$_io_slaves_1_b_valid = io_deviceTree_b_valid;
+ assign interconnect$_io_slaves_1_b_bits_resp = io_deviceTree_b_bits_resp;
+ assign interconnect$_io_slaves_1_b_bits_id = io_deviceTree_b_bits_id;
+ assign interconnect$_io_slaves_1_b_bits_user = io_deviceTree_b_bits_user;
+ assign interconnect$_io_slaves_1_ar_ready = io_deviceTree_ar_ready;
+ assign interconnect$_io_slaves_1_r_valid = io_deviceTree_r_valid;
+ assign interconnect$_io_slaves_1_r_bits_resp = io_deviceTree_r_bits_resp;
+ assign interconnect$_io_slaves_1_r_bits_data = io_deviceTree_r_bits_data;
+ assign interconnect$_io_slaves_1_r_bits_last = io_deviceTree_r_bits_last;
+ assign interconnect$_io_slaves_1_r_bits_id = io_deviceTree_r_bits_id;
+ assign interconnect$_io_slaves_1_r_bits_user = io_deviceTree_r_bits_user;
+ assign interconnect$_io_slaves_2_aw_ready = T_8119_io_nasti_aw_ready;
+ assign interconnect$_io_slaves_2_w_ready = T_8119_io_nasti_w_ready;
+ assign interconnect$_io_slaves_2_b_valid = T_8119_io_nasti_b_valid;
+ assign interconnect$_io_slaves_2_b_bits_resp = T_8119_io_nasti_b_bits_resp;
+ assign interconnect$_io_slaves_2_b_bits_id = T_8119_io_nasti_b_bits_id;
+ assign interconnect$_io_slaves_2_b_bits_user = T_8119_io_nasti_b_bits_user;
+ assign interconnect$_io_slaves_2_ar_ready = T_8119_io_nasti_ar_ready;
+ assign interconnect$_io_slaves_2_r_valid = T_8119_io_nasti_r_valid;
+ assign interconnect$_io_slaves_2_r_bits_resp = T_8119_io_nasti_r_bits_resp;
+ assign interconnect$_io_slaves_2_r_bits_data = T_8119_io_nasti_r_bits_data;
+ assign interconnect$_io_slaves_2_r_bits_last = T_8119_io_nasti_r_bits_last;
+ assign interconnect$_io_slaves_2_r_bits_id = T_8119_io_nasti_r_bits_id;
+ assign interconnect$_io_slaves_2_r_bits_user = T_8119_io_nasti_r_bits_user;
+ assign interconnect$_io_slaves_3_aw_ready = src_conv_io_nasti_aw_ready;
+ assign interconnect$_io_slaves_3_w_ready = src_conv_io_nasti_w_ready;
+ assign interconnect$_io_slaves_3_b_valid = src_conv_io_nasti_b_valid;
+ assign interconnect$_io_slaves_3_b_bits_resp = src_conv_io_nasti_b_bits_resp;
+ assign interconnect$_io_slaves_3_b_bits_id = src_conv_io_nasti_b_bits_id;
+ assign interconnect$_io_slaves_3_b_bits_user = src_conv_io_nasti_b_bits_user;
+ assign interconnect$_io_slaves_3_ar_ready = src_conv_io_nasti_ar_ready;
+ assign interconnect$_io_slaves_3_r_valid = src_conv_io_nasti_r_valid;
+ assign interconnect$_io_slaves_3_r_bits_resp = src_conv_io_nasti_r_bits_resp;
+ assign interconnect$_io_slaves_3_r_bits_data = src_conv_io_nasti_r_bits_data;
+ assign interconnect$_io_slaves_3_r_bits_last = src_conv_io_nasti_r_bits_last;
+ assign interconnect$_io_slaves_3_r_bits_id = src_conv_io_nasti_r_bits_id;
+ assign interconnect$_io_slaves_3_r_bits_user = src_conv_io_nasti_r_bits_user;
+ assign interconnect$_io_slaves_4_aw_ready = io_mmio_aw_ready;
+ assign interconnect$_io_slaves_4_w_ready = io_mmio_w_ready;
+ assign interconnect$_io_slaves_4_b_valid = io_mmio_b_valid;
+ assign interconnect$_io_slaves_4_b_bits_resp = io_mmio_b_bits_resp;
+ assign interconnect$_io_slaves_4_b_bits_id = io_mmio_b_bits_id;
+ assign interconnect$_io_slaves_4_b_bits_user = io_mmio_b_bits_user;
+ assign interconnect$_io_slaves_4_ar_ready = io_mmio_ar_ready;
+ assign interconnect$_io_slaves_4_r_valid = io_mmio_r_valid;
+ assign interconnect$_io_slaves_4_r_bits_resp = io_mmio_r_bits_resp;
+ assign interconnect$_io_slaves_4_r_bits_data = io_mmio_r_bits_data;
+ assign interconnect$_io_slaves_4_r_bits_last = io_mmio_r_bits_last;
+ assign interconnect$_io_slaves_4_r_bits_id = io_mmio_r_bits_id;
+ assign interconnect$_io_slaves_4_r_bits_user = io_mmio_r_bits_user;
+ assign T_8069_clk = clk;
+ assign T_8069_reset = reset;
+ assign T_8069_io_in_acquire_valid = T_8073_io_outer_acquire_valid;
+ assign T_8069_io_in_acquire_bits_addr_block = T_8073_io_outer_acquire_bits_addr_block;
+ assign T_8069_io_in_acquire_bits_client_xact_id = T_8073_io_outer_acquire_bits_client_xact_id;
+ assign T_8069_io_in_acquire_bits_addr_beat = T_8073_io_outer_acquire_bits_addr_beat;
+ assign T_8069_io_in_acquire_bits_is_builtin_type = T_8073_io_outer_acquire_bits_is_builtin_type;
+ assign T_8069_io_in_acquire_bits_a_type = T_8073_io_outer_acquire_bits_a_type;
+ assign T_8069_io_in_acquire_bits_union = T_8073_io_outer_acquire_bits_union;
+ assign T_8069_io_in_acquire_bits_data = T_8073_io_outer_acquire_bits_data;
+ assign T_8069_io_in_grant_ready = T_8073_io_outer_grant_ready;
+ assign T_8069_io_in_probe_ready = T_8073_io_outer_probe_ready;
+ assign T_8069_io_in_release_valid = T_8073_io_outer_release_valid;
+ assign T_8069_io_in_release_bits_addr_beat = T_8073_io_outer_release_bits_addr_beat;
+ assign T_8069_io_in_release_bits_addr_block = T_8073_io_outer_release_bits_addr_block;
+ assign T_8069_io_in_release_bits_client_xact_id = T_8073_io_outer_release_bits_client_xact_id;
+ assign T_8069_io_in_release_bits_voluntary = T_8073_io_outer_release_bits_voluntary;
+ assign T_8069_io_in_release_bits_r_type = T_8073_io_outer_release_bits_r_type;
+ assign T_8069_io_in_release_bits_data = T_8073_io_outer_release_bits_data;
+ assign T_8069_io_out_acquire_ready = T_8070_io_in_acquire_ready;
+ assign T_8069_io_out_grant_valid = T_8070_io_in_grant_valid;
+ assign T_8069_io_out_grant_bits_addr_beat = T_8070_io_in_grant_bits_addr_beat;
+ assign T_8069_io_out_grant_bits_client_xact_id = T_8070_io_in_grant_bits_client_xact_id;
+ assign T_8069_io_out_grant_bits_manager_xact_id = T_8070_io_in_grant_bits_manager_xact_id;
+ assign T_8069_io_out_grant_bits_is_builtin_type = T_8070_io_in_grant_bits_is_builtin_type;
+ assign T_8069_io_out_grant_bits_g_type = T_8070_io_in_grant_bits_g_type;
+ assign T_8069_io_out_grant_bits_data = T_8070_io_in_grant_bits_data;
+ assign T_8070_clk = clk;
+ assign T_8070_reset = reset;
+ assign T_8070_io_in_acquire_valid = T_8069_io_out_acquire_valid;
+ assign T_8070_io_in_acquire_bits_addr_block = T_8069_io_out_acquire_bits_addr_block;
+ assign T_8070_io_in_acquire_bits_client_xact_id = T_8069_io_out_acquire_bits_client_xact_id;
+ assign T_8070_io_in_acquire_bits_addr_beat = T_8069_io_out_acquire_bits_addr_beat;
+ assign T_8070_io_in_acquire_bits_is_builtin_type = T_8069_io_out_acquire_bits_is_builtin_type;
+ assign T_8070_io_in_acquire_bits_a_type = T_8069_io_out_acquire_bits_a_type;
+ assign T_8070_io_in_acquire_bits_union = T_8069_io_out_acquire_bits_union;
+ assign T_8070_io_in_acquire_bits_data = T_8069_io_out_acquire_bits_data;
+ assign T_8070_io_in_grant_ready = T_8069_io_out_grant_ready;
+ assign T_8070_io_out_acquire_ready = T_8071_io_tl_acquire_ready;
+ assign T_8070_io_out_grant_valid = T_8071_io_tl_grant_valid;
+ assign T_8070_io_out_grant_bits_addr_beat = T_8071_io_tl_grant_bits_addr_beat;
+ assign T_8070_io_out_grant_bits_client_xact_id = T_8071_io_tl_grant_bits_client_xact_id;
+ assign T_8070_io_out_grant_bits_manager_xact_id = T_8071_io_tl_grant_bits_manager_xact_id;
+ assign T_8070_io_out_grant_bits_is_builtin_type = T_8071_io_tl_grant_bits_is_builtin_type;
+ assign T_8070_io_out_grant_bits_g_type = T_8071_io_tl_grant_bits_g_type;
+ assign T_8070_io_out_grant_bits_data = T_8071_io_tl_grant_bits_data;
+ assign T_8071_clk = clk;
+ assign T_8071_reset = reset;
+ assign T_8071_io_tl_acquire_valid = T_8070_io_out_acquire_valid;
+ assign T_8071_io_tl_acquire_bits_addr_block = T_8070_io_out_acquire_bits_addr_block;
+ assign T_8071_io_tl_acquire_bits_client_xact_id = T_8070_io_out_acquire_bits_client_xact_id;
+ assign T_8071_io_tl_acquire_bits_addr_beat = T_8070_io_out_acquire_bits_addr_beat;
+ assign T_8071_io_tl_acquire_bits_is_builtin_type = T_8070_io_out_acquire_bits_is_builtin_type;
+ assign T_8071_io_tl_acquire_bits_a_type = T_8070_io_out_acquire_bits_a_type;
+ assign T_8071_io_tl_acquire_bits_union = T_8070_io_out_acquire_bits_union;
+ assign T_8071_io_tl_acquire_bits_data = T_8070_io_out_acquire_bits_data;
+ assign T_8071_io_tl_grant_ready = T_8070_io_out_grant_ready;
+ assign T_8071_io_nasti_aw_ready = T_8099_io_enq_ready;
+ assign T_8071_io_nasti_w_ready = T_8105_io_enq_ready;
+ assign T_8071_io_nasti_b_valid = T_8117_io_deq_valid;
+ assign T_8071_io_nasti_b_bits_resp = T_8117_io_deq_bits_resp;
+ assign T_8071_io_nasti_b_bits_id = T_8117_io_deq_bits_id;
+ assign T_8071_io_nasti_b_bits_user = T_8117_io_deq_bits_user;
+ assign T_8071_io_nasti_ar_ready = T_8086_io_enq_ready;
+ assign T_8071_io_nasti_r_valid = T_8112_io_deq_valid;
+ assign T_8071_io_nasti_r_bits_resp = T_8112_io_deq_bits_resp;
+ assign T_8071_io_nasti_r_bits_data = T_8112_io_deq_bits_data;
+ assign T_8071_io_nasti_r_bits_last = T_8112_io_deq_bits_last;
+ assign T_8071_io_nasti_r_bits_id = T_8112_io_deq_bits_id;
+ assign T_8071_io_nasti_r_bits_user = T_8112_io_deq_bits_user;
+ assign T_8072_clk = clk;
+ assign T_8072_reset = reset;
+ assign T_8072_io_in_acquire_valid = T_8067_io_outer_acquire_valid;
+ assign T_8072_io_in_acquire_bits_addr_block = T_8067_io_outer_acquire_bits_addr_block;
+ assign T_8072_io_in_acquire_bits_client_xact_id = T_8067_io_outer_acquire_bits_client_xact_id;
+ assign T_8072_io_in_acquire_bits_addr_beat = T_8067_io_outer_acquire_bits_addr_beat;
+ assign T_8072_io_in_acquire_bits_is_builtin_type = T_8067_io_outer_acquire_bits_is_builtin_type;
+ assign T_8072_io_in_acquire_bits_a_type = T_8067_io_outer_acquire_bits_a_type;
+ assign T_8072_io_in_acquire_bits_union = T_8067_io_outer_acquire_bits_union;
+ assign T_8072_io_in_acquire_bits_data = T_8067_io_outer_acquire_bits_data;
+ assign T_8072_io_in_grant_ready = T_8067_io_outer_grant_ready;
+ assign T_8072_io_out_acquire_ready = T_8073_io_inner_acquire_ready;
+ assign T_8072_io_out_grant_valid = T_8073_io_inner_grant_valid;
+ assign T_8072_io_out_grant_bits_addr_beat = T_8073_io_inner_grant_bits_addr_beat;
+ assign T_8072_io_out_grant_bits_client_xact_id = T_8073_io_inner_grant_bits_client_xact_id;
+ assign T_8072_io_out_grant_bits_manager_xact_id = T_8073_io_inner_grant_bits_manager_xact_id;
+ assign T_8072_io_out_grant_bits_is_builtin_type = T_8073_io_inner_grant_bits_is_builtin_type;
+ assign T_8072_io_out_grant_bits_g_type = T_8073_io_inner_grant_bits_g_type;
+ assign T_8072_io_out_grant_bits_data = T_8073_io_inner_grant_bits_data;
+ assign T_8072_io_out_probe_valid = T_8073_io_inner_probe_valid;
+ assign T_8072_io_out_probe_bits_addr_block = T_8073_io_inner_probe_bits_addr_block;
+ assign T_8072_io_out_probe_bits_p_type = T_8073_io_inner_probe_bits_p_type;
+ assign T_8072_io_out_release_ready = T_8073_io_inner_release_ready;
+ assign T_8073_clk = clk;
+ assign T_8073_reset = reset;
+ assign T_8073_io_inner_acquire_valid = T_8072_io_out_acquire_valid;
+ assign T_8073_io_inner_acquire_bits_addr_block = T_8072_io_out_acquire_bits_addr_block;
+ assign T_8073_io_inner_acquire_bits_client_xact_id = T_8072_io_out_acquire_bits_client_xact_id;
+ assign T_8073_io_inner_acquire_bits_addr_beat = T_8072_io_out_acquire_bits_addr_beat;
+ assign T_8073_io_inner_acquire_bits_is_builtin_type = T_8072_io_out_acquire_bits_is_builtin_type;
+ assign T_8073_io_inner_acquire_bits_a_type = T_8072_io_out_acquire_bits_a_type;
+ assign T_8073_io_inner_acquire_bits_union = T_8072_io_out_acquire_bits_union;
+ assign T_8073_io_inner_acquire_bits_data = T_8072_io_out_acquire_bits_data;
+ assign T_8073_io_inner_grant_ready = T_8072_io_out_grant_ready;
+ assign T_8073_io_inner_probe_ready = T_8072_io_out_probe_ready;
+ assign T_8073_io_inner_release_valid = T_8072_io_out_release_valid;
+ assign T_8073_io_inner_release_bits_addr_beat = T_8072_io_out_release_bits_addr_beat;
+ assign T_8073_io_inner_release_bits_addr_block = T_8072_io_out_release_bits_addr_block;
+ assign T_8073_io_inner_release_bits_client_xact_id = T_8072_io_out_release_bits_client_xact_id;
+ assign T_8073_io_inner_release_bits_voluntary = T_8072_io_out_release_bits_voluntary;
+ assign T_8073_io_inner_release_bits_r_type = T_8072_io_out_release_bits_r_type;
+ assign T_8073_io_inner_release_bits_data = T_8072_io_out_release_bits_data;
+ assign T_8073_io_outer_acquire_ready = T_8069_io_in_acquire_ready;
+ assign T_8073_io_outer_grant_valid = T_8069_io_in_grant_valid;
+ assign T_8073_io_outer_grant_bits_addr_beat = T_8069_io_in_grant_bits_addr_beat;
+ assign T_8073_io_outer_grant_bits_client_xact_id = T_8069_io_in_grant_bits_client_xact_id;
+ assign T_8073_io_outer_grant_bits_manager_xact_id = T_8069_io_in_grant_bits_manager_xact_id;
+ assign T_8073_io_outer_grant_bits_is_builtin_type = T_8069_io_in_grant_bits_is_builtin_type;
+ assign T_8073_io_outer_grant_bits_g_type = T_8069_io_in_grant_bits_g_type;
+ assign T_8073_io_outer_grant_bits_data = T_8069_io_in_grant_bits_data;
+ assign T_8073_io_outer_probe_valid = T_8069_io_in_probe_valid;
+ assign T_8073_io_outer_probe_bits_addr_block = T_8069_io_in_probe_bits_addr_block;
+ assign T_8073_io_outer_probe_bits_p_type = T_8069_io_in_probe_bits_p_type;
+ assign T_8073_io_outer_release_ready = T_8069_io_in_release_ready;
+ assign T_8086_clk = clk;
+ assign T_8086_reset = reset;
+ assign T_8086_io_enq_valid = T_8071_io_nasti_ar_valid;
+ assign T_8086_io_enq_bits_addr = T_8071_io_nasti_ar_bits_addr;
+ assign T_8086_io_enq_bits_len = T_8071_io_nasti_ar_bits_len;
+ assign T_8086_io_enq_bits_size = T_8071_io_nasti_ar_bits_size;
+ assign T_8086_io_enq_bits_burst = T_8071_io_nasti_ar_bits_burst;
+ assign T_8086_io_enq_bits_lock = T_8071_io_nasti_ar_bits_lock;
+ assign T_8086_io_enq_bits_cache = T_8071_io_nasti_ar_bits_cache;
+ assign T_8086_io_enq_bits_prot = T_8071_io_nasti_ar_bits_prot;
+ assign T_8086_io_enq_bits_qos = T_8071_io_nasti_ar_bits_qos;
+ assign T_8086_io_enq_bits_region = T_8071_io_nasti_ar_bits_region;
+ assign T_8086_io_enq_bits_id = T_8071_io_nasti_ar_bits_id;
+ assign T_8086_io_enq_bits_user = T_8071_io_nasti_ar_bits_user;
+ assign T_8086_io_deq_ready = interconnect$_io_masters_0_ar_ready;
+ assign T_8099_clk = clk;
+ assign T_8099_reset = reset;
+ assign T_8099_io_enq_valid = T_8071_io_nasti_aw_valid;
+ assign T_8099_io_enq_bits_addr = T_8071_io_nasti_aw_bits_addr;
+ assign T_8099_io_enq_bits_len = T_8071_io_nasti_aw_bits_len;
+ assign T_8099_io_enq_bits_size = T_8071_io_nasti_aw_bits_size;
+ assign T_8099_io_enq_bits_burst = T_8071_io_nasti_aw_bits_burst;
+ assign T_8099_io_enq_bits_lock = T_8071_io_nasti_aw_bits_lock;
+ assign T_8099_io_enq_bits_cache = T_8071_io_nasti_aw_bits_cache;
+ assign T_8099_io_enq_bits_prot = T_8071_io_nasti_aw_bits_prot;
+ assign T_8099_io_enq_bits_qos = T_8071_io_nasti_aw_bits_qos;
+ assign T_8099_io_enq_bits_region = T_8071_io_nasti_aw_bits_region;
+ assign T_8099_io_enq_bits_id = T_8071_io_nasti_aw_bits_id;
+ assign T_8099_io_enq_bits_user = T_8071_io_nasti_aw_bits_user;
+ assign T_8099_io_deq_ready = interconnect$_io_masters_0_aw_ready;
+ assign T_8105_clk = clk;
+ assign T_8105_reset = reset;
+ assign T_8105_io_enq_valid = T_8071_io_nasti_w_valid;
+ assign T_8105_io_enq_bits_data = T_8071_io_nasti_w_bits_data;
+ assign T_8105_io_enq_bits_last = T_8071_io_nasti_w_bits_last;
+ assign T_8105_io_enq_bits_strb = T_8071_io_nasti_w_bits_strb;
+ assign T_8105_io_enq_bits_user = T_8071_io_nasti_w_bits_user;
+ assign T_8105_io_deq_ready = interconnect$_io_masters_0_w_ready;
+ assign T_8112_clk = clk;
+ assign T_8112_reset = reset;
+ assign T_8112_io_enq_valid = interconnect$_io_masters_0_r_valid;
+ assign T_8112_io_enq_bits_resp = interconnect$_io_masters_0_r_bits_resp;
+ assign T_8112_io_enq_bits_data = interconnect$_io_masters_0_r_bits_data;
+ assign T_8112_io_enq_bits_last = interconnect$_io_masters_0_r_bits_last;
+ assign T_8112_io_enq_bits_id = interconnect$_io_masters_0_r_bits_id;
+ assign T_8112_io_enq_bits_user = interconnect$_io_masters_0_r_bits_user;
+ assign T_8112_io_deq_ready = T_8071_io_nasti_r_ready;
+ assign T_8117_clk = clk;
+ assign T_8117_reset = reset;
+ assign T_8117_io_enq_valid = interconnect$_io_masters_0_b_valid;
+ assign T_8117_io_enq_bits_resp = interconnect$_io_masters_0_b_bits_resp;
+ assign T_8117_io_enq_bits_id = interconnect$_io_masters_0_b_bits_id;
+ assign T_8117_io_enq_bits_user = interconnect$_io_masters_0_b_bits_user;
+ assign T_8117_io_deq_ready = T_8071_io_nasti_b_ready;
+ assign rtc_clk = clk;
+ assign rtc_reset = reset;
+ assign rtc_io_aw_ready = interconnect$_io_masters_1_aw_ready;
+ assign rtc_io_w_ready = interconnect$_io_masters_1_w_ready;
+ assign rtc_io_b_valid = interconnect$_io_masters_1_b_valid;
+ assign rtc_io_b_bits_resp = interconnect$_io_masters_1_b_bits_resp;
+ assign rtc_io_b_bits_id = interconnect$_io_masters_1_b_bits_id;
+ assign rtc_io_b_bits_user = interconnect$_io_masters_1_b_bits_user;
+ assign rtc_io_ar_ready = interconnect$_io_masters_1_ar_ready;
+ assign rtc_io_r_valid = interconnect$_io_masters_1_r_valid;
+ assign rtc_io_r_bits_resp = interconnect$_io_masters_1_r_bits_resp;
+ assign rtc_io_r_bits_data = interconnect$_io_masters_1_r_bits_data;
+ assign rtc_io_r_bits_last = interconnect$_io_masters_1_r_bits_last;
+ assign rtc_io_r_bits_id = interconnect$_io_masters_1_r_bits_id;
+ assign rtc_io_r_bits_user = interconnect$_io_masters_1_r_bits_user;
+ assign T_8119_clk = clk;
+ assign T_8119_reset = reset;
+ assign T_8119_io_nasti_aw_valid = interconnect$_io_slaves_2_aw_valid;
+ assign T_8119_io_nasti_aw_bits_addr = interconnect$_io_slaves_2_aw_bits_addr;
+ assign T_8119_io_nasti_aw_bits_len = interconnect$_io_slaves_2_aw_bits_len;
+ assign T_8119_io_nasti_aw_bits_size = interconnect$_io_slaves_2_aw_bits_size;
+ assign T_8119_io_nasti_aw_bits_burst = interconnect$_io_slaves_2_aw_bits_burst;
+ assign T_8119_io_nasti_aw_bits_lock = interconnect$_io_slaves_2_aw_bits_lock;
+ assign T_8119_io_nasti_aw_bits_cache = interconnect$_io_slaves_2_aw_bits_cache;
+ assign T_8119_io_nasti_aw_bits_prot = interconnect$_io_slaves_2_aw_bits_prot;
+ assign T_8119_io_nasti_aw_bits_qos = interconnect$_io_slaves_2_aw_bits_qos;
+ assign T_8119_io_nasti_aw_bits_region = interconnect$_io_slaves_2_aw_bits_region;
+ assign T_8119_io_nasti_aw_bits_id = interconnect$_io_slaves_2_aw_bits_id;
+ assign T_8119_io_nasti_aw_bits_user = interconnect$_io_slaves_2_aw_bits_user;
+ assign T_8119_io_nasti_w_valid = interconnect$_io_slaves_2_w_valid;
+ assign T_8119_io_nasti_w_bits_data = interconnect$_io_slaves_2_w_bits_data;
+ assign T_8119_io_nasti_w_bits_last = interconnect$_io_slaves_2_w_bits_last;
+ assign T_8119_io_nasti_w_bits_strb = interconnect$_io_slaves_2_w_bits_strb;
+ assign T_8119_io_nasti_w_bits_user = interconnect$_io_slaves_2_w_bits_user;
+ assign T_8119_io_nasti_b_ready = interconnect$_io_slaves_2_b_ready;
+ assign T_8119_io_nasti_ar_valid = interconnect$_io_slaves_2_ar_valid;
+ assign T_8119_io_nasti_ar_bits_addr = interconnect$_io_slaves_2_ar_bits_addr;
+ assign T_8119_io_nasti_ar_bits_len = interconnect$_io_slaves_2_ar_bits_len;
+ assign T_8119_io_nasti_ar_bits_size = interconnect$_io_slaves_2_ar_bits_size;
+ assign T_8119_io_nasti_ar_bits_burst = interconnect$_io_slaves_2_ar_bits_burst;
+ assign T_8119_io_nasti_ar_bits_lock = interconnect$_io_slaves_2_ar_bits_lock;
+ assign T_8119_io_nasti_ar_bits_cache = interconnect$_io_slaves_2_ar_bits_cache;
+ assign T_8119_io_nasti_ar_bits_prot = interconnect$_io_slaves_2_ar_bits_prot;
+ assign T_8119_io_nasti_ar_bits_qos = interconnect$_io_slaves_2_ar_bits_qos;
+ assign T_8119_io_nasti_ar_bits_region = interconnect$_io_slaves_2_ar_bits_region;
+ assign T_8119_io_nasti_ar_bits_id = interconnect$_io_slaves_2_ar_bits_id;
+ assign T_8119_io_nasti_ar_bits_user = interconnect$_io_slaves_2_ar_bits_user;
+ assign T_8119_io_nasti_r_ready = interconnect$_io_slaves_2_r_ready;
+ assign T_8119_io_smi_req_ready = io_csr_0_req_ready;
+ assign T_8119_io_smi_resp_valid = io_csr_0_resp_valid;
+ assign T_8119_io_smi_resp_bits = io_csr_0_resp_bits;
+ assign src_conv_clk = clk;
+ assign src_conv_reset = reset;
+ assign src_conv_io_nasti_aw_valid = interconnect$_io_slaves_3_aw_valid;
+ assign src_conv_io_nasti_aw_bits_addr = interconnect$_io_slaves_3_aw_bits_addr;
+ assign src_conv_io_nasti_aw_bits_len = interconnect$_io_slaves_3_aw_bits_len;
+ assign src_conv_io_nasti_aw_bits_size = interconnect$_io_slaves_3_aw_bits_size;
+ assign src_conv_io_nasti_aw_bits_burst = interconnect$_io_slaves_3_aw_bits_burst;
+ assign src_conv_io_nasti_aw_bits_lock = interconnect$_io_slaves_3_aw_bits_lock;
+ assign src_conv_io_nasti_aw_bits_cache = interconnect$_io_slaves_3_aw_bits_cache;
+ assign src_conv_io_nasti_aw_bits_prot = interconnect$_io_slaves_3_aw_bits_prot;
+ assign src_conv_io_nasti_aw_bits_qos = interconnect$_io_slaves_3_aw_bits_qos;
+ assign src_conv_io_nasti_aw_bits_region = interconnect$_io_slaves_3_aw_bits_region;
+ assign src_conv_io_nasti_aw_bits_id = interconnect$_io_slaves_3_aw_bits_id;
+ assign src_conv_io_nasti_aw_bits_user = interconnect$_io_slaves_3_aw_bits_user;
+ assign src_conv_io_nasti_w_valid = interconnect$_io_slaves_3_w_valid;
+ assign src_conv_io_nasti_w_bits_data = interconnect$_io_slaves_3_w_bits_data;
+ assign src_conv_io_nasti_w_bits_last = interconnect$_io_slaves_3_w_bits_last;
+ assign src_conv_io_nasti_w_bits_strb = interconnect$_io_slaves_3_w_bits_strb;
+ assign src_conv_io_nasti_w_bits_user = interconnect$_io_slaves_3_w_bits_user;
+ assign src_conv_io_nasti_b_ready = interconnect$_io_slaves_3_b_ready;
+ assign src_conv_io_nasti_ar_valid = interconnect$_io_slaves_3_ar_valid;
+ assign src_conv_io_nasti_ar_bits_addr = interconnect$_io_slaves_3_ar_bits_addr;
+ assign src_conv_io_nasti_ar_bits_len = interconnect$_io_slaves_3_ar_bits_len;
+ assign src_conv_io_nasti_ar_bits_size = interconnect$_io_slaves_3_ar_bits_size;
+ assign src_conv_io_nasti_ar_bits_burst = interconnect$_io_slaves_3_ar_bits_burst;
+ assign src_conv_io_nasti_ar_bits_lock = interconnect$_io_slaves_3_ar_bits_lock;
+ assign src_conv_io_nasti_ar_bits_cache = interconnect$_io_slaves_3_ar_bits_cache;
+ assign src_conv_io_nasti_ar_bits_prot = interconnect$_io_slaves_3_ar_bits_prot;
+ assign src_conv_io_nasti_ar_bits_qos = interconnect$_io_slaves_3_ar_bits_qos;
+ assign src_conv_io_nasti_ar_bits_region = interconnect$_io_slaves_3_ar_bits_region;
+ assign src_conv_io_nasti_ar_bits_id = interconnect$_io_slaves_3_ar_bits_id;
+ assign src_conv_io_nasti_ar_bits_user = interconnect$_io_slaves_3_ar_bits_user;
+ assign src_conv_io_nasti_r_ready = interconnect$_io_slaves_3_r_ready;
+ assign src_conv_io_smi_req_ready = io_scr_req_ready;
+ assign src_conv_io_smi_resp_valid = io_scr_resp_valid;
+ assign src_conv_io_smi_resp_bits = io_scr_resp_bits;
+ assign T_8121_clk = clk;
+ assign T_8121_reset = reset;
+ assign T_8121_io_master_0_aw_valid = T_8133;
+ assign T_8121_io_master_0_aw_bits_addr = interconnect$_io_slaves_0_aw_bits_addr;
+ assign T_8121_io_master_0_aw_bits_len = interconnect$_io_slaves_0_aw_bits_len;
+ assign T_8121_io_master_0_aw_bits_size = interconnect$_io_slaves_0_aw_bits_size;
+ assign T_8121_io_master_0_aw_bits_burst = interconnect$_io_slaves_0_aw_bits_burst;
+ assign T_8121_io_master_0_aw_bits_lock = interconnect$_io_slaves_0_aw_bits_lock;
+ assign T_8121_io_master_0_aw_bits_cache = interconnect$_io_slaves_0_aw_bits_cache;
+ assign T_8121_io_master_0_aw_bits_prot = interconnect$_io_slaves_0_aw_bits_prot;
+ assign T_8121_io_master_0_aw_bits_qos = interconnect$_io_slaves_0_aw_bits_qos;
+ assign T_8121_io_master_0_aw_bits_region = interconnect$_io_slaves_0_aw_bits_region;
+ assign T_8121_io_master_0_aw_bits_id = interconnect$_io_slaves_0_aw_bits_id;
+ assign T_8121_io_master_0_aw_bits_user = interconnect$_io_slaves_0_aw_bits_user;
+ assign T_8121_io_master_0_w_valid = T_8138;
+ assign T_8121_io_master_0_w_bits_data = interconnect$_io_slaves_0_w_bits_data;
+ assign T_8121_io_master_0_w_bits_last = interconnect$_io_slaves_0_w_bits_last;
+ assign T_8121_io_master_0_w_bits_strb = interconnect$_io_slaves_0_w_bits_strb;
+ assign T_8121_io_master_0_w_bits_user = interconnect$_io_slaves_0_w_bits_user;
+ assign T_8121_io_master_0_b_ready = T_8147;
+ assign T_8121_io_master_0_ar_valid = T_8128;
+ assign T_8121_io_master_0_ar_bits_addr = interconnect$_io_slaves_0_ar_bits_addr;
+ assign T_8121_io_master_0_ar_bits_len = interconnect$_io_slaves_0_ar_bits_len;
+ assign T_8121_io_master_0_ar_bits_size = interconnect$_io_slaves_0_ar_bits_size;
+ assign T_8121_io_master_0_ar_bits_burst = interconnect$_io_slaves_0_ar_bits_burst;
+ assign T_8121_io_master_0_ar_bits_lock = interconnect$_io_slaves_0_ar_bits_lock;
+ assign T_8121_io_master_0_ar_bits_cache = interconnect$_io_slaves_0_ar_bits_cache;
+ assign T_8121_io_master_0_ar_bits_prot = interconnect$_io_slaves_0_ar_bits_prot;
+ assign T_8121_io_master_0_ar_bits_qos = interconnect$_io_slaves_0_ar_bits_qos;
+ assign T_8121_io_master_0_ar_bits_region = interconnect$_io_slaves_0_ar_bits_region;
+ assign T_8121_io_master_0_ar_bits_id = interconnect$_io_slaves_0_ar_bits_id;
+ assign T_8121_io_master_0_ar_bits_user = interconnect$_io_slaves_0_ar_bits_user;
+ assign T_8121_io_master_0_r_ready = T_8158;
+ assign T_8121_io_slave_aw_ready = T_8122_io_nasti_aw_ready;
+ assign T_8121_io_slave_w_ready = T_8122_io_nasti_w_ready;
+ assign T_8121_io_slave_b_valid = T_8122_io_nasti_b_valid;
+ assign T_8121_io_slave_b_bits_resp = T_8122_io_nasti_b_bits_resp;
+ assign T_8121_io_slave_b_bits_id = T_8122_io_nasti_b_bits_id;
+ assign T_8121_io_slave_b_bits_user = T_8122_io_nasti_b_bits_user;
+ assign T_8121_io_slave_ar_ready = T_8122_io_nasti_ar_ready;
+ assign T_8121_io_slave_r_valid = T_8122_io_nasti_r_valid;
+ assign T_8121_io_slave_r_bits_resp = T_8122_io_nasti_r_bits_resp;
+ assign T_8121_io_slave_r_bits_data = T_8122_io_nasti_r_bits_data;
+ assign T_8121_io_slave_r_bits_last = T_8122_io_nasti_r_bits_last;
+ assign T_8121_io_slave_r_bits_id = T_8122_io_nasti_r_bits_id;
+ assign T_8121_io_slave_r_bits_user = T_8122_io_nasti_r_bits_user;
+ assign T_8122_clk = clk;
+ assign T_8122_reset = reset;
+ assign T_8122_io_nasti_aw_valid = T_8121_io_slave_aw_valid;
+ assign T_8122_io_nasti_aw_bits_addr = T_8121_io_slave_aw_bits_addr;
+ assign T_8122_io_nasti_aw_bits_len = T_8121_io_slave_aw_bits_len;
+ assign T_8122_io_nasti_aw_bits_size = T_8121_io_slave_aw_bits_size;
+ assign T_8122_io_nasti_aw_bits_burst = T_8121_io_slave_aw_bits_burst;
+ assign T_8122_io_nasti_aw_bits_lock = T_8121_io_slave_aw_bits_lock;
+ assign T_8122_io_nasti_aw_bits_cache = T_8121_io_slave_aw_bits_cache;
+ assign T_8122_io_nasti_aw_bits_prot = T_8121_io_slave_aw_bits_prot;
+ assign T_8122_io_nasti_aw_bits_qos = T_8121_io_slave_aw_bits_qos;
+ assign T_8122_io_nasti_aw_bits_region = T_8121_io_slave_aw_bits_region;
+ assign T_8122_io_nasti_aw_bits_id = T_8121_io_slave_aw_bits_id;
+ assign T_8122_io_nasti_aw_bits_user = T_8121_io_slave_aw_bits_user;
+ assign T_8122_io_nasti_w_valid = T_8121_io_slave_w_valid;
+ assign T_8122_io_nasti_w_bits_data = T_8121_io_slave_w_bits_data;
+ assign T_8122_io_nasti_w_bits_last = T_8121_io_slave_w_bits_last;
+ assign T_8122_io_nasti_w_bits_strb = T_8121_io_slave_w_bits_strb;
+ assign T_8122_io_nasti_w_bits_user = T_8121_io_slave_w_bits_user;
+ assign T_8122_io_nasti_b_ready = T_8121_io_slave_b_ready;
+ assign T_8122_io_nasti_ar_valid = T_8121_io_slave_ar_valid;
+ assign T_8122_io_nasti_ar_bits_addr = T_8121_io_slave_ar_bits_addr;
+ assign T_8122_io_nasti_ar_bits_len = T_8121_io_slave_ar_bits_len;
+ assign T_8122_io_nasti_ar_bits_size = T_8121_io_slave_ar_bits_size;
+ assign T_8122_io_nasti_ar_bits_burst = T_8121_io_slave_ar_bits_burst;
+ assign T_8122_io_nasti_ar_bits_lock = T_8121_io_slave_ar_bits_lock;
+ assign T_8122_io_nasti_ar_bits_cache = T_8121_io_slave_ar_bits_cache;
+ assign T_8122_io_nasti_ar_bits_prot = T_8121_io_slave_ar_bits_prot;
+ assign T_8122_io_nasti_ar_bits_qos = T_8121_io_slave_ar_bits_qos;
+ assign T_8122_io_nasti_ar_bits_region = T_8121_io_slave_ar_bits_region;
+ assign T_8122_io_nasti_ar_bits_id = T_8121_io_slave_ar_bits_id;
+ assign T_8122_io_nasti_ar_bits_user = T_8121_io_slave_ar_bits_user;
+ assign T_8122_io_nasti_r_ready = T_8121_io_slave_r_ready;
+ assign T_8122_io_mem_req_cmd_ready = T_8123_io_wide_req_cmd_ready;
+ assign T_8122_io_mem_req_data_ready = T_8123_io_wide_req_data_ready;
+ assign T_8122_io_mem_resp_valid = T_8123_io_wide_resp_valid;
+ assign T_8122_io_mem_resp_bits_data = T_8123_io_wide_resp_bits_data;
+ assign T_8122_io_mem_resp_bits_tag = T_8123_io_wide_resp_bits_tag;
+ assign T_8123_clk = clk;
+ assign T_8123_reset = reset;
+ assign T_8123_io_wide_req_cmd_valid = T_8122_io_mem_req_cmd_valid;
+ assign T_8123_io_wide_req_cmd_bits_addr = T_8122_io_mem_req_cmd_bits_addr;
+ assign T_8123_io_wide_req_cmd_bits_tag = T_8122_io_mem_req_cmd_bits_tag;
+ assign T_8123_io_wide_req_cmd_bits_rw = T_8122_io_mem_req_cmd_bits_rw;
+ assign T_8123_io_wide_req_data_valid = T_8122_io_mem_req_data_valid;
+ assign T_8123_io_wide_req_data_bits_data = T_8122_io_mem_req_data_bits_data;
+ assign T_8123_io_wide_resp_ready = T_8122_io_mem_resp_ready;
+ assign T_8123_io_narrow_req_ready = io_mem_backup_req_ready;
+ assign T_8123_io_narrow_resp_valid = io_mem_backup_resp_valid;
+ assign T_8123_io_narrow_resp_bits = io_mem_backup_resp_bits;
+ assign T_8124 = io_mem_backup_en ? T_8121_io_master_0_ar_ready : io_mem_0_ar_ready;
+ assign T_8126 = io_mem_backup_en == 1'h0;
+ assign T_8127 = interconnect$_io_slaves_0_ar_valid & T_8126;
+ assign T_8128 = interconnect$_io_slaves_0_ar_valid & io_mem_backup_en;
+ assign T_8129 = io_mem_backup_en ? T_8121_io_master_0_aw_ready : io_mem_0_aw_ready;
+ assign T_8131 = io_mem_backup_en == 1'h0;
+ assign T_8132 = interconnect$_io_slaves_0_aw_valid & T_8131;
+ assign T_8133 = interconnect$_io_slaves_0_aw_valid & io_mem_backup_en;
+ assign T_8134 = io_mem_backup_en ? T_8121_io_master_0_w_ready : io_mem_0_w_ready;
+ assign T_8136 = io_mem_backup_en == 1'h0;
+ assign T_8137 = interconnect$_io_slaves_0_w_valid & T_8136;
+ assign T_8138 = interconnect$_io_slaves_0_w_valid & io_mem_backup_en;
+ assign T_8139 = io_mem_backup_en ? T_8121_io_master_0_b_valid : io_mem_0_b_valid;
+ assign T_8140_resp = io_mem_backup_en ? T_8121_io_master_0_b_bits_resp : io_mem_0_b_bits_resp;
+ assign T_8140_id = io_mem_backup_en ? T_8121_io_master_0_b_bits_id : io_mem_0_b_bits_id;
+ assign T_8140_user = io_mem_backup_en ? T_8121_io_master_0_b_bits_user : io_mem_0_b_bits_user;
+ assign T_8145 = io_mem_backup_en == 1'h0;
+ assign T_8146 = interconnect$_io_slaves_0_b_ready & T_8145;
+ assign T_8147 = interconnect$_io_slaves_0_b_ready & io_mem_backup_en;
+ assign T_8148 = io_mem_backup_en ? T_8121_io_master_0_r_valid : io_mem_0_r_valid;
+ assign T_8149_resp = io_mem_backup_en ? T_8121_io_master_0_r_bits_resp : io_mem_0_r_bits_resp;
+ assign T_8149_data = io_mem_backup_en ? T_8121_io_master_0_r_bits_data : io_mem_0_r_bits_data;
+ assign T_8149_last = io_mem_backup_en ? T_8121_io_master_0_r_bits_last : io_mem_0_r_bits_last;
+ assign T_8149_id = io_mem_backup_en ? T_8121_io_master_0_r_bits_id : io_mem_0_r_bits_id;
+ assign T_8149_user = io_mem_backup_en ? T_8121_io_master_0_r_bits_user : io_mem_0_r_bits_user;
+ assign T_8156 = io_mem_backup_en == 1'h0;
+ assign T_8157 = interconnect$_io_slaves_0_r_ready & T_8156;
+ assign T_8158 = interconnect$_io_slaves_0_r_ready & io_mem_backup_en;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ GEN_0 = {1{$random}};
+ GEN_1 = {1{$random}};
+ GEN_2 = {1{$random}};
+ GEN_3 = {1{$random}};
+ end
+`endif
+endmodule
+module SCRFile(
+ input clk,
+ input reset,
+ output io_smi_req_ready,
+ input io_smi_req_valid,
+ input io_smi_req_bits_rw,
+ input [5:0] io_smi_req_bits_addr,
+ input [63:0] io_smi_req_bits_data,
+ input io_smi_resp_ready,
+ output io_smi_resp_valid,
+ output [63:0] io_smi_resp_bits,
+ input [63:0] io_scr_rdata_0,
+ input [63:0] io_scr_rdata_1,
+ input [63:0] io_scr_rdata_2,
+ input [63:0] io_scr_rdata_3,
+ input [63:0] io_scr_rdata_4,
+ input [63:0] io_scr_rdata_5,
+ input [63:0] io_scr_rdata_6,
+ input [63:0] io_scr_rdata_7,
+ input [63:0] io_scr_rdata_8,
+ input [63:0] io_scr_rdata_9,
+ input [63:0] io_scr_rdata_10,
+ input [63:0] io_scr_rdata_11,
+ input [63:0] io_scr_rdata_12,
+ input [63:0] io_scr_rdata_13,
+ input [63:0] io_scr_rdata_14,
+ input [63:0] io_scr_rdata_15,
+ input [63:0] io_scr_rdata_16,
+ input [63:0] io_scr_rdata_17,
+ input [63:0] io_scr_rdata_18,
+ input [63:0] io_scr_rdata_19,
+ input [63:0] io_scr_rdata_20,
+ input [63:0] io_scr_rdata_21,
+ input [63:0] io_scr_rdata_22,
+ input [63:0] io_scr_rdata_23,
+ input [63:0] io_scr_rdata_24,
+ input [63:0] io_scr_rdata_25,
+ input [63:0] io_scr_rdata_26,
+ input [63:0] io_scr_rdata_27,
+ input [63:0] io_scr_rdata_28,
+ input [63:0] io_scr_rdata_29,
+ input [63:0] io_scr_rdata_30,
+ input [63:0] io_scr_rdata_31,
+ input [63:0] io_scr_rdata_32,
+ input [63:0] io_scr_rdata_33,
+ input [63:0] io_scr_rdata_34,
+ input [63:0] io_scr_rdata_35,
+ input [63:0] io_scr_rdata_36,
+ input [63:0] io_scr_rdata_37,
+ input [63:0] io_scr_rdata_38,
+ input [63:0] io_scr_rdata_39,
+ input [63:0] io_scr_rdata_40,
+ input [63:0] io_scr_rdata_41,
+ input [63:0] io_scr_rdata_42,
+ input [63:0] io_scr_rdata_43,
+ input [63:0] io_scr_rdata_44,
+ input [63:0] io_scr_rdata_45,
+ input [63:0] io_scr_rdata_46,
+ input [63:0] io_scr_rdata_47,
+ input [63:0] io_scr_rdata_48,
+ input [63:0] io_scr_rdata_49,
+ input [63:0] io_scr_rdata_50,
+ input [63:0] io_scr_rdata_51,
+ input [63:0] io_scr_rdata_52,
+ input [63:0] io_scr_rdata_53,
+ input [63:0] io_scr_rdata_54,
+ input [63:0] io_scr_rdata_55,
+ input [63:0] io_scr_rdata_56,
+ input [63:0] io_scr_rdata_57,
+ input [63:0] io_scr_rdata_58,
+ input [63:0] io_scr_rdata_59,
+ input [63:0] io_scr_rdata_60,
+ input [63:0] io_scr_rdata_61,
+ input [63:0] io_scr_rdata_62,
+ input [63:0] io_scr_rdata_63,
+ output io_scr_wen,
+ output [5:0] io_scr_waddr,
+ output [63:0] io_scr_wdata
+);
+ wire [63:0] scr_rdata_0;
+ wire [63:0] scr_rdata_1;
+ wire [63:0] scr_rdata_2;
+ wire [63:0] scr_rdata_3;
+ wire [63:0] scr_rdata_4;
+ wire [63:0] scr_rdata_5;
+ wire [63:0] scr_rdata_6;
+ wire [63:0] scr_rdata_7;
+ wire [63:0] scr_rdata_8;
+ wire [63:0] scr_rdata_9;
+ wire [63:0] scr_rdata_10;
+ wire [63:0] scr_rdata_11;
+ wire [63:0] scr_rdata_12;
+ wire [63:0] scr_rdata_13;
+ wire [63:0] scr_rdata_14;
+ wire [63:0] scr_rdata_15;
+ wire [63:0] scr_rdata_16;
+ wire [63:0] scr_rdata_17;
+ wire [63:0] scr_rdata_18;
+ wire [63:0] scr_rdata_19;
+ wire [63:0] scr_rdata_20;
+ wire [63:0] scr_rdata_21;
+ wire [63:0] scr_rdata_22;
+ wire [63:0] scr_rdata_23;
+ wire [63:0] scr_rdata_24;
+ wire [63:0] scr_rdata_25;
+ wire [63:0] scr_rdata_26;
+ wire [63:0] scr_rdata_27;
+ wire [63:0] scr_rdata_28;
+ wire [63:0] scr_rdata_29;
+ wire [63:0] scr_rdata_30;
+ wire [63:0] scr_rdata_31;
+ wire [63:0] scr_rdata_32;
+ wire [63:0] scr_rdata_33;
+ wire [63:0] scr_rdata_34;
+ wire [63:0] scr_rdata_35;
+ wire [63:0] scr_rdata_36;
+ wire [63:0] scr_rdata_37;
+ wire [63:0] scr_rdata_38;
+ wire [63:0] scr_rdata_39;
+ wire [63:0] scr_rdata_40;
+ wire [63:0] scr_rdata_41;
+ wire [63:0] scr_rdata_42;
+ wire [63:0] scr_rdata_43;
+ wire [63:0] scr_rdata_44;
+ wire [63:0] scr_rdata_45;
+ wire [63:0] scr_rdata_46;
+ wire [63:0] scr_rdata_47;
+ wire [63:0] scr_rdata_48;
+ wire [63:0] scr_rdata_49;
+ wire [63:0] scr_rdata_50;
+ wire [63:0] scr_rdata_51;
+ wire [63:0] scr_rdata_52;
+ wire [63:0] scr_rdata_53;
+ wire [63:0] scr_rdata_54;
+ wire [63:0] scr_rdata_55;
+ wire [63:0] scr_rdata_56;
+ wire [63:0] scr_rdata_57;
+ wire [63:0] scr_rdata_58;
+ wire [63:0] scr_rdata_59;
+ wire [63:0] scr_rdata_60;
+ wire [63:0] scr_rdata_61;
+ wire [63:0] scr_rdata_62;
+ wire [63:0] scr_rdata_63;
+ reg [5:0] read_addr;
+ reg resp_valid;
+ wire T_365;
+ wire [63:0] GEN_0;
+ wire T_367;
+ wire T_368;
+ wire T_369;
+ wire T_371;
+ wire GEN_1;
+ wire GEN_2;
+ wire GEN_3;
+ wire GEN_4;
+ wire GEN_5;
+ wire GEN_6;
+ wire GEN_7;
+ wire GEN_8;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ wire GEN_17;
+ wire GEN_18;
+ wire GEN_19;
+ wire GEN_20;
+ wire GEN_21;
+ wire GEN_22;
+ wire GEN_23;
+ wire GEN_24;
+ wire GEN_25;
+ wire GEN_26;
+ wire GEN_27;
+ wire GEN_28;
+ wire GEN_29;
+ wire GEN_30;
+ wire GEN_31;
+ wire GEN_32;
+ wire GEN_33;
+ wire GEN_34;
+ wire GEN_35;
+ wire GEN_36;
+ wire GEN_37;
+ wire GEN_38;
+ wire GEN_39;
+ wire GEN_40;
+ wire GEN_41;
+ wire GEN_42;
+ wire GEN_43;
+ wire GEN_44;
+ wire GEN_45;
+ wire GEN_46;
+ wire GEN_47;
+ wire GEN_48;
+ wire GEN_49;
+ wire GEN_50;
+ wire GEN_51;
+ wire GEN_52;
+ wire GEN_53;
+ wire GEN_54;
+ wire GEN_55;
+ wire GEN_56;
+ wire GEN_57;
+ wire GEN_58;
+ wire GEN_59;
+ wire GEN_60;
+ wire GEN_61;
+ wire GEN_62;
+ wire GEN_63;
+ assign io_smi_req_ready = T_365;
+ assign io_smi_resp_valid = resp_valid;
+ assign io_smi_resp_bits = GEN_0;
+ assign io_scr_wen = T_368;
+ assign io_scr_waddr = io_smi_req_bits_addr;
+ assign io_scr_wdata = io_smi_req_bits_data;
+ assign scr_rdata_0 = 1'h1;
+ assign scr_rdata_1 = 11'h400;
+ assign scr_rdata_2 = io_scr_rdata_2;
+ assign scr_rdata_3 = io_scr_rdata_3;
+ assign scr_rdata_4 = io_scr_rdata_4;
+ assign scr_rdata_5 = io_scr_rdata_5;
+ assign scr_rdata_6 = io_scr_rdata_6;
+ assign scr_rdata_7 = io_scr_rdata_7;
+ assign scr_rdata_8 = io_scr_rdata_8;
+ assign scr_rdata_9 = io_scr_rdata_9;
+ assign scr_rdata_10 = io_scr_rdata_10;
+ assign scr_rdata_11 = io_scr_rdata_11;
+ assign scr_rdata_12 = io_scr_rdata_12;
+ assign scr_rdata_13 = io_scr_rdata_13;
+ assign scr_rdata_14 = io_scr_rdata_14;
+ assign scr_rdata_15 = io_scr_rdata_15;
+ assign scr_rdata_16 = io_scr_rdata_16;
+ assign scr_rdata_17 = io_scr_rdata_17;
+ assign scr_rdata_18 = io_scr_rdata_18;
+ assign scr_rdata_19 = io_scr_rdata_19;
+ assign scr_rdata_20 = io_scr_rdata_20;
+ assign scr_rdata_21 = io_scr_rdata_21;
+ assign scr_rdata_22 = io_scr_rdata_22;
+ assign scr_rdata_23 = io_scr_rdata_23;
+ assign scr_rdata_24 = io_scr_rdata_24;
+ assign scr_rdata_25 = io_scr_rdata_25;
+ assign scr_rdata_26 = io_scr_rdata_26;
+ assign scr_rdata_27 = io_scr_rdata_27;
+ assign scr_rdata_28 = io_scr_rdata_28;
+ assign scr_rdata_29 = io_scr_rdata_29;
+ assign scr_rdata_30 = io_scr_rdata_30;
+ assign scr_rdata_31 = io_scr_rdata_31;
+ assign scr_rdata_32 = io_scr_rdata_32;
+ assign scr_rdata_33 = io_scr_rdata_33;
+ assign scr_rdata_34 = io_scr_rdata_34;
+ assign scr_rdata_35 = io_scr_rdata_35;
+ assign scr_rdata_36 = io_scr_rdata_36;
+ assign scr_rdata_37 = io_scr_rdata_37;
+ assign scr_rdata_38 = io_scr_rdata_38;
+ assign scr_rdata_39 = io_scr_rdata_39;
+ assign scr_rdata_40 = io_scr_rdata_40;
+ assign scr_rdata_41 = io_scr_rdata_41;
+ assign scr_rdata_42 = io_scr_rdata_42;
+ assign scr_rdata_43 = io_scr_rdata_43;
+ assign scr_rdata_44 = io_scr_rdata_44;
+ assign scr_rdata_45 = io_scr_rdata_45;
+ assign scr_rdata_46 = io_scr_rdata_46;
+ assign scr_rdata_47 = io_scr_rdata_47;
+ assign scr_rdata_48 = io_scr_rdata_48;
+ assign scr_rdata_49 = io_scr_rdata_49;
+ assign scr_rdata_50 = io_scr_rdata_50;
+ assign scr_rdata_51 = io_scr_rdata_51;
+ assign scr_rdata_52 = io_scr_rdata_52;
+ assign scr_rdata_53 = io_scr_rdata_53;
+ assign scr_rdata_54 = io_scr_rdata_54;
+ assign scr_rdata_55 = io_scr_rdata_55;
+ assign scr_rdata_56 = io_scr_rdata_56;
+ assign scr_rdata_57 = io_scr_rdata_57;
+ assign scr_rdata_58 = io_scr_rdata_58;
+ assign scr_rdata_59 = io_scr_rdata_59;
+ assign scr_rdata_60 = io_scr_rdata_60;
+ assign scr_rdata_61 = io_scr_rdata_61;
+ assign scr_rdata_62 = io_scr_rdata_62;
+ assign scr_rdata_63 = io_scr_rdata_63;
+ assign T_365 = resp_valid == 1'h0;
+ assign GEN_0 = GEN_1 ? scr_rdata_63 : GEN_2 ? scr_rdata_62 : GEN_3 ? scr_rdata_61 : GEN_4 ? scr_rdata_60 : GEN_5 ? scr_rdata_59 : GEN_6 ? scr_rdata_58 : GEN_7 ? scr_rdata_57 : GEN_8 ? scr_rdata_56 : GEN_9 ? scr_rdata_55 : GEN_10 ? scr_rdata_54 : GEN_11 ? scr_rdata_53 : GEN_12 ? scr_rdata_52 : GEN_13 ? scr_rdata_51 : GEN_14 ? scr_rdata_50 : GEN_15 ? scr_rdata_49 : GEN_16 ? scr_rdata_48 : GEN_17 ? scr_rdata_47 : GEN_18 ? scr_rdata_46 : GEN_19 ? scr_rdata_45 : GEN_20 ? scr_rdata_44 : GEN_21 ? scr_rdata_43 : GEN_22 ? scr_rdata_42 : GEN_23 ? scr_rdata_41 : GEN_24 ? scr_rdata_40 : GEN_25 ? scr_rdata_39 : GEN_26 ? scr_rdata_38 : GEN_27 ? scr_rdata_37 : GEN_28 ? scr_rdata_36 : GEN_29 ? scr_rdata_35 : GEN_30 ? scr_rdata_34 : GEN_31 ? scr_rdata_33 : GEN_32 ? scr_rdata_32 : GEN_33 ? scr_rdata_31 : GEN_34 ? scr_rdata_30 : GEN_35 ? scr_rdata_29 : GEN_36 ? scr_rdata_28 : GEN_37 ? scr_rdata_27 : GEN_38 ? scr_rdata_26 : GEN_39 ? scr_rdata_25 : GEN_40 ? scr_rdata_24 : GEN_41 ? scr_rdata_23 : GEN_42 ? scr_rdata_22 : GEN_43 ? scr_rdata_21 : GEN_44 ? scr_rdata_20 : GEN_45 ? scr_rdata_19 : GEN_46 ? scr_rdata_18 : GEN_47 ? scr_rdata_17 : GEN_48 ? scr_rdata_16 : GEN_49 ? scr_rdata_15 : GEN_50 ? scr_rdata_14 : GEN_51 ? scr_rdata_13 : GEN_52 ? scr_rdata_12 : GEN_53 ? scr_rdata_11 : GEN_54 ? scr_rdata_10 : GEN_55 ? scr_rdata_9 : GEN_56 ? scr_rdata_8 : GEN_57 ? scr_rdata_7 : GEN_58 ? scr_rdata_6 : GEN_59 ? scr_rdata_5 : GEN_60 ? scr_rdata_4 : GEN_61 ? scr_rdata_3 : GEN_62 ? scr_rdata_2 : GEN_63 ? scr_rdata_1 : scr_rdata_0;
+ assign T_367 = io_smi_req_ready & io_smi_req_valid;
+ assign T_368 = T_367 & io_smi_req_bits_rw;
+ assign T_369 = io_smi_req_ready & io_smi_req_valid;
+ assign T_371 = io_smi_resp_ready & io_smi_resp_valid;
+ assign GEN_1 = 6'h3f == read_addr;
+ assign GEN_2 = 6'h3e == read_addr;
+ assign GEN_3 = 6'h3d == read_addr;
+ assign GEN_4 = 6'h3c == read_addr;
+ assign GEN_5 = 6'h3b == read_addr;
+ assign GEN_6 = 6'h3a == read_addr;
+ assign GEN_7 = 6'h39 == read_addr;
+ assign GEN_8 = 6'h38 == read_addr;
+ assign GEN_9 = 6'h37 == read_addr;
+ assign GEN_10 = 6'h36 == read_addr;
+ assign GEN_11 = 6'h35 == read_addr;
+ assign GEN_12 = 6'h34 == read_addr;
+ assign GEN_13 = 6'h33 == read_addr;
+ assign GEN_14 = 6'h32 == read_addr;
+ assign GEN_15 = 6'h31 == read_addr;
+ assign GEN_16 = 6'h30 == read_addr;
+ assign GEN_17 = 6'h2f == read_addr;
+ assign GEN_18 = 6'h2e == read_addr;
+ assign GEN_19 = 6'h2d == read_addr;
+ assign GEN_20 = 6'h2c == read_addr;
+ assign GEN_21 = 6'h2b == read_addr;
+ assign GEN_22 = 6'h2a == read_addr;
+ assign GEN_23 = 6'h29 == read_addr;
+ assign GEN_24 = 6'h28 == read_addr;
+ assign GEN_25 = 6'h27 == read_addr;
+ assign GEN_26 = 6'h26 == read_addr;
+ assign GEN_27 = 6'h25 == read_addr;
+ assign GEN_28 = 6'h24 == read_addr;
+ assign GEN_29 = 6'h23 == read_addr;
+ assign GEN_30 = 6'h22 == read_addr;
+ assign GEN_31 = 6'h21 == read_addr;
+ assign GEN_32 = 6'h20 == read_addr;
+ assign GEN_33 = 5'h1f == read_addr;
+ assign GEN_34 = 5'h1e == read_addr;
+ assign GEN_35 = 5'h1d == read_addr;
+ assign GEN_36 = 5'h1c == read_addr;
+ assign GEN_37 = 5'h1b == read_addr;
+ assign GEN_38 = 5'h1a == read_addr;
+ assign GEN_39 = 5'h19 == read_addr;
+ assign GEN_40 = 5'h18 == read_addr;
+ assign GEN_41 = 5'h17 == read_addr;
+ assign GEN_42 = 5'h16 == read_addr;
+ assign GEN_43 = 5'h15 == read_addr;
+ assign GEN_44 = 5'h14 == read_addr;
+ assign GEN_45 = 5'h13 == read_addr;
+ assign GEN_46 = 5'h12 == read_addr;
+ assign GEN_47 = 5'h11 == read_addr;
+ assign GEN_48 = 5'h10 == read_addr;
+ assign GEN_49 = 4'hf == read_addr;
+ assign GEN_50 = 4'he == read_addr;
+ assign GEN_51 = 4'hd == read_addr;
+ assign GEN_52 = 4'hc == read_addr;
+ assign GEN_53 = 4'hb == read_addr;
+ assign GEN_54 = 4'ha == read_addr;
+ assign GEN_55 = 4'h9 == read_addr;
+ assign GEN_56 = 4'h8 == read_addr;
+ assign GEN_57 = 3'h7 == read_addr;
+ assign GEN_58 = 3'h6 == read_addr;
+ assign GEN_59 = 3'h5 == read_addr;
+ assign GEN_60 = 3'h4 == read_addr;
+ assign GEN_61 = 2'h3 == read_addr;
+ assign GEN_62 = 2'h2 == read_addr;
+ assign GEN_63 = 1'h1 == read_addr;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ read_addr = {1{$random}};
+ resp_valid = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ read_addr <= 6'h0;
+ end else begin
+ if(T_369) begin
+ read_addr <= io_smi_req_bits_addr;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ resp_valid <= 1'h0;
+ end else begin
+ if(T_371) begin
+ resp_valid <= 1'h0;
+ end else begin
+ if(T_369) begin
+ resp_valid <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+endmodule
+module Queue_89(
+ input clk,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [31:0] io_enq_bits_addr,
+ input [7:0] io_enq_bits_len,
+ input [2:0] io_enq_bits_size,
+ input [1:0] io_enq_bits_burst,
+ input io_enq_bits_lock,
+ input [3:0] io_enq_bits_cache,
+ input [2:0] io_enq_bits_prot,
+ input [3:0] io_enq_bits_qos,
+ input [3:0] io_enq_bits_region,
+ input [4:0] io_enq_bits_id,
+ input io_enq_bits_user,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [31:0] io_deq_bits_addr,
+ output [7:0] io_deq_bits_len,
+ output [2:0] io_deq_bits_size,
+ output [1:0] io_deq_bits_burst,
+ output io_deq_bits_lock,
+ output [3:0] io_deq_bits_cache,
+ output [2:0] io_deq_bits_prot,
+ output [3:0] io_deq_bits_qos,
+ output [3:0] io_deq_bits_region,
+ output [4:0] io_deq_bits_id,
+ output io_deq_bits_user,
+ output io_count
+);
+ reg [31:0] ram_addr [0:0];
+ wire [31:0] ram_addr_T_169_data;
+ wire ram_addr_T_169_addr;
+ wire ram_addr_T_169_en;
+ wire ram_addr_T_169_clk;
+ wire [31:0] ram_addr_T_144_data;
+ wire ram_addr_T_144_addr;
+ wire ram_addr_T_144_mask;
+ wire ram_addr_T_144_en;
+ wire ram_addr_T_144_clk;
+ reg [7:0] ram_len [0:0];
+ wire [7:0] ram_len_T_169_data;
+ wire ram_len_T_169_addr;
+ wire ram_len_T_169_en;
+ wire ram_len_T_169_clk;
+ wire [7:0] ram_len_T_144_data;
+ wire ram_len_T_144_addr;
+ wire ram_len_T_144_mask;
+ wire ram_len_T_144_en;
+ wire ram_len_T_144_clk;
+ reg [2:0] ram_size [0:0];
+ wire [2:0] ram_size_T_169_data;
+ wire ram_size_T_169_addr;
+ wire ram_size_T_169_en;
+ wire ram_size_T_169_clk;
+ wire [2:0] ram_size_T_144_data;
+ wire ram_size_T_144_addr;
+ wire ram_size_T_144_mask;
+ wire ram_size_T_144_en;
+ wire ram_size_T_144_clk;
+ reg [1:0] ram_burst [0:0];
+ wire [1:0] ram_burst_T_169_data;
+ wire ram_burst_T_169_addr;
+ wire ram_burst_T_169_en;
+ wire ram_burst_T_169_clk;
+ wire [1:0] ram_burst_T_144_data;
+ wire ram_burst_T_144_addr;
+ wire ram_burst_T_144_mask;
+ wire ram_burst_T_144_en;
+ wire ram_burst_T_144_clk;
+ reg ram_lock [0:0];
+ wire ram_lock_T_169_data;
+ wire ram_lock_T_169_addr;
+ wire ram_lock_T_169_en;
+ wire ram_lock_T_169_clk;
+ wire ram_lock_T_144_data;
+ wire ram_lock_T_144_addr;
+ wire ram_lock_T_144_mask;
+ wire ram_lock_T_144_en;
+ wire ram_lock_T_144_clk;
+ reg [3:0] ram_cache [0:0];
+ wire [3:0] ram_cache_T_169_data;
+ wire ram_cache_T_169_addr;
+ wire ram_cache_T_169_en;
+ wire ram_cache_T_169_clk;
+ wire [3:0] ram_cache_T_144_data;
+ wire ram_cache_T_144_addr;
+ wire ram_cache_T_144_mask;
+ wire ram_cache_T_144_en;
+ wire ram_cache_T_144_clk;
+ reg [2:0] ram_prot [0:0];
+ wire [2:0] ram_prot_T_169_data;
+ wire ram_prot_T_169_addr;
+ wire ram_prot_T_169_en;
+ wire ram_prot_T_169_clk;
+ wire [2:0] ram_prot_T_144_data;
+ wire ram_prot_T_144_addr;
+ wire ram_prot_T_144_mask;
+ wire ram_prot_T_144_en;
+ wire ram_prot_T_144_clk;
+ reg [3:0] ram_qos [0:0];
+ wire [3:0] ram_qos_T_169_data;
+ wire ram_qos_T_169_addr;
+ wire ram_qos_T_169_en;
+ wire ram_qos_T_169_clk;
+ wire [3:0] ram_qos_T_144_data;
+ wire ram_qos_T_144_addr;
+ wire ram_qos_T_144_mask;
+ wire ram_qos_T_144_en;
+ wire ram_qos_T_144_clk;
+ reg [3:0] ram_region [0:0];
+ wire [3:0] ram_region_T_169_data;
+ wire ram_region_T_169_addr;
+ wire ram_region_T_169_en;
+ wire ram_region_T_169_clk;
+ wire [3:0] ram_region_T_144_data;
+ wire ram_region_T_144_addr;
+ wire ram_region_T_144_mask;
+ wire ram_region_T_144_en;
+ wire ram_region_T_144_clk;
+ reg [4:0] ram_id [0:0];
+ wire [4:0] ram_id_T_169_data;
+ wire ram_id_T_169_addr;
+ wire ram_id_T_169_en;
+ wire ram_id_T_169_clk;
+ wire [4:0] ram_id_T_144_data;
+ wire ram_id_T_144_addr;
+ wire ram_id_T_144_mask;
+ wire ram_id_T_144_en;
+ wire ram_id_T_144_clk;
+ reg ram_user [0:0];
+ wire ram_user_T_169_data;
+ wire ram_user_T_169_addr;
+ wire ram_user_T_169_en;
+ wire ram_user_T_169_clk;
+ wire ram_user_T_144_data;
+ wire ram_user_T_144_addr;
+ wire ram_user_T_144_mask;
+ wire ram_user_T_144_en;
+ wire ram_user_T_144_clk;
+ reg maybe_full;
+ wire ptr_match;
+ wire T_130;
+ wire empty;
+ wire full;
+ wire maybe_flow;
+ wire do_flow;
+ wire T_136;
+ wire T_138;
+ wire do_enq;
+ wire T_140;
+ wire T_142;
+ wire do_deq;
+ wire T_158;
+ wire T_160;
+ wire T_162;
+ wire T_163;
+ wire T_165;
+ wire T_167;
+ wire T_168;
+ wire [31:0] T_181_addr;
+ wire [7:0] T_181_len;
+ wire [2:0] T_181_size;
+ wire [1:0] T_181_burst;
+ wire T_181_lock;
+ wire [3:0] T_181_cache;
+ wire [2:0] T_181_prot;
+ wire [3:0] T_181_qos;
+ wire [3:0] T_181_region;
+ wire [4:0] T_181_id;
+ wire T_181_user;
+ wire [1:0] T_193;
+ wire ptr_diff;
+ wire T_195;
+ wire [1:0] T_196;
+ assign io_enq_ready = T_168;
+ assign io_deq_valid = T_163;
+ assign io_deq_bits_addr = T_181_addr;
+ assign io_deq_bits_len = T_181_len;
+ assign io_deq_bits_size = T_181_size;
+ assign io_deq_bits_burst = T_181_burst;
+ assign io_deq_bits_lock = T_181_lock;
+ assign io_deq_bits_cache = T_181_cache;
+ assign io_deq_bits_prot = T_181_prot;
+ assign io_deq_bits_qos = T_181_qos;
+ assign io_deq_bits_region = T_181_region;
+ assign io_deq_bits_id = T_181_id;
+ assign io_deq_bits_user = T_181_user;
+ assign io_count = T_196;
+ assign ram_addr_T_169_addr = 1'h0;
+ assign ram_addr_T_169_en = 1'h1;
+ assign ram_addr_T_169_clk = clk;
+ assign ram_addr_T_169_data = ram_addr[ram_addr_T_169_addr];
+ assign ram_addr_T_144_data = io_enq_bits_addr;
+ assign ram_addr_T_144_addr = 1'h0;
+ assign ram_addr_T_144_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_addr_T_144_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_addr_T_144_clk = clk;
+ assign ram_len_T_169_addr = 1'h0;
+ assign ram_len_T_169_en = 1'h1;
+ assign ram_len_T_169_clk = clk;
+ assign ram_len_T_169_data = ram_len[ram_len_T_169_addr];
+ assign ram_len_T_144_data = io_enq_bits_len;
+ assign ram_len_T_144_addr = 1'h0;
+ assign ram_len_T_144_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_len_T_144_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_len_T_144_clk = clk;
+ assign ram_size_T_169_addr = 1'h0;
+ assign ram_size_T_169_en = 1'h1;
+ assign ram_size_T_169_clk = clk;
+ assign ram_size_T_169_data = ram_size[ram_size_T_169_addr];
+ assign ram_size_T_144_data = io_enq_bits_size;
+ assign ram_size_T_144_addr = 1'h0;
+ assign ram_size_T_144_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_size_T_144_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_size_T_144_clk = clk;
+ assign ram_burst_T_169_addr = 1'h0;
+ assign ram_burst_T_169_en = 1'h1;
+ assign ram_burst_T_169_clk = clk;
+ assign ram_burst_T_169_data = ram_burst[ram_burst_T_169_addr];
+ assign ram_burst_T_144_data = io_enq_bits_burst;
+ assign ram_burst_T_144_addr = 1'h0;
+ assign ram_burst_T_144_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_burst_T_144_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_burst_T_144_clk = clk;
+ assign ram_lock_T_169_addr = 1'h0;
+ assign ram_lock_T_169_en = 1'h1;
+ assign ram_lock_T_169_clk = clk;
+ assign ram_lock_T_169_data = ram_lock[ram_lock_T_169_addr];
+ assign ram_lock_T_144_data = io_enq_bits_lock;
+ assign ram_lock_T_144_addr = 1'h0;
+ assign ram_lock_T_144_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_lock_T_144_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_lock_T_144_clk = clk;
+ assign ram_cache_T_169_addr = 1'h0;
+ assign ram_cache_T_169_en = 1'h1;
+ assign ram_cache_T_169_clk = clk;
+ assign ram_cache_T_169_data = ram_cache[ram_cache_T_169_addr];
+ assign ram_cache_T_144_data = io_enq_bits_cache;
+ assign ram_cache_T_144_addr = 1'h0;
+ assign ram_cache_T_144_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_cache_T_144_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_cache_T_144_clk = clk;
+ assign ram_prot_T_169_addr = 1'h0;
+ assign ram_prot_T_169_en = 1'h1;
+ assign ram_prot_T_169_clk = clk;
+ assign ram_prot_T_169_data = ram_prot[ram_prot_T_169_addr];
+ assign ram_prot_T_144_data = io_enq_bits_prot;
+ assign ram_prot_T_144_addr = 1'h0;
+ assign ram_prot_T_144_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_prot_T_144_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_prot_T_144_clk = clk;
+ assign ram_qos_T_169_addr = 1'h0;
+ assign ram_qos_T_169_en = 1'h1;
+ assign ram_qos_T_169_clk = clk;
+ assign ram_qos_T_169_data = ram_qos[ram_qos_T_169_addr];
+ assign ram_qos_T_144_data = io_enq_bits_qos;
+ assign ram_qos_T_144_addr = 1'h0;
+ assign ram_qos_T_144_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_qos_T_144_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_qos_T_144_clk = clk;
+ assign ram_region_T_169_addr = 1'h0;
+ assign ram_region_T_169_en = 1'h1;
+ assign ram_region_T_169_clk = clk;
+ assign ram_region_T_169_data = ram_region[ram_region_T_169_addr];
+ assign ram_region_T_144_data = io_enq_bits_region;
+ assign ram_region_T_144_addr = 1'h0;
+ assign ram_region_T_144_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_region_T_144_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_region_T_144_clk = clk;
+ assign ram_id_T_169_addr = 1'h0;
+ assign ram_id_T_169_en = 1'h1;
+ assign ram_id_T_169_clk = clk;
+ assign ram_id_T_169_data = ram_id[ram_id_T_169_addr];
+ assign ram_id_T_144_data = io_enq_bits_id;
+ assign ram_id_T_144_addr = 1'h0;
+ assign ram_id_T_144_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_id_T_144_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_id_T_144_clk = clk;
+ assign ram_user_T_169_addr = 1'h0;
+ assign ram_user_T_169_en = 1'h1;
+ assign ram_user_T_169_clk = clk;
+ assign ram_user_T_169_data = ram_user[ram_user_T_169_addr];
+ assign ram_user_T_144_data = io_enq_bits_user;
+ assign ram_user_T_144_addr = 1'h0;
+ assign ram_user_T_144_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_user_T_144_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_user_T_144_clk = clk;
+ assign ptr_match = 1'h0 == 1'h0;
+ assign T_130 = maybe_full == 1'h0;
+ assign empty = ptr_match & T_130;
+ assign full = ptr_match & maybe_full;
+ assign maybe_flow = 1'h0 & empty;
+ assign do_flow = maybe_flow & io_deq_ready;
+ assign T_136 = io_enq_ready & io_enq_valid;
+ assign T_138 = do_flow == 1'h0;
+ assign do_enq = T_136 & T_138;
+ assign T_140 = io_deq_ready & io_deq_valid;
+ assign T_142 = do_flow == 1'h0;
+ assign do_deq = T_140 & T_142;
+ assign T_158 = do_enq != do_deq;
+ assign T_160 = empty == 1'h0;
+ assign T_162 = 1'h0 & io_enq_valid;
+ assign T_163 = T_160 | T_162;
+ assign T_165 = full == 1'h0;
+ assign T_167 = 1'h0 & io_deq_ready;
+ assign T_168 = T_165 | T_167;
+ assign T_181_addr = maybe_flow ? io_enq_bits_addr : ram_addr_T_169_data;
+ assign T_181_len = maybe_flow ? io_enq_bits_len : ram_len_T_169_data;
+ assign T_181_size = maybe_flow ? io_enq_bits_size : ram_size_T_169_data;
+ assign T_181_burst = maybe_flow ? io_enq_bits_burst : ram_burst_T_169_data;
+ assign T_181_lock = maybe_flow ? io_enq_bits_lock : ram_lock_T_169_data;
+ assign T_181_cache = maybe_flow ? io_enq_bits_cache : ram_cache_T_169_data;
+ assign T_181_prot = maybe_flow ? io_enq_bits_prot : ram_prot_T_169_data;
+ assign T_181_qos = maybe_flow ? io_enq_bits_qos : ram_qos_T_169_data;
+ assign T_181_region = maybe_flow ? io_enq_bits_region : ram_region_T_169_data;
+ assign T_181_id = maybe_flow ? io_enq_bits_id : ram_id_T_169_data;
+ assign T_181_user = maybe_flow ? io_enq_bits_user : ram_user_T_169_data;
+ assign T_193 = 1'h0 - 1'h0;
+ assign ptr_diff = T_193[0:0];
+ assign T_195 = maybe_full & ptr_match;
+ assign T_196 = {T_195,ptr_diff};
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_addr[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_len[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_size[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_burst[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_lock[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_cache[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_prot[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_qos[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_region[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_id[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_user[initvar] = {1{$random}};
+ maybe_full = {1{$random}};
+ end
+`endif
+ always @(posedge ram_addr_T_144_clk) begin
+ if(ram_addr_T_144_en & ram_addr_T_144_mask) begin
+ ram_addr[ram_addr_T_144_addr] <= ram_addr_T_144_data;
+ end
+ end
+ always @(posedge ram_len_T_144_clk) begin
+ if(ram_len_T_144_en & ram_len_T_144_mask) begin
+ ram_len[ram_len_T_144_addr] <= ram_len_T_144_data;
+ end
+ end
+ always @(posedge ram_size_T_144_clk) begin
+ if(ram_size_T_144_en & ram_size_T_144_mask) begin
+ ram_size[ram_size_T_144_addr] <= ram_size_T_144_data;
+ end
+ end
+ always @(posedge ram_burst_T_144_clk) begin
+ if(ram_burst_T_144_en & ram_burst_T_144_mask) begin
+ ram_burst[ram_burst_T_144_addr] <= ram_burst_T_144_data;
+ end
+ end
+ always @(posedge ram_lock_T_144_clk) begin
+ if(ram_lock_T_144_en & ram_lock_T_144_mask) begin
+ ram_lock[ram_lock_T_144_addr] <= ram_lock_T_144_data;
+ end
+ end
+ always @(posedge ram_cache_T_144_clk) begin
+ if(ram_cache_T_144_en & ram_cache_T_144_mask) begin
+ ram_cache[ram_cache_T_144_addr] <= ram_cache_T_144_data;
+ end
+ end
+ always @(posedge ram_prot_T_144_clk) begin
+ if(ram_prot_T_144_en & ram_prot_T_144_mask) begin
+ ram_prot[ram_prot_T_144_addr] <= ram_prot_T_144_data;
+ end
+ end
+ always @(posedge ram_qos_T_144_clk) begin
+ if(ram_qos_T_144_en & ram_qos_T_144_mask) begin
+ ram_qos[ram_qos_T_144_addr] <= ram_qos_T_144_data;
+ end
+ end
+ always @(posedge ram_region_T_144_clk) begin
+ if(ram_region_T_144_en & ram_region_T_144_mask) begin
+ ram_region[ram_region_T_144_addr] <= ram_region_T_144_data;
+ end
+ end
+ always @(posedge ram_id_T_144_clk) begin
+ if(ram_id_T_144_en & ram_id_T_144_mask) begin
+ ram_id[ram_id_T_144_addr] <= ram_id_T_144_data;
+ end
+ end
+ always @(posedge ram_user_T_144_clk) begin
+ if(ram_user_T_144_en & ram_user_T_144_mask) begin
+ ram_user[ram_user_T_144_addr] <= ram_user_T_144_data;
+ end
+ end
+ always @(posedge clk) begin
+ if(reset) begin
+ maybe_full <= 1'h0;
+ end else begin
+ if(T_158) begin
+ maybe_full <= do_enq;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module NastiROM(
+ input clk,
+ input reset,
+ output io_aw_ready,
+ input io_aw_valid,
+ input [31:0] io_aw_bits_addr,
+ input [7:0] io_aw_bits_len,
+ input [2:0] io_aw_bits_size,
+ input [1:0] io_aw_bits_burst,
+ input io_aw_bits_lock,
+ input [3:0] io_aw_bits_cache,
+ input [2:0] io_aw_bits_prot,
+ input [3:0] io_aw_bits_qos,
+ input [3:0] io_aw_bits_region,
+ input [4:0] io_aw_bits_id,
+ input io_aw_bits_user,
+ output io_w_ready,
+ input io_w_valid,
+ input [63:0] io_w_bits_data,
+ input io_w_bits_last,
+ input [7:0] io_w_bits_strb,
+ input io_w_bits_user,
+ input io_b_ready,
+ output io_b_valid,
+ output [1:0] io_b_bits_resp,
+ output [4:0] io_b_bits_id,
+ output io_b_bits_user,
+ output io_ar_ready,
+ input io_ar_valid,
+ input [31:0] io_ar_bits_addr,
+ input [7:0] io_ar_bits_len,
+ input [2:0] io_ar_bits_size,
+ input [1:0] io_ar_bits_burst,
+ input io_ar_bits_lock,
+ input [3:0] io_ar_bits_cache,
+ input [2:0] io_ar_bits_prot,
+ input [3:0] io_ar_bits_qos,
+ input [3:0] io_ar_bits_region,
+ input [4:0] io_ar_bits_id,
+ input io_ar_bits_user,
+ input io_r_ready,
+ output io_r_valid,
+ output [1:0] io_r_bits_resp,
+ output [63:0] io_r_bits_data,
+ output io_r_bits_last,
+ output [4:0] io_r_bits_id,
+ output io_r_bits_user
+);
+ wire T_334_clk;
+ wire T_334_reset;
+ wire T_334_io_enq_ready;
+ wire T_334_io_enq_valid;
+ wire [31:0] T_334_io_enq_bits_addr;
+ wire [7:0] T_334_io_enq_bits_len;
+ wire [2:0] T_334_io_enq_bits_size;
+ wire [1:0] T_334_io_enq_bits_burst;
+ wire T_334_io_enq_bits_lock;
+ wire [3:0] T_334_io_enq_bits_cache;
+ wire [2:0] T_334_io_enq_bits_prot;
+ wire [3:0] T_334_io_enq_bits_qos;
+ wire [3:0] T_334_io_enq_bits_region;
+ wire [4:0] T_334_io_enq_bits_id;
+ wire T_334_io_enq_bits_user;
+ wire T_334_io_deq_ready;
+ wire T_334_io_deq_valid;
+ wire [31:0] T_334_io_deq_bits_addr;
+ wire [7:0] T_334_io_deq_bits_len;
+ wire [2:0] T_334_io_deq_bits_size;
+ wire [1:0] T_334_io_deq_bits_burst;
+ wire T_334_io_deq_bits_lock;
+ wire [3:0] T_334_io_deq_bits_cache;
+ wire [2:0] T_334_io_deq_bits_prot;
+ wire [3:0] T_334_io_deq_bits_qos;
+ wire [3:0] T_334_io_deq_bits_region;
+ wire [4:0] T_334_io_deq_bits_id;
+ wire T_334_io_deq_bits_user;
+ wire T_334_io_count;
+ wire T_336;
+ wire T_338;
+ wire T_340;
+ wire T_342;
+ wire T_343;
+ wire T_345;
+ wire T_347;
+ wire T_349;
+ wire T_351;
+ wire [63:0] rom_0;
+ wire [63:0] rom_1;
+ wire [63:0] rom_2;
+ wire [63:0] rom_3;
+ wire [63:0] rom_4;
+ wire [63:0] rom_5;
+ wire [63:0] rom_6;
+ wire [63:0] rom_7;
+ wire [63:0] rom_8;
+ wire [63:0] rom_9;
+ wire [63:0] rom_10;
+ wire [63:0] rom_11;
+ wire [63:0] rom_12;
+ wire [63:0] rom_13;
+ wire [63:0] rom_14;
+ wire [63:0] rom_15;
+ wire [63:0] rom_16;
+ wire [63:0] rom_17;
+ wire [63:0] rom_18;
+ wire [63:0] rom_19;
+ wire [63:0] rom_20;
+ wire [63:0] rom_21;
+ wire [63:0] rom_22;
+ wire [63:0] rom_23;
+ wire [63:0] rom_24;
+ wire [63:0] rom_25;
+ wire [63:0] rom_26;
+ wire [63:0] rom_27;
+ wire [63:0] rom_28;
+ wire [63:0] rom_29;
+ wire [63:0] rom_30;
+ wire [63:0] rom_31;
+ wire [63:0] rom_32;
+ wire [63:0] rom_33;
+ wire [63:0] rom_34;
+ wire [63:0] rom_35;
+ wire [63:0] rom_36;
+ wire [63:0] rom_37;
+ wire [63:0] rom_38;
+ wire [63:0] rom_39;
+ wire [63:0] rom_40;
+ wire [63:0] rom_41;
+ wire [63:0] rom_42;
+ wire [63:0] rom_43;
+ wire [63:0] rom_44;
+ wire [63:0] rom_45;
+ wire [63:0] rom_46;
+ wire [63:0] rom_47;
+ wire [63:0] rom_48;
+ wire [63:0] rom_49;
+ wire [63:0] rom_50;
+ wire [63:0] rom_51;
+ wire [63:0] rom_52;
+ wire [63:0] rom_53;
+ wire [63:0] rom_54;
+ wire [63:0] rom_55;
+ wire [63:0] rom_56;
+ wire [63:0] rom_57;
+ wire [63:0] rom_58;
+ wire [63:0] rom_59;
+ wire [63:0] rom_60;
+ wire [63:0] rom_61;
+ wire [63:0] rom_62;
+ wire [63:0] rom_63;
+ wire [63:0] rom_64;
+ wire [63:0] rom_65;
+ wire [63:0] rom_66;
+ wire [6:0] T_492;
+ wire [3:0] T_495;
+ wire [1:0] T_497;
+ wire [3:0] T_498;
+ wire GEN_3;
+ wire T_500;
+ wire T_501;
+ wire [63:0] GEN_0;
+ wire [31:0] T_502;
+ wire [63:0] GEN_1;
+ wire [31:0] T_503;
+ wire [31:0] T_504;
+ wire T_506;
+ wire [31:0] T_508;
+ wire T_510;
+ wire T_511;
+ wire T_512;
+ wire T_513;
+ wire [32:0] T_515;
+ wire [31:0] T_516;
+ wire [63:0] GEN_2;
+ wire [31:0] T_517;
+ wire [31:0] T_518;
+ wire [63:0] T_519;
+ wire T_520;
+ wire [15:0] T_521;
+ wire [15:0] T_522;
+ wire [15:0] T_523;
+ wire T_525;
+ wire [15:0] T_527;
+ wire T_529;
+ wire T_530;
+ wire T_531;
+ wire T_532;
+ wire [48:0] T_534;
+ wire [47:0] T_535;
+ wire [47:0] T_536;
+ wire [47:0] T_537;
+ wire [63:0] T_538;
+ wire T_539;
+ wire [7:0] T_540;
+ wire [7:0] T_541;
+ wire [7:0] T_542;
+ wire T_544;
+ wire [7:0] T_546;
+ wire T_548;
+ wire T_549;
+ wire T_550;
+ wire T_551;
+ wire [56:0] T_553;
+ wire [55:0] T_554;
+ wire [55:0] T_555;
+ wire [55:0] T_556;
+ wire [63:0] rdata;
+ wire [1:0] T_566_resp;
+ wire [63:0] T_566_data;
+ wire T_566_last;
+ wire [4:0] T_566_id;
+ wire T_566_user;
+ wire GEN_4;
+ wire GEN_5;
+ wire GEN_6;
+ wire GEN_7;
+ wire GEN_8;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ wire GEN_17;
+ wire GEN_18;
+ wire GEN_19;
+ wire GEN_20;
+ wire GEN_21;
+ wire GEN_22;
+ wire GEN_23;
+ wire GEN_24;
+ wire GEN_25;
+ wire GEN_26;
+ wire GEN_27;
+ wire GEN_28;
+ wire GEN_29;
+ wire GEN_30;
+ wire GEN_31;
+ wire GEN_32;
+ wire GEN_33;
+ wire GEN_34;
+ wire GEN_35;
+ wire GEN_36;
+ wire GEN_37;
+ wire GEN_38;
+ wire GEN_39;
+ wire GEN_40;
+ wire GEN_41;
+ wire GEN_42;
+ wire GEN_43;
+ wire GEN_44;
+ wire GEN_45;
+ wire GEN_46;
+ wire GEN_47;
+ wire GEN_48;
+ wire GEN_49;
+ wire GEN_50;
+ wire GEN_51;
+ wire GEN_52;
+ wire GEN_53;
+ wire GEN_54;
+ wire GEN_55;
+ wire GEN_56;
+ wire GEN_57;
+ wire GEN_58;
+ wire GEN_59;
+ wire GEN_60;
+ wire GEN_61;
+ wire GEN_62;
+ wire GEN_63;
+ wire GEN_64;
+ wire GEN_65;
+ wire GEN_66;
+ wire GEN_67;
+ wire GEN_68;
+ wire GEN_69;
+ wire GEN_70;
+ wire GEN_71;
+ wire GEN_72;
+ wire GEN_73;
+ wire GEN_74;
+ wire GEN_75;
+ wire GEN_76;
+ wire GEN_77;
+ wire GEN_78;
+ wire GEN_79;
+ wire GEN_80;
+ wire GEN_81;
+ wire GEN_82;
+ wire GEN_83;
+ wire GEN_84;
+ wire GEN_85;
+ wire GEN_86;
+ wire GEN_87;
+ wire GEN_88;
+ wire GEN_89;
+ wire GEN_90;
+ wire GEN_91;
+ wire GEN_92;
+ wire GEN_93;
+ wire GEN_94;
+ wire GEN_95;
+ wire GEN_96;
+ wire GEN_97;
+ wire GEN_98;
+ wire GEN_99;
+ wire GEN_100;
+ wire GEN_101;
+ wire GEN_102;
+ wire GEN_103;
+ wire GEN_104;
+ wire GEN_105;
+ wire GEN_106;
+ wire GEN_107;
+ wire GEN_108;
+ wire GEN_109;
+ wire GEN_110;
+ wire GEN_111;
+ wire GEN_112;
+ wire GEN_113;
+ wire GEN_114;
+ wire GEN_115;
+ wire GEN_116;
+ wire GEN_117;
+ wire GEN_118;
+ wire GEN_119;
+ wire GEN_120;
+ wire GEN_121;
+ wire GEN_122;
+ wire GEN_123;
+ wire GEN_124;
+ wire GEN_125;
+ wire GEN_126;
+ wire GEN_127;
+ wire GEN_128;
+ wire GEN_129;
+ wire GEN_130;
+ wire GEN_131;
+ wire GEN_132;
+ wire GEN_133;
+ wire GEN_134;
+ wire GEN_135;
+ wire GEN_136;
+ wire GEN_137;
+ wire GEN_138;
+ wire GEN_139;
+ wire GEN_140;
+ wire GEN_141;
+ wire GEN_142;
+ wire GEN_143;
+ wire GEN_144;
+ wire GEN_145;
+ wire GEN_146;
+ wire GEN_147;
+ wire GEN_148;
+ wire GEN_149;
+ wire GEN_150;
+ wire GEN_151;
+ wire GEN_152;
+ wire GEN_153;
+ wire GEN_154;
+ wire GEN_155;
+ wire GEN_156;
+ wire GEN_157;
+ wire GEN_158;
+ wire GEN_159;
+ wire GEN_160;
+ wire GEN_161;
+ wire GEN_162;
+ wire GEN_163;
+ wire GEN_164;
+ wire GEN_165;
+ wire GEN_166;
+ wire GEN_167;
+ wire GEN_168;
+ wire GEN_169;
+ wire GEN_170;
+ wire GEN_171;
+ wire GEN_172;
+ wire GEN_173;
+ wire GEN_174;
+ wire GEN_175;
+ wire GEN_176;
+ wire GEN_177;
+ wire GEN_178;
+ wire GEN_179;
+ wire GEN_180;
+ wire GEN_181;
+ wire GEN_182;
+ wire GEN_183;
+ wire GEN_184;
+ wire GEN_185;
+ wire GEN_186;
+ wire GEN_187;
+ wire GEN_188;
+ wire GEN_189;
+ wire GEN_190;
+ wire GEN_191;
+ wire GEN_192;
+ wire GEN_193;
+ wire GEN_194;
+ wire GEN_195;
+ wire GEN_196;
+ wire GEN_197;
+ wire GEN_198;
+ wire GEN_199;
+ wire GEN_200;
+ wire GEN_201;
+ wire GEN_202;
+ wire GEN_203;
+ wire GEN_204;
+ wire GEN_205;
+ reg [1:0] GEN_206;
+ reg [4:0] GEN_207;
+ reg GEN_208;
+ Queue_89 T_334 (
+ .clk(T_334_clk),
+ .reset(T_334_reset),
+ .io_enq_ready(T_334_io_enq_ready),
+ .io_enq_valid(T_334_io_enq_valid),
+ .io_enq_bits_addr(T_334_io_enq_bits_addr),
+ .io_enq_bits_len(T_334_io_enq_bits_len),
+ .io_enq_bits_size(T_334_io_enq_bits_size),
+ .io_enq_bits_burst(T_334_io_enq_bits_burst),
+ .io_enq_bits_lock(T_334_io_enq_bits_lock),
+ .io_enq_bits_cache(T_334_io_enq_bits_cache),
+ .io_enq_bits_prot(T_334_io_enq_bits_prot),
+ .io_enq_bits_qos(T_334_io_enq_bits_qos),
+ .io_enq_bits_region(T_334_io_enq_bits_region),
+ .io_enq_bits_id(T_334_io_enq_bits_id),
+ .io_enq_bits_user(T_334_io_enq_bits_user),
+ .io_deq_ready(T_334_io_deq_ready),
+ .io_deq_valid(T_334_io_deq_valid),
+ .io_deq_bits_addr(T_334_io_deq_bits_addr),
+ .io_deq_bits_len(T_334_io_deq_bits_len),
+ .io_deq_bits_size(T_334_io_deq_bits_size),
+ .io_deq_bits_burst(T_334_io_deq_bits_burst),
+ .io_deq_bits_lock(T_334_io_deq_bits_lock),
+ .io_deq_bits_cache(T_334_io_deq_bits_cache),
+ .io_deq_bits_prot(T_334_io_deq_bits_prot),
+ .io_deq_bits_qos(T_334_io_deq_bits_qos),
+ .io_deq_bits_region(T_334_io_deq_bits_region),
+ .io_deq_bits_id(T_334_io_deq_bits_id),
+ .io_deq_bits_user(T_334_io_deq_bits_user),
+ .io_count(T_334_io_count)
+ );
+ assign io_aw_ready = 1'h0;
+ assign io_w_ready = 1'h0;
+ assign io_b_valid = 1'h0;
+ assign io_b_bits_resp = GEN_206;
+ assign io_b_bits_id = GEN_207;
+ assign io_b_bits_user = GEN_208;
+ assign io_ar_ready = T_334_io_enq_ready;
+ assign io_r_valid = T_334_io_deq_valid;
+ assign io_r_bits_resp = T_566_resp;
+ assign io_r_bits_data = T_566_data;
+ assign io_r_bits_last = T_566_last;
+ assign io_r_bits_id = T_566_id;
+ assign io_r_bits_user = T_566_user;
+ assign T_334_clk = clk;
+ assign T_334_reset = reset;
+ assign T_334_io_enq_valid = io_ar_valid;
+ assign T_334_io_enq_bits_addr = io_ar_bits_addr;
+ assign T_334_io_enq_bits_len = io_ar_bits_len;
+ assign T_334_io_enq_bits_size = io_ar_bits_size;
+ assign T_334_io_enq_bits_burst = io_ar_bits_burst;
+ assign T_334_io_enq_bits_lock = io_ar_bits_lock;
+ assign T_334_io_enq_bits_cache = io_ar_bits_cache;
+ assign T_334_io_enq_bits_prot = io_ar_bits_prot;
+ assign T_334_io_enq_bits_qos = io_ar_bits_qos;
+ assign T_334_io_enq_bits_region = io_ar_bits_region;
+ assign T_334_io_enq_bits_id = io_ar_bits_id;
+ assign T_334_io_enq_bits_user = io_ar_bits_user;
+ assign T_334_io_deq_ready = io_r_ready;
+ assign T_336 = T_334_io_deq_bits_len == 1'h0;
+ assign T_338 = reset == 1'h0;
+ assign T_340 = T_336 == 1'h0;
+ assign T_342 = reset == 1'h0;
+ assign T_343 = io_aw_valid | io_w_valid;
+ assign T_345 = T_343 == 1'h0;
+ assign T_347 = reset == 1'h0;
+ assign T_349 = T_345 == 1'h0;
+ assign T_351 = reset == 1'h0;
+ assign rom_0 = 60'hb020000edfe0dd0;
+ assign rom_1 = 64'hc001000038000000;
+ assign rom_2 = 61'h1100000028000000;
+ assign rom_3 = 29'h10000000;
+ assign rom_4 = 64'h880100004b000000;
+ assign rom_5 = 1'h0;
+ assign rom_6 = 1'h0;
+ assign rom_7 = 25'h1000000;
+ assign rom_8 = 59'h400000003000000;
+ assign rom_9 = 58'h200000000000000;
+ assign rom_10 = 59'h400000003000000;
+ assign rom_11 = 58'h20000000f000000;
+ assign rom_12 = 60'hc00000003000000;
+ assign rom_13 = 63'h6b636f521b000000;
+ assign rom_14 = 55'h706968432d7465;
+ assign rom_15 = 63'h6f6d656d01000000;
+ assign rom_16 = 30'h30407972;
+ assign rom_17 = 59'h700000003000000;
+ assign rom_18 = 63'h6f6d656d21000000;
+ assign rom_19 = 58'h300000000007972;
+ assign rom_20 = 62'h2d00000010000000;
+ assign rom_21 = 1'h0;
+ assign rom_22 = 39'h4000000000;
+ assign rom_23 = 57'h100000002000000;
+ assign rom_24 = 31'h73757063;
+ assign rom_25 = 59'h400000003000000;
+ assign rom_26 = 58'h200000000000000;
+ assign rom_27 = 59'h400000003000000;
+ assign rom_28 = 58'h20000000f000000;
+ assign rom_29 = 63'h4075706301000000;
+ assign rom_30 = 62'h3030303830303034;
+ assign rom_31 = 58'h300000000000000;
+ assign rom_32 = 62'h2100000004000000;
+ assign rom_33 = 58'h300000000757063;
+ assign rom_34 = 62'h3100000006000000;
+ assign rom_35 = 39'h7663736972;
+ assign rom_36 = 59'h500000003000000;
+ assign rom_37 = 62'h343676723c000000;
+ assign rom_38 = 58'h300000000000000;
+ assign rom_39 = 62'h2d00000008000000;
+ assign rom_40 = 56'h80004000000000;
+ assign rom_41 = 58'h200000002000000;
+ assign rom_42 = 63'h4072637301000000;
+ assign rom_43 = 62'h3030303031303034;
+ assign rom_44 = 58'h300000000000000;
+ assign rom_45 = 62'h2100000004000000;
+ assign rom_46 = 58'h300000000726373;
+ assign rom_47 = 62'h3100000006000000;
+ assign rom_48 = 39'h7663736972;
+ assign rom_49 = 59'h400000003000000;
+ assign rom_50 = 58'h300000040000000;
+ assign rom_51 = 61'h1000000003000000;
+ assign rom_52 = 30'h2d000000;
+ assign rom_53 = 9'h140;
+ assign rom_54 = 58'h200000000020000;
+ assign rom_55 = 60'h900000002000000;
+ assign rom_56 = 63'h7373657264646123;
+ assign rom_57 = 62'h2300736c6c65632d;
+ assign rom_58 = 63'h6c65632d657a6973;
+ assign rom_59 = 63'h6c65646f6d00736c;
+ assign rom_60 = 63'h5f65636976656400;
+ assign rom_61 = 63'h6765720065707974;
+ assign rom_62 = 63'h697461706d6f6300;
+ assign rom_63 = 55'h61736900656c62;
+ assign rom_64 = 63'h69746365746f7270;
+ assign rom_65 = 15'h6e6f;
+ assign rom_66 = 1'h0;
+ assign T_492 = T_334_io_deq_bits_addr[9:3];
+ assign T_495 = {1'h1,T_334_io_deq_bits_size};
+ assign T_497 = T_495[1:0];
+ assign T_498 = $signed(T_495);
+ assign GEN_3 = $signed(1'h0);
+ assign T_500 = $signed(T_498) >= $signed(GEN_3);
+ assign T_501 = T_334_io_deq_bits_addr[2];
+ assign GEN_0 = GEN_8 ? rom_66 : GEN_9 ? rom_65 : GEN_10 ? rom_64 : GEN_11 ? rom_63 : GEN_12 ? rom_62 : GEN_13 ? rom_61 : GEN_14 ? rom_60 : GEN_15 ? rom_59 : GEN_16 ? rom_58 : GEN_17 ? rom_57 : GEN_18 ? rom_56 : GEN_19 ? rom_55 : GEN_20 ? rom_54 : GEN_21 ? rom_53 : GEN_22 ? rom_52 : GEN_23 ? rom_51 : GEN_24 ? rom_50 : GEN_25 ? rom_49 : GEN_26 ? rom_48 : GEN_27 ? rom_47 : GEN_28 ? rom_46 : GEN_29 ? rom_45 : GEN_30 ? rom_44 : GEN_31 ? rom_43 : GEN_32 ? rom_42 : GEN_33 ? rom_41 : GEN_34 ? rom_40 : GEN_35 ? rom_39 : GEN_36 ? rom_38 : GEN_37 ? rom_37 : GEN_38 ? rom_36 : GEN_39 ? rom_35 : GEN_40 ? rom_34 : GEN_41 ? rom_33 : GEN_42 ? rom_32 : GEN_43 ? rom_31 : GEN_44 ? rom_30 : GEN_45 ? rom_29 : GEN_46 ? rom_28 : GEN_47 ? rom_27 : GEN_48 ? rom_26 : GEN_49 ? rom_25 : GEN_50 ? rom_24 : GEN_51 ? rom_23 : GEN_52 ? rom_22 : GEN_53 ? rom_21 : GEN_54 ? rom_20 : GEN_55 ? rom_19 : GEN_56 ? rom_18 : GEN_57 ? rom_17 : GEN_58 ? rom_16 : GEN_59 ? rom_15 : GEN_60 ? rom_14 : GEN_61 ? rom_13 : GEN_62 ? rom_12 : GEN_63 ? rom_11 : GEN_64 ? rom_10 : GEN_65 ? rom_9 : GEN_66 ? rom_8 : GEN_67 ? rom_7 : GEN_68 ? rom_6 : GEN_69 ? rom_5 : GEN_70 ? rom_4 : GEN_71 ? rom_3 : GEN_72 ? rom_2 : GEN_73 ? rom_1 : rom_0;
+ assign T_502 = GEN_0[63:32];
+ assign GEN_1 = GEN_74 ? rom_66 : GEN_75 ? rom_65 : GEN_76 ? rom_64 : GEN_77 ? rom_63 : GEN_78 ? rom_62 : GEN_79 ? rom_61 : GEN_80 ? rom_60 : GEN_81 ? rom_59 : GEN_82 ? rom_58 : GEN_83 ? rom_57 : GEN_84 ? rom_56 : GEN_85 ? rom_55 : GEN_86 ? rom_54 : GEN_87 ? rom_53 : GEN_88 ? rom_52 : GEN_89 ? rom_51 : GEN_90 ? rom_50 : GEN_91 ? rom_49 : GEN_92 ? rom_48 : GEN_93 ? rom_47 : GEN_94 ? rom_46 : GEN_95 ? rom_45 : GEN_96 ? rom_44 : GEN_97 ? rom_43 : GEN_98 ? rom_42 : GEN_99 ? rom_41 : GEN_100 ? rom_40 : GEN_101 ? rom_39 : GEN_102 ? rom_38 : GEN_103 ? rom_37 : GEN_104 ? rom_36 : GEN_105 ? rom_35 : GEN_106 ? rom_34 : GEN_107 ? rom_33 : GEN_108 ? rom_32 : GEN_109 ? rom_31 : GEN_110 ? rom_30 : GEN_111 ? rom_29 : GEN_112 ? rom_28 : GEN_113 ? rom_27 : GEN_114 ? rom_26 : GEN_115 ? rom_25 : GEN_116 ? rom_24 : GEN_117 ? rom_23 : GEN_118 ? rom_22 : GEN_119 ? rom_21 : GEN_120 ? rom_20 : GEN_121 ? rom_19 : GEN_122 ? rom_18 : GEN_123 ? rom_17 : GEN_124 ? rom_16 : GEN_125 ? rom_15 : GEN_126 ? rom_14 : GEN_127 ? rom_13 : GEN_128 ? rom_12 : GEN_129 ? rom_11 : GEN_130 ? rom_10 : GEN_131 ? rom_9 : GEN_132 ? rom_8 : GEN_133 ? rom_7 : GEN_134 ? rom_6 : GEN_135 ? rom_5 : GEN_136 ? rom_4 : GEN_137 ? rom_3 : GEN_138 ? rom_2 : GEN_139 ? rom_1 : rom_0;
+ assign T_503 = GEN_1[31:0];
+ assign T_504 = T_501 ? T_502 : T_503;
+ assign T_506 = 1'h0 & 1'h0;
+ assign T_508 = T_506 ? 1'h0 : T_504;
+ assign T_510 = T_497 == 2'h2;
+ assign T_511 = T_510 | T_506;
+ assign T_512 = T_508[31];
+ assign T_513 = T_500 & T_512;
+ assign T_515 = 32'h0 - T_513;
+ assign T_516 = T_515[31:0];
+ assign GEN_2 = GEN_140 ? rom_66 : GEN_141 ? rom_65 : GEN_142 ? rom_64 : GEN_143 ? rom_63 : GEN_144 ? rom_62 : GEN_145 ? rom_61 : GEN_146 ? rom_60 : GEN_147 ? rom_59 : GEN_148 ? rom_58 : GEN_149 ? rom_57 : GEN_150 ? rom_56 : GEN_151 ? rom_55 : GEN_152 ? rom_54 : GEN_153 ? rom_53 : GEN_154 ? rom_52 : GEN_155 ? rom_51 : GEN_156 ? rom_50 : GEN_157 ? rom_49 : GEN_158 ? rom_48 : GEN_159 ? rom_47 : GEN_160 ? rom_46 : GEN_161 ? rom_45 : GEN_162 ? rom_44 : GEN_163 ? rom_43 : GEN_164 ? rom_42 : GEN_165 ? rom_41 : GEN_166 ? rom_40 : GEN_167 ? rom_39 : GEN_168 ? rom_38 : GEN_169 ? rom_37 : GEN_170 ? rom_36 : GEN_171 ? rom_35 : GEN_172 ? rom_34 : GEN_173 ? rom_33 : GEN_174 ? rom_32 : GEN_175 ? rom_31 : GEN_176 ? rom_30 : GEN_177 ? rom_29 : GEN_178 ? rom_28 : GEN_179 ? rom_27 : GEN_180 ? rom_26 : GEN_181 ? rom_25 : GEN_182 ? rom_24 : GEN_183 ? rom_23 : GEN_184 ? rom_22 : GEN_185 ? rom_21 : GEN_186 ? rom_20 : GEN_187 ? rom_19 : GEN_188 ? rom_18 : GEN_189 ? rom_17 : GEN_190 ? rom_16 : GEN_191 ? rom_15 : GEN_192 ? rom_14 : GEN_193 ? rom_13 : GEN_194 ? rom_12 : GEN_195 ? rom_11 : GEN_196 ? rom_10 : GEN_197 ? rom_9 : GEN_198 ? rom_8 : GEN_199 ? rom_7 : GEN_200 ? rom_6 : GEN_201 ? rom_5 : GEN_202 ? rom_4 : GEN_203 ? rom_3 : GEN_204 ? rom_2 : GEN_205 ? rom_1 : rom_0;
+ assign T_517 = GEN_2[63:32];
+ assign T_518 = T_511 ? T_516 : T_517;
+ assign T_519 = {T_518,T_508};
+ assign T_520 = T_334_io_deq_bits_addr[1];
+ assign T_521 = T_519[31:16];
+ assign T_522 = T_519[15:0];
+ assign T_523 = T_520 ? T_521 : T_522;
+ assign T_525 = 1'h0 & 1'h0;
+ assign T_527 = T_525 ? 1'h0 : T_523;
+ assign T_529 = T_497 == 1'h1;
+ assign T_530 = T_529 | T_525;
+ assign T_531 = T_527[15];
+ assign T_532 = T_500 & T_531;
+ assign T_534 = 48'h0 - T_532;
+ assign T_535 = T_534[47:0];
+ assign T_536 = T_519[63:16];
+ assign T_537 = T_530 ? T_535 : T_536;
+ assign T_538 = {T_537,T_527};
+ assign T_539 = T_334_io_deq_bits_addr[0];
+ assign T_540 = T_538[15:8];
+ assign T_541 = T_538[7:0];
+ assign T_542 = T_539 ? T_540 : T_541;
+ assign T_544 = 1'h1 & 1'h0;
+ assign T_546 = T_544 ? 1'h0 : T_542;
+ assign T_548 = T_497 == 1'h0;
+ assign T_549 = T_548 | T_544;
+ assign T_550 = T_546[7];
+ assign T_551 = T_500 & T_550;
+ assign T_553 = 56'h0 - T_551;
+ assign T_554 = T_553[55:0];
+ assign T_555 = T_538[63:8];
+ assign T_556 = T_549 ? T_554 : T_555;
+ assign rdata = {T_556,T_546};
+ assign T_566_resp = 1'h0;
+ assign T_566_data = rdata;
+ assign T_566_last = 1'h1;
+ assign T_566_id = T_334_io_deq_bits_id;
+ assign T_566_user = 1'h0;
+ assign GEN_4 = T_334_io_deq_valid & T_338;
+ assign GEN_5 = GEN_4 & T_340;
+ assign GEN_6 = T_334_io_deq_valid & T_338;
+ assign GEN_7 = T_347 & T_349;
+ assign GEN_8 = 7'h42 == T_492;
+ assign GEN_9 = 7'h41 == T_492;
+ assign GEN_10 = 7'h40 == T_492;
+ assign GEN_11 = 6'h3f == T_492;
+ assign GEN_12 = 6'h3e == T_492;
+ assign GEN_13 = 6'h3d == T_492;
+ assign GEN_14 = 6'h3c == T_492;
+ assign GEN_15 = 6'h3b == T_492;
+ assign GEN_16 = 6'h3a == T_492;
+ assign GEN_17 = 6'h39 == T_492;
+ assign GEN_18 = 6'h38 == T_492;
+ assign GEN_19 = 6'h37 == T_492;
+ assign GEN_20 = 6'h36 == T_492;
+ assign GEN_21 = 6'h35 == T_492;
+ assign GEN_22 = 6'h34 == T_492;
+ assign GEN_23 = 6'h33 == T_492;
+ assign GEN_24 = 6'h32 == T_492;
+ assign GEN_25 = 6'h31 == T_492;
+ assign GEN_26 = 6'h30 == T_492;
+ assign GEN_27 = 6'h2f == T_492;
+ assign GEN_28 = 6'h2e == T_492;
+ assign GEN_29 = 6'h2d == T_492;
+ assign GEN_30 = 6'h2c == T_492;
+ assign GEN_31 = 6'h2b == T_492;
+ assign GEN_32 = 6'h2a == T_492;
+ assign GEN_33 = 6'h29 == T_492;
+ assign GEN_34 = 6'h28 == T_492;
+ assign GEN_35 = 6'h27 == T_492;
+ assign GEN_36 = 6'h26 == T_492;
+ assign GEN_37 = 6'h25 == T_492;
+ assign GEN_38 = 6'h24 == T_492;
+ assign GEN_39 = 6'h23 == T_492;
+ assign GEN_40 = 6'h22 == T_492;
+ assign GEN_41 = 6'h21 == T_492;
+ assign GEN_42 = 6'h20 == T_492;
+ assign GEN_43 = 5'h1f == T_492;
+ assign GEN_44 = 5'h1e == T_492;
+ assign GEN_45 = 5'h1d == T_492;
+ assign GEN_46 = 5'h1c == T_492;
+ assign GEN_47 = 5'h1b == T_492;
+ assign GEN_48 = 5'h1a == T_492;
+ assign GEN_49 = 5'h19 == T_492;
+ assign GEN_50 = 5'h18 == T_492;
+ assign GEN_51 = 5'h17 == T_492;
+ assign GEN_52 = 5'h16 == T_492;
+ assign GEN_53 = 5'h15 == T_492;
+ assign GEN_54 = 5'h14 == T_492;
+ assign GEN_55 = 5'h13 == T_492;
+ assign GEN_56 = 5'h12 == T_492;
+ assign GEN_57 = 5'h11 == T_492;
+ assign GEN_58 = 5'h10 == T_492;
+ assign GEN_59 = 4'hf == T_492;
+ assign GEN_60 = 4'he == T_492;
+ assign GEN_61 = 4'hd == T_492;
+ assign GEN_62 = 4'hc == T_492;
+ assign GEN_63 = 4'hb == T_492;
+ assign GEN_64 = 4'ha == T_492;
+ assign GEN_65 = 4'h9 == T_492;
+ assign GEN_66 = 4'h8 == T_492;
+ assign GEN_67 = 3'h7 == T_492;
+ assign GEN_68 = 3'h6 == T_492;
+ assign GEN_69 = 3'h5 == T_492;
+ assign GEN_70 = 3'h4 == T_492;
+ assign GEN_71 = 2'h3 == T_492;
+ assign GEN_72 = 2'h2 == T_492;
+ assign GEN_73 = 1'h1 == T_492;
+ assign GEN_74 = 7'h42 == T_492;
+ assign GEN_75 = 7'h41 == T_492;
+ assign GEN_76 = 7'h40 == T_492;
+ assign GEN_77 = 6'h3f == T_492;
+ assign GEN_78 = 6'h3e == T_492;
+ assign GEN_79 = 6'h3d == T_492;
+ assign GEN_80 = 6'h3c == T_492;
+ assign GEN_81 = 6'h3b == T_492;
+ assign GEN_82 = 6'h3a == T_492;
+ assign GEN_83 = 6'h39 == T_492;
+ assign GEN_84 = 6'h38 == T_492;
+ assign GEN_85 = 6'h37 == T_492;
+ assign GEN_86 = 6'h36 == T_492;
+ assign GEN_87 = 6'h35 == T_492;
+ assign GEN_88 = 6'h34 == T_492;
+ assign GEN_89 = 6'h33 == T_492;
+ assign GEN_90 = 6'h32 == T_492;
+ assign GEN_91 = 6'h31 == T_492;
+ assign GEN_92 = 6'h30 == T_492;
+ assign GEN_93 = 6'h2f == T_492;
+ assign GEN_94 = 6'h2e == T_492;
+ assign GEN_95 = 6'h2d == T_492;
+ assign GEN_96 = 6'h2c == T_492;
+ assign GEN_97 = 6'h2b == T_492;
+ assign GEN_98 = 6'h2a == T_492;
+ assign GEN_99 = 6'h29 == T_492;
+ assign GEN_100 = 6'h28 == T_492;
+ assign GEN_101 = 6'h27 == T_492;
+ assign GEN_102 = 6'h26 == T_492;
+ assign GEN_103 = 6'h25 == T_492;
+ assign GEN_104 = 6'h24 == T_492;
+ assign GEN_105 = 6'h23 == T_492;
+ assign GEN_106 = 6'h22 == T_492;
+ assign GEN_107 = 6'h21 == T_492;
+ assign GEN_108 = 6'h20 == T_492;
+ assign GEN_109 = 5'h1f == T_492;
+ assign GEN_110 = 5'h1e == T_492;
+ assign GEN_111 = 5'h1d == T_492;
+ assign GEN_112 = 5'h1c == T_492;
+ assign GEN_113 = 5'h1b == T_492;
+ assign GEN_114 = 5'h1a == T_492;
+ assign GEN_115 = 5'h19 == T_492;
+ assign GEN_116 = 5'h18 == T_492;
+ assign GEN_117 = 5'h17 == T_492;
+ assign GEN_118 = 5'h16 == T_492;
+ assign GEN_119 = 5'h15 == T_492;
+ assign GEN_120 = 5'h14 == T_492;
+ assign GEN_121 = 5'h13 == T_492;
+ assign GEN_122 = 5'h12 == T_492;
+ assign GEN_123 = 5'h11 == T_492;
+ assign GEN_124 = 5'h10 == T_492;
+ assign GEN_125 = 4'hf == T_492;
+ assign GEN_126 = 4'he == T_492;
+ assign GEN_127 = 4'hd == T_492;
+ assign GEN_128 = 4'hc == T_492;
+ assign GEN_129 = 4'hb == T_492;
+ assign GEN_130 = 4'ha == T_492;
+ assign GEN_131 = 4'h9 == T_492;
+ assign GEN_132 = 4'h8 == T_492;
+ assign GEN_133 = 3'h7 == T_492;
+ assign GEN_134 = 3'h6 == T_492;
+ assign GEN_135 = 3'h5 == T_492;
+ assign GEN_136 = 3'h4 == T_492;
+ assign GEN_137 = 2'h3 == T_492;
+ assign GEN_138 = 2'h2 == T_492;
+ assign GEN_139 = 1'h1 == T_492;
+ assign GEN_140 = 7'h42 == T_492;
+ assign GEN_141 = 7'h41 == T_492;
+ assign GEN_142 = 7'h40 == T_492;
+ assign GEN_143 = 6'h3f == T_492;
+ assign GEN_144 = 6'h3e == T_492;
+ assign GEN_145 = 6'h3d == T_492;
+ assign GEN_146 = 6'h3c == T_492;
+ assign GEN_147 = 6'h3b == T_492;
+ assign GEN_148 = 6'h3a == T_492;
+ assign GEN_149 = 6'h39 == T_492;
+ assign GEN_150 = 6'h38 == T_492;
+ assign GEN_151 = 6'h37 == T_492;
+ assign GEN_152 = 6'h36 == T_492;
+ assign GEN_153 = 6'h35 == T_492;
+ assign GEN_154 = 6'h34 == T_492;
+ assign GEN_155 = 6'h33 == T_492;
+ assign GEN_156 = 6'h32 == T_492;
+ assign GEN_157 = 6'h31 == T_492;
+ assign GEN_158 = 6'h30 == T_492;
+ assign GEN_159 = 6'h2f == T_492;
+ assign GEN_160 = 6'h2e == T_492;
+ assign GEN_161 = 6'h2d == T_492;
+ assign GEN_162 = 6'h2c == T_492;
+ assign GEN_163 = 6'h2b == T_492;
+ assign GEN_164 = 6'h2a == T_492;
+ assign GEN_165 = 6'h29 == T_492;
+ assign GEN_166 = 6'h28 == T_492;
+ assign GEN_167 = 6'h27 == T_492;
+ assign GEN_168 = 6'h26 == T_492;
+ assign GEN_169 = 6'h25 == T_492;
+ assign GEN_170 = 6'h24 == T_492;
+ assign GEN_171 = 6'h23 == T_492;
+ assign GEN_172 = 6'h22 == T_492;
+ assign GEN_173 = 6'h21 == T_492;
+ assign GEN_174 = 6'h20 == T_492;
+ assign GEN_175 = 5'h1f == T_492;
+ assign GEN_176 = 5'h1e == T_492;
+ assign GEN_177 = 5'h1d == T_492;
+ assign GEN_178 = 5'h1c == T_492;
+ assign GEN_179 = 5'h1b == T_492;
+ assign GEN_180 = 5'h1a == T_492;
+ assign GEN_181 = 5'h19 == T_492;
+ assign GEN_182 = 5'h18 == T_492;
+ assign GEN_183 = 5'h17 == T_492;
+ assign GEN_184 = 5'h16 == T_492;
+ assign GEN_185 = 5'h15 == T_492;
+ assign GEN_186 = 5'h14 == T_492;
+ assign GEN_187 = 5'h13 == T_492;
+ assign GEN_188 = 5'h12 == T_492;
+ assign GEN_189 = 5'h11 == T_492;
+ assign GEN_190 = 5'h10 == T_492;
+ assign GEN_191 = 4'hf == T_492;
+ assign GEN_192 = 4'he == T_492;
+ assign GEN_193 = 4'hd == T_492;
+ assign GEN_194 = 4'hc == T_492;
+ assign GEN_195 = 4'hb == T_492;
+ assign GEN_196 = 4'ha == T_492;
+ assign GEN_197 = 4'h9 == T_492;
+ assign GEN_198 = 4'h8 == T_492;
+ assign GEN_199 = 3'h7 == T_492;
+ assign GEN_200 = 3'h6 == T_492;
+ assign GEN_201 = 3'h5 == T_492;
+ assign GEN_202 = 3'h4 == T_492;
+ assign GEN_203 = 2'h3 == T_492;
+ assign GEN_204 = 2'h2 == T_492;
+ assign GEN_205 = 1'h1 == T_492;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ GEN_206 = {1{$random}};
+ GEN_207 = {1{$random}};
+ GEN_208 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ `ifndef SYNTHESIS
+ if(GEN_5 & T_342) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Can't burst-read from NastiROM");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_6 & T_340) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_7 & T_351) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Can't write to NastiROM");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_347 & T_349) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ end
+endmodule
+module Queue_90(
+ input clk,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [16:0] io_enq_bits,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [16:0] io_deq_bits,
+ output io_count
+);
+ reg [16:0] ram [0:0];
+ wire [16:0] ram_T_59_data;
+ wire ram_T_59_addr;
+ wire ram_T_59_en;
+ wire ram_T_59_clk;
+ wire [16:0] ram_T_45_data;
+ wire ram_T_45_addr;
+ wire ram_T_45_mask;
+ wire ram_T_45_en;
+ wire ram_T_45_clk;
+ reg maybe_full;
+ wire ptr_match;
+ wire T_31;
+ wire empty;
+ wire full;
+ wire maybe_flow;
+ wire do_flow;
+ wire T_37;
+ wire T_39;
+ wire do_enq;
+ wire T_41;
+ wire T_43;
+ wire do_deq;
+ wire T_48;
+ wire T_50;
+ wire T_52;
+ wire T_53;
+ wire T_55;
+ wire T_57;
+ wire T_58;
+ wire [16:0] T_60;
+ wire [1:0] T_61;
+ wire ptr_diff;
+ wire T_63;
+ wire [1:0] T_64;
+ assign io_enq_ready = T_58;
+ assign io_deq_valid = T_53;
+ assign io_deq_bits = T_60;
+ assign io_count = T_64;
+ assign ram_T_59_addr = 1'h0;
+ assign ram_T_59_en = 1'h1;
+ assign ram_T_59_clk = clk;
+ assign ram_T_59_data = ram[ram_T_59_addr];
+ assign ram_T_45_data = io_enq_bits;
+ assign ram_T_45_addr = 1'h0;
+ assign ram_T_45_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_T_45_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_T_45_clk = clk;
+ assign ptr_match = 1'h0 == 1'h0;
+ assign T_31 = maybe_full == 1'h0;
+ assign empty = ptr_match & T_31;
+ assign full = ptr_match & maybe_full;
+ assign maybe_flow = 1'h0 & empty;
+ assign do_flow = maybe_flow & io_deq_ready;
+ assign T_37 = io_enq_ready & io_enq_valid;
+ assign T_39 = do_flow == 1'h0;
+ assign do_enq = T_37 & T_39;
+ assign T_41 = io_deq_ready & io_deq_valid;
+ assign T_43 = do_flow == 1'h0;
+ assign do_deq = T_41 & T_43;
+ assign T_48 = do_enq != do_deq;
+ assign T_50 = empty == 1'h0;
+ assign T_52 = 1'h0 & io_enq_valid;
+ assign T_53 = T_50 | T_52;
+ assign T_55 = full == 1'h0;
+ assign T_57 = 1'h0 & io_deq_ready;
+ assign T_58 = T_55 | T_57;
+ assign T_60 = maybe_flow ? io_enq_bits : ram_T_59_data;
+ assign T_61 = 1'h0 - 1'h0;
+ assign ptr_diff = T_61[0:0];
+ assign T_63 = maybe_full & ptr_match;
+ assign T_64 = {T_63,ptr_diff};
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram[initvar] = {1{$random}};
+ maybe_full = {1{$random}};
+ end
+`endif
+ always @(posedge ram_T_45_clk) begin
+ if(ram_T_45_en & ram_T_45_mask) begin
+ ram[ram_T_45_addr] <= ram_T_45_data;
+ end
+ end
+ always @(posedge clk) begin
+ if(reset) begin
+ maybe_full <= 1'h0;
+ end else begin
+ if(T_48) begin
+ maybe_full <= do_enq;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module SlowIO(
+ input clk,
+ input reset,
+ output io_out_fast_ready,
+ input io_out_fast_valid,
+ input [16:0] io_out_fast_bits,
+ input io_out_slow_ready,
+ output io_out_slow_valid,
+ output [16:0] io_out_slow_bits,
+ input io_in_fast_ready,
+ output io_in_fast_valid,
+ output [16:0] io_in_fast_bits,
+ output io_in_slow_ready,
+ input io_in_slow_valid,
+ input [16:0] io_in_slow_bits,
+ output io_clk_slow,
+ input io_set_divisor_valid,
+ input [31:0] io_set_divisor_bits,
+ output [31:0] io_divisor
+);
+ reg [8:0] divisor;
+ reg [8:0] d_shadow;
+ reg [8:0] hold;
+ reg [8:0] h_shadow;
+ wire [8:0] T_57;
+ wire [8:0] T_58;
+ wire [24:0] T_59;
+ wire [24:0] T_60;
+ reg [8:0] count;
+ reg myclock;
+ wire [9:0] T_66;
+ wire [8:0] T_67;
+ wire [7:0] T_68;
+ wire rising;
+ wire falling;
+ wire [7:0] T_71;
+ wire [9:0] T_72;
+ wire [8:0] T_73;
+ wire held;
+ reg in_slow_rdy;
+ reg out_slow_val;
+ reg [16:0] out_slow_bits;
+ wire fromhost_q_clk;
+ wire fromhost_q_reset;
+ wire fromhost_q_io_enq_ready;
+ wire fromhost_q_io_enq_valid;
+ wire [16:0] fromhost_q_io_enq_bits;
+ wire fromhost_q_io_deq_ready;
+ wire fromhost_q_io_deq_valid;
+ wire [16:0] fromhost_q_io_deq_bits;
+ wire fromhost_q_io_count;
+ wire T_86;
+ wire T_87;
+ wire T_88;
+ wire tohost_q_clk;
+ wire tohost_q_reset;
+ wire tohost_q_io_enq_ready;
+ wire tohost_q_io_enq_valid;
+ wire [16:0] tohost_q_io_enq_bits;
+ wire tohost_q_io_deq_ready;
+ wire tohost_q_io_deq_valid;
+ wire [16:0] tohost_q_io_deq_bits;
+ wire tohost_q_io_count;
+ wire T_91;
+ wire T_92;
+ wire [16:0] T_93;
+ Queue_90 fromhost_q (
+ .clk(fromhost_q_clk),
+ .reset(fromhost_q_reset),
+ .io_enq_ready(fromhost_q_io_enq_ready),
+ .io_enq_valid(fromhost_q_io_enq_valid),
+ .io_enq_bits(fromhost_q_io_enq_bits),
+ .io_deq_ready(fromhost_q_io_deq_ready),
+ .io_deq_valid(fromhost_q_io_deq_valid),
+ .io_deq_bits(fromhost_q_io_deq_bits),
+ .io_count(fromhost_q_io_count)
+ );
+ Queue_90 tohost_q (
+ .clk(tohost_q_clk),
+ .reset(tohost_q_reset),
+ .io_enq_ready(tohost_q_io_enq_ready),
+ .io_enq_valid(tohost_q_io_enq_valid),
+ .io_enq_bits(tohost_q_io_enq_bits),
+ .io_deq_ready(tohost_q_io_deq_ready),
+ .io_deq_valid(tohost_q_io_deq_valid),
+ .io_deq_bits(tohost_q_io_deq_bits),
+ .io_count(tohost_q_io_count)
+ );
+ assign io_out_fast_ready = tohost_q_io_enq_ready;
+ assign io_out_slow_valid = out_slow_val;
+ assign io_out_slow_bits = out_slow_bits;
+ assign io_in_fast_valid = fromhost_q_io_deq_valid;
+ assign io_in_fast_bits = fromhost_q_io_deq_bits;
+ assign io_in_slow_ready = in_slow_rdy;
+ assign io_clk_slow = myclock;
+ assign io_divisor = T_60;
+ assign T_57 = io_set_divisor_bits[8:0];
+ assign T_58 = io_set_divisor_bits[24:16];
+ assign T_59 = hold << 16;
+ assign T_60 = T_59 | divisor;
+ assign T_66 = count + 1'h1;
+ assign T_67 = T_66[8:0];
+ assign T_68 = divisor[8:1];
+ assign rising = count == T_68;
+ assign falling = count == divisor;
+ assign T_71 = divisor[8:1];
+ assign T_72 = T_71 + hold;
+ assign T_73 = T_72[8:0];
+ assign held = count == T_73;
+ assign fromhost_q_clk = clk;
+ assign fromhost_q_reset = reset;
+ assign fromhost_q_io_enq_valid = T_88;
+ assign fromhost_q_io_enq_bits = io_in_slow_bits;
+ assign fromhost_q_io_deq_ready = io_in_fast_ready;
+ assign T_86 = io_in_slow_valid & in_slow_rdy;
+ assign T_87 = T_86 | reset;
+ assign T_88 = rising & T_87;
+ assign tohost_q_clk = clk;
+ assign tohost_q_reset = reset;
+ assign tohost_q_io_enq_valid = io_out_fast_valid;
+ assign tohost_q_io_enq_bits = io_out_fast_bits;
+ assign tohost_q_io_deq_ready = T_92;
+ assign T_91 = rising & io_out_slow_ready;
+ assign T_92 = T_91 & out_slow_val;
+ assign T_93 = reset ? fromhost_q_io_deq_bits : tohost_q_io_deq_bits;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ divisor = {1{$random}};
+ d_shadow = {1{$random}};
+ hold = {1{$random}};
+ h_shadow = {1{$random}};
+ count = {1{$random}};
+ myclock = {1{$random}};
+ in_slow_rdy = {1{$random}};
+ out_slow_val = {1{$random}};
+ out_slow_bits = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ divisor <= 9'h1ff;
+ end else begin
+ if(falling) begin
+ divisor <= d_shadow;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ d_shadow <= 9'h1ff;
+ end else begin
+ if(io_set_divisor_valid) begin
+ d_shadow <= T_57;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ hold <= 7'h7f;
+ end else begin
+ if(falling) begin
+ hold <= h_shadow;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ h_shadow <= 7'h7f;
+ end else begin
+ if(io_set_divisor_valid) begin
+ h_shadow <= T_58;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(falling) begin
+ count <= 1'h0;
+ end else begin
+ count <= T_67;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(rising) begin
+ myclock <= 1'h1;
+ end else begin
+ if(falling) begin
+ myclock <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ in_slow_rdy <= 1'h0;
+ end else begin
+ if(held) begin
+ in_slow_rdy <= fromhost_q_io_enq_ready;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ out_slow_val <= 1'h0;
+ end else begin
+ if(held) begin
+ out_slow_val <= tohost_q_io_deq_valid;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(held) begin
+ out_slow_bits <= T_93;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module Uncore(
+ input clk,
+ input reset,
+ output io_host_clk,
+ output io_host_clk_edge,
+ output io_host_in_ready,
+ input io_host_in_valid,
+ input [15:0] io_host_in_bits,
+ input io_host_out_ready,
+ output io_host_out_valid,
+ output [15:0] io_host_out_bits,
+ output io_host_debug_stats_csr,
+ input io_mem_0_aw_ready,
+ output io_mem_0_aw_valid,
+ output [31:0] io_mem_0_aw_bits_addr,
+ output [7:0] io_mem_0_aw_bits_len,
+ output [2:0] io_mem_0_aw_bits_size,
+ output [1:0] io_mem_0_aw_bits_burst,
+ output io_mem_0_aw_bits_lock,
+ output [3:0] io_mem_0_aw_bits_cache,
+ output [2:0] io_mem_0_aw_bits_prot,
+ output [3:0] io_mem_0_aw_bits_qos,
+ output [3:0] io_mem_0_aw_bits_region,
+ output [4:0] io_mem_0_aw_bits_id,
+ output io_mem_0_aw_bits_user,
+ input io_mem_0_w_ready,
+ output io_mem_0_w_valid,
+ output [63:0] io_mem_0_w_bits_data,
+ output io_mem_0_w_bits_last,
+ output [7:0] io_mem_0_w_bits_strb,
+ output io_mem_0_w_bits_user,
+ output io_mem_0_b_ready,
+ input io_mem_0_b_valid,
+ input [1:0] io_mem_0_b_bits_resp,
+ input [4:0] io_mem_0_b_bits_id,
+ input io_mem_0_b_bits_user,
+ input io_mem_0_ar_ready,
+ output io_mem_0_ar_valid,
+ output [31:0] io_mem_0_ar_bits_addr,
+ output [7:0] io_mem_0_ar_bits_len,
+ output [2:0] io_mem_0_ar_bits_size,
+ output [1:0] io_mem_0_ar_bits_burst,
+ output io_mem_0_ar_bits_lock,
+ output [3:0] io_mem_0_ar_bits_cache,
+ output [2:0] io_mem_0_ar_bits_prot,
+ output [3:0] io_mem_0_ar_bits_qos,
+ output [3:0] io_mem_0_ar_bits_region,
+ output [4:0] io_mem_0_ar_bits_id,
+ output io_mem_0_ar_bits_user,
+ output io_mem_0_r_ready,
+ input io_mem_0_r_valid,
+ input [1:0] io_mem_0_r_bits_resp,
+ input [63:0] io_mem_0_r_bits_data,
+ input io_mem_0_r_bits_last,
+ input [4:0] io_mem_0_r_bits_id,
+ input io_mem_0_r_bits_user,
+ output io_tiles_cached_0_acquire_ready,
+ input io_tiles_cached_0_acquire_valid,
+ input [25:0] io_tiles_cached_0_acquire_bits_addr_block,
+ input [1:0] io_tiles_cached_0_acquire_bits_client_xact_id,
+ input [1:0] io_tiles_cached_0_acquire_bits_addr_beat,
+ input io_tiles_cached_0_acquire_bits_is_builtin_type,
+ input [2:0] io_tiles_cached_0_acquire_bits_a_type,
+ input [16:0] io_tiles_cached_0_acquire_bits_union,
+ input [127:0] io_tiles_cached_0_acquire_bits_data,
+ input io_tiles_cached_0_grant_ready,
+ output io_tiles_cached_0_grant_valid,
+ output [1:0] io_tiles_cached_0_grant_bits_addr_beat,
+ output [1:0] io_tiles_cached_0_grant_bits_client_xact_id,
+ output [3:0] io_tiles_cached_0_grant_bits_manager_xact_id,
+ output io_tiles_cached_0_grant_bits_is_builtin_type,
+ output [3:0] io_tiles_cached_0_grant_bits_g_type,
+ output [127:0] io_tiles_cached_0_grant_bits_data,
+ input io_tiles_cached_0_probe_ready,
+ output io_tiles_cached_0_probe_valid,
+ output [25:0] io_tiles_cached_0_probe_bits_addr_block,
+ output [1:0] io_tiles_cached_0_probe_bits_p_type,
+ output io_tiles_cached_0_release_ready,
+ input io_tiles_cached_0_release_valid,
+ input [1:0] io_tiles_cached_0_release_bits_addr_beat,
+ input [25:0] io_tiles_cached_0_release_bits_addr_block,
+ input [1:0] io_tiles_cached_0_release_bits_client_xact_id,
+ input io_tiles_cached_0_release_bits_voluntary,
+ input [2:0] io_tiles_cached_0_release_bits_r_type,
+ input [127:0] io_tiles_cached_0_release_bits_data,
+ output io_tiles_uncached_0_acquire_ready,
+ input io_tiles_uncached_0_acquire_valid,
+ input [25:0] io_tiles_uncached_0_acquire_bits_addr_block,
+ input [1:0] io_tiles_uncached_0_acquire_bits_client_xact_id,
+ input [1:0] io_tiles_uncached_0_acquire_bits_addr_beat,
+ input io_tiles_uncached_0_acquire_bits_is_builtin_type,
+ input [2:0] io_tiles_uncached_0_acquire_bits_a_type,
+ input [16:0] io_tiles_uncached_0_acquire_bits_union,
+ input [127:0] io_tiles_uncached_0_acquire_bits_data,
+ input io_tiles_uncached_0_grant_ready,
+ output io_tiles_uncached_0_grant_valid,
+ output [1:0] io_tiles_uncached_0_grant_bits_addr_beat,
+ output [1:0] io_tiles_uncached_0_grant_bits_client_xact_id,
+ output [3:0] io_tiles_uncached_0_grant_bits_manager_xact_id,
+ output io_tiles_uncached_0_grant_bits_is_builtin_type,
+ output [3:0] io_tiles_uncached_0_grant_bits_g_type,
+ output [127:0] io_tiles_uncached_0_grant_bits_data,
+ output io_htif_0_reset,
+ output io_htif_0_id,
+ input io_htif_0_csr_req_ready,
+ output io_htif_0_csr_req_valid,
+ output io_htif_0_csr_req_bits_rw,
+ output [11:0] io_htif_0_csr_req_bits_addr,
+ output [63:0] io_htif_0_csr_req_bits_data,
+ output io_htif_0_csr_resp_ready,
+ input io_htif_0_csr_resp_valid,
+ input [63:0] io_htif_0_csr_resp_bits,
+ input io_htif_0_debug_stats_csr,
+ input io_mem_backup_ctrl_en,
+ input io_mem_backup_ctrl_in_valid,
+ input io_mem_backup_ctrl_out_ready,
+ output io_mem_backup_ctrl_out_valid,
+ input io_mmio_aw_ready,
+ output io_mmio_aw_valid,
+ output [31:0] io_mmio_aw_bits_addr,
+ output [7:0] io_mmio_aw_bits_len,
+ output [2:0] io_mmio_aw_bits_size,
+ output [1:0] io_mmio_aw_bits_burst,
+ output io_mmio_aw_bits_lock,
+ output [3:0] io_mmio_aw_bits_cache,
+ output [2:0] io_mmio_aw_bits_prot,
+ output [3:0] io_mmio_aw_bits_qos,
+ output [3:0] io_mmio_aw_bits_region,
+ output [4:0] io_mmio_aw_bits_id,
+ output io_mmio_aw_bits_user,
+ input io_mmio_w_ready,
+ output io_mmio_w_valid,
+ output [63:0] io_mmio_w_bits_data,
+ output io_mmio_w_bits_last,
+ output [7:0] io_mmio_w_bits_strb,
+ output io_mmio_w_bits_user,
+ output io_mmio_b_ready,
+ input io_mmio_b_valid,
+ input [1:0] io_mmio_b_bits_resp,
+ input [4:0] io_mmio_b_bits_id,
+ input io_mmio_b_bits_user,
+ input io_mmio_ar_ready,
+ output io_mmio_ar_valid,
+ output [31:0] io_mmio_ar_bits_addr,
+ output [7:0] io_mmio_ar_bits_len,
+ output [2:0] io_mmio_ar_bits_size,
+ output [1:0] io_mmio_ar_bits_burst,
+ output io_mmio_ar_bits_lock,
+ output [3:0] io_mmio_ar_bits_cache,
+ output [2:0] io_mmio_ar_bits_prot,
+ output [3:0] io_mmio_ar_bits_qos,
+ output [3:0] io_mmio_ar_bits_region,
+ output [4:0] io_mmio_ar_bits_id,
+ output io_mmio_ar_bits_user,
+ output io_mmio_r_ready,
+ input io_mmio_r_valid,
+ input [1:0] io_mmio_r_bits_resp,
+ input [63:0] io_mmio_r_bits_data,
+ input io_mmio_r_bits_last,
+ input [4:0] io_mmio_r_bits_id,
+ input io_mmio_r_bits_user,
+ output io_dma_0_req_ready,
+ input io_dma_0_req_valid,
+ input [1:0] io_dma_0_req_bits_client_xact_id,
+ input [2:0] io_dma_0_req_bits_cmd,
+ input [31:0] io_dma_0_req_bits_source,
+ input [31:0] io_dma_0_req_bits_dest,
+ input [31:0] io_dma_0_req_bits_length,
+ input [1:0] io_dma_0_req_bits_size,
+ input io_dma_0_resp_ready,
+ output io_dma_0_resp_valid,
+ output [1:0] io_dma_0_resp_bits_client_xact_id,
+ output [1:0] io_dma_0_resp_bits_status
+);
+ wire htif_clk;
+ wire htif_reset;
+ wire htif_io_host_clk;
+ wire htif_io_host_clk_edge;
+ wire htif_io_host_in_ready;
+ wire htif_io_host_in_valid;
+ wire [15:0] htif_io_host_in_bits;
+ wire htif_io_host_out_ready;
+ wire htif_io_host_out_valid;
+ wire [15:0] htif_io_host_out_bits;
+ wire htif_io_host_debug_stats_csr;
+ wire htif_io_cpu_0_reset;
+ wire htif_io_cpu_0_id;
+ wire htif_io_cpu_0_csr_req_ready;
+ wire htif_io_cpu_0_csr_req_valid;
+ wire htif_io_cpu_0_csr_req_bits_rw;
+ wire [11:0] htif_io_cpu_0_csr_req_bits_addr;
+ wire [63:0] htif_io_cpu_0_csr_req_bits_data;
+ wire htif_io_cpu_0_csr_resp_ready;
+ wire htif_io_cpu_0_csr_resp_valid;
+ wire [63:0] htif_io_cpu_0_csr_resp_bits;
+ wire htif_io_cpu_0_debug_stats_csr;
+ wire htif_io_mem_acquire_ready;
+ wire htif_io_mem_acquire_valid;
+ wire [25:0] htif_io_mem_acquire_bits_addr_block;
+ wire [1:0] htif_io_mem_acquire_bits_client_xact_id;
+ wire [1:0] htif_io_mem_acquire_bits_addr_beat;
+ wire htif_io_mem_acquire_bits_is_builtin_type;
+ wire [2:0] htif_io_mem_acquire_bits_a_type;
+ wire [16:0] htif_io_mem_acquire_bits_union;
+ wire [127:0] htif_io_mem_acquire_bits_data;
+ wire htif_io_mem_grant_ready;
+ wire htif_io_mem_grant_valid;
+ wire [1:0] htif_io_mem_grant_bits_addr_beat;
+ wire [1:0] htif_io_mem_grant_bits_client_xact_id;
+ wire [3:0] htif_io_mem_grant_bits_manager_xact_id;
+ wire htif_io_mem_grant_bits_is_builtin_type;
+ wire [3:0] htif_io_mem_grant_bits_g_type;
+ wire [127:0] htif_io_mem_grant_bits_data;
+ wire htif_io_scr_req_ready;
+ wire htif_io_scr_req_valid;
+ wire htif_io_scr_req_bits_rw;
+ wire [5:0] htif_io_scr_req_bits_addr;
+ wire [63:0] htif_io_scr_req_bits_data;
+ wire htif_io_scr_resp_ready;
+ wire htif_io_scr_resp_valid;
+ wire [63:0] htif_io_scr_resp_bits;
+ wire outmemsys_clk;
+ wire outmemsys_reset;
+ wire outmemsys_io_tiles_cached_0_acquire_ready;
+ wire outmemsys_io_tiles_cached_0_acquire_valid;
+ wire [25:0] outmemsys_io_tiles_cached_0_acquire_bits_addr_block;
+ wire [1:0] outmemsys_io_tiles_cached_0_acquire_bits_client_xact_id;
+ wire [1:0] outmemsys_io_tiles_cached_0_acquire_bits_addr_beat;
+ wire outmemsys_io_tiles_cached_0_acquire_bits_is_builtin_type;
+ wire [2:0] outmemsys_io_tiles_cached_0_acquire_bits_a_type;
+ wire [16:0] outmemsys_io_tiles_cached_0_acquire_bits_union;
+ wire [127:0] outmemsys_io_tiles_cached_0_acquire_bits_data;
+ wire outmemsys_io_tiles_cached_0_grant_ready;
+ wire outmemsys_io_tiles_cached_0_grant_valid;
+ wire [1:0] outmemsys_io_tiles_cached_0_grant_bits_addr_beat;
+ wire [1:0] outmemsys_io_tiles_cached_0_grant_bits_client_xact_id;
+ wire [3:0] outmemsys_io_tiles_cached_0_grant_bits_manager_xact_id;
+ wire outmemsys_io_tiles_cached_0_grant_bits_is_builtin_type;
+ wire [3:0] outmemsys_io_tiles_cached_0_grant_bits_g_type;
+ wire [127:0] outmemsys_io_tiles_cached_0_grant_bits_data;
+ wire outmemsys_io_tiles_cached_0_probe_ready;
+ wire outmemsys_io_tiles_cached_0_probe_valid;
+ wire [25:0] outmemsys_io_tiles_cached_0_probe_bits_addr_block;
+ wire [1:0] outmemsys_io_tiles_cached_0_probe_bits_p_type;
+ wire outmemsys_io_tiles_cached_0_release_ready;
+ wire outmemsys_io_tiles_cached_0_release_valid;
+ wire [1:0] outmemsys_io_tiles_cached_0_release_bits_addr_beat;
+ wire [25:0] outmemsys_io_tiles_cached_0_release_bits_addr_block;
+ wire [1:0] outmemsys_io_tiles_cached_0_release_bits_client_xact_id;
+ wire outmemsys_io_tiles_cached_0_release_bits_voluntary;
+ wire [2:0] outmemsys_io_tiles_cached_0_release_bits_r_type;
+ wire [127:0] outmemsys_io_tiles_cached_0_release_bits_data;
+ wire outmemsys_io_tiles_uncached_0_acquire_ready;
+ wire outmemsys_io_tiles_uncached_0_acquire_valid;
+ wire [25:0] outmemsys_io_tiles_uncached_0_acquire_bits_addr_block;
+ wire [1:0] outmemsys_io_tiles_uncached_0_acquire_bits_client_xact_id;
+ wire [1:0] outmemsys_io_tiles_uncached_0_acquire_bits_addr_beat;
+ wire outmemsys_io_tiles_uncached_0_acquire_bits_is_builtin_type;
+ wire [2:0] outmemsys_io_tiles_uncached_0_acquire_bits_a_type;
+ wire [16:0] outmemsys_io_tiles_uncached_0_acquire_bits_union;
+ wire [127:0] outmemsys_io_tiles_uncached_0_acquire_bits_data;
+ wire outmemsys_io_tiles_uncached_0_grant_ready;
+ wire outmemsys_io_tiles_uncached_0_grant_valid;
+ wire [1:0] outmemsys_io_tiles_uncached_0_grant_bits_addr_beat;
+ wire [1:0] outmemsys_io_tiles_uncached_0_grant_bits_client_xact_id;
+ wire [3:0] outmemsys_io_tiles_uncached_0_grant_bits_manager_xact_id;
+ wire outmemsys_io_tiles_uncached_0_grant_bits_is_builtin_type;
+ wire [3:0] outmemsys_io_tiles_uncached_0_grant_bits_g_type;
+ wire [127:0] outmemsys_io_tiles_uncached_0_grant_bits_data;
+ wire outmemsys_io_htif_uncached_acquire_ready;
+ wire outmemsys_io_htif_uncached_acquire_valid;
+ wire [25:0] outmemsys_io_htif_uncached_acquire_bits_addr_block;
+ wire [1:0] outmemsys_io_htif_uncached_acquire_bits_client_xact_id;
+ wire [1:0] outmemsys_io_htif_uncached_acquire_bits_addr_beat;
+ wire outmemsys_io_htif_uncached_acquire_bits_is_builtin_type;
+ wire [2:0] outmemsys_io_htif_uncached_acquire_bits_a_type;
+ wire [16:0] outmemsys_io_htif_uncached_acquire_bits_union;
+ wire [127:0] outmemsys_io_htif_uncached_acquire_bits_data;
+ wire outmemsys_io_htif_uncached_grant_ready;
+ wire outmemsys_io_htif_uncached_grant_valid;
+ wire [1:0] outmemsys_io_htif_uncached_grant_bits_addr_beat;
+ wire [1:0] outmemsys_io_htif_uncached_grant_bits_client_xact_id;
+ wire [3:0] outmemsys_io_htif_uncached_grant_bits_manager_xact_id;
+ wire outmemsys_io_htif_uncached_grant_bits_is_builtin_type;
+ wire [3:0] outmemsys_io_htif_uncached_grant_bits_g_type;
+ wire [127:0] outmemsys_io_htif_uncached_grant_bits_data;
+ wire outmemsys_io_incoherent_0;
+ wire outmemsys_io_mem_0_aw_ready;
+ wire outmemsys_io_mem_0_aw_valid;
+ wire [31:0] outmemsys_io_mem_0_aw_bits_addr;
+ wire [7:0] outmemsys_io_mem_0_aw_bits_len;
+ wire [2:0] outmemsys_io_mem_0_aw_bits_size;
+ wire [1:0] outmemsys_io_mem_0_aw_bits_burst;
+ wire outmemsys_io_mem_0_aw_bits_lock;
+ wire [3:0] outmemsys_io_mem_0_aw_bits_cache;
+ wire [2:0] outmemsys_io_mem_0_aw_bits_prot;
+ wire [3:0] outmemsys_io_mem_0_aw_bits_qos;
+ wire [3:0] outmemsys_io_mem_0_aw_bits_region;
+ wire [4:0] outmemsys_io_mem_0_aw_bits_id;
+ wire outmemsys_io_mem_0_aw_bits_user;
+ wire outmemsys_io_mem_0_w_ready;
+ wire outmemsys_io_mem_0_w_valid;
+ wire [63:0] outmemsys_io_mem_0_w_bits_data;
+ wire outmemsys_io_mem_0_w_bits_last;
+ wire [7:0] outmemsys_io_mem_0_w_bits_strb;
+ wire outmemsys_io_mem_0_w_bits_user;
+ wire outmemsys_io_mem_0_b_ready;
+ wire outmemsys_io_mem_0_b_valid;
+ wire [1:0] outmemsys_io_mem_0_b_bits_resp;
+ wire [4:0] outmemsys_io_mem_0_b_bits_id;
+ wire outmemsys_io_mem_0_b_bits_user;
+ wire outmemsys_io_mem_0_ar_ready;
+ wire outmemsys_io_mem_0_ar_valid;
+ wire [31:0] outmemsys_io_mem_0_ar_bits_addr;
+ wire [7:0] outmemsys_io_mem_0_ar_bits_len;
+ wire [2:0] outmemsys_io_mem_0_ar_bits_size;
+ wire [1:0] outmemsys_io_mem_0_ar_bits_burst;
+ wire outmemsys_io_mem_0_ar_bits_lock;
+ wire [3:0] outmemsys_io_mem_0_ar_bits_cache;
+ wire [2:0] outmemsys_io_mem_0_ar_bits_prot;
+ wire [3:0] outmemsys_io_mem_0_ar_bits_qos;
+ wire [3:0] outmemsys_io_mem_0_ar_bits_region;
+ wire [4:0] outmemsys_io_mem_0_ar_bits_id;
+ wire outmemsys_io_mem_0_ar_bits_user;
+ wire outmemsys_io_mem_0_r_ready;
+ wire outmemsys_io_mem_0_r_valid;
+ wire [1:0] outmemsys_io_mem_0_r_bits_resp;
+ wire [63:0] outmemsys_io_mem_0_r_bits_data;
+ wire outmemsys_io_mem_0_r_bits_last;
+ wire [4:0] outmemsys_io_mem_0_r_bits_id;
+ wire outmemsys_io_mem_0_r_bits_user;
+ wire outmemsys_io_mem_backup_req_ready;
+ wire outmemsys_io_mem_backup_req_valid;
+ wire [15:0] outmemsys_io_mem_backup_req_bits;
+ wire outmemsys_io_mem_backup_resp_valid;
+ wire [15:0] outmemsys_io_mem_backup_resp_bits;
+ wire outmemsys_io_mem_backup_en;
+ wire outmemsys_io_csr_0_req_ready;
+ wire outmemsys_io_csr_0_req_valid;
+ wire outmemsys_io_csr_0_req_bits_rw;
+ wire [11:0] outmemsys_io_csr_0_req_bits_addr;
+ wire [63:0] outmemsys_io_csr_0_req_bits_data;
+ wire outmemsys_io_csr_0_resp_ready;
+ wire outmemsys_io_csr_0_resp_valid;
+ wire [63:0] outmemsys_io_csr_0_resp_bits;
+ wire outmemsys_io_scr_req_ready;
+ wire outmemsys_io_scr_req_valid;
+ wire outmemsys_io_scr_req_bits_rw;
+ wire [5:0] outmemsys_io_scr_req_bits_addr;
+ wire [63:0] outmemsys_io_scr_req_bits_data;
+ wire outmemsys_io_scr_resp_ready;
+ wire outmemsys_io_scr_resp_valid;
+ wire [63:0] outmemsys_io_scr_resp_bits;
+ wire outmemsys_io_mmio_aw_ready;
+ wire outmemsys_io_mmio_aw_valid;
+ wire [31:0] outmemsys_io_mmio_aw_bits_addr;
+ wire [7:0] outmemsys_io_mmio_aw_bits_len;
+ wire [2:0] outmemsys_io_mmio_aw_bits_size;
+ wire [1:0] outmemsys_io_mmio_aw_bits_burst;
+ wire outmemsys_io_mmio_aw_bits_lock;
+ wire [3:0] outmemsys_io_mmio_aw_bits_cache;
+ wire [2:0] outmemsys_io_mmio_aw_bits_prot;
+ wire [3:0] outmemsys_io_mmio_aw_bits_qos;
+ wire [3:0] outmemsys_io_mmio_aw_bits_region;
+ wire [4:0] outmemsys_io_mmio_aw_bits_id;
+ wire outmemsys_io_mmio_aw_bits_user;
+ wire outmemsys_io_mmio_w_ready;
+ wire outmemsys_io_mmio_w_valid;
+ wire [63:0] outmemsys_io_mmio_w_bits_data;
+ wire outmemsys_io_mmio_w_bits_last;
+ wire [7:0] outmemsys_io_mmio_w_bits_strb;
+ wire outmemsys_io_mmio_w_bits_user;
+ wire outmemsys_io_mmio_b_ready;
+ wire outmemsys_io_mmio_b_valid;
+ wire [1:0] outmemsys_io_mmio_b_bits_resp;
+ wire [4:0] outmemsys_io_mmio_b_bits_id;
+ wire outmemsys_io_mmio_b_bits_user;
+ wire outmemsys_io_mmio_ar_ready;
+ wire outmemsys_io_mmio_ar_valid;
+ wire [31:0] outmemsys_io_mmio_ar_bits_addr;
+ wire [7:0] outmemsys_io_mmio_ar_bits_len;
+ wire [2:0] outmemsys_io_mmio_ar_bits_size;
+ wire [1:0] outmemsys_io_mmio_ar_bits_burst;
+ wire outmemsys_io_mmio_ar_bits_lock;
+ wire [3:0] outmemsys_io_mmio_ar_bits_cache;
+ wire [2:0] outmemsys_io_mmio_ar_bits_prot;
+ wire [3:0] outmemsys_io_mmio_ar_bits_qos;
+ wire [3:0] outmemsys_io_mmio_ar_bits_region;
+ wire [4:0] outmemsys_io_mmio_ar_bits_id;
+ wire outmemsys_io_mmio_ar_bits_user;
+ wire outmemsys_io_mmio_r_ready;
+ wire outmemsys_io_mmio_r_valid;
+ wire [1:0] outmemsys_io_mmio_r_bits_resp;
+ wire [63:0] outmemsys_io_mmio_r_bits_data;
+ wire outmemsys_io_mmio_r_bits_last;
+ wire [4:0] outmemsys_io_mmio_r_bits_id;
+ wire outmemsys_io_mmio_r_bits_user;
+ wire outmemsys_io_deviceTree_aw_ready;
+ wire outmemsys_io_deviceTree_aw_valid;
+ wire [31:0] outmemsys_io_deviceTree_aw_bits_addr;
+ wire [7:0] outmemsys_io_deviceTree_aw_bits_len;
+ wire [2:0] outmemsys_io_deviceTree_aw_bits_size;
+ wire [1:0] outmemsys_io_deviceTree_aw_bits_burst;
+ wire outmemsys_io_deviceTree_aw_bits_lock;
+ wire [3:0] outmemsys_io_deviceTree_aw_bits_cache;
+ wire [2:0] outmemsys_io_deviceTree_aw_bits_prot;
+ wire [3:0] outmemsys_io_deviceTree_aw_bits_qos;
+ wire [3:0] outmemsys_io_deviceTree_aw_bits_region;
+ wire [4:0] outmemsys_io_deviceTree_aw_bits_id;
+ wire outmemsys_io_deviceTree_aw_bits_user;
+ wire outmemsys_io_deviceTree_w_ready;
+ wire outmemsys_io_deviceTree_w_valid;
+ wire [63:0] outmemsys_io_deviceTree_w_bits_data;
+ wire outmemsys_io_deviceTree_w_bits_last;
+ wire [7:0] outmemsys_io_deviceTree_w_bits_strb;
+ wire outmemsys_io_deviceTree_w_bits_user;
+ wire outmemsys_io_deviceTree_b_ready;
+ wire outmemsys_io_deviceTree_b_valid;
+ wire [1:0] outmemsys_io_deviceTree_b_bits_resp;
+ wire [4:0] outmemsys_io_deviceTree_b_bits_id;
+ wire outmemsys_io_deviceTree_b_bits_user;
+ wire outmemsys_io_deviceTree_ar_ready;
+ wire outmemsys_io_deviceTree_ar_valid;
+ wire [31:0] outmemsys_io_deviceTree_ar_bits_addr;
+ wire [7:0] outmemsys_io_deviceTree_ar_bits_len;
+ wire [2:0] outmemsys_io_deviceTree_ar_bits_size;
+ wire [1:0] outmemsys_io_deviceTree_ar_bits_burst;
+ wire outmemsys_io_deviceTree_ar_bits_lock;
+ wire [3:0] outmemsys_io_deviceTree_ar_bits_cache;
+ wire [2:0] outmemsys_io_deviceTree_ar_bits_prot;
+ wire [3:0] outmemsys_io_deviceTree_ar_bits_qos;
+ wire [3:0] outmemsys_io_deviceTree_ar_bits_region;
+ wire [4:0] outmemsys_io_deviceTree_ar_bits_id;
+ wire outmemsys_io_deviceTree_ar_bits_user;
+ wire outmemsys_io_deviceTree_r_ready;
+ wire outmemsys_io_deviceTree_r_valid;
+ wire [1:0] outmemsys_io_deviceTree_r_bits_resp;
+ wire [63:0] outmemsys_io_deviceTree_r_bits_data;
+ wire outmemsys_io_deviceTree_r_bits_last;
+ wire [4:0] outmemsys_io_deviceTree_r_bits_id;
+ wire outmemsys_io_deviceTree_r_bits_user;
+ wire outmemsys_io_dma_req_ready;
+ wire outmemsys_io_dma_req_valid;
+ wire [1:0] outmemsys_io_dma_req_bits_client_xact_id;
+ wire [2:0] outmemsys_io_dma_req_bits_cmd;
+ wire [31:0] outmemsys_io_dma_req_bits_source;
+ wire [31:0] outmemsys_io_dma_req_bits_dest;
+ wire [31:0] outmemsys_io_dma_req_bits_length;
+ wire [1:0] outmemsys_io_dma_req_bits_size;
+ wire outmemsys_io_dma_resp_ready;
+ wire outmemsys_io_dma_resp_valid;
+ wire [1:0] outmemsys_io_dma_resp_bits_client_xact_id;
+ wire [1:0] outmemsys_io_dma_resp_bits_status;
+ wire T_8362_clk;
+ wire T_8362_reset;
+ wire T_8362_io_in_0_req_ready;
+ wire T_8362_io_in_0_req_valid;
+ wire T_8362_io_in_0_req_bits_rw;
+ wire [11:0] T_8362_io_in_0_req_bits_addr;
+ wire [63:0] T_8362_io_in_0_req_bits_data;
+ wire T_8362_io_in_0_resp_ready;
+ wire T_8362_io_in_0_resp_valid;
+ wire [63:0] T_8362_io_in_0_resp_bits;
+ wire T_8362_io_in_1_req_ready;
+ wire T_8362_io_in_1_req_valid;
+ wire T_8362_io_in_1_req_bits_rw;
+ wire [11:0] T_8362_io_in_1_req_bits_addr;
+ wire [63:0] T_8362_io_in_1_req_bits_data;
+ wire T_8362_io_in_1_resp_ready;
+ wire T_8362_io_in_1_resp_valid;
+ wire [63:0] T_8362_io_in_1_resp_bits;
+ wire T_8362_io_out_req_ready;
+ wire T_8362_io_out_req_valid;
+ wire T_8362_io_out_req_bits_rw;
+ wire [11:0] T_8362_io_out_req_bits_addr;
+ wire [63:0] T_8362_io_out_req_bits_data;
+ wire T_8362_io_out_resp_ready;
+ wire T_8362_io_out_resp_valid;
+ wire [63:0] T_8362_io_out_resp_bits;
+ wire scrFile_clk;
+ wire scrFile_reset;
+ wire scrFile_io_smi_req_ready;
+ wire scrFile_io_smi_req_valid;
+ wire scrFile_io_smi_req_bits_rw;
+ wire [5:0] scrFile_io_smi_req_bits_addr;
+ wire [63:0] scrFile_io_smi_req_bits_data;
+ wire scrFile_io_smi_resp_ready;
+ wire scrFile_io_smi_resp_valid;
+ wire [63:0] scrFile_io_smi_resp_bits;
+ wire [63:0] scrFile_io_scr_rdata_0;
+ wire [63:0] scrFile_io_scr_rdata_1;
+ wire [63:0] scrFile_io_scr_rdata_2;
+ wire [63:0] scrFile_io_scr_rdata_3;
+ wire [63:0] scrFile_io_scr_rdata_4;
+ wire [63:0] scrFile_io_scr_rdata_5;
+ wire [63:0] scrFile_io_scr_rdata_6;
+ wire [63:0] scrFile_io_scr_rdata_7;
+ wire [63:0] scrFile_io_scr_rdata_8;
+ wire [63:0] scrFile_io_scr_rdata_9;
+ wire [63:0] scrFile_io_scr_rdata_10;
+ wire [63:0] scrFile_io_scr_rdata_11;
+ wire [63:0] scrFile_io_scr_rdata_12;
+ wire [63:0] scrFile_io_scr_rdata_13;
+ wire [63:0] scrFile_io_scr_rdata_14;
+ wire [63:0] scrFile_io_scr_rdata_15;
+ wire [63:0] scrFile_io_scr_rdata_16;
+ wire [63:0] scrFile_io_scr_rdata_17;
+ wire [63:0] scrFile_io_scr_rdata_18;
+ wire [63:0] scrFile_io_scr_rdata_19;
+ wire [63:0] scrFile_io_scr_rdata_20;
+ wire [63:0] scrFile_io_scr_rdata_21;
+ wire [63:0] scrFile_io_scr_rdata_22;
+ wire [63:0] scrFile_io_scr_rdata_23;
+ wire [63:0] scrFile_io_scr_rdata_24;
+ wire [63:0] scrFile_io_scr_rdata_25;
+ wire [63:0] scrFile_io_scr_rdata_26;
+ wire [63:0] scrFile_io_scr_rdata_27;
+ wire [63:0] scrFile_io_scr_rdata_28;
+ wire [63:0] scrFile_io_scr_rdata_29;
+ wire [63:0] scrFile_io_scr_rdata_30;
+ wire [63:0] scrFile_io_scr_rdata_31;
+ wire [63:0] scrFile_io_scr_rdata_32;
+ wire [63:0] scrFile_io_scr_rdata_33;
+ wire [63:0] scrFile_io_scr_rdata_34;
+ wire [63:0] scrFile_io_scr_rdata_35;
+ wire [63:0] scrFile_io_scr_rdata_36;
+ wire [63:0] scrFile_io_scr_rdata_37;
+ wire [63:0] scrFile_io_scr_rdata_38;
+ wire [63:0] scrFile_io_scr_rdata_39;
+ wire [63:0] scrFile_io_scr_rdata_40;
+ wire [63:0] scrFile_io_scr_rdata_41;
+ wire [63:0] scrFile_io_scr_rdata_42;
+ wire [63:0] scrFile_io_scr_rdata_43;
+ wire [63:0] scrFile_io_scr_rdata_44;
+ wire [63:0] scrFile_io_scr_rdata_45;
+ wire [63:0] scrFile_io_scr_rdata_46;
+ wire [63:0] scrFile_io_scr_rdata_47;
+ wire [63:0] scrFile_io_scr_rdata_48;
+ wire [63:0] scrFile_io_scr_rdata_49;
+ wire [63:0] scrFile_io_scr_rdata_50;
+ wire [63:0] scrFile_io_scr_rdata_51;
+ wire [63:0] scrFile_io_scr_rdata_52;
+ wire [63:0] scrFile_io_scr_rdata_53;
+ wire [63:0] scrFile_io_scr_rdata_54;
+ wire [63:0] scrFile_io_scr_rdata_55;
+ wire [63:0] scrFile_io_scr_rdata_56;
+ wire [63:0] scrFile_io_scr_rdata_57;
+ wire [63:0] scrFile_io_scr_rdata_58;
+ wire [63:0] scrFile_io_scr_rdata_59;
+ wire [63:0] scrFile_io_scr_rdata_60;
+ wire [63:0] scrFile_io_scr_rdata_61;
+ wire [63:0] scrFile_io_scr_rdata_62;
+ wire [63:0] scrFile_io_scr_rdata_63;
+ wire scrFile_io_scr_wen;
+ wire [5:0] scrFile_io_scr_waddr;
+ wire [63:0] scrFile_io_scr_wdata;
+ wire scrArb_clk;
+ wire scrArb_reset;
+ wire scrArb_io_in_0_req_ready;
+ wire scrArb_io_in_0_req_valid;
+ wire scrArb_io_in_0_req_bits_rw;
+ wire [5:0] scrArb_io_in_0_req_bits_addr;
+ wire [63:0] scrArb_io_in_0_req_bits_data;
+ wire scrArb_io_in_0_resp_ready;
+ wire scrArb_io_in_0_resp_valid;
+ wire [63:0] scrArb_io_in_0_resp_bits;
+ wire scrArb_io_in_1_req_ready;
+ wire scrArb_io_in_1_req_valid;
+ wire scrArb_io_in_1_req_bits_rw;
+ wire [5:0] scrArb_io_in_1_req_bits_addr;
+ wire [63:0] scrArb_io_in_1_req_bits_data;
+ wire scrArb_io_in_1_resp_ready;
+ wire scrArb_io_in_1_resp_valid;
+ wire [63:0] scrArb_io_in_1_resp_bits;
+ wire scrArb_io_out_req_ready;
+ wire scrArb_io_out_req_valid;
+ wire scrArb_io_out_req_bits_rw;
+ wire [5:0] scrArb_io_out_req_bits_addr;
+ wire [63:0] scrArb_io_out_req_bits_data;
+ wire scrArb_io_out_resp_ready;
+ wire scrArb_io_out_resp_valid;
+ wire [63:0] scrArb_io_out_resp_bits;
+ wire deviceTree_clk;
+ wire deviceTree_reset;
+ wire deviceTree_io_aw_ready;
+ wire deviceTree_io_aw_valid;
+ wire [31:0] deviceTree_io_aw_bits_addr;
+ wire [7:0] deviceTree_io_aw_bits_len;
+ wire [2:0] deviceTree_io_aw_bits_size;
+ wire [1:0] deviceTree_io_aw_bits_burst;
+ wire deviceTree_io_aw_bits_lock;
+ wire [3:0] deviceTree_io_aw_bits_cache;
+ wire [2:0] deviceTree_io_aw_bits_prot;
+ wire [3:0] deviceTree_io_aw_bits_qos;
+ wire [3:0] deviceTree_io_aw_bits_region;
+ wire [4:0] deviceTree_io_aw_bits_id;
+ wire deviceTree_io_aw_bits_user;
+ wire deviceTree_io_w_ready;
+ wire deviceTree_io_w_valid;
+ wire [63:0] deviceTree_io_w_bits_data;
+ wire deviceTree_io_w_bits_last;
+ wire [7:0] deviceTree_io_w_bits_strb;
+ wire deviceTree_io_w_bits_user;
+ wire deviceTree_io_b_ready;
+ wire deviceTree_io_b_valid;
+ wire [1:0] deviceTree_io_b_bits_resp;
+ wire [4:0] deviceTree_io_b_bits_id;
+ wire deviceTree_io_b_bits_user;
+ wire deviceTree_io_ar_ready;
+ wire deviceTree_io_ar_valid;
+ wire [31:0] deviceTree_io_ar_bits_addr;
+ wire [7:0] deviceTree_io_ar_bits_len;
+ wire [2:0] deviceTree_io_ar_bits_size;
+ wire [1:0] deviceTree_io_ar_bits_burst;
+ wire deviceTree_io_ar_bits_lock;
+ wire [3:0] deviceTree_io_ar_bits_cache;
+ wire [2:0] deviceTree_io_ar_bits_prot;
+ wire [3:0] deviceTree_io_ar_bits_qos;
+ wire [3:0] deviceTree_io_ar_bits_region;
+ wire [4:0] deviceTree_io_ar_bits_id;
+ wire deviceTree_io_ar_bits_user;
+ wire deviceTree_io_r_ready;
+ wire deviceTree_io_r_valid;
+ wire [1:0] deviceTree_io_r_bits_resp;
+ wire [63:0] deviceTree_io_r_bits_data;
+ wire deviceTree_io_r_bits_last;
+ wire [4:0] deviceTree_io_r_bits_id;
+ wire deviceTree_io_r_bits_user;
+ wire T_8366_clk;
+ wire T_8366_reset;
+ wire T_8366_io_out_fast_ready;
+ wire T_8366_io_out_fast_valid;
+ wire [16:0] T_8366_io_out_fast_bits;
+ wire T_8366_io_out_slow_ready;
+ wire T_8366_io_out_slow_valid;
+ wire [16:0] T_8366_io_out_slow_bits;
+ wire T_8366_io_in_fast_ready;
+ wire T_8366_io_in_fast_valid;
+ wire [16:0] T_8366_io_in_fast_bits;
+ wire T_8366_io_in_slow_ready;
+ wire T_8366_io_in_slow_valid;
+ wire [16:0] T_8366_io_in_slow_bits;
+ wire T_8366_io_clk_slow;
+ wire T_8366_io_set_divisor_valid;
+ wire [31:0] T_8366_io_set_divisor_bits;
+ wire [31:0] T_8366_io_divisor;
+ wire T_8368;
+ wire T_8369;
+ wire T_8370;
+ wire [15:0] T_8371;
+ wire [16:0] T_8372;
+ wire T_8374;
+ wire T_8375;
+ wire T_8376;
+ wire T_8377;
+ wire T_8378;
+ wire T_8380;
+ wire T_8381;
+ wire T_8382;
+ wire T_8383;
+ wire T_8384;
+ wire T_8385;
+ wire [16:0] T_8386;
+ wire T_8387;
+ wire T_8388;
+ wire T_8389;
+ wire T_8391;
+ wire T_8392;
+ wire T_8393;
+ wire T_8395;
+ reg T_8396;
+ wire T_8398;
+ wire T_8399;
+ reg T_8400;
+ reg GEN_0;
+ reg [1:0] GEN_1;
+ reg [2:0] GEN_2;
+ reg [31:0] GEN_3;
+ reg [31:0] GEN_4;
+ reg [31:0] GEN_5;
+ reg [1:0] GEN_6;
+ reg GEN_7;
+ reg [63:0] GEN_8;
+ reg [63:0] GEN_9;
+ reg [63:0] GEN_10;
+ reg [63:0] GEN_11;
+ reg [63:0] GEN_12;
+ reg [63:0] GEN_13;
+ reg [63:0] GEN_14;
+ reg [63:0] GEN_15;
+ reg [63:0] GEN_16;
+ reg [63:0] GEN_17;
+ reg [63:0] GEN_18;
+ reg [63:0] GEN_19;
+ reg [63:0] GEN_20;
+ reg [63:0] GEN_21;
+ reg [63:0] GEN_22;
+ reg [63:0] GEN_23;
+ reg [63:0] GEN_24;
+ reg [63:0] GEN_25;
+ reg [63:0] GEN_26;
+ reg [63:0] GEN_27;
+ reg [63:0] GEN_28;
+ reg [63:0] GEN_29;
+ reg [63:0] GEN_30;
+ reg [63:0] GEN_31;
+ reg [63:0] GEN_32;
+ reg [63:0] GEN_33;
+ reg [63:0] GEN_34;
+ reg [63:0] GEN_35;
+ reg [63:0] GEN_36;
+ reg [63:0] GEN_37;
+ reg [63:0] GEN_38;
+ reg [63:0] GEN_39;
+ reg [63:0] GEN_40;
+ reg [63:0] GEN_41;
+ reg [63:0] GEN_42;
+ reg [63:0] GEN_43;
+ reg [63:0] GEN_44;
+ reg [63:0] GEN_45;
+ reg [63:0] GEN_46;
+ reg [63:0] GEN_47;
+ reg [63:0] GEN_48;
+ reg [63:0] GEN_49;
+ reg [63:0] GEN_50;
+ reg [63:0] GEN_51;
+ reg [63:0] GEN_52;
+ reg [63:0] GEN_53;
+ reg [63:0] GEN_54;
+ reg [63:0] GEN_55;
+ reg [63:0] GEN_56;
+ reg [63:0] GEN_57;
+ reg [63:0] GEN_58;
+ reg [63:0] GEN_59;
+ reg [63:0] GEN_60;
+ reg [63:0] GEN_61;
+ reg [63:0] GEN_62;
+ reg [63:0] GEN_63;
+ reg [63:0] GEN_64;
+ reg [63:0] GEN_65;
+ reg [63:0] GEN_66;
+ reg [63:0] GEN_67;
+ reg [63:0] GEN_68;
+ reg [63:0] GEN_69;
+ reg [63:0] GEN_70;
+ reg GEN_71;
+ reg GEN_72;
+ reg [1:0] GEN_73;
+ reg [1:0] GEN_74;
+ Htif htif (
+ .clk(htif_clk),
+ .reset(htif_reset),
+ .io_host_clk(htif_io_host_clk),
+ .io_host_clk_edge(htif_io_host_clk_edge),
+ .io_host_in_ready(htif_io_host_in_ready),
+ .io_host_in_valid(htif_io_host_in_valid),
+ .io_host_in_bits(htif_io_host_in_bits),
+ .io_host_out_ready(htif_io_host_out_ready),
+ .io_host_out_valid(htif_io_host_out_valid),
+ .io_host_out_bits(htif_io_host_out_bits),
+ .io_host_debug_stats_csr(htif_io_host_debug_stats_csr),
+ .io_cpu_0_reset(htif_io_cpu_0_reset),
+ .io_cpu_0_id(htif_io_cpu_0_id),
+ .io_cpu_0_csr_req_ready(htif_io_cpu_0_csr_req_ready),
+ .io_cpu_0_csr_req_valid(htif_io_cpu_0_csr_req_valid),
+ .io_cpu_0_csr_req_bits_rw(htif_io_cpu_0_csr_req_bits_rw),
+ .io_cpu_0_csr_req_bits_addr(htif_io_cpu_0_csr_req_bits_addr),
+ .io_cpu_0_csr_req_bits_data(htif_io_cpu_0_csr_req_bits_data),
+ .io_cpu_0_csr_resp_ready(htif_io_cpu_0_csr_resp_ready),
+ .io_cpu_0_csr_resp_valid(htif_io_cpu_0_csr_resp_valid),
+ .io_cpu_0_csr_resp_bits(htif_io_cpu_0_csr_resp_bits),
+ .io_cpu_0_debug_stats_csr(htif_io_cpu_0_debug_stats_csr),
+ .io_mem_acquire_ready(htif_io_mem_acquire_ready),
+ .io_mem_acquire_valid(htif_io_mem_acquire_valid),
+ .io_mem_acquire_bits_addr_block(htif_io_mem_acquire_bits_addr_block),
+ .io_mem_acquire_bits_client_xact_id(htif_io_mem_acquire_bits_client_xact_id),
+ .io_mem_acquire_bits_addr_beat(htif_io_mem_acquire_bits_addr_beat),
+ .io_mem_acquire_bits_is_builtin_type(htif_io_mem_acquire_bits_is_builtin_type),
+ .io_mem_acquire_bits_a_type(htif_io_mem_acquire_bits_a_type),
+ .io_mem_acquire_bits_union(htif_io_mem_acquire_bits_union),
+ .io_mem_acquire_bits_data(htif_io_mem_acquire_bits_data),
+ .io_mem_grant_ready(htif_io_mem_grant_ready),
+ .io_mem_grant_valid(htif_io_mem_grant_valid),
+ .io_mem_grant_bits_addr_beat(htif_io_mem_grant_bits_addr_beat),
+ .io_mem_grant_bits_client_xact_id(htif_io_mem_grant_bits_client_xact_id),
+ .io_mem_grant_bits_manager_xact_id(htif_io_mem_grant_bits_manager_xact_id),
+ .io_mem_grant_bits_is_builtin_type(htif_io_mem_grant_bits_is_builtin_type),
+ .io_mem_grant_bits_g_type(htif_io_mem_grant_bits_g_type),
+ .io_mem_grant_bits_data(htif_io_mem_grant_bits_data),
+ .io_scr_req_ready(htif_io_scr_req_ready),
+ .io_scr_req_valid(htif_io_scr_req_valid),
+ .io_scr_req_bits_rw(htif_io_scr_req_bits_rw),
+ .io_scr_req_bits_addr(htif_io_scr_req_bits_addr),
+ .io_scr_req_bits_data(htif_io_scr_req_bits_data),
+ .io_scr_resp_ready(htif_io_scr_resp_ready),
+ .io_scr_resp_valid(htif_io_scr_resp_valid),
+ .io_scr_resp_bits(htif_io_scr_resp_bits)
+ );
+ OuterMemorySystem outmemsys (
+ .clk(outmemsys_clk),
+ .reset(outmemsys_reset),
+ .io_tiles_cached_0_acquire_ready(outmemsys_io_tiles_cached_0_acquire_ready),
+ .io_tiles_cached_0_acquire_valid(outmemsys_io_tiles_cached_0_acquire_valid),
+ .io_tiles_cached_0_acquire_bits_addr_block(outmemsys_io_tiles_cached_0_acquire_bits_addr_block),
+ .io_tiles_cached_0_acquire_bits_client_xact_id(outmemsys_io_tiles_cached_0_acquire_bits_client_xact_id),
+ .io_tiles_cached_0_acquire_bits_addr_beat(outmemsys_io_tiles_cached_0_acquire_bits_addr_beat),
+ .io_tiles_cached_0_acquire_bits_is_builtin_type(outmemsys_io_tiles_cached_0_acquire_bits_is_builtin_type),
+ .io_tiles_cached_0_acquire_bits_a_type(outmemsys_io_tiles_cached_0_acquire_bits_a_type),
+ .io_tiles_cached_0_acquire_bits_union(outmemsys_io_tiles_cached_0_acquire_bits_union),
+ .io_tiles_cached_0_acquire_bits_data(outmemsys_io_tiles_cached_0_acquire_bits_data),
+ .io_tiles_cached_0_grant_ready(outmemsys_io_tiles_cached_0_grant_ready),
+ .io_tiles_cached_0_grant_valid(outmemsys_io_tiles_cached_0_grant_valid),
+ .io_tiles_cached_0_grant_bits_addr_beat(outmemsys_io_tiles_cached_0_grant_bits_addr_beat),
+ .io_tiles_cached_0_grant_bits_client_xact_id(outmemsys_io_tiles_cached_0_grant_bits_client_xact_id),
+ .io_tiles_cached_0_grant_bits_manager_xact_id(outmemsys_io_tiles_cached_0_grant_bits_manager_xact_id),
+ .io_tiles_cached_0_grant_bits_is_builtin_type(outmemsys_io_tiles_cached_0_grant_bits_is_builtin_type),
+ .io_tiles_cached_0_grant_bits_g_type(outmemsys_io_tiles_cached_0_grant_bits_g_type),
+ .io_tiles_cached_0_grant_bits_data(outmemsys_io_tiles_cached_0_grant_bits_data),
+ .io_tiles_cached_0_probe_ready(outmemsys_io_tiles_cached_0_probe_ready),
+ .io_tiles_cached_0_probe_valid(outmemsys_io_tiles_cached_0_probe_valid),
+ .io_tiles_cached_0_probe_bits_addr_block(outmemsys_io_tiles_cached_0_probe_bits_addr_block),
+ .io_tiles_cached_0_probe_bits_p_type(outmemsys_io_tiles_cached_0_probe_bits_p_type),
+ .io_tiles_cached_0_release_ready(outmemsys_io_tiles_cached_0_release_ready),
+ .io_tiles_cached_0_release_valid(outmemsys_io_tiles_cached_0_release_valid),
+ .io_tiles_cached_0_release_bits_addr_beat(outmemsys_io_tiles_cached_0_release_bits_addr_beat),
+ .io_tiles_cached_0_release_bits_addr_block(outmemsys_io_tiles_cached_0_release_bits_addr_block),
+ .io_tiles_cached_0_release_bits_client_xact_id(outmemsys_io_tiles_cached_0_release_bits_client_xact_id),
+ .io_tiles_cached_0_release_bits_voluntary(outmemsys_io_tiles_cached_0_release_bits_voluntary),
+ .io_tiles_cached_0_release_bits_r_type(outmemsys_io_tiles_cached_0_release_bits_r_type),
+ .io_tiles_cached_0_release_bits_data(outmemsys_io_tiles_cached_0_release_bits_data),
+ .io_tiles_uncached_0_acquire_ready(outmemsys_io_tiles_uncached_0_acquire_ready),
+ .io_tiles_uncached_0_acquire_valid(outmemsys_io_tiles_uncached_0_acquire_valid),
+ .io_tiles_uncached_0_acquire_bits_addr_block(outmemsys_io_tiles_uncached_0_acquire_bits_addr_block),
+ .io_tiles_uncached_0_acquire_bits_client_xact_id(outmemsys_io_tiles_uncached_0_acquire_bits_client_xact_id),
+ .io_tiles_uncached_0_acquire_bits_addr_beat(outmemsys_io_tiles_uncached_0_acquire_bits_addr_beat),
+ .io_tiles_uncached_0_acquire_bits_is_builtin_type(outmemsys_io_tiles_uncached_0_acquire_bits_is_builtin_type),
+ .io_tiles_uncached_0_acquire_bits_a_type(outmemsys_io_tiles_uncached_0_acquire_bits_a_type),
+ .io_tiles_uncached_0_acquire_bits_union(outmemsys_io_tiles_uncached_0_acquire_bits_union),
+ .io_tiles_uncached_0_acquire_bits_data(outmemsys_io_tiles_uncached_0_acquire_bits_data),
+ .io_tiles_uncached_0_grant_ready(outmemsys_io_tiles_uncached_0_grant_ready),
+ .io_tiles_uncached_0_grant_valid(outmemsys_io_tiles_uncached_0_grant_valid),
+ .io_tiles_uncached_0_grant_bits_addr_beat(outmemsys_io_tiles_uncached_0_grant_bits_addr_beat),
+ .io_tiles_uncached_0_grant_bits_client_xact_id(outmemsys_io_tiles_uncached_0_grant_bits_client_xact_id),
+ .io_tiles_uncached_0_grant_bits_manager_xact_id(outmemsys_io_tiles_uncached_0_grant_bits_manager_xact_id),
+ .io_tiles_uncached_0_grant_bits_is_builtin_type(outmemsys_io_tiles_uncached_0_grant_bits_is_builtin_type),
+ .io_tiles_uncached_0_grant_bits_g_type(outmemsys_io_tiles_uncached_0_grant_bits_g_type),
+ .io_tiles_uncached_0_grant_bits_data(outmemsys_io_tiles_uncached_0_grant_bits_data),
+ .io_htif_uncached_acquire_ready(outmemsys_io_htif_uncached_acquire_ready),
+ .io_htif_uncached_acquire_valid(outmemsys_io_htif_uncached_acquire_valid),
+ .io_htif_uncached_acquire_bits_addr_block(outmemsys_io_htif_uncached_acquire_bits_addr_block),
+ .io_htif_uncached_acquire_bits_client_xact_id(outmemsys_io_htif_uncached_acquire_bits_client_xact_id),
+ .io_htif_uncached_acquire_bits_addr_beat(outmemsys_io_htif_uncached_acquire_bits_addr_beat),
+ .io_htif_uncached_acquire_bits_is_builtin_type(outmemsys_io_htif_uncached_acquire_bits_is_builtin_type),
+ .io_htif_uncached_acquire_bits_a_type(outmemsys_io_htif_uncached_acquire_bits_a_type),
+ .io_htif_uncached_acquire_bits_union(outmemsys_io_htif_uncached_acquire_bits_union),
+ .io_htif_uncached_acquire_bits_data(outmemsys_io_htif_uncached_acquire_bits_data),
+ .io_htif_uncached_grant_ready(outmemsys_io_htif_uncached_grant_ready),
+ .io_htif_uncached_grant_valid(outmemsys_io_htif_uncached_grant_valid),
+ .io_htif_uncached_grant_bits_addr_beat(outmemsys_io_htif_uncached_grant_bits_addr_beat),
+ .io_htif_uncached_grant_bits_client_xact_id(outmemsys_io_htif_uncached_grant_bits_client_xact_id),
+ .io_htif_uncached_grant_bits_manager_xact_id(outmemsys_io_htif_uncached_grant_bits_manager_xact_id),
+ .io_htif_uncached_grant_bits_is_builtin_type(outmemsys_io_htif_uncached_grant_bits_is_builtin_type),
+ .io_htif_uncached_grant_bits_g_type(outmemsys_io_htif_uncached_grant_bits_g_type),
+ .io_htif_uncached_grant_bits_data(outmemsys_io_htif_uncached_grant_bits_data),
+ .io_incoherent_0(outmemsys_io_incoherent_0),
+ .io_mem_0_aw_ready(outmemsys_io_mem_0_aw_ready),
+ .io_mem_0_aw_valid(outmemsys_io_mem_0_aw_valid),
+ .io_mem_0_aw_bits_addr(outmemsys_io_mem_0_aw_bits_addr),
+ .io_mem_0_aw_bits_len(outmemsys_io_mem_0_aw_bits_len),
+ .io_mem_0_aw_bits_size(outmemsys_io_mem_0_aw_bits_size),
+ .io_mem_0_aw_bits_burst(outmemsys_io_mem_0_aw_bits_burst),
+ .io_mem_0_aw_bits_lock(outmemsys_io_mem_0_aw_bits_lock),
+ .io_mem_0_aw_bits_cache(outmemsys_io_mem_0_aw_bits_cache),
+ .io_mem_0_aw_bits_prot(outmemsys_io_mem_0_aw_bits_prot),
+ .io_mem_0_aw_bits_qos(outmemsys_io_mem_0_aw_bits_qos),
+ .io_mem_0_aw_bits_region(outmemsys_io_mem_0_aw_bits_region),
+ .io_mem_0_aw_bits_id(outmemsys_io_mem_0_aw_bits_id),
+ .io_mem_0_aw_bits_user(outmemsys_io_mem_0_aw_bits_user),
+ .io_mem_0_w_ready(outmemsys_io_mem_0_w_ready),
+ .io_mem_0_w_valid(outmemsys_io_mem_0_w_valid),
+ .io_mem_0_w_bits_data(outmemsys_io_mem_0_w_bits_data),
+ .io_mem_0_w_bits_last(outmemsys_io_mem_0_w_bits_last),
+ .io_mem_0_w_bits_strb(outmemsys_io_mem_0_w_bits_strb),
+ .io_mem_0_w_bits_user(outmemsys_io_mem_0_w_bits_user),
+ .io_mem_0_b_ready(outmemsys_io_mem_0_b_ready),
+ .io_mem_0_b_valid(outmemsys_io_mem_0_b_valid),
+ .io_mem_0_b_bits_resp(outmemsys_io_mem_0_b_bits_resp),
+ .io_mem_0_b_bits_id(outmemsys_io_mem_0_b_bits_id),
+ .io_mem_0_b_bits_user(outmemsys_io_mem_0_b_bits_user),
+ .io_mem_0_ar_ready(outmemsys_io_mem_0_ar_ready),
+ .io_mem_0_ar_valid(outmemsys_io_mem_0_ar_valid),
+ .io_mem_0_ar_bits_addr(outmemsys_io_mem_0_ar_bits_addr),
+ .io_mem_0_ar_bits_len(outmemsys_io_mem_0_ar_bits_len),
+ .io_mem_0_ar_bits_size(outmemsys_io_mem_0_ar_bits_size),
+ .io_mem_0_ar_bits_burst(outmemsys_io_mem_0_ar_bits_burst),
+ .io_mem_0_ar_bits_lock(outmemsys_io_mem_0_ar_bits_lock),
+ .io_mem_0_ar_bits_cache(outmemsys_io_mem_0_ar_bits_cache),
+ .io_mem_0_ar_bits_prot(outmemsys_io_mem_0_ar_bits_prot),
+ .io_mem_0_ar_bits_qos(outmemsys_io_mem_0_ar_bits_qos),
+ .io_mem_0_ar_bits_region(outmemsys_io_mem_0_ar_bits_region),
+ .io_mem_0_ar_bits_id(outmemsys_io_mem_0_ar_bits_id),
+ .io_mem_0_ar_bits_user(outmemsys_io_mem_0_ar_bits_user),
+ .io_mem_0_r_ready(outmemsys_io_mem_0_r_ready),
+ .io_mem_0_r_valid(outmemsys_io_mem_0_r_valid),
+ .io_mem_0_r_bits_resp(outmemsys_io_mem_0_r_bits_resp),
+ .io_mem_0_r_bits_data(outmemsys_io_mem_0_r_bits_data),
+ .io_mem_0_r_bits_last(outmemsys_io_mem_0_r_bits_last),
+ .io_mem_0_r_bits_id(outmemsys_io_mem_0_r_bits_id),
+ .io_mem_0_r_bits_user(outmemsys_io_mem_0_r_bits_user),
+ .io_mem_backup_req_ready(outmemsys_io_mem_backup_req_ready),
+ .io_mem_backup_req_valid(outmemsys_io_mem_backup_req_valid),
+ .io_mem_backup_req_bits(outmemsys_io_mem_backup_req_bits),
+ .io_mem_backup_resp_valid(outmemsys_io_mem_backup_resp_valid),
+ .io_mem_backup_resp_bits(outmemsys_io_mem_backup_resp_bits),
+ .io_mem_backup_en(outmemsys_io_mem_backup_en),
+ .io_csr_0_req_ready(outmemsys_io_csr_0_req_ready),
+ .io_csr_0_req_valid(outmemsys_io_csr_0_req_valid),
+ .io_csr_0_req_bits_rw(outmemsys_io_csr_0_req_bits_rw),
+ .io_csr_0_req_bits_addr(outmemsys_io_csr_0_req_bits_addr),
+ .io_csr_0_req_bits_data(outmemsys_io_csr_0_req_bits_data),
+ .io_csr_0_resp_ready(outmemsys_io_csr_0_resp_ready),
+ .io_csr_0_resp_valid(outmemsys_io_csr_0_resp_valid),
+ .io_csr_0_resp_bits(outmemsys_io_csr_0_resp_bits),
+ .io_scr_req_ready(outmemsys_io_scr_req_ready),
+ .io_scr_req_valid(outmemsys_io_scr_req_valid),
+ .io_scr_req_bits_rw(outmemsys_io_scr_req_bits_rw),
+ .io_scr_req_bits_addr(outmemsys_io_scr_req_bits_addr),
+ .io_scr_req_bits_data(outmemsys_io_scr_req_bits_data),
+ .io_scr_resp_ready(outmemsys_io_scr_resp_ready),
+ .io_scr_resp_valid(outmemsys_io_scr_resp_valid),
+ .io_scr_resp_bits(outmemsys_io_scr_resp_bits),
+ .io_mmio_aw_ready(outmemsys_io_mmio_aw_ready),
+ .io_mmio_aw_valid(outmemsys_io_mmio_aw_valid),
+ .io_mmio_aw_bits_addr(outmemsys_io_mmio_aw_bits_addr),
+ .io_mmio_aw_bits_len(outmemsys_io_mmio_aw_bits_len),
+ .io_mmio_aw_bits_size(outmemsys_io_mmio_aw_bits_size),
+ .io_mmio_aw_bits_burst(outmemsys_io_mmio_aw_bits_burst),
+ .io_mmio_aw_bits_lock(outmemsys_io_mmio_aw_bits_lock),
+ .io_mmio_aw_bits_cache(outmemsys_io_mmio_aw_bits_cache),
+ .io_mmio_aw_bits_prot(outmemsys_io_mmio_aw_bits_prot),
+ .io_mmio_aw_bits_qos(outmemsys_io_mmio_aw_bits_qos),
+ .io_mmio_aw_bits_region(outmemsys_io_mmio_aw_bits_region),
+ .io_mmio_aw_bits_id(outmemsys_io_mmio_aw_bits_id),
+ .io_mmio_aw_bits_user(outmemsys_io_mmio_aw_bits_user),
+ .io_mmio_w_ready(outmemsys_io_mmio_w_ready),
+ .io_mmio_w_valid(outmemsys_io_mmio_w_valid),
+ .io_mmio_w_bits_data(outmemsys_io_mmio_w_bits_data),
+ .io_mmio_w_bits_last(outmemsys_io_mmio_w_bits_last),
+ .io_mmio_w_bits_strb(outmemsys_io_mmio_w_bits_strb),
+ .io_mmio_w_bits_user(outmemsys_io_mmio_w_bits_user),
+ .io_mmio_b_ready(outmemsys_io_mmio_b_ready),
+ .io_mmio_b_valid(outmemsys_io_mmio_b_valid),
+ .io_mmio_b_bits_resp(outmemsys_io_mmio_b_bits_resp),
+ .io_mmio_b_bits_id(outmemsys_io_mmio_b_bits_id),
+ .io_mmio_b_bits_user(outmemsys_io_mmio_b_bits_user),
+ .io_mmio_ar_ready(outmemsys_io_mmio_ar_ready),
+ .io_mmio_ar_valid(outmemsys_io_mmio_ar_valid),
+ .io_mmio_ar_bits_addr(outmemsys_io_mmio_ar_bits_addr),
+ .io_mmio_ar_bits_len(outmemsys_io_mmio_ar_bits_len),
+ .io_mmio_ar_bits_size(outmemsys_io_mmio_ar_bits_size),
+ .io_mmio_ar_bits_burst(outmemsys_io_mmio_ar_bits_burst),
+ .io_mmio_ar_bits_lock(outmemsys_io_mmio_ar_bits_lock),
+ .io_mmio_ar_bits_cache(outmemsys_io_mmio_ar_bits_cache),
+ .io_mmio_ar_bits_prot(outmemsys_io_mmio_ar_bits_prot),
+ .io_mmio_ar_bits_qos(outmemsys_io_mmio_ar_bits_qos),
+ .io_mmio_ar_bits_region(outmemsys_io_mmio_ar_bits_region),
+ .io_mmio_ar_bits_id(outmemsys_io_mmio_ar_bits_id),
+ .io_mmio_ar_bits_user(outmemsys_io_mmio_ar_bits_user),
+ .io_mmio_r_ready(outmemsys_io_mmio_r_ready),
+ .io_mmio_r_valid(outmemsys_io_mmio_r_valid),
+ .io_mmio_r_bits_resp(outmemsys_io_mmio_r_bits_resp),
+ .io_mmio_r_bits_data(outmemsys_io_mmio_r_bits_data),
+ .io_mmio_r_bits_last(outmemsys_io_mmio_r_bits_last),
+ .io_mmio_r_bits_id(outmemsys_io_mmio_r_bits_id),
+ .io_mmio_r_bits_user(outmemsys_io_mmio_r_bits_user),
+ .io_deviceTree_aw_ready(outmemsys_io_deviceTree_aw_ready),
+ .io_deviceTree_aw_valid(outmemsys_io_deviceTree_aw_valid),
+ .io_deviceTree_aw_bits_addr(outmemsys_io_deviceTree_aw_bits_addr),
+ .io_deviceTree_aw_bits_len(outmemsys_io_deviceTree_aw_bits_len),
+ .io_deviceTree_aw_bits_size(outmemsys_io_deviceTree_aw_bits_size),
+ .io_deviceTree_aw_bits_burst(outmemsys_io_deviceTree_aw_bits_burst),
+ .io_deviceTree_aw_bits_lock(outmemsys_io_deviceTree_aw_bits_lock),
+ .io_deviceTree_aw_bits_cache(outmemsys_io_deviceTree_aw_bits_cache),
+ .io_deviceTree_aw_bits_prot(outmemsys_io_deviceTree_aw_bits_prot),
+ .io_deviceTree_aw_bits_qos(outmemsys_io_deviceTree_aw_bits_qos),
+ .io_deviceTree_aw_bits_region(outmemsys_io_deviceTree_aw_bits_region),
+ .io_deviceTree_aw_bits_id(outmemsys_io_deviceTree_aw_bits_id),
+ .io_deviceTree_aw_bits_user(outmemsys_io_deviceTree_aw_bits_user),
+ .io_deviceTree_w_ready(outmemsys_io_deviceTree_w_ready),
+ .io_deviceTree_w_valid(outmemsys_io_deviceTree_w_valid),
+ .io_deviceTree_w_bits_data(outmemsys_io_deviceTree_w_bits_data),
+ .io_deviceTree_w_bits_last(outmemsys_io_deviceTree_w_bits_last),
+ .io_deviceTree_w_bits_strb(outmemsys_io_deviceTree_w_bits_strb),
+ .io_deviceTree_w_bits_user(outmemsys_io_deviceTree_w_bits_user),
+ .io_deviceTree_b_ready(outmemsys_io_deviceTree_b_ready),
+ .io_deviceTree_b_valid(outmemsys_io_deviceTree_b_valid),
+ .io_deviceTree_b_bits_resp(outmemsys_io_deviceTree_b_bits_resp),
+ .io_deviceTree_b_bits_id(outmemsys_io_deviceTree_b_bits_id),
+ .io_deviceTree_b_bits_user(outmemsys_io_deviceTree_b_bits_user),
+ .io_deviceTree_ar_ready(outmemsys_io_deviceTree_ar_ready),
+ .io_deviceTree_ar_valid(outmemsys_io_deviceTree_ar_valid),
+ .io_deviceTree_ar_bits_addr(outmemsys_io_deviceTree_ar_bits_addr),
+ .io_deviceTree_ar_bits_len(outmemsys_io_deviceTree_ar_bits_len),
+ .io_deviceTree_ar_bits_size(outmemsys_io_deviceTree_ar_bits_size),
+ .io_deviceTree_ar_bits_burst(outmemsys_io_deviceTree_ar_bits_burst),
+ .io_deviceTree_ar_bits_lock(outmemsys_io_deviceTree_ar_bits_lock),
+ .io_deviceTree_ar_bits_cache(outmemsys_io_deviceTree_ar_bits_cache),
+ .io_deviceTree_ar_bits_prot(outmemsys_io_deviceTree_ar_bits_prot),
+ .io_deviceTree_ar_bits_qos(outmemsys_io_deviceTree_ar_bits_qos),
+ .io_deviceTree_ar_bits_region(outmemsys_io_deviceTree_ar_bits_region),
+ .io_deviceTree_ar_bits_id(outmemsys_io_deviceTree_ar_bits_id),
+ .io_deviceTree_ar_bits_user(outmemsys_io_deviceTree_ar_bits_user),
+ .io_deviceTree_r_ready(outmemsys_io_deviceTree_r_ready),
+ .io_deviceTree_r_valid(outmemsys_io_deviceTree_r_valid),
+ .io_deviceTree_r_bits_resp(outmemsys_io_deviceTree_r_bits_resp),
+ .io_deviceTree_r_bits_data(outmemsys_io_deviceTree_r_bits_data),
+ .io_deviceTree_r_bits_last(outmemsys_io_deviceTree_r_bits_last),
+ .io_deviceTree_r_bits_id(outmemsys_io_deviceTree_r_bits_id),
+ .io_deviceTree_r_bits_user(outmemsys_io_deviceTree_r_bits_user),
+ .io_dma_req_ready(outmemsys_io_dma_req_ready),
+ .io_dma_req_valid(outmemsys_io_dma_req_valid),
+ .io_dma_req_bits_client_xact_id(outmemsys_io_dma_req_bits_client_xact_id),
+ .io_dma_req_bits_cmd(outmemsys_io_dma_req_bits_cmd),
+ .io_dma_req_bits_source(outmemsys_io_dma_req_bits_source),
+ .io_dma_req_bits_dest(outmemsys_io_dma_req_bits_dest),
+ .io_dma_req_bits_length(outmemsys_io_dma_req_bits_length),
+ .io_dma_req_bits_size(outmemsys_io_dma_req_bits_size),
+ .io_dma_resp_ready(outmemsys_io_dma_resp_ready),
+ .io_dma_resp_valid(outmemsys_io_dma_resp_valid),
+ .io_dma_resp_bits_client_xact_id(outmemsys_io_dma_resp_bits_client_xact_id),
+ .io_dma_resp_bits_status(outmemsys_io_dma_resp_bits_status)
+ );
+ SmiArbiter T_8362 (
+ .clk(T_8362_clk),
+ .reset(T_8362_reset),
+ .io_in_0_req_ready(T_8362_io_in_0_req_ready),
+ .io_in_0_req_valid(T_8362_io_in_0_req_valid),
+ .io_in_0_req_bits_rw(T_8362_io_in_0_req_bits_rw),
+ .io_in_0_req_bits_addr(T_8362_io_in_0_req_bits_addr),
+ .io_in_0_req_bits_data(T_8362_io_in_0_req_bits_data),
+ .io_in_0_resp_ready(T_8362_io_in_0_resp_ready),
+ .io_in_0_resp_valid(T_8362_io_in_0_resp_valid),
+ .io_in_0_resp_bits(T_8362_io_in_0_resp_bits),
+ .io_in_1_req_ready(T_8362_io_in_1_req_ready),
+ .io_in_1_req_valid(T_8362_io_in_1_req_valid),
+ .io_in_1_req_bits_rw(T_8362_io_in_1_req_bits_rw),
+ .io_in_1_req_bits_addr(T_8362_io_in_1_req_bits_addr),
+ .io_in_1_req_bits_data(T_8362_io_in_1_req_bits_data),
+ .io_in_1_resp_ready(T_8362_io_in_1_resp_ready),
+ .io_in_1_resp_valid(T_8362_io_in_1_resp_valid),
+ .io_in_1_resp_bits(T_8362_io_in_1_resp_bits),
+ .io_out_req_ready(T_8362_io_out_req_ready),
+ .io_out_req_valid(T_8362_io_out_req_valid),
+ .io_out_req_bits_rw(T_8362_io_out_req_bits_rw),
+ .io_out_req_bits_addr(T_8362_io_out_req_bits_addr),
+ .io_out_req_bits_data(T_8362_io_out_req_bits_data),
+ .io_out_resp_ready(T_8362_io_out_resp_ready),
+ .io_out_resp_valid(T_8362_io_out_resp_valid),
+ .io_out_resp_bits(T_8362_io_out_resp_bits)
+ );
+ SCRFile scrFile (
+ .clk(scrFile_clk),
+ .reset(scrFile_reset),
+ .io_smi_req_ready(scrFile_io_smi_req_ready),
+ .io_smi_req_valid(scrFile_io_smi_req_valid),
+ .io_smi_req_bits_rw(scrFile_io_smi_req_bits_rw),
+ .io_smi_req_bits_addr(scrFile_io_smi_req_bits_addr),
+ .io_smi_req_bits_data(scrFile_io_smi_req_bits_data),
+ .io_smi_resp_ready(scrFile_io_smi_resp_ready),
+ .io_smi_resp_valid(scrFile_io_smi_resp_valid),
+ .io_smi_resp_bits(scrFile_io_smi_resp_bits),
+ .io_scr_rdata_0(scrFile_io_scr_rdata_0),
+ .io_scr_rdata_1(scrFile_io_scr_rdata_1),
+ .io_scr_rdata_2(scrFile_io_scr_rdata_2),
+ .io_scr_rdata_3(scrFile_io_scr_rdata_3),
+ .io_scr_rdata_4(scrFile_io_scr_rdata_4),
+ .io_scr_rdata_5(scrFile_io_scr_rdata_5),
+ .io_scr_rdata_6(scrFile_io_scr_rdata_6),
+ .io_scr_rdata_7(scrFile_io_scr_rdata_7),
+ .io_scr_rdata_8(scrFile_io_scr_rdata_8),
+ .io_scr_rdata_9(scrFile_io_scr_rdata_9),
+ .io_scr_rdata_10(scrFile_io_scr_rdata_10),
+ .io_scr_rdata_11(scrFile_io_scr_rdata_11),
+ .io_scr_rdata_12(scrFile_io_scr_rdata_12),
+ .io_scr_rdata_13(scrFile_io_scr_rdata_13),
+ .io_scr_rdata_14(scrFile_io_scr_rdata_14),
+ .io_scr_rdata_15(scrFile_io_scr_rdata_15),
+ .io_scr_rdata_16(scrFile_io_scr_rdata_16),
+ .io_scr_rdata_17(scrFile_io_scr_rdata_17),
+ .io_scr_rdata_18(scrFile_io_scr_rdata_18),
+ .io_scr_rdata_19(scrFile_io_scr_rdata_19),
+ .io_scr_rdata_20(scrFile_io_scr_rdata_20),
+ .io_scr_rdata_21(scrFile_io_scr_rdata_21),
+ .io_scr_rdata_22(scrFile_io_scr_rdata_22),
+ .io_scr_rdata_23(scrFile_io_scr_rdata_23),
+ .io_scr_rdata_24(scrFile_io_scr_rdata_24),
+ .io_scr_rdata_25(scrFile_io_scr_rdata_25),
+ .io_scr_rdata_26(scrFile_io_scr_rdata_26),
+ .io_scr_rdata_27(scrFile_io_scr_rdata_27),
+ .io_scr_rdata_28(scrFile_io_scr_rdata_28),
+ .io_scr_rdata_29(scrFile_io_scr_rdata_29),
+ .io_scr_rdata_30(scrFile_io_scr_rdata_30),
+ .io_scr_rdata_31(scrFile_io_scr_rdata_31),
+ .io_scr_rdata_32(scrFile_io_scr_rdata_32),
+ .io_scr_rdata_33(scrFile_io_scr_rdata_33),
+ .io_scr_rdata_34(scrFile_io_scr_rdata_34),
+ .io_scr_rdata_35(scrFile_io_scr_rdata_35),
+ .io_scr_rdata_36(scrFile_io_scr_rdata_36),
+ .io_scr_rdata_37(scrFile_io_scr_rdata_37),
+ .io_scr_rdata_38(scrFile_io_scr_rdata_38),
+ .io_scr_rdata_39(scrFile_io_scr_rdata_39),
+ .io_scr_rdata_40(scrFile_io_scr_rdata_40),
+ .io_scr_rdata_41(scrFile_io_scr_rdata_41),
+ .io_scr_rdata_42(scrFile_io_scr_rdata_42),
+ .io_scr_rdata_43(scrFile_io_scr_rdata_43),
+ .io_scr_rdata_44(scrFile_io_scr_rdata_44),
+ .io_scr_rdata_45(scrFile_io_scr_rdata_45),
+ .io_scr_rdata_46(scrFile_io_scr_rdata_46),
+ .io_scr_rdata_47(scrFile_io_scr_rdata_47),
+ .io_scr_rdata_48(scrFile_io_scr_rdata_48),
+ .io_scr_rdata_49(scrFile_io_scr_rdata_49),
+ .io_scr_rdata_50(scrFile_io_scr_rdata_50),
+ .io_scr_rdata_51(scrFile_io_scr_rdata_51),
+ .io_scr_rdata_52(scrFile_io_scr_rdata_52),
+ .io_scr_rdata_53(scrFile_io_scr_rdata_53),
+ .io_scr_rdata_54(scrFile_io_scr_rdata_54),
+ .io_scr_rdata_55(scrFile_io_scr_rdata_55),
+ .io_scr_rdata_56(scrFile_io_scr_rdata_56),
+ .io_scr_rdata_57(scrFile_io_scr_rdata_57),
+ .io_scr_rdata_58(scrFile_io_scr_rdata_58),
+ .io_scr_rdata_59(scrFile_io_scr_rdata_59),
+ .io_scr_rdata_60(scrFile_io_scr_rdata_60),
+ .io_scr_rdata_61(scrFile_io_scr_rdata_61),
+ .io_scr_rdata_62(scrFile_io_scr_rdata_62),
+ .io_scr_rdata_63(scrFile_io_scr_rdata_63),
+ .io_scr_wen(scrFile_io_scr_wen),
+ .io_scr_waddr(scrFile_io_scr_waddr),
+ .io_scr_wdata(scrFile_io_scr_wdata)
+ );
+ SmiArbiter_81 scrArb (
+ .clk(scrArb_clk),
+ .reset(scrArb_reset),
+ .io_in_0_req_ready(scrArb_io_in_0_req_ready),
+ .io_in_0_req_valid(scrArb_io_in_0_req_valid),
+ .io_in_0_req_bits_rw(scrArb_io_in_0_req_bits_rw),
+ .io_in_0_req_bits_addr(scrArb_io_in_0_req_bits_addr),
+ .io_in_0_req_bits_data(scrArb_io_in_0_req_bits_data),
+ .io_in_0_resp_ready(scrArb_io_in_0_resp_ready),
+ .io_in_0_resp_valid(scrArb_io_in_0_resp_valid),
+ .io_in_0_resp_bits(scrArb_io_in_0_resp_bits),
+ .io_in_1_req_ready(scrArb_io_in_1_req_ready),
+ .io_in_1_req_valid(scrArb_io_in_1_req_valid),
+ .io_in_1_req_bits_rw(scrArb_io_in_1_req_bits_rw),
+ .io_in_1_req_bits_addr(scrArb_io_in_1_req_bits_addr),
+ .io_in_1_req_bits_data(scrArb_io_in_1_req_bits_data),
+ .io_in_1_resp_ready(scrArb_io_in_1_resp_ready),
+ .io_in_1_resp_valid(scrArb_io_in_1_resp_valid),
+ .io_in_1_resp_bits(scrArb_io_in_1_resp_bits),
+ .io_out_req_ready(scrArb_io_out_req_ready),
+ .io_out_req_valid(scrArb_io_out_req_valid),
+ .io_out_req_bits_rw(scrArb_io_out_req_bits_rw),
+ .io_out_req_bits_addr(scrArb_io_out_req_bits_addr),
+ .io_out_req_bits_data(scrArb_io_out_req_bits_data),
+ .io_out_resp_ready(scrArb_io_out_resp_ready),
+ .io_out_resp_valid(scrArb_io_out_resp_valid),
+ .io_out_resp_bits(scrArb_io_out_resp_bits)
+ );
+ NastiROM deviceTree (
+ .clk(deviceTree_clk),
+ .reset(deviceTree_reset),
+ .io_aw_ready(deviceTree_io_aw_ready),
+ .io_aw_valid(deviceTree_io_aw_valid),
+ .io_aw_bits_addr(deviceTree_io_aw_bits_addr),
+ .io_aw_bits_len(deviceTree_io_aw_bits_len),
+ .io_aw_bits_size(deviceTree_io_aw_bits_size),
+ .io_aw_bits_burst(deviceTree_io_aw_bits_burst),
+ .io_aw_bits_lock(deviceTree_io_aw_bits_lock),
+ .io_aw_bits_cache(deviceTree_io_aw_bits_cache),
+ .io_aw_bits_prot(deviceTree_io_aw_bits_prot),
+ .io_aw_bits_qos(deviceTree_io_aw_bits_qos),
+ .io_aw_bits_region(deviceTree_io_aw_bits_region),
+ .io_aw_bits_id(deviceTree_io_aw_bits_id),
+ .io_aw_bits_user(deviceTree_io_aw_bits_user),
+ .io_w_ready(deviceTree_io_w_ready),
+ .io_w_valid(deviceTree_io_w_valid),
+ .io_w_bits_data(deviceTree_io_w_bits_data),
+ .io_w_bits_last(deviceTree_io_w_bits_last),
+ .io_w_bits_strb(deviceTree_io_w_bits_strb),
+ .io_w_bits_user(deviceTree_io_w_bits_user),
+ .io_b_ready(deviceTree_io_b_ready),
+ .io_b_valid(deviceTree_io_b_valid),
+ .io_b_bits_resp(deviceTree_io_b_bits_resp),
+ .io_b_bits_id(deviceTree_io_b_bits_id),
+ .io_b_bits_user(deviceTree_io_b_bits_user),
+ .io_ar_ready(deviceTree_io_ar_ready),
+ .io_ar_valid(deviceTree_io_ar_valid),
+ .io_ar_bits_addr(deviceTree_io_ar_bits_addr),
+ .io_ar_bits_len(deviceTree_io_ar_bits_len),
+ .io_ar_bits_size(deviceTree_io_ar_bits_size),
+ .io_ar_bits_burst(deviceTree_io_ar_bits_burst),
+ .io_ar_bits_lock(deviceTree_io_ar_bits_lock),
+ .io_ar_bits_cache(deviceTree_io_ar_bits_cache),
+ .io_ar_bits_prot(deviceTree_io_ar_bits_prot),
+ .io_ar_bits_qos(deviceTree_io_ar_bits_qos),
+ .io_ar_bits_region(deviceTree_io_ar_bits_region),
+ .io_ar_bits_id(deviceTree_io_ar_bits_id),
+ .io_ar_bits_user(deviceTree_io_ar_bits_user),
+ .io_r_ready(deviceTree_io_r_ready),
+ .io_r_valid(deviceTree_io_r_valid),
+ .io_r_bits_resp(deviceTree_io_r_bits_resp),
+ .io_r_bits_data(deviceTree_io_r_bits_data),
+ .io_r_bits_last(deviceTree_io_r_bits_last),
+ .io_r_bits_id(deviceTree_io_r_bits_id),
+ .io_r_bits_user(deviceTree_io_r_bits_user)
+ );
+ SlowIO T_8366 (
+ .clk(T_8366_clk),
+ .reset(T_8366_reset),
+ .io_out_fast_ready(T_8366_io_out_fast_ready),
+ .io_out_fast_valid(T_8366_io_out_fast_valid),
+ .io_out_fast_bits(T_8366_io_out_fast_bits),
+ .io_out_slow_ready(T_8366_io_out_slow_ready),
+ .io_out_slow_valid(T_8366_io_out_slow_valid),
+ .io_out_slow_bits(T_8366_io_out_slow_bits),
+ .io_in_fast_ready(T_8366_io_in_fast_ready),
+ .io_in_fast_valid(T_8366_io_in_fast_valid),
+ .io_in_fast_bits(T_8366_io_in_fast_bits),
+ .io_in_slow_ready(T_8366_io_in_slow_ready),
+ .io_in_slow_valid(T_8366_io_in_slow_valid),
+ .io_in_slow_bits(T_8366_io_in_slow_bits),
+ .io_clk_slow(T_8366_io_clk_slow),
+ .io_set_divisor_valid(T_8366_io_set_divisor_valid),
+ .io_set_divisor_bits(T_8366_io_set_divisor_bits),
+ .io_divisor(T_8366_io_divisor)
+ );
+ assign io_host_clk = T_8366_io_clk_slow;
+ assign io_host_clk_edge = T_8400;
+ assign io_host_in_ready = T_8366_io_in_slow_ready;
+ assign io_host_out_valid = T_8377;
+ assign io_host_out_bits = T_8366_io_out_slow_bits;
+ assign io_host_debug_stats_csr = htif_io_host_debug_stats_csr;
+ assign io_mem_0_aw_valid = outmemsys_io_mem_0_aw_valid;
+ assign io_mem_0_aw_bits_addr = outmemsys_io_mem_0_aw_bits_addr;
+ assign io_mem_0_aw_bits_len = outmemsys_io_mem_0_aw_bits_len;
+ assign io_mem_0_aw_bits_size = outmemsys_io_mem_0_aw_bits_size;
+ assign io_mem_0_aw_bits_burst = outmemsys_io_mem_0_aw_bits_burst;
+ assign io_mem_0_aw_bits_lock = outmemsys_io_mem_0_aw_bits_lock;
+ assign io_mem_0_aw_bits_cache = outmemsys_io_mem_0_aw_bits_cache;
+ assign io_mem_0_aw_bits_prot = outmemsys_io_mem_0_aw_bits_prot;
+ assign io_mem_0_aw_bits_qos = outmemsys_io_mem_0_aw_bits_qos;
+ assign io_mem_0_aw_bits_region = outmemsys_io_mem_0_aw_bits_region;
+ assign io_mem_0_aw_bits_id = outmemsys_io_mem_0_aw_bits_id;
+ assign io_mem_0_aw_bits_user = outmemsys_io_mem_0_aw_bits_user;
+ assign io_mem_0_w_valid = outmemsys_io_mem_0_w_valid;
+ assign io_mem_0_w_bits_data = outmemsys_io_mem_0_w_bits_data;
+ assign io_mem_0_w_bits_last = outmemsys_io_mem_0_w_bits_last;
+ assign io_mem_0_w_bits_strb = outmemsys_io_mem_0_w_bits_strb;
+ assign io_mem_0_w_bits_user = outmemsys_io_mem_0_w_bits_user;
+ assign io_mem_0_b_ready = outmemsys_io_mem_0_b_ready;
+ assign io_mem_0_ar_valid = outmemsys_io_mem_0_ar_valid;
+ assign io_mem_0_ar_bits_addr = outmemsys_io_mem_0_ar_bits_addr;
+ assign io_mem_0_ar_bits_len = outmemsys_io_mem_0_ar_bits_len;
+ assign io_mem_0_ar_bits_size = outmemsys_io_mem_0_ar_bits_size;
+ assign io_mem_0_ar_bits_burst = outmemsys_io_mem_0_ar_bits_burst;
+ assign io_mem_0_ar_bits_lock = outmemsys_io_mem_0_ar_bits_lock;
+ assign io_mem_0_ar_bits_cache = outmemsys_io_mem_0_ar_bits_cache;
+ assign io_mem_0_ar_bits_prot = outmemsys_io_mem_0_ar_bits_prot;
+ assign io_mem_0_ar_bits_qos = outmemsys_io_mem_0_ar_bits_qos;
+ assign io_mem_0_ar_bits_region = outmemsys_io_mem_0_ar_bits_region;
+ assign io_mem_0_ar_bits_id = outmemsys_io_mem_0_ar_bits_id;
+ assign io_mem_0_ar_bits_user = outmemsys_io_mem_0_ar_bits_user;
+ assign io_mem_0_r_ready = outmemsys_io_mem_0_r_ready;
+ assign io_tiles_cached_0_acquire_ready = outmemsys_io_tiles_cached_0_acquire_ready;
+ assign io_tiles_cached_0_grant_valid = outmemsys_io_tiles_cached_0_grant_valid;
+ assign io_tiles_cached_0_grant_bits_addr_beat = outmemsys_io_tiles_cached_0_grant_bits_addr_beat;
+ assign io_tiles_cached_0_grant_bits_client_xact_id = outmemsys_io_tiles_cached_0_grant_bits_client_xact_id;
+ assign io_tiles_cached_0_grant_bits_manager_xact_id = outmemsys_io_tiles_cached_0_grant_bits_manager_xact_id;
+ assign io_tiles_cached_0_grant_bits_is_builtin_type = outmemsys_io_tiles_cached_0_grant_bits_is_builtin_type;
+ assign io_tiles_cached_0_grant_bits_g_type = outmemsys_io_tiles_cached_0_grant_bits_g_type;
+ assign io_tiles_cached_0_grant_bits_data = outmemsys_io_tiles_cached_0_grant_bits_data;
+ assign io_tiles_cached_0_probe_valid = outmemsys_io_tiles_cached_0_probe_valid;
+ assign io_tiles_cached_0_probe_bits_addr_block = outmemsys_io_tiles_cached_0_probe_bits_addr_block;
+ assign io_tiles_cached_0_probe_bits_p_type = outmemsys_io_tiles_cached_0_probe_bits_p_type;
+ assign io_tiles_cached_0_release_ready = outmemsys_io_tiles_cached_0_release_ready;
+ assign io_tiles_uncached_0_acquire_ready = outmemsys_io_tiles_uncached_0_acquire_ready;
+ assign io_tiles_uncached_0_grant_valid = outmemsys_io_tiles_uncached_0_grant_valid;
+ assign io_tiles_uncached_0_grant_bits_addr_beat = outmemsys_io_tiles_uncached_0_grant_bits_addr_beat;
+ assign io_tiles_uncached_0_grant_bits_client_xact_id = outmemsys_io_tiles_uncached_0_grant_bits_client_xact_id;
+ assign io_tiles_uncached_0_grant_bits_manager_xact_id = outmemsys_io_tiles_uncached_0_grant_bits_manager_xact_id;
+ assign io_tiles_uncached_0_grant_bits_is_builtin_type = outmemsys_io_tiles_uncached_0_grant_bits_is_builtin_type;
+ assign io_tiles_uncached_0_grant_bits_g_type = outmemsys_io_tiles_uncached_0_grant_bits_g_type;
+ assign io_tiles_uncached_0_grant_bits_data = outmemsys_io_tiles_uncached_0_grant_bits_data;
+ assign io_htif_0_reset = htif_io_cpu_0_reset;
+ assign io_htif_0_id = htif_io_cpu_0_id;
+ assign io_htif_0_csr_req_valid = T_8362_io_out_req_valid;
+ assign io_htif_0_csr_req_bits_rw = T_8362_io_out_req_bits_rw;
+ assign io_htif_0_csr_req_bits_addr = T_8362_io_out_req_bits_addr;
+ assign io_htif_0_csr_req_bits_data = T_8362_io_out_req_bits_data;
+ assign io_htif_0_csr_resp_ready = T_8362_io_out_resp_ready;
+ assign io_mem_backup_ctrl_out_valid = T_8381;
+ assign io_mmio_aw_valid = outmemsys_io_mmio_aw_valid;
+ assign io_mmio_aw_bits_addr = outmemsys_io_mmio_aw_bits_addr;
+ assign io_mmio_aw_bits_len = outmemsys_io_mmio_aw_bits_len;
+ assign io_mmio_aw_bits_size = outmemsys_io_mmio_aw_bits_size;
+ assign io_mmio_aw_bits_burst = outmemsys_io_mmio_aw_bits_burst;
+ assign io_mmio_aw_bits_lock = outmemsys_io_mmio_aw_bits_lock;
+ assign io_mmio_aw_bits_cache = outmemsys_io_mmio_aw_bits_cache;
+ assign io_mmio_aw_bits_prot = outmemsys_io_mmio_aw_bits_prot;
+ assign io_mmio_aw_bits_qos = outmemsys_io_mmio_aw_bits_qos;
+ assign io_mmio_aw_bits_region = outmemsys_io_mmio_aw_bits_region;
+ assign io_mmio_aw_bits_id = outmemsys_io_mmio_aw_bits_id;
+ assign io_mmio_aw_bits_user = outmemsys_io_mmio_aw_bits_user;
+ assign io_mmio_w_valid = outmemsys_io_mmio_w_valid;
+ assign io_mmio_w_bits_data = outmemsys_io_mmio_w_bits_data;
+ assign io_mmio_w_bits_last = outmemsys_io_mmio_w_bits_last;
+ assign io_mmio_w_bits_strb = outmemsys_io_mmio_w_bits_strb;
+ assign io_mmio_w_bits_user = outmemsys_io_mmio_w_bits_user;
+ assign io_mmio_b_ready = outmemsys_io_mmio_b_ready;
+ assign io_mmio_ar_valid = outmemsys_io_mmio_ar_valid;
+ assign io_mmio_ar_bits_addr = outmemsys_io_mmio_ar_bits_addr;
+ assign io_mmio_ar_bits_len = outmemsys_io_mmio_ar_bits_len;
+ assign io_mmio_ar_bits_size = outmemsys_io_mmio_ar_bits_size;
+ assign io_mmio_ar_bits_burst = outmemsys_io_mmio_ar_bits_burst;
+ assign io_mmio_ar_bits_lock = outmemsys_io_mmio_ar_bits_lock;
+ assign io_mmio_ar_bits_cache = outmemsys_io_mmio_ar_bits_cache;
+ assign io_mmio_ar_bits_prot = outmemsys_io_mmio_ar_bits_prot;
+ assign io_mmio_ar_bits_qos = outmemsys_io_mmio_ar_bits_qos;
+ assign io_mmio_ar_bits_region = outmemsys_io_mmio_ar_bits_region;
+ assign io_mmio_ar_bits_id = outmemsys_io_mmio_ar_bits_id;
+ assign io_mmio_ar_bits_user = outmemsys_io_mmio_ar_bits_user;
+ assign io_mmio_r_ready = outmemsys_io_mmio_r_ready;
+ assign io_dma_0_req_ready = GEN_71;
+ assign io_dma_0_resp_valid = GEN_72;
+ assign io_dma_0_resp_bits_client_xact_id = GEN_73;
+ assign io_dma_0_resp_bits_status = GEN_74;
+ assign htif_clk = clk;
+ assign htif_reset = reset;
+ assign htif_io_host_in_valid = T_8392;
+ assign htif_io_host_in_bits = T_8366_io_in_fast_bits;
+ assign htif_io_host_out_ready = T_8366_io_out_fast_ready;
+ assign htif_io_cpu_0_csr_req_ready = T_8362_io_in_0_req_ready;
+ assign htif_io_cpu_0_csr_resp_valid = T_8362_io_in_0_resp_valid;
+ assign htif_io_cpu_0_csr_resp_bits = T_8362_io_in_0_resp_bits;
+ assign htif_io_cpu_0_debug_stats_csr = io_htif_0_debug_stats_csr;
+ assign htif_io_mem_acquire_ready = outmemsys_io_htif_uncached_acquire_ready;
+ assign htif_io_mem_grant_valid = outmemsys_io_htif_uncached_grant_valid;
+ assign htif_io_mem_grant_bits_addr_beat = outmemsys_io_htif_uncached_grant_bits_addr_beat;
+ assign htif_io_mem_grant_bits_client_xact_id = outmemsys_io_htif_uncached_grant_bits_client_xact_id;
+ assign htif_io_mem_grant_bits_manager_xact_id = outmemsys_io_htif_uncached_grant_bits_manager_xact_id;
+ assign htif_io_mem_grant_bits_is_builtin_type = outmemsys_io_htif_uncached_grant_bits_is_builtin_type;
+ assign htif_io_mem_grant_bits_g_type = outmemsys_io_htif_uncached_grant_bits_g_type;
+ assign htif_io_mem_grant_bits_data = outmemsys_io_htif_uncached_grant_bits_data;
+ assign htif_io_scr_req_ready = scrArb_io_in_0_req_ready;
+ assign htif_io_scr_resp_valid = scrArb_io_in_0_resp_valid;
+ assign htif_io_scr_resp_bits = scrArb_io_in_0_resp_bits;
+ assign outmemsys_clk = clk;
+ assign outmemsys_reset = reset;
+ assign outmemsys_io_tiles_cached_0_acquire_valid = io_tiles_cached_0_acquire_valid;
+ assign outmemsys_io_tiles_cached_0_acquire_bits_addr_block = io_tiles_cached_0_acquire_bits_addr_block;
+ assign outmemsys_io_tiles_cached_0_acquire_bits_client_xact_id = io_tiles_cached_0_acquire_bits_client_xact_id;
+ assign outmemsys_io_tiles_cached_0_acquire_bits_addr_beat = io_tiles_cached_0_acquire_bits_addr_beat;
+ assign outmemsys_io_tiles_cached_0_acquire_bits_is_builtin_type = io_tiles_cached_0_acquire_bits_is_builtin_type;
+ assign outmemsys_io_tiles_cached_0_acquire_bits_a_type = io_tiles_cached_0_acquire_bits_a_type;
+ assign outmemsys_io_tiles_cached_0_acquire_bits_union = io_tiles_cached_0_acquire_bits_union;
+ assign outmemsys_io_tiles_cached_0_acquire_bits_data = io_tiles_cached_0_acquire_bits_data;
+ assign outmemsys_io_tiles_cached_0_grant_ready = io_tiles_cached_0_grant_ready;
+ assign outmemsys_io_tiles_cached_0_probe_ready = io_tiles_cached_0_probe_ready;
+ assign outmemsys_io_tiles_cached_0_release_valid = io_tiles_cached_0_release_valid;
+ assign outmemsys_io_tiles_cached_0_release_bits_addr_beat = io_tiles_cached_0_release_bits_addr_beat;
+ assign outmemsys_io_tiles_cached_0_release_bits_addr_block = io_tiles_cached_0_release_bits_addr_block;
+ assign outmemsys_io_tiles_cached_0_release_bits_client_xact_id = io_tiles_cached_0_release_bits_client_xact_id;
+ assign outmemsys_io_tiles_cached_0_release_bits_voluntary = io_tiles_cached_0_release_bits_voluntary;
+ assign outmemsys_io_tiles_cached_0_release_bits_r_type = io_tiles_cached_0_release_bits_r_type;
+ assign outmemsys_io_tiles_cached_0_release_bits_data = io_tiles_cached_0_release_bits_data;
+ assign outmemsys_io_tiles_uncached_0_acquire_valid = io_tiles_uncached_0_acquire_valid;
+ assign outmemsys_io_tiles_uncached_0_acquire_bits_addr_block = io_tiles_uncached_0_acquire_bits_addr_block;
+ assign outmemsys_io_tiles_uncached_0_acquire_bits_client_xact_id = io_tiles_uncached_0_acquire_bits_client_xact_id;
+ assign outmemsys_io_tiles_uncached_0_acquire_bits_addr_beat = io_tiles_uncached_0_acquire_bits_addr_beat;
+ assign outmemsys_io_tiles_uncached_0_acquire_bits_is_builtin_type = io_tiles_uncached_0_acquire_bits_is_builtin_type;
+ assign outmemsys_io_tiles_uncached_0_acquire_bits_a_type = io_tiles_uncached_0_acquire_bits_a_type;
+ assign outmemsys_io_tiles_uncached_0_acquire_bits_union = io_tiles_uncached_0_acquire_bits_union;
+ assign outmemsys_io_tiles_uncached_0_acquire_bits_data = io_tiles_uncached_0_acquire_bits_data;
+ assign outmemsys_io_tiles_uncached_0_grant_ready = io_tiles_uncached_0_grant_ready;
+ assign outmemsys_io_htif_uncached_acquire_valid = htif_io_mem_acquire_valid;
+ assign outmemsys_io_htif_uncached_acquire_bits_addr_block = htif_io_mem_acquire_bits_addr_block;
+ assign outmemsys_io_htif_uncached_acquire_bits_client_xact_id = htif_io_mem_acquire_bits_client_xact_id;
+ assign outmemsys_io_htif_uncached_acquire_bits_addr_beat = htif_io_mem_acquire_bits_addr_beat;
+ assign outmemsys_io_htif_uncached_acquire_bits_is_builtin_type = htif_io_mem_acquire_bits_is_builtin_type;
+ assign outmemsys_io_htif_uncached_acquire_bits_a_type = htif_io_mem_acquire_bits_a_type;
+ assign outmemsys_io_htif_uncached_acquire_bits_union = htif_io_mem_acquire_bits_union;
+ assign outmemsys_io_htif_uncached_acquire_bits_data = htif_io_mem_acquire_bits_data;
+ assign outmemsys_io_htif_uncached_grant_ready = htif_io_mem_grant_ready;
+ assign outmemsys_io_incoherent_0 = htif_io_cpu_0_reset;
+ assign outmemsys_io_mem_0_aw_ready = io_mem_0_aw_ready;
+ assign outmemsys_io_mem_0_w_ready = io_mem_0_w_ready;
+ assign outmemsys_io_mem_0_b_valid = io_mem_0_b_valid;
+ assign outmemsys_io_mem_0_b_bits_resp = io_mem_0_b_bits_resp;
+ assign outmemsys_io_mem_0_b_bits_id = io_mem_0_b_bits_id;
+ assign outmemsys_io_mem_0_b_bits_user = io_mem_0_b_bits_user;
+ assign outmemsys_io_mem_0_ar_ready = io_mem_0_ar_ready;
+ assign outmemsys_io_mem_0_r_valid = io_mem_0_r_valid;
+ assign outmemsys_io_mem_0_r_bits_resp = io_mem_0_r_bits_resp;
+ assign outmemsys_io_mem_0_r_bits_data = io_mem_0_r_bits_data;
+ assign outmemsys_io_mem_0_r_bits_last = io_mem_0_r_bits_last;
+ assign outmemsys_io_mem_0_r_bits_id = io_mem_0_r_bits_id;
+ assign outmemsys_io_mem_0_r_bits_user = io_mem_0_r_bits_user;
+ assign outmemsys_io_mem_backup_req_ready = T_8375;
+ assign outmemsys_io_mem_backup_resp_valid = T_8388;
+ assign outmemsys_io_mem_backup_resp_bits = T_8366_io_in_fast_bits;
+ assign outmemsys_io_mem_backup_en = io_mem_backup_ctrl_en;
+ assign outmemsys_io_csr_0_req_ready = T_8362_io_in_1_req_ready;
+ assign outmemsys_io_csr_0_resp_valid = T_8362_io_in_1_resp_valid;
+ assign outmemsys_io_csr_0_resp_bits = T_8362_io_in_1_resp_bits;
+ assign outmemsys_io_scr_req_ready = scrArb_io_in_1_req_ready;
+ assign outmemsys_io_scr_resp_valid = scrArb_io_in_1_resp_valid;
+ assign outmemsys_io_scr_resp_bits = scrArb_io_in_1_resp_bits;
+ assign outmemsys_io_mmio_aw_ready = io_mmio_aw_ready;
+ assign outmemsys_io_mmio_w_ready = io_mmio_w_ready;
+ assign outmemsys_io_mmio_b_valid = io_mmio_b_valid;
+ assign outmemsys_io_mmio_b_bits_resp = io_mmio_b_bits_resp;
+ assign outmemsys_io_mmio_b_bits_id = io_mmio_b_bits_id;
+ assign outmemsys_io_mmio_b_bits_user = io_mmio_b_bits_user;
+ assign outmemsys_io_mmio_ar_ready = io_mmio_ar_ready;
+ assign outmemsys_io_mmio_r_valid = io_mmio_r_valid;
+ assign outmemsys_io_mmio_r_bits_resp = io_mmio_r_bits_resp;
+ assign outmemsys_io_mmio_r_bits_data = io_mmio_r_bits_data;
+ assign outmemsys_io_mmio_r_bits_last = io_mmio_r_bits_last;
+ assign outmemsys_io_mmio_r_bits_id = io_mmio_r_bits_id;
+ assign outmemsys_io_mmio_r_bits_user = io_mmio_r_bits_user;
+ assign outmemsys_io_deviceTree_aw_ready = deviceTree_io_aw_ready;
+ assign outmemsys_io_deviceTree_w_ready = deviceTree_io_w_ready;
+ assign outmemsys_io_deviceTree_b_valid = deviceTree_io_b_valid;
+ assign outmemsys_io_deviceTree_b_bits_resp = deviceTree_io_b_bits_resp;
+ assign outmemsys_io_deviceTree_b_bits_id = deviceTree_io_b_bits_id;
+ assign outmemsys_io_deviceTree_b_bits_user = deviceTree_io_b_bits_user;
+ assign outmemsys_io_deviceTree_ar_ready = deviceTree_io_ar_ready;
+ assign outmemsys_io_deviceTree_r_valid = deviceTree_io_r_valid;
+ assign outmemsys_io_deviceTree_r_bits_resp = deviceTree_io_r_bits_resp;
+ assign outmemsys_io_deviceTree_r_bits_data = deviceTree_io_r_bits_data;
+ assign outmemsys_io_deviceTree_r_bits_last = deviceTree_io_r_bits_last;
+ assign outmemsys_io_deviceTree_r_bits_id = deviceTree_io_r_bits_id;
+ assign outmemsys_io_deviceTree_r_bits_user = deviceTree_io_r_bits_user;
+ assign outmemsys_io_dma_req_valid = GEN_0;
+ assign outmemsys_io_dma_req_bits_client_xact_id = GEN_1;
+ assign outmemsys_io_dma_req_bits_cmd = GEN_2;
+ assign outmemsys_io_dma_req_bits_source = GEN_3;
+ assign outmemsys_io_dma_req_bits_dest = GEN_4;
+ assign outmemsys_io_dma_req_bits_length = GEN_5;
+ assign outmemsys_io_dma_req_bits_size = GEN_6;
+ assign outmemsys_io_dma_resp_ready = GEN_7;
+ assign T_8362_clk = clk;
+ assign T_8362_reset = reset;
+ assign T_8362_io_in_0_req_valid = htif_io_cpu_0_csr_req_valid;
+ assign T_8362_io_in_0_req_bits_rw = htif_io_cpu_0_csr_req_bits_rw;
+ assign T_8362_io_in_0_req_bits_addr = htif_io_cpu_0_csr_req_bits_addr;
+ assign T_8362_io_in_0_req_bits_data = htif_io_cpu_0_csr_req_bits_data;
+ assign T_8362_io_in_0_resp_ready = htif_io_cpu_0_csr_resp_ready;
+ assign T_8362_io_in_1_req_valid = outmemsys_io_csr_0_req_valid;
+ assign T_8362_io_in_1_req_bits_rw = outmemsys_io_csr_0_req_bits_rw;
+ assign T_8362_io_in_1_req_bits_addr = outmemsys_io_csr_0_req_bits_addr;
+ assign T_8362_io_in_1_req_bits_data = outmemsys_io_csr_0_req_bits_data;
+ assign T_8362_io_in_1_resp_ready = outmemsys_io_csr_0_resp_ready;
+ assign T_8362_io_out_req_ready = io_htif_0_csr_req_ready;
+ assign T_8362_io_out_resp_valid = io_htif_0_csr_resp_valid;
+ assign T_8362_io_out_resp_bits = io_htif_0_csr_resp_bits;
+ assign scrFile_clk = clk;
+ assign scrFile_reset = reset;
+ assign scrFile_io_smi_req_valid = scrArb_io_out_req_valid;
+ assign scrFile_io_smi_req_bits_rw = scrArb_io_out_req_bits_rw;
+ assign scrFile_io_smi_req_bits_addr = scrArb_io_out_req_bits_addr;
+ assign scrFile_io_smi_req_bits_data = scrArb_io_out_req_bits_data;
+ assign scrFile_io_smi_resp_ready = scrArb_io_out_resp_ready;
+ assign scrFile_io_scr_rdata_0 = GEN_8;
+ assign scrFile_io_scr_rdata_1 = GEN_9;
+ assign scrFile_io_scr_rdata_2 = GEN_10;
+ assign scrFile_io_scr_rdata_3 = GEN_11;
+ assign scrFile_io_scr_rdata_4 = GEN_12;
+ assign scrFile_io_scr_rdata_5 = GEN_13;
+ assign scrFile_io_scr_rdata_6 = GEN_14;
+ assign scrFile_io_scr_rdata_7 = GEN_15;
+ assign scrFile_io_scr_rdata_8 = GEN_16;
+ assign scrFile_io_scr_rdata_9 = GEN_17;
+ assign scrFile_io_scr_rdata_10 = GEN_18;
+ assign scrFile_io_scr_rdata_11 = GEN_19;
+ assign scrFile_io_scr_rdata_12 = GEN_20;
+ assign scrFile_io_scr_rdata_13 = GEN_21;
+ assign scrFile_io_scr_rdata_14 = GEN_22;
+ assign scrFile_io_scr_rdata_15 = GEN_23;
+ assign scrFile_io_scr_rdata_16 = GEN_24;
+ assign scrFile_io_scr_rdata_17 = GEN_25;
+ assign scrFile_io_scr_rdata_18 = GEN_26;
+ assign scrFile_io_scr_rdata_19 = GEN_27;
+ assign scrFile_io_scr_rdata_20 = GEN_28;
+ assign scrFile_io_scr_rdata_21 = GEN_29;
+ assign scrFile_io_scr_rdata_22 = GEN_30;
+ assign scrFile_io_scr_rdata_23 = GEN_31;
+ assign scrFile_io_scr_rdata_24 = GEN_32;
+ assign scrFile_io_scr_rdata_25 = GEN_33;
+ assign scrFile_io_scr_rdata_26 = GEN_34;
+ assign scrFile_io_scr_rdata_27 = GEN_35;
+ assign scrFile_io_scr_rdata_28 = GEN_36;
+ assign scrFile_io_scr_rdata_29 = GEN_37;
+ assign scrFile_io_scr_rdata_30 = GEN_38;
+ assign scrFile_io_scr_rdata_31 = GEN_39;
+ assign scrFile_io_scr_rdata_32 = GEN_40;
+ assign scrFile_io_scr_rdata_33 = GEN_41;
+ assign scrFile_io_scr_rdata_34 = GEN_42;
+ assign scrFile_io_scr_rdata_35 = GEN_43;
+ assign scrFile_io_scr_rdata_36 = GEN_44;
+ assign scrFile_io_scr_rdata_37 = GEN_45;
+ assign scrFile_io_scr_rdata_38 = GEN_46;
+ assign scrFile_io_scr_rdata_39 = GEN_47;
+ assign scrFile_io_scr_rdata_40 = GEN_48;
+ assign scrFile_io_scr_rdata_41 = GEN_49;
+ assign scrFile_io_scr_rdata_42 = GEN_50;
+ assign scrFile_io_scr_rdata_43 = GEN_51;
+ assign scrFile_io_scr_rdata_44 = GEN_52;
+ assign scrFile_io_scr_rdata_45 = GEN_53;
+ assign scrFile_io_scr_rdata_46 = GEN_54;
+ assign scrFile_io_scr_rdata_47 = GEN_55;
+ assign scrFile_io_scr_rdata_48 = GEN_56;
+ assign scrFile_io_scr_rdata_49 = GEN_57;
+ assign scrFile_io_scr_rdata_50 = GEN_58;
+ assign scrFile_io_scr_rdata_51 = GEN_59;
+ assign scrFile_io_scr_rdata_52 = GEN_60;
+ assign scrFile_io_scr_rdata_53 = GEN_61;
+ assign scrFile_io_scr_rdata_54 = GEN_62;
+ assign scrFile_io_scr_rdata_55 = GEN_63;
+ assign scrFile_io_scr_rdata_56 = GEN_64;
+ assign scrFile_io_scr_rdata_57 = GEN_65;
+ assign scrFile_io_scr_rdata_58 = GEN_66;
+ assign scrFile_io_scr_rdata_59 = GEN_67;
+ assign scrFile_io_scr_rdata_60 = GEN_68;
+ assign scrFile_io_scr_rdata_61 = GEN_69;
+ assign scrFile_io_scr_rdata_62 = GEN_70;
+ assign scrFile_io_scr_rdata_63 = T_8366_io_divisor;
+ assign scrArb_clk = clk;
+ assign scrArb_reset = reset;
+ assign scrArb_io_in_0_req_valid = htif_io_scr_req_valid;
+ assign scrArb_io_in_0_req_bits_rw = htif_io_scr_req_bits_rw;
+ assign scrArb_io_in_0_req_bits_addr = htif_io_scr_req_bits_addr;
+ assign scrArb_io_in_0_req_bits_data = htif_io_scr_req_bits_data;
+ assign scrArb_io_in_0_resp_ready = htif_io_scr_resp_ready;
+ assign scrArb_io_in_1_req_valid = outmemsys_io_scr_req_valid;
+ assign scrArb_io_in_1_req_bits_rw = outmemsys_io_scr_req_bits_rw;
+ assign scrArb_io_in_1_req_bits_addr = outmemsys_io_scr_req_bits_addr;
+ assign scrArb_io_in_1_req_bits_data = outmemsys_io_scr_req_bits_data;
+ assign scrArb_io_in_1_resp_ready = outmemsys_io_scr_resp_ready;
+ assign scrArb_io_out_req_ready = scrFile_io_smi_req_ready;
+ assign scrArb_io_out_resp_valid = scrFile_io_smi_resp_valid;
+ assign scrArb_io_out_resp_bits = scrFile_io_smi_resp_bits;
+ assign deviceTree_clk = clk;
+ assign deviceTree_reset = reset;
+ assign deviceTree_io_aw_valid = outmemsys_io_deviceTree_aw_valid;
+ assign deviceTree_io_aw_bits_addr = outmemsys_io_deviceTree_aw_bits_addr;
+ assign deviceTree_io_aw_bits_len = outmemsys_io_deviceTree_aw_bits_len;
+ assign deviceTree_io_aw_bits_size = outmemsys_io_deviceTree_aw_bits_size;
+ assign deviceTree_io_aw_bits_burst = outmemsys_io_deviceTree_aw_bits_burst;
+ assign deviceTree_io_aw_bits_lock = outmemsys_io_deviceTree_aw_bits_lock;
+ assign deviceTree_io_aw_bits_cache = outmemsys_io_deviceTree_aw_bits_cache;
+ assign deviceTree_io_aw_bits_prot = outmemsys_io_deviceTree_aw_bits_prot;
+ assign deviceTree_io_aw_bits_qos = outmemsys_io_deviceTree_aw_bits_qos;
+ assign deviceTree_io_aw_bits_region = outmemsys_io_deviceTree_aw_bits_region;
+ assign deviceTree_io_aw_bits_id = outmemsys_io_deviceTree_aw_bits_id;
+ assign deviceTree_io_aw_bits_user = outmemsys_io_deviceTree_aw_bits_user;
+ assign deviceTree_io_w_valid = outmemsys_io_deviceTree_w_valid;
+ assign deviceTree_io_w_bits_data = outmemsys_io_deviceTree_w_bits_data;
+ assign deviceTree_io_w_bits_last = outmemsys_io_deviceTree_w_bits_last;
+ assign deviceTree_io_w_bits_strb = outmemsys_io_deviceTree_w_bits_strb;
+ assign deviceTree_io_w_bits_user = outmemsys_io_deviceTree_w_bits_user;
+ assign deviceTree_io_b_ready = outmemsys_io_deviceTree_b_ready;
+ assign deviceTree_io_ar_valid = outmemsys_io_deviceTree_ar_valid;
+ assign deviceTree_io_ar_bits_addr = outmemsys_io_deviceTree_ar_bits_addr;
+ assign deviceTree_io_ar_bits_len = outmemsys_io_deviceTree_ar_bits_len;
+ assign deviceTree_io_ar_bits_size = outmemsys_io_deviceTree_ar_bits_size;
+ assign deviceTree_io_ar_bits_burst = outmemsys_io_deviceTree_ar_bits_burst;
+ assign deviceTree_io_ar_bits_lock = outmemsys_io_deviceTree_ar_bits_lock;
+ assign deviceTree_io_ar_bits_cache = outmemsys_io_deviceTree_ar_bits_cache;
+ assign deviceTree_io_ar_bits_prot = outmemsys_io_deviceTree_ar_bits_prot;
+ assign deviceTree_io_ar_bits_qos = outmemsys_io_deviceTree_ar_bits_qos;
+ assign deviceTree_io_ar_bits_region = outmemsys_io_deviceTree_ar_bits_region;
+ assign deviceTree_io_ar_bits_id = outmemsys_io_deviceTree_ar_bits_id;
+ assign deviceTree_io_ar_bits_user = outmemsys_io_deviceTree_ar_bits_user;
+ assign deviceTree_io_r_ready = outmemsys_io_deviceTree_r_ready;
+ assign T_8366_clk = clk;
+ assign T_8366_reset = reset;
+ assign T_8366_io_out_fast_valid = T_8370;
+ assign T_8366_io_out_fast_bits = T_8372;
+ assign T_8366_io_out_slow_ready = T_8383;
+ assign T_8366_io_in_fast_ready = T_8395;
+ assign T_8366_io_in_slow_valid = T_8385;
+ assign T_8366_io_in_slow_bits = T_8386;
+ assign T_8366_io_set_divisor_valid = T_8369;
+ assign T_8366_io_set_divisor_bits = scrFile_io_scr_wdata;
+ assign T_8368 = scrFile_io_scr_waddr == 6'h3f;
+ assign T_8369 = scrFile_io_scr_wen & T_8368;
+ assign T_8370 = htif_io_host_out_valid | outmemsys_io_mem_backup_req_valid;
+ assign T_8371 = htif_io_host_out_valid ? htif_io_host_out_bits : outmemsys_io_mem_backup_req_bits;
+ assign T_8372 = {htif_io_host_out_valid,T_8371};
+ assign T_8374 = htif_io_host_out_valid == 1'h0;
+ assign T_8375 = T_8366_io_out_fast_ready & T_8374;
+ assign T_8376 = T_8366_io_out_slow_bits[16];
+ assign T_8377 = T_8366_io_out_slow_valid & T_8376;
+ assign T_8378 = T_8366_io_out_slow_bits[16];
+ assign T_8380 = T_8378 == 1'h0;
+ assign T_8381 = T_8366_io_out_slow_valid & T_8380;
+ assign T_8382 = T_8366_io_out_slow_bits[16];
+ assign T_8383 = T_8382 ? io_host_out_ready : io_mem_backup_ctrl_out_ready;
+ assign T_8384 = io_mem_backup_ctrl_en & io_mem_backup_ctrl_in_valid;
+ assign T_8385 = T_8384 | io_host_in_valid;
+ assign T_8386 = {T_8384,io_host_in_bits};
+ assign T_8387 = T_8366_io_in_fast_bits[16];
+ assign T_8388 = T_8366_io_in_fast_valid & T_8387;
+ assign T_8389 = T_8366_io_in_fast_bits[16];
+ assign T_8391 = T_8389 == 1'h0;
+ assign T_8392 = T_8366_io_in_fast_valid & T_8391;
+ assign T_8393 = T_8366_io_in_fast_bits[16];
+ assign T_8395 = T_8393 ? 1'h1 : htif_io_host_in_ready;
+ assign T_8398 = T_8396 == 1'h0;
+ assign T_8399 = io_host_clk & T_8398;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_8396 = {1{$random}};
+ T_8400 = {1{$random}};
+ GEN_0 = {1{$random}};
+ GEN_1 = {1{$random}};
+ GEN_2 = {1{$random}};
+ GEN_3 = {1{$random}};
+ GEN_4 = {1{$random}};
+ GEN_5 = {1{$random}};
+ GEN_6 = {1{$random}};
+ GEN_7 = {1{$random}};
+ GEN_8 = {2{$random}};
+ GEN_9 = {2{$random}};
+ GEN_10 = {2{$random}};
+ GEN_11 = {2{$random}};
+ GEN_12 = {2{$random}};
+ GEN_13 = {2{$random}};
+ GEN_14 = {2{$random}};
+ GEN_15 = {2{$random}};
+ GEN_16 = {2{$random}};
+ GEN_17 = {2{$random}};
+ GEN_18 = {2{$random}};
+ GEN_19 = {2{$random}};
+ GEN_20 = {2{$random}};
+ GEN_21 = {2{$random}};
+ GEN_22 = {2{$random}};
+ GEN_23 = {2{$random}};
+ GEN_24 = {2{$random}};
+ GEN_25 = {2{$random}};
+ GEN_26 = {2{$random}};
+ GEN_27 = {2{$random}};
+ GEN_28 = {2{$random}};
+ GEN_29 = {2{$random}};
+ GEN_30 = {2{$random}};
+ GEN_31 = {2{$random}};
+ GEN_32 = {2{$random}};
+ GEN_33 = {2{$random}};
+ GEN_34 = {2{$random}};
+ GEN_35 = {2{$random}};
+ GEN_36 = {2{$random}};
+ GEN_37 = {2{$random}};
+ GEN_38 = {2{$random}};
+ GEN_39 = {2{$random}};
+ GEN_40 = {2{$random}};
+ GEN_41 = {2{$random}};
+ GEN_42 = {2{$random}};
+ GEN_43 = {2{$random}};
+ GEN_44 = {2{$random}};
+ GEN_45 = {2{$random}};
+ GEN_46 = {2{$random}};
+ GEN_47 = {2{$random}};
+ GEN_48 = {2{$random}};
+ GEN_49 = {2{$random}};
+ GEN_50 = {2{$random}};
+ GEN_51 = {2{$random}};
+ GEN_52 = {2{$random}};
+ GEN_53 = {2{$random}};
+ GEN_54 = {2{$random}};
+ GEN_55 = {2{$random}};
+ GEN_56 = {2{$random}};
+ GEN_57 = {2{$random}};
+ GEN_58 = {2{$random}};
+ GEN_59 = {2{$random}};
+ GEN_60 = {2{$random}};
+ GEN_61 = {2{$random}};
+ GEN_62 = {2{$random}};
+ GEN_63 = {2{$random}};
+ GEN_64 = {2{$random}};
+ GEN_65 = {2{$random}};
+ GEN_66 = {2{$random}};
+ GEN_67 = {2{$random}};
+ GEN_68 = {2{$random}};
+ GEN_69 = {2{$random}};
+ GEN_70 = {2{$random}};
+ GEN_71 = {1{$random}};
+ GEN_72 = {1{$random}};
+ GEN_73 = {1{$random}};
+ GEN_74 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(1'h0) begin
+ ;
+ end else begin
+ T_8396 <= io_host_clk;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ T_8400 <= T_8399;
+ end
+ end
+endmodule
+module CSRFile(
+ input clk,
+ input reset,
+ input io_host_reset,
+ input io_host_id,
+ output io_host_csr_req_ready,
+ input io_host_csr_req_valid,
+ input io_host_csr_req_bits_rw,
+ input [11:0] io_host_csr_req_bits_addr,
+ input [63:0] io_host_csr_req_bits_data,
+ input io_host_csr_resp_ready,
+ output io_host_csr_resp_valid,
+ output [63:0] io_host_csr_resp_bits,
+ output io_host_debug_stats_csr,
+ input [11:0] io_rw_addr,
+ input [2:0] io_rw_cmd,
+ output [63:0] io_rw_rdata,
+ input [63:0] io_rw_wdata,
+ output io_csr_stall,
+ output io_csr_xcpt,
+ output io_eret,
+ output io_status_sd,
+ output [30:0] io_status_zero2,
+ output io_status_sd_rv32,
+ output [8:0] io_status_zero1,
+ output [4:0] io_status_vm,
+ output io_status_mprv,
+ output [1:0] io_status_xs,
+ output [1:0] io_status_fs,
+ output [1:0] io_status_prv3,
+ output io_status_ie3,
+ output [1:0] io_status_prv2,
+ output io_status_ie2,
+ output [1:0] io_status_prv1,
+ output io_status_ie1,
+ output [1:0] io_status_prv,
+ output io_status_ie,
+ output [31:0] io_ptbr,
+ output [39:0] io_evec,
+ input io_exception,
+ input io_retire,
+ input io_uarch_counters_0,
+ input io_uarch_counters_1,
+ input io_uarch_counters_2,
+ input io_uarch_counters_3,
+ input io_uarch_counters_4,
+ input io_uarch_counters_5,
+ input io_uarch_counters_6,
+ input io_uarch_counters_7,
+ input io_uarch_counters_8,
+ input io_uarch_counters_9,
+ input io_uarch_counters_10,
+ input io_uarch_counters_11,
+ input io_uarch_counters_12,
+ input io_uarch_counters_13,
+ input io_uarch_counters_14,
+ input io_uarch_counters_15,
+ input [63:0] io_cause,
+ input [39:0] io_pc,
+ output io_fatc,
+ output [63:0] io_time,
+ output [2:0] io_fcsr_rm,
+ input io_fcsr_flags_valid,
+ input [4:0] io_fcsr_flags_bits,
+ input io_rocc_cmd_ready,
+ output io_rocc_cmd_valid,
+ output [6:0] io_rocc_cmd_bits_inst_funct,
+ output [4:0] io_rocc_cmd_bits_inst_rs2,
+ output [4:0] io_rocc_cmd_bits_inst_rs1,
+ output io_rocc_cmd_bits_inst_xd,
+ output io_rocc_cmd_bits_inst_xs1,
+ output io_rocc_cmd_bits_inst_xs2,
+ output [4:0] io_rocc_cmd_bits_inst_rd,
+ output [6:0] io_rocc_cmd_bits_inst_opcode,
+ output [63:0] io_rocc_cmd_bits_rs1,
+ output [63:0] io_rocc_cmd_bits_rs2,
+ output io_rocc_resp_ready,
+ input io_rocc_resp_valid,
+ input [4:0] io_rocc_resp_bits_rd,
+ input [63:0] io_rocc_resp_bits_data,
+ output io_rocc_mem_req_ready,
+ input io_rocc_mem_req_valid,
+ input [39:0] io_rocc_mem_req_bits_addr,
+ input [8:0] io_rocc_mem_req_bits_tag,
+ input [4:0] io_rocc_mem_req_bits_cmd,
+ input [2:0] io_rocc_mem_req_bits_typ,
+ input io_rocc_mem_req_bits_kill,
+ input io_rocc_mem_req_bits_phys,
+ input [63:0] io_rocc_mem_req_bits_data,
+ output io_rocc_mem_resp_valid,
+ output [39:0] io_rocc_mem_resp_bits_addr,
+ output [8:0] io_rocc_mem_resp_bits_tag,
+ output [4:0] io_rocc_mem_resp_bits_cmd,
+ output [2:0] io_rocc_mem_resp_bits_typ,
+ output [63:0] io_rocc_mem_resp_bits_data,
+ output io_rocc_mem_resp_bits_nack,
+ output io_rocc_mem_resp_bits_replay,
+ output io_rocc_mem_resp_bits_has_data,
+ output [63:0] io_rocc_mem_resp_bits_data_word_bypass,
+ output [63:0] io_rocc_mem_resp_bits_store_data,
+ output io_rocc_mem_replay_next_valid,
+ output [8:0] io_rocc_mem_replay_next_bits,
+ output io_rocc_mem_xcpt_ma_ld,
+ output io_rocc_mem_xcpt_ma_st,
+ output io_rocc_mem_xcpt_pf_ld,
+ output io_rocc_mem_xcpt_pf_st,
+ input io_rocc_mem_invalidate_lr,
+ output io_rocc_mem_ordered,
+ input io_rocc_busy,
+ output io_rocc_s,
+ input io_rocc_interrupt,
+ output io_rocc_autl_acquire_ready,
+ input io_rocc_autl_acquire_valid,
+ input [25:0] io_rocc_autl_acquire_bits_addr_block,
+ input [1:0] io_rocc_autl_acquire_bits_client_xact_id,
+ input [1:0] io_rocc_autl_acquire_bits_addr_beat,
+ input io_rocc_autl_acquire_bits_is_builtin_type,
+ input [2:0] io_rocc_autl_acquire_bits_a_type,
+ input [16:0] io_rocc_autl_acquire_bits_union,
+ input [127:0] io_rocc_autl_acquire_bits_data,
+ input io_rocc_autl_grant_ready,
+ output io_rocc_autl_grant_valid,
+ output [1:0] io_rocc_autl_grant_bits_addr_beat,
+ output [1:0] io_rocc_autl_grant_bits_client_xact_id,
+ output [3:0] io_rocc_autl_grant_bits_manager_xact_id,
+ output io_rocc_autl_grant_bits_is_builtin_type,
+ output [3:0] io_rocc_autl_grant_bits_g_type,
+ output [127:0] io_rocc_autl_grant_bits_data,
+ output io_rocc_iptw_req_ready,
+ input io_rocc_iptw_req_valid,
+ input [26:0] io_rocc_iptw_req_bits_addr,
+ input [1:0] io_rocc_iptw_req_bits_prv,
+ input io_rocc_iptw_req_bits_store,
+ input io_rocc_iptw_req_bits_fetch,
+ output io_rocc_iptw_resp_valid,
+ output io_rocc_iptw_resp_bits_error,
+ output [19:0] io_rocc_iptw_resp_bits_pte_ppn,
+ output [2:0] io_rocc_iptw_resp_bits_pte_reserved_for_software,
+ output io_rocc_iptw_resp_bits_pte_d,
+ output io_rocc_iptw_resp_bits_pte_r,
+ output [3:0] io_rocc_iptw_resp_bits_pte_typ,
+ output io_rocc_iptw_resp_bits_pte_v,
+ output io_rocc_iptw_status_sd,
+ output [30:0] io_rocc_iptw_status_zero2,
+ output io_rocc_iptw_status_sd_rv32,
+ output [8:0] io_rocc_iptw_status_zero1,
+ output [4:0] io_rocc_iptw_status_vm,
+ output io_rocc_iptw_status_mprv,
+ output [1:0] io_rocc_iptw_status_xs,
+ output [1:0] io_rocc_iptw_status_fs,
+ output [1:0] io_rocc_iptw_status_prv3,
+ output io_rocc_iptw_status_ie3,
+ output [1:0] io_rocc_iptw_status_prv2,
+ output io_rocc_iptw_status_ie2,
+ output [1:0] io_rocc_iptw_status_prv1,
+ output io_rocc_iptw_status_ie1,
+ output [1:0] io_rocc_iptw_status_prv,
+ output io_rocc_iptw_status_ie,
+ output io_rocc_iptw_invalidate,
+ output io_rocc_dptw_req_ready,
+ input io_rocc_dptw_req_valid,
+ input [26:0] io_rocc_dptw_req_bits_addr,
+ input [1:0] io_rocc_dptw_req_bits_prv,
+ input io_rocc_dptw_req_bits_store,
+ input io_rocc_dptw_req_bits_fetch,
+ output io_rocc_dptw_resp_valid,
+ output io_rocc_dptw_resp_bits_error,
+ output [19:0] io_rocc_dptw_resp_bits_pte_ppn,
+ output [2:0] io_rocc_dptw_resp_bits_pte_reserved_for_software,
+ output io_rocc_dptw_resp_bits_pte_d,
+ output io_rocc_dptw_resp_bits_pte_r,
+ output [3:0] io_rocc_dptw_resp_bits_pte_typ,
+ output io_rocc_dptw_resp_bits_pte_v,
+ output io_rocc_dptw_status_sd,
+ output [30:0] io_rocc_dptw_status_zero2,
+ output io_rocc_dptw_status_sd_rv32,
+ output [8:0] io_rocc_dptw_status_zero1,
+ output [4:0] io_rocc_dptw_status_vm,
+ output io_rocc_dptw_status_mprv,
+ output [1:0] io_rocc_dptw_status_xs,
+ output [1:0] io_rocc_dptw_status_fs,
+ output [1:0] io_rocc_dptw_status_prv3,
+ output io_rocc_dptw_status_ie3,
+ output [1:0] io_rocc_dptw_status_prv2,
+ output io_rocc_dptw_status_ie2,
+ output [1:0] io_rocc_dptw_status_prv1,
+ output io_rocc_dptw_status_ie1,
+ output [1:0] io_rocc_dptw_status_prv,
+ output io_rocc_dptw_status_ie,
+ output io_rocc_dptw_invalidate,
+ output io_rocc_pptw_req_ready,
+ input io_rocc_pptw_req_valid,
+ input [26:0] io_rocc_pptw_req_bits_addr,
+ input [1:0] io_rocc_pptw_req_bits_prv,
+ input io_rocc_pptw_req_bits_store,
+ input io_rocc_pptw_req_bits_fetch,
+ output io_rocc_pptw_resp_valid,
+ output io_rocc_pptw_resp_bits_error,
+ output [19:0] io_rocc_pptw_resp_bits_pte_ppn,
+ output [2:0] io_rocc_pptw_resp_bits_pte_reserved_for_software,
+ output io_rocc_pptw_resp_bits_pte_d,
+ output io_rocc_pptw_resp_bits_pte_r,
+ output [3:0] io_rocc_pptw_resp_bits_pte_typ,
+ output io_rocc_pptw_resp_bits_pte_v,
+ output io_rocc_pptw_status_sd,
+ output [30:0] io_rocc_pptw_status_zero2,
+ output io_rocc_pptw_status_sd_rv32,
+ output [8:0] io_rocc_pptw_status_zero1,
+ output [4:0] io_rocc_pptw_status_vm,
+ output io_rocc_pptw_status_mprv,
+ output [1:0] io_rocc_pptw_status_xs,
+ output [1:0] io_rocc_pptw_status_fs,
+ output [1:0] io_rocc_pptw_status_prv3,
+ output io_rocc_pptw_status_ie3,
+ output [1:0] io_rocc_pptw_status_prv2,
+ output io_rocc_pptw_status_ie2,
+ output [1:0] io_rocc_pptw_status_prv1,
+ output io_rocc_pptw_status_ie1,
+ output [1:0] io_rocc_pptw_status_prv,
+ output io_rocc_pptw_status_ie,
+ output io_rocc_pptw_invalidate,
+ output io_rocc_fpu_req_ready,
+ input io_rocc_fpu_req_valid,
+ input [4:0] io_rocc_fpu_req_bits_cmd,
+ input io_rocc_fpu_req_bits_ldst,
+ input io_rocc_fpu_req_bits_wen,
+ input io_rocc_fpu_req_bits_ren1,
+ input io_rocc_fpu_req_bits_ren2,
+ input io_rocc_fpu_req_bits_ren3,
+ input io_rocc_fpu_req_bits_swap12,
+ input io_rocc_fpu_req_bits_swap23,
+ input io_rocc_fpu_req_bits_single,
+ input io_rocc_fpu_req_bits_fromint,
+ input io_rocc_fpu_req_bits_toint,
+ input io_rocc_fpu_req_bits_fastpipe,
+ input io_rocc_fpu_req_bits_fma,
+ input io_rocc_fpu_req_bits_div,
+ input io_rocc_fpu_req_bits_sqrt,
+ input io_rocc_fpu_req_bits_round,
+ input io_rocc_fpu_req_bits_wflags,
+ input [2:0] io_rocc_fpu_req_bits_rm,
+ input [1:0] io_rocc_fpu_req_bits_typ,
+ input [64:0] io_rocc_fpu_req_bits_in1,
+ input [64:0] io_rocc_fpu_req_bits_in2,
+ input [64:0] io_rocc_fpu_req_bits_in3,
+ input io_rocc_fpu_resp_ready,
+ output io_rocc_fpu_resp_valid,
+ output [64:0] io_rocc_fpu_resp_bits_data,
+ output [4:0] io_rocc_fpu_resp_bits_exc,
+ output io_rocc_exception,
+ output io_rocc_dma_req_ready,
+ input io_rocc_dma_req_valid,
+ input [1:0] io_rocc_dma_req_bits_client_xact_id,
+ input [2:0] io_rocc_dma_req_bits_cmd,
+ input [31:0] io_rocc_dma_req_bits_source,
+ input [31:0] io_rocc_dma_req_bits_dest,
+ input [31:0] io_rocc_dma_req_bits_length,
+ input [1:0] io_rocc_dma_req_bits_size,
+ input io_rocc_dma_resp_ready,
+ output io_rocc_dma_resp_valid,
+ output [1:0] io_rocc_dma_resp_bits_client_xact_id,
+ output [1:0] io_rocc_dma_resp_bits_status,
+ output io_interrupt,
+ output [63:0] io_interrupt_cause
+);
+ reg reg_mstatus_sd;
+ reg [30:0] reg_mstatus_zero2;
+ reg reg_mstatus_sd_rv32;
+ reg [8:0] reg_mstatus_zero1;
+ reg [4:0] reg_mstatus_vm;
+ reg reg_mstatus_mprv;
+ reg [1:0] reg_mstatus_xs;
+ reg [1:0] reg_mstatus_fs;
+ reg [1:0] reg_mstatus_prv3;
+ reg reg_mstatus_ie3;
+ reg [1:0] reg_mstatus_prv2;
+ reg reg_mstatus_ie2;
+ reg [1:0] reg_mstatus_prv1;
+ reg reg_mstatus_ie1;
+ reg [1:0] reg_mstatus_prv;
+ reg reg_mstatus_ie;
+ wire T_4480_mtip;
+ wire T_4480_htip;
+ wire T_4480_stip;
+ wire T_4480_utip;
+ wire T_4480_msip;
+ wire T_4480_hsip;
+ wire T_4480_ssip;
+ wire T_4480_usip;
+ reg reg_mie_mtip;
+ reg reg_mie_htip;
+ reg reg_mie_stip;
+ reg reg_mie_utip;
+ reg reg_mie_msip;
+ reg reg_mie_hsip;
+ reg reg_mie_ssip;
+ reg reg_mie_usip;
+ wire T_4525_mtip;
+ wire T_4525_htip;
+ wire T_4525_stip;
+ wire T_4525_utip;
+ wire T_4525_msip;
+ wire T_4525_hsip;
+ wire T_4525_ssip;
+ wire T_4525_usip;
+ reg reg_mip_mtip;
+ reg reg_mip_htip;
+ reg reg_mip_stip;
+ reg reg_mip_utip;
+ reg reg_mip_msip;
+ reg reg_mip_hsip;
+ reg reg_mip_ssip;
+ reg reg_mip_usip;
+ reg [39:0] reg_mepc;
+ reg [63:0] reg_mcause;
+ reg [39:0] reg_mbadaddr;
+ reg [63:0] reg_mscratch;
+ reg [39:0] reg_sepc;
+ reg [63:0] reg_scause;
+ reg [39:0] reg_sbadaddr;
+ reg [63:0] reg_sscratch;
+ reg [38:0] reg_stvec;
+ reg [63:0] reg_mtimecmp;
+ reg [31:0] reg_sptbr;
+ reg reg_wfi;
+ reg [63:0] reg_tohost;
+ reg [63:0] reg_fromhost;
+ reg reg_stats;
+ reg [63:0] reg_time;
+ reg [5:0] T_4584;
+ wire T_4586;
+ wire [7:0] T_4588;
+ wire [6:0] T_4589;
+ wire [5:0] T_4590;
+ reg [57:0] T_4592;
+ wire T_4593;
+ wire T_4594;
+ wire [58:0] T_4596;
+ wire [57:0] T_4597;
+ wire [63:0] T_4598;
+ reg [5:0] T_4601;
+ wire T_4603;
+ wire [7:0] T_4605;
+ wire [6:0] T_4606;
+ wire [5:0] T_4607;
+ reg [57:0] T_4609;
+ wire T_4610;
+ wire T_4611;
+ wire [58:0] T_4613;
+ wire [57:0] T_4614;
+ wire [63:0] T_4615;
+ reg [5:0] T_4617;
+ wire T_4619;
+ wire [7:0] T_4621;
+ wire [6:0] T_4622;
+ wire [5:0] T_4623;
+ reg [57:0] T_4625;
+ wire T_4626;
+ wire T_4627;
+ wire [58:0] T_4629;
+ wire [57:0] T_4630;
+ wire [63:0] T_4631;
+ reg [5:0] T_4633;
+ wire T_4635;
+ wire [7:0] T_4637;
+ wire [6:0] T_4638;
+ wire [5:0] T_4639;
+ reg [57:0] T_4641;
+ wire T_4642;
+ wire T_4643;
+ wire [58:0] T_4645;
+ wire [57:0] T_4646;
+ wire [63:0] T_4647;
+ reg [5:0] T_4649;
+ wire T_4651;
+ wire [7:0] T_4653;
+ wire [6:0] T_4654;
+ wire [5:0] T_4655;
+ reg [57:0] T_4657;
+ wire T_4658;
+ wire T_4659;
+ wire [58:0] T_4661;
+ wire [57:0] T_4662;
+ wire [63:0] T_4663;
+ reg [5:0] T_4665;
+ wire T_4667;
+ wire [7:0] T_4669;
+ wire [6:0] T_4670;
+ wire [5:0] T_4671;
+ reg [57:0] T_4673;
+ wire T_4674;
+ wire T_4675;
+ wire [58:0] T_4677;
+ wire [57:0] T_4678;
+ wire [63:0] T_4679;
+ reg [5:0] T_4681;
+ wire T_4683;
+ wire [7:0] T_4685;
+ wire [6:0] T_4686;
+ wire [5:0] T_4687;
+ reg [57:0] T_4689;
+ wire T_4690;
+ wire T_4691;
+ wire [58:0] T_4693;
+ wire [57:0] T_4694;
+ wire [63:0] T_4695;
+ reg [5:0] T_4697;
+ wire T_4699;
+ wire [7:0] T_4701;
+ wire [6:0] T_4702;
+ wire [5:0] T_4703;
+ reg [57:0] T_4705;
+ wire T_4706;
+ wire T_4707;
+ wire [58:0] T_4709;
+ wire [57:0] T_4710;
+ wire [63:0] T_4711;
+ reg [5:0] T_4713;
+ wire T_4715;
+ wire [7:0] T_4717;
+ wire [6:0] T_4718;
+ wire [5:0] T_4719;
+ reg [57:0] T_4721;
+ wire T_4722;
+ wire T_4723;
+ wire [58:0] T_4725;
+ wire [57:0] T_4726;
+ wire [63:0] T_4727;
+ reg [5:0] T_4729;
+ wire T_4731;
+ wire [7:0] T_4733;
+ wire [6:0] T_4734;
+ wire [5:0] T_4735;
+ reg [57:0] T_4737;
+ wire T_4738;
+ wire T_4739;
+ wire [58:0] T_4741;
+ wire [57:0] T_4742;
+ wire [63:0] T_4743;
+ reg [5:0] T_4745;
+ wire T_4747;
+ wire [7:0] T_4749;
+ wire [6:0] T_4750;
+ wire [5:0] T_4751;
+ reg [57:0] T_4753;
+ wire T_4754;
+ wire T_4755;
+ wire [58:0] T_4757;
+ wire [57:0] T_4758;
+ wire [63:0] T_4759;
+ reg [5:0] T_4761;
+ wire T_4763;
+ wire [7:0] T_4765;
+ wire [6:0] T_4766;
+ wire [5:0] T_4767;
+ reg [57:0] T_4769;
+ wire T_4770;
+ wire T_4771;
+ wire [58:0] T_4773;
+ wire [57:0] T_4774;
+ wire [63:0] T_4775;
+ reg [5:0] T_4777;
+ wire T_4779;
+ wire [7:0] T_4781;
+ wire [6:0] T_4782;
+ wire [5:0] T_4783;
+ reg [57:0] T_4785;
+ wire T_4786;
+ wire T_4787;
+ wire [58:0] T_4789;
+ wire [57:0] T_4790;
+ wire [63:0] T_4791;
+ reg [5:0] T_4793;
+ wire T_4795;
+ wire [7:0] T_4797;
+ wire [6:0] T_4798;
+ wire [5:0] T_4799;
+ reg [57:0] T_4801;
+ wire T_4802;
+ wire T_4803;
+ wire [58:0] T_4805;
+ wire [57:0] T_4806;
+ wire [63:0] T_4807;
+ reg [5:0] T_4809;
+ wire T_4811;
+ wire [7:0] T_4813;
+ wire [6:0] T_4814;
+ wire [5:0] T_4815;
+ reg [57:0] T_4817;
+ wire T_4818;
+ wire T_4819;
+ wire [58:0] T_4821;
+ wire [57:0] T_4822;
+ wire [63:0] T_4823;
+ reg [5:0] T_4825;
+ wire T_4827;
+ wire [7:0] T_4829;
+ wire [6:0] T_4830;
+ wire [5:0] T_4831;
+ reg [57:0] T_4833;
+ wire T_4834;
+ wire T_4835;
+ wire [58:0] T_4837;
+ wire [57:0] T_4838;
+ wire [63:0] T_4839;
+ reg [5:0] T_4841;
+ wire T_4843;
+ wire [7:0] T_4845;
+ wire [6:0] T_4846;
+ wire [5:0] T_4847;
+ reg [57:0] T_4849;
+ wire T_4850;
+ wire T_4851;
+ wire [58:0] T_4853;
+ wire [57:0] T_4854;
+ wire [63:0] T_4855;
+ reg [5:0] T_4857;
+ wire T_4859;
+ wire [7:0] T_4861;
+ wire [6:0] T_4862;
+ wire [5:0] T_4863;
+ reg [57:0] T_4865;
+ wire T_4866;
+ wire T_4867;
+ wire [58:0] T_4869;
+ wire [57:0] T_4870;
+ wire [63:0] T_4871;
+ reg [4:0] reg_fflags;
+ reg [2:0] reg_frm;
+ wire irq_rocc;
+ wire T_4879;
+ wire some_interrupt_pending;
+ wire T_4883;
+ wire T_4884;
+ wire T_4885;
+ wire T_4886;
+ wire T_4887;
+ wire T_4888;
+ wire T_4890;
+ wire T_4891;
+ wire T_4894;
+ wire T_4895;
+ wire T_4896;
+ wire T_4897;
+ wire T_4898;
+ wire T_4899;
+ wire T_4901;
+ wire T_4902;
+ wire T_4905;
+ wire T_4906;
+ wire T_4907;
+ wire T_4908;
+ wire T_4909;
+ wire T_4910;
+ wire T_4912;
+ wire T_4913;
+ wire T_4916;
+ wire T_4917;
+ wire T_4918;
+ wire T_4919;
+ wire T_4920;
+ wire T_4921;
+ wire T_4923;
+ wire T_4924;
+ wire T_4928;
+ wire T_4929;
+ wire T_4930;
+ wire T_4931;
+ wire T_4932;
+ wire T_4933;
+ wire T_4935;
+ wire T_4936;
+ wire T_4939;
+ wire T_4940;
+ wire T_4941;
+ wire T_4942;
+ wire T_4943;
+ wire T_4945;
+ wire T_4946;
+ wire system_insn;
+ wire T_4949;
+ wire T_4951;
+ wire cpu_ren;
+ reg host_csr_req_valid;
+ wire T_4956;
+ wire host_csr_req_fire;
+ reg host_csr_rep_valid;
+ reg host_csr_bits_rw;
+ reg [11:0] host_csr_bits_addr;
+ reg [63:0] host_csr_bits_data;
+ wire T_4965;
+ wire T_4967;
+ wire T_4968;
+ wire T_4969;
+ wire T_4973;
+ wire [31:0] T_4975;
+ wire [9:0] T_4976;
+ wire [41:0] T_4977;
+ wire [5:0] T_4978;
+ wire [3:0] T_4979;
+ wire [9:0] T_4980;
+ wire [51:0] T_4981;
+ wire [2:0] T_4982;
+ wire [2:0] T_4983;
+ wire [5:0] T_4984;
+ wire [2:0] T_4985;
+ wire [2:0] T_4986;
+ wire [5:0] T_4987;
+ wire [11:0] T_4988;
+ wire [63:0] read_mstatus;
+ wire [7:0] T_4990;
+ wire [1:0] T_4998;
+ wire [1:0] T_4999;
+ wire [3:0] T_5000;
+ wire [1:0] T_5001;
+ wire [1:0] T_5002;
+ wire [3:0] T_5003;
+ wire [7:0] T_5004;
+ wire [1:0] T_5005;
+ wire [1:0] T_5006;
+ wire [3:0] T_5007;
+ wire [1:0] T_5008;
+ wire [1:0] T_5009;
+ wire [3:0] T_5010;
+ wire [7:0] T_5011;
+ wire T_5012;
+ wire [24:0] T_5014;
+ wire [23:0] T_5015;
+ wire [63:0] T_5016;
+ wire T_5017;
+ wire [24:0] T_5019;
+ wire [23:0] T_5020;
+ wire [63:0] T_5021;
+ wire T_5048_sd;
+ wire [30:0] T_5048_zero4;
+ wire T_5048_sd_rv32;
+ wire [13:0] T_5048_zero3;
+ wire T_5048_mprv;
+ wire [1:0] T_5048_xs;
+ wire [1:0] T_5048_fs;
+ wire [6:0] T_5048_zero2;
+ wire T_5048_ps;
+ wire T_5048_pie;
+ wire [1:0] T_5048_zero1;
+ wire T_5048_ie;
+ wire T_5061;
+ wire [1:0] T_5062;
+ wire T_5063;
+ wire T_5064;
+ wire [6:0] T_5065;
+ wire [1:0] T_5066;
+ wire [1:0] T_5067;
+ wire T_5068;
+ wire [13:0] T_5069;
+ wire T_5070;
+ wire [30:0] T_5071;
+ wire T_5072;
+ wire T_5073_sd;
+ wire [30:0] T_5073_zero4;
+ wire T_5073_sd_rv32;
+ wire [13:0] T_5073_zero3;
+ wire T_5073_mprv;
+ wire [1:0] T_5073_xs;
+ wire [1:0] T_5073_fs;
+ wire [6:0] T_5073_zero2;
+ wire T_5073_ps;
+ wire T_5073_pie;
+ wire [1:0] T_5073_zero1;
+ wire T_5073_ie;
+ wire T_5109_mtip;
+ wire T_5109_htip;
+ wire T_5109_stip;
+ wire T_5109_utip;
+ wire T_5109_msip;
+ wire T_5109_hsip;
+ wire T_5109_ssip;
+ wire T_5109_usip;
+ wire T_5126_mtip;
+ wire T_5126_htip;
+ wire T_5126_stip;
+ wire T_5126_utip;
+ wire T_5126_msip;
+ wire T_5126_hsip;
+ wire T_5126_ssip;
+ wire T_5126_usip;
+ wire T_5154_mtip;
+ wire T_5154_htip;
+ wire T_5154_stip;
+ wire T_5154_utip;
+ wire T_5154_msip;
+ wire T_5154_hsip;
+ wire T_5154_ssip;
+ wire T_5154_usip;
+ wire T_5171_mtip;
+ wire T_5171_htip;
+ wire T_5171_stip;
+ wire T_5171_utip;
+ wire T_5171_msip;
+ wire T_5171_hsip;
+ wire T_5171_ssip;
+ wire T_5171_usip;
+ wire [31:0] T_5180;
+ wire [32:0] T_5181;
+ wire [2:0] T_5182;
+ wire [16:0] T_5183;
+ wire [49:0] T_5184;
+ wire [7:0] T_5185;
+ wire [9:0] T_5186;
+ wire [2:0] T_5187;
+ wire [3:0] T_5188;
+ wire [13:0] T_5189;
+ wire [63:0] T_5190;
+ wire [1:0] T_5191;
+ wire [1:0] T_5192;
+ wire [3:0] T_5193;
+ wire [1:0] T_5194;
+ wire [1:0] T_5195;
+ wire [3:0] T_5196;
+ wire [7:0] T_5197;
+ wire [1:0] T_5198;
+ wire [1:0] T_5199;
+ wire [3:0] T_5200;
+ wire [1:0] T_5201;
+ wire [1:0] T_5202;
+ wire [3:0] T_5203;
+ wire [7:0] T_5204;
+ wire T_5205;
+ wire [24:0] T_5207;
+ wire [23:0] T_5208;
+ wire [63:0] T_5209;
+ wire T_5211;
+ wire [24:0] T_5213;
+ wire [23:0] T_5214;
+ wire [63:0] T_5215;
+ wire T_5216;
+ wire [25:0] T_5218;
+ wire [24:0] T_5219;
+ wire [63:0] T_5220;
+ wire [11:0] addr;
+ wire T_5223;
+ wire T_5225;
+ wire T_5227;
+ wire T_5229;
+ wire T_5231;
+ wire T_5233;
+ wire T_5235;
+ wire T_5237;
+ wire T_5239;
+ wire T_5241;
+ wire T_5243;
+ wire T_5245;
+ wire T_5247;
+ wire T_5249;
+ wire T_5251;
+ wire T_5253;
+ wire T_5255;
+ wire T_5257;
+ wire T_5259;
+ wire T_5261;
+ wire T_5263;
+ wire T_5265;
+ wire T_5267;
+ wire T_5269;
+ wire T_5271;
+ wire T_5273;
+ wire T_5275;
+ wire T_5277;
+ wire T_5279;
+ wire T_5281;
+ wire T_5283;
+ wire T_5285;
+ wire T_5287;
+ wire T_5289;
+ wire T_5291;
+ wire T_5293;
+ wire T_5295;
+ wire T_5297;
+ wire T_5299;
+ wire T_5301;
+ wire T_5303;
+ wire T_5305;
+ wire T_5307;
+ wire T_5309;
+ wire T_5311;
+ wire T_5313;
+ wire T_5315;
+ wire T_5317;
+ wire T_5319;
+ wire T_5321;
+ wire T_5323;
+ wire T_5325;
+ wire T_5327;
+ wire T_5329;
+ wire T_5331;
+ wire T_5333;
+ wire T_5335;
+ wire T_5336;
+ wire T_5337;
+ wire T_5338;
+ wire T_5339;
+ wire T_5340;
+ wire T_5341;
+ wire T_5342;
+ wire T_5343;
+ wire T_5344;
+ wire T_5345;
+ wire T_5346;
+ wire T_5347;
+ wire T_5348;
+ wire T_5349;
+ wire T_5350;
+ wire T_5351;
+ wire T_5352;
+ wire T_5353;
+ wire T_5354;
+ wire T_5355;
+ wire T_5356;
+ wire T_5357;
+ wire T_5358;
+ wire T_5359;
+ wire T_5360;
+ wire T_5361;
+ wire T_5362;
+ wire T_5363;
+ wire T_5364;
+ wire T_5365;
+ wire T_5366;
+ wire T_5367;
+ wire T_5368;
+ wire T_5369;
+ wire T_5370;
+ wire T_5371;
+ wire T_5372;
+ wire T_5373;
+ wire T_5374;
+ wire T_5375;
+ wire T_5376;
+ wire T_5377;
+ wire T_5378;
+ wire T_5379;
+ wire T_5380;
+ wire T_5381;
+ wire T_5382;
+ wire T_5383;
+ wire T_5384;
+ wire T_5385;
+ wire T_5386;
+ wire T_5387;
+ wire T_5388;
+ wire T_5389;
+ wire T_5390;
+ wire addr_valid;
+ wire T_5392;
+ wire fp_csr;
+ wire [1:0] csr_addr_priv;
+ wire priv_sufficient;
+ wire [1:0] T_5396;
+ wire [1:0] T_5397;
+ wire read_only;
+ wire T_5400;
+ wire T_5401;
+ wire cpu_wen;
+ wire T_5404;
+ wire T_5405;
+ wire T_5406;
+ wire wen;
+ wire T_5408;
+ wire T_5409;
+ wire [63:0] T_5410;
+ wire [63:0] T_5411;
+ wire T_5412;
+ wire [63:0] T_5413;
+ wire [63:0] T_5414;
+ wire [63:0] T_5415;
+ wire [63:0] wdata;
+ wire T_5417;
+ wire T_5419;
+ wire T_5420;
+ wire T_5422;
+ wire T_5423;
+ wire insn_call;
+ wire T_5425;
+ wire T_5427;
+ wire T_5428;
+ wire T_5429;
+ wire insn_break;
+ wire T_5431;
+ wire T_5432;
+ wire T_5434;
+ wire T_5435;
+ wire T_5436;
+ wire T_5438;
+ wire T_5439;
+ wire T_5440;
+ wire insn_ret;
+ wire T_5442;
+ wire T_5443;
+ wire T_5445;
+ wire T_5446;
+ wire T_5447;
+ wire T_5448;
+ wire T_5449;
+ wire insn_sfence_vm;
+ wire T_5451;
+ wire maybe_insn_redirect_trap;
+ wire insn_redirect_trap;
+ wire T_5454;
+ wire T_5455;
+ wire T_5456;
+ wire T_5457;
+ wire T_5459;
+ wire T_5460;
+ wire T_5461;
+ wire insn_wfi;
+ wire T_5463;
+ wire T_5465;
+ wire T_5467;
+ wire T_5468;
+ wire T_5470;
+ wire T_5472;
+ wire T_5473;
+ wire T_5474;
+ wire T_5475;
+ wire T_5476;
+ wire T_5478;
+ wire T_5479;
+ wire T_5480;
+ wire T_5481;
+ wire csr_xcpt;
+ wire T_5485;
+ wire [7:0] T_5486;
+ wire [9:0] T_5488;
+ wire [8:0] T_5489;
+ wire T_5490;
+ wire [39:0] T_5491;
+ wire T_5492;
+ wire T_5494;
+ wire [39:0] T_5495;
+ wire [39:0] T_5496;
+ wire [39:0] T_5497;
+ wire T_5498;
+ wire T_5500;
+ wire [2:0] T_5502;
+ wire [1:0] T_5503;
+ wire T_5505;
+ wire [2:0] T_5507;
+ wire [1:0] T_5508;
+ wire [1:0] T_5509;
+ wire T_5511;
+ wire [1:0] T_5512;
+ wire T_5514;
+ wire T_5515;
+ wire T_5516;
+ wire [39:0] T_5520;
+ wire [39:0] T_5522;
+ wire [39:0] T_5523;
+ wire [4:0] T_5527;
+ wire [3:0] T_5528;
+ wire T_5530;
+ wire T_5532;
+ wire T_5533;
+ wire T_5535;
+ wire T_5536;
+ wire T_5538;
+ wire T_5539;
+ wire [24:0] T_5540;
+ wire [38:0] T_5541;
+ wire [38:0] T_5542;
+ wire GEN_0;
+ wire T_5544;
+ wire [24:0] T_5545;
+ wire T_5547;
+ wire T_5549;
+ wire T_5550;
+ wire [39:0] T_5551;
+ wire [1:0] T_5556;
+ wire [2:0] T_5557;
+ wire [1:0] T_5558;
+ wire [1:0] T_5561;
+ wire [2:0] T_5562;
+ wire [1:0] T_5563;
+ wire [2:0] T_5564;
+ wire [3:0] T_5565;
+ wire [2:0] T_5566;
+ wire T_5568;
+ wire T_5570;
+ wire T_5572;
+ wire T_5574;
+ wire T_5575;
+ wire T_5578;
+ wire T_5579;
+ wire T_5580;
+ wire [4:0] T_5583;
+ wire [2:0] T_5585;
+ wire [7:0] T_5587;
+ wire [63:0] T_5589;
+ wire [63:0] T_5591;
+ wire [63:0] T_5593;
+ wire [63:0] T_5595;
+ wire [63:0] T_5597;
+ wire [63:0] T_5599;
+ wire [63:0] T_5601;
+ wire [63:0] T_5603;
+ wire T_5605;
+ wire [63:0] T_5607;
+ wire T_5609;
+ wire T_5611;
+ wire [8:0] T_5613;
+ wire [30:0] T_5615;
+ wire T_5617;
+ wire [7:0] T_5619;
+ wire [7:0] T_5621;
+ wire [63:0] T_5623;
+ wire [63:0] T_5625;
+ wire [63:0] T_5627;
+ wire [63:0] T_5629;
+ wire [63:0] T_5631;
+ wire T_5633;
+ wire T_5635;
+ wire T_5636;
+ wire [63:0] T_5638;
+ wire [63:0] T_5640;
+ wire [63:0] T_5642;
+ wire [63:0] T_5644;
+ wire [63:0] T_5646;
+ wire [63:0] T_5648;
+ wire [63:0] T_5650;
+ wire [63:0] T_5652;
+ wire [63:0] T_5654;
+ wire [63:0] T_5656;
+ wire [63:0] T_5658;
+ wire [63:0] T_5660;
+ wire [63:0] T_5662;
+ wire [63:0] T_5664;
+ wire [63:0] T_5666;
+ wire [63:0] T_5668;
+ wire [63:0] T_5670;
+ wire [63:0] T_5672;
+ wire [63:0] T_5674;
+ wire [63:0] T_5676;
+ wire [63:0] T_5678;
+ wire [7:0] T_5680;
+ wire [7:0] T_5682;
+ wire [63:0] T_5684;
+ wire [63:0] T_5686;
+ wire [63:0] T_5688;
+ wire [31:0] T_5690;
+ wire T_5692;
+ wire [63:0] T_5694;
+ wire [63:0] T_5696;
+ wire [4:0] T_5698;
+ wire [7:0] T_5699;
+ wire [63:0] T_5700;
+ wire [63:0] T_5701;
+ wire [63:0] T_5702;
+ wire [63:0] T_5703;
+ wire [63:0] T_5704;
+ wire [63:0] T_5705;
+ wire [63:0] T_5706;
+ wire [63:0] T_5707;
+ wire [63:0] T_5708;
+ wire [63:0] T_5709;
+ wire [63:0] T_5710;
+ wire [63:0] T_5711;
+ wire [63:0] T_5712;
+ wire [63:0] T_5713;
+ wire [63:0] T_5714;
+ wire [63:0] T_5715;
+ wire [63:0] T_5716;
+ wire [63:0] T_5717;
+ wire [63:0] T_5718;
+ wire [63:0] T_5719;
+ wire [63:0] T_5720;
+ wire [63:0] T_5721;
+ wire [63:0] T_5722;
+ wire [63:0] T_5723;
+ wire [63:0] T_5724;
+ wire [63:0] T_5725;
+ wire [63:0] T_5726;
+ wire [63:0] T_5727;
+ wire [63:0] T_5728;
+ wire [63:0] T_5729;
+ wire [63:0] T_5730;
+ wire [63:0] T_5731;
+ wire [63:0] T_5732;
+ wire [63:0] T_5733;
+ wire [63:0] T_5734;
+ wire [63:0] T_5735;
+ wire [63:0] T_5736;
+ wire [63:0] T_5737;
+ wire [63:0] T_5738;
+ wire [63:0] T_5739;
+ wire [63:0] T_5740;
+ wire [63:0] T_5741;
+ wire [63:0] T_5742;
+ wire [63:0] T_5743;
+ wire [63:0] T_5744;
+ wire [63:0] T_5745;
+ wire [63:0] T_5746;
+ wire [63:0] T_5747;
+ wire [63:0] T_5748;
+ wire [63:0] T_5749;
+ wire [63:0] T_5750;
+ wire [63:0] T_5751;
+ wire [63:0] T_5752;
+ wire [63:0] T_5753;
+ wire [63:0] T_5754;
+ wire [4:0] T_5755;
+ wire T_5790_sd;
+ wire [30:0] T_5790_zero2;
+ wire T_5790_sd_rv32;
+ wire [8:0] T_5790_zero1;
+ wire [4:0] T_5790_vm;
+ wire T_5790_mprv;
+ wire [1:0] T_5790_xs;
+ wire [1:0] T_5790_fs;
+ wire [1:0] T_5790_prv3;
+ wire T_5790_ie3;
+ wire [1:0] T_5790_prv2;
+ wire T_5790_ie2;
+ wire [1:0] T_5790_prv1;
+ wire T_5790_ie1;
+ wire [1:0] T_5790_prv;
+ wire T_5790_ie;
+ wire T_5807;
+ wire [1:0] T_5808;
+ wire T_5809;
+ wire [1:0] T_5810;
+ wire T_5811;
+ wire [1:0] T_5812;
+ wire T_5813;
+ wire [1:0] T_5814;
+ wire [1:0] T_5815;
+ wire [1:0] T_5816;
+ wire T_5817;
+ wire [4:0] T_5818;
+ wire [8:0] T_5819;
+ wire T_5820;
+ wire [30:0] T_5821;
+ wire T_5822;
+ wire [1:0] T_5827_0;
+ wire [1:0] T_5827_1;
+ wire [1:0] T_5827_2;
+ wire T_5832;
+ wire T_5833;
+ wire T_5834;
+ wire T_5836;
+ wire T_5837;
+ wire T_5838;
+ wire T_5839;
+ wire T_5840;
+ wire T_5841;
+ wire T_5843;
+ wire T_5844;
+ wire T_5845;
+ wire T_5846;
+ wire T_5847;
+ wire T_5848;
+ wire T_5850;
+ wire T_5851;
+ wire T_5852;
+ wire T_5854;
+ wire T_5857;
+ wire T_5877_mtip;
+ wire T_5877_htip;
+ wire T_5877_stip;
+ wire T_5877_utip;
+ wire T_5877_msip;
+ wire T_5877_hsip;
+ wire T_5877_ssip;
+ wire T_5877_usip;
+ wire T_5886;
+ wire T_5887;
+ wire T_5888;
+ wire T_5889;
+ wire T_5890;
+ wire T_5891;
+ wire T_5892;
+ wire T_5893;
+ wire T_5894;
+ wire T_5913_mtip;
+ wire T_5913_htip;
+ wire T_5913_stip;
+ wire T_5913_utip;
+ wire T_5913_msip;
+ wire T_5913_hsip;
+ wire T_5913_ssip;
+ wire T_5913_usip;
+ wire T_5922;
+ wire T_5923;
+ wire T_5924;
+ wire T_5925;
+ wire T_5926;
+ wire T_5927;
+ wire T_5928;
+ wire T_5929;
+ wire [58:0] T_5930;
+ wire [63:0] T_5931;
+ wire [63:0] T_5933;
+ wire [63:0] T_5934;
+ wire [63:0] T_5936;
+ wire [39:0] T_5937;
+ wire [5:0] T_5938;
+ wire [57:0] T_5939;
+ wire T_5942;
+ wire T_5944;
+ wire T_5945;
+ wire T_5947;
+ wire T_5948;
+ wire T_5949;
+ wire T_5976_sd;
+ wire [30:0] T_5976_zero4;
+ wire T_5976_sd_rv32;
+ wire [13:0] T_5976_zero3;
+ wire T_5976_mprv;
+ wire [1:0] T_5976_xs;
+ wire [1:0] T_5976_fs;
+ wire [6:0] T_5976_zero2;
+ wire T_5976_ps;
+ wire T_5976_pie;
+ wire [1:0] T_5976_zero1;
+ wire T_5976_ie;
+ wire T_5989;
+ wire [1:0] T_5990;
+ wire T_5991;
+ wire T_5992;
+ wire [6:0] T_5993;
+ wire [1:0] T_5994;
+ wire [1:0] T_5995;
+ wire T_5996;
+ wire [13:0] T_5997;
+ wire T_5998;
+ wire [30:0] T_5999;
+ wire T_6000;
+ wire T_6003;
+ wire T_6022_mtip;
+ wire T_6022_htip;
+ wire T_6022_stip;
+ wire T_6022_utip;
+ wire T_6022_msip;
+ wire T_6022_hsip;
+ wire T_6022_ssip;
+ wire T_6022_usip;
+ wire T_6031;
+ wire T_6032;
+ wire T_6033;
+ wire T_6034;
+ wire T_6035;
+ wire T_6036;
+ wire T_6037;
+ wire T_6038;
+ wire T_6057_mtip;
+ wire T_6057_htip;
+ wire T_6057_stip;
+ wire T_6057_utip;
+ wire T_6057_msip;
+ wire T_6057_hsip;
+ wire T_6057_ssip;
+ wire T_6057_usip;
+ wire T_6066;
+ wire T_6067;
+ wire T_6068;
+ wire T_6069;
+ wire T_6070;
+ wire T_6071;
+ wire T_6072;
+ wire T_6073;
+ wire [19:0] T_6074;
+ wire [31:0] T_6076;
+ wire [63:0] T_6077;
+ wire [63:0] T_6079;
+ wire [63:0] T_6080;
+ wire [63:0] T_6081;
+ wire [63:0] T_6083;
+ wire [63:0] T_6084;
+ wire GEN_1;
+ reg GEN_2;
+ reg [6:0] GEN_3;
+ reg [4:0] GEN_4;
+ reg [4:0] GEN_5;
+ reg GEN_6;
+ reg GEN_7;
+ reg GEN_8;
+ reg [4:0] GEN_9;
+ reg [6:0] GEN_10;
+ reg [63:0] GEN_11;
+ reg [63:0] GEN_12;
+ reg GEN_13;
+ reg GEN_14;
+ reg GEN_15;
+ reg [39:0] GEN_16;
+ reg [8:0] GEN_17;
+ reg [4:0] GEN_18;
+ reg [2:0] GEN_19;
+ reg [63:0] GEN_20;
+ reg GEN_21;
+ reg GEN_22;
+ reg GEN_23;
+ reg [63:0] GEN_24;
+ reg [63:0] GEN_25;
+ reg GEN_26;
+ reg [8:0] GEN_27;
+ reg GEN_28;
+ reg GEN_29;
+ reg GEN_30;
+ reg GEN_31;
+ reg GEN_32;
+ reg GEN_33;
+ reg GEN_34;
+ reg GEN_35;
+ reg [1:0] GEN_36;
+ reg [1:0] GEN_37;
+ reg [3:0] GEN_38;
+ reg GEN_39;
+ reg [3:0] GEN_40;
+ reg [127:0] GEN_41;
+ reg GEN_42;
+ reg GEN_43;
+ reg GEN_44;
+ reg [19:0] GEN_45;
+ reg [2:0] GEN_46;
+ reg GEN_47;
+ reg GEN_48;
+ reg [3:0] GEN_49;
+ reg GEN_50;
+ reg GEN_51;
+ reg [30:0] GEN_52;
+ reg GEN_53;
+ reg [8:0] GEN_54;
+ reg [4:0] GEN_55;
+ reg GEN_56;
+ reg [1:0] GEN_57;
+ reg [1:0] GEN_58;
+ reg [1:0] GEN_59;
+ reg GEN_60;
+ reg [1:0] GEN_61;
+ reg GEN_62;
+ reg [1:0] GEN_63;
+ reg GEN_64;
+ reg [1:0] GEN_65;
+ reg GEN_66;
+ reg GEN_67;
+ reg GEN_68;
+ reg GEN_69;
+ reg GEN_70;
+ reg [19:0] GEN_71;
+ reg [2:0] GEN_72;
+ reg GEN_73;
+ reg GEN_74;
+ reg [3:0] GEN_75;
+ reg GEN_76;
+ reg GEN_77;
+ reg [30:0] GEN_78;
+ reg GEN_79;
+ reg [8:0] GEN_80;
+ reg [4:0] GEN_81;
+ reg GEN_82;
+ reg [1:0] GEN_83;
+ reg [1:0] GEN_84;
+ reg [1:0] GEN_85;
+ reg GEN_86;
+ reg [1:0] GEN_87;
+ reg GEN_88;
+ reg [1:0] GEN_89;
+ reg GEN_90;
+ reg [1:0] GEN_91;
+ reg GEN_92;
+ reg GEN_93;
+ reg GEN_94;
+ reg GEN_95;
+ reg GEN_96;
+ reg [19:0] GEN_97;
+ reg [2:0] GEN_98;
+ reg GEN_99;
+ reg GEN_100;
+ reg [3:0] GEN_101;
+ reg GEN_102;
+ reg GEN_103;
+ reg [30:0] GEN_104;
+ reg GEN_105;
+ reg [8:0] GEN_106;
+ reg [4:0] GEN_107;
+ reg GEN_108;
+ reg [1:0] GEN_109;
+ reg [1:0] GEN_110;
+ reg [1:0] GEN_111;
+ reg GEN_112;
+ reg [1:0] GEN_113;
+ reg GEN_114;
+ reg [1:0] GEN_115;
+ reg GEN_116;
+ reg [1:0] GEN_117;
+ reg GEN_118;
+ reg GEN_119;
+ reg GEN_120;
+ reg GEN_121;
+ reg [64:0] GEN_122;
+ reg [4:0] GEN_123;
+ reg GEN_124;
+ reg GEN_125;
+ reg GEN_126;
+ reg [1:0] GEN_127;
+ reg [1:0] GEN_128;
+ assign io_host_csr_req_ready = T_4968;
+ assign io_host_csr_resp_valid = host_csr_rep_valid;
+ assign io_host_csr_resp_bits = host_csr_bits_data;
+ assign io_host_debug_stats_csr = reg_stats;
+ assign io_rw_rdata = T_5754;
+ assign io_csr_stall = reg_wfi;
+ assign io_csr_xcpt = csr_xcpt;
+ assign io_eret = T_5498;
+ assign io_status_sd = T_5515;
+ assign io_status_zero2 = reg_mstatus_zero2;
+ assign io_status_sd_rv32 = reg_mstatus_sd_rv32;
+ assign io_status_zero1 = reg_mstatus_zero1;
+ assign io_status_vm = reg_mstatus_vm;
+ assign io_status_mprv = reg_mstatus_mprv;
+ assign io_status_xs = T_5508;
+ assign io_status_fs = T_5503;
+ assign io_status_prv3 = reg_mstatus_prv3;
+ assign io_status_ie3 = reg_mstatus_ie3;
+ assign io_status_prv2 = reg_mstatus_prv2;
+ assign io_status_ie2 = reg_mstatus_ie2;
+ assign io_status_prv1 = reg_mstatus_prv1;
+ assign io_status_ie1 = reg_mstatus_ie1;
+ assign io_status_prv = reg_mstatus_prv;
+ assign io_status_ie = reg_mstatus_ie;
+ assign io_ptbr = reg_sptbr;
+ assign io_evec = T_5497;
+ assign io_fatc = insn_sfence_vm;
+ assign io_time = T_4615;
+ assign io_fcsr_rm = reg_frm;
+ assign io_rocc_cmd_valid = GEN_2;
+ assign io_rocc_cmd_bits_inst_funct = GEN_3;
+ assign io_rocc_cmd_bits_inst_rs2 = GEN_4;
+ assign io_rocc_cmd_bits_inst_rs1 = GEN_5;
+ assign io_rocc_cmd_bits_inst_xd = GEN_6;
+ assign io_rocc_cmd_bits_inst_xs1 = GEN_7;
+ assign io_rocc_cmd_bits_inst_xs2 = GEN_8;
+ assign io_rocc_cmd_bits_inst_rd = GEN_9;
+ assign io_rocc_cmd_bits_inst_opcode = GEN_10;
+ assign io_rocc_cmd_bits_rs1 = GEN_11;
+ assign io_rocc_cmd_bits_rs2 = GEN_12;
+ assign io_rocc_resp_ready = GEN_13;
+ assign io_rocc_mem_req_ready = GEN_14;
+ assign io_rocc_mem_resp_valid = GEN_15;
+ assign io_rocc_mem_resp_bits_addr = GEN_16;
+ assign io_rocc_mem_resp_bits_tag = GEN_17;
+ assign io_rocc_mem_resp_bits_cmd = GEN_18;
+ assign io_rocc_mem_resp_bits_typ = GEN_19;
+ assign io_rocc_mem_resp_bits_data = GEN_20;
+ assign io_rocc_mem_resp_bits_nack = GEN_21;
+ assign io_rocc_mem_resp_bits_replay = GEN_22;
+ assign io_rocc_mem_resp_bits_has_data = GEN_23;
+ assign io_rocc_mem_resp_bits_data_word_bypass = GEN_24;
+ assign io_rocc_mem_resp_bits_store_data = GEN_25;
+ assign io_rocc_mem_replay_next_valid = GEN_26;
+ assign io_rocc_mem_replay_next_bits = GEN_27;
+ assign io_rocc_mem_xcpt_ma_ld = GEN_28;
+ assign io_rocc_mem_xcpt_ma_st = GEN_29;
+ assign io_rocc_mem_xcpt_pf_ld = GEN_30;
+ assign io_rocc_mem_xcpt_pf_st = GEN_31;
+ assign io_rocc_mem_ordered = GEN_32;
+ assign io_rocc_s = GEN_33;
+ assign io_rocc_autl_acquire_ready = GEN_34;
+ assign io_rocc_autl_grant_valid = GEN_35;
+ assign io_rocc_autl_grant_bits_addr_beat = GEN_36;
+ assign io_rocc_autl_grant_bits_client_xact_id = GEN_37;
+ assign io_rocc_autl_grant_bits_manager_xact_id = GEN_38;
+ assign io_rocc_autl_grant_bits_is_builtin_type = GEN_39;
+ assign io_rocc_autl_grant_bits_g_type = GEN_40;
+ assign io_rocc_autl_grant_bits_data = GEN_41;
+ assign io_rocc_iptw_req_ready = GEN_42;
+ assign io_rocc_iptw_resp_valid = GEN_43;
+ assign io_rocc_iptw_resp_bits_error = GEN_44;
+ assign io_rocc_iptw_resp_bits_pte_ppn = GEN_45;
+ assign io_rocc_iptw_resp_bits_pte_reserved_for_software = GEN_46;
+ assign io_rocc_iptw_resp_bits_pte_d = GEN_47;
+ assign io_rocc_iptw_resp_bits_pte_r = GEN_48;
+ assign io_rocc_iptw_resp_bits_pte_typ = GEN_49;
+ assign io_rocc_iptw_resp_bits_pte_v = GEN_50;
+ assign io_rocc_iptw_status_sd = GEN_51;
+ assign io_rocc_iptw_status_zero2 = GEN_52;
+ assign io_rocc_iptw_status_sd_rv32 = GEN_53;
+ assign io_rocc_iptw_status_zero1 = GEN_54;
+ assign io_rocc_iptw_status_vm = GEN_55;
+ assign io_rocc_iptw_status_mprv = GEN_56;
+ assign io_rocc_iptw_status_xs = GEN_57;
+ assign io_rocc_iptw_status_fs = GEN_58;
+ assign io_rocc_iptw_status_prv3 = GEN_59;
+ assign io_rocc_iptw_status_ie3 = GEN_60;
+ assign io_rocc_iptw_status_prv2 = GEN_61;
+ assign io_rocc_iptw_status_ie2 = GEN_62;
+ assign io_rocc_iptw_status_prv1 = GEN_63;
+ assign io_rocc_iptw_status_ie1 = GEN_64;
+ assign io_rocc_iptw_status_prv = GEN_65;
+ assign io_rocc_iptw_status_ie = GEN_66;
+ assign io_rocc_iptw_invalidate = GEN_67;
+ assign io_rocc_dptw_req_ready = GEN_68;
+ assign io_rocc_dptw_resp_valid = GEN_69;
+ assign io_rocc_dptw_resp_bits_error = GEN_70;
+ assign io_rocc_dptw_resp_bits_pte_ppn = GEN_71;
+ assign io_rocc_dptw_resp_bits_pte_reserved_for_software = GEN_72;
+ assign io_rocc_dptw_resp_bits_pte_d = GEN_73;
+ assign io_rocc_dptw_resp_bits_pte_r = GEN_74;
+ assign io_rocc_dptw_resp_bits_pte_typ = GEN_75;
+ assign io_rocc_dptw_resp_bits_pte_v = GEN_76;
+ assign io_rocc_dptw_status_sd = GEN_77;
+ assign io_rocc_dptw_status_zero2 = GEN_78;
+ assign io_rocc_dptw_status_sd_rv32 = GEN_79;
+ assign io_rocc_dptw_status_zero1 = GEN_80;
+ assign io_rocc_dptw_status_vm = GEN_81;
+ assign io_rocc_dptw_status_mprv = GEN_82;
+ assign io_rocc_dptw_status_xs = GEN_83;
+ assign io_rocc_dptw_status_fs = GEN_84;
+ assign io_rocc_dptw_status_prv3 = GEN_85;
+ assign io_rocc_dptw_status_ie3 = GEN_86;
+ assign io_rocc_dptw_status_prv2 = GEN_87;
+ assign io_rocc_dptw_status_ie2 = GEN_88;
+ assign io_rocc_dptw_status_prv1 = GEN_89;
+ assign io_rocc_dptw_status_ie1 = GEN_90;
+ assign io_rocc_dptw_status_prv = GEN_91;
+ assign io_rocc_dptw_status_ie = GEN_92;
+ assign io_rocc_dptw_invalidate = GEN_93;
+ assign io_rocc_pptw_req_ready = GEN_94;
+ assign io_rocc_pptw_resp_valid = GEN_95;
+ assign io_rocc_pptw_resp_bits_error = GEN_96;
+ assign io_rocc_pptw_resp_bits_pte_ppn = GEN_97;
+ assign io_rocc_pptw_resp_bits_pte_reserved_for_software = GEN_98;
+ assign io_rocc_pptw_resp_bits_pte_d = GEN_99;
+ assign io_rocc_pptw_resp_bits_pte_r = GEN_100;
+ assign io_rocc_pptw_resp_bits_pte_typ = GEN_101;
+ assign io_rocc_pptw_resp_bits_pte_v = GEN_102;
+ assign io_rocc_pptw_status_sd = GEN_103;
+ assign io_rocc_pptw_status_zero2 = GEN_104;
+ assign io_rocc_pptw_status_sd_rv32 = GEN_105;
+ assign io_rocc_pptw_status_zero1 = GEN_106;
+ assign io_rocc_pptw_status_vm = GEN_107;
+ assign io_rocc_pptw_status_mprv = GEN_108;
+ assign io_rocc_pptw_status_xs = GEN_109;
+ assign io_rocc_pptw_status_fs = GEN_110;
+ assign io_rocc_pptw_status_prv3 = GEN_111;
+ assign io_rocc_pptw_status_ie3 = GEN_112;
+ assign io_rocc_pptw_status_prv2 = GEN_113;
+ assign io_rocc_pptw_status_ie2 = GEN_114;
+ assign io_rocc_pptw_status_prv1 = GEN_115;
+ assign io_rocc_pptw_status_ie1 = GEN_116;
+ assign io_rocc_pptw_status_prv = GEN_117;
+ assign io_rocc_pptw_status_ie = GEN_118;
+ assign io_rocc_pptw_invalidate = GEN_119;
+ assign io_rocc_fpu_req_ready = GEN_120;
+ assign io_rocc_fpu_resp_valid = GEN_121;
+ assign io_rocc_fpu_resp_bits_data = GEN_122;
+ assign io_rocc_fpu_resp_bits_exc = GEN_123;
+ assign io_rocc_exception = GEN_124;
+ assign io_rocc_dma_req_ready = GEN_125;
+ assign io_rocc_dma_resp_valid = GEN_126;
+ assign io_rocc_dma_resp_bits_client_xact_id = GEN_127;
+ assign io_rocc_dma_resp_bits_status = GEN_128;
+ assign io_interrupt = T_4879;
+ assign io_interrupt_cause = T_4943 ? 64'h8000000000000003 : T_4933 ? 64'h8000000000000002 : T_4921 ? 64'h8000000000000001 : T_4910 ? 64'h8000000000000001 : T_4899 ? 64'h8000000000000000 : T_4888 ? 64'h8000000000000000 : 1'h0;
+ assign T_4480_mtip = 1'h0;
+ assign T_4480_htip = 1'h0;
+ assign T_4480_stip = 1'h0;
+ assign T_4480_utip = 1'h0;
+ assign T_4480_msip = 1'h0;
+ assign T_4480_hsip = 1'h0;
+ assign T_4480_ssip = 1'h0;
+ assign T_4480_usip = 1'h0;
+ assign T_4525_mtip = 1'h0;
+ assign T_4525_htip = 1'h0;
+ assign T_4525_stip = 1'h0;
+ assign T_4525_utip = 1'h0;
+ assign T_4525_msip = 1'h0;
+ assign T_4525_hsip = 1'h0;
+ assign T_4525_ssip = 1'h0;
+ assign T_4525_usip = 1'h0;
+ assign T_4586 = io_retire != 1'h0;
+ assign T_4588 = T_4584 + 7'h1;
+ assign T_4589 = T_4588[6:0];
+ assign T_4590 = T_4589[5:0];
+ assign T_4593 = T_4589[6];
+ assign T_4594 = T_4586 & T_4593;
+ assign T_4596 = T_4592 + 1'h1;
+ assign T_4597 = T_4596[57:0];
+ assign T_4598 = {T_4592,T_4584};
+ assign T_4603 = 1'h1 != 1'h0;
+ assign T_4605 = T_4601 + 7'h1;
+ assign T_4606 = T_4605[6:0];
+ assign T_4607 = T_4606[5:0];
+ assign T_4610 = T_4606[6];
+ assign T_4611 = T_4603 & T_4610;
+ assign T_4613 = T_4609 + 1'h1;
+ assign T_4614 = T_4613[57:0];
+ assign T_4615 = {T_4609,T_4601};
+ assign T_4619 = io_uarch_counters_0 != 1'h0;
+ assign T_4621 = T_4617 + 7'h1;
+ assign T_4622 = T_4621[6:0];
+ assign T_4623 = T_4622[5:0];
+ assign T_4626 = T_4622[6];
+ assign T_4627 = T_4619 & T_4626;
+ assign T_4629 = T_4625 + 1'h1;
+ assign T_4630 = T_4629[57:0];
+ assign T_4631 = {T_4625,T_4617};
+ assign T_4635 = io_uarch_counters_1 != 1'h0;
+ assign T_4637 = T_4633 + 7'h1;
+ assign T_4638 = T_4637[6:0];
+ assign T_4639 = T_4638[5:0];
+ assign T_4642 = T_4638[6];
+ assign T_4643 = T_4635 & T_4642;
+ assign T_4645 = T_4641 + 1'h1;
+ assign T_4646 = T_4645[57:0];
+ assign T_4647 = {T_4641,T_4633};
+ assign T_4651 = io_uarch_counters_2 != 1'h0;
+ assign T_4653 = T_4649 + 7'h1;
+ assign T_4654 = T_4653[6:0];
+ assign T_4655 = T_4654[5:0];
+ assign T_4658 = T_4654[6];
+ assign T_4659 = T_4651 & T_4658;
+ assign T_4661 = T_4657 + 1'h1;
+ assign T_4662 = T_4661[57:0];
+ assign T_4663 = {T_4657,T_4649};
+ assign T_4667 = io_uarch_counters_3 != 1'h0;
+ assign T_4669 = T_4665 + 7'h1;
+ assign T_4670 = T_4669[6:0];
+ assign T_4671 = T_4670[5:0];
+ assign T_4674 = T_4670[6];
+ assign T_4675 = T_4667 & T_4674;
+ assign T_4677 = T_4673 + 1'h1;
+ assign T_4678 = T_4677[57:0];
+ assign T_4679 = {T_4673,T_4665};
+ assign T_4683 = io_uarch_counters_4 != 1'h0;
+ assign T_4685 = T_4681 + 7'h1;
+ assign T_4686 = T_4685[6:0];
+ assign T_4687 = T_4686[5:0];
+ assign T_4690 = T_4686[6];
+ assign T_4691 = T_4683 & T_4690;
+ assign T_4693 = T_4689 + 1'h1;
+ assign T_4694 = T_4693[57:0];
+ assign T_4695 = {T_4689,T_4681};
+ assign T_4699 = io_uarch_counters_5 != 1'h0;
+ assign T_4701 = T_4697 + 7'h1;
+ assign T_4702 = T_4701[6:0];
+ assign T_4703 = T_4702[5:0];
+ assign T_4706 = T_4702[6];
+ assign T_4707 = T_4699 & T_4706;
+ assign T_4709 = T_4705 + 1'h1;
+ assign T_4710 = T_4709[57:0];
+ assign T_4711 = {T_4705,T_4697};
+ assign T_4715 = io_uarch_counters_6 != 1'h0;
+ assign T_4717 = T_4713 + 7'h1;
+ assign T_4718 = T_4717[6:0];
+ assign T_4719 = T_4718[5:0];
+ assign T_4722 = T_4718[6];
+ assign T_4723 = T_4715 & T_4722;
+ assign T_4725 = T_4721 + 1'h1;
+ assign T_4726 = T_4725[57:0];
+ assign T_4727 = {T_4721,T_4713};
+ assign T_4731 = io_uarch_counters_7 != 1'h0;
+ assign T_4733 = T_4729 + 7'h1;
+ assign T_4734 = T_4733[6:0];
+ assign T_4735 = T_4734[5:0];
+ assign T_4738 = T_4734[6];
+ assign T_4739 = T_4731 & T_4738;
+ assign T_4741 = T_4737 + 1'h1;
+ assign T_4742 = T_4741[57:0];
+ assign T_4743 = {T_4737,T_4729};
+ assign T_4747 = io_uarch_counters_8 != 1'h0;
+ assign T_4749 = T_4745 + 7'h1;
+ assign T_4750 = T_4749[6:0];
+ assign T_4751 = T_4750[5:0];
+ assign T_4754 = T_4750[6];
+ assign T_4755 = T_4747 & T_4754;
+ assign T_4757 = T_4753 + 1'h1;
+ assign T_4758 = T_4757[57:0];
+ assign T_4759 = {T_4753,T_4745};
+ assign T_4763 = io_uarch_counters_9 != 1'h0;
+ assign T_4765 = T_4761 + 7'h1;
+ assign T_4766 = T_4765[6:0];
+ assign T_4767 = T_4766[5:0];
+ assign T_4770 = T_4766[6];
+ assign T_4771 = T_4763 & T_4770;
+ assign T_4773 = T_4769 + 1'h1;
+ assign T_4774 = T_4773[57:0];
+ assign T_4775 = {T_4769,T_4761};
+ assign T_4779 = io_uarch_counters_10 != 1'h0;
+ assign T_4781 = T_4777 + 7'h1;
+ assign T_4782 = T_4781[6:0];
+ assign T_4783 = T_4782[5:0];
+ assign T_4786 = T_4782[6];
+ assign T_4787 = T_4779 & T_4786;
+ assign T_4789 = T_4785 + 1'h1;
+ assign T_4790 = T_4789[57:0];
+ assign T_4791 = {T_4785,T_4777};
+ assign T_4795 = io_uarch_counters_11 != 1'h0;
+ assign T_4797 = T_4793 + 7'h1;
+ assign T_4798 = T_4797[6:0];
+ assign T_4799 = T_4798[5:0];
+ assign T_4802 = T_4798[6];
+ assign T_4803 = T_4795 & T_4802;
+ assign T_4805 = T_4801 + 1'h1;
+ assign T_4806 = T_4805[57:0];
+ assign T_4807 = {T_4801,T_4793};
+ assign T_4811 = io_uarch_counters_12 != 1'h0;
+ assign T_4813 = T_4809 + 7'h1;
+ assign T_4814 = T_4813[6:0];
+ assign T_4815 = T_4814[5:0];
+ assign T_4818 = T_4814[6];
+ assign T_4819 = T_4811 & T_4818;
+ assign T_4821 = T_4817 + 1'h1;
+ assign T_4822 = T_4821[57:0];
+ assign T_4823 = {T_4817,T_4809};
+ assign T_4827 = io_uarch_counters_13 != 1'h0;
+ assign T_4829 = T_4825 + 7'h1;
+ assign T_4830 = T_4829[6:0];
+ assign T_4831 = T_4830[5:0];
+ assign T_4834 = T_4830[6];
+ assign T_4835 = T_4827 & T_4834;
+ assign T_4837 = T_4833 + 1'h1;
+ assign T_4838 = T_4837[57:0];
+ assign T_4839 = {T_4833,T_4825};
+ assign T_4843 = io_uarch_counters_14 != 1'h0;
+ assign T_4845 = T_4841 + 7'h1;
+ assign T_4846 = T_4845[6:0];
+ assign T_4847 = T_4846[5:0];
+ assign T_4850 = T_4846[6];
+ assign T_4851 = T_4843 & T_4850;
+ assign T_4853 = T_4849 + 1'h1;
+ assign T_4854 = T_4853[57:0];
+ assign T_4855 = {T_4849,T_4841};
+ assign T_4859 = io_uarch_counters_15 != 1'h0;
+ assign T_4861 = T_4857 + 7'h1;
+ assign T_4862 = T_4861[6:0];
+ assign T_4863 = T_4862[5:0];
+ assign T_4866 = T_4862[6];
+ assign T_4867 = T_4859 & T_4866;
+ assign T_4869 = T_4865 + 1'h1;
+ assign T_4870 = T_4869[57:0];
+ assign T_4871 = {T_4865,T_4857};
+ assign irq_rocc = 1'h0 & io_rocc_interrupt;
+ assign T_4879 = io_interrupt_cause[63];
+ assign some_interrupt_pending = T_4946 ? 1'h1 : T_4936 ? 1'h1 : T_4924 ? 1'h1 : T_4913 ? 1'h1 : T_4902 ? 1'h1 : T_4891 ? 1'h1 : 1'h0;
+ assign T_4883 = reg_mie_ssip & reg_mip_ssip;
+ assign T_4884 = reg_mstatus_prv < 1'h1;
+ assign T_4885 = reg_mstatus_prv == 1'h1;
+ assign T_4886 = T_4885 & reg_mstatus_ie;
+ assign T_4887 = T_4884 | T_4886;
+ assign T_4888 = T_4883 & T_4887;
+ assign T_4890 = reg_mstatus_prv <= 1'h1;
+ assign T_4891 = T_4883 & T_4890;
+ assign T_4894 = reg_mie_msip & reg_mip_msip;
+ assign T_4895 = reg_mstatus_prv < 2'h3;
+ assign T_4896 = reg_mstatus_prv == 2'h3;
+ assign T_4897 = T_4896 & reg_mstatus_ie;
+ assign T_4898 = T_4895 | T_4897;
+ assign T_4899 = T_4894 & T_4898;
+ assign T_4901 = reg_mstatus_prv <= 2'h3;
+ assign T_4902 = T_4894 & T_4901;
+ assign T_4905 = reg_mie_stip & reg_mip_stip;
+ assign T_4906 = reg_mstatus_prv < 1'h1;
+ assign T_4907 = reg_mstatus_prv == 1'h1;
+ assign T_4908 = T_4907 & reg_mstatus_ie;
+ assign T_4909 = T_4906 | T_4908;
+ assign T_4910 = T_4905 & T_4909;
+ assign T_4912 = reg_mstatus_prv <= 1'h1;
+ assign T_4913 = T_4905 & T_4912;
+ assign T_4916 = reg_mie_mtip & reg_mip_mtip;
+ assign T_4917 = reg_mstatus_prv < 2'h3;
+ assign T_4918 = reg_mstatus_prv == 2'h3;
+ assign T_4919 = T_4918 & reg_mstatus_ie;
+ assign T_4920 = T_4917 | T_4919;
+ assign T_4921 = T_4916 & T_4920;
+ assign T_4923 = reg_mstatus_prv <= 2'h3;
+ assign T_4924 = T_4916 & T_4923;
+ assign T_4928 = reg_fromhost != 1'h0;
+ assign T_4929 = reg_mstatus_prv < 2'h3;
+ assign T_4930 = reg_mstatus_prv == 2'h3;
+ assign T_4931 = T_4930 & reg_mstatus_ie;
+ assign T_4932 = T_4929 | T_4931;
+ assign T_4933 = T_4928 & T_4932;
+ assign T_4935 = reg_mstatus_prv <= 2'h3;
+ assign T_4936 = T_4928 & T_4935;
+ assign T_4939 = reg_mstatus_prv < 2'h3;
+ assign T_4940 = reg_mstatus_prv == 2'h3;
+ assign T_4941 = T_4940 & reg_mstatus_ie;
+ assign T_4942 = T_4939 | T_4941;
+ assign T_4943 = irq_rocc & T_4942;
+ assign T_4945 = reg_mstatus_prv <= 2'h3;
+ assign T_4946 = irq_rocc & T_4945;
+ assign system_insn = io_rw_cmd == 3'h4;
+ assign T_4949 = io_rw_cmd != 3'h0;
+ assign T_4951 = system_insn == 1'h0;
+ assign cpu_ren = T_4949 & T_4951;
+ assign T_4956 = cpu_ren == 1'h0;
+ assign host_csr_req_fire = host_csr_req_valid & T_4956;
+ assign T_4965 = host_csr_req_valid == 1'h0;
+ assign T_4967 = host_csr_rep_valid == 1'h0;
+ assign T_4968 = T_4965 & T_4967;
+ assign T_4969 = io_host_csr_req_ready & io_host_csr_req_valid;
+ assign T_4973 = io_host_csr_resp_ready & io_host_csr_resp_valid;
+ assign T_4975 = {io_status_sd,io_status_zero2};
+ assign T_4976 = {io_status_sd_rv32,io_status_zero1};
+ assign T_4977 = {T_4975,T_4976};
+ assign T_4978 = {io_status_vm,io_status_mprv};
+ assign T_4979 = {io_status_xs,io_status_fs};
+ assign T_4980 = {T_4978,T_4979};
+ assign T_4981 = {T_4977,T_4980};
+ assign T_4982 = {io_status_prv3,io_status_ie3};
+ assign T_4983 = {io_status_prv2,io_status_ie2};
+ assign T_4984 = {T_4982,T_4983};
+ assign T_4985 = {io_status_prv1,io_status_ie1};
+ assign T_4986 = {io_status_prv,io_status_ie};
+ assign T_4987 = {T_4985,T_4986};
+ assign T_4988 = {T_4984,T_4987};
+ assign read_mstatus = {T_4981,T_4988};
+ assign T_4990 = {reg_frm,reg_fflags};
+ assign T_4998 = {reg_mip_mtip,reg_mip_htip};
+ assign T_4999 = {reg_mip_stip,reg_mip_utip};
+ assign T_5000 = {T_4998,T_4999};
+ assign T_5001 = {reg_mip_msip,reg_mip_hsip};
+ assign T_5002 = {reg_mip_ssip,reg_mip_usip};
+ assign T_5003 = {T_5001,T_5002};
+ assign T_5004 = {T_5000,T_5003};
+ assign T_5005 = {reg_mie_mtip,reg_mie_htip};
+ assign T_5006 = {reg_mie_stip,reg_mie_utip};
+ assign T_5007 = {T_5005,T_5006};
+ assign T_5008 = {reg_mie_msip,reg_mie_hsip};
+ assign T_5009 = {reg_mie_ssip,reg_mie_usip};
+ assign T_5010 = {T_5008,T_5009};
+ assign T_5011 = {T_5007,T_5010};
+ assign T_5012 = reg_mepc[39];
+ assign T_5014 = 24'h0 - T_5012;
+ assign T_5015 = T_5014[23:0];
+ assign T_5016 = {T_5015,reg_mepc};
+ assign T_5017 = reg_mbadaddr[39];
+ assign T_5019 = 24'h0 - T_5017;
+ assign T_5020 = T_5019[23:0];
+ assign T_5021 = {T_5020,reg_mbadaddr};
+ assign T_5048_sd = T_5072;
+ assign T_5048_zero4 = T_5071;
+ assign T_5048_sd_rv32 = T_5070;
+ assign T_5048_zero3 = T_5069;
+ assign T_5048_mprv = T_5068;
+ assign T_5048_xs = T_5067;
+ assign T_5048_fs = T_5066;
+ assign T_5048_zero2 = T_5065;
+ assign T_5048_ps = T_5064;
+ assign T_5048_pie = T_5063;
+ assign T_5048_zero1 = T_5062;
+ assign T_5048_ie = T_5061;
+ assign T_5061 = read_mstatus[0];
+ assign T_5062 = read_mstatus[2:1];
+ assign T_5063 = read_mstatus[3];
+ assign T_5064 = read_mstatus[4];
+ assign T_5065 = read_mstatus[11:5];
+ assign T_5066 = read_mstatus[13:12];
+ assign T_5067 = read_mstatus[15:14];
+ assign T_5068 = read_mstatus[16];
+ assign T_5069 = read_mstatus[30:17];
+ assign T_5070 = read_mstatus[31];
+ assign T_5071 = read_mstatus[62:32];
+ assign T_5072 = read_mstatus[63];
+ assign T_5073_sd = T_5048_sd;
+ assign T_5073_zero4 = 1'h0;
+ assign T_5073_sd_rv32 = T_5048_sd_rv32;
+ assign T_5073_zero3 = 1'h0;
+ assign T_5073_mprv = T_5048_mprv;
+ assign T_5073_xs = T_5048_xs;
+ assign T_5073_fs = T_5048_fs;
+ assign T_5073_zero2 = 1'h0;
+ assign T_5073_ps = T_5048_ps;
+ assign T_5073_pie = T_5048_pie;
+ assign T_5073_zero1 = 1'h0;
+ assign T_5073_ie = T_5048_ie;
+ assign T_5109_mtip = 1'h0;
+ assign T_5109_htip = 1'h0;
+ assign T_5109_stip = 1'h0;
+ assign T_5109_utip = 1'h0;
+ assign T_5109_msip = 1'h0;
+ assign T_5109_hsip = 1'h0;
+ assign T_5109_ssip = 1'h0;
+ assign T_5109_usip = 1'h0;
+ assign T_5126_mtip = T_5109_mtip;
+ assign T_5126_htip = T_5109_htip;
+ assign T_5126_stip = reg_mip_stip;
+ assign T_5126_utip = T_5109_utip;
+ assign T_5126_msip = T_5109_msip;
+ assign T_5126_hsip = T_5109_hsip;
+ assign T_5126_ssip = reg_mip_ssip;
+ assign T_5126_usip = T_5109_usip;
+ assign T_5154_mtip = 1'h0;
+ assign T_5154_htip = 1'h0;
+ assign T_5154_stip = 1'h0;
+ assign T_5154_utip = 1'h0;
+ assign T_5154_msip = 1'h0;
+ assign T_5154_hsip = 1'h0;
+ assign T_5154_ssip = 1'h0;
+ assign T_5154_usip = 1'h0;
+ assign T_5171_mtip = T_5154_mtip;
+ assign T_5171_htip = T_5154_htip;
+ assign T_5171_stip = reg_mie_stip;
+ assign T_5171_utip = T_5154_utip;
+ assign T_5171_msip = T_5154_msip;
+ assign T_5171_hsip = T_5154_hsip;
+ assign T_5171_ssip = reg_mie_ssip;
+ assign T_5171_usip = T_5154_usip;
+ assign T_5180 = {T_5073_zero4,T_5073_sd_rv32};
+ assign T_5181 = {T_5073_sd,T_5180};
+ assign T_5182 = {T_5073_mprv,T_5073_xs};
+ assign T_5183 = {T_5073_zero3,T_5182};
+ assign T_5184 = {T_5181,T_5183};
+ assign T_5185 = {T_5073_zero2,T_5073_ps};
+ assign T_5186 = {T_5073_fs,T_5185};
+ assign T_5187 = {T_5073_zero1,T_5073_ie};
+ assign T_5188 = {T_5073_pie,T_5187};
+ assign T_5189 = {T_5186,T_5188};
+ assign T_5190 = {T_5184,T_5189};
+ assign T_5191 = {T_5126_mtip,T_5126_htip};
+ assign T_5192 = {T_5126_stip,T_5126_utip};
+ assign T_5193 = {T_5191,T_5192};
+ assign T_5194 = {T_5126_msip,T_5126_hsip};
+ assign T_5195 = {T_5126_ssip,T_5126_usip};
+ assign T_5196 = {T_5194,T_5195};
+ assign T_5197 = {T_5193,T_5196};
+ assign T_5198 = {T_5171_mtip,T_5171_htip};
+ assign T_5199 = {T_5171_stip,T_5171_utip};
+ assign T_5200 = {T_5198,T_5199};
+ assign T_5201 = {T_5171_msip,T_5171_hsip};
+ assign T_5202 = {T_5171_ssip,T_5171_usip};
+ assign T_5203 = {T_5201,T_5202};
+ assign T_5204 = {T_5200,T_5203};
+ assign T_5205 = reg_sbadaddr[39];
+ assign T_5207 = 24'h0 - T_5205;
+ assign T_5208 = T_5207[23:0];
+ assign T_5209 = {T_5208,reg_sbadaddr};
+ assign T_5211 = reg_sepc[39];
+ assign T_5213 = 24'h0 - T_5211;
+ assign T_5214 = T_5213[23:0];
+ assign T_5215 = {T_5214,reg_sepc};
+ assign T_5216 = reg_stvec[38];
+ assign T_5218 = 25'h0 - T_5216;
+ assign T_5219 = T_5218[24:0];
+ assign T_5220 = {T_5219,reg_stvec};
+ assign addr = cpu_ren ? io_rw_addr : host_csr_bits_addr;
+ assign T_5223 = addr == 1'h1;
+ assign T_5225 = addr == 2'h2;
+ assign T_5227 = addr == 2'h3;
+ assign T_5229 = addr == 12'hc00;
+ assign T_5231 = addr == 12'h900;
+ assign T_5233 = addr == 12'hc01;
+ assign T_5235 = addr == 12'h901;
+ assign T_5237 = addr == 12'hd01;
+ assign T_5239 = addr == 12'ha01;
+ assign T_5241 = addr == 11'h701;
+ assign T_5243 = addr == 12'hf00;
+ assign T_5245 = addr == 12'hf01;
+ assign T_5247 = addr == 10'h300;
+ assign T_5249 = addr == 10'h302;
+ assign T_5251 = addr == 11'h782;
+ assign T_5253 = addr == 10'h301;
+ assign T_5255 = addr == 11'h784;
+ assign T_5257 = addr == 11'h783;
+ assign T_5259 = addr == 10'h344;
+ assign T_5261 = addr == 10'h304;
+ assign T_5263 = addr == 10'h340;
+ assign T_5265 = addr == 10'h341;
+ assign T_5267 = addr == 10'h343;
+ assign T_5269 = addr == 10'h342;
+ assign T_5271 = addr == 10'h321;
+ assign T_5273 = addr == 12'hf10;
+ assign T_5275 = addr == 8'hc0;
+ assign T_5277 = addr == 11'h780;
+ assign T_5279 = addr == 11'h781;
+ assign T_5281 = addr == 12'hc02;
+ assign T_5283 = addr == 12'h902;
+ assign T_5285 = addr == 12'hcc0;
+ assign T_5287 = addr == 12'hcc1;
+ assign T_5289 = addr == 12'hcc2;
+ assign T_5291 = addr == 12'hcc3;
+ assign T_5293 = addr == 12'hcc4;
+ assign T_5295 = addr == 12'hcc5;
+ assign T_5297 = addr == 12'hcc6;
+ assign T_5299 = addr == 12'hcc7;
+ assign T_5301 = addr == 12'hcc8;
+ assign T_5303 = addr == 12'hcc9;
+ assign T_5305 = addr == 12'hcca;
+ assign T_5307 = addr == 12'hccb;
+ assign T_5309 = addr == 12'hccc;
+ assign T_5311 = addr == 12'hccd;
+ assign T_5313 = addr == 12'hcce;
+ assign T_5315 = addr == 12'hccf;
+ assign T_5317 = addr == 9'h100;
+ assign T_5319 = addr == 9'h144;
+ assign T_5321 = addr == 9'h104;
+ assign T_5323 = addr == 9'h140;
+ assign T_5325 = addr == 12'hd42;
+ assign T_5327 = addr == 12'hd43;
+ assign T_5329 = addr == 9'h180;
+ assign T_5331 = addr == 9'h181;
+ assign T_5333 = addr == 9'h141;
+ assign T_5335 = addr == 9'h101;
+ assign T_5336 = T_5223 | T_5225;
+ assign T_5337 = T_5336 | T_5227;
+ assign T_5338 = T_5337 | T_5229;
+ assign T_5339 = T_5338 | T_5231;
+ assign T_5340 = T_5339 | T_5233;
+ assign T_5341 = T_5340 | T_5235;
+ assign T_5342 = T_5341 | T_5237;
+ assign T_5343 = T_5342 | T_5239;
+ assign T_5344 = T_5343 | T_5241;
+ assign T_5345 = T_5344 | T_5243;
+ assign T_5346 = T_5345 | T_5245;
+ assign T_5347 = T_5346 | T_5247;
+ assign T_5348 = T_5347 | T_5249;
+ assign T_5349 = T_5348 | T_5251;
+ assign T_5350 = T_5349 | T_5253;
+ assign T_5351 = T_5350 | T_5255;
+ assign T_5352 = T_5351 | T_5257;
+ assign T_5353 = T_5352 | T_5259;
+ assign T_5354 = T_5353 | T_5261;
+ assign T_5355 = T_5354 | T_5263;
+ assign T_5356 = T_5355 | T_5265;
+ assign T_5357 = T_5356 | T_5267;
+ assign T_5358 = T_5357 | T_5269;
+ assign T_5359 = T_5358 | T_5271;
+ assign T_5360 = T_5359 | T_5273;
+ assign T_5361 = T_5360 | T_5275;
+ assign T_5362 = T_5361 | T_5277;
+ assign T_5363 = T_5362 | T_5279;
+ assign T_5364 = T_5363 | T_5281;
+ assign T_5365 = T_5364 | T_5283;
+ assign T_5366 = T_5365 | T_5285;
+ assign T_5367 = T_5366 | T_5287;
+ assign T_5368 = T_5367 | T_5289;
+ assign T_5369 = T_5368 | T_5291;
+ assign T_5370 = T_5369 | T_5293;
+ assign T_5371 = T_5370 | T_5295;
+ assign T_5372 = T_5371 | T_5297;
+ assign T_5373 = T_5372 | T_5299;
+ assign T_5374 = T_5373 | T_5301;
+ assign T_5375 = T_5374 | T_5303;
+ assign T_5376 = T_5375 | T_5305;
+ assign T_5377 = T_5376 | T_5307;
+ assign T_5378 = T_5377 | T_5309;
+ assign T_5379 = T_5378 | T_5311;
+ assign T_5380 = T_5379 | T_5313;
+ assign T_5381 = T_5380 | T_5315;
+ assign T_5382 = T_5381 | T_5317;
+ assign T_5383 = T_5382 | T_5319;
+ assign T_5384 = T_5383 | T_5321;
+ assign T_5385 = T_5384 | T_5323;
+ assign T_5386 = T_5385 | T_5325;
+ assign T_5387 = T_5386 | T_5327;
+ assign T_5388 = T_5387 | T_5329;
+ assign T_5389 = T_5388 | T_5331;
+ assign T_5390 = T_5389 | T_5333;
+ assign addr_valid = T_5390 | T_5335;
+ assign T_5392 = T_5223 | T_5225;
+ assign fp_csr = T_5392 | T_5227;
+ assign csr_addr_priv = io_rw_addr[9:8];
+ assign priv_sufficient = reg_mstatus_prv >= csr_addr_priv;
+ assign T_5396 = io_rw_addr[11:10];
+ assign T_5397 = ~ T_5396;
+ assign read_only = T_5397 == 1'h0;
+ assign T_5400 = io_rw_cmd != 3'h5;
+ assign T_5401 = cpu_ren & T_5400;
+ assign cpu_wen = T_5401 & priv_sufficient;
+ assign T_5404 = read_only == 1'h0;
+ assign T_5405 = cpu_wen & T_5404;
+ assign T_5406 = host_csr_req_fire & host_csr_bits_rw;
+ assign wen = T_5405 | T_5406;
+ assign T_5408 = io_rw_cmd == 3'h1;
+ assign T_5409 = io_rw_cmd == 3'h3;
+ assign T_5410 = ~ io_rw_wdata;
+ assign T_5411 = io_rw_rdata & T_5410;
+ assign T_5412 = io_rw_cmd == 3'h2;
+ assign T_5413 = io_rw_rdata | io_rw_wdata;
+ assign T_5414 = T_5412 ? T_5413 : host_csr_bits_data;
+ assign T_5415 = T_5409 ? T_5411 : T_5414;
+ assign wdata = T_5408 ? io_rw_wdata : T_5415;
+ assign T_5417 = io_rw_addr[8];
+ assign T_5419 = T_5417 == 1'h0;
+ assign T_5420 = io_rw_addr[0];
+ assign T_5422 = T_5420 == 1'h0;
+ assign T_5423 = T_5419 & T_5422;
+ assign insn_call = T_5423 & system_insn;
+ assign T_5425 = io_rw_addr[8];
+ assign T_5427 = T_5425 == 1'h0;
+ assign T_5428 = io_rw_addr[0];
+ assign T_5429 = T_5427 & T_5428;
+ assign insn_break = T_5429 & system_insn;
+ assign T_5431 = io_rw_addr[8];
+ assign T_5432 = io_rw_addr[1];
+ assign T_5434 = T_5432 == 1'h0;
+ assign T_5435 = T_5431 & T_5434;
+ assign T_5436 = io_rw_addr[0];
+ assign T_5438 = T_5436 == 1'h0;
+ assign T_5439 = T_5435 & T_5438;
+ assign T_5440 = T_5439 & system_insn;
+ assign insn_ret = T_5440 & priv_sufficient;
+ assign T_5442 = io_rw_addr[8];
+ assign T_5443 = io_rw_addr[1];
+ assign T_5445 = T_5443 == 1'h0;
+ assign T_5446 = T_5442 & T_5445;
+ assign T_5447 = io_rw_addr[0];
+ assign T_5448 = T_5446 & T_5447;
+ assign T_5449 = T_5448 & system_insn;
+ assign insn_sfence_vm = T_5449 & priv_sufficient;
+ assign T_5451 = io_rw_addr[2];
+ assign maybe_insn_redirect_trap = T_5451 & system_insn;
+ assign insn_redirect_trap = maybe_insn_redirect_trap & priv_sufficient;
+ assign T_5454 = io_rw_addr[8];
+ assign T_5455 = io_rw_addr[1];
+ assign T_5456 = T_5454 & T_5455;
+ assign T_5457 = io_rw_addr[0];
+ assign T_5459 = T_5457 == 1'h0;
+ assign T_5460 = T_5456 & T_5459;
+ assign T_5461 = T_5460 & system_insn;
+ assign insn_wfi = T_5461 & priv_sufficient;
+ assign T_5463 = cpu_wen & read_only;
+ assign T_5465 = priv_sufficient == 1'h0;
+ assign T_5467 = addr_valid == 1'h0;
+ assign T_5468 = T_5465 | T_5467;
+ assign T_5470 = io_status_fs != 1'h0;
+ assign T_5472 = T_5470 == 1'h0;
+ assign T_5473 = fp_csr & T_5472;
+ assign T_5474 = T_5468 | T_5473;
+ assign T_5475 = cpu_ren & T_5474;
+ assign T_5476 = T_5463 | T_5475;
+ assign T_5478 = priv_sufficient == 1'h0;
+ assign T_5479 = system_insn & T_5478;
+ assign T_5480 = T_5476 | T_5479;
+ assign T_5481 = T_5480 | insn_call;
+ assign csr_xcpt = T_5481 | insn_break;
+ assign T_5485 = io_exception | csr_xcpt;
+ assign T_5486 = reg_mstatus_prv << 6;
+ assign T_5488 = T_5486 + 9'h100;
+ assign T_5489 = T_5488[8:0];
+ assign T_5490 = reg_stvec[38];
+ assign T_5491 = {T_5490,reg_stvec};
+ assign T_5492 = reg_mstatus_prv[1];
+ assign T_5494 = T_5492 | 1'h0;
+ assign T_5495 = T_5494 ? reg_mepc : reg_sepc;
+ assign T_5496 = maybe_insn_redirect_trap ? T_5491 : T_5495;
+ assign T_5497 = T_5485 ? T_5489 : T_5496;
+ assign T_5498 = insn_ret | insn_redirect_trap;
+ assign T_5500 = reg_mstatus_fs != 1'h0;
+ assign T_5502 = 2'h0 - T_5500;
+ assign T_5503 = T_5502[1:0];
+ assign T_5505 = reg_mstatus_xs != 1'h0;
+ assign T_5507 = 2'h0 - T_5505;
+ assign T_5508 = T_5507[1:0];
+ assign T_5509 = ~ io_status_fs;
+ assign T_5511 = T_5509 == 1'h0;
+ assign T_5512 = ~ io_status_xs;
+ assign T_5514 = T_5512 == 1'h0;
+ assign T_5515 = T_5511 | T_5514;
+ assign T_5516 = io_exception | csr_xcpt;
+ assign T_5520 = ~ io_pc;
+ assign T_5522 = T_5520 | 2'h3;
+ assign T_5523 = ~ T_5522;
+ assign T_5527 = reg_mstatus_prv + 4'h8;
+ assign T_5528 = T_5527[3:0];
+ assign T_5530 = io_cause == 3'h5;
+ assign T_5532 = io_cause == 3'h4;
+ assign T_5533 = T_5530 | T_5532;
+ assign T_5535 = io_cause == 3'h7;
+ assign T_5536 = T_5533 | T_5535;
+ assign T_5538 = io_cause == 3'h6;
+ assign T_5539 = T_5536 | T_5538;
+ assign T_5540 = io_rw_wdata[63:39];
+ assign T_5541 = io_rw_wdata[38:0];
+ assign T_5542 = $signed(T_5541);
+ assign GEN_0 = $signed(1'h0);
+ assign T_5544 = $signed(T_5542) < $signed(GEN_0);
+ assign T_5545 = ~ T_5540;
+ assign T_5547 = T_5545 == 1'h0;
+ assign T_5549 = T_5540 != 1'h0;
+ assign T_5550 = T_5544 ? T_5547 : T_5549;
+ assign T_5551 = {T_5550,T_5541};
+ assign T_5556 = {1'h0,insn_redirect_trap};
+ assign T_5557 = insn_ret + T_5556;
+ assign T_5558 = T_5557[1:0];
+ assign T_5561 = {1'h0,csr_xcpt};
+ assign T_5562 = io_exception + T_5561;
+ assign T_5563 = T_5562[1:0];
+ assign T_5564 = {1'h0,T_5563};
+ assign T_5565 = T_5558 + T_5564;
+ assign T_5566 = T_5565[2:0];
+ assign T_5568 = T_5566 <= 1'h1;
+ assign T_5570 = reset == 1'h0;
+ assign T_5572 = T_5568 == 1'h0;
+ assign T_5574 = reset == 1'h0;
+ assign T_5575 = reg_time >= reg_mtimecmp;
+ assign T_5578 = host_csr_bits_rw == 1'h0;
+ assign T_5579 = host_csr_req_fire & T_5578;
+ assign T_5580 = T_5579 & T_5277;
+ assign T_5583 = T_5223 ? reg_fflags : 1'h0;
+ assign T_5585 = T_5225 ? reg_frm : 1'h0;
+ assign T_5587 = T_5227 ? T_4990 : 1'h0;
+ assign T_5589 = T_5229 ? T_4615 : 1'h0;
+ assign T_5591 = T_5231 ? T_4615 : 1'h0;
+ assign T_5593 = T_5233 ? reg_time : 1'h0;
+ assign T_5595 = T_5235 ? reg_time : 1'h0;
+ assign T_5597 = T_5237 ? reg_time : 1'h0;
+ assign T_5599 = T_5239 ? reg_time : 1'h0;
+ assign T_5601 = T_5241 ? reg_time : 1'h0;
+ assign T_5603 = T_5243 ? 64'h8000000000041129 : 1'h0;
+ assign T_5605 = T_5245 ? 1'h1 : 1'h0;
+ assign T_5607 = T_5247 ? read_mstatus : 1'h0;
+ assign T_5609 = T_5249 ? 1'h0 : 1'h0;
+ assign T_5611 = T_5251 ? 1'h0 : 1'h0;
+ assign T_5613 = T_5253 ? 9'h100 : 1'h0;
+ assign T_5615 = T_5255 ? 31'h40000000 : 1'h0;
+ assign T_5617 = T_5257 ? 1'h0 : 1'h0;
+ assign T_5619 = T_5259 ? T_5004 : 1'h0;
+ assign T_5621 = T_5261 ? T_5011 : 1'h0;
+ assign T_5623 = T_5263 ? reg_mscratch : 1'h0;
+ assign T_5625 = T_5265 ? T_5016 : 1'h0;
+ assign T_5627 = T_5267 ? T_5021 : 1'h0;
+ assign T_5629 = T_5269 ? reg_mcause : 1'h0;
+ assign T_5631 = T_5271 ? reg_mtimecmp : 1'h0;
+ assign T_5633 = T_5273 ? io_host_id : 1'h0;
+ assign T_5635 = reg_stats << 0;
+ assign T_5636 = T_5275 ? T_5635 : 1'h0;
+ assign T_5638 = T_5277 ? reg_tohost : 1'h0;
+ assign T_5640 = T_5279 ? reg_fromhost : 1'h0;
+ assign T_5642 = T_5281 ? T_4598 : 1'h0;
+ assign T_5644 = T_5283 ? T_4598 : 1'h0;
+ assign T_5646 = T_5285 ? T_4631 : 1'h0;
+ assign T_5648 = T_5287 ? T_4647 : 1'h0;
+ assign T_5650 = T_5289 ? T_4663 : 1'h0;
+ assign T_5652 = T_5291 ? T_4679 : 1'h0;
+ assign T_5654 = T_5293 ? T_4695 : 1'h0;
+ assign T_5656 = T_5295 ? T_4711 : 1'h0;
+ assign T_5658 = T_5297 ? T_4727 : 1'h0;
+ assign T_5660 = T_5299 ? T_4743 : 1'h0;
+ assign T_5662 = T_5301 ? T_4759 : 1'h0;
+ assign T_5664 = T_5303 ? T_4775 : 1'h0;
+ assign T_5666 = T_5305 ? T_4791 : 1'h0;
+ assign T_5668 = T_5307 ? T_4807 : 1'h0;
+ assign T_5670 = T_5309 ? T_4823 : 1'h0;
+ assign T_5672 = T_5311 ? T_4839 : 1'h0;
+ assign T_5674 = T_5313 ? T_4855 : 1'h0;
+ assign T_5676 = T_5315 ? T_4871 : 1'h0;
+ assign T_5678 = T_5317 ? T_5190 : 1'h0;
+ assign T_5680 = T_5319 ? T_5197 : 1'h0;
+ assign T_5682 = T_5321 ? T_5204 : 1'h0;
+ assign T_5684 = T_5323 ? reg_sscratch : 1'h0;
+ assign T_5686 = T_5325 ? reg_scause : 1'h0;
+ assign T_5688 = T_5327 ? T_5209 : 1'h0;
+ assign T_5690 = T_5329 ? reg_sptbr : 1'h0;
+ assign T_5692 = T_5331 ? 1'h0 : 1'h0;
+ assign T_5694 = T_5333 ? T_5215 : 1'h0;
+ assign T_5696 = T_5335 ? T_5220 : 1'h0;
+ assign T_5698 = T_5583 | T_5585;
+ assign T_5699 = T_5698 | T_5587;
+ assign T_5700 = T_5699 | T_5589;
+ assign T_5701 = T_5700 | T_5591;
+ assign T_5702 = T_5701 | T_5593;
+ assign T_5703 = T_5702 | T_5595;
+ assign T_5704 = T_5703 | T_5597;
+ assign T_5705 = T_5704 | T_5599;
+ assign T_5706 = T_5705 | T_5601;
+ assign T_5707 = T_5706 | T_5603;
+ assign T_5708 = T_5707 | T_5605;
+ assign T_5709 = T_5708 | T_5607;
+ assign T_5710 = T_5709 | T_5609;
+ assign T_5711 = T_5710 | T_5611;
+ assign T_5712 = T_5711 | T_5613;
+ assign T_5713 = T_5712 | T_5615;
+ assign T_5714 = T_5713 | T_5617;
+ assign T_5715 = T_5714 | T_5619;
+ assign T_5716 = T_5715 | T_5621;
+ assign T_5717 = T_5716 | T_5623;
+ assign T_5718 = T_5717 | T_5625;
+ assign T_5719 = T_5718 | T_5627;
+ assign T_5720 = T_5719 | T_5629;
+ assign T_5721 = T_5720 | T_5631;
+ assign T_5722 = T_5721 | T_5633;
+ assign T_5723 = T_5722 | T_5636;
+ assign T_5724 = T_5723 | T_5638;
+ assign T_5725 = T_5724 | T_5640;
+ assign T_5726 = T_5725 | T_5642;
+ assign T_5727 = T_5726 | T_5644;
+ assign T_5728 = T_5727 | T_5646;
+ assign T_5729 = T_5728 | T_5648;
+ assign T_5730 = T_5729 | T_5650;
+ assign T_5731 = T_5730 | T_5652;
+ assign T_5732 = T_5731 | T_5654;
+ assign T_5733 = T_5732 | T_5656;
+ assign T_5734 = T_5733 | T_5658;
+ assign T_5735 = T_5734 | T_5660;
+ assign T_5736 = T_5735 | T_5662;
+ assign T_5737 = T_5736 | T_5664;
+ assign T_5738 = T_5737 | T_5666;
+ assign T_5739 = T_5738 | T_5668;
+ assign T_5740 = T_5739 | T_5670;
+ assign T_5741 = T_5740 | T_5672;
+ assign T_5742 = T_5741 | T_5674;
+ assign T_5743 = T_5742 | T_5676;
+ assign T_5744 = T_5743 | T_5678;
+ assign T_5745 = T_5744 | T_5680;
+ assign T_5746 = T_5745 | T_5682;
+ assign T_5747 = T_5746 | T_5684;
+ assign T_5748 = T_5747 | T_5686;
+ assign T_5749 = T_5748 | T_5688;
+ assign T_5750 = T_5749 | T_5690;
+ assign T_5751 = T_5750 | T_5692;
+ assign T_5752 = T_5751 | T_5694;
+ assign T_5753 = T_5752 | T_5696;
+ assign T_5754 = T_5753;
+ assign T_5755 = reg_fflags | io_fcsr_flags_bits;
+ assign T_5790_sd = T_5822;
+ assign T_5790_zero2 = T_5821;
+ assign T_5790_sd_rv32 = T_5820;
+ assign T_5790_zero1 = T_5819;
+ assign T_5790_vm = T_5818;
+ assign T_5790_mprv = T_5817;
+ assign T_5790_xs = T_5816;
+ assign T_5790_fs = T_5815;
+ assign T_5790_prv3 = T_5814;
+ assign T_5790_ie3 = T_5813;
+ assign T_5790_prv2 = T_5812;
+ assign T_5790_ie2 = T_5811;
+ assign T_5790_prv1 = T_5810;
+ assign T_5790_ie1 = T_5809;
+ assign T_5790_prv = T_5808;
+ assign T_5790_ie = T_5807;
+ assign T_5807 = wdata[0];
+ assign T_5808 = wdata[2:1];
+ assign T_5809 = wdata[3];
+ assign T_5810 = wdata[5:4];
+ assign T_5811 = wdata[6];
+ assign T_5812 = wdata[8:7];
+ assign T_5813 = wdata[9];
+ assign T_5814 = wdata[11:10];
+ assign T_5815 = wdata[13:12];
+ assign T_5816 = wdata[15:14];
+ assign T_5817 = wdata[16];
+ assign T_5818 = wdata[21:17];
+ assign T_5819 = wdata[30:22];
+ assign T_5820 = wdata[31];
+ assign T_5821 = wdata[62:32];
+ assign T_5822 = wdata[63];
+ assign T_5827_0 = 2'h3;
+ assign T_5827_1 = 1'h0;
+ assign T_5827_2 = 1'h1;
+ assign T_5832 = T_5827_0 == T_5790_prv;
+ assign T_5833 = T_5827_1 == T_5790_prv;
+ assign T_5834 = T_5827_2 == T_5790_prv;
+ assign T_5836 = 1'h0 | T_5832;
+ assign T_5837 = T_5836 | T_5833;
+ assign T_5838 = T_5837 | T_5834;
+ assign T_5839 = T_5827_0 == T_5790_prv1;
+ assign T_5840 = T_5827_1 == T_5790_prv1;
+ assign T_5841 = T_5827_2 == T_5790_prv1;
+ assign T_5843 = 1'h0 | T_5839;
+ assign T_5844 = T_5843 | T_5840;
+ assign T_5845 = T_5844 | T_5841;
+ assign T_5846 = T_5827_0 == T_5790_prv2;
+ assign T_5847 = T_5827_1 == T_5790_prv2;
+ assign T_5848 = T_5827_2 == T_5790_prv2;
+ assign T_5850 = 1'h0 | T_5846;
+ assign T_5851 = T_5850 | T_5847;
+ assign T_5852 = T_5851 | T_5848;
+ assign T_5854 = T_5790_vm == 1'h0;
+ assign T_5857 = T_5790_vm == 4'h9;
+ assign T_5877_mtip = T_5893;
+ assign T_5877_htip = T_5892;
+ assign T_5877_stip = T_5891;
+ assign T_5877_utip = T_5890;
+ assign T_5877_msip = T_5889;
+ assign T_5877_hsip = T_5888;
+ assign T_5877_ssip = T_5887;
+ assign T_5877_usip = T_5886;
+ assign T_5886 = wdata[0];
+ assign T_5887 = wdata[1];
+ assign T_5888 = wdata[2];
+ assign T_5889 = wdata[3];
+ assign T_5890 = wdata[4];
+ assign T_5891 = wdata[5];
+ assign T_5892 = wdata[6];
+ assign T_5893 = wdata[7];
+ assign T_5894 = wdata[0];
+ assign T_5913_mtip = T_5929;
+ assign T_5913_htip = T_5928;
+ assign T_5913_stip = T_5927;
+ assign T_5913_utip = T_5926;
+ assign T_5913_msip = T_5925;
+ assign T_5913_hsip = T_5924;
+ assign T_5913_ssip = T_5923;
+ assign T_5913_usip = T_5922;
+ assign T_5922 = wdata[0];
+ assign T_5923 = wdata[1];
+ assign T_5924 = wdata[2];
+ assign T_5925 = wdata[3];
+ assign T_5926 = wdata[4];
+ assign T_5927 = wdata[5];
+ assign T_5928 = wdata[6];
+ assign T_5929 = wdata[7];
+ assign T_5930 = wdata[63:5];
+ assign T_5931 = ~ wdata;
+ assign T_5933 = T_5931 | 2'h3;
+ assign T_5934 = ~ T_5933;
+ assign T_5936 = wdata & 64'h800000000000001f;
+ assign T_5937 = wdata[39:0];
+ assign T_5938 = wdata[5:0];
+ assign T_5939 = wdata[63:6];
+ assign T_5942 = reg_fromhost == 1'h0;
+ assign T_5944 = host_csr_req_fire == 1'h0;
+ assign T_5945 = T_5942 | T_5944;
+ assign T_5947 = reg_tohost == 1'h0;
+ assign T_5948 = T_5947 | host_csr_req_fire;
+ assign T_5949 = wdata[0];
+ assign T_5976_sd = T_6000;
+ assign T_5976_zero4 = T_5999;
+ assign T_5976_sd_rv32 = T_5998;
+ assign T_5976_zero3 = T_5997;
+ assign T_5976_mprv = T_5996;
+ assign T_5976_xs = T_5995;
+ assign T_5976_fs = T_5994;
+ assign T_5976_zero2 = T_5993;
+ assign T_5976_ps = T_5992;
+ assign T_5976_pie = T_5991;
+ assign T_5976_zero1 = T_5990;
+ assign T_5976_ie = T_5989;
+ assign T_5989 = wdata[0];
+ assign T_5990 = wdata[2:1];
+ assign T_5991 = wdata[3];
+ assign T_5992 = wdata[4];
+ assign T_5993 = wdata[11:5];
+ assign T_5994 = wdata[13:12];
+ assign T_5995 = wdata[15:14];
+ assign T_5996 = wdata[16];
+ assign T_5997 = wdata[30:17];
+ assign T_5998 = wdata[31];
+ assign T_5999 = wdata[62:32];
+ assign T_6000 = wdata[63];
+ assign T_6003 = T_5976_ps ? 1'h1 : 1'h0;
+ assign T_6022_mtip = T_6038;
+ assign T_6022_htip = T_6037;
+ assign T_6022_stip = T_6036;
+ assign T_6022_utip = T_6035;
+ assign T_6022_msip = T_6034;
+ assign T_6022_hsip = T_6033;
+ assign T_6022_ssip = T_6032;
+ assign T_6022_usip = T_6031;
+ assign T_6031 = wdata[0];
+ assign T_6032 = wdata[1];
+ assign T_6033 = wdata[2];
+ assign T_6034 = wdata[3];
+ assign T_6035 = wdata[4];
+ assign T_6036 = wdata[5];
+ assign T_6037 = wdata[6];
+ assign T_6038 = wdata[7];
+ assign T_6057_mtip = T_6073;
+ assign T_6057_htip = T_6072;
+ assign T_6057_stip = T_6071;
+ assign T_6057_utip = T_6070;
+ assign T_6057_msip = T_6069;
+ assign T_6057_hsip = T_6068;
+ assign T_6057_ssip = T_6067;
+ assign T_6057_usip = T_6066;
+ assign T_6066 = wdata[0];
+ assign T_6067 = wdata[1];
+ assign T_6068 = wdata[2];
+ assign T_6069 = wdata[3];
+ assign T_6070 = wdata[4];
+ assign T_6071 = wdata[5];
+ assign T_6072 = wdata[6];
+ assign T_6073 = wdata[7];
+ assign T_6074 = wdata[31:12];
+ assign T_6076 = {T_6074,12'h0};
+ assign T_6077 = ~ wdata;
+ assign T_6079 = T_6077 | 2'h3;
+ assign T_6080 = ~ T_6079;
+ assign T_6081 = ~ wdata;
+ assign T_6083 = T_6081 | 2'h3;
+ assign T_6084 = ~ T_6083;
+ assign GEN_1 = T_5570 & T_5572;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ reg_mstatus_sd = {1{$random}};
+ reg_mstatus_zero2 = {1{$random}};
+ reg_mstatus_sd_rv32 = {1{$random}};
+ reg_mstatus_zero1 = {1{$random}};
+ reg_mstatus_vm = {1{$random}};
+ reg_mstatus_mprv = {1{$random}};
+ reg_mstatus_xs = {1{$random}};
+ reg_mstatus_fs = {1{$random}};
+ reg_mstatus_prv3 = {1{$random}};
+ reg_mstatus_ie3 = {1{$random}};
+ reg_mstatus_prv2 = {1{$random}};
+ reg_mstatus_ie2 = {1{$random}};
+ reg_mstatus_prv1 = {1{$random}};
+ reg_mstatus_ie1 = {1{$random}};
+ reg_mstatus_prv = {1{$random}};
+ reg_mstatus_ie = {1{$random}};
+ reg_mie_mtip = {1{$random}};
+ reg_mie_htip = {1{$random}};
+ reg_mie_stip = {1{$random}};
+ reg_mie_utip = {1{$random}};
+ reg_mie_msip = {1{$random}};
+ reg_mie_hsip = {1{$random}};
+ reg_mie_ssip = {1{$random}};
+ reg_mie_usip = {1{$random}};
+ reg_mip_mtip = {1{$random}};
+ reg_mip_htip = {1{$random}};
+ reg_mip_stip = {1{$random}};
+ reg_mip_utip = {1{$random}};
+ reg_mip_msip = {1{$random}};
+ reg_mip_hsip = {1{$random}};
+ reg_mip_ssip = {1{$random}};
+ reg_mip_usip = {1{$random}};
+ reg_mepc = {2{$random}};
+ reg_mcause = {2{$random}};
+ reg_mbadaddr = {2{$random}};
+ reg_mscratch = {2{$random}};
+ reg_sepc = {2{$random}};
+ reg_scause = {2{$random}};
+ reg_sbadaddr = {2{$random}};
+ reg_sscratch = {2{$random}};
+ reg_stvec = {2{$random}};
+ reg_mtimecmp = {2{$random}};
+ reg_sptbr = {1{$random}};
+ reg_wfi = {1{$random}};
+ reg_tohost = {2{$random}};
+ reg_fromhost = {2{$random}};
+ reg_stats = {1{$random}};
+ reg_time = {2{$random}};
+ T_4584 = {1{$random}};
+ T_4592 = {2{$random}};
+ T_4601 = {1{$random}};
+ T_4609 = {2{$random}};
+ T_4617 = {1{$random}};
+ T_4625 = {2{$random}};
+ T_4633 = {1{$random}};
+ T_4641 = {2{$random}};
+ T_4649 = {1{$random}};
+ T_4657 = {2{$random}};
+ T_4665 = {1{$random}};
+ T_4673 = {2{$random}};
+ T_4681 = {1{$random}};
+ T_4689 = {2{$random}};
+ T_4697 = {1{$random}};
+ T_4705 = {2{$random}};
+ T_4713 = {1{$random}};
+ T_4721 = {2{$random}};
+ T_4729 = {1{$random}};
+ T_4737 = {2{$random}};
+ T_4745 = {1{$random}};
+ T_4753 = {2{$random}};
+ T_4761 = {1{$random}};
+ T_4769 = {2{$random}};
+ T_4777 = {1{$random}};
+ T_4785 = {2{$random}};
+ T_4793 = {1{$random}};
+ T_4801 = {2{$random}};
+ T_4809 = {1{$random}};
+ T_4817 = {2{$random}};
+ T_4825 = {1{$random}};
+ T_4833 = {2{$random}};
+ T_4841 = {1{$random}};
+ T_4849 = {2{$random}};
+ T_4857 = {1{$random}};
+ T_4865 = {2{$random}};
+ reg_fflags = {1{$random}};
+ reg_frm = {1{$random}};
+ host_csr_req_valid = {1{$random}};
+ host_csr_rep_valid = {1{$random}};
+ host_csr_bits_rw = {1{$random}};
+ host_csr_bits_addr = {1{$random}};
+ host_csr_bits_data = {2{$random}};
+ GEN_2 = {1{$random}};
+ GEN_3 = {1{$random}};
+ GEN_4 = {1{$random}};
+ GEN_5 = {1{$random}};
+ GEN_6 = {1{$random}};
+ GEN_7 = {1{$random}};
+ GEN_8 = {1{$random}};
+ GEN_9 = {1{$random}};
+ GEN_10 = {1{$random}};
+ GEN_11 = {2{$random}};
+ GEN_12 = {2{$random}};
+ GEN_13 = {1{$random}};
+ GEN_14 = {1{$random}};
+ GEN_15 = {1{$random}};
+ GEN_16 = {2{$random}};
+ GEN_17 = {1{$random}};
+ GEN_18 = {1{$random}};
+ GEN_19 = {1{$random}};
+ GEN_20 = {2{$random}};
+ GEN_21 = {1{$random}};
+ GEN_22 = {1{$random}};
+ GEN_23 = {1{$random}};
+ GEN_24 = {2{$random}};
+ GEN_25 = {2{$random}};
+ GEN_26 = {1{$random}};
+ GEN_27 = {1{$random}};
+ GEN_28 = {1{$random}};
+ GEN_29 = {1{$random}};
+ GEN_30 = {1{$random}};
+ GEN_31 = {1{$random}};
+ GEN_32 = {1{$random}};
+ GEN_33 = {1{$random}};
+ GEN_34 = {1{$random}};
+ GEN_35 = {1{$random}};
+ GEN_36 = {1{$random}};
+ GEN_37 = {1{$random}};
+ GEN_38 = {1{$random}};
+ GEN_39 = {1{$random}};
+ GEN_40 = {1{$random}};
+ GEN_41 = {4{$random}};
+ GEN_42 = {1{$random}};
+ GEN_43 = {1{$random}};
+ GEN_44 = {1{$random}};
+ GEN_45 = {1{$random}};
+ GEN_46 = {1{$random}};
+ GEN_47 = {1{$random}};
+ GEN_48 = {1{$random}};
+ GEN_49 = {1{$random}};
+ GEN_50 = {1{$random}};
+ GEN_51 = {1{$random}};
+ GEN_52 = {1{$random}};
+ GEN_53 = {1{$random}};
+ GEN_54 = {1{$random}};
+ GEN_55 = {1{$random}};
+ GEN_56 = {1{$random}};
+ GEN_57 = {1{$random}};
+ GEN_58 = {1{$random}};
+ GEN_59 = {1{$random}};
+ GEN_60 = {1{$random}};
+ GEN_61 = {1{$random}};
+ GEN_62 = {1{$random}};
+ GEN_63 = {1{$random}};
+ GEN_64 = {1{$random}};
+ GEN_65 = {1{$random}};
+ GEN_66 = {1{$random}};
+ GEN_67 = {1{$random}};
+ GEN_68 = {1{$random}};
+ GEN_69 = {1{$random}};
+ GEN_70 = {1{$random}};
+ GEN_71 = {1{$random}};
+ GEN_72 = {1{$random}};
+ GEN_73 = {1{$random}};
+ GEN_74 = {1{$random}};
+ GEN_75 = {1{$random}};
+ GEN_76 = {1{$random}};
+ GEN_77 = {1{$random}};
+ GEN_78 = {1{$random}};
+ GEN_79 = {1{$random}};
+ GEN_80 = {1{$random}};
+ GEN_81 = {1{$random}};
+ GEN_82 = {1{$random}};
+ GEN_83 = {1{$random}};
+ GEN_84 = {1{$random}};
+ GEN_85 = {1{$random}};
+ GEN_86 = {1{$random}};
+ GEN_87 = {1{$random}};
+ GEN_88 = {1{$random}};
+ GEN_89 = {1{$random}};
+ GEN_90 = {1{$random}};
+ GEN_91 = {1{$random}};
+ GEN_92 = {1{$random}};
+ GEN_93 = {1{$random}};
+ GEN_94 = {1{$random}};
+ GEN_95 = {1{$random}};
+ GEN_96 = {1{$random}};
+ GEN_97 = {1{$random}};
+ GEN_98 = {1{$random}};
+ GEN_99 = {1{$random}};
+ GEN_100 = {1{$random}};
+ GEN_101 = {1{$random}};
+ GEN_102 = {1{$random}};
+ GEN_103 = {1{$random}};
+ GEN_104 = {1{$random}};
+ GEN_105 = {1{$random}};
+ GEN_106 = {1{$random}};
+ GEN_107 = {1{$random}};
+ GEN_108 = {1{$random}};
+ GEN_109 = {1{$random}};
+ GEN_110 = {1{$random}};
+ GEN_111 = {1{$random}};
+ GEN_112 = {1{$random}};
+ GEN_113 = {1{$random}};
+ GEN_114 = {1{$random}};
+ GEN_115 = {1{$random}};
+ GEN_116 = {1{$random}};
+ GEN_117 = {1{$random}};
+ GEN_118 = {1{$random}};
+ GEN_119 = {1{$random}};
+ GEN_120 = {1{$random}};
+ GEN_121 = {1{$random}};
+ GEN_122 = {3{$random}};
+ GEN_123 = {1{$random}};
+ GEN_124 = {1{$random}};
+ GEN_125 = {1{$random}};
+ GEN_126 = {1{$random}};
+ GEN_127 = {1{$random}};
+ GEN_128 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(1'h0) begin
+ ;
+ end else begin
+ if(reset) begin
+ reg_mstatus_sd <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(reset) begin
+ reg_mstatus_zero2 <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(reset) begin
+ reg_mstatus_sd_rv32 <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(reset) begin
+ reg_mstatus_zero1 <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(reset) begin
+ reg_mstatus_vm <= 1'h0;
+ end else begin
+ if(wen) begin
+ if(T_5247) begin
+ if(T_5857) begin
+ reg_mstatus_vm <= 4'h9;
+ end else begin
+ if(T_5854) begin
+ reg_mstatus_vm <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(reset) begin
+ reg_mstatus_mprv <= 1'h0;
+ end else begin
+ if(wen) begin
+ if(T_5317) begin
+ reg_mstatus_mprv <= T_5976_mprv;
+ end else begin
+ if(T_5247) begin
+ reg_mstatus_mprv <= T_5790_mprv;
+ end else begin
+ if(T_5516) begin
+ reg_mstatus_mprv <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_5516) begin
+ reg_mstatus_mprv <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(reset) begin
+ reg_mstatus_xs <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(reset) begin
+ reg_mstatus_fs <= 1'h0;
+ end else begin
+ if(wen) begin
+ if(T_5317) begin
+ reg_mstatus_fs <= T_5976_fs;
+ end else begin
+ if(T_5247) begin
+ reg_mstatus_fs <= T_5790_fs;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(reset) begin
+ reg_mstatus_prv3 <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(reset) begin
+ reg_mstatus_ie3 <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(reset) begin
+ reg_mstatus_prv2 <= 1'h0;
+ end else begin
+ if(wen) begin
+ if(T_5247) begin
+ if(T_5852) begin
+ reg_mstatus_prv2 <= T_5790_prv2;
+ end else begin
+ if(insn_ret) begin
+ reg_mstatus_prv2 <= 1'h0;
+ end else begin
+ if(T_5516) begin
+ reg_mstatus_prv2 <= reg_mstatus_prv1;
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(insn_ret) begin
+ reg_mstatus_prv2 <= 1'h0;
+ end else begin
+ if(T_5516) begin
+ reg_mstatus_prv2 <= reg_mstatus_prv1;
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(insn_ret) begin
+ reg_mstatus_prv2 <= 1'h0;
+ end else begin
+ if(T_5516) begin
+ reg_mstatus_prv2 <= reg_mstatus_prv1;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(reset) begin
+ reg_mstatus_ie2 <= 1'h0;
+ end else begin
+ if(wen) begin
+ if(T_5247) begin
+ reg_mstatus_ie2 <= T_5790_ie2;
+ end else begin
+ if(insn_ret) begin
+ reg_mstatus_ie2 <= 1'h1;
+ end else begin
+ if(T_5516) begin
+ reg_mstatus_ie2 <= reg_mstatus_ie1;
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(insn_ret) begin
+ reg_mstatus_ie2 <= 1'h1;
+ end else begin
+ if(T_5516) begin
+ reg_mstatus_ie2 <= reg_mstatus_ie1;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(reset) begin
+ reg_mstatus_prv1 <= 2'h3;
+ end else begin
+ if(wen) begin
+ if(T_5317) begin
+ reg_mstatus_prv1 <= T_6003;
+ end else begin
+ if(T_5247) begin
+ if(T_5845) begin
+ reg_mstatus_prv1 <= T_5790_prv1;
+ end else begin
+ if(insn_ret) begin
+ reg_mstatus_prv1 <= reg_mstatus_prv2;
+ end else begin
+ if(T_5516) begin
+ reg_mstatus_prv1 <= reg_mstatus_prv;
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(insn_ret) begin
+ reg_mstatus_prv1 <= reg_mstatus_prv2;
+ end else begin
+ if(T_5516) begin
+ reg_mstatus_prv1 <= reg_mstatus_prv;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(insn_ret) begin
+ reg_mstatus_prv1 <= reg_mstatus_prv2;
+ end else begin
+ if(T_5516) begin
+ reg_mstatus_prv1 <= reg_mstatus_prv;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(reset) begin
+ reg_mstatus_ie1 <= 1'h0;
+ end else begin
+ if(wen) begin
+ if(T_5317) begin
+ reg_mstatus_ie1 <= T_5976_pie;
+ end else begin
+ if(T_5247) begin
+ reg_mstatus_ie1 <= T_5790_ie1;
+ end else begin
+ if(insn_ret) begin
+ reg_mstatus_ie1 <= reg_mstatus_ie2;
+ end else begin
+ if(T_5516) begin
+ reg_mstatus_ie1 <= reg_mstatus_ie;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(insn_ret) begin
+ reg_mstatus_ie1 <= reg_mstatus_ie2;
+ end else begin
+ if(T_5516) begin
+ reg_mstatus_ie1 <= reg_mstatus_ie;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(reset) begin
+ reg_mstatus_prv <= 2'h3;
+ end else begin
+ if(wen) begin
+ if(T_5247) begin
+ if(T_5838) begin
+ reg_mstatus_prv <= T_5790_prv;
+ end else begin
+ if(insn_redirect_trap) begin
+ reg_mstatus_prv <= 1'h1;
+ end else begin
+ if(insn_ret) begin
+ reg_mstatus_prv <= reg_mstatus_prv1;
+ end else begin
+ if(T_5516) begin
+ reg_mstatus_prv <= 2'h3;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(insn_redirect_trap) begin
+ reg_mstatus_prv <= 1'h1;
+ end else begin
+ if(insn_ret) begin
+ reg_mstatus_prv <= reg_mstatus_prv1;
+ end else begin
+ if(T_5516) begin
+ reg_mstatus_prv <= 2'h3;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(insn_redirect_trap) begin
+ reg_mstatus_prv <= 1'h1;
+ end else begin
+ if(insn_ret) begin
+ reg_mstatus_prv <= reg_mstatus_prv1;
+ end else begin
+ if(T_5516) begin
+ reg_mstatus_prv <= 2'h3;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(reset) begin
+ reg_mstatus_ie <= 1'h0;
+ end else begin
+ if(wen) begin
+ if(T_5317) begin
+ reg_mstatus_ie <= T_5976_ie;
+ end else begin
+ if(T_5247) begin
+ reg_mstatus_ie <= T_5790_ie;
+ end else begin
+ if(insn_ret) begin
+ reg_mstatus_ie <= reg_mstatus_ie1;
+ end else begin
+ if(T_5516) begin
+ reg_mstatus_ie <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(insn_ret) begin
+ reg_mstatus_ie <= reg_mstatus_ie1;
+ end else begin
+ if(T_5516) begin
+ reg_mstatus_ie <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ if(reset) begin
+ reg_mie_mtip <= T_4480_mtip;
+ end else begin
+ if(wen) begin
+ if(T_5261) begin
+ reg_mie_mtip <= T_5913_mtip;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ reg_mie_htip <= T_4480_htip;
+ end else begin
+ ;
+ end
+ if(reset) begin
+ reg_mie_stip <= T_4480_stip;
+ end else begin
+ if(wen) begin
+ if(T_5321) begin
+ reg_mie_stip <= T_6057_stip;
+ end else begin
+ if(T_5261) begin
+ reg_mie_stip <= T_5913_stip;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ reg_mie_utip <= T_4480_utip;
+ end else begin
+ ;
+ end
+ if(reset) begin
+ reg_mie_msip <= T_4480_msip;
+ end else begin
+ if(wen) begin
+ if(T_5261) begin
+ reg_mie_msip <= T_5913_msip;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ reg_mie_hsip <= T_4480_hsip;
+ end else begin
+ ;
+ end
+ if(reset) begin
+ reg_mie_ssip <= T_4480_ssip;
+ end else begin
+ if(wen) begin
+ if(T_5321) begin
+ reg_mie_ssip <= T_6057_ssip;
+ end else begin
+ if(T_5261) begin
+ reg_mie_ssip <= T_5913_ssip;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ reg_mie_usip <= T_4480_usip;
+ end else begin
+ ;
+ end
+ if(reset) begin
+ reg_mip_mtip <= T_4525_mtip;
+ end else begin
+ if(wen) begin
+ if(T_5271) begin
+ reg_mip_mtip <= 1'h0;
+ end else begin
+ if(T_5575) begin
+ reg_mip_mtip <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_5575) begin
+ reg_mip_mtip <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ reg_mip_htip <= T_4525_htip;
+ end else begin
+ ;
+ end
+ if(reset) begin
+ reg_mip_stip <= T_4525_stip;
+ end else begin
+ if(wen) begin
+ if(T_5259) begin
+ reg_mip_stip <= T_5877_stip;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ reg_mip_utip <= T_4525_utip;
+ end else begin
+ ;
+ end
+ if(reset) begin
+ reg_mip_msip <= T_4525_msip;
+ end else begin
+ if(wen) begin
+ if(T_5257) begin
+ reg_mip_msip <= T_5894;
+ end else begin
+ if(T_5259) begin
+ reg_mip_msip <= T_5877_msip;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ reg_mip_hsip <= T_4525_hsip;
+ end else begin
+ ;
+ end
+ if(reset) begin
+ reg_mip_ssip <= T_4525_ssip;
+ end else begin
+ if(wen) begin
+ if(T_5319) begin
+ reg_mip_ssip <= T_6022_ssip;
+ end else begin
+ if(T_5259) begin
+ reg_mip_ssip <= T_5877_ssip;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ reg_mip_usip <= T_4525_usip;
+ end else begin
+ ;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(wen) begin
+ if(T_5265) begin
+ reg_mepc <= T_5934;
+ end else begin
+ if(T_5516) begin
+ reg_mepc <= T_5523;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_5516) begin
+ reg_mepc <= T_5523;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(wen) begin
+ if(T_5269) begin
+ reg_mcause <= T_5936;
+ end else begin
+ if(T_5516) begin
+ if(csr_xcpt) begin
+ if(insn_call) begin
+ reg_mcause <= T_5528;
+ end else begin
+ if(insn_break) begin
+ reg_mcause <= 2'h3;
+ end else begin
+ reg_mcause <= 2'h2;
+ end
+ end
+ end else begin
+ reg_mcause <= io_cause;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_5516) begin
+ if(csr_xcpt) begin
+ if(insn_call) begin
+ reg_mcause <= T_5528;
+ end else begin
+ if(insn_break) begin
+ reg_mcause <= 2'h3;
+ end else begin
+ reg_mcause <= 2'h2;
+ end
+ end
+ end else begin
+ reg_mcause <= io_cause;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(wen) begin
+ if(T_5267) begin
+ reg_mbadaddr <= T_5937;
+ end else begin
+ if(T_5516) begin
+ if(T_5539) begin
+ reg_mbadaddr <= T_5551;
+ end else begin
+ reg_mbadaddr <= io_pc;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_5516) begin
+ if(T_5539) begin
+ reg_mbadaddr <= T_5551;
+ end else begin
+ reg_mbadaddr <= io_pc;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(wen) begin
+ if(T_5263) begin
+ reg_mscratch <= wdata;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(wen) begin
+ if(T_5333) begin
+ reg_sepc <= T_6080;
+ end else begin
+ if(insn_redirect_trap) begin
+ reg_sepc <= reg_mepc;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(insn_redirect_trap) begin
+ reg_sepc <= reg_mepc;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(insn_redirect_trap) begin
+ reg_scause <= reg_mcause;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(insn_redirect_trap) begin
+ reg_sbadaddr <= reg_mbadaddr;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(wen) begin
+ if(T_5323) begin
+ reg_sscratch <= wdata;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(wen) begin
+ if(T_5335) begin
+ reg_stvec <= T_6084;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(wen) begin
+ if(T_5271) begin
+ reg_mtimecmp <= wdata;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(wen) begin
+ if(T_5329) begin
+ reg_sptbr <= T_6076;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ reg_wfi <= 1'h0;
+ end else begin
+ if(some_interrupt_pending) begin
+ reg_wfi <= 1'h0;
+ end else begin
+ if(insn_wfi) begin
+ reg_wfi <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ reg_tohost <= 64'h0;
+ end else begin
+ if(wen) begin
+ if(T_5277) begin
+ if(T_5948) begin
+ reg_tohost <= wdata;
+ end else begin
+ if(T_5580) begin
+ reg_tohost <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_5580) begin
+ reg_tohost <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_5580) begin
+ reg_tohost <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ reg_fromhost <= 64'h0;
+ end else begin
+ if(wen) begin
+ if(T_5279) begin
+ if(T_5945) begin
+ reg_fromhost <= wdata;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ reg_stats <= 1'h0;
+ end else begin
+ if(wen) begin
+ if(T_5275) begin
+ reg_stats <= T_5949;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(wen) begin
+ if(T_5241) begin
+ reg_time <= wdata;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4584 <= 6'h0;
+ end else begin
+ if(wen) begin
+ if(T_5283) begin
+ T_4584 <= T_5938;
+ end else begin
+ if(T_4586) begin
+ T_4584 <= T_4590;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_4586) begin
+ T_4584 <= T_4590;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ T_4592 <= 58'h0;
+ end else begin
+ if(wen) begin
+ if(T_5283) begin
+ T_4592 <= T_5939;
+ end else begin
+ if(T_4594) begin
+ T_4592 <= T_4597;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_4594) begin
+ T_4592 <= T_4597;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ T_4601 <= 6'h0;
+ end else begin
+ if(T_4603) begin
+ T_4601 <= T_4607;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4609 <= 58'h0;
+ end else begin
+ if(T_4611) begin
+ T_4609 <= T_4614;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4617 <= 6'h0;
+ end else begin
+ if(T_4619) begin
+ T_4617 <= T_4623;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4625 <= 58'h0;
+ end else begin
+ if(T_4627) begin
+ T_4625 <= T_4630;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4633 <= 6'h0;
+ end else begin
+ if(T_4635) begin
+ T_4633 <= T_4639;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4641 <= 58'h0;
+ end else begin
+ if(T_4643) begin
+ T_4641 <= T_4646;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4649 <= 6'h0;
+ end else begin
+ if(T_4651) begin
+ T_4649 <= T_4655;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4657 <= 58'h0;
+ end else begin
+ if(T_4659) begin
+ T_4657 <= T_4662;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4665 <= 6'h0;
+ end else begin
+ if(T_4667) begin
+ T_4665 <= T_4671;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4673 <= 58'h0;
+ end else begin
+ if(T_4675) begin
+ T_4673 <= T_4678;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4681 <= 6'h0;
+ end else begin
+ if(T_4683) begin
+ T_4681 <= T_4687;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4689 <= 58'h0;
+ end else begin
+ if(T_4691) begin
+ T_4689 <= T_4694;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4697 <= 6'h0;
+ end else begin
+ if(T_4699) begin
+ T_4697 <= T_4703;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4705 <= 58'h0;
+ end else begin
+ if(T_4707) begin
+ T_4705 <= T_4710;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4713 <= 6'h0;
+ end else begin
+ if(T_4715) begin
+ T_4713 <= T_4719;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4721 <= 58'h0;
+ end else begin
+ if(T_4723) begin
+ T_4721 <= T_4726;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4729 <= 6'h0;
+ end else begin
+ if(T_4731) begin
+ T_4729 <= T_4735;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4737 <= 58'h0;
+ end else begin
+ if(T_4739) begin
+ T_4737 <= T_4742;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4745 <= 6'h0;
+ end else begin
+ if(T_4747) begin
+ T_4745 <= T_4751;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4753 <= 58'h0;
+ end else begin
+ if(T_4755) begin
+ T_4753 <= T_4758;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4761 <= 6'h0;
+ end else begin
+ if(T_4763) begin
+ T_4761 <= T_4767;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4769 <= 58'h0;
+ end else begin
+ if(T_4771) begin
+ T_4769 <= T_4774;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4777 <= 6'h0;
+ end else begin
+ if(T_4779) begin
+ T_4777 <= T_4783;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4785 <= 58'h0;
+ end else begin
+ if(T_4787) begin
+ T_4785 <= T_4790;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4793 <= 6'h0;
+ end else begin
+ if(T_4795) begin
+ T_4793 <= T_4799;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4801 <= 58'h0;
+ end else begin
+ if(T_4803) begin
+ T_4801 <= T_4806;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4809 <= 6'h0;
+ end else begin
+ if(T_4811) begin
+ T_4809 <= T_4815;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4817 <= 58'h0;
+ end else begin
+ if(T_4819) begin
+ T_4817 <= T_4822;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4825 <= 6'h0;
+ end else begin
+ if(T_4827) begin
+ T_4825 <= T_4831;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4833 <= 58'h0;
+ end else begin
+ if(T_4835) begin
+ T_4833 <= T_4838;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4841 <= 6'h0;
+ end else begin
+ if(T_4843) begin
+ T_4841 <= T_4847;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4849 <= 58'h0;
+ end else begin
+ if(T_4851) begin
+ T_4849 <= T_4854;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4857 <= 6'h0;
+ end else begin
+ if(T_4859) begin
+ T_4857 <= T_4863;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_4865 <= 58'h0;
+ end else begin
+ if(T_4867) begin
+ T_4865 <= T_4870;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(wen) begin
+ if(T_5227) begin
+ reg_fflags <= wdata;
+ end else begin
+ if(T_5223) begin
+ reg_fflags <= wdata;
+ end else begin
+ if(io_fcsr_flags_valid) begin
+ reg_fflags <= T_5755;
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(io_fcsr_flags_valid) begin
+ reg_fflags <= T_5755;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(wen) begin
+ if(T_5227) begin
+ reg_frm <= T_5930;
+ end else begin
+ if(T_5225) begin
+ reg_frm <= wdata;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(host_csr_req_fire) begin
+ host_csr_req_valid <= 1'h0;
+ end else begin
+ if(T_4969) begin
+ host_csr_req_valid <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_4973) begin
+ host_csr_rep_valid <= 1'h0;
+ end else begin
+ if(host_csr_req_fire) begin
+ host_csr_rep_valid <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_4969) begin
+ host_csr_bits_rw <= io_host_csr_req_bits_rw;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_4969) begin
+ host_csr_bits_addr <= io_host_csr_req_bits_addr;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(host_csr_req_fire) begin
+ host_csr_bits_data <= io_rw_rdata;
+ end else begin
+ if(T_4969) begin
+ host_csr_bits_data <= io_host_csr_req_bits_data;
+ end else begin
+ ;
+ end
+ end
+ end
+ `ifndef SYNTHESIS
+ if(GEN_1 & T_5574) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): these conditions must be mutually exclusive");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_5570 & T_5572) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ end
+endmodule
+module ALU(
+ input clk,
+ input reset,
+ input io_dw,
+ input [3:0] io_fn,
+ input [63:0] io_in2,
+ input [63:0] io_in1,
+ output [63:0] io_out,
+ output [63:0] io_adder_out,
+ output io_cmp_out
+);
+ wire T_11;
+ wire [63:0] T_12;
+ wire [63:0] in2_inv;
+ wire [63:0] in1_xor_in2;
+ wire [64:0] T_15;
+ wire [63:0] T_16;
+ wire T_17;
+ wire [64:0] T_18;
+ wire [63:0] T_19;
+ wire T_20;
+ wire T_21;
+ wire T_23;
+ wire T_25;
+ wire T_26;
+ wire T_27;
+ wire T_28;
+ wire T_29;
+ wire T_30;
+ wire T_31;
+ wire T_32;
+ wire T_33;
+ wire T_34;
+ wire T_35;
+ wire T_36;
+ wire T_37;
+ wire T_38;
+ wire T_39;
+ wire [32:0] T_41;
+ wire [31:0] T_42;
+ wire T_45;
+ wire T_46;
+ wire [31:0] T_47;
+ wire [31:0] T_48;
+ wire T_49;
+ wire T_52;
+ wire T_53;
+ wire T_54;
+ wire [4:0] T_55;
+ wire [5:0] shamt;
+ wire [31:0] T_57;
+ wire [63:0] shin_r;
+ wire T_59;
+ wire T_60;
+ wire T_61;
+ wire [63:0] T_64;
+ wire [63:0] T_65;
+ wire [31:0] T_66;
+ wire [63:0] T_67;
+ wire [31:0] T_68;
+ wire [63:0] T_69;
+ wire [63:0] T_70;
+ wire [63:0] T_71;
+ wire [63:0] T_72;
+ wire [47:0] T_73;
+ wire [63:0] T_74;
+ wire [63:0] T_75;
+ wire [47:0] T_76;
+ wire [63:0] T_77;
+ wire [47:0] T_78;
+ wire [63:0] T_79;
+ wire [63:0] T_80;
+ wire [63:0] T_81;
+ wire [63:0] T_82;
+ wire [55:0] T_83;
+ wire [63:0] T_84;
+ wire [63:0] T_85;
+ wire [55:0] T_86;
+ wire [63:0] T_87;
+ wire [55:0] T_88;
+ wire [63:0] T_89;
+ wire [63:0] T_90;
+ wire [63:0] T_91;
+ wire [63:0] T_92;
+ wire [59:0] T_93;
+ wire [63:0] T_94;
+ wire [63:0] T_95;
+ wire [59:0] T_96;
+ wire [63:0] T_97;
+ wire [59:0] T_98;
+ wire [63:0] T_99;
+ wire [63:0] T_100;
+ wire [63:0] T_101;
+ wire [63:0] T_102;
+ wire [61:0] T_103;
+ wire [63:0] T_104;
+ wire [63:0] T_105;
+ wire [61:0] T_106;
+ wire [63:0] T_107;
+ wire [61:0] T_108;
+ wire [63:0] T_109;
+ wire [63:0] T_110;
+ wire [63:0] T_111;
+ wire [63:0] T_112;
+ wire [62:0] T_113;
+ wire [63:0] T_114;
+ wire [63:0] T_115;
+ wire [62:0] T_116;
+ wire [63:0] T_117;
+ wire [62:0] T_118;
+ wire [63:0] T_119;
+ wire [63:0] T_120;
+ wire [63:0] T_121;
+ wire [63:0] T_122;
+ wire [63:0] shin;
+ wire T_124;
+ wire T_125;
+ wire T_126;
+ wire [64:0] T_127;
+ wire [64:0] T_128;
+ wire [64:0] T_129;
+ wire [63:0] shout_r;
+ wire [63:0] T_133;
+ wire [63:0] T_134;
+ wire [31:0] T_135;
+ wire [63:0] T_136;
+ wire [31:0] T_137;
+ wire [63:0] T_138;
+ wire [63:0] T_139;
+ wire [63:0] T_140;
+ wire [63:0] T_141;
+ wire [47:0] T_142;
+ wire [63:0] T_143;
+ wire [63:0] T_144;
+ wire [47:0] T_145;
+ wire [63:0] T_146;
+ wire [47:0] T_147;
+ wire [63:0] T_148;
+ wire [63:0] T_149;
+ wire [63:0] T_150;
+ wire [63:0] T_151;
+ wire [55:0] T_152;
+ wire [63:0] T_153;
+ wire [63:0] T_154;
+ wire [55:0] T_155;
+ wire [63:0] T_156;
+ wire [55:0] T_157;
+ wire [63:0] T_158;
+ wire [63:0] T_159;
+ wire [63:0] T_160;
+ wire [63:0] T_161;
+ wire [59:0] T_162;
+ wire [63:0] T_163;
+ wire [63:0] T_164;
+ wire [59:0] T_165;
+ wire [63:0] T_166;
+ wire [59:0] T_167;
+ wire [63:0] T_168;
+ wire [63:0] T_169;
+ wire [63:0] T_170;
+ wire [63:0] T_171;
+ wire [61:0] T_172;
+ wire [63:0] T_173;
+ wire [63:0] T_174;
+ wire [61:0] T_175;
+ wire [63:0] T_176;
+ wire [61:0] T_177;
+ wire [63:0] T_178;
+ wire [63:0] T_179;
+ wire [63:0] T_180;
+ wire [63:0] T_181;
+ wire [62:0] T_182;
+ wire [63:0] T_183;
+ wire [63:0] T_184;
+ wire [62:0] T_185;
+ wire [63:0] T_186;
+ wire [62:0] T_187;
+ wire [63:0] T_188;
+ wire [63:0] T_189;
+ wire [63:0] T_190;
+ wire [63:0] shout_l;
+ wire T_192;
+ wire T_193;
+ wire T_194;
+ wire [63:0] T_196;
+ wire T_197;
+ wire [63:0] T_199;
+ wire [63:0] shout;
+ wire T_201;
+ wire T_202;
+ wire T_203;
+ wire [63:0] T_205;
+ wire T_206;
+ wire T_207;
+ wire T_208;
+ wire [63:0] T_209;
+ wire [63:0] T_211;
+ wire [63:0] logic$;
+ wire T_213;
+ wire T_214;
+ wire T_215;
+ wire T_216;
+ wire T_217;
+ wire T_218;
+ wire [63:0] T_219;
+ wire [63:0] shift_logic;
+ wire T_221;
+ wire T_222;
+ wire T_223;
+ wire [63:0] out;
+ wire T_227;
+ wire T_228;
+ wire T_229;
+ wire [32:0] T_231;
+ wire [31:0] T_232;
+ wire [31:0] T_233;
+ wire [63:0] T_234;
+ assign io_out = T_228 ? T_234 : out;
+ assign io_adder_out = T_19;
+ assign io_cmp_out = T_36;
+ assign T_11 = io_fn[3];
+ assign T_12 = ~ io_in2;
+ assign in2_inv = T_11 ? T_12 : io_in2;
+ assign in1_xor_in2 = io_in1 ^ in2_inv;
+ assign T_15 = io_in1 + in2_inv;
+ assign T_16 = T_15[63:0];
+ assign T_17 = io_fn[3];
+ assign T_18 = T_16 + T_17;
+ assign T_19 = T_18[63:0];
+ assign T_20 = io_fn[0];
+ assign T_21 = io_fn[3];
+ assign T_23 = T_21 == 1'h0;
+ assign T_25 = in1_xor_in2 == 1'h0;
+ assign T_26 = io_in1[63];
+ assign T_27 = io_in2[63];
+ assign T_28 = T_26 == T_27;
+ assign T_29 = io_adder_out[63];
+ assign T_30 = io_fn[1];
+ assign T_31 = io_in2[63];
+ assign T_32 = io_in1[63];
+ assign T_33 = T_30 ? T_31 : T_32;
+ assign T_34 = T_28 ? T_29 : T_33;
+ assign T_35 = T_23 ? T_25 : T_34;
+ assign T_36 = T_20 ^ T_35;
+ assign T_37 = io_fn[3];
+ assign T_38 = io_in1[31];
+ assign T_39 = T_37 & T_38;
+ assign T_41 = 32'h0 - T_39;
+ assign T_42 = T_41[31:0];
+ assign T_45 = io_dw & 1'h1;
+ assign T_46 = 1'h1 == T_45;
+ assign T_47 = io_in1[63:32];
+ assign T_48 = T_46 ? T_47 : T_42;
+ assign T_49 = io_in2[5];
+ assign T_52 = io_dw & 1'h1;
+ assign T_53 = 1'h1 == T_52;
+ assign T_54 = T_49 & T_53;
+ assign T_55 = io_in2[4:0];
+ assign shamt = {T_54,T_55};
+ assign T_57 = io_in1[31:0];
+ assign shin_r = {T_48,T_57};
+ assign T_59 = io_fn == 3'h5;
+ assign T_60 = io_fn == 4'hb;
+ assign T_61 = T_59 | T_60;
+ assign T_64 = 32'hffffffff << 32;
+ assign T_65 = 64'hffffffffffffffff ^ T_64;
+ assign T_66 = shin_r[63:32];
+ assign T_67 = T_66 & T_65;
+ assign T_68 = shin_r[31:0];
+ assign T_69 = T_68 << 32;
+ assign T_70 = ~ T_65;
+ assign T_71 = T_69 & T_70;
+ assign T_72 = T_67 | T_71;
+ assign T_73 = T_65[47:0];
+ assign T_74 = T_73 << 16;
+ assign T_75 = T_65 ^ T_74;
+ assign T_76 = T_72[63:16];
+ assign T_77 = T_76 & T_75;
+ assign T_78 = T_72[47:0];
+ assign T_79 = T_78 << 16;
+ assign T_80 = ~ T_75;
+ assign T_81 = T_79 & T_80;
+ assign T_82 = T_77 | T_81;
+ assign T_83 = T_75[55:0];
+ assign T_84 = T_83 << 8;
+ assign T_85 = T_75 ^ T_84;
+ assign T_86 = T_82[63:8];
+ assign T_87 = T_86 & T_85;
+ assign T_88 = T_82[55:0];
+ assign T_89 = T_88 << 8;
+ assign T_90 = ~ T_85;
+ assign T_91 = T_89 & T_90;
+ assign T_92 = T_87 | T_91;
+ assign T_93 = T_85[59:0];
+ assign T_94 = T_93 << 4;
+ assign T_95 = T_85 ^ T_94;
+ assign T_96 = T_92[63:4];
+ assign T_97 = T_96 & T_95;
+ assign T_98 = T_92[59:0];
+ assign T_99 = T_98 << 4;
+ assign T_100 = ~ T_95;
+ assign T_101 = T_99 & T_100;
+ assign T_102 = T_97 | T_101;
+ assign T_103 = T_95[61:0];
+ assign T_104 = T_103 << 2;
+ assign T_105 = T_95 ^ T_104;
+ assign T_106 = T_102[63:2];
+ assign T_107 = T_106 & T_105;
+ assign T_108 = T_102[61:0];
+ assign T_109 = T_108 << 2;
+ assign T_110 = ~ T_105;
+ assign T_111 = T_109 & T_110;
+ assign T_112 = T_107 | T_111;
+ assign T_113 = T_105[62:0];
+ assign T_114 = T_113 << 1;
+ assign T_115 = T_105 ^ T_114;
+ assign T_116 = T_112[63:1];
+ assign T_117 = T_116 & T_115;
+ assign T_118 = T_112[62:0];
+ assign T_119 = T_118 << 1;
+ assign T_120 = ~ T_115;
+ assign T_121 = T_119 & T_120;
+ assign T_122 = T_117 | T_121;
+ assign shin = T_61 ? shin_r : T_122;
+ assign T_124 = io_fn[3];
+ assign T_125 = shin[63];
+ assign T_126 = T_124 & T_125;
+ assign T_127 = {T_126,shin};
+ assign T_128 = $signed(T_127);
+ assign T_129 = $signed(T_128) >>> shamt;
+ assign shout_r = T_129[63:0];
+ assign T_133 = 32'hffffffff << 32;
+ assign T_134 = 64'hffffffffffffffff ^ T_133;
+ assign T_135 = shout_r[63:32];
+ assign T_136 = T_135 & T_134;
+ assign T_137 = shout_r[31:0];
+ assign T_138 = T_137 << 32;
+ assign T_139 = ~ T_134;
+ assign T_140 = T_138 & T_139;
+ assign T_141 = T_136 | T_140;
+ assign T_142 = T_134[47:0];
+ assign T_143 = T_142 << 16;
+ assign T_144 = T_134 ^ T_143;
+ assign T_145 = T_141[63:16];
+ assign T_146 = T_145 & T_144;
+ assign T_147 = T_141[47:0];
+ assign T_148 = T_147 << 16;
+ assign T_149 = ~ T_144;
+ assign T_150 = T_148 & T_149;
+ assign T_151 = T_146 | T_150;
+ assign T_152 = T_144[55:0];
+ assign T_153 = T_152 << 8;
+ assign T_154 = T_144 ^ T_153;
+ assign T_155 = T_151[63:8];
+ assign T_156 = T_155 & T_154;
+ assign T_157 = T_151[55:0];
+ assign T_158 = T_157 << 8;
+ assign T_159 = ~ T_154;
+ assign T_160 = T_158 & T_159;
+ assign T_161 = T_156 | T_160;
+ assign T_162 = T_154[59:0];
+ assign T_163 = T_162 << 4;
+ assign T_164 = T_154 ^ T_163;
+ assign T_165 = T_161[63:4];
+ assign T_166 = T_165 & T_164;
+ assign T_167 = T_161[59:0];
+ assign T_168 = T_167 << 4;
+ assign T_169 = ~ T_164;
+ assign T_170 = T_168 & T_169;
+ assign T_171 = T_166 | T_170;
+ assign T_172 = T_164[61:0];
+ assign T_173 = T_172 << 2;
+ assign T_174 = T_164 ^ T_173;
+ assign T_175 = T_171[63:2];
+ assign T_176 = T_175 & T_174;
+ assign T_177 = T_171[61:0];
+ assign T_178 = T_177 << 2;
+ assign T_179 = ~ T_174;
+ assign T_180 = T_178 & T_179;
+ assign T_181 = T_176 | T_180;
+ assign T_182 = T_174[62:0];
+ assign T_183 = T_182 << 1;
+ assign T_184 = T_174 ^ T_183;
+ assign T_185 = T_181[63:1];
+ assign T_186 = T_185 & T_184;
+ assign T_187 = T_181[62:0];
+ assign T_188 = T_187 << 1;
+ assign T_189 = ~ T_184;
+ assign T_190 = T_188 & T_189;
+ assign shout_l = T_186 | T_190;
+ assign T_192 = io_fn == 3'h5;
+ assign T_193 = io_fn == 4'hb;
+ assign T_194 = T_192 | T_193;
+ assign T_196 = T_194 ? shout_r : 1'h0;
+ assign T_197 = io_fn == 1'h1;
+ assign T_199 = T_197 ? shout_l : 1'h0;
+ assign shout = T_196 | T_199;
+ assign T_201 = io_fn == 3'h4;
+ assign T_202 = io_fn == 3'h6;
+ assign T_203 = T_201 | T_202;
+ assign T_205 = T_203 ? in1_xor_in2 : 1'h0;
+ assign T_206 = io_fn == 3'h6;
+ assign T_207 = io_fn == 3'h7;
+ assign T_208 = T_206 | T_207;
+ assign T_209 = io_in1 & io_in2;
+ assign T_211 = T_208 ? T_209 : 1'h0;
+ assign logic$ = T_205 | T_211;
+ assign T_213 = io_fn == 2'h2;
+ assign T_214 = io_fn == 2'h3;
+ assign T_215 = T_213 | T_214;
+ assign T_216 = io_fn >= 4'hc;
+ assign T_217 = T_215 | T_216;
+ assign T_218 = T_217 & io_cmp_out;
+ assign T_219 = T_218 | logic$;
+ assign shift_logic = T_219 | shout;
+ assign T_221 = io_fn == 1'h0;
+ assign T_222 = io_fn == 4'ha;
+ assign T_223 = T_221 | T_222;
+ assign out = T_223 ? io_adder_out : shift_logic;
+ assign T_227 = io_dw & 1'h1;
+ assign T_228 = 1'h0 == T_227;
+ assign T_229 = out[31];
+ assign T_231 = 32'h0 - T_229;
+ assign T_232 = T_231[31:0];
+ assign T_233 = out[31:0];
+ assign T_234 = {T_232,T_233};
+endmodule
+module MulDiv(
+ input clk,
+ input reset,
+ output io_req_ready,
+ input io_req_valid,
+ input [3:0] io_req_bits_fn,
+ input io_req_bits_dw,
+ input [63:0] io_req_bits_in1,
+ input [63:0] io_req_bits_in2,
+ input [4:0] io_req_bits_tag,
+ input io_kill,
+ input io_resp_ready,
+ output io_resp_valid,
+ output [63:0] io_resp_bits_data,
+ output [4:0] io_resp_bits_tag
+);
+ reg [2:0] state;
+ reg [3:0] req_fn;
+ reg req_dw;
+ reg [63:0] req_in1;
+ reg [63:0] req_in2;
+ reg [4:0] req_tag;
+ reg [6:0] count;
+ reg neg_out;
+ reg isMul;
+ reg isHi;
+ reg [64:0] divisor;
+ reg [129:0] remainder;
+ wire [3:0] T_81;
+ wire T_83;
+ wire [3:0] T_85;
+ wire T_87;
+ wire T_89;
+ wire T_90;
+ wire [3:0] T_92;
+ wire T_94;
+ wire [3:0] T_96;
+ wire T_98;
+ wire T_100;
+ wire T_101;
+ wire T_102;
+ wire [3:0] T_104;
+ wire T_106;
+ wire [3:0] T_108;
+ wire T_110;
+ wire T_112;
+ wire T_113;
+ wire T_114;
+ wire T_116;
+ wire T_117;
+ wire cmdMul;
+ wire cmdHi;
+ wire lhsSigned;
+ wire rhsSigned;
+ wire T_124;
+ wire T_125;
+ wire T_126;
+ wire T_127;
+ wire T_128;
+ wire lhs_sign;
+ wire T_132;
+ wire T_133;
+ wire [31:0] T_134;
+ wire [32:0] T_136;
+ wire [31:0] T_137;
+ wire [31:0] T_138;
+ wire [31:0] T_139;
+ wire [63:0] lhs_in;
+ wire T_143;
+ wire T_144;
+ wire T_145;
+ wire T_146;
+ wire T_147;
+ wire rhs_sign;
+ wire T_151;
+ wire T_152;
+ wire [31:0] T_153;
+ wire [32:0] T_155;
+ wire [31:0] T_156;
+ wire [31:0] T_157;
+ wire [31:0] T_158;
+ wire [63:0] rhs_in;
+ wire [64:0] T_160;
+ wire [64:0] T_161;
+ wire [65:0] T_162;
+ wire [64:0] subtractor;
+ wire less;
+ wire [63:0] T_165;
+ wire [64:0] T_167;
+ wire [63:0] negated_remainder;
+ wire T_169;
+ wire T_170;
+ wire T_171;
+ wire T_172;
+ wire T_173;
+ wire T_174;
+ wire T_175;
+ wire [63:0] T_176;
+ wire [2:0] T_177;
+ wire T_178;
+ wire T_179;
+ wire [64:0] T_180;
+ wire [63:0] T_181;
+ wire [128:0] T_182;
+ wire [63:0] T_183;
+ wire [64:0] T_184;
+ wire [64:0] T_185;
+ wire [64:0] T_186;
+ wire [7:0] T_187;
+ wire [72:0] T_188;
+ wire [73:0] T_189;
+ wire [72:0] T_190;
+ wire [72:0] T_191;
+ wire [55:0] T_192;
+ wire [72:0] T_193;
+ wire [128:0] T_194;
+ wire [10:0] T_197;
+ wire [5:0] T_198;
+ wire [64:0] GEN_0;
+ wire [64:0] T_199;
+ wire [63:0] T_200;
+ wire T_203;
+ wire T_204;
+ wire T_206;
+ wire T_207;
+ wire T_209;
+ wire T_210;
+ wire [63:0] T_211;
+ wire [63:0] T_212;
+ wire T_214;
+ wire T_215;
+ wire [10:0] T_218;
+ wire [11:0] T_219;
+ wire [10:0] T_220;
+ wire [5:0] T_221;
+ wire [128:0] T_222;
+ wire [64:0] T_223;
+ wire [128:0] T_224;
+ wire [63:0] T_225;
+ wire [128:0] T_226;
+ wire [64:0] T_227;
+ wire [63:0] T_229;
+ wire [64:0] T_230;
+ wire [129:0] T_231;
+ wire [7:0] T_233;
+ wire [6:0] T_234;
+ wire T_236;
+ wire T_237;
+ wire [2:0] T_238;
+ wire T_239;
+ wire T_241;
+ wire T_242;
+ wire T_244;
+ wire [2:0] T_245;
+ wire [2:0] T_246;
+ wire [7:0] T_248;
+ wire [6:0] T_249;
+ wire [63:0] T_250;
+ wire [63:0] T_251;
+ wire [63:0] T_252;
+ wire [63:0] T_253;
+ wire T_255;
+ wire [64:0] T_256;
+ wire [128:0] T_257;
+ wire [63:0] T_258;
+ wire T_259;
+ wire T_261;
+ wire T_263;
+ wire T_265;
+ wire T_267;
+ wire T_269;
+ wire T_271;
+ wire T_273;
+ wire T_275;
+ wire T_277;
+ wire T_279;
+ wire T_281;
+ wire T_283;
+ wire T_285;
+ wire T_287;
+ wire T_289;
+ wire T_291;
+ wire T_293;
+ wire T_295;
+ wire T_297;
+ wire T_299;
+ wire T_301;
+ wire T_303;
+ wire T_305;
+ wire T_307;
+ wire T_309;
+ wire T_311;
+ wire T_313;
+ wire T_315;
+ wire T_317;
+ wire T_319;
+ wire T_321;
+ wire T_323;
+ wire T_325;
+ wire T_327;
+ wire T_329;
+ wire T_331;
+ wire T_333;
+ wire T_335;
+ wire T_337;
+ wire T_339;
+ wire T_341;
+ wire T_343;
+ wire T_345;
+ wire T_347;
+ wire T_349;
+ wire T_351;
+ wire T_353;
+ wire T_355;
+ wire T_357;
+ wire T_359;
+ wire T_361;
+ wire T_363;
+ wire T_365;
+ wire T_367;
+ wire T_369;
+ wire T_371;
+ wire T_373;
+ wire T_375;
+ wire T_377;
+ wire T_379;
+ wire T_381;
+ wire T_383;
+ wire T_384;
+ wire [1:0] T_385;
+ wire [1:0] T_386;
+ wire [2:0] T_387;
+ wire [2:0] T_388;
+ wire [2:0] T_389;
+ wire [2:0] T_390;
+ wire [3:0] T_391;
+ wire [3:0] T_392;
+ wire [3:0] T_393;
+ wire [3:0] T_394;
+ wire [3:0] T_395;
+ wire [3:0] T_396;
+ wire [3:0] T_397;
+ wire [3:0] T_398;
+ wire [4:0] T_399;
+ wire [4:0] T_400;
+ wire [4:0] T_401;
+ wire [4:0] T_402;
+ wire [4:0] T_403;
+ wire [4:0] T_404;
+ wire [4:0] T_405;
+ wire [4:0] T_406;
+ wire [4:0] T_407;
+ wire [4:0] T_408;
+ wire [4:0] T_409;
+ wire [4:0] T_410;
+ wire [4:0] T_411;
+ wire [4:0] T_412;
+ wire [4:0] T_413;
+ wire [4:0] T_414;
+ wire [5:0] T_415;
+ wire [5:0] T_416;
+ wire [5:0] T_417;
+ wire [5:0] T_418;
+ wire [5:0] T_419;
+ wire [5:0] T_420;
+ wire [5:0] T_421;
+ wire [5:0] T_422;
+ wire [5:0] T_423;
+ wire [5:0] T_424;
+ wire [5:0] T_425;
+ wire [5:0] T_426;
+ wire [5:0] T_427;
+ wire [5:0] T_428;
+ wire [5:0] T_429;
+ wire [5:0] T_430;
+ wire [5:0] T_431;
+ wire [5:0] T_432;
+ wire [5:0] T_433;
+ wire [5:0] T_434;
+ wire [5:0] T_435;
+ wire [5:0] T_436;
+ wire [5:0] T_437;
+ wire [5:0] T_438;
+ wire [5:0] T_439;
+ wire [5:0] T_440;
+ wire [5:0] T_441;
+ wire [5:0] T_442;
+ wire [5:0] T_443;
+ wire [5:0] T_444;
+ wire [5:0] T_445;
+ wire [5:0] T_446;
+ wire [63:0] T_447;
+ wire T_448;
+ wire T_450;
+ wire T_452;
+ wire T_454;
+ wire T_456;
+ wire T_458;
+ wire T_460;
+ wire T_462;
+ wire T_464;
+ wire T_466;
+ wire T_468;
+ wire T_470;
+ wire T_472;
+ wire T_474;
+ wire T_476;
+ wire T_478;
+ wire T_480;
+ wire T_482;
+ wire T_484;
+ wire T_486;
+ wire T_488;
+ wire T_490;
+ wire T_492;
+ wire T_494;
+ wire T_496;
+ wire T_498;
+ wire T_500;
+ wire T_502;
+ wire T_504;
+ wire T_506;
+ wire T_508;
+ wire T_510;
+ wire T_512;
+ wire T_514;
+ wire T_516;
+ wire T_518;
+ wire T_520;
+ wire T_522;
+ wire T_524;
+ wire T_526;
+ wire T_528;
+ wire T_530;
+ wire T_532;
+ wire T_534;
+ wire T_536;
+ wire T_538;
+ wire T_540;
+ wire T_542;
+ wire T_544;
+ wire T_546;
+ wire T_548;
+ wire T_550;
+ wire T_552;
+ wire T_554;
+ wire T_556;
+ wire T_558;
+ wire T_560;
+ wire T_562;
+ wire T_564;
+ wire T_566;
+ wire T_568;
+ wire T_570;
+ wire T_572;
+ wire T_573;
+ wire [1:0] T_574;
+ wire [1:0] T_575;
+ wire [2:0] T_576;
+ wire [2:0] T_577;
+ wire [2:0] T_578;
+ wire [2:0] T_579;
+ wire [3:0] T_580;
+ wire [3:0] T_581;
+ wire [3:0] T_582;
+ wire [3:0] T_583;
+ wire [3:0] T_584;
+ wire [3:0] T_585;
+ wire [3:0] T_586;
+ wire [3:0] T_587;
+ wire [4:0] T_588;
+ wire [4:0] T_589;
+ wire [4:0] T_590;
+ wire [4:0] T_591;
+ wire [4:0] T_592;
+ wire [4:0] T_593;
+ wire [4:0] T_594;
+ wire [4:0] T_595;
+ wire [4:0] T_596;
+ wire [4:0] T_597;
+ wire [4:0] T_598;
+ wire [4:0] T_599;
+ wire [4:0] T_600;
+ wire [4:0] T_601;
+ wire [4:0] T_602;
+ wire [4:0] T_603;
+ wire [5:0] T_604;
+ wire [5:0] T_605;
+ wire [5:0] T_606;
+ wire [5:0] T_607;
+ wire [5:0] T_608;
+ wire [5:0] T_609;
+ wire [5:0] T_610;
+ wire [5:0] T_611;
+ wire [5:0] T_612;
+ wire [5:0] T_613;
+ wire [5:0] T_614;
+ wire [5:0] T_615;
+ wire [5:0] T_616;
+ wire [5:0] T_617;
+ wire [5:0] T_618;
+ wire [5:0] T_619;
+ wire [5:0] T_620;
+ wire [5:0] T_621;
+ wire [5:0] T_622;
+ wire [5:0] T_623;
+ wire [5:0] T_624;
+ wire [5:0] T_625;
+ wire [5:0] T_626;
+ wire [5:0] T_627;
+ wire [5:0] T_628;
+ wire [5:0] T_629;
+ wire [5:0] T_630;
+ wire [5:0] T_631;
+ wire [5:0] T_632;
+ wire [5:0] T_633;
+ wire [5:0] T_634;
+ wire [5:0] T_635;
+ wire [6:0] T_637;
+ wire [5:0] T_638;
+ wire [6:0] T_639;
+ wire [5:0] T_640;
+ wire T_641;
+ wire T_643;
+ wire T_644;
+ wire T_646;
+ wire T_647;
+ wire T_648;
+ wire T_650;
+ wire [5:0] T_652;
+ wire [5:0] T_653;
+ wire [63:0] T_654;
+ wire [126:0] T_655;
+ wire T_657;
+ wire T_659;
+ wire T_660;
+ wire T_662;
+ wire T_663;
+ wire T_665;
+ wire T_666;
+ wire T_667;
+ wire T_669;
+ wire T_670;
+ wire T_671;
+ wire [1:0] T_672;
+ wire T_675;
+ wire T_676;
+ wire T_677;
+ wire T_678;
+ wire [64:0] T_679;
+ wire T_682;
+ wire T_683;
+ wire T_684;
+ wire [32:0] T_686;
+ wire [31:0] T_687;
+ wire [31:0] T_688;
+ wire [63:0] T_689;
+ wire [63:0] T_690;
+ wire [63:0] T_691;
+ wire T_692;
+ wire T_693;
+ assign io_req_ready = T_693;
+ assign io_resp_valid = T_692;
+ assign io_resp_bits_data = T_691;
+ assign io_resp_bits_tag = req_tag;
+ assign T_81 = io_req_bits_fn & 4'h4;
+ assign T_83 = T_81 == 4'h0;
+ assign T_85 = io_req_bits_fn & 4'h8;
+ assign T_87 = T_85 == 4'h8;
+ assign T_89 = 1'h0 | T_83;
+ assign T_90 = T_89 | T_87;
+ assign T_92 = io_req_bits_fn & 4'h5;
+ assign T_94 = T_92 == 4'h1;
+ assign T_96 = io_req_bits_fn & 4'h2;
+ assign T_98 = T_96 == 4'h2;
+ assign T_100 = 1'h0 | T_94;
+ assign T_101 = T_100 | T_98;
+ assign T_102 = T_101 | T_87;
+ assign T_104 = io_req_bits_fn & 4'h9;
+ assign T_106 = T_104 == 4'h0;
+ assign T_108 = io_req_bits_fn & 4'h3;
+ assign T_110 = T_108 == 4'h0;
+ assign T_112 = 1'h0 | T_106;
+ assign T_113 = T_112 | T_83;
+ assign T_114 = T_113 | T_110;
+ assign T_116 = 1'h0 | T_106;
+ assign T_117 = T_116 | T_83;
+ assign cmdMul = T_90;
+ assign cmdHi = T_102;
+ assign lhsSigned = T_114;
+ assign rhsSigned = T_117;
+ assign T_124 = io_req_bits_dw & 1'h1;
+ assign T_125 = 1'h1 == T_124;
+ assign T_126 = io_req_bits_in1[63];
+ assign T_127 = io_req_bits_in1[31];
+ assign T_128 = T_125 ? T_126 : T_127;
+ assign lhs_sign = lhsSigned & T_128;
+ assign T_132 = io_req_bits_dw & 1'h1;
+ assign T_133 = 1'h1 == T_132;
+ assign T_134 = io_req_bits_in1[63:32];
+ assign T_136 = 32'h0 - lhs_sign;
+ assign T_137 = T_136[31:0];
+ assign T_138 = T_133 ? T_134 : T_137;
+ assign T_139 = io_req_bits_in1[31:0];
+ assign lhs_in = {T_138,T_139};
+ assign T_143 = io_req_bits_dw & 1'h1;
+ assign T_144 = 1'h1 == T_143;
+ assign T_145 = io_req_bits_in2[63];
+ assign T_146 = io_req_bits_in2[31];
+ assign T_147 = T_144 ? T_145 : T_146;
+ assign rhs_sign = rhsSigned & T_147;
+ assign T_151 = io_req_bits_dw & 1'h1;
+ assign T_152 = 1'h1 == T_151;
+ assign T_153 = io_req_bits_in2[63:32];
+ assign T_155 = 32'h0 - rhs_sign;
+ assign T_156 = T_155[31:0];
+ assign T_157 = T_152 ? T_153 : T_156;
+ assign T_158 = io_req_bits_in2[31:0];
+ assign rhs_in = {T_157,T_158};
+ assign T_160 = remainder[128:64];
+ assign T_161 = divisor;
+ assign T_162 = T_160 - T_161;
+ assign subtractor = T_162[64:0];
+ assign less = subtractor[64];
+ assign T_165 = remainder[63:0];
+ assign T_167 = 1'h0 - T_165;
+ assign negated_remainder = T_167[63:0];
+ assign T_169 = state == 1'h1;
+ assign T_170 = remainder[63];
+ assign T_171 = T_170 | isMul;
+ assign T_172 = divisor[63];
+ assign T_173 = T_172 | isMul;
+ assign T_174 = state == 3'h4;
+ assign T_175 = state == 2'h3;
+ assign T_176 = remainder[128:65];
+ assign T_177 = neg_out ? 3'h4 : 3'h5;
+ assign T_178 = state == 2'h2;
+ assign T_179 = T_178 & isMul;
+ assign T_180 = remainder[129:65];
+ assign T_181 = remainder[63:0];
+ assign T_182 = {T_180,T_181};
+ assign T_183 = T_182[63:0];
+ assign T_184 = T_182[128:64];
+ assign T_185 = $signed(T_184);
+ assign T_186 = $signed(divisor);
+ assign T_187 = T_183[7:0];
+ assign T_188 = $signed(T_186) * $signed({1'b0,T_187});
+ assign T_189 = $signed(T_188) + $signed(T_185);
+ assign T_190 = T_189[72:0];
+ assign T_191 = $signed(T_190);
+ assign T_192 = T_183[63:8];
+ assign T_193 = $unsigned(T_191);
+ assign T_194 = {T_193,T_192};
+ assign T_197 = count * 4'h8;
+ assign T_198 = T_197[5:0];
+ assign GEN_0 = $signed(65'h10000000000000000);
+ assign T_199 = $signed(GEN_0) >>> T_198;
+ assign T_200 = T_199[63:0];
+ assign T_203 = count != 3'h7;
+ assign T_204 = 1'h1 & T_203;
+ assign T_206 = count != 1'h0;
+ assign T_207 = T_204 & T_206;
+ assign T_209 = isHi == 1'h0;
+ assign T_210 = T_207 & T_209;
+ assign T_211 = ~ T_200;
+ assign T_212 = T_183 & T_211;
+ assign T_214 = T_212 == 1'h0;
+ assign T_215 = T_210 & T_214;
+ assign T_218 = count * 4'h8;
+ assign T_219 = 7'h40 - T_218;
+ assign T_220 = T_219[10:0];
+ assign T_221 = T_220[5:0];
+ assign T_222 = T_182 >> T_221;
+ assign T_223 = T_194[128:64];
+ assign T_224 = T_215 ? T_222 : T_194;
+ assign T_225 = T_224[63:0];
+ assign T_226 = {T_223,T_225};
+ assign T_227 = T_226[128:64];
+ assign T_229 = T_226[63:0];
+ assign T_230 = {1'h0,T_229};
+ assign T_231 = {T_227,T_230};
+ assign T_233 = count + 1'h1;
+ assign T_234 = T_233[6:0];
+ assign T_236 = count == 3'h7;
+ assign T_237 = T_215 | T_236;
+ assign T_238 = isHi ? 2'h3 : 3'h5;
+ assign T_239 = state == 2'h2;
+ assign T_241 = isMul == 1'h0;
+ assign T_242 = T_239 & T_241;
+ assign T_244 = count == 7'h40;
+ assign T_245 = neg_out ? 3'h4 : 3'h5;
+ assign T_246 = isHi ? 2'h3 : T_245;
+ assign T_248 = count + 1'h1;
+ assign T_249 = T_248[6:0];
+ assign T_250 = remainder[127:64];
+ assign T_251 = subtractor[63:0];
+ assign T_252 = less ? T_250 : T_251;
+ assign T_253 = remainder[63:0];
+ assign T_255 = less == 1'h0;
+ assign T_256 = {T_253,T_255};
+ assign T_257 = {T_252,T_256};
+ assign T_258 = divisor[63:0];
+ assign T_259 = T_258[63];
+ assign T_261 = T_258[62];
+ assign T_263 = T_258[61];
+ assign T_265 = T_258[60];
+ assign T_267 = T_258[59];
+ assign T_269 = T_258[58];
+ assign T_271 = T_258[57];
+ assign T_273 = T_258[56];
+ assign T_275 = T_258[55];
+ assign T_277 = T_258[54];
+ assign T_279 = T_258[53];
+ assign T_281 = T_258[52];
+ assign T_283 = T_258[51];
+ assign T_285 = T_258[50];
+ assign T_287 = T_258[49];
+ assign T_289 = T_258[48];
+ assign T_291 = T_258[47];
+ assign T_293 = T_258[46];
+ assign T_295 = T_258[45];
+ assign T_297 = T_258[44];
+ assign T_299 = T_258[43];
+ assign T_301 = T_258[42];
+ assign T_303 = T_258[41];
+ assign T_305 = T_258[40];
+ assign T_307 = T_258[39];
+ assign T_309 = T_258[38];
+ assign T_311 = T_258[37];
+ assign T_313 = T_258[36];
+ assign T_315 = T_258[35];
+ assign T_317 = T_258[34];
+ assign T_319 = T_258[33];
+ assign T_321 = T_258[32];
+ assign T_323 = T_258[31];
+ assign T_325 = T_258[30];
+ assign T_327 = T_258[29];
+ assign T_329 = T_258[28];
+ assign T_331 = T_258[27];
+ assign T_333 = T_258[26];
+ assign T_335 = T_258[25];
+ assign T_337 = T_258[24];
+ assign T_339 = T_258[23];
+ assign T_341 = T_258[22];
+ assign T_343 = T_258[21];
+ assign T_345 = T_258[20];
+ assign T_347 = T_258[19];
+ assign T_349 = T_258[18];
+ assign T_351 = T_258[17];
+ assign T_353 = T_258[16];
+ assign T_355 = T_258[15];
+ assign T_357 = T_258[14];
+ assign T_359 = T_258[13];
+ assign T_361 = T_258[12];
+ assign T_363 = T_258[11];
+ assign T_365 = T_258[10];
+ assign T_367 = T_258[9];
+ assign T_369 = T_258[8];
+ assign T_371 = T_258[7];
+ assign T_373 = T_258[6];
+ assign T_375 = T_258[5];
+ assign T_377 = T_258[4];
+ assign T_379 = T_258[3];
+ assign T_381 = T_258[2];
+ assign T_383 = T_258[1];
+ assign T_384 = T_383 << 0;
+ assign T_385 = T_381 ? 2'h2 : T_384;
+ assign T_386 = T_379 ? 2'h3 : T_385;
+ assign T_387 = T_377 ? 3'h4 : T_386;
+ assign T_388 = T_375 ? 3'h5 : T_387;
+ assign T_389 = T_373 ? 3'h6 : T_388;
+ assign T_390 = T_371 ? 3'h7 : T_389;
+ assign T_391 = T_369 ? 4'h8 : T_390;
+ assign T_392 = T_367 ? 4'h9 : T_391;
+ assign T_393 = T_365 ? 4'ha : T_392;
+ assign T_394 = T_363 ? 4'hb : T_393;
+ assign T_395 = T_361 ? 4'hc : T_394;
+ assign T_396 = T_359 ? 4'hd : T_395;
+ assign T_397 = T_357 ? 4'he : T_396;
+ assign T_398 = T_355 ? 4'hf : T_397;
+ assign T_399 = T_353 ? 5'h10 : T_398;
+ assign T_400 = T_351 ? 5'h11 : T_399;
+ assign T_401 = T_349 ? 5'h12 : T_400;
+ assign T_402 = T_347 ? 5'h13 : T_401;
+ assign T_403 = T_345 ? 5'h14 : T_402;
+ assign T_404 = T_343 ? 5'h15 : T_403;
+ assign T_405 = T_341 ? 5'h16 : T_404;
+ assign T_406 = T_339 ? 5'h17 : T_405;
+ assign T_407 = T_337 ? 5'h18 : T_406;
+ assign T_408 = T_335 ? 5'h19 : T_407;
+ assign T_409 = T_333 ? 5'h1a : T_408;
+ assign T_410 = T_331 ? 5'h1b : T_409;
+ assign T_411 = T_329 ? 5'h1c : T_410;
+ assign T_412 = T_327 ? 5'h1d : T_411;
+ assign T_413 = T_325 ? 5'h1e : T_412;
+ assign T_414 = T_323 ? 5'h1f : T_413;
+ assign T_415 = T_321 ? 6'h20 : T_414;
+ assign T_416 = T_319 ? 6'h21 : T_415;
+ assign T_417 = T_317 ? 6'h22 : T_416;
+ assign T_418 = T_315 ? 6'h23 : T_417;
+ assign T_419 = T_313 ? 6'h24 : T_418;
+ assign T_420 = T_311 ? 6'h25 : T_419;
+ assign T_421 = T_309 ? 6'h26 : T_420;
+ assign T_422 = T_307 ? 6'h27 : T_421;
+ assign T_423 = T_305 ? 6'h28 : T_422;
+ assign T_424 = T_303 ? 6'h29 : T_423;
+ assign T_425 = T_301 ? 6'h2a : T_424;
+ assign T_426 = T_299 ? 6'h2b : T_425;
+ assign T_427 = T_297 ? 6'h2c : T_426;
+ assign T_428 = T_295 ? 6'h2d : T_427;
+ assign T_429 = T_293 ? 6'h2e : T_428;
+ assign T_430 = T_291 ? 6'h2f : T_429;
+ assign T_431 = T_289 ? 6'h30 : T_430;
+ assign T_432 = T_287 ? 6'h31 : T_431;
+ assign T_433 = T_285 ? 6'h32 : T_432;
+ assign T_434 = T_283 ? 6'h33 : T_433;
+ assign T_435 = T_281 ? 6'h34 : T_434;
+ assign T_436 = T_279 ? 6'h35 : T_435;
+ assign T_437 = T_277 ? 6'h36 : T_436;
+ assign T_438 = T_275 ? 6'h37 : T_437;
+ assign T_439 = T_273 ? 6'h38 : T_438;
+ assign T_440 = T_271 ? 6'h39 : T_439;
+ assign T_441 = T_269 ? 6'h3a : T_440;
+ assign T_442 = T_267 ? 6'h3b : T_441;
+ assign T_443 = T_265 ? 6'h3c : T_442;
+ assign T_444 = T_263 ? 6'h3d : T_443;
+ assign T_445 = T_261 ? 6'h3e : T_444;
+ assign T_446 = T_259 ? 6'h3f : T_445;
+ assign T_447 = remainder[63:0];
+ assign T_448 = T_447[63];
+ assign T_450 = T_447[62];
+ assign T_452 = T_447[61];
+ assign T_454 = T_447[60];
+ assign T_456 = T_447[59];
+ assign T_458 = T_447[58];
+ assign T_460 = T_447[57];
+ assign T_462 = T_447[56];
+ assign T_464 = T_447[55];
+ assign T_466 = T_447[54];
+ assign T_468 = T_447[53];
+ assign T_470 = T_447[52];
+ assign T_472 = T_447[51];
+ assign T_474 = T_447[50];
+ assign T_476 = T_447[49];
+ assign T_478 = T_447[48];
+ assign T_480 = T_447[47];
+ assign T_482 = T_447[46];
+ assign T_484 = T_447[45];
+ assign T_486 = T_447[44];
+ assign T_488 = T_447[43];
+ assign T_490 = T_447[42];
+ assign T_492 = T_447[41];
+ assign T_494 = T_447[40];
+ assign T_496 = T_447[39];
+ assign T_498 = T_447[38];
+ assign T_500 = T_447[37];
+ assign T_502 = T_447[36];
+ assign T_504 = T_447[35];
+ assign T_506 = T_447[34];
+ assign T_508 = T_447[33];
+ assign T_510 = T_447[32];
+ assign T_512 = T_447[31];
+ assign T_514 = T_447[30];
+ assign T_516 = T_447[29];
+ assign T_518 = T_447[28];
+ assign T_520 = T_447[27];
+ assign T_522 = T_447[26];
+ assign T_524 = T_447[25];
+ assign T_526 = T_447[24];
+ assign T_528 = T_447[23];
+ assign T_530 = T_447[22];
+ assign T_532 = T_447[21];
+ assign T_534 = T_447[20];
+ assign T_536 = T_447[19];
+ assign T_538 = T_447[18];
+ assign T_540 = T_447[17];
+ assign T_542 = T_447[16];
+ assign T_544 = T_447[15];
+ assign T_546 = T_447[14];
+ assign T_548 = T_447[13];
+ assign T_550 = T_447[12];
+ assign T_552 = T_447[11];
+ assign T_554 = T_447[10];
+ assign T_556 = T_447[9];
+ assign T_558 = T_447[8];
+ assign T_560 = T_447[7];
+ assign T_562 = T_447[6];
+ assign T_564 = T_447[5];
+ assign T_566 = T_447[4];
+ assign T_568 = T_447[3];
+ assign T_570 = T_447[2];
+ assign T_572 = T_447[1];
+ assign T_573 = T_572 << 0;
+ assign T_574 = T_570 ? 2'h2 : T_573;
+ assign T_575 = T_568 ? 2'h3 : T_574;
+ assign T_576 = T_566 ? 3'h4 : T_575;
+ assign T_577 = T_564 ? 3'h5 : T_576;
+ assign T_578 = T_562 ? 3'h6 : T_577;
+ assign T_579 = T_560 ? 3'h7 : T_578;
+ assign T_580 = T_558 ? 4'h8 : T_579;
+ assign T_581 = T_556 ? 4'h9 : T_580;
+ assign T_582 = T_554 ? 4'ha : T_581;
+ assign T_583 = T_552 ? 4'hb : T_582;
+ assign T_584 = T_550 ? 4'hc : T_583;
+ assign T_585 = T_548 ? 4'hd : T_584;
+ assign T_586 = T_546 ? 4'he : T_585;
+ assign T_587 = T_544 ? 4'hf : T_586;
+ assign T_588 = T_542 ? 5'h10 : T_587;
+ assign T_589 = T_540 ? 5'h11 : T_588;
+ assign T_590 = T_538 ? 5'h12 : T_589;
+ assign T_591 = T_536 ? 5'h13 : T_590;
+ assign T_592 = T_534 ? 5'h14 : T_591;
+ assign T_593 = T_532 ? 5'h15 : T_592;
+ assign T_594 = T_530 ? 5'h16 : T_593;
+ assign T_595 = T_528 ? 5'h17 : T_594;
+ assign T_596 = T_526 ? 5'h18 : T_595;
+ assign T_597 = T_524 ? 5'h19 : T_596;
+ assign T_598 = T_522 ? 5'h1a : T_597;
+ assign T_599 = T_520 ? 5'h1b : T_598;
+ assign T_600 = T_518 ? 5'h1c : T_599;
+ assign T_601 = T_516 ? 5'h1d : T_600;
+ assign T_602 = T_514 ? 5'h1e : T_601;
+ assign T_603 = T_512 ? 5'h1f : T_602;
+ assign T_604 = T_510 ? 6'h20 : T_603;
+ assign T_605 = T_508 ? 6'h21 : T_604;
+ assign T_606 = T_506 ? 6'h22 : T_605;
+ assign T_607 = T_504 ? 6'h23 : T_606;
+ assign T_608 = T_502 ? 6'h24 : T_607;
+ assign T_609 = T_500 ? 6'h25 : T_608;
+ assign T_610 = T_498 ? 6'h26 : T_609;
+ assign T_611 = T_496 ? 6'h27 : T_610;
+ assign T_612 = T_494 ? 6'h28 : T_611;
+ assign T_613 = T_492 ? 6'h29 : T_612;
+ assign T_614 = T_490 ? 6'h2a : T_613;
+ assign T_615 = T_488 ? 6'h2b : T_614;
+ assign T_616 = T_486 ? 6'h2c : T_615;
+ assign T_617 = T_484 ? 6'h2d : T_616;
+ assign T_618 = T_482 ? 6'h2e : T_617;
+ assign T_619 = T_480 ? 6'h2f : T_618;
+ assign T_620 = T_478 ? 6'h30 : T_619;
+ assign T_621 = T_476 ? 6'h31 : T_620;
+ assign T_622 = T_474 ? 6'h32 : T_621;
+ assign T_623 = T_472 ? 6'h33 : T_622;
+ assign T_624 = T_470 ? 6'h34 : T_623;
+ assign T_625 = T_468 ? 6'h35 : T_624;
+ assign T_626 = T_466 ? 6'h36 : T_625;
+ assign T_627 = T_464 ? 6'h37 : T_626;
+ assign T_628 = T_462 ? 6'h38 : T_627;
+ assign T_629 = T_460 ? 6'h39 : T_628;
+ assign T_630 = T_458 ? 6'h3a : T_629;
+ assign T_631 = T_456 ? 6'h3b : T_630;
+ assign T_632 = T_454 ? 6'h3c : T_631;
+ assign T_633 = T_452 ? 6'h3d : T_632;
+ assign T_634 = T_450 ? 6'h3e : T_633;
+ assign T_635 = T_448 ? 6'h3f : T_634;
+ assign T_637 = 6'h3f + T_446;
+ assign T_638 = T_637[5:0];
+ assign T_639 = T_638 - T_635;
+ assign T_640 = T_639[5:0];
+ assign T_641 = T_446 > T_635;
+ assign T_643 = count == 1'h0;
+ assign T_644 = T_643 & less;
+ assign T_646 = T_640 > 1'h0;
+ assign T_647 = T_646 | T_641;
+ assign T_648 = T_644 & T_647;
+ assign T_650 = 1'h1 & T_648;
+ assign T_652 = T_640;
+ assign T_653 = T_641 ? 6'h3f : T_652;
+ assign T_654 = remainder[63:0];
+ assign T_655 = T_654 << T_653;
+ assign T_657 = count == 1'h0;
+ assign T_659 = less == 1'h0;
+ assign T_660 = T_657 & T_659;
+ assign T_662 = isHi == 1'h0;
+ assign T_663 = T_660 & T_662;
+ assign T_665 = io_resp_ready & io_resp_valid;
+ assign T_666 = T_665 | io_kill;
+ assign T_667 = io_req_ready & io_req_valid;
+ assign T_669 = cmdMul == 1'h0;
+ assign T_670 = rhs_sign & T_669;
+ assign T_671 = lhs_sign | T_670;
+ assign T_672 = T_671 ? 1'h1 : 2'h2;
+ assign T_675 = cmdMul == 1'h0;
+ assign T_676 = lhs_sign != rhs_sign;
+ assign T_677 = cmdHi ? lhs_sign : T_676;
+ assign T_678 = T_675 & T_677;
+ assign T_679 = {rhs_sign,rhs_in};
+ assign T_682 = req_dw & 1'h1;
+ assign T_683 = 1'h0 == T_682;
+ assign T_684 = remainder[31];
+ assign T_686 = 32'h0 - T_684;
+ assign T_687 = T_686[31:0];
+ assign T_688 = remainder[31:0];
+ assign T_689 = {T_687,T_688};
+ assign T_690 = remainder[63:0];
+ assign T_691 = T_683 ? T_689 : T_690;
+ assign T_692 = state == 3'h5;
+ assign T_693 = state == 1'h0;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ state = {1{$random}};
+ req_fn = {1{$random}};
+ req_dw = {1{$random}};
+ req_in1 = {2{$random}};
+ req_in2 = {2{$random}};
+ req_tag = {1{$random}};
+ count = {1{$random}};
+ neg_out = {1{$random}};
+ isMul = {1{$random}};
+ isHi = {1{$random}};
+ divisor = {3{$random}};
+ remainder = {5{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ state <= 1'h0;
+ end else begin
+ if(T_667) begin
+ state <= T_672;
+ end else begin
+ if(T_666) begin
+ state <= 1'h0;
+ end else begin
+ if(T_242) begin
+ if(T_244) begin
+ state <= T_246;
+ end else begin
+ if(T_179) begin
+ if(T_237) begin
+ state <= T_238;
+ end else begin
+ if(T_175) begin
+ state <= T_177;
+ end else begin
+ if(T_174) begin
+ state <= 3'h5;
+ end else begin
+ if(T_169) begin
+ state <= 2'h2;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_175) begin
+ state <= T_177;
+ end else begin
+ if(T_174) begin
+ state <= 3'h5;
+ end else begin
+ if(T_169) begin
+ state <= 2'h2;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_179) begin
+ if(T_237) begin
+ state <= T_238;
+ end else begin
+ if(T_175) begin
+ state <= T_177;
+ end else begin
+ if(T_174) begin
+ state <= 3'h5;
+ end else begin
+ if(T_169) begin
+ state <= 2'h2;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_175) begin
+ state <= T_177;
+ end else begin
+ if(T_174) begin
+ state <= 3'h5;
+ end else begin
+ if(T_169) begin
+ state <= 2'h2;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_667) begin
+ req_fn <= io_req_bits_fn;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_667) begin
+ req_dw <= io_req_bits_dw;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_667) begin
+ req_in1 <= io_req_bits_in1;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_667) begin
+ req_in2 <= io_req_bits_in2;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_667) begin
+ req_tag <= io_req_bits_tag;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_667) begin
+ count <= 1'h0;
+ end else begin
+ if(T_242) begin
+ if(T_650) begin
+ count <= T_653;
+ end else begin
+ count <= T_249;
+ end
+ end else begin
+ if(T_179) begin
+ count <= T_234;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_667) begin
+ neg_out <= T_678;
+ end else begin
+ if(T_242) begin
+ if(T_663) begin
+ neg_out <= 1'h0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_667) begin
+ isMul <= cmdMul;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_667) begin
+ isHi <= cmdHi;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_667) begin
+ divisor <= T_679;
+ end else begin
+ if(T_169) begin
+ if(T_173) begin
+ divisor <= subtractor;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_667) begin
+ remainder <= lhs_in;
+ end else begin
+ if(T_242) begin
+ if(T_650) begin
+ remainder <= T_655;
+ end else begin
+ remainder <= T_257;
+ end
+ end else begin
+ if(T_179) begin
+ remainder <= T_231;
+ end else begin
+ if(T_175) begin
+ remainder <= T_176;
+ end else begin
+ if(T_174) begin
+ remainder <= negated_remainder;
+ end else begin
+ if(T_169) begin
+ if(T_171) begin
+ remainder <= negated_remainder;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+endmodule
+module Rocket(
+ input clk,
+ input reset,
+ input io_host_reset,
+ input io_host_id,
+ output io_host_csr_req_ready,
+ input io_host_csr_req_valid,
+ input io_host_csr_req_bits_rw,
+ input [11:0] io_host_csr_req_bits_addr,
+ input [63:0] io_host_csr_req_bits_data,
+ input io_host_csr_resp_ready,
+ output io_host_csr_resp_valid,
+ output [63:0] io_host_csr_resp_bits,
+ output io_host_debug_stats_csr,
+ output io_imem_req_valid,
+ output [39:0] io_imem_req_bits_pc,
+ output io_imem_resp_ready,
+ input io_imem_resp_valid,
+ input [39:0] io_imem_resp_bits_pc,
+ input [31:0] io_imem_resp_bits_data_0,
+ input io_imem_resp_bits_mask,
+ input io_imem_resp_bits_xcpt_if,
+ input io_imem_btb_resp_valid,
+ input io_imem_btb_resp_bits_taken,
+ input io_imem_btb_resp_bits_mask,
+ input io_imem_btb_resp_bits_bridx,
+ input [38:0] io_imem_btb_resp_bits_target,
+ input [5:0] io_imem_btb_resp_bits_entry,
+ input [6:0] io_imem_btb_resp_bits_bht_history,
+ input [1:0] io_imem_btb_resp_bits_bht_value,
+ output io_imem_btb_update_valid,
+ output io_imem_btb_update_bits_prediction_valid,
+ output io_imem_btb_update_bits_prediction_bits_taken,
+ output io_imem_btb_update_bits_prediction_bits_mask,
+ output io_imem_btb_update_bits_prediction_bits_bridx,
+ output [38:0] io_imem_btb_update_bits_prediction_bits_target,
+ output [5:0] io_imem_btb_update_bits_prediction_bits_entry,
+ output [6:0] io_imem_btb_update_bits_prediction_bits_bht_history,
+ output [1:0] io_imem_btb_update_bits_prediction_bits_bht_value,
+ output [38:0] io_imem_btb_update_bits_pc,
+ output [38:0] io_imem_btb_update_bits_target,
+ output io_imem_btb_update_bits_taken,
+ output io_imem_btb_update_bits_isJump,
+ output io_imem_btb_update_bits_isReturn,
+ output [38:0] io_imem_btb_update_bits_br_pc,
+ output io_imem_bht_update_valid,
+ output io_imem_bht_update_bits_prediction_valid,
+ output io_imem_bht_update_bits_prediction_bits_taken,
+ output io_imem_bht_update_bits_prediction_bits_mask,
+ output io_imem_bht_update_bits_prediction_bits_bridx,
+ output [38:0] io_imem_bht_update_bits_prediction_bits_target,
+ output [5:0] io_imem_bht_update_bits_prediction_bits_entry,
+ output [6:0] io_imem_bht_update_bits_prediction_bits_bht_history,
+ output [1:0] io_imem_bht_update_bits_prediction_bits_bht_value,
+ output [38:0] io_imem_bht_update_bits_pc,
+ output io_imem_bht_update_bits_taken,
+ output io_imem_bht_update_bits_mispredict,
+ output io_imem_ras_update_valid,
+ output io_imem_ras_update_bits_isCall,
+ output io_imem_ras_update_bits_isReturn,
+ output [38:0] io_imem_ras_update_bits_returnAddr,
+ output io_imem_ras_update_bits_prediction_valid,
+ output io_imem_ras_update_bits_prediction_bits_taken,
+ output io_imem_ras_update_bits_prediction_bits_mask,
+ output io_imem_ras_update_bits_prediction_bits_bridx,
+ output [38:0] io_imem_ras_update_bits_prediction_bits_target,
+ output [5:0] io_imem_ras_update_bits_prediction_bits_entry,
+ output [6:0] io_imem_ras_update_bits_prediction_bits_bht_history,
+ output [1:0] io_imem_ras_update_bits_prediction_bits_bht_value,
+ output io_imem_invalidate,
+ input [39:0] io_imem_npc,
+ input io_dmem_req_ready,
+ output io_dmem_req_valid,
+ output [39:0] io_dmem_req_bits_addr,
+ output [8:0] io_dmem_req_bits_tag,
+ output [4:0] io_dmem_req_bits_cmd,
+ output [2:0] io_dmem_req_bits_typ,
+ output io_dmem_req_bits_kill,
+ output io_dmem_req_bits_phys,
+ output [63:0] io_dmem_req_bits_data,
+ input io_dmem_resp_valid,
+ input [39:0] io_dmem_resp_bits_addr,
+ input [8:0] io_dmem_resp_bits_tag,
+ input [4:0] io_dmem_resp_bits_cmd,
+ input [2:0] io_dmem_resp_bits_typ,
+ input [63:0] io_dmem_resp_bits_data,
+ input io_dmem_resp_bits_nack,
+ input io_dmem_resp_bits_replay,
+ input io_dmem_resp_bits_has_data,
+ input [63:0] io_dmem_resp_bits_data_word_bypass,
+ input [63:0] io_dmem_resp_bits_store_data,
+ input io_dmem_replay_next_valid,
+ input [8:0] io_dmem_replay_next_bits,
+ input io_dmem_xcpt_ma_ld,
+ input io_dmem_xcpt_ma_st,
+ input io_dmem_xcpt_pf_ld,
+ input io_dmem_xcpt_pf_st,
+ output io_dmem_invalidate_lr,
+ input io_dmem_ordered,
+ output [31:0] io_ptw_ptbr,
+ output io_ptw_invalidate,
+ output io_ptw_status_sd,
+ output [30:0] io_ptw_status_zero2,
+ output io_ptw_status_sd_rv32,
+ output [8:0] io_ptw_status_zero1,
+ output [4:0] io_ptw_status_vm,
+ output io_ptw_status_mprv,
+ output [1:0] io_ptw_status_xs,
+ output [1:0] io_ptw_status_fs,
+ output [1:0] io_ptw_status_prv3,
+ output io_ptw_status_ie3,
+ output [1:0] io_ptw_status_prv2,
+ output io_ptw_status_ie2,
+ output [1:0] io_ptw_status_prv1,
+ output io_ptw_status_ie1,
+ output [1:0] io_ptw_status_prv,
+ output io_ptw_status_ie,
+ output [31:0] io_fpu_inst,
+ output [63:0] io_fpu_fromint_data,
+ output [2:0] io_fpu_fcsr_rm,
+ input io_fpu_fcsr_flags_valid,
+ input [4:0] io_fpu_fcsr_flags_bits,
+ input [63:0] io_fpu_store_data,
+ input [63:0] io_fpu_toint_data,
+ output io_fpu_dmem_resp_val,
+ output [2:0] io_fpu_dmem_resp_type,
+ output [4:0] io_fpu_dmem_resp_tag,
+ output [63:0] io_fpu_dmem_resp_data,
+ output io_fpu_valid,
+ input io_fpu_fcsr_rdy,
+ input io_fpu_nack_mem,
+ input io_fpu_illegal_rm,
+ output io_fpu_killx,
+ output io_fpu_killm,
+ input [4:0] io_fpu_dec_cmd,
+ input io_fpu_dec_ldst,
+ input io_fpu_dec_wen,
+ input io_fpu_dec_ren1,
+ input io_fpu_dec_ren2,
+ input io_fpu_dec_ren3,
+ input io_fpu_dec_swap12,
+ input io_fpu_dec_swap23,
+ input io_fpu_dec_single,
+ input io_fpu_dec_fromint,
+ input io_fpu_dec_toint,
+ input io_fpu_dec_fastpipe,
+ input io_fpu_dec_fma,
+ input io_fpu_dec_div,
+ input io_fpu_dec_sqrt,
+ input io_fpu_dec_round,
+ input io_fpu_dec_wflags,
+ input io_fpu_sboard_set,
+ input io_fpu_sboard_clr,
+ input [4:0] io_fpu_sboard_clra,
+ input io_fpu_cp_req_ready,
+ output io_fpu_cp_req_valid,
+ output [4:0] io_fpu_cp_req_bits_cmd,
+ output io_fpu_cp_req_bits_ldst,
+ output io_fpu_cp_req_bits_wen,
+ output io_fpu_cp_req_bits_ren1,
+ output io_fpu_cp_req_bits_ren2,
+ output io_fpu_cp_req_bits_ren3,
+ output io_fpu_cp_req_bits_swap12,
+ output io_fpu_cp_req_bits_swap23,
+ output io_fpu_cp_req_bits_single,
+ output io_fpu_cp_req_bits_fromint,
+ output io_fpu_cp_req_bits_toint,
+ output io_fpu_cp_req_bits_fastpipe,
+ output io_fpu_cp_req_bits_fma,
+ output io_fpu_cp_req_bits_div,
+ output io_fpu_cp_req_bits_sqrt,
+ output io_fpu_cp_req_bits_round,
+ output io_fpu_cp_req_bits_wflags,
+ output [2:0] io_fpu_cp_req_bits_rm,
+ output [1:0] io_fpu_cp_req_bits_typ,
+ output [64:0] io_fpu_cp_req_bits_in1,
+ output [64:0] io_fpu_cp_req_bits_in2,
+ output [64:0] io_fpu_cp_req_bits_in3,
+ output io_fpu_cp_resp_ready,
+ input io_fpu_cp_resp_valid,
+ input [64:0] io_fpu_cp_resp_bits_data,
+ input [4:0] io_fpu_cp_resp_bits_exc,
+ input io_rocc_cmd_ready,
+ output io_rocc_cmd_valid,
+ output [6:0] io_rocc_cmd_bits_inst_funct,
+ output [4:0] io_rocc_cmd_bits_inst_rs2,
+ output [4:0] io_rocc_cmd_bits_inst_rs1,
+ output io_rocc_cmd_bits_inst_xd,
+ output io_rocc_cmd_bits_inst_xs1,
+ output io_rocc_cmd_bits_inst_xs2,
+ output [4:0] io_rocc_cmd_bits_inst_rd,
+ output [6:0] io_rocc_cmd_bits_inst_opcode,
+ output [63:0] io_rocc_cmd_bits_rs1,
+ output [63:0] io_rocc_cmd_bits_rs2,
+ output io_rocc_resp_ready,
+ input io_rocc_resp_valid,
+ input [4:0] io_rocc_resp_bits_rd,
+ input [63:0] io_rocc_resp_bits_data,
+ output io_rocc_mem_req_ready,
+ input io_rocc_mem_req_valid,
+ input [39:0] io_rocc_mem_req_bits_addr,
+ input [8:0] io_rocc_mem_req_bits_tag,
+ input [4:0] io_rocc_mem_req_bits_cmd,
+ input [2:0] io_rocc_mem_req_bits_typ,
+ input io_rocc_mem_req_bits_kill,
+ input io_rocc_mem_req_bits_phys,
+ input [63:0] io_rocc_mem_req_bits_data,
+ output io_rocc_mem_resp_valid,
+ output [39:0] io_rocc_mem_resp_bits_addr,
+ output [8:0] io_rocc_mem_resp_bits_tag,
+ output [4:0] io_rocc_mem_resp_bits_cmd,
+ output [2:0] io_rocc_mem_resp_bits_typ,
+ output [63:0] io_rocc_mem_resp_bits_data,
+ output io_rocc_mem_resp_bits_nack,
+ output io_rocc_mem_resp_bits_replay,
+ output io_rocc_mem_resp_bits_has_data,
+ output [63:0] io_rocc_mem_resp_bits_data_word_bypass,
+ output [63:0] io_rocc_mem_resp_bits_store_data,
+ output io_rocc_mem_replay_next_valid,
+ output [8:0] io_rocc_mem_replay_next_bits,
+ output io_rocc_mem_xcpt_ma_ld,
+ output io_rocc_mem_xcpt_ma_st,
+ output io_rocc_mem_xcpt_pf_ld,
+ output io_rocc_mem_xcpt_pf_st,
+ input io_rocc_mem_invalidate_lr,
+ output io_rocc_mem_ordered,
+ input io_rocc_busy,
+ output io_rocc_s,
+ input io_rocc_interrupt,
+ output io_rocc_autl_acquire_ready,
+ input io_rocc_autl_acquire_valid,
+ input [25:0] io_rocc_autl_acquire_bits_addr_block,
+ input [1:0] io_rocc_autl_acquire_bits_client_xact_id,
+ input [1:0] io_rocc_autl_acquire_bits_addr_beat,
+ input io_rocc_autl_acquire_bits_is_builtin_type,
+ input [2:0] io_rocc_autl_acquire_bits_a_type,
+ input [16:0] io_rocc_autl_acquire_bits_union,
+ input [127:0] io_rocc_autl_acquire_bits_data,
+ input io_rocc_autl_grant_ready,
+ output io_rocc_autl_grant_valid,
+ output [1:0] io_rocc_autl_grant_bits_addr_beat,
+ output [1:0] io_rocc_autl_grant_bits_client_xact_id,
+ output [3:0] io_rocc_autl_grant_bits_manager_xact_id,
+ output io_rocc_autl_grant_bits_is_builtin_type,
+ output [3:0] io_rocc_autl_grant_bits_g_type,
+ output [127:0] io_rocc_autl_grant_bits_data,
+ output io_rocc_iptw_req_ready,
+ input io_rocc_iptw_req_valid,
+ input [26:0] io_rocc_iptw_req_bits_addr,
+ input [1:0] io_rocc_iptw_req_bits_prv,
+ input io_rocc_iptw_req_bits_store,
+ input io_rocc_iptw_req_bits_fetch,
+ output io_rocc_iptw_resp_valid,
+ output io_rocc_iptw_resp_bits_error,
+ output [19:0] io_rocc_iptw_resp_bits_pte_ppn,
+ output [2:0] io_rocc_iptw_resp_bits_pte_reserved_for_software,
+ output io_rocc_iptw_resp_bits_pte_d,
+ output io_rocc_iptw_resp_bits_pte_r,
+ output [3:0] io_rocc_iptw_resp_bits_pte_typ,
+ output io_rocc_iptw_resp_bits_pte_v,
+ output io_rocc_iptw_status_sd,
+ output [30:0] io_rocc_iptw_status_zero2,
+ output io_rocc_iptw_status_sd_rv32,
+ output [8:0] io_rocc_iptw_status_zero1,
+ output [4:0] io_rocc_iptw_status_vm,
+ output io_rocc_iptw_status_mprv,
+ output [1:0] io_rocc_iptw_status_xs,
+ output [1:0] io_rocc_iptw_status_fs,
+ output [1:0] io_rocc_iptw_status_prv3,
+ output io_rocc_iptw_status_ie3,
+ output [1:0] io_rocc_iptw_status_prv2,
+ output io_rocc_iptw_status_ie2,
+ output [1:0] io_rocc_iptw_status_prv1,
+ output io_rocc_iptw_status_ie1,
+ output [1:0] io_rocc_iptw_status_prv,
+ output io_rocc_iptw_status_ie,
+ output io_rocc_iptw_invalidate,
+ output io_rocc_dptw_req_ready,
+ input io_rocc_dptw_req_valid,
+ input [26:0] io_rocc_dptw_req_bits_addr,
+ input [1:0] io_rocc_dptw_req_bits_prv,
+ input io_rocc_dptw_req_bits_store,
+ input io_rocc_dptw_req_bits_fetch,
+ output io_rocc_dptw_resp_valid,
+ output io_rocc_dptw_resp_bits_error,
+ output [19:0] io_rocc_dptw_resp_bits_pte_ppn,
+ output [2:0] io_rocc_dptw_resp_bits_pte_reserved_for_software,
+ output io_rocc_dptw_resp_bits_pte_d,
+ output io_rocc_dptw_resp_bits_pte_r,
+ output [3:0] io_rocc_dptw_resp_bits_pte_typ,
+ output io_rocc_dptw_resp_bits_pte_v,
+ output io_rocc_dptw_status_sd,
+ output [30:0] io_rocc_dptw_status_zero2,
+ output io_rocc_dptw_status_sd_rv32,
+ output [8:0] io_rocc_dptw_status_zero1,
+ output [4:0] io_rocc_dptw_status_vm,
+ output io_rocc_dptw_status_mprv,
+ output [1:0] io_rocc_dptw_status_xs,
+ output [1:0] io_rocc_dptw_status_fs,
+ output [1:0] io_rocc_dptw_status_prv3,
+ output io_rocc_dptw_status_ie3,
+ output [1:0] io_rocc_dptw_status_prv2,
+ output io_rocc_dptw_status_ie2,
+ output [1:0] io_rocc_dptw_status_prv1,
+ output io_rocc_dptw_status_ie1,
+ output [1:0] io_rocc_dptw_status_prv,
+ output io_rocc_dptw_status_ie,
+ output io_rocc_dptw_invalidate,
+ output io_rocc_pptw_req_ready,
+ input io_rocc_pptw_req_valid,
+ input [26:0] io_rocc_pptw_req_bits_addr,
+ input [1:0] io_rocc_pptw_req_bits_prv,
+ input io_rocc_pptw_req_bits_store,
+ input io_rocc_pptw_req_bits_fetch,
+ output io_rocc_pptw_resp_valid,
+ output io_rocc_pptw_resp_bits_error,
+ output [19:0] io_rocc_pptw_resp_bits_pte_ppn,
+ output [2:0] io_rocc_pptw_resp_bits_pte_reserved_for_software,
+ output io_rocc_pptw_resp_bits_pte_d,
+ output io_rocc_pptw_resp_bits_pte_r,
+ output [3:0] io_rocc_pptw_resp_bits_pte_typ,
+ output io_rocc_pptw_resp_bits_pte_v,
+ output io_rocc_pptw_status_sd,
+ output [30:0] io_rocc_pptw_status_zero2,
+ output io_rocc_pptw_status_sd_rv32,
+ output [8:0] io_rocc_pptw_status_zero1,
+ output [4:0] io_rocc_pptw_status_vm,
+ output io_rocc_pptw_status_mprv,
+ output [1:0] io_rocc_pptw_status_xs,
+ output [1:0] io_rocc_pptw_status_fs,
+ output [1:0] io_rocc_pptw_status_prv3,
+ output io_rocc_pptw_status_ie3,
+ output [1:0] io_rocc_pptw_status_prv2,
+ output io_rocc_pptw_status_ie2,
+ output [1:0] io_rocc_pptw_status_prv1,
+ output io_rocc_pptw_status_ie1,
+ output [1:0] io_rocc_pptw_status_prv,
+ output io_rocc_pptw_status_ie,
+ output io_rocc_pptw_invalidate,
+ output io_rocc_fpu_req_ready,
+ input io_rocc_fpu_req_valid,
+ input [4:0] io_rocc_fpu_req_bits_cmd,
+ input io_rocc_fpu_req_bits_ldst,
+ input io_rocc_fpu_req_bits_wen,
+ input io_rocc_fpu_req_bits_ren1,
+ input io_rocc_fpu_req_bits_ren2,
+ input io_rocc_fpu_req_bits_ren3,
+ input io_rocc_fpu_req_bits_swap12,
+ input io_rocc_fpu_req_bits_swap23,
+ input io_rocc_fpu_req_bits_single,
+ input io_rocc_fpu_req_bits_fromint,
+ input io_rocc_fpu_req_bits_toint,
+ input io_rocc_fpu_req_bits_fastpipe,
+ input io_rocc_fpu_req_bits_fma,
+ input io_rocc_fpu_req_bits_div,
+ input io_rocc_fpu_req_bits_sqrt,
+ input io_rocc_fpu_req_bits_round,
+ input io_rocc_fpu_req_bits_wflags,
+ input [2:0] io_rocc_fpu_req_bits_rm,
+ input [1:0] io_rocc_fpu_req_bits_typ,
+ input [64:0] io_rocc_fpu_req_bits_in1,
+ input [64:0] io_rocc_fpu_req_bits_in2,
+ input [64:0] io_rocc_fpu_req_bits_in3,
+ input io_rocc_fpu_resp_ready,
+ output io_rocc_fpu_resp_valid,
+ output [64:0] io_rocc_fpu_resp_bits_data,
+ output [4:0] io_rocc_fpu_resp_bits_exc,
+ output io_rocc_exception,
+ output io_rocc_dma_req_ready,
+ input io_rocc_dma_req_valid,
+ input [1:0] io_rocc_dma_req_bits_client_xact_id,
+ input [2:0] io_rocc_dma_req_bits_cmd,
+ input [31:0] io_rocc_dma_req_bits_source,
+ input [31:0] io_rocc_dma_req_bits_dest,
+ input [31:0] io_rocc_dma_req_bits_length,
+ input [1:0] io_rocc_dma_req_bits_size,
+ input io_rocc_dma_resp_ready,
+ output io_rocc_dma_resp_valid,
+ output [1:0] io_rocc_dma_resp_bits_client_xact_id,
+ output [1:0] io_rocc_dma_resp_bits_status
+);
+ reg ex_ctrl_legal;
+ reg ex_ctrl_fp;
+ reg ex_ctrl_rocc;
+ reg ex_ctrl_branch;
+ reg ex_ctrl_jal;
+ reg ex_ctrl_jalr;
+ reg ex_ctrl_rxs2;
+ reg ex_ctrl_rxs1;
+ reg [1:0] ex_ctrl_sel_alu2;
+ reg [1:0] ex_ctrl_sel_alu1;
+ reg [2:0] ex_ctrl_sel_imm;
+ reg ex_ctrl_alu_dw;
+ reg [3:0] ex_ctrl_alu_fn;
+ reg ex_ctrl_mem;
+ reg [4:0] ex_ctrl_mem_cmd;
+ reg [2:0] ex_ctrl_mem_type;
+ reg ex_ctrl_rfs1;
+ reg ex_ctrl_rfs2;
+ reg ex_ctrl_rfs3;
+ reg ex_ctrl_wfd;
+ reg ex_ctrl_div;
+ reg ex_ctrl_wxd;
+ reg [2:0] ex_ctrl_csr;
+ reg ex_ctrl_fence_i;
+ reg ex_ctrl_fence;
+ reg ex_ctrl_amo;
+ reg mem_ctrl_legal;
+ reg mem_ctrl_fp;
+ reg mem_ctrl_rocc;
+ reg mem_ctrl_branch;
+ reg mem_ctrl_jal;
+ reg mem_ctrl_jalr;
+ reg mem_ctrl_rxs2;
+ reg mem_ctrl_rxs1;
+ reg [1:0] mem_ctrl_sel_alu2;
+ reg [1:0] mem_ctrl_sel_alu1;
+ reg [2:0] mem_ctrl_sel_imm;
+ reg mem_ctrl_alu_dw;
+ reg [3:0] mem_ctrl_alu_fn;
+ reg mem_ctrl_mem;
+ reg [4:0] mem_ctrl_mem_cmd;
+ reg [2:0] mem_ctrl_mem_type;
+ reg mem_ctrl_rfs1;
+ reg mem_ctrl_rfs2;
+ reg mem_ctrl_rfs3;
+ reg mem_ctrl_wfd;
+ reg mem_ctrl_div;
+ reg mem_ctrl_wxd;
+ reg [2:0] mem_ctrl_csr;
+ reg mem_ctrl_fence_i;
+ reg mem_ctrl_fence;
+ reg mem_ctrl_amo;
+ reg wb_ctrl_legal;
+ reg wb_ctrl_fp;
+ reg wb_ctrl_rocc;
+ reg wb_ctrl_branch;
+ reg wb_ctrl_jal;
+ reg wb_ctrl_jalr;
+ reg wb_ctrl_rxs2;
+ reg wb_ctrl_rxs1;
+ reg [1:0] wb_ctrl_sel_alu2;
+ reg [1:0] wb_ctrl_sel_alu1;
+ reg [2:0] wb_ctrl_sel_imm;
+ reg wb_ctrl_alu_dw;
+ reg [3:0] wb_ctrl_alu_fn;
+ reg wb_ctrl_mem;
+ reg [4:0] wb_ctrl_mem_cmd;
+ reg [2:0] wb_ctrl_mem_type;
+ reg wb_ctrl_rfs1;
+ reg wb_ctrl_rfs2;
+ reg wb_ctrl_rfs3;
+ reg wb_ctrl_wfd;
+ reg wb_ctrl_div;
+ reg wb_ctrl_wxd;
+ reg [2:0] wb_ctrl_csr;
+ reg wb_ctrl_fence_i;
+ reg wb_ctrl_fence;
+ reg wb_ctrl_amo;
+ reg ex_reg_xcpt_interrupt;
+ reg ex_reg_valid;
+ reg ex_reg_btb_hit;
+ reg ex_reg_btb_resp_taken;
+ reg ex_reg_btb_resp_mask;
+ reg ex_reg_btb_resp_bridx;
+ reg [38:0] ex_reg_btb_resp_target;
+ reg [5:0] ex_reg_btb_resp_entry;
+ reg [6:0] ex_reg_btb_resp_bht_history;
+ reg [1:0] ex_reg_btb_resp_bht_value;
+ reg ex_reg_xcpt;
+ reg ex_reg_flush_pipe;
+ reg ex_reg_load_use;
+ reg [63:0] ex_reg_cause;
+ reg [39:0] ex_reg_pc;
+ reg [31:0] ex_reg_inst;
+ reg mem_reg_xcpt_interrupt;
+ reg mem_reg_valid;
+ reg mem_reg_btb_hit;
+ reg mem_reg_btb_resp_taken;
+ reg mem_reg_btb_resp_mask;
+ reg mem_reg_btb_resp_bridx;
+ reg [38:0] mem_reg_btb_resp_target;
+ reg [5:0] mem_reg_btb_resp_entry;
+ reg [6:0] mem_reg_btb_resp_bht_history;
+ reg [1:0] mem_reg_btb_resp_bht_value;
+ reg mem_reg_xcpt;
+ reg mem_reg_replay;
+ reg mem_reg_flush_pipe;
+ reg [63:0] mem_reg_cause;
+ reg mem_reg_slow_bypass;
+ reg [39:0] mem_reg_pc;
+ reg [31:0] mem_reg_inst;
+ reg [63:0] mem_reg_wdata;
+ reg [63:0] mem_reg_rs2;
+ wire take_pc_mem;
+ reg wb_reg_valid;
+ reg wb_reg_xcpt;
+ reg wb_reg_replay;
+ reg [63:0] wb_reg_cause;
+ reg wb_reg_rocc_pending;
+ reg [39:0] wb_reg_pc;
+ reg [31:0] wb_reg_inst;
+ reg [63:0] wb_reg_wdata;
+ reg [63:0] wb_reg_rs2;
+ wire take_pc_wb;
+ wire take_pc_mem_wb;
+ wire id_ctrl_legal;
+ wire id_ctrl_fp;
+ wire id_ctrl_rocc;
+ wire id_ctrl_branch;
+ wire id_ctrl_jal;
+ wire id_ctrl_jalr;
+ wire id_ctrl_rxs2;
+ wire id_ctrl_rxs1;
+ wire [1:0] id_ctrl_sel_alu2;
+ wire [1:0] id_ctrl_sel_alu1;
+ wire [2:0] id_ctrl_sel_imm;
+ wire id_ctrl_alu_dw;
+ wire [3:0] id_ctrl_alu_fn;
+ wire id_ctrl_mem;
+ wire [4:0] id_ctrl_mem_cmd;
+ wire [2:0] id_ctrl_mem_type;
+ wire id_ctrl_rfs1;
+ wire id_ctrl_rfs2;
+ wire id_ctrl_rfs3;
+ wire id_ctrl_wfd;
+ wire id_ctrl_div;
+ wire id_ctrl_wxd;
+ wire [2:0] id_ctrl_csr;
+ wire id_ctrl_fence_i;
+ wire id_ctrl_fence;
+ wire id_ctrl_amo;
+ wire [31:0] T_6071;
+ wire T_6073;
+ wire [31:0] T_6075;
+ wire T_6077;
+ wire [31:0] T_6079;
+ wire T_6081;
+ wire [31:0] T_6083;
+ wire T_6085;
+ wire [31:0] T_6087;
+ wire T_6089;
+ wire [31:0] T_6091;
+ wire T_6093;
+ wire [31:0] T_6095;
+ wire T_6097;
+ wire [31:0] T_6099;
+ wire T_6101;
+ wire [31:0] T_6103;
+ wire T_6105;
+ wire [31:0] T_6107;
+ wire T_6109;
+ wire [31:0] T_6111;
+ wire T_6113;
+ wire [31:0] T_6115;
+ wire T_6117;
+ wire [31:0] T_6119;
+ wire T_6121;
+ wire [31:0] T_6123;
+ wire T_6125;
+ wire [31:0] T_6127;
+ wire T_6129;
+ wire [31:0] T_6131;
+ wire T_6133;
+ wire [31:0] T_6135;
+ wire T_6137;
+ wire [31:0] T_6139;
+ wire T_6141;
+ wire [31:0] T_6143;
+ wire T_6145;
+ wire [31:0] T_6147;
+ wire T_6149;
+ wire [31:0] T_6151;
+ wire T_6153;
+ wire [31:0] T_6155;
+ wire T_6157;
+ wire [31:0] T_6159;
+ wire T_6161;
+ wire [31:0] T_6163;
+ wire T_6165;
+ wire [31:0] T_6167;
+ wire T_6169;
+ wire [31:0] T_6171;
+ wire T_6173;
+ wire [31:0] T_6175;
+ wire T_6177;
+ wire [31:0] T_6179;
+ wire T_6181;
+ wire [31:0] T_6183;
+ wire T_6185;
+ wire T_6187;
+ wire [31:0] T_6189;
+ wire T_6191;
+ wire [31:0] T_6193;
+ wire T_6195;
+ wire [31:0] T_6197;
+ wire T_6199;
+ wire [31:0] T_6201;
+ wire T_6203;
+ wire [31:0] T_6205;
+ wire T_6207;
+ wire [31:0] T_6209;
+ wire T_6211;
+ wire [31:0] T_6213;
+ wire T_6215;
+ wire [31:0] T_6217;
+ wire T_6219;
+ wire [31:0] T_6221;
+ wire T_6223;
+ wire [31:0] T_6225;
+ wire T_6227;
+ wire T_6229;
+ wire T_6230;
+ wire T_6231;
+ wire T_6232;
+ wire T_6233;
+ wire T_6234;
+ wire T_6235;
+ wire T_6236;
+ wire T_6237;
+ wire T_6238;
+ wire T_6239;
+ wire T_6240;
+ wire T_6241;
+ wire T_6242;
+ wire T_6243;
+ wire T_6244;
+ wire T_6245;
+ wire T_6246;
+ wire T_6247;
+ wire T_6248;
+ wire T_6249;
+ wire T_6250;
+ wire T_6251;
+ wire T_6252;
+ wire T_6253;
+ wire T_6254;
+ wire T_6255;
+ wire T_6256;
+ wire T_6257;
+ wire T_6258;
+ wire T_6259;
+ wire T_6260;
+ wire T_6261;
+ wire T_6262;
+ wire T_6263;
+ wire T_6264;
+ wire T_6265;
+ wire T_6266;
+ wire T_6267;
+ wire T_6268;
+ wire [31:0] T_6270;
+ wire T_6272;
+ wire [31:0] T_6274;
+ wire T_6276;
+ wire T_6278;
+ wire T_6279;
+ wire [31:0] T_6282;
+ wire T_6284;
+ wire T_6286;
+ wire [31:0] T_6288;
+ wire T_6290;
+ wire T_6292;
+ wire [31:0] T_6294;
+ wire T_6296;
+ wire T_6298;
+ wire [31:0] T_6300;
+ wire T_6302;
+ wire [31:0] T_6304;
+ wire T_6306;
+ wire [31:0] T_6308;
+ wire T_6310;
+ wire T_6312;
+ wire T_6313;
+ wire T_6314;
+ wire [31:0] T_6316;
+ wire T_6318;
+ wire [31:0] T_6320;
+ wire T_6322;
+ wire [31:0] T_6324;
+ wire T_6326;
+ wire [31:0] T_6328;
+ wire T_6330;
+ wire [31:0] T_6332;
+ wire T_6334;
+ wire T_6336;
+ wire T_6337;
+ wire T_6338;
+ wire T_6339;
+ wire T_6340;
+ wire [31:0] T_6342;
+ wire T_6344;
+ wire [31:0] T_6346;
+ wire T_6348;
+ wire [31:0] T_6350;
+ wire T_6352;
+ wire [31:0] T_6354;
+ wire T_6356;
+ wire [31:0] T_6358;
+ wire T_6360;
+ wire T_6362;
+ wire T_6363;
+ wire T_6364;
+ wire T_6365;
+ wire T_6366;
+ wire [31:0] T_6368;
+ wire T_6370;
+ wire [31:0] T_6372;
+ wire T_6374;
+ wire [31:0] T_6376;
+ wire T_6378;
+ wire T_6380;
+ wire T_6381;
+ wire T_6382;
+ wire T_6383;
+ wire [1:0] T_6384;
+ wire [31:0] T_6386;
+ wire T_6388;
+ wire [31:0] T_6390;
+ wire T_6392;
+ wire [31:0] T_6394;
+ wire T_6396;
+ wire T_6398;
+ wire T_6399;
+ wire T_6400;
+ wire T_6401;
+ wire T_6402;
+ wire [31:0] T_6404;
+ wire T_6406;
+ wire T_6408;
+ wire T_6409;
+ wire [1:0] T_6410;
+ wire [31:0] T_6412;
+ wire T_6414;
+ wire [31:0] T_6416;
+ wire T_6418;
+ wire T_6420;
+ wire T_6421;
+ wire [31:0] T_6423;
+ wire T_6425;
+ wire T_6427;
+ wire T_6428;
+ wire [31:0] T_6430;
+ wire T_6432;
+ wire [31:0] T_6434;
+ wire T_6436;
+ wire [31:0] T_6438;
+ wire T_6440;
+ wire T_6442;
+ wire T_6443;
+ wire T_6444;
+ wire [1:0] T_6445;
+ wire [2:0] T_6446;
+ wire [31:0] T_6448;
+ wire T_6450;
+ wire [31:0] T_6452;
+ wire T_6454;
+ wire T_6456;
+ wire T_6457;
+ wire [31:0] T_6459;
+ wire T_6461;
+ wire [31:0] T_6463;
+ wire T_6465;
+ wire [31:0] T_6467;
+ wire T_6469;
+ wire T_6471;
+ wire T_6472;
+ wire T_6473;
+ wire [31:0] T_6475;
+ wire T_6477;
+ wire [31:0] T_6479;
+ wire T_6481;
+ wire [31:0] T_6483;
+ wire T_6485;
+ wire [31:0] T_6487;
+ wire T_6489;
+ wire [31:0] T_6491;
+ wire T_6493;
+ wire [31:0] T_6495;
+ wire T_6497;
+ wire T_6499;
+ wire T_6500;
+ wire T_6501;
+ wire T_6502;
+ wire T_6503;
+ wire T_6504;
+ wire [31:0] T_6506;
+ wire T_6508;
+ wire [31:0] T_6510;
+ wire T_6512;
+ wire [31:0] T_6514;
+ wire T_6516;
+ wire [31:0] T_6518;
+ wire T_6520;
+ wire T_6522;
+ wire T_6523;
+ wire T_6524;
+ wire T_6525;
+ wire [31:0] T_6527;
+ wire T_6529;
+ wire [31:0] T_6531;
+ wire T_6533;
+ wire T_6535;
+ wire T_6536;
+ wire T_6537;
+ wire T_6538;
+ wire [1:0] T_6539;
+ wire [2:0] T_6540;
+ wire [3:0] T_6541;
+ wire [31:0] T_6543;
+ wire T_6545;
+ wire [31:0] T_6547;
+ wire T_6549;
+ wire T_6551;
+ wire T_6552;
+ wire T_6553;
+ wire T_6554;
+ wire T_6555;
+ wire T_6556;
+ wire T_6557;
+ wire [31:0] T_6559;
+ wire T_6561;
+ wire [31:0] T_6563;
+ wire T_6565;
+ wire [31:0] T_6567;
+ wire T_6569;
+ wire T_6571;
+ wire T_6572;
+ wire T_6573;
+ wire [31:0] T_6575;
+ wire T_6577;
+ wire [31:0] T_6579;
+ wire T_6581;
+ wire T_6583;
+ wire T_6584;
+ wire [31:0] T_6586;
+ wire T_6588;
+ wire [31:0] T_6590;
+ wire T_6592;
+ wire T_6594;
+ wire T_6595;
+ wire T_6596;
+ wire [31:0] T_6598;
+ wire T_6600;
+ wire T_6602;
+ wire [1:0] T_6604;
+ wire [2:0] T_6605;
+ wire [3:0] T_6606;
+ wire [4:0] T_6607;
+ wire [31:0] T_6609;
+ wire T_6611;
+ wire T_6613;
+ wire [31:0] T_6615;
+ wire T_6617;
+ wire T_6619;
+ wire [31:0] T_6621;
+ wire T_6623;
+ wire T_6625;
+ wire [1:0] T_6626;
+ wire [2:0] T_6627;
+ wire [31:0] T_6629;
+ wire T_6631;
+ wire [31:0] T_6633;
+ wire T_6635;
+ wire [31:0] T_6637;
+ wire T_6639;
+ wire T_6641;
+ wire T_6642;
+ wire T_6643;
+ wire [31:0] T_6645;
+ wire T_6647;
+ wire [31:0] T_6649;
+ wire T_6651;
+ wire [31:0] T_6653;
+ wire T_6655;
+ wire T_6657;
+ wire T_6658;
+ wire T_6659;
+ wire T_6660;
+ wire T_6662;
+ wire [31:0] T_6664;
+ wire T_6666;
+ wire [31:0] T_6668;
+ wire T_6670;
+ wire T_6672;
+ wire T_6673;
+ wire T_6674;
+ wire T_6675;
+ wire [31:0] T_6677;
+ wire T_6679;
+ wire T_6681;
+ wire [31:0] T_6683;
+ wire T_6685;
+ wire [31:0] T_6687;
+ wire T_6689;
+ wire [31:0] T_6691;
+ wire T_6693;
+ wire [31:0] T_6695;
+ wire T_6697;
+ wire [31:0] T_6699;
+ wire T_6701;
+ wire [31:0] T_6703;
+ wire T_6705;
+ wire [31:0] T_6707;
+ wire T_6709;
+ wire T_6711;
+ wire T_6712;
+ wire T_6713;
+ wire T_6714;
+ wire T_6715;
+ wire T_6716;
+ wire T_6717;
+ wire [31:0] T_6719;
+ wire T_6721;
+ wire T_6723;
+ wire [31:0] T_6725;
+ wire T_6727;
+ wire T_6729;
+ wire [31:0] T_6731;
+ wire T_6733;
+ wire T_6735;
+ wire [1:0] T_6736;
+ wire [2:0] T_6737;
+ wire [31:0] T_6739;
+ wire T_6741;
+ wire T_6743;
+ wire [31:0] T_6745;
+ wire T_6747;
+ wire T_6749;
+ wire [31:0] T_6751;
+ wire T_6753;
+ wire T_6755;
+ wire [4:0] id_raddr3;
+ wire [4:0] id_raddr2;
+ wire [4:0] id_raddr1;
+ wire [4:0] id_waddr;
+ wire id_load_use;
+ reg id_reg_fence;
+ reg [63:0] T_6766 [0:30];
+ wire [63:0] T_6766_T_6776_data;
+ wire [4:0] T_6766_T_6776_addr;
+ wire T_6766_T_6776_en;
+ wire T_6766_T_6776_clk;
+ wire [63:0] T_6766_T_6787_data;
+ wire [4:0] T_6766_T_6787_addr;
+ wire T_6766_T_6787_en;
+ wire T_6766_T_6787_clk;
+ wire [63:0] T_6766_T_7490_data;
+ wire [4:0] T_6766_T_7490_addr;
+ wire T_6766_T_7490_mask;
+ wire T_6766_T_7490_en;
+ wire T_6766_T_7490_clk;
+ wire [63:0] T_6768;
+ wire T_6771;
+ wire T_6772;
+ wire [4:0] T_6774;
+ wire [4:0] T_6775;
+ wire [63:0] T_6777;
+ wire [63:0] T_6779;
+ wire T_6782;
+ wire T_6783;
+ wire [4:0] T_6785;
+ wire [4:0] T_6786;
+ wire [63:0] T_6788;
+ wire ctrl_killd;
+ wire csr_clk;
+ wire csr_reset;
+ wire csr_io_host_reset;
+ wire csr_io_host_id;
+ wire csr_io_host_csr_req_ready;
+ wire csr_io_host_csr_req_valid;
+ wire csr_io_host_csr_req_bits_rw;
+ wire [11:0] csr_io_host_csr_req_bits_addr;
+ wire [63:0] csr_io_host_csr_req_bits_data;
+ wire csr_io_host_csr_resp_ready;
+ wire csr_io_host_csr_resp_valid;
+ wire [63:0] csr_io_host_csr_resp_bits;
+ wire csr_io_host_debug_stats_csr;
+ wire [11:0] csr_io_rw_addr;
+ wire [2:0] csr_io_rw_cmd;
+ wire [63:0] csr_io_rw_rdata;
+ wire [63:0] csr_io_rw_wdata;
+ wire csr_io_csr_stall;
+ wire csr_io_csr_xcpt;
+ wire csr_io_eret;
+ wire csr_io_status_sd;
+ wire [30:0] csr_io_status_zero2;
+ wire csr_io_status_sd_rv32;
+ wire [8:0] csr_io_status_zero1;
+ wire [4:0] csr_io_status_vm;
+ wire csr_io_status_mprv;
+ wire [1:0] csr_io_status_xs;
+ wire [1:0] csr_io_status_fs;
+ wire [1:0] csr_io_status_prv3;
+ wire csr_io_status_ie3;
+ wire [1:0] csr_io_status_prv2;
+ wire csr_io_status_ie2;
+ wire [1:0] csr_io_status_prv1;
+ wire csr_io_status_ie1;
+ wire [1:0] csr_io_status_prv;
+ wire csr_io_status_ie;
+ wire [31:0] csr_io_ptbr;
+ wire [39:0] csr_io_evec;
+ wire csr_io_exception;
+ wire csr_io_retire;
+ wire csr_io_uarch_counters_0;
+ wire csr_io_uarch_counters_1;
+ wire csr_io_uarch_counters_2;
+ wire csr_io_uarch_counters_3;
+ wire csr_io_uarch_counters_4;
+ wire csr_io_uarch_counters_5;
+ wire csr_io_uarch_counters_6;
+ wire csr_io_uarch_counters_7;
+ wire csr_io_uarch_counters_8;
+ wire csr_io_uarch_counters_9;
+ wire csr_io_uarch_counters_10;
+ wire csr_io_uarch_counters_11;
+ wire csr_io_uarch_counters_12;
+ wire csr_io_uarch_counters_13;
+ wire csr_io_uarch_counters_14;
+ wire csr_io_uarch_counters_15;
+ wire [63:0] csr_io_cause;
+ wire [39:0] csr_io_pc;
+ wire csr_io_fatc;
+ wire [63:0] csr_io_time;
+ wire [2:0] csr_io_fcsr_rm;
+ wire csr_io_fcsr_flags_valid;
+ wire [4:0] csr_io_fcsr_flags_bits;
+ wire csr_io_rocc_cmd_ready;
+ wire csr_io_rocc_cmd_valid;
+ wire [6:0] csr_io_rocc_cmd_bits_inst_funct;
+ wire [4:0] csr_io_rocc_cmd_bits_inst_rs2;
+ wire [4:0] csr_io_rocc_cmd_bits_inst_rs1;
+ wire csr_io_rocc_cmd_bits_inst_xd;
+ wire csr_io_rocc_cmd_bits_inst_xs1;
+ wire csr_io_rocc_cmd_bits_inst_xs2;
+ wire [4:0] csr_io_rocc_cmd_bits_inst_rd;
+ wire [6:0] csr_io_rocc_cmd_bits_inst_opcode;
+ wire [63:0] csr_io_rocc_cmd_bits_rs1;
+ wire [63:0] csr_io_rocc_cmd_bits_rs2;
+ wire csr_io_rocc_resp_ready;
+ wire csr_io_rocc_resp_valid;
+ wire [4:0] csr_io_rocc_resp_bits_rd;
+ wire [63:0] csr_io_rocc_resp_bits_data;
+ wire csr_io_rocc_mem_req_ready;
+ wire csr_io_rocc_mem_req_valid;
+ wire [39:0] csr_io_rocc_mem_req_bits_addr;
+ wire [8:0] csr_io_rocc_mem_req_bits_tag;
+ wire [4:0] csr_io_rocc_mem_req_bits_cmd;
+ wire [2:0] csr_io_rocc_mem_req_bits_typ;
+ wire csr_io_rocc_mem_req_bits_kill;
+ wire csr_io_rocc_mem_req_bits_phys;
+ wire [63:0] csr_io_rocc_mem_req_bits_data;
+ wire csr_io_rocc_mem_resp_valid;
+ wire [39:0] csr_io_rocc_mem_resp_bits_addr;
+ wire [8:0] csr_io_rocc_mem_resp_bits_tag;
+ wire [4:0] csr_io_rocc_mem_resp_bits_cmd;
+ wire [2:0] csr_io_rocc_mem_resp_bits_typ;
+ wire [63:0] csr_io_rocc_mem_resp_bits_data;
+ wire csr_io_rocc_mem_resp_bits_nack;
+ wire csr_io_rocc_mem_resp_bits_replay;
+ wire csr_io_rocc_mem_resp_bits_has_data;
+ wire [63:0] csr_io_rocc_mem_resp_bits_data_word_bypass;
+ wire [63:0] csr_io_rocc_mem_resp_bits_store_data;
+ wire csr_io_rocc_mem_replay_next_valid;
+ wire [8:0] csr_io_rocc_mem_replay_next_bits;
+ wire csr_io_rocc_mem_xcpt_ma_ld;
+ wire csr_io_rocc_mem_xcpt_ma_st;
+ wire csr_io_rocc_mem_xcpt_pf_ld;
+ wire csr_io_rocc_mem_xcpt_pf_st;
+ wire csr_io_rocc_mem_invalidate_lr;
+ wire csr_io_rocc_mem_ordered;
+ wire csr_io_rocc_busy;
+ wire csr_io_rocc_s;
+ wire csr_io_rocc_interrupt;
+ wire csr_io_rocc_autl_acquire_ready;
+ wire csr_io_rocc_autl_acquire_valid;
+ wire [25:0] csr_io_rocc_autl_acquire_bits_addr_block;
+ wire [1:0] csr_io_rocc_autl_acquire_bits_client_xact_id;
+ wire [1:0] csr_io_rocc_autl_acquire_bits_addr_beat;
+ wire csr_io_rocc_autl_acquire_bits_is_builtin_type;
+ wire [2:0] csr_io_rocc_autl_acquire_bits_a_type;
+ wire [16:0] csr_io_rocc_autl_acquire_bits_union;
+ wire [127:0] csr_io_rocc_autl_acquire_bits_data;
+ wire csr_io_rocc_autl_grant_ready;
+ wire csr_io_rocc_autl_grant_valid;
+ wire [1:0] csr_io_rocc_autl_grant_bits_addr_beat;
+ wire [1:0] csr_io_rocc_autl_grant_bits_client_xact_id;
+ wire [3:0] csr_io_rocc_autl_grant_bits_manager_xact_id;
+ wire csr_io_rocc_autl_grant_bits_is_builtin_type;
+ wire [3:0] csr_io_rocc_autl_grant_bits_g_type;
+ wire [127:0] csr_io_rocc_autl_grant_bits_data;
+ wire csr_io_rocc_iptw_req_ready;
+ wire csr_io_rocc_iptw_req_valid;
+ wire [26:0] csr_io_rocc_iptw_req_bits_addr;
+ wire [1:0] csr_io_rocc_iptw_req_bits_prv;
+ wire csr_io_rocc_iptw_req_bits_store;
+ wire csr_io_rocc_iptw_req_bits_fetch;
+ wire csr_io_rocc_iptw_resp_valid;
+ wire csr_io_rocc_iptw_resp_bits_error;
+ wire [19:0] csr_io_rocc_iptw_resp_bits_pte_ppn;
+ wire [2:0] csr_io_rocc_iptw_resp_bits_pte_reserved_for_software;
+ wire csr_io_rocc_iptw_resp_bits_pte_d;
+ wire csr_io_rocc_iptw_resp_bits_pte_r;
+ wire [3:0] csr_io_rocc_iptw_resp_bits_pte_typ;
+ wire csr_io_rocc_iptw_resp_bits_pte_v;
+ wire csr_io_rocc_iptw_status_sd;
+ wire [30:0] csr_io_rocc_iptw_status_zero2;
+ wire csr_io_rocc_iptw_status_sd_rv32;
+ wire [8:0] csr_io_rocc_iptw_status_zero1;
+ wire [4:0] csr_io_rocc_iptw_status_vm;
+ wire csr_io_rocc_iptw_status_mprv;
+ wire [1:0] csr_io_rocc_iptw_status_xs;
+ wire [1:0] csr_io_rocc_iptw_status_fs;
+ wire [1:0] csr_io_rocc_iptw_status_prv3;
+ wire csr_io_rocc_iptw_status_ie3;
+ wire [1:0] csr_io_rocc_iptw_status_prv2;
+ wire csr_io_rocc_iptw_status_ie2;
+ wire [1:0] csr_io_rocc_iptw_status_prv1;
+ wire csr_io_rocc_iptw_status_ie1;
+ wire [1:0] csr_io_rocc_iptw_status_prv;
+ wire csr_io_rocc_iptw_status_ie;
+ wire csr_io_rocc_iptw_invalidate;
+ wire csr_io_rocc_dptw_req_ready;
+ wire csr_io_rocc_dptw_req_valid;
+ wire [26:0] csr_io_rocc_dptw_req_bits_addr;
+ wire [1:0] csr_io_rocc_dptw_req_bits_prv;
+ wire csr_io_rocc_dptw_req_bits_store;
+ wire csr_io_rocc_dptw_req_bits_fetch;
+ wire csr_io_rocc_dptw_resp_valid;
+ wire csr_io_rocc_dptw_resp_bits_error;
+ wire [19:0] csr_io_rocc_dptw_resp_bits_pte_ppn;
+ wire [2:0] csr_io_rocc_dptw_resp_bits_pte_reserved_for_software;
+ wire csr_io_rocc_dptw_resp_bits_pte_d;
+ wire csr_io_rocc_dptw_resp_bits_pte_r;
+ wire [3:0] csr_io_rocc_dptw_resp_bits_pte_typ;
+ wire csr_io_rocc_dptw_resp_bits_pte_v;
+ wire csr_io_rocc_dptw_status_sd;
+ wire [30:0] csr_io_rocc_dptw_status_zero2;
+ wire csr_io_rocc_dptw_status_sd_rv32;
+ wire [8:0] csr_io_rocc_dptw_status_zero1;
+ wire [4:0] csr_io_rocc_dptw_status_vm;
+ wire csr_io_rocc_dptw_status_mprv;
+ wire [1:0] csr_io_rocc_dptw_status_xs;
+ wire [1:0] csr_io_rocc_dptw_status_fs;
+ wire [1:0] csr_io_rocc_dptw_status_prv3;
+ wire csr_io_rocc_dptw_status_ie3;
+ wire [1:0] csr_io_rocc_dptw_status_prv2;
+ wire csr_io_rocc_dptw_status_ie2;
+ wire [1:0] csr_io_rocc_dptw_status_prv1;
+ wire csr_io_rocc_dptw_status_ie1;
+ wire [1:0] csr_io_rocc_dptw_status_prv;
+ wire csr_io_rocc_dptw_status_ie;
+ wire csr_io_rocc_dptw_invalidate;
+ wire csr_io_rocc_pptw_req_ready;
+ wire csr_io_rocc_pptw_req_valid;
+ wire [26:0] csr_io_rocc_pptw_req_bits_addr;
+ wire [1:0] csr_io_rocc_pptw_req_bits_prv;
+ wire csr_io_rocc_pptw_req_bits_store;
+ wire csr_io_rocc_pptw_req_bits_fetch;
+ wire csr_io_rocc_pptw_resp_valid;
+ wire csr_io_rocc_pptw_resp_bits_error;
+ wire [19:0] csr_io_rocc_pptw_resp_bits_pte_ppn;
+ wire [2:0] csr_io_rocc_pptw_resp_bits_pte_reserved_for_software;
+ wire csr_io_rocc_pptw_resp_bits_pte_d;
+ wire csr_io_rocc_pptw_resp_bits_pte_r;
+ wire [3:0] csr_io_rocc_pptw_resp_bits_pte_typ;
+ wire csr_io_rocc_pptw_resp_bits_pte_v;
+ wire csr_io_rocc_pptw_status_sd;
+ wire [30:0] csr_io_rocc_pptw_status_zero2;
+ wire csr_io_rocc_pptw_status_sd_rv32;
+ wire [8:0] csr_io_rocc_pptw_status_zero1;
+ wire [4:0] csr_io_rocc_pptw_status_vm;
+ wire csr_io_rocc_pptw_status_mprv;
+ wire [1:0] csr_io_rocc_pptw_status_xs;
+ wire [1:0] csr_io_rocc_pptw_status_fs;
+ wire [1:0] csr_io_rocc_pptw_status_prv3;
+ wire csr_io_rocc_pptw_status_ie3;
+ wire [1:0] csr_io_rocc_pptw_status_prv2;
+ wire csr_io_rocc_pptw_status_ie2;
+ wire [1:0] csr_io_rocc_pptw_status_prv1;
+ wire csr_io_rocc_pptw_status_ie1;
+ wire [1:0] csr_io_rocc_pptw_status_prv;
+ wire csr_io_rocc_pptw_status_ie;
+ wire csr_io_rocc_pptw_invalidate;
+ wire csr_io_rocc_fpu_req_ready;
+ wire csr_io_rocc_fpu_req_valid;
+ wire [4:0] csr_io_rocc_fpu_req_bits_cmd;
+ wire csr_io_rocc_fpu_req_bits_ldst;
+ wire csr_io_rocc_fpu_req_bits_wen;
+ wire csr_io_rocc_fpu_req_bits_ren1;
+ wire csr_io_rocc_fpu_req_bits_ren2;
+ wire csr_io_rocc_fpu_req_bits_ren3;
+ wire csr_io_rocc_fpu_req_bits_swap12;
+ wire csr_io_rocc_fpu_req_bits_swap23;
+ wire csr_io_rocc_fpu_req_bits_single;
+ wire csr_io_rocc_fpu_req_bits_fromint;
+ wire csr_io_rocc_fpu_req_bits_toint;
+ wire csr_io_rocc_fpu_req_bits_fastpipe;
+ wire csr_io_rocc_fpu_req_bits_fma;
+ wire csr_io_rocc_fpu_req_bits_div;
+ wire csr_io_rocc_fpu_req_bits_sqrt;
+ wire csr_io_rocc_fpu_req_bits_round;
+ wire csr_io_rocc_fpu_req_bits_wflags;
+ wire [2:0] csr_io_rocc_fpu_req_bits_rm;
+ wire [1:0] csr_io_rocc_fpu_req_bits_typ;
+ wire [64:0] csr_io_rocc_fpu_req_bits_in1;
+ wire [64:0] csr_io_rocc_fpu_req_bits_in2;
+ wire [64:0] csr_io_rocc_fpu_req_bits_in3;
+ wire csr_io_rocc_fpu_resp_ready;
+ wire csr_io_rocc_fpu_resp_valid;
+ wire [64:0] csr_io_rocc_fpu_resp_bits_data;
+ wire [4:0] csr_io_rocc_fpu_resp_bits_exc;
+ wire csr_io_rocc_exception;
+ wire csr_io_rocc_dma_req_ready;
+ wire csr_io_rocc_dma_req_valid;
+ wire [1:0] csr_io_rocc_dma_req_bits_client_xact_id;
+ wire [2:0] csr_io_rocc_dma_req_bits_cmd;
+ wire [31:0] csr_io_rocc_dma_req_bits_source;
+ wire [31:0] csr_io_rocc_dma_req_bits_dest;
+ wire [31:0] csr_io_rocc_dma_req_bits_length;
+ wire [1:0] csr_io_rocc_dma_req_bits_size;
+ wire csr_io_rocc_dma_resp_ready;
+ wire csr_io_rocc_dma_resp_valid;
+ wire [1:0] csr_io_rocc_dma_resp_bits_client_xact_id;
+ wire [1:0] csr_io_rocc_dma_resp_bits_status;
+ wire csr_io_interrupt;
+ wire [63:0] csr_io_interrupt_cause;
+ wire id_csr_en;
+ wire id_system_insn;
+ wire T_6794;
+ wire T_6795;
+ wire T_6796;
+ wire T_6798;
+ wire id_csr_ren;
+ wire [2:0] id_csr;
+ wire [11:0] id_csr_addr;
+ wire T_6803;
+ wire T_6804;
+ wire [11:0] T_6863;
+ wire T_6865;
+ wire T_6867;
+ wire T_6868;
+ wire T_6870;
+ wire T_6871;
+ wire id_csr_flush;
+ wire T_6874;
+ wire T_6876;
+ wire T_6878;
+ wire T_6879;
+ wire T_6880;
+ wire T_6882;
+ wire T_6884;
+ wire T_6885;
+ wire id_illegal_insn;
+ wire id_amo_aq;
+ wire id_amo_rl;
+ wire T_6889;
+ wire id_fence_next;
+ wire T_6892;
+ wire id_mem_busy;
+ wire T_6895;
+ wire T_6896;
+ wire T_6897;
+ wire T_6898;
+ wire T_6899;
+ wire T_6900;
+ wire id_rocc_busy;
+ wire T_6902;
+ wire T_6903;
+ wire T_6904;
+ wire T_6905;
+ wire T_6906;
+ wire T_6907;
+ wire T_6908;
+ wire T_6909;
+ wire T_6910;
+ wire T_6911;
+ wire id_do_fence;
+ wire T_6915;
+ wire id_xcpt;
+ wire [1:0] T_6917;
+ wire [63:0] id_cause;
+ wire [4:0] ex_waddr;
+ wire [4:0] mem_waddr;
+ wire [4:0] wb_waddr;
+ wire T_6925;
+ wire T_6926;
+ wire T_6928;
+ wire T_6929;
+ wire T_6930;
+ wire T_6931;
+ wire T_6932;
+ wire T_6933;
+ wire T_6934;
+ wire T_6935;
+ wire T_6936;
+ wire T_6937;
+ wire T_6938;
+ wire T_6939;
+ wire T_6940;
+ wire T_6941;
+ wire T_6942;
+ wire T_6943;
+ wire T_6944;
+ wire T_6945;
+ wire T_6946;
+ wire [63:0] bypass_mux_0;
+ wire [63:0] bypass_mux_1;
+ wire [63:0] bypass_mux_2;
+ wire [63:0] bypass_mux_3;
+ reg ex_reg_rs_bypass_0;
+ reg ex_reg_rs_bypass_1;
+ reg [1:0] ex_reg_rs_lsb_0;
+ reg [1:0] ex_reg_rs_lsb_1;
+ reg [61:0] ex_reg_rs_msb_0;
+ reg [61:0] ex_reg_rs_msb_1;
+ wire [63:0] T_6991;
+ wire [63:0] GEN_0;
+ wire [63:0] T_6992;
+ wire [63:0] T_6994;
+ wire [63:0] GEN_1;
+ wire [63:0] T_6995;
+ wire T_6996;
+ wire T_6998;
+ wire T_6999;
+ wire GEN_2;
+ wire T_7000;
+ wire T_7001;
+ wire [10:0] T_7002;
+ wire [10:0] T_7003;
+ wire [10:0] T_7004;
+ wire T_7005;
+ wire T_7006;
+ wire T_7007;
+ wire [7:0] T_7008;
+ wire [7:0] T_7009;
+ wire [7:0] T_7010;
+ wire T_7011;
+ wire T_7012;
+ wire T_7013;
+ wire T_7015;
+ wire T_7016;
+ wire T_7017;
+ wire T_7018;
+ wire T_7019;
+ wire T_7020;
+ wire T_7021;
+ wire T_7022;
+ wire GEN_3;
+ wire T_7023;
+ wire T_7024;
+ wire T_7025;
+ wire T_7026;
+ wire [5:0] T_7028;
+ wire [5:0] T_7029;
+ wire T_7030;
+ wire T_7032;
+ wire T_7033;
+ wire T_7034;
+ wire [3:0] T_7035;
+ wire T_7036;
+ wire [3:0] T_7037;
+ wire [3:0] T_7038;
+ wire [3:0] T_7039;
+ wire [3:0] T_7040;
+ wire [3:0] T_7041;
+ wire T_7042;
+ wire T_7043;
+ wire T_7044;
+ wire T_7045;
+ wire T_7046;
+ wire T_7047;
+ wire T_7049;
+ wire T_7050;
+ wire T_7051;
+ wire T_7052;
+ wire T_7053;
+ wire T_7054;
+ wire T_7055;
+ wire [10:0] T_7056;
+ wire [7:0] T_7057;
+ wire [18:0] T_7058;
+ wire [19:0] T_7059;
+ wire T_7060;
+ wire [6:0] T_7061;
+ wire [4:0] T_7062;
+ wire [11:0] T_7063;
+ wire [31:0] T_7064;
+ wire [31:0] ex_imm;
+ wire [63:0] T_7067;
+ wire [39:0] T_7068;
+ wire T_7069;
+ wire GEN_4;
+ wire [39:0] T_7070;
+ wire T_7071;
+ wire [63:0] ex_op1;
+ wire [63:0] T_7074;
+ wire T_7076;
+ wire [3:0] GEN_5;
+ wire GEN_6;
+ wire [3:0] T_7077;
+ wire T_7078;
+ wire [31:0] T_7079;
+ wire T_7080;
+ wire [63:0] ex_op2;
+ wire alu_clk;
+ wire alu_reset;
+ wire alu_io_dw;
+ wire [3:0] alu_io_fn;
+ wire [63:0] alu_io_in2;
+ wire [63:0] alu_io_in1;
+ wire [63:0] alu_io_out;
+ wire [63:0] alu_io_adder_out;
+ wire alu_io_cmp_out;
+ wire [63:0] T_7083;
+ wire [63:0] T_7084;
+ wire div_clk;
+ wire div_reset;
+ wire div_io_req_ready;
+ wire div_io_req_valid;
+ wire [3:0] div_io_req_bits_fn;
+ wire div_io_req_bits_dw;
+ wire [63:0] div_io_req_bits_in1;
+ wire [63:0] div_io_req_bits_in2;
+ wire [4:0] div_io_req_bits_tag;
+ wire div_io_kill;
+ wire div_io_resp_ready;
+ wire div_io_resp_valid;
+ wire [63:0] div_io_resp_bits_data;
+ wire [4:0] div_io_resp_bits_tag;
+ wire T_7086;
+ wire T_7088;
+ wire T_7090;
+ wire T_7091;
+ wire T_7093;
+ wire T_7094;
+ wire T_7095;
+ wire T_7097;
+ wire T_7098;
+ wire T_7099;
+ wire T_7100;
+ wire T_7101;
+ wire [1:0] T_7106;
+ wire [1:0] T_7107;
+ wire [1:0] T_7108;
+ wire T_7110;
+ wire T_7111;
+ wire [1:0] T_7112;
+ wire [61:0] T_7113;
+ wire T_7114;
+ wire T_7115;
+ wire T_7116;
+ wire [1:0] T_7121;
+ wire [1:0] T_7122;
+ wire [1:0] T_7123;
+ wire T_7125;
+ wire T_7126;
+ wire [1:0] T_7127;
+ wire [61:0] T_7128;
+ wire T_7130;
+ wire T_7131;
+ wire T_7133;
+ wire wb_dcache_miss;
+ wire T_7136;
+ wire T_7137;
+ wire T_7139;
+ wire T_7140;
+ wire replay_ex_structural;
+ wire replay_ex_load_use;
+ wire T_7143;
+ wire replay_ex;
+ wire T_7145;
+ wire T_7147;
+ wire ctrl_killx;
+ wire T_7149;
+ wire [2:0] T_7151_0;
+ wire [2:0] T_7151_1;
+ wire [2:0] T_7151_2;
+ wire [2:0] T_7151_3;
+ wire T_7157;
+ wire T_7158;
+ wire T_7159;
+ wire T_7160;
+ wire T_7162;
+ wire T_7163;
+ wire T_7164;
+ wire T_7165;
+ wire ex_slow_bypass;
+ wire T_7167;
+ wire T_7168;
+ wire ex_xcpt;
+ wire [63:0] ex_cause;
+ wire mem_br_taken;
+ wire [39:0] T_7173;
+ wire T_7174;
+ wire T_7175;
+ wire T_7177;
+ wire T_7178;
+ wire GEN_7;
+ wire T_7179;
+ wire T_7180;
+ wire [10:0] T_7181;
+ wire [10:0] T_7182;
+ wire [10:0] T_7183;
+ wire T_7184;
+ wire T_7185;
+ wire T_7186;
+ wire [7:0] T_7187;
+ wire [7:0] T_7188;
+ wire [7:0] T_7189;
+ wire T_7190;
+ wire T_7191;
+ wire T_7192;
+ wire T_7194;
+ wire T_7195;
+ wire T_7196;
+ wire T_7197;
+ wire T_7198;
+ wire T_7199;
+ wire T_7200;
+ wire T_7201;
+ wire GEN_8;
+ wire T_7202;
+ wire T_7203;
+ wire T_7204;
+ wire T_7205;
+ wire [5:0] T_7207;
+ wire [5:0] T_7208;
+ wire T_7209;
+ wire T_7211;
+ wire T_7212;
+ wire T_7213;
+ wire [3:0] T_7214;
+ wire T_7215;
+ wire [3:0] T_7216;
+ wire [3:0] T_7217;
+ wire [3:0] T_7218;
+ wire [3:0] T_7219;
+ wire [3:0] T_7220;
+ wire T_7221;
+ wire T_7222;
+ wire T_7223;
+ wire T_7224;
+ wire T_7225;
+ wire T_7226;
+ wire T_7228;
+ wire T_7229;
+ wire T_7230;
+ wire T_7231;
+ wire T_7232;
+ wire T_7233;
+ wire T_7234;
+ wire [10:0] T_7235;
+ wire [7:0] T_7236;
+ wire [18:0] T_7237;
+ wire [19:0] T_7238;
+ wire T_7239;
+ wire [6:0] T_7240;
+ wire [4:0] T_7241;
+ wire [11:0] T_7242;
+ wire [31:0] T_7243;
+ wire [31:0] T_7244;
+ wire T_7245;
+ wire T_7247;
+ wire T_7248;
+ wire GEN_9;
+ wire T_7249;
+ wire T_7250;
+ wire [10:0] T_7251;
+ wire [10:0] T_7252;
+ wire [10:0] T_7253;
+ wire T_7254;
+ wire T_7255;
+ wire T_7256;
+ wire [7:0] T_7257;
+ wire [7:0] T_7258;
+ wire [7:0] T_7259;
+ wire T_7260;
+ wire T_7261;
+ wire T_7262;
+ wire T_7264;
+ wire T_7265;
+ wire T_7266;
+ wire T_7267;
+ wire T_7268;
+ wire T_7269;
+ wire T_7270;
+ wire T_7271;
+ wire GEN_10;
+ wire T_7272;
+ wire T_7273;
+ wire T_7274;
+ wire T_7275;
+ wire [5:0] T_7277;
+ wire [5:0] T_7278;
+ wire T_7279;
+ wire T_7281;
+ wire T_7282;
+ wire T_7283;
+ wire [3:0] T_7284;
+ wire T_7285;
+ wire [3:0] T_7286;
+ wire [3:0] T_7287;
+ wire [3:0] T_7288;
+ wire [3:0] T_7289;
+ wire [3:0] T_7290;
+ wire T_7291;
+ wire T_7292;
+ wire T_7293;
+ wire T_7294;
+ wire T_7295;
+ wire T_7296;
+ wire T_7298;
+ wire T_7299;
+ wire T_7300;
+ wire T_7301;
+ wire T_7302;
+ wire T_7303;
+ wire T_7304;
+ wire [10:0] T_7305;
+ wire [7:0] T_7306;
+ wire [18:0] T_7307;
+ wire [19:0] T_7308;
+ wire T_7309;
+ wire [6:0] T_7310;
+ wire [4:0] T_7311;
+ wire [11:0] T_7312;
+ wire [31:0] T_7313;
+ wire [31:0] T_7314;
+ wire [3:0] GEN_11;
+ wire [31:0] T_7316;
+ wire [31:0] T_7317;
+ wire [40:0] T_7318;
+ wire [39:0] T_7319;
+ wire [39:0] mem_br_target;
+ wire [63:0] T_7321;
+ wire [63:0] T_7322;
+ wire [63:0] mem_int_wdata;
+ wire [25:0] T_7324;
+ wire [1:0] T_7325;
+ wire T_7327;
+ wire T_7329;
+ wire T_7330;
+ wire T_7332;
+ wire [25:0] T_7333;
+ wire GEN_12;
+ wire T_7335;
+ wire [25:0] T_7336;
+ wire [1:0] GEN_13;
+ wire T_7338;
+ wire T_7339;
+ wire [1:0] T_7340;
+ wire GEN_14;
+ wire T_7342;
+ wire T_7343;
+ wire T_7344;
+ wire T_7345;
+ wire [38:0] T_7346;
+ wire [39:0] T_7347;
+ wire [39:0] T_7348;
+ wire [39:0] T_7349;
+ wire [1:0] GEN_15;
+ wire [39:0] T_7351;
+ wire [39:0] T_7352;
+ wire [39:0] mem_npc;
+ wire T_7354;
+ wire T_7356;
+ wire mem_wrong_npc;
+ wire mem_npc_misaligned;
+ wire T_7359;
+ wire T_7360;
+ wire T_7361;
+ wire mem_misprediction;
+ wire T_7363;
+ wire want_take_pc_mem;
+ wire T_7366;
+ wire T_7367;
+ wire T_7369;
+ wire T_7371;
+ wire T_7372;
+ wire T_7374;
+ wire T_7375;
+ wire T_7377;
+ wire T_7378;
+ wire T_7379;
+ wire T_7380;
+ wire T_7381;
+ wire T_7382;
+ wire T_7383;
+ wire T_7385;
+ wire T_7386;
+ wire T_7388;
+ wire T_7389;
+ wire T_7391;
+ wire T_7392;
+ wire T_7394;
+ wire T_7395;
+ wire T_7397;
+ wire T_7398;
+ wire T_7399;
+ wire T_7400;
+ wire mem_xcpt;
+ wire [2:0] T_7402;
+ wire [2:0] T_7403;
+ wire [2:0] T_7404;
+ wire [2:0] T_7405;
+ wire [63:0] mem_cause;
+ wire T_7407;
+ wire dcache_kill_mem;
+ wire T_7409;
+ wire fpu_kill_mem;
+ wire T_7411;
+ wire replay_mem;
+ wire T_7413;
+ wire T_7414;
+ wire T_7416;
+ wire killm_common;
+ wire T_7418;
+ reg T_7419;
+ wire T_7420;
+ wire T_7421;
+ wire ctrl_killm;
+ wire T_7424;
+ wire T_7426;
+ wire T_7427;
+ wire T_7429;
+ wire T_7430;
+ wire T_7431;
+ wire T_7432;
+ wire T_7433;
+ wire [63:0] T_7434;
+ wire T_7435;
+ wire wb_set_sboard;
+ wire replay_wb_common;
+ wire T_7438;
+ wire T_7440;
+ wire wb_rocc_val;
+ wire T_7442;
+ wire T_7444;
+ wire T_7445;
+ wire replay_wb;
+ wire wb_xcpt;
+ wire T_7448;
+ wire T_7449;
+ wire T_7451;
+ wire T_7453;
+ wire T_7454;
+ wire dmem_resp_xpu;
+ wire T_7457;
+ wire dmem_resp_fpu;
+ wire [4:0] dmem_resp_waddr;
+ wire dmem_resp_valid;
+ wire dmem_resp_replay;
+ wire T_7462;
+ wire T_7464;
+ wire [63:0] ll_wdata;
+ wire [4:0] ll_waddr;
+ wire T_7467;
+ wire ll_wen;
+ wire T_7469;
+ wire T_7473;
+ wire T_7474;
+ wire T_7476;
+ wire wb_valid;
+ wire wb_wen;
+ wire rf_wen;
+ wire [4:0] rf_waddr;
+ wire T_7481;
+ wire T_7482;
+ wire [63:0] T_7483;
+ wire [63:0] T_7484;
+ wire [63:0] rf_wdata;
+ wire T_7487;
+ wire [4:0] T_7488;
+ wire [4:0] T_7489;
+ wire T_7491;
+ wire T_7492;
+ wire [11:0] T_7509;
+ wire [2:0] T_7510;
+ wire T_7512;
+ wire T_7513;
+ wire T_7515;
+ wire T_7516;
+ wire T_7518;
+ wire T_7519;
+ reg [31:0] T_7521;
+ wire [31:0] T_7524;
+ wire [31:0] T_7526;
+ wire [31:0] T_7527;
+ wire [31:0] T_7528;
+ wire T_7529;
+ wire [31:0] T_7530;
+ wire T_7531;
+ wire T_7532;
+ wire [31:0] T_7533;
+ wire T_7534;
+ wire T_7535;
+ wire [31:0] T_7536;
+ wire T_7537;
+ wire T_7538;
+ wire T_7539;
+ wire id_sboard_hazard;
+ wire T_7541;
+ wire [31:0] T_7543;
+ wire [31:0] T_7545;
+ wire [31:0] T_7546;
+ wire T_7547;
+ wire T_7548;
+ wire T_7549;
+ wire T_7550;
+ wire T_7551;
+ wire T_7552;
+ wire ex_cannot_bypass;
+ wire T_7554;
+ wire T_7555;
+ wire T_7556;
+ wire T_7557;
+ wire T_7558;
+ wire T_7559;
+ wire T_7560;
+ wire T_7561;
+ wire data_hazard_ex;
+ wire T_7563;
+ wire T_7564;
+ wire T_7565;
+ wire T_7566;
+ wire T_7567;
+ wire T_7568;
+ wire T_7569;
+ wire T_7570;
+ wire T_7571;
+ wire T_7572;
+ wire T_7573;
+ wire fp_data_hazard_ex;
+ wire T_7575;
+ wire T_7576;
+ wire id_ex_hazard;
+ wire mem_mem_cmd_bh;
+ wire T_7580;
+ wire T_7581;
+ wire T_7582;
+ wire T_7583;
+ wire T_7584;
+ wire mem_cannot_bypass;
+ wire T_7586;
+ wire T_7587;
+ wire T_7588;
+ wire T_7589;
+ wire T_7590;
+ wire T_7591;
+ wire T_7592;
+ wire T_7593;
+ wire data_hazard_mem;
+ wire T_7595;
+ wire T_7596;
+ wire T_7597;
+ wire T_7598;
+ wire T_7599;
+ wire T_7600;
+ wire T_7601;
+ wire T_7602;
+ wire T_7603;
+ wire T_7604;
+ wire T_7605;
+ wire fp_data_hazard_mem;
+ wire T_7607;
+ wire T_7608;
+ wire id_mem_hazard;
+ wire T_7610;
+ wire T_7611;
+ wire T_7612;
+ wire T_7613;
+ wire T_7614;
+ wire T_7615;
+ wire T_7616;
+ wire T_7617;
+ wire T_7618;
+ wire T_7619;
+ wire data_hazard_wb;
+ wire T_7621;
+ wire T_7622;
+ wire T_7623;
+ wire T_7624;
+ wire T_7625;
+ wire T_7626;
+ wire T_7627;
+ wire T_7628;
+ wire T_7629;
+ wire T_7630;
+ wire T_7631;
+ wire fp_data_hazard_wb;
+ wire T_7633;
+ wire T_7634;
+ wire id_wb_hazard;
+ reg [31:0] T_7637;
+ wire T_7639;
+ wire T_7640;
+ wire T_7641;
+ wire [31:0] T_7643;
+ wire [31:0] T_7645;
+ wire [31:0] T_7646;
+ wire T_7647;
+ wire T_7648;
+ wire [31:0] T_7650;
+ wire [31:0] T_7652;
+ wire [31:0] T_7653;
+ wire [31:0] T_7654;
+ wire T_7655;
+ wire [31:0] T_7657;
+ wire [31:0] T_7659;
+ wire [31:0] T_7660;
+ wire [31:0] T_7661;
+ wire T_7662;
+ wire T_7664;
+ wire T_7665;
+ wire [31:0] T_7666;
+ wire T_7667;
+ wire T_7668;
+ wire [31:0] T_7669;
+ wire T_7670;
+ wire T_7671;
+ wire [31:0] T_7672;
+ wire T_7673;
+ wire T_7674;
+ wire [31:0] T_7675;
+ wire T_7676;
+ wire T_7677;
+ wire T_7678;
+ wire T_7679;
+ wire T_7680;
+ wire id_stall_fpu;
+ wire T_7682;
+ wire T_7683;
+ wire T_7684;
+ wire T_7685;
+ wire T_7686;
+ wire T_7688;
+ wire T_7689;
+ wire T_7690;
+ wire T_7692;
+ wire T_7693;
+ wire T_7695;
+ wire T_7696;
+ wire T_7697;
+ wire T_7698;
+ wire ctrl_stalld;
+ wire T_7701;
+ wire T_7702;
+ wire T_7703;
+ wire T_7704;
+ wire T_7705;
+ wire [39:0] T_7706;
+ wire [39:0] T_7707;
+ wire T_7708;
+ wire T_7710;
+ wire T_7711;
+ wire T_7713;
+ wire T_7714;
+ wire T_7715;
+ wire T_7716;
+ wire T_7717;
+ wire T_7718;
+ wire T_7719;
+ wire T_7721;
+ wire T_7722;
+ wire T_7723;
+ wire [4:0] T_7724;
+ wire [4:0] T_7727;
+ wire T_7728;
+ wire T_7729;
+ wire T_7730;
+ wire T_7732;
+ wire T_7733;
+ wire T_7734;
+ wire T_7736;
+ wire T_7737;
+ wire T_7739;
+ wire T_7740;
+ wire T_7741;
+ wire T_7742;
+ wire T_7744;
+ wire T_7745;
+ wire T_7746;
+ wire T_7747;
+ wire T_7748;
+ wire [25:0] T_7750;
+ wire [1:0] T_7751;
+ wire T_7753;
+ wire T_7755;
+ wire T_7756;
+ wire T_7758;
+ wire [25:0] T_7759;
+ wire GEN_16;
+ wire T_7761;
+ wire [25:0] T_7762;
+ wire [1:0] GEN_17;
+ wire T_7764;
+ wire T_7765;
+ wire [1:0] T_7766;
+ wire GEN_18;
+ wire T_7768;
+ wire T_7769;
+ wire T_7770;
+ wire T_7771;
+ wire [38:0] T_7772;
+ wire [39:0] T_7773;
+ wire [5:0] T_7774;
+ wire [63:0] T_7775;
+ wire T_7777;
+ wire T_7778;
+ wire T_7780;
+ wire [6:0] T_7799_funct;
+ wire [4:0] T_7799_rs2;
+ wire [4:0] T_7799_rs1;
+ wire T_7799_xd;
+ wire T_7799_xs1;
+ wire T_7799_xs2;
+ wire [4:0] T_7799_rd;
+ wire [6:0] T_7799_opcode;
+ wire [6:0] T_7808;
+ wire [4:0] T_7809;
+ wire T_7810;
+ wire T_7811;
+ wire T_7812;
+ wire [4:0] T_7813;
+ wire [4:0] T_7814;
+ wire [6:0] T_7815;
+ wire [32:0] T_7816;
+ wire [4:0] T_7818;
+ wire [4:0] T_7819;
+ reg [63:0] T_7820;
+ reg [63:0] T_7821;
+ wire [4:0] T_7822;
+ reg [63:0] T_7823;
+ reg [63:0] T_7824;
+ wire T_7826;
+ wire GEN_19;
+ wire GEN_20;
+ wire GEN_21;
+ wire GEN_22;
+ wire GEN_23;
+ wire GEN_24;
+ reg GEN_25;
+ reg GEN_26;
+ reg [4:0] GEN_27;
+ reg GEN_28;
+ reg GEN_29;
+ reg GEN_30;
+ reg GEN_31;
+ reg GEN_32;
+ reg GEN_33;
+ reg GEN_34;
+ reg GEN_35;
+ reg GEN_36;
+ reg GEN_37;
+ reg GEN_38;
+ reg GEN_39;
+ reg GEN_40;
+ reg GEN_41;
+ reg GEN_42;
+ reg GEN_43;
+ reg [2:0] GEN_44;
+ reg [1:0] GEN_45;
+ reg [64:0] GEN_46;
+ reg [64:0] GEN_47;
+ reg [64:0] GEN_48;
+ reg GEN_49;
+ CSRFile csr (
+ .clk(csr_clk),
+ .reset(csr_reset),
+ .io_host_reset(csr_io_host_reset),
+ .io_host_id(csr_io_host_id),
+ .io_host_csr_req_ready(csr_io_host_csr_req_ready),
+ .io_host_csr_req_valid(csr_io_host_csr_req_valid),
+ .io_host_csr_req_bits_rw(csr_io_host_csr_req_bits_rw),
+ .io_host_csr_req_bits_addr(csr_io_host_csr_req_bits_addr),
+ .io_host_csr_req_bits_data(csr_io_host_csr_req_bits_data),
+ .io_host_csr_resp_ready(csr_io_host_csr_resp_ready),
+ .io_host_csr_resp_valid(csr_io_host_csr_resp_valid),
+ .io_host_csr_resp_bits(csr_io_host_csr_resp_bits),
+ .io_host_debug_stats_csr(csr_io_host_debug_stats_csr),
+ .io_rw_addr(csr_io_rw_addr),
+ .io_rw_cmd(csr_io_rw_cmd),
+ .io_rw_rdata(csr_io_rw_rdata),
+ .io_rw_wdata(csr_io_rw_wdata),
+ .io_csr_stall(csr_io_csr_stall),
+ .io_csr_xcpt(csr_io_csr_xcpt),
+ .io_eret(csr_io_eret),
+ .io_status_sd(csr_io_status_sd),
+ .io_status_zero2(csr_io_status_zero2),
+ .io_status_sd_rv32(csr_io_status_sd_rv32),
+ .io_status_zero1(csr_io_status_zero1),
+ .io_status_vm(csr_io_status_vm),
+ .io_status_mprv(csr_io_status_mprv),
+ .io_status_xs(csr_io_status_xs),
+ .io_status_fs(csr_io_status_fs),
+ .io_status_prv3(csr_io_status_prv3),
+ .io_status_ie3(csr_io_status_ie3),
+ .io_status_prv2(csr_io_status_prv2),
+ .io_status_ie2(csr_io_status_ie2),
+ .io_status_prv1(csr_io_status_prv1),
+ .io_status_ie1(csr_io_status_ie1),
+ .io_status_prv(csr_io_status_prv),
+ .io_status_ie(csr_io_status_ie),
+ .io_ptbr(csr_io_ptbr),
+ .io_evec(csr_io_evec),
+ .io_exception(csr_io_exception),
+ .io_retire(csr_io_retire),
+ .io_uarch_counters_0(csr_io_uarch_counters_0),
+ .io_uarch_counters_1(csr_io_uarch_counters_1),
+ .io_uarch_counters_2(csr_io_uarch_counters_2),
+ .io_uarch_counters_3(csr_io_uarch_counters_3),
+ .io_uarch_counters_4(csr_io_uarch_counters_4),
+ .io_uarch_counters_5(csr_io_uarch_counters_5),
+ .io_uarch_counters_6(csr_io_uarch_counters_6),
+ .io_uarch_counters_7(csr_io_uarch_counters_7),
+ .io_uarch_counters_8(csr_io_uarch_counters_8),
+ .io_uarch_counters_9(csr_io_uarch_counters_9),
+ .io_uarch_counters_10(csr_io_uarch_counters_10),
+ .io_uarch_counters_11(csr_io_uarch_counters_11),
+ .io_uarch_counters_12(csr_io_uarch_counters_12),
+ .io_uarch_counters_13(csr_io_uarch_counters_13),
+ .io_uarch_counters_14(csr_io_uarch_counters_14),
+ .io_uarch_counters_15(csr_io_uarch_counters_15),
+ .io_cause(csr_io_cause),
+ .io_pc(csr_io_pc),
+ .io_fatc(csr_io_fatc),
+ .io_time(csr_io_time),
+ .io_fcsr_rm(csr_io_fcsr_rm),
+ .io_fcsr_flags_valid(csr_io_fcsr_flags_valid),
+ .io_fcsr_flags_bits(csr_io_fcsr_flags_bits),
+ .io_rocc_cmd_ready(csr_io_rocc_cmd_ready),
+ .io_rocc_cmd_valid(csr_io_rocc_cmd_valid),
+ .io_rocc_cmd_bits_inst_funct(csr_io_rocc_cmd_bits_inst_funct),
+ .io_rocc_cmd_bits_inst_rs2(csr_io_rocc_cmd_bits_inst_rs2),
+ .io_rocc_cmd_bits_inst_rs1(csr_io_rocc_cmd_bits_inst_rs1),
+ .io_rocc_cmd_bits_inst_xd(csr_io_rocc_cmd_bits_inst_xd),
+ .io_rocc_cmd_bits_inst_xs1(csr_io_rocc_cmd_bits_inst_xs1),
+ .io_rocc_cmd_bits_inst_xs2(csr_io_rocc_cmd_bits_inst_xs2),
+ .io_rocc_cmd_bits_inst_rd(csr_io_rocc_cmd_bits_inst_rd),
+ .io_rocc_cmd_bits_inst_opcode(csr_io_rocc_cmd_bits_inst_opcode),
+ .io_rocc_cmd_bits_rs1(csr_io_rocc_cmd_bits_rs1),
+ .io_rocc_cmd_bits_rs2(csr_io_rocc_cmd_bits_rs2),
+ .io_rocc_resp_ready(csr_io_rocc_resp_ready),
+ .io_rocc_resp_valid(csr_io_rocc_resp_valid),
+ .io_rocc_resp_bits_rd(csr_io_rocc_resp_bits_rd),
+ .io_rocc_resp_bits_data(csr_io_rocc_resp_bits_data),
+ .io_rocc_mem_req_ready(csr_io_rocc_mem_req_ready),
+ .io_rocc_mem_req_valid(csr_io_rocc_mem_req_valid),
+ .io_rocc_mem_req_bits_addr(csr_io_rocc_mem_req_bits_addr),
+ .io_rocc_mem_req_bits_tag(csr_io_rocc_mem_req_bits_tag),
+ .io_rocc_mem_req_bits_cmd(csr_io_rocc_mem_req_bits_cmd),
+ .io_rocc_mem_req_bits_typ(csr_io_rocc_mem_req_bits_typ),
+ .io_rocc_mem_req_bits_kill(csr_io_rocc_mem_req_bits_kill),
+ .io_rocc_mem_req_bits_phys(csr_io_rocc_mem_req_bits_phys),
+ .io_rocc_mem_req_bits_data(csr_io_rocc_mem_req_bits_data),
+ .io_rocc_mem_resp_valid(csr_io_rocc_mem_resp_valid),
+ .io_rocc_mem_resp_bits_addr(csr_io_rocc_mem_resp_bits_addr),
+ .io_rocc_mem_resp_bits_tag(csr_io_rocc_mem_resp_bits_tag),
+ .io_rocc_mem_resp_bits_cmd(csr_io_rocc_mem_resp_bits_cmd),
+ .io_rocc_mem_resp_bits_typ(csr_io_rocc_mem_resp_bits_typ),
+ .io_rocc_mem_resp_bits_data(csr_io_rocc_mem_resp_bits_data),
+ .io_rocc_mem_resp_bits_nack(csr_io_rocc_mem_resp_bits_nack),
+ .io_rocc_mem_resp_bits_replay(csr_io_rocc_mem_resp_bits_replay),
+ .io_rocc_mem_resp_bits_has_data(csr_io_rocc_mem_resp_bits_has_data),
+ .io_rocc_mem_resp_bits_data_word_bypass(csr_io_rocc_mem_resp_bits_data_word_bypass),
+ .io_rocc_mem_resp_bits_store_data(csr_io_rocc_mem_resp_bits_store_data),
+ .io_rocc_mem_replay_next_valid(csr_io_rocc_mem_replay_next_valid),
+ .io_rocc_mem_replay_next_bits(csr_io_rocc_mem_replay_next_bits),
+ .io_rocc_mem_xcpt_ma_ld(csr_io_rocc_mem_xcpt_ma_ld),
+ .io_rocc_mem_xcpt_ma_st(csr_io_rocc_mem_xcpt_ma_st),
+ .io_rocc_mem_xcpt_pf_ld(csr_io_rocc_mem_xcpt_pf_ld),
+ .io_rocc_mem_xcpt_pf_st(csr_io_rocc_mem_xcpt_pf_st),
+ .io_rocc_mem_invalidate_lr(csr_io_rocc_mem_invalidate_lr),
+ .io_rocc_mem_ordered(csr_io_rocc_mem_ordered),
+ .io_rocc_busy(csr_io_rocc_busy),
+ .io_rocc_s(csr_io_rocc_s),
+ .io_rocc_interrupt(csr_io_rocc_interrupt),
+ .io_rocc_autl_acquire_ready(csr_io_rocc_autl_acquire_ready),
+ .io_rocc_autl_acquire_valid(csr_io_rocc_autl_acquire_valid),
+ .io_rocc_autl_acquire_bits_addr_block(csr_io_rocc_autl_acquire_bits_addr_block),
+ .io_rocc_autl_acquire_bits_client_xact_id(csr_io_rocc_autl_acquire_bits_client_xact_id),
+ .io_rocc_autl_acquire_bits_addr_beat(csr_io_rocc_autl_acquire_bits_addr_beat),
+ .io_rocc_autl_acquire_bits_is_builtin_type(csr_io_rocc_autl_acquire_bits_is_builtin_type),
+ .io_rocc_autl_acquire_bits_a_type(csr_io_rocc_autl_acquire_bits_a_type),
+ .io_rocc_autl_acquire_bits_union(csr_io_rocc_autl_acquire_bits_union),
+ .io_rocc_autl_acquire_bits_data(csr_io_rocc_autl_acquire_bits_data),
+ .io_rocc_autl_grant_ready(csr_io_rocc_autl_grant_ready),
+ .io_rocc_autl_grant_valid(csr_io_rocc_autl_grant_valid),
+ .io_rocc_autl_grant_bits_addr_beat(csr_io_rocc_autl_grant_bits_addr_beat),
+ .io_rocc_autl_grant_bits_client_xact_id(csr_io_rocc_autl_grant_bits_client_xact_id),
+ .io_rocc_autl_grant_bits_manager_xact_id(csr_io_rocc_autl_grant_bits_manager_xact_id),
+ .io_rocc_autl_grant_bits_is_builtin_type(csr_io_rocc_autl_grant_bits_is_builtin_type),
+ .io_rocc_autl_grant_bits_g_type(csr_io_rocc_autl_grant_bits_g_type),
+ .io_rocc_autl_grant_bits_data(csr_io_rocc_autl_grant_bits_data),
+ .io_rocc_iptw_req_ready(csr_io_rocc_iptw_req_ready),
+ .io_rocc_iptw_req_valid(csr_io_rocc_iptw_req_valid),
+ .io_rocc_iptw_req_bits_addr(csr_io_rocc_iptw_req_bits_addr),
+ .io_rocc_iptw_req_bits_prv(csr_io_rocc_iptw_req_bits_prv),
+ .io_rocc_iptw_req_bits_store(csr_io_rocc_iptw_req_bits_store),
+ .io_rocc_iptw_req_bits_fetch(csr_io_rocc_iptw_req_bits_fetch),
+ .io_rocc_iptw_resp_valid(csr_io_rocc_iptw_resp_valid),
+ .io_rocc_iptw_resp_bits_error(csr_io_rocc_iptw_resp_bits_error),
+ .io_rocc_iptw_resp_bits_pte_ppn(csr_io_rocc_iptw_resp_bits_pte_ppn),
+ .io_rocc_iptw_resp_bits_pte_reserved_for_software(csr_io_rocc_iptw_resp_bits_pte_reserved_for_software),
+ .io_rocc_iptw_resp_bits_pte_d(csr_io_rocc_iptw_resp_bits_pte_d),
+ .io_rocc_iptw_resp_bits_pte_r(csr_io_rocc_iptw_resp_bits_pte_r),
+ .io_rocc_iptw_resp_bits_pte_typ(csr_io_rocc_iptw_resp_bits_pte_typ),
+ .io_rocc_iptw_resp_bits_pte_v(csr_io_rocc_iptw_resp_bits_pte_v),
+ .io_rocc_iptw_status_sd(csr_io_rocc_iptw_status_sd),
+ .io_rocc_iptw_status_zero2(csr_io_rocc_iptw_status_zero2),
+ .io_rocc_iptw_status_sd_rv32(csr_io_rocc_iptw_status_sd_rv32),
+ .io_rocc_iptw_status_zero1(csr_io_rocc_iptw_status_zero1),
+ .io_rocc_iptw_status_vm(csr_io_rocc_iptw_status_vm),
+ .io_rocc_iptw_status_mprv(csr_io_rocc_iptw_status_mprv),
+ .io_rocc_iptw_status_xs(csr_io_rocc_iptw_status_xs),
+ .io_rocc_iptw_status_fs(csr_io_rocc_iptw_status_fs),
+ .io_rocc_iptw_status_prv3(csr_io_rocc_iptw_status_prv3),
+ .io_rocc_iptw_status_ie3(csr_io_rocc_iptw_status_ie3),
+ .io_rocc_iptw_status_prv2(csr_io_rocc_iptw_status_prv2),
+ .io_rocc_iptw_status_ie2(csr_io_rocc_iptw_status_ie2),
+ .io_rocc_iptw_status_prv1(csr_io_rocc_iptw_status_prv1),
+ .io_rocc_iptw_status_ie1(csr_io_rocc_iptw_status_ie1),
+ .io_rocc_iptw_status_prv(csr_io_rocc_iptw_status_prv),
+ .io_rocc_iptw_status_ie(csr_io_rocc_iptw_status_ie),
+ .io_rocc_iptw_invalidate(csr_io_rocc_iptw_invalidate),
+ .io_rocc_dptw_req_ready(csr_io_rocc_dptw_req_ready),
+ .io_rocc_dptw_req_valid(csr_io_rocc_dptw_req_valid),
+ .io_rocc_dptw_req_bits_addr(csr_io_rocc_dptw_req_bits_addr),
+ .io_rocc_dptw_req_bits_prv(csr_io_rocc_dptw_req_bits_prv),
+ .io_rocc_dptw_req_bits_store(csr_io_rocc_dptw_req_bits_store),
+ .io_rocc_dptw_req_bits_fetch(csr_io_rocc_dptw_req_bits_fetch),
+ .io_rocc_dptw_resp_valid(csr_io_rocc_dptw_resp_valid),
+ .io_rocc_dptw_resp_bits_error(csr_io_rocc_dptw_resp_bits_error),
+ .io_rocc_dptw_resp_bits_pte_ppn(csr_io_rocc_dptw_resp_bits_pte_ppn),
+ .io_rocc_dptw_resp_bits_pte_reserved_for_software(csr_io_rocc_dptw_resp_bits_pte_reserved_for_software),
+ .io_rocc_dptw_resp_bits_pte_d(csr_io_rocc_dptw_resp_bits_pte_d),
+ .io_rocc_dptw_resp_bits_pte_r(csr_io_rocc_dptw_resp_bits_pte_r),
+ .io_rocc_dptw_resp_bits_pte_typ(csr_io_rocc_dptw_resp_bits_pte_typ),
+ .io_rocc_dptw_resp_bits_pte_v(csr_io_rocc_dptw_resp_bits_pte_v),
+ .io_rocc_dptw_status_sd(csr_io_rocc_dptw_status_sd),
+ .io_rocc_dptw_status_zero2(csr_io_rocc_dptw_status_zero2),
+ .io_rocc_dptw_status_sd_rv32(csr_io_rocc_dptw_status_sd_rv32),
+ .io_rocc_dptw_status_zero1(csr_io_rocc_dptw_status_zero1),
+ .io_rocc_dptw_status_vm(csr_io_rocc_dptw_status_vm),
+ .io_rocc_dptw_status_mprv(csr_io_rocc_dptw_status_mprv),
+ .io_rocc_dptw_status_xs(csr_io_rocc_dptw_status_xs),
+ .io_rocc_dptw_status_fs(csr_io_rocc_dptw_status_fs),
+ .io_rocc_dptw_status_prv3(csr_io_rocc_dptw_status_prv3),
+ .io_rocc_dptw_status_ie3(csr_io_rocc_dptw_status_ie3),
+ .io_rocc_dptw_status_prv2(csr_io_rocc_dptw_status_prv2),
+ .io_rocc_dptw_status_ie2(csr_io_rocc_dptw_status_ie2),
+ .io_rocc_dptw_status_prv1(csr_io_rocc_dptw_status_prv1),
+ .io_rocc_dptw_status_ie1(csr_io_rocc_dptw_status_ie1),
+ .io_rocc_dptw_status_prv(csr_io_rocc_dptw_status_prv),
+ .io_rocc_dptw_status_ie(csr_io_rocc_dptw_status_ie),
+ .io_rocc_dptw_invalidate(csr_io_rocc_dptw_invalidate),
+ .io_rocc_pptw_req_ready(csr_io_rocc_pptw_req_ready),
+ .io_rocc_pptw_req_valid(csr_io_rocc_pptw_req_valid),
+ .io_rocc_pptw_req_bits_addr(csr_io_rocc_pptw_req_bits_addr),
+ .io_rocc_pptw_req_bits_prv(csr_io_rocc_pptw_req_bits_prv),
+ .io_rocc_pptw_req_bits_store(csr_io_rocc_pptw_req_bits_store),
+ .io_rocc_pptw_req_bits_fetch(csr_io_rocc_pptw_req_bits_fetch),
+ .io_rocc_pptw_resp_valid(csr_io_rocc_pptw_resp_valid),
+ .io_rocc_pptw_resp_bits_error(csr_io_rocc_pptw_resp_bits_error),
+ .io_rocc_pptw_resp_bits_pte_ppn(csr_io_rocc_pptw_resp_bits_pte_ppn),
+ .io_rocc_pptw_resp_bits_pte_reserved_for_software(csr_io_rocc_pptw_resp_bits_pte_reserved_for_software),
+ .io_rocc_pptw_resp_bits_pte_d(csr_io_rocc_pptw_resp_bits_pte_d),
+ .io_rocc_pptw_resp_bits_pte_r(csr_io_rocc_pptw_resp_bits_pte_r),
+ .io_rocc_pptw_resp_bits_pte_typ(csr_io_rocc_pptw_resp_bits_pte_typ),
+ .io_rocc_pptw_resp_bits_pte_v(csr_io_rocc_pptw_resp_bits_pte_v),
+ .io_rocc_pptw_status_sd(csr_io_rocc_pptw_status_sd),
+ .io_rocc_pptw_status_zero2(csr_io_rocc_pptw_status_zero2),
+ .io_rocc_pptw_status_sd_rv32(csr_io_rocc_pptw_status_sd_rv32),
+ .io_rocc_pptw_status_zero1(csr_io_rocc_pptw_status_zero1),
+ .io_rocc_pptw_status_vm(csr_io_rocc_pptw_status_vm),
+ .io_rocc_pptw_status_mprv(csr_io_rocc_pptw_status_mprv),
+ .io_rocc_pptw_status_xs(csr_io_rocc_pptw_status_xs),
+ .io_rocc_pptw_status_fs(csr_io_rocc_pptw_status_fs),
+ .io_rocc_pptw_status_prv3(csr_io_rocc_pptw_status_prv3),
+ .io_rocc_pptw_status_ie3(csr_io_rocc_pptw_status_ie3),
+ .io_rocc_pptw_status_prv2(csr_io_rocc_pptw_status_prv2),
+ .io_rocc_pptw_status_ie2(csr_io_rocc_pptw_status_ie2),
+ .io_rocc_pptw_status_prv1(csr_io_rocc_pptw_status_prv1),
+ .io_rocc_pptw_status_ie1(csr_io_rocc_pptw_status_ie1),
+ .io_rocc_pptw_status_prv(csr_io_rocc_pptw_status_prv),
+ .io_rocc_pptw_status_ie(csr_io_rocc_pptw_status_ie),
+ .io_rocc_pptw_invalidate(csr_io_rocc_pptw_invalidate),
+ .io_rocc_fpu_req_ready(csr_io_rocc_fpu_req_ready),
+ .io_rocc_fpu_req_valid(csr_io_rocc_fpu_req_valid),
+ .io_rocc_fpu_req_bits_cmd(csr_io_rocc_fpu_req_bits_cmd),
+ .io_rocc_fpu_req_bits_ldst(csr_io_rocc_fpu_req_bits_ldst),
+ .io_rocc_fpu_req_bits_wen(csr_io_rocc_fpu_req_bits_wen),
+ .io_rocc_fpu_req_bits_ren1(csr_io_rocc_fpu_req_bits_ren1),
+ .io_rocc_fpu_req_bits_ren2(csr_io_rocc_fpu_req_bits_ren2),
+ .io_rocc_fpu_req_bits_ren3(csr_io_rocc_fpu_req_bits_ren3),
+ .io_rocc_fpu_req_bits_swap12(csr_io_rocc_fpu_req_bits_swap12),
+ .io_rocc_fpu_req_bits_swap23(csr_io_rocc_fpu_req_bits_swap23),
+ .io_rocc_fpu_req_bits_single(csr_io_rocc_fpu_req_bits_single),
+ .io_rocc_fpu_req_bits_fromint(csr_io_rocc_fpu_req_bits_fromint),
+ .io_rocc_fpu_req_bits_toint(csr_io_rocc_fpu_req_bits_toint),
+ .io_rocc_fpu_req_bits_fastpipe(csr_io_rocc_fpu_req_bits_fastpipe),
+ .io_rocc_fpu_req_bits_fma(csr_io_rocc_fpu_req_bits_fma),
+ .io_rocc_fpu_req_bits_div(csr_io_rocc_fpu_req_bits_div),
+ .io_rocc_fpu_req_bits_sqrt(csr_io_rocc_fpu_req_bits_sqrt),
+ .io_rocc_fpu_req_bits_round(csr_io_rocc_fpu_req_bits_round),
+ .io_rocc_fpu_req_bits_wflags(csr_io_rocc_fpu_req_bits_wflags),
+ .io_rocc_fpu_req_bits_rm(csr_io_rocc_fpu_req_bits_rm),
+ .io_rocc_fpu_req_bits_typ(csr_io_rocc_fpu_req_bits_typ),
+ .io_rocc_fpu_req_bits_in1(csr_io_rocc_fpu_req_bits_in1),
+ .io_rocc_fpu_req_bits_in2(csr_io_rocc_fpu_req_bits_in2),
+ .io_rocc_fpu_req_bits_in3(csr_io_rocc_fpu_req_bits_in3),
+ .io_rocc_fpu_resp_ready(csr_io_rocc_fpu_resp_ready),
+ .io_rocc_fpu_resp_valid(csr_io_rocc_fpu_resp_valid),
+ .io_rocc_fpu_resp_bits_data(csr_io_rocc_fpu_resp_bits_data),
+ .io_rocc_fpu_resp_bits_exc(csr_io_rocc_fpu_resp_bits_exc),
+ .io_rocc_exception(csr_io_rocc_exception),
+ .io_rocc_dma_req_ready(csr_io_rocc_dma_req_ready),
+ .io_rocc_dma_req_valid(csr_io_rocc_dma_req_valid),
+ .io_rocc_dma_req_bits_client_xact_id(csr_io_rocc_dma_req_bits_client_xact_id),
+ .io_rocc_dma_req_bits_cmd(csr_io_rocc_dma_req_bits_cmd),
+ .io_rocc_dma_req_bits_source(csr_io_rocc_dma_req_bits_source),
+ .io_rocc_dma_req_bits_dest(csr_io_rocc_dma_req_bits_dest),
+ .io_rocc_dma_req_bits_length(csr_io_rocc_dma_req_bits_length),
+ .io_rocc_dma_req_bits_size(csr_io_rocc_dma_req_bits_size),
+ .io_rocc_dma_resp_ready(csr_io_rocc_dma_resp_ready),
+ .io_rocc_dma_resp_valid(csr_io_rocc_dma_resp_valid),
+ .io_rocc_dma_resp_bits_client_xact_id(csr_io_rocc_dma_resp_bits_client_xact_id),
+ .io_rocc_dma_resp_bits_status(csr_io_rocc_dma_resp_bits_status),
+ .io_interrupt(csr_io_interrupt),
+ .io_interrupt_cause(csr_io_interrupt_cause)
+ );
+ ALU alu (
+ .clk(alu_clk),
+ .reset(alu_reset),
+ .io_dw(alu_io_dw),
+ .io_fn(alu_io_fn),
+ .io_in2(alu_io_in2),
+ .io_in1(alu_io_in1),
+ .io_out(alu_io_out),
+ .io_adder_out(alu_io_adder_out),
+ .io_cmp_out(alu_io_cmp_out)
+ );
+ MulDiv div (
+ .clk(div_clk),
+ .reset(div_reset),
+ .io_req_ready(div_io_req_ready),
+ .io_req_valid(div_io_req_valid),
+ .io_req_bits_fn(div_io_req_bits_fn),
+ .io_req_bits_dw(div_io_req_bits_dw),
+ .io_req_bits_in1(div_io_req_bits_in1),
+ .io_req_bits_in2(div_io_req_bits_in2),
+ .io_req_bits_tag(div_io_req_bits_tag),
+ .io_kill(div_io_kill),
+ .io_resp_ready(div_io_resp_ready),
+ .io_resp_valid(div_io_resp_valid),
+ .io_resp_bits_data(div_io_resp_bits_data),
+ .io_resp_bits_tag(div_io_resp_bits_tag)
+ );
+ assign io_host_csr_req_ready = csr_io_host_csr_req_ready;
+ assign io_host_csr_resp_valid = csr_io_host_csr_resp_valid;
+ assign io_host_csr_resp_bits = csr_io_host_csr_resp_bits;
+ assign io_host_debug_stats_csr = csr_io_host_debug_stats_csr;
+ assign io_imem_req_valid = take_pc_mem_wb;
+ assign io_imem_req_bits_pc = T_7707;
+ assign io_imem_resp_ready = T_7711;
+ assign io_imem_btb_update_valid = T_7722;
+ assign io_imem_btb_update_bits_prediction_valid = mem_reg_btb_hit;
+ assign io_imem_btb_update_bits_prediction_bits_taken = mem_reg_btb_resp_taken;
+ assign io_imem_btb_update_bits_prediction_bits_mask = mem_reg_btb_resp_mask;
+ assign io_imem_btb_update_bits_prediction_bits_bridx = mem_reg_btb_resp_bridx;
+ assign io_imem_btb_update_bits_prediction_bits_target = mem_reg_btb_resp_target;
+ assign io_imem_btb_update_bits_prediction_bits_entry = mem_reg_btb_resp_entry;
+ assign io_imem_btb_update_bits_prediction_bits_bht_history = mem_reg_btb_resp_bht_history;
+ assign io_imem_btb_update_bits_prediction_bits_bht_value = mem_reg_btb_resp_bht_value;
+ assign io_imem_btb_update_bits_pc = mem_reg_pc;
+ assign io_imem_btb_update_bits_target = io_imem_req_bits_pc;
+ assign io_imem_btb_update_bits_taken = GEN_25;
+ assign io_imem_btb_update_bits_isJump = T_7723;
+ assign io_imem_btb_update_bits_isReturn = T_7729;
+ assign io_imem_btb_update_bits_br_pc = mem_reg_pc;
+ assign io_imem_bht_update_valid = T_7733;
+ assign io_imem_bht_update_bits_prediction_valid = io_imem_btb_update_bits_prediction_valid;
+ assign io_imem_bht_update_bits_prediction_bits_taken = io_imem_btb_update_bits_prediction_bits_taken;
+ assign io_imem_bht_update_bits_prediction_bits_mask = io_imem_btb_update_bits_prediction_bits_mask;
+ assign io_imem_bht_update_bits_prediction_bits_bridx = io_imem_btb_update_bits_prediction_bits_bridx;
+ assign io_imem_bht_update_bits_prediction_bits_target = io_imem_btb_update_bits_prediction_bits_target;
+ assign io_imem_bht_update_bits_prediction_bits_entry = io_imem_btb_update_bits_prediction_bits_entry;
+ assign io_imem_bht_update_bits_prediction_bits_bht_history = io_imem_btb_update_bits_prediction_bits_bht_history;
+ assign io_imem_bht_update_bits_prediction_bits_bht_value = io_imem_btb_update_bits_prediction_bits_bht_value;
+ assign io_imem_bht_update_bits_pc = mem_reg_pc;
+ assign io_imem_bht_update_bits_taken = mem_br_taken;
+ assign io_imem_bht_update_bits_mispredict = mem_wrong_npc;
+ assign io_imem_ras_update_valid = T_7740;
+ assign io_imem_ras_update_bits_isCall = T_7742;
+ assign io_imem_ras_update_bits_isReturn = io_imem_btb_update_bits_isReturn;
+ assign io_imem_ras_update_bits_returnAddr = mem_int_wdata;
+ assign io_imem_ras_update_bits_prediction_valid = io_imem_btb_update_bits_prediction_valid;
+ assign io_imem_ras_update_bits_prediction_bits_taken = io_imem_btb_update_bits_prediction_bits_taken;
+ assign io_imem_ras_update_bits_prediction_bits_mask = io_imem_btb_update_bits_prediction_bits_mask;
+ assign io_imem_ras_update_bits_prediction_bits_bridx = io_imem_btb_update_bits_prediction_bits_bridx;
+ assign io_imem_ras_update_bits_prediction_bits_target = io_imem_btb_update_bits_prediction_bits_target;
+ assign io_imem_ras_update_bits_prediction_bits_entry = io_imem_btb_update_bits_prediction_bits_entry;
+ assign io_imem_ras_update_bits_prediction_bits_bht_history = io_imem_btb_update_bits_prediction_bits_bht_history;
+ assign io_imem_ras_update_bits_prediction_bits_bht_value = io_imem_btb_update_bits_prediction_bits_bht_value;
+ assign io_imem_invalidate = T_7708;
+ assign io_dmem_req_valid = T_7747;
+ assign io_dmem_req_bits_addr = T_7773;
+ assign io_dmem_req_bits_tag = T_7774;
+ assign io_dmem_req_bits_cmd = ex_ctrl_mem_cmd;
+ assign io_dmem_req_bits_typ = ex_ctrl_mem_type;
+ assign io_dmem_req_bits_kill = T_7748;
+ assign io_dmem_req_bits_phys = 1'h0;
+ assign io_dmem_req_bits_data = T_7775;
+ assign io_dmem_invalidate_lr = wb_xcpt;
+ assign io_ptw_ptbr = csr_io_ptbr;
+ assign io_ptw_invalidate = csr_io_fatc;
+ assign io_ptw_status_sd = csr_io_status_sd;
+ assign io_ptw_status_zero2 = csr_io_status_zero2;
+ assign io_ptw_status_sd_rv32 = csr_io_status_sd_rv32;
+ assign io_ptw_status_zero1 = csr_io_status_zero1;
+ assign io_ptw_status_vm = csr_io_status_vm;
+ assign io_ptw_status_mprv = csr_io_status_mprv;
+ assign io_ptw_status_xs = csr_io_status_xs;
+ assign io_ptw_status_fs = csr_io_status_fs;
+ assign io_ptw_status_prv3 = csr_io_status_prv3;
+ assign io_ptw_status_ie3 = csr_io_status_ie3;
+ assign io_ptw_status_prv2 = csr_io_status_prv2;
+ assign io_ptw_status_ie2 = csr_io_status_ie2;
+ assign io_ptw_status_prv1 = csr_io_status_prv1;
+ assign io_ptw_status_ie1 = csr_io_status_ie1;
+ assign io_ptw_status_prv = csr_io_status_prv;
+ assign io_ptw_status_ie = csr_io_status_ie;
+ assign io_fpu_inst = io_imem_resp_bits_data_0;
+ assign io_fpu_fromint_data = T_6992;
+ assign io_fpu_fcsr_rm = csr_io_fcsr_rm;
+ assign io_fpu_dmem_resp_val = T_7746;
+ assign io_fpu_dmem_resp_type = io_dmem_resp_bits_typ;
+ assign io_fpu_dmem_resp_tag = dmem_resp_waddr;
+ assign io_fpu_dmem_resp_data = io_dmem_resp_bits_data_word_bypass;
+ assign io_fpu_valid = T_7745;
+ assign io_fpu_killx = ctrl_killx;
+ assign io_fpu_killm = killm_common;
+ assign io_fpu_cp_req_valid = GEN_26;
+ assign io_fpu_cp_req_bits_cmd = GEN_27;
+ assign io_fpu_cp_req_bits_ldst = GEN_28;
+ assign io_fpu_cp_req_bits_wen = GEN_29;
+ assign io_fpu_cp_req_bits_ren1 = GEN_30;
+ assign io_fpu_cp_req_bits_ren2 = GEN_31;
+ assign io_fpu_cp_req_bits_ren3 = GEN_32;
+ assign io_fpu_cp_req_bits_swap12 = GEN_33;
+ assign io_fpu_cp_req_bits_swap23 = GEN_34;
+ assign io_fpu_cp_req_bits_single = GEN_35;
+ assign io_fpu_cp_req_bits_fromint = GEN_36;
+ assign io_fpu_cp_req_bits_toint = GEN_37;
+ assign io_fpu_cp_req_bits_fastpipe = GEN_38;
+ assign io_fpu_cp_req_bits_fma = GEN_39;
+ assign io_fpu_cp_req_bits_div = GEN_40;
+ assign io_fpu_cp_req_bits_sqrt = GEN_41;
+ assign io_fpu_cp_req_bits_round = GEN_42;
+ assign io_fpu_cp_req_bits_wflags = GEN_43;
+ assign io_fpu_cp_req_bits_rm = GEN_44;
+ assign io_fpu_cp_req_bits_typ = GEN_45;
+ assign io_fpu_cp_req_bits_in1 = GEN_46;
+ assign io_fpu_cp_req_bits_in2 = GEN_47;
+ assign io_fpu_cp_req_bits_in3 = GEN_48;
+ assign io_fpu_cp_resp_ready = GEN_49;
+ assign io_rocc_cmd_valid = wb_rocc_val;
+ assign io_rocc_cmd_bits_inst_funct = T_7799_funct;
+ assign io_rocc_cmd_bits_inst_rs2 = T_7799_rs2;
+ assign io_rocc_cmd_bits_inst_rs1 = T_7799_rs1;
+ assign io_rocc_cmd_bits_inst_xd = T_7799_xd;
+ assign io_rocc_cmd_bits_inst_xs1 = T_7799_xs1;
+ assign io_rocc_cmd_bits_inst_xs2 = T_7799_xs2;
+ assign io_rocc_cmd_bits_inst_rd = T_7799_rd;
+ assign io_rocc_cmd_bits_inst_opcode = T_7799_opcode;
+ assign io_rocc_cmd_bits_rs1 = wb_reg_wdata;
+ assign io_rocc_cmd_bits_rs2 = wb_reg_rs2;
+ assign io_rocc_resp_ready = csr_io_rocc_resp_ready;
+ assign io_rocc_mem_req_ready = csr_io_rocc_mem_req_ready;
+ assign io_rocc_mem_resp_valid = csr_io_rocc_mem_resp_valid;
+ assign io_rocc_mem_resp_bits_addr = csr_io_rocc_mem_resp_bits_addr;
+ assign io_rocc_mem_resp_bits_tag = csr_io_rocc_mem_resp_bits_tag;
+ assign io_rocc_mem_resp_bits_cmd = csr_io_rocc_mem_resp_bits_cmd;
+ assign io_rocc_mem_resp_bits_typ = csr_io_rocc_mem_resp_bits_typ;
+ assign io_rocc_mem_resp_bits_data = csr_io_rocc_mem_resp_bits_data;
+ assign io_rocc_mem_resp_bits_nack = csr_io_rocc_mem_resp_bits_nack;
+ assign io_rocc_mem_resp_bits_replay = csr_io_rocc_mem_resp_bits_replay;
+ assign io_rocc_mem_resp_bits_has_data = csr_io_rocc_mem_resp_bits_has_data;
+ assign io_rocc_mem_resp_bits_data_word_bypass = csr_io_rocc_mem_resp_bits_data_word_bypass;
+ assign io_rocc_mem_resp_bits_store_data = csr_io_rocc_mem_resp_bits_store_data;
+ assign io_rocc_mem_replay_next_valid = csr_io_rocc_mem_replay_next_valid;
+ assign io_rocc_mem_replay_next_bits = csr_io_rocc_mem_replay_next_bits;
+ assign io_rocc_mem_xcpt_ma_ld = csr_io_rocc_mem_xcpt_ma_ld;
+ assign io_rocc_mem_xcpt_ma_st = csr_io_rocc_mem_xcpt_ma_st;
+ assign io_rocc_mem_xcpt_pf_ld = csr_io_rocc_mem_xcpt_pf_ld;
+ assign io_rocc_mem_xcpt_pf_st = csr_io_rocc_mem_xcpt_pf_st;
+ assign io_rocc_mem_ordered = csr_io_rocc_mem_ordered;
+ assign io_rocc_s = T_7780;
+ assign io_rocc_autl_acquire_ready = csr_io_rocc_autl_acquire_ready;
+ assign io_rocc_autl_grant_valid = csr_io_rocc_autl_grant_valid;
+ assign io_rocc_autl_grant_bits_addr_beat = csr_io_rocc_autl_grant_bits_addr_beat;
+ assign io_rocc_autl_grant_bits_client_xact_id = csr_io_rocc_autl_grant_bits_client_xact_id;
+ assign io_rocc_autl_grant_bits_manager_xact_id = csr_io_rocc_autl_grant_bits_manager_xact_id;
+ assign io_rocc_autl_grant_bits_is_builtin_type = csr_io_rocc_autl_grant_bits_is_builtin_type;
+ assign io_rocc_autl_grant_bits_g_type = csr_io_rocc_autl_grant_bits_g_type;
+ assign io_rocc_autl_grant_bits_data = csr_io_rocc_autl_grant_bits_data;
+ assign io_rocc_iptw_req_ready = csr_io_rocc_iptw_req_ready;
+ assign io_rocc_iptw_resp_valid = csr_io_rocc_iptw_resp_valid;
+ assign io_rocc_iptw_resp_bits_error = csr_io_rocc_iptw_resp_bits_error;
+ assign io_rocc_iptw_resp_bits_pte_ppn = csr_io_rocc_iptw_resp_bits_pte_ppn;
+ assign io_rocc_iptw_resp_bits_pte_reserved_for_software = csr_io_rocc_iptw_resp_bits_pte_reserved_for_software;
+ assign io_rocc_iptw_resp_bits_pte_d = csr_io_rocc_iptw_resp_bits_pte_d;
+ assign io_rocc_iptw_resp_bits_pte_r = csr_io_rocc_iptw_resp_bits_pte_r;
+ assign io_rocc_iptw_resp_bits_pte_typ = csr_io_rocc_iptw_resp_bits_pte_typ;
+ assign io_rocc_iptw_resp_bits_pte_v = csr_io_rocc_iptw_resp_bits_pte_v;
+ assign io_rocc_iptw_status_sd = csr_io_rocc_iptw_status_sd;
+ assign io_rocc_iptw_status_zero2 = csr_io_rocc_iptw_status_zero2;
+ assign io_rocc_iptw_status_sd_rv32 = csr_io_rocc_iptw_status_sd_rv32;
+ assign io_rocc_iptw_status_zero1 = csr_io_rocc_iptw_status_zero1;
+ assign io_rocc_iptw_status_vm = csr_io_rocc_iptw_status_vm;
+ assign io_rocc_iptw_status_mprv = csr_io_rocc_iptw_status_mprv;
+ assign io_rocc_iptw_status_xs = csr_io_rocc_iptw_status_xs;
+ assign io_rocc_iptw_status_fs = csr_io_rocc_iptw_status_fs;
+ assign io_rocc_iptw_status_prv3 = csr_io_rocc_iptw_status_prv3;
+ assign io_rocc_iptw_status_ie3 = csr_io_rocc_iptw_status_ie3;
+ assign io_rocc_iptw_status_prv2 = csr_io_rocc_iptw_status_prv2;
+ assign io_rocc_iptw_status_ie2 = csr_io_rocc_iptw_status_ie2;
+ assign io_rocc_iptw_status_prv1 = csr_io_rocc_iptw_status_prv1;
+ assign io_rocc_iptw_status_ie1 = csr_io_rocc_iptw_status_ie1;
+ assign io_rocc_iptw_status_prv = csr_io_rocc_iptw_status_prv;
+ assign io_rocc_iptw_status_ie = csr_io_rocc_iptw_status_ie;
+ assign io_rocc_iptw_invalidate = csr_io_rocc_iptw_invalidate;
+ assign io_rocc_dptw_req_ready = csr_io_rocc_dptw_req_ready;
+ assign io_rocc_dptw_resp_valid = csr_io_rocc_dptw_resp_valid;
+ assign io_rocc_dptw_resp_bits_error = csr_io_rocc_dptw_resp_bits_error;
+ assign io_rocc_dptw_resp_bits_pte_ppn = csr_io_rocc_dptw_resp_bits_pte_ppn;
+ assign io_rocc_dptw_resp_bits_pte_reserved_for_software = csr_io_rocc_dptw_resp_bits_pte_reserved_for_software;
+ assign io_rocc_dptw_resp_bits_pte_d = csr_io_rocc_dptw_resp_bits_pte_d;
+ assign io_rocc_dptw_resp_bits_pte_r = csr_io_rocc_dptw_resp_bits_pte_r;
+ assign io_rocc_dptw_resp_bits_pte_typ = csr_io_rocc_dptw_resp_bits_pte_typ;
+ assign io_rocc_dptw_resp_bits_pte_v = csr_io_rocc_dptw_resp_bits_pte_v;
+ assign io_rocc_dptw_status_sd = csr_io_rocc_dptw_status_sd;
+ assign io_rocc_dptw_status_zero2 = csr_io_rocc_dptw_status_zero2;
+ assign io_rocc_dptw_status_sd_rv32 = csr_io_rocc_dptw_status_sd_rv32;
+ assign io_rocc_dptw_status_zero1 = csr_io_rocc_dptw_status_zero1;
+ assign io_rocc_dptw_status_vm = csr_io_rocc_dptw_status_vm;
+ assign io_rocc_dptw_status_mprv = csr_io_rocc_dptw_status_mprv;
+ assign io_rocc_dptw_status_xs = csr_io_rocc_dptw_status_xs;
+ assign io_rocc_dptw_status_fs = csr_io_rocc_dptw_status_fs;
+ assign io_rocc_dptw_status_prv3 = csr_io_rocc_dptw_status_prv3;
+ assign io_rocc_dptw_status_ie3 = csr_io_rocc_dptw_status_ie3;
+ assign io_rocc_dptw_status_prv2 = csr_io_rocc_dptw_status_prv2;
+ assign io_rocc_dptw_status_ie2 = csr_io_rocc_dptw_status_ie2;
+ assign io_rocc_dptw_status_prv1 = csr_io_rocc_dptw_status_prv1;
+ assign io_rocc_dptw_status_ie1 = csr_io_rocc_dptw_status_ie1;
+ assign io_rocc_dptw_status_prv = csr_io_rocc_dptw_status_prv;
+ assign io_rocc_dptw_status_ie = csr_io_rocc_dptw_status_ie;
+ assign io_rocc_dptw_invalidate = csr_io_rocc_dptw_invalidate;
+ assign io_rocc_pptw_req_ready = csr_io_rocc_pptw_req_ready;
+ assign io_rocc_pptw_resp_valid = csr_io_rocc_pptw_resp_valid;
+ assign io_rocc_pptw_resp_bits_error = csr_io_rocc_pptw_resp_bits_error;
+ assign io_rocc_pptw_resp_bits_pte_ppn = csr_io_rocc_pptw_resp_bits_pte_ppn;
+ assign io_rocc_pptw_resp_bits_pte_reserved_for_software = csr_io_rocc_pptw_resp_bits_pte_reserved_for_software;
+ assign io_rocc_pptw_resp_bits_pte_d = csr_io_rocc_pptw_resp_bits_pte_d;
+ assign io_rocc_pptw_resp_bits_pte_r = csr_io_rocc_pptw_resp_bits_pte_r;
+ assign io_rocc_pptw_resp_bits_pte_typ = csr_io_rocc_pptw_resp_bits_pte_typ;
+ assign io_rocc_pptw_resp_bits_pte_v = csr_io_rocc_pptw_resp_bits_pte_v;
+ assign io_rocc_pptw_status_sd = csr_io_rocc_pptw_status_sd;
+ assign io_rocc_pptw_status_zero2 = csr_io_rocc_pptw_status_zero2;
+ assign io_rocc_pptw_status_sd_rv32 = csr_io_rocc_pptw_status_sd_rv32;
+ assign io_rocc_pptw_status_zero1 = csr_io_rocc_pptw_status_zero1;
+ assign io_rocc_pptw_status_vm = csr_io_rocc_pptw_status_vm;
+ assign io_rocc_pptw_status_mprv = csr_io_rocc_pptw_status_mprv;
+ assign io_rocc_pptw_status_xs = csr_io_rocc_pptw_status_xs;
+ assign io_rocc_pptw_status_fs = csr_io_rocc_pptw_status_fs;
+ assign io_rocc_pptw_status_prv3 = csr_io_rocc_pptw_status_prv3;
+ assign io_rocc_pptw_status_ie3 = csr_io_rocc_pptw_status_ie3;
+ assign io_rocc_pptw_status_prv2 = csr_io_rocc_pptw_status_prv2;
+ assign io_rocc_pptw_status_ie2 = csr_io_rocc_pptw_status_ie2;
+ assign io_rocc_pptw_status_prv1 = csr_io_rocc_pptw_status_prv1;
+ assign io_rocc_pptw_status_ie1 = csr_io_rocc_pptw_status_ie1;
+ assign io_rocc_pptw_status_prv = csr_io_rocc_pptw_status_prv;
+ assign io_rocc_pptw_status_ie = csr_io_rocc_pptw_status_ie;
+ assign io_rocc_pptw_invalidate = csr_io_rocc_pptw_invalidate;
+ assign io_rocc_fpu_req_ready = csr_io_rocc_fpu_req_ready;
+ assign io_rocc_fpu_resp_valid = csr_io_rocc_fpu_resp_valid;
+ assign io_rocc_fpu_resp_bits_data = csr_io_rocc_fpu_resp_bits_data;
+ assign io_rocc_fpu_resp_bits_exc = csr_io_rocc_fpu_resp_bits_exc;
+ assign io_rocc_exception = T_7778;
+ assign io_rocc_dma_req_ready = csr_io_rocc_dma_req_ready;
+ assign io_rocc_dma_resp_valid = csr_io_rocc_dma_resp_valid;
+ assign io_rocc_dma_resp_bits_client_xact_id = csr_io_rocc_dma_resp_bits_client_xact_id;
+ assign io_rocc_dma_resp_bits_status = csr_io_rocc_dma_resp_bits_status;
+ assign take_pc_mem = T_7367;
+ assign take_pc_wb = T_7449;
+ assign take_pc_mem_wb = take_pc_wb | take_pc_mem;
+ assign id_ctrl_legal = T_6268;
+ assign id_ctrl_fp = T_6279;
+ assign id_ctrl_rocc = 1'h0;
+ assign id_ctrl_branch = T_6286;
+ assign id_ctrl_jal = T_6292;
+ assign id_ctrl_jalr = T_6298;
+ assign id_ctrl_rxs2 = T_6314;
+ assign id_ctrl_rxs1 = T_6340;
+ assign id_ctrl_sel_alu2 = T_6384;
+ assign id_ctrl_sel_alu1 = T_6410;
+ assign id_ctrl_sel_imm = T_6446;
+ assign id_ctrl_alu_dw = T_6457;
+ assign id_ctrl_alu_fn = T_6541;
+ assign id_ctrl_mem = T_6557;
+ assign id_ctrl_mem_cmd = T_6607;
+ assign id_ctrl_mem_type = T_6627;
+ assign id_ctrl_rfs1 = T_6643;
+ assign id_ctrl_rfs2 = T_6660;
+ assign id_ctrl_rfs3 = T_6662;
+ assign id_ctrl_wfd = T_6675;
+ assign id_ctrl_div = T_6681;
+ assign id_ctrl_wxd = T_6717;
+ assign id_ctrl_csr = T_6737;
+ assign id_ctrl_fence_i = T_6743;
+ assign id_ctrl_fence = T_6749;
+ assign id_ctrl_amo = T_6755;
+ assign T_6071 = io_imem_resp_bits_data_0 & 32'h207f;
+ assign T_6073 = T_6071 == 32'h3;
+ assign T_6075 = io_imem_resp_bits_data_0 & 32'h106f;
+ assign T_6077 = T_6075 == 32'h3;
+ assign T_6079 = io_imem_resp_bits_data_0 & 32'h607f;
+ assign T_6081 = T_6079 == 32'hf;
+ assign T_6083 = io_imem_resp_bits_data_0 & 32'h7077;
+ assign T_6085 = T_6083 == 32'h13;
+ assign T_6087 = io_imem_resp_bits_data_0 & 32'h5f;
+ assign T_6089 = T_6087 == 32'h17;
+ assign T_6091 = io_imem_resp_bits_data_0 & 32'hfc00007f;
+ assign T_6093 = T_6091 == 32'h33;
+ assign T_6095 = io_imem_resp_bits_data_0 & 32'hbe007077;
+ assign T_6097 = T_6095 == 32'h33;
+ assign T_6099 = io_imem_resp_bits_data_0 & 32'h4000073;
+ assign T_6101 = T_6099 == 32'h43;
+ assign T_6103 = io_imem_resp_bits_data_0 & 32'he400007f;
+ assign T_6105 = T_6103 == 32'h53;
+ assign T_6107 = io_imem_resp_bits_data_0 & 32'h707b;
+ assign T_6109 = T_6107 == 32'h63;
+ assign T_6111 = io_imem_resp_bits_data_0 & 32'h7f;
+ assign T_6113 = T_6111 == 32'h6f;
+ assign T_6115 = io_imem_resp_bits_data_0 & 32'hffefffff;
+ assign T_6117 = T_6115 == 32'h73;
+ assign T_6119 = io_imem_resp_bits_data_0 & 32'hfc00305f;
+ assign T_6121 = T_6119 == 32'h1013;
+ assign T_6123 = io_imem_resp_bits_data_0 & 32'hfe00305f;
+ assign T_6125 = T_6123 == 32'h101b;
+ assign T_6127 = io_imem_resp_bits_data_0 & 32'h605b;
+ assign T_6129 = T_6127 == 32'h2003;
+ assign T_6131 = io_imem_resp_bits_data_0 & 32'h207f;
+ assign T_6133 = T_6131 == 32'h2013;
+ assign T_6135 = io_imem_resp_bits_data_0 & 32'h1800607f;
+ assign T_6137 = T_6135 == 32'h202f;
+ assign T_6139 = io_imem_resp_bits_data_0 & 32'h207f;
+ assign T_6141 = T_6139 == 32'h2073;
+ assign T_6143 = io_imem_resp_bits_data_0 & 32'hbc00707f;
+ assign T_6145 = T_6143 == 32'h5013;
+ assign T_6147 = io_imem_resp_bits_data_0 & 32'hbe00705f;
+ assign T_6149 = T_6147 == 32'h501b;
+ assign T_6151 = io_imem_resp_bits_data_0 & 32'hbe007077;
+ assign T_6153 = T_6151 == 32'h5033;
+ assign T_6155 = io_imem_resp_bits_data_0 & 32'hfe004077;
+ assign T_6157 = T_6155 == 32'h2004033;
+ assign T_6159 = io_imem_resp_bits_data_0 & 32'he800607f;
+ assign T_6161 = T_6159 == 32'h800202f;
+ assign T_6163 = io_imem_resp_bits_data_0 & 32'hffdfffff;
+ assign T_6165 = T_6163 == 32'h10000073;
+ assign T_6167 = io_imem_resp_bits_data_0 & 32'hf9f0607f;
+ assign T_6169 = T_6167 == 32'h1000202f;
+ assign T_6171 = io_imem_resp_bits_data_0 & 32'hfff07fff;
+ assign T_6173 = T_6171 == 32'h10100073;
+ assign T_6175 = io_imem_resp_bits_data_0 & 32'hf400607f;
+ assign T_6177 = T_6175 == 32'h20000053;
+ assign T_6179 = io_imem_resp_bits_data_0 & 32'h7c00607f;
+ assign T_6181 = T_6179 == 32'h20000053;
+ assign T_6183 = io_imem_resp_bits_data_0 & 32'h7c00507f;
+ assign T_6185 = T_6183 == 32'h20000053;
+ assign T_6187 = io_imem_resp_bits_data_0 == 32'h30500073;
+ assign T_6189 = io_imem_resp_bits_data_0 & 32'h7ff0007f;
+ assign T_6191 = T_6189 == 32'h40100053;
+ assign T_6193 = io_imem_resp_bits_data_0 & 32'h7ff0007f;
+ assign T_6195 = T_6193 == 32'h42000053;
+ assign T_6197 = io_imem_resp_bits_data_0 & 32'hfdf0007f;
+ assign T_6199 = T_6197 == 32'h58000053;
+ assign T_6201 = io_imem_resp_bits_data_0 & 32'hedc0007f;
+ assign T_6203 = T_6201 == 32'hc0000053;
+ assign T_6205 = io_imem_resp_bits_data_0 & 32'hfdf0607f;
+ assign T_6207 = T_6205 == 32'he0000053;
+ assign T_6209 = io_imem_resp_bits_data_0 & 32'hedf0707f;
+ assign T_6211 = T_6209 == 32'he0000053;
+ assign T_6213 = io_imem_resp_bits_data_0 & 32'h603f;
+ assign T_6215 = T_6213 == 32'h23;
+ assign T_6217 = io_imem_resp_bits_data_0 & 32'h306f;
+ assign T_6219 = T_6217 == 32'h1063;
+ assign T_6221 = io_imem_resp_bits_data_0 & 32'h407f;
+ assign T_6223 = T_6221 == 32'h4063;
+ assign T_6225 = io_imem_resp_bits_data_0 & 32'hfc007077;
+ assign T_6227 = T_6225 == 32'h33;
+ assign T_6229 = 1'h0 | T_6073;
+ assign T_6230 = T_6229 | T_6077;
+ assign T_6231 = T_6230 | T_6081;
+ assign T_6232 = T_6231 | T_6085;
+ assign T_6233 = T_6232 | T_6089;
+ assign T_6234 = T_6233 | T_6093;
+ assign T_6235 = T_6234 | T_6097;
+ assign T_6236 = T_6235 | T_6101;
+ assign T_6237 = T_6236 | T_6105;
+ assign T_6238 = T_6237 | T_6109;
+ assign T_6239 = T_6238 | T_6113;
+ assign T_6240 = T_6239 | T_6117;
+ assign T_6241 = T_6240 | T_6121;
+ assign T_6242 = T_6241 | T_6125;
+ assign T_6243 = T_6242 | T_6129;
+ assign T_6244 = T_6243 | T_6133;
+ assign T_6245 = T_6244 | T_6137;
+ assign T_6246 = T_6245 | T_6141;
+ assign T_6247 = T_6246 | T_6145;
+ assign T_6248 = T_6247 | T_6149;
+ assign T_6249 = T_6248 | T_6153;
+ assign T_6250 = T_6249 | T_6157;
+ assign T_6251 = T_6250 | T_6161;
+ assign T_6252 = T_6251 | T_6165;
+ assign T_6253 = T_6252 | T_6169;
+ assign T_6254 = T_6253 | T_6173;
+ assign T_6255 = T_6254 | T_6177;
+ assign T_6256 = T_6255 | T_6181;
+ assign T_6257 = T_6256 | T_6185;
+ assign T_6258 = T_6257 | T_6187;
+ assign T_6259 = T_6258 | T_6191;
+ assign T_6260 = T_6259 | T_6195;
+ assign T_6261 = T_6260 | T_6199;
+ assign T_6262 = T_6261 | T_6203;
+ assign T_6263 = T_6262 | T_6207;
+ assign T_6264 = T_6263 | T_6211;
+ assign T_6265 = T_6264 | T_6215;
+ assign T_6266 = T_6265 | T_6219;
+ assign T_6267 = T_6266 | T_6223;
+ assign T_6268 = T_6267 | T_6227;
+ assign T_6270 = io_imem_resp_bits_data_0 & 32'h5c;
+ assign T_6272 = T_6270 == 32'h4;
+ assign T_6274 = io_imem_resp_bits_data_0 & 32'h60;
+ assign T_6276 = T_6274 == 32'h40;
+ assign T_6278 = 1'h0 | T_6272;
+ assign T_6279 = T_6278 | T_6276;
+ assign T_6282 = io_imem_resp_bits_data_0 & 32'h74;
+ assign T_6284 = T_6282 == 32'h60;
+ assign T_6286 = 1'h0 | T_6284;
+ assign T_6288 = io_imem_resp_bits_data_0 & 32'h68;
+ assign T_6290 = T_6288 == 32'h68;
+ assign T_6292 = 1'h0 | T_6290;
+ assign T_6294 = io_imem_resp_bits_data_0 & 32'h203c;
+ assign T_6296 = T_6294 == 32'h24;
+ assign T_6298 = 1'h0 | T_6296;
+ assign T_6300 = io_imem_resp_bits_data_0 & 32'h64;
+ assign T_6302 = T_6300 == 32'h20;
+ assign T_6304 = io_imem_resp_bits_data_0 & 32'h34;
+ assign T_6306 = T_6304 == 32'h20;
+ assign T_6308 = io_imem_resp_bits_data_0 & 32'h2048;
+ assign T_6310 = T_6308 == 32'h2008;
+ assign T_6312 = 1'h0 | T_6302;
+ assign T_6313 = T_6312 | T_6306;
+ assign T_6314 = T_6313 | T_6310;
+ assign T_6316 = io_imem_resp_bits_data_0 & 32'h44;
+ assign T_6318 = T_6316 == 32'h0;
+ assign T_6320 = io_imem_resp_bits_data_0 & 32'h4024;
+ assign T_6322 = T_6320 == 32'h20;
+ assign T_6324 = io_imem_resp_bits_data_0 & 32'h38;
+ assign T_6326 = T_6324 == 32'h20;
+ assign T_6328 = io_imem_resp_bits_data_0 & 32'h2050;
+ assign T_6330 = T_6328 == 32'h2000;
+ assign T_6332 = io_imem_resp_bits_data_0 & 32'h90000034;
+ assign T_6334 = T_6332 == 32'h90000010;
+ assign T_6336 = 1'h0 | T_6318;
+ assign T_6337 = T_6336 | T_6322;
+ assign T_6338 = T_6337 | T_6326;
+ assign T_6339 = T_6338 | T_6330;
+ assign T_6340 = T_6339 | T_6334;
+ assign T_6342 = io_imem_resp_bits_data_0 & 32'h58;
+ assign T_6344 = T_6342 == 32'h0;
+ assign T_6346 = io_imem_resp_bits_data_0 & 32'h20;
+ assign T_6348 = T_6346 == 32'h0;
+ assign T_6350 = io_imem_resp_bits_data_0 & 32'hc;
+ assign T_6352 = T_6350 == 32'h4;
+ assign T_6354 = io_imem_resp_bits_data_0 & 32'h48;
+ assign T_6356 = T_6354 == 32'h48;
+ assign T_6358 = io_imem_resp_bits_data_0 & 32'h4050;
+ assign T_6360 = T_6358 == 32'h4050;
+ assign T_6362 = 1'h0 | T_6344;
+ assign T_6363 = T_6362 | T_6348;
+ assign T_6364 = T_6363 | T_6352;
+ assign T_6365 = T_6364 | T_6356;
+ assign T_6366 = T_6365 | T_6360;
+ assign T_6368 = io_imem_resp_bits_data_0 & 32'h48;
+ assign T_6370 = T_6368 == 32'h0;
+ assign T_6372 = io_imem_resp_bits_data_0 & 32'h18;
+ assign T_6374 = T_6372 == 32'h0;
+ assign T_6376 = io_imem_resp_bits_data_0 & 32'h4008;
+ assign T_6378 = T_6376 == 32'h4000;
+ assign T_6380 = 1'h0 | T_6370;
+ assign T_6381 = T_6380 | T_6318;
+ assign T_6382 = T_6381 | T_6374;
+ assign T_6383 = T_6382 | T_6378;
+ assign T_6384 = {T_6383,T_6366};
+ assign T_6386 = io_imem_resp_bits_data_0 & 32'h4004;
+ assign T_6388 = T_6386 == 32'h0;
+ assign T_6390 = io_imem_resp_bits_data_0 & 32'h50;
+ assign T_6392 = T_6390 == 32'h0;
+ assign T_6394 = io_imem_resp_bits_data_0 & 32'h24;
+ assign T_6396 = T_6394 == 32'h0;
+ assign T_6398 = 1'h0 | T_6388;
+ assign T_6399 = T_6398 | T_6392;
+ assign T_6400 = T_6399 | T_6318;
+ assign T_6401 = T_6400 | T_6396;
+ assign T_6402 = T_6401 | T_6374;
+ assign T_6404 = io_imem_resp_bits_data_0 & 32'h34;
+ assign T_6406 = T_6404 == 32'h14;
+ assign T_6408 = 1'h0 | T_6406;
+ assign T_6409 = T_6408 | T_6356;
+ assign T_6410 = {T_6409,T_6402};
+ assign T_6412 = io_imem_resp_bits_data_0 & 32'h18;
+ assign T_6414 = T_6412 == 32'h8;
+ assign T_6416 = io_imem_resp_bits_data_0 & 32'h44;
+ assign T_6418 = T_6416 == 32'h40;
+ assign T_6420 = 1'h0 | T_6414;
+ assign T_6421 = T_6420 | T_6418;
+ assign T_6423 = io_imem_resp_bits_data_0 & 32'h14;
+ assign T_6425 = T_6423 == 32'h14;
+ assign T_6427 = 1'h0 | T_6414;
+ assign T_6428 = T_6427 | T_6425;
+ assign T_6430 = io_imem_resp_bits_data_0 & 32'h30;
+ assign T_6432 = T_6430 == 32'h0;
+ assign T_6434 = io_imem_resp_bits_data_0 & 32'h201c;
+ assign T_6436 = T_6434 == 32'h4;
+ assign T_6438 = io_imem_resp_bits_data_0 & 32'h14;
+ assign T_6440 = T_6438 == 32'h10;
+ assign T_6442 = 1'h0 | T_6432;
+ assign T_6443 = T_6442 | T_6436;
+ assign T_6444 = T_6443 | T_6440;
+ assign T_6445 = {T_6428,T_6421};
+ assign T_6446 = {T_6444,T_6445};
+ assign T_6448 = io_imem_resp_bits_data_0 & 32'h10;
+ assign T_6450 = T_6448 == 32'h0;
+ assign T_6452 = io_imem_resp_bits_data_0 & 32'h8;
+ assign T_6454 = T_6452 == 32'h0;
+ assign T_6456 = 1'h0 | T_6450;
+ assign T_6457 = T_6456 | T_6454;
+ assign T_6459 = io_imem_resp_bits_data_0 & 32'h3054;
+ assign T_6461 = T_6459 == 32'h1010;
+ assign T_6463 = io_imem_resp_bits_data_0 & 32'h1058;
+ assign T_6465 = T_6463 == 32'h1040;
+ assign T_6467 = io_imem_resp_bits_data_0 & 32'h7044;
+ assign T_6469 = T_6467 == 32'h7000;
+ assign T_6471 = 1'h0 | T_6461;
+ assign T_6472 = T_6471 | T_6465;
+ assign T_6473 = T_6472 | T_6469;
+ assign T_6475 = io_imem_resp_bits_data_0 & 32'h4054;
+ assign T_6477 = T_6475 == 32'h40;
+ assign T_6479 = io_imem_resp_bits_data_0 & 32'h2058;
+ assign T_6481 = T_6479 == 32'h2040;
+ assign T_6483 = io_imem_resp_bits_data_0 & 32'h3054;
+ assign T_6485 = T_6483 == 32'h3010;
+ assign T_6487 = io_imem_resp_bits_data_0 & 32'h6054;
+ assign T_6489 = T_6487 == 32'h6010;
+ assign T_6491 = io_imem_resp_bits_data_0 & 32'h40003034;
+ assign T_6493 = T_6491 == 32'h40000030;
+ assign T_6495 = io_imem_resp_bits_data_0 & 32'h40001054;
+ assign T_6497 = T_6495 == 32'h40001010;
+ assign T_6499 = 1'h0 | T_6477;
+ assign T_6500 = T_6499 | T_6481;
+ assign T_6501 = T_6500 | T_6485;
+ assign T_6502 = T_6501 | T_6489;
+ assign T_6503 = T_6502 | T_6493;
+ assign T_6504 = T_6503 | T_6497;
+ assign T_6506 = io_imem_resp_bits_data_0 & 32'h2054;
+ assign T_6508 = T_6506 == 32'h2010;
+ assign T_6510 = io_imem_resp_bits_data_0 & 32'h40004054;
+ assign T_6512 = T_6510 == 32'h4010;
+ assign T_6514 = io_imem_resp_bits_data_0 & 32'h5054;
+ assign T_6516 = T_6514 == 32'h4010;
+ assign T_6518 = io_imem_resp_bits_data_0 & 32'h4058;
+ assign T_6520 = T_6518 == 32'h4040;
+ assign T_6522 = 1'h0 | T_6508;
+ assign T_6523 = T_6522 | T_6512;
+ assign T_6524 = T_6523 | T_6516;
+ assign T_6525 = T_6524 | T_6520;
+ assign T_6527 = io_imem_resp_bits_data_0 & 32'h6054;
+ assign T_6529 = T_6527 == 32'h2010;
+ assign T_6531 = io_imem_resp_bits_data_0 & 32'h40003054;
+ assign T_6533 = T_6531 == 32'h40001010;
+ assign T_6535 = 1'h0 | T_6529;
+ assign T_6536 = T_6535 | T_6520;
+ assign T_6537 = T_6536 | T_6493;
+ assign T_6538 = T_6537 | T_6533;
+ assign T_6539 = {T_6504,T_6473};
+ assign T_6540 = {T_6525,T_6539};
+ assign T_6541 = {T_6538,T_6540};
+ assign T_6543 = io_imem_resp_bits_data_0 & 32'h405f;
+ assign T_6545 = T_6543 == 32'h3;
+ assign T_6547 = io_imem_resp_bits_data_0 & 32'h107f;
+ assign T_6549 = T_6547 == 32'h3;
+ assign T_6551 = 1'h0 | T_6545;
+ assign T_6552 = T_6551 | T_6073;
+ assign T_6553 = T_6552 | T_6549;
+ assign T_6554 = T_6553 | T_6129;
+ assign T_6555 = T_6554 | T_6137;
+ assign T_6556 = T_6555 | T_6161;
+ assign T_6557 = T_6556 | T_6169;
+ assign T_6559 = io_imem_resp_bits_data_0 & 32'h28;
+ assign T_6561 = T_6559 == 32'h20;
+ assign T_6563 = io_imem_resp_bits_data_0 & 32'h18000020;
+ assign T_6565 = T_6563 == 32'h18000020;
+ assign T_6567 = io_imem_resp_bits_data_0 & 32'h20000020;
+ assign T_6569 = T_6567 == 32'h20000020;
+ assign T_6571 = 1'h0 | T_6561;
+ assign T_6572 = T_6571 | T_6565;
+ assign T_6573 = T_6572 | T_6569;
+ assign T_6575 = io_imem_resp_bits_data_0 & 32'h10000008;
+ assign T_6577 = T_6575 == 32'h10000008;
+ assign T_6579 = io_imem_resp_bits_data_0 & 32'h40000008;
+ assign T_6581 = T_6579 == 32'h40000008;
+ assign T_6583 = 1'h0 | T_6577;
+ assign T_6584 = T_6583 | T_6581;
+ assign T_6586 = io_imem_resp_bits_data_0 & 32'h8000008;
+ assign T_6588 = T_6586 == 32'h8000008;
+ assign T_6590 = io_imem_resp_bits_data_0 & 32'h80000008;
+ assign T_6592 = T_6590 == 32'h80000008;
+ assign T_6594 = 1'h0 | T_6588;
+ assign T_6595 = T_6594 | T_6577;
+ assign T_6596 = T_6595 | T_6592;
+ assign T_6598 = io_imem_resp_bits_data_0 & 32'h18000008;
+ assign T_6600 = T_6598 == 32'h8;
+ assign T_6602 = 1'h0 | T_6600;
+ assign T_6604 = {T_6584,T_6573};
+ assign T_6605 = {T_6596,T_6604};
+ assign T_6606 = {T_6602,T_6605};
+ assign T_6607 = {1'h0,T_6606};
+ assign T_6609 = io_imem_resp_bits_data_0 & 32'h1000;
+ assign T_6611 = T_6609 == 32'h1000;
+ assign T_6613 = 1'h0 | T_6611;
+ assign T_6615 = io_imem_resp_bits_data_0 & 32'h2000;
+ assign T_6617 = T_6615 == 32'h2000;
+ assign T_6619 = 1'h0 | T_6617;
+ assign T_6621 = io_imem_resp_bits_data_0 & 32'h4000;
+ assign T_6623 = T_6621 == 32'h4000;
+ assign T_6625 = 1'h0 | T_6623;
+ assign T_6626 = {T_6619,T_6613};
+ assign T_6627 = {T_6625,T_6626};
+ assign T_6629 = io_imem_resp_bits_data_0 & 32'h80000060;
+ assign T_6631 = T_6629 == 32'h40;
+ assign T_6633 = io_imem_resp_bits_data_0 & 32'h10000060;
+ assign T_6635 = T_6633 == 32'h40;
+ assign T_6637 = io_imem_resp_bits_data_0 & 32'h70;
+ assign T_6639 = T_6637 == 32'h40;
+ assign T_6641 = 1'h0 | T_6631;
+ assign T_6642 = T_6641 | T_6635;
+ assign T_6643 = T_6642 | T_6639;
+ assign T_6645 = io_imem_resp_bits_data_0 & 32'h7c;
+ assign T_6647 = T_6645 == 32'h24;
+ assign T_6649 = io_imem_resp_bits_data_0 & 32'h40000060;
+ assign T_6651 = T_6649 == 32'h40;
+ assign T_6653 = io_imem_resp_bits_data_0 & 32'h90000060;
+ assign T_6655 = T_6653 == 32'h10000040;
+ assign T_6657 = 1'h0 | T_6647;
+ assign T_6658 = T_6657 | T_6651;
+ assign T_6659 = T_6658 | T_6639;
+ assign T_6660 = T_6659 | T_6655;
+ assign T_6662 = 1'h0 | T_6639;
+ assign T_6664 = io_imem_resp_bits_data_0 & 32'h3c;
+ assign T_6666 = T_6664 == 32'h4;
+ assign T_6668 = io_imem_resp_bits_data_0 & 32'h10000060;
+ assign T_6670 = T_6668 == 32'h10000040;
+ assign T_6672 = 1'h0 | T_6666;
+ assign T_6673 = T_6672 | T_6631;
+ assign T_6674 = T_6673 | T_6639;
+ assign T_6675 = T_6674 | T_6670;
+ assign T_6677 = io_imem_resp_bits_data_0 & 32'h2000074;
+ assign T_6679 = T_6677 == 32'h2000030;
+ assign T_6681 = 1'h0 | T_6679;
+ assign T_6683 = io_imem_resp_bits_data_0 & 32'h64;
+ assign T_6685 = T_6683 == 32'h0;
+ assign T_6687 = io_imem_resp_bits_data_0 & 32'h50;
+ assign T_6689 = T_6687 == 32'h10;
+ assign T_6691 = io_imem_resp_bits_data_0 & 32'h2024;
+ assign T_6693 = T_6691 == 32'h24;
+ assign T_6695 = io_imem_resp_bits_data_0 & 32'h28;
+ assign T_6697 = T_6695 == 32'h28;
+ assign T_6699 = io_imem_resp_bits_data_0 & 32'h1030;
+ assign T_6701 = T_6699 == 32'h1030;
+ assign T_6703 = io_imem_resp_bits_data_0 & 32'h2030;
+ assign T_6705 = T_6703 == 32'h2030;
+ assign T_6707 = io_imem_resp_bits_data_0 & 32'h90000010;
+ assign T_6709 = T_6707 == 32'h80000010;
+ assign T_6711 = 1'h0 | T_6685;
+ assign T_6712 = T_6711 | T_6689;
+ assign T_6713 = T_6712 | T_6693;
+ assign T_6714 = T_6713 | T_6697;
+ assign T_6715 = T_6714 | T_6701;
+ assign T_6716 = T_6715 | T_6705;
+ assign T_6717 = T_6716 | T_6709;
+ assign T_6719 = io_imem_resp_bits_data_0 & 32'h1070;
+ assign T_6721 = T_6719 == 32'h1070;
+ assign T_6723 = 1'h0 | T_6721;
+ assign T_6725 = io_imem_resp_bits_data_0 & 32'h2070;
+ assign T_6727 = T_6725 == 32'h2070;
+ assign T_6729 = 1'h0 | T_6727;
+ assign T_6731 = io_imem_resp_bits_data_0 & 32'h3070;
+ assign T_6733 = T_6731 == 32'h70;
+ assign T_6735 = 1'h0 | T_6733;
+ assign T_6736 = {T_6729,T_6723};
+ assign T_6737 = {T_6735,T_6736};
+ assign T_6739 = io_imem_resp_bits_data_0 & 32'h3058;
+ assign T_6741 = T_6739 == 32'h1008;
+ assign T_6743 = 1'h0 | T_6741;
+ assign T_6745 = io_imem_resp_bits_data_0 & 32'h3058;
+ assign T_6747 = T_6745 == 32'h8;
+ assign T_6749 = 1'h0 | T_6747;
+ assign T_6751 = io_imem_resp_bits_data_0 & 32'h6048;
+ assign T_6753 = T_6751 == 32'h2008;
+ assign T_6755 = 1'h0 | T_6753;
+ assign id_raddr3 = io_imem_resp_bits_data_0[31:27];
+ assign id_raddr2 = io_imem_resp_bits_data_0[24:20];
+ assign id_raddr1 = io_imem_resp_bits_data_0[19:15];
+ assign id_waddr = io_imem_resp_bits_data_0[11:7];
+ assign id_load_use = T_7611;
+ assign T_6766_T_6776_addr = T_6775;
+ assign T_6766_T_6776_en = 1'h1;
+ assign T_6766_T_6776_clk = clk;
+ assign T_6766_T_6776_data = T_6766[T_6766_T_6776_addr];
+ assign T_6766_T_6787_addr = T_6786;
+ assign T_6766_T_6787_en = 1'h1;
+ assign T_6766_T_6787_clk = clk;
+ assign T_6766_T_6787_data = T_6766[T_6766_T_6787_addr];
+ assign T_6766_T_7490_data = rf_wdata;
+ assign T_6766_T_7490_addr = T_7489;
+ assign T_6766_T_7490_mask = rf_wen ? T_7487 ? 1'h1 : 1'h0 : 1'h0;
+ assign T_6766_T_7490_en = rf_wen ? T_7487 ? 1'h1 : 1'h0 : 1'h0;
+ assign T_6766_T_7490_clk = clk;
+ assign T_6768 = rf_wen ? T_7487 ? T_7491 ? rf_wdata : T_6777 : T_6777 : T_6777;
+ assign T_6771 = id_raddr1 == 1'h0;
+ assign T_6772 = 1'h0 & T_6771;
+ assign T_6774 = id_raddr1;
+ assign T_6775 = ~ T_6774;
+ assign T_6777 = T_6772 ? 1'h0 : T_6766_T_6776_data;
+ assign T_6779 = rf_wen ? T_7487 ? T_7492 ? rf_wdata : T_6788 : T_6788 : T_6788;
+ assign T_6782 = id_raddr2 == 1'h0;
+ assign T_6783 = 1'h0 & T_6782;
+ assign T_6785 = id_raddr2;
+ assign T_6786 = ~ T_6785;
+ assign T_6788 = T_6783 ? 1'h0 : T_6766_T_6787_data;
+ assign ctrl_killd = T_7704;
+ assign csr_clk = clk;
+ assign csr_reset = reset;
+ assign csr_io_host_reset = io_host_reset;
+ assign csr_io_host_id = io_host_id;
+ assign csr_io_host_csr_req_valid = io_host_csr_req_valid;
+ assign csr_io_host_csr_req_bits_rw = io_host_csr_req_bits_rw;
+ assign csr_io_host_csr_req_bits_addr = io_host_csr_req_bits_addr;
+ assign csr_io_host_csr_req_bits_data = io_host_csr_req_bits_data;
+ assign csr_io_host_csr_resp_ready = io_host_csr_resp_ready;
+ assign csr_io_rw_addr = T_7509;
+ assign csr_io_rw_cmd = T_7510;
+ assign csr_io_rw_wdata = wb_reg_wdata;
+ assign csr_io_exception = wb_reg_xcpt;
+ assign csr_io_retire = wb_valid;
+ assign csr_io_uarch_counters_0 = 1'h0;
+ assign csr_io_uarch_counters_1 = 1'h0;
+ assign csr_io_uarch_counters_2 = 1'h0;
+ assign csr_io_uarch_counters_3 = 1'h0;
+ assign csr_io_uarch_counters_4 = 1'h0;
+ assign csr_io_uarch_counters_5 = 1'h0;
+ assign csr_io_uarch_counters_6 = 1'h0;
+ assign csr_io_uarch_counters_7 = 1'h0;
+ assign csr_io_uarch_counters_8 = 1'h0;
+ assign csr_io_uarch_counters_9 = 1'h0;
+ assign csr_io_uarch_counters_10 = 1'h0;
+ assign csr_io_uarch_counters_11 = 1'h0;
+ assign csr_io_uarch_counters_12 = 1'h0;
+ assign csr_io_uarch_counters_13 = 1'h0;
+ assign csr_io_uarch_counters_14 = 1'h0;
+ assign csr_io_uarch_counters_15 = 1'h0;
+ assign csr_io_cause = wb_reg_cause;
+ assign csr_io_pc = wb_reg_pc;
+ assign csr_io_fcsr_flags_valid = io_fpu_fcsr_flags_valid;
+ assign csr_io_fcsr_flags_bits = io_fpu_fcsr_flags_bits;
+ assign csr_io_rocc_cmd_ready = io_rocc_cmd_ready;
+ assign csr_io_rocc_resp_valid = io_rocc_resp_valid;
+ assign csr_io_rocc_resp_bits_rd = io_rocc_resp_bits_rd;
+ assign csr_io_rocc_resp_bits_data = io_rocc_resp_bits_data;
+ assign csr_io_rocc_mem_req_valid = io_rocc_mem_req_valid;
+ assign csr_io_rocc_mem_req_bits_addr = io_rocc_mem_req_bits_addr;
+ assign csr_io_rocc_mem_req_bits_tag = io_rocc_mem_req_bits_tag;
+ assign csr_io_rocc_mem_req_bits_cmd = io_rocc_mem_req_bits_cmd;
+ assign csr_io_rocc_mem_req_bits_typ = io_rocc_mem_req_bits_typ;
+ assign csr_io_rocc_mem_req_bits_kill = io_rocc_mem_req_bits_kill;
+ assign csr_io_rocc_mem_req_bits_phys = io_rocc_mem_req_bits_phys;
+ assign csr_io_rocc_mem_req_bits_data = io_rocc_mem_req_bits_data;
+ assign csr_io_rocc_mem_invalidate_lr = io_rocc_mem_invalidate_lr;
+ assign csr_io_rocc_busy = io_rocc_busy;
+ assign csr_io_rocc_interrupt = io_rocc_interrupt;
+ assign csr_io_rocc_autl_acquire_valid = io_rocc_autl_acquire_valid;
+ assign csr_io_rocc_autl_acquire_bits_addr_block = io_rocc_autl_acquire_bits_addr_block;
+ assign csr_io_rocc_autl_acquire_bits_client_xact_id = io_rocc_autl_acquire_bits_client_xact_id;
+ assign csr_io_rocc_autl_acquire_bits_addr_beat = io_rocc_autl_acquire_bits_addr_beat;
+ assign csr_io_rocc_autl_acquire_bits_is_builtin_type = io_rocc_autl_acquire_bits_is_builtin_type;
+ assign csr_io_rocc_autl_acquire_bits_a_type = io_rocc_autl_acquire_bits_a_type;
+ assign csr_io_rocc_autl_acquire_bits_union = io_rocc_autl_acquire_bits_union;
+ assign csr_io_rocc_autl_acquire_bits_data = io_rocc_autl_acquire_bits_data;
+ assign csr_io_rocc_autl_grant_ready = io_rocc_autl_grant_ready;
+ assign csr_io_rocc_iptw_req_valid = io_rocc_iptw_req_valid;
+ assign csr_io_rocc_iptw_req_bits_addr = io_rocc_iptw_req_bits_addr;
+ assign csr_io_rocc_iptw_req_bits_prv = io_rocc_iptw_req_bits_prv;
+ assign csr_io_rocc_iptw_req_bits_store = io_rocc_iptw_req_bits_store;
+ assign csr_io_rocc_iptw_req_bits_fetch = io_rocc_iptw_req_bits_fetch;
+ assign csr_io_rocc_dptw_req_valid = io_rocc_dptw_req_valid;
+ assign csr_io_rocc_dptw_req_bits_addr = io_rocc_dptw_req_bits_addr;
+ assign csr_io_rocc_dptw_req_bits_prv = io_rocc_dptw_req_bits_prv;
+ assign csr_io_rocc_dptw_req_bits_store = io_rocc_dptw_req_bits_store;
+ assign csr_io_rocc_dptw_req_bits_fetch = io_rocc_dptw_req_bits_fetch;
+ assign csr_io_rocc_pptw_req_valid = io_rocc_pptw_req_valid;
+ assign csr_io_rocc_pptw_req_bits_addr = io_rocc_pptw_req_bits_addr;
+ assign csr_io_rocc_pptw_req_bits_prv = io_rocc_pptw_req_bits_prv;
+ assign csr_io_rocc_pptw_req_bits_store = io_rocc_pptw_req_bits_store;
+ assign csr_io_rocc_pptw_req_bits_fetch = io_rocc_pptw_req_bits_fetch;
+ assign csr_io_rocc_fpu_req_valid = io_rocc_fpu_req_valid;
+ assign csr_io_rocc_fpu_req_bits_cmd = io_rocc_fpu_req_bits_cmd;
+ assign csr_io_rocc_fpu_req_bits_ldst = io_rocc_fpu_req_bits_ldst;
+ assign csr_io_rocc_fpu_req_bits_wen = io_rocc_fpu_req_bits_wen;
+ assign csr_io_rocc_fpu_req_bits_ren1 = io_rocc_fpu_req_bits_ren1;
+ assign csr_io_rocc_fpu_req_bits_ren2 = io_rocc_fpu_req_bits_ren2;
+ assign csr_io_rocc_fpu_req_bits_ren3 = io_rocc_fpu_req_bits_ren3;
+ assign csr_io_rocc_fpu_req_bits_swap12 = io_rocc_fpu_req_bits_swap12;
+ assign csr_io_rocc_fpu_req_bits_swap23 = io_rocc_fpu_req_bits_swap23;
+ assign csr_io_rocc_fpu_req_bits_single = io_rocc_fpu_req_bits_single;
+ assign csr_io_rocc_fpu_req_bits_fromint = io_rocc_fpu_req_bits_fromint;
+ assign csr_io_rocc_fpu_req_bits_toint = io_rocc_fpu_req_bits_toint;
+ assign csr_io_rocc_fpu_req_bits_fastpipe = io_rocc_fpu_req_bits_fastpipe;
+ assign csr_io_rocc_fpu_req_bits_fma = io_rocc_fpu_req_bits_fma;
+ assign csr_io_rocc_fpu_req_bits_div = io_rocc_fpu_req_bits_div;
+ assign csr_io_rocc_fpu_req_bits_sqrt = io_rocc_fpu_req_bits_sqrt;
+ assign csr_io_rocc_fpu_req_bits_round = io_rocc_fpu_req_bits_round;
+ assign csr_io_rocc_fpu_req_bits_wflags = io_rocc_fpu_req_bits_wflags;
+ assign csr_io_rocc_fpu_req_bits_rm = io_rocc_fpu_req_bits_rm;
+ assign csr_io_rocc_fpu_req_bits_typ = io_rocc_fpu_req_bits_typ;
+ assign csr_io_rocc_fpu_req_bits_in1 = io_rocc_fpu_req_bits_in1;
+ assign csr_io_rocc_fpu_req_bits_in2 = io_rocc_fpu_req_bits_in2;
+ assign csr_io_rocc_fpu_req_bits_in3 = io_rocc_fpu_req_bits_in3;
+ assign csr_io_rocc_fpu_resp_ready = io_rocc_fpu_resp_ready;
+ assign csr_io_rocc_dma_req_valid = io_rocc_dma_req_valid;
+ assign csr_io_rocc_dma_req_bits_client_xact_id = io_rocc_dma_req_bits_client_xact_id;
+ assign csr_io_rocc_dma_req_bits_cmd = io_rocc_dma_req_bits_cmd;
+ assign csr_io_rocc_dma_req_bits_source = io_rocc_dma_req_bits_source;
+ assign csr_io_rocc_dma_req_bits_dest = io_rocc_dma_req_bits_dest;
+ assign csr_io_rocc_dma_req_bits_length = io_rocc_dma_req_bits_length;
+ assign csr_io_rocc_dma_req_bits_size = io_rocc_dma_req_bits_size;
+ assign csr_io_rocc_dma_resp_ready = io_rocc_dma_resp_ready;
+ assign id_csr_en = id_ctrl_csr != 3'h0;
+ assign id_system_insn = id_ctrl_csr == 3'h4;
+ assign T_6794 = id_ctrl_csr == 3'h2;
+ assign T_6795 = id_ctrl_csr == 3'h3;
+ assign T_6796 = T_6794 | T_6795;
+ assign T_6798 = id_raddr1 == 1'h0;
+ assign id_csr_ren = T_6796 & T_6798;
+ assign id_csr = id_csr_ren ? 3'h5 : id_ctrl_csr;
+ assign id_csr_addr = io_imem_resp_bits_data_0[31:20];
+ assign T_6803 = id_csr_ren == 1'h0;
+ assign T_6804 = id_csr_en & T_6803;
+ assign T_6863 = id_csr_addr & 12'h8c4;
+ assign T_6865 = T_6863 == 12'h40;
+ assign T_6867 = 1'h0 | T_6865;
+ assign T_6868 = T_6867;
+ assign T_6870 = T_6868 == 1'h0;
+ assign T_6871 = T_6804 & T_6870;
+ assign id_csr_flush = id_system_insn | T_6871;
+ assign T_6874 = id_ctrl_legal == 1'h0;
+ assign T_6876 = csr_io_status_fs != 1'h0;
+ assign T_6878 = T_6876 == 1'h0;
+ assign T_6879 = id_ctrl_fp & T_6878;
+ assign T_6880 = T_6874 | T_6879;
+ assign T_6882 = csr_io_status_xs != 1'h0;
+ assign T_6884 = T_6882 == 1'h0;
+ assign T_6885 = id_ctrl_rocc & T_6884;
+ assign id_illegal_insn = T_6880 | T_6885;
+ assign id_amo_aq = io_imem_resp_bits_data_0[26];
+ assign id_amo_rl = io_imem_resp_bits_data_0[25];
+ assign T_6889 = id_ctrl_amo & id_amo_rl;
+ assign id_fence_next = id_ctrl_fence | T_6889;
+ assign T_6892 = io_dmem_ordered == 1'h0;
+ assign id_mem_busy = T_6892 | io_dmem_req_valid;
+ assign T_6895 = ex_reg_valid & ex_ctrl_rocc;
+ assign T_6896 = io_rocc_busy | T_6895;
+ assign T_6897 = mem_reg_valid & mem_ctrl_rocc;
+ assign T_6898 = T_6896 | T_6897;
+ assign T_6899 = wb_reg_valid & wb_ctrl_rocc;
+ assign T_6900 = T_6898 | T_6899;
+ assign id_rocc_busy = 1'h0 & T_6900;
+ assign T_6902 = id_reg_fence & id_mem_busy;
+ assign T_6903 = id_fence_next | T_6902;
+ assign T_6904 = id_rocc_busy & id_ctrl_fence;
+ assign T_6905 = id_ctrl_amo & id_amo_aq;
+ assign T_6906 = T_6905 | id_ctrl_fence_i;
+ assign T_6907 = id_ctrl_mem | id_ctrl_rocc;
+ assign T_6908 = id_reg_fence & T_6907;
+ assign T_6909 = T_6906 | T_6908;
+ assign T_6910 = T_6909 | id_csr_en;
+ assign T_6911 = id_mem_busy & T_6910;
+ assign id_do_fence = T_6904 | T_6911;
+ assign T_6915 = csr_io_interrupt | io_imem_resp_bits_xcpt_if;
+ assign id_xcpt = T_6915 | id_illegal_insn;
+ assign T_6917 = io_imem_resp_bits_xcpt_if ? 1'h1 : 2'h2;
+ assign id_cause = csr_io_interrupt ? csr_io_interrupt_cause : T_6917;
+ assign ex_waddr = ex_reg_inst[11:7];
+ assign mem_waddr = mem_reg_inst[11:7];
+ assign wb_waddr = wb_reg_inst[11:7];
+ assign T_6925 = ex_reg_valid & ex_ctrl_wxd;
+ assign T_6926 = mem_reg_valid & mem_ctrl_wxd;
+ assign T_6928 = mem_ctrl_mem == 1'h0;
+ assign T_6929 = T_6926 & T_6928;
+ assign T_6930 = mem_reg_valid & mem_ctrl_wxd;
+ assign T_6931 = 1'h0 == id_raddr1;
+ assign T_6932 = 1'h1 & T_6931;
+ assign T_6933 = ex_waddr == id_raddr1;
+ assign T_6934 = T_6925 & T_6933;
+ assign T_6935 = mem_waddr == id_raddr1;
+ assign T_6936 = T_6929 & T_6935;
+ assign T_6937 = mem_waddr == id_raddr1;
+ assign T_6938 = T_6930 & T_6937;
+ assign T_6939 = 1'h0 == id_raddr2;
+ assign T_6940 = 1'h1 & T_6939;
+ assign T_6941 = ex_waddr == id_raddr2;
+ assign T_6942 = T_6925 & T_6941;
+ assign T_6943 = mem_waddr == id_raddr2;
+ assign T_6944 = T_6929 & T_6943;
+ assign T_6945 = mem_waddr == id_raddr2;
+ assign T_6946 = T_6930 & T_6945;
+ assign bypass_mux_0 = 1'h0;
+ assign bypass_mux_1 = mem_reg_wdata;
+ assign bypass_mux_2 = wb_reg_wdata;
+ assign bypass_mux_3 = io_dmem_resp_bits_data_word_bypass;
+ assign T_6991 = {ex_reg_rs_msb_0,ex_reg_rs_lsb_0};
+ assign GEN_0 = GEN_19 ? bypass_mux_3 : GEN_20 ? bypass_mux_2 : GEN_21 ? bypass_mux_1 : bypass_mux_0;
+ assign T_6992 = ex_reg_rs_bypass_0 ? GEN_0 : T_6991;
+ assign T_6994 = {ex_reg_rs_msb_1,ex_reg_rs_lsb_1};
+ assign GEN_1 = GEN_22 ? bypass_mux_3 : GEN_23 ? bypass_mux_2 : GEN_24 ? bypass_mux_1 : bypass_mux_0;
+ assign T_6995 = ex_reg_rs_bypass_1 ? GEN_1 : T_6994;
+ assign T_6996 = ex_ctrl_sel_imm == 3'h5;
+ assign T_6998 = ex_reg_inst[31];
+ assign T_6999 = $signed(T_6998);
+ assign GEN_2 = $signed(1'h0);
+ assign T_7000 = T_6996 ? $signed(GEN_2) : $signed(T_6999);
+ assign T_7001 = ex_ctrl_sel_imm == 3'h2;
+ assign T_7002 = ex_reg_inst[30:20];
+ assign T_7003 = $signed(T_7002);
+ assign T_7004 = T_7001 ? $signed(T_7003) : $signed(T_7000);
+ assign T_7005 = ex_ctrl_sel_imm != 3'h2;
+ assign T_7006 = ex_ctrl_sel_imm != 3'h3;
+ assign T_7007 = T_7005 & T_7006;
+ assign T_7008 = ex_reg_inst[19:12];
+ assign T_7009 = $signed(T_7008);
+ assign T_7010 = T_7007 ? $signed(T_7000) : $signed(T_7009);
+ assign T_7011 = ex_ctrl_sel_imm == 3'h2;
+ assign T_7012 = ex_ctrl_sel_imm == 3'h5;
+ assign T_7013 = T_7011 | T_7012;
+ assign T_7015 = ex_ctrl_sel_imm == 3'h3;
+ assign T_7016 = ex_reg_inst[20];
+ assign T_7017 = $signed(T_7016);
+ assign T_7018 = ex_ctrl_sel_imm == 3'h1;
+ assign T_7019 = ex_reg_inst[7];
+ assign T_7020 = $signed(T_7019);
+ assign T_7021 = T_7018 ? $signed(T_7020) : $signed(T_7000);
+ assign T_7022 = T_7015 ? $signed(T_7017) : $signed(T_7021);
+ assign GEN_3 = $signed(1'h0);
+ assign T_7023 = T_7013 ? $signed(GEN_3) : $signed(T_7022);
+ assign T_7024 = ex_ctrl_sel_imm == 3'h2;
+ assign T_7025 = ex_ctrl_sel_imm == 3'h5;
+ assign T_7026 = T_7024 | T_7025;
+ assign T_7028 = ex_reg_inst[30:25];
+ assign T_7029 = T_7026 ? 1'h0 : T_7028;
+ assign T_7030 = ex_ctrl_sel_imm == 3'h2;
+ assign T_7032 = ex_ctrl_sel_imm == 3'h0;
+ assign T_7033 = ex_ctrl_sel_imm == 3'h1;
+ assign T_7034 = T_7032 | T_7033;
+ assign T_7035 = ex_reg_inst[11:8];
+ assign T_7036 = ex_ctrl_sel_imm == 3'h5;
+ assign T_7037 = ex_reg_inst[19:16];
+ assign T_7038 = ex_reg_inst[24:21];
+ assign T_7039 = T_7036 ? T_7037 : T_7038;
+ assign T_7040 = T_7034 ? T_7035 : T_7039;
+ assign T_7041 = T_7030 ? 1'h0 : T_7040;
+ assign T_7042 = ex_ctrl_sel_imm == 3'h0;
+ assign T_7043 = ex_reg_inst[7];
+ assign T_7044 = ex_ctrl_sel_imm == 3'h4;
+ assign T_7045 = ex_reg_inst[20];
+ assign T_7046 = ex_ctrl_sel_imm == 3'h5;
+ assign T_7047 = ex_reg_inst[15];
+ assign T_7049 = T_7047 << 0;
+ assign T_7050 = T_7046 ? T_7049 : 1'h0;
+ assign T_7051 = T_7045 << 0;
+ assign T_7052 = T_7044 ? T_7051 : T_7050;
+ assign T_7053 = T_7043 << 0;
+ assign T_7054 = T_7042 ? T_7053 : T_7052;
+ assign T_7055 = $unsigned(T_7000);
+ assign T_7056 = $unsigned(T_7004);
+ assign T_7057 = $unsigned(T_7010);
+ assign T_7058 = {T_7056,T_7057};
+ assign T_7059 = {T_7055,T_7058};
+ assign T_7060 = $unsigned(T_7023);
+ assign T_7061 = {T_7060,T_7029};
+ assign T_7062 = {T_7041,T_7054};
+ assign T_7063 = {T_7061,T_7062};
+ assign T_7064 = {T_7059,T_7063};
+ assign ex_imm = $signed(T_7064);
+ assign T_7067 = $signed(T_6992);
+ assign T_7068 = $signed(ex_reg_pc);
+ assign T_7069 = 2'h2 == ex_ctrl_sel_alu1;
+ assign GEN_4 = $signed(1'h0);
+ assign T_7070 = T_7069 ? $signed(T_7068) : $signed(GEN_4);
+ assign T_7071 = 2'h1 == ex_ctrl_sel_alu1;
+ assign ex_op1 = T_7071 ? $signed(T_7067) : $signed(T_7070);
+ assign T_7074 = $signed(T_6995);
+ assign T_7076 = 2'h1 == ex_ctrl_sel_alu2;
+ assign GEN_5 = $signed(4'h4);
+ assign GEN_6 = $signed(1'h0);
+ assign T_7077 = T_7076 ? $signed(GEN_5) : $signed(GEN_6);
+ assign T_7078 = 2'h3 == ex_ctrl_sel_alu2;
+ assign T_7079 = T_7078 ? $signed(ex_imm) : $signed(T_7077);
+ assign T_7080 = 2'h2 == ex_ctrl_sel_alu2;
+ assign ex_op2 = T_7080 ? $signed(T_7074) : $signed(T_7079);
+ assign alu_clk = clk;
+ assign alu_reset = reset;
+ assign alu_io_dw = ex_ctrl_alu_dw;
+ assign alu_io_fn = ex_ctrl_alu_fn;
+ assign alu_io_in2 = T_7083;
+ assign alu_io_in1 = T_7084;
+ assign T_7083 = $unsigned(ex_op2);
+ assign T_7084 = $unsigned(ex_op1);
+ assign div_clk = clk;
+ assign div_reset = reset;
+ assign div_io_req_valid = T_7086;
+ assign div_io_req_bits_fn = ex_ctrl_alu_fn;
+ assign div_io_req_bits_dw = ex_ctrl_alu_dw;
+ assign div_io_req_bits_in1 = T_6992;
+ assign div_io_req_bits_in2 = T_6995;
+ assign div_io_req_bits_tag = ex_waddr;
+ assign div_io_kill = T_7420;
+ assign div_io_resp_ready = T_7469 ? 1'h0 : T_7464;
+ assign T_7086 = ex_reg_valid & ex_ctrl_div;
+ assign T_7088 = ctrl_killd == 1'h0;
+ assign T_7090 = ctrl_killd == 1'h0;
+ assign T_7091 = T_7090 & id_xcpt;
+ assign T_7093 = take_pc_mem_wb == 1'h0;
+ assign T_7094 = csr_io_interrupt & T_7093;
+ assign T_7095 = T_7094 & io_imem_resp_valid;
+ assign T_7097 = ctrl_killd == 1'h0;
+ assign T_7098 = id_ctrl_fence_i | id_csr_flush;
+ assign T_7099 = T_6932 | T_6934;
+ assign T_7100 = T_7099 | T_6936;
+ assign T_7101 = T_7100 | T_6938;
+ assign T_7106 = T_6936 ? 2'h2 : 2'h3;
+ assign T_7107 = T_6934 ? 1'h1 : T_7106;
+ assign T_7108 = T_6932 ? 1'h0 : T_7107;
+ assign T_7110 = T_7101 == 1'h0;
+ assign T_7111 = id_ctrl_rxs1 & T_7110;
+ assign T_7112 = T_6768[1:0];
+ assign T_7113 = T_6768[63:2];
+ assign T_7114 = T_6940 | T_6942;
+ assign T_7115 = T_7114 | T_6944;
+ assign T_7116 = T_7115 | T_6946;
+ assign T_7121 = T_6944 ? 2'h2 : 2'h3;
+ assign T_7122 = T_6942 ? 1'h1 : T_7121;
+ assign T_7123 = T_6940 ? 1'h0 : T_7122;
+ assign T_7125 = T_7116 == 1'h0;
+ assign T_7126 = id_ctrl_rxs2 & T_7125;
+ assign T_7127 = T_6779[1:0];
+ assign T_7128 = T_6779[63:2];
+ assign T_7130 = ctrl_killd == 1'h0;
+ assign T_7131 = T_7130 | csr_io_interrupt;
+ assign T_7133 = io_dmem_resp_valid == 1'h0;
+ assign wb_dcache_miss = wb_ctrl_mem & T_7133;
+ assign T_7136 = io_dmem_req_ready == 1'h0;
+ assign T_7137 = ex_ctrl_mem & T_7136;
+ assign T_7139 = div_io_req_ready == 1'h0;
+ assign T_7140 = ex_ctrl_div & T_7139;
+ assign replay_ex_structural = T_7137 | T_7140;
+ assign replay_ex_load_use = wb_dcache_miss & ex_reg_load_use;
+ assign T_7143 = replay_ex_structural | replay_ex_load_use;
+ assign replay_ex = ex_reg_valid & T_7143;
+ assign T_7145 = take_pc_mem_wb | replay_ex;
+ assign T_7147 = ex_reg_valid == 1'h0;
+ assign ctrl_killx = T_7145 | T_7147;
+ assign T_7149 = ex_ctrl_mem_cmd == 5'h7;
+ assign T_7151_0 = 3'h0;
+ assign T_7151_1 = 3'h4;
+ assign T_7151_2 = 3'h1;
+ assign T_7151_3 = 3'h5;
+ assign T_7157 = T_7151_0 == ex_ctrl_mem_type;
+ assign T_7158 = T_7151_1 == ex_ctrl_mem_type;
+ assign T_7159 = T_7151_2 == ex_ctrl_mem_type;
+ assign T_7160 = T_7151_3 == ex_ctrl_mem_type;
+ assign T_7162 = 1'h0 | T_7157;
+ assign T_7163 = T_7162 | T_7158;
+ assign T_7164 = T_7163 | T_7159;
+ assign T_7165 = T_7164 | T_7160;
+ assign ex_slow_bypass = T_7149 | T_7165;
+ assign T_7167 = ex_reg_xcpt_interrupt | ex_reg_xcpt;
+ assign T_7168 = ex_ctrl_fp & io_fpu_illegal_rm;
+ assign ex_xcpt = T_7167 | T_7168;
+ assign ex_cause = T_7167 ? ex_reg_cause : 2'h2;
+ assign mem_br_taken = mem_reg_wdata[0];
+ assign T_7173 = $signed(mem_reg_pc);
+ assign T_7174 = mem_ctrl_branch & mem_br_taken;
+ assign T_7175 = 3'h1 == 3'h5;
+ assign T_7177 = mem_reg_inst[31];
+ assign T_7178 = $signed(T_7177);
+ assign GEN_7 = $signed(1'h0);
+ assign T_7179 = T_7175 ? $signed(GEN_7) : $signed(T_7178);
+ assign T_7180 = 3'h1 == 3'h2;
+ assign T_7181 = mem_reg_inst[30:20];
+ assign T_7182 = $signed(T_7181);
+ assign T_7183 = T_7180 ? $signed(T_7182) : $signed(T_7179);
+ assign T_7184 = 3'h1 != 3'h2;
+ assign T_7185 = 3'h1 != 3'h3;
+ assign T_7186 = T_7184 & T_7185;
+ assign T_7187 = mem_reg_inst[19:12];
+ assign T_7188 = $signed(T_7187);
+ assign T_7189 = T_7186 ? $signed(T_7179) : $signed(T_7188);
+ assign T_7190 = 3'h1 == 3'h2;
+ assign T_7191 = 3'h1 == 3'h5;
+ assign T_7192 = T_7190 | T_7191;
+ assign T_7194 = 3'h1 == 3'h3;
+ assign T_7195 = mem_reg_inst[20];
+ assign T_7196 = $signed(T_7195);
+ assign T_7197 = 3'h1 == 3'h1;
+ assign T_7198 = mem_reg_inst[7];
+ assign T_7199 = $signed(T_7198);
+ assign T_7200 = T_7197 ? $signed(T_7199) : $signed(T_7179);
+ assign T_7201 = T_7194 ? $signed(T_7196) : $signed(T_7200);
+ assign GEN_8 = $signed(1'h0);
+ assign T_7202 = T_7192 ? $signed(GEN_8) : $signed(T_7201);
+ assign T_7203 = 3'h1 == 3'h2;
+ assign T_7204 = 3'h1 == 3'h5;
+ assign T_7205 = T_7203 | T_7204;
+ assign T_7207 = mem_reg_inst[30:25];
+ assign T_7208 = T_7205 ? 1'h0 : T_7207;
+ assign T_7209 = 3'h1 == 3'h2;
+ assign T_7211 = 3'h1 == 3'h0;
+ assign T_7212 = 3'h1 == 3'h1;
+ assign T_7213 = T_7211 | T_7212;
+ assign T_7214 = mem_reg_inst[11:8];
+ assign T_7215 = 3'h1 == 3'h5;
+ assign T_7216 = mem_reg_inst[19:16];
+ assign T_7217 = mem_reg_inst[24:21];
+ assign T_7218 = T_7215 ? T_7216 : T_7217;
+ assign T_7219 = T_7213 ? T_7214 : T_7218;
+ assign T_7220 = T_7209 ? 1'h0 : T_7219;
+ assign T_7221 = 3'h1 == 3'h0;
+ assign T_7222 = mem_reg_inst[7];
+ assign T_7223 = 3'h1 == 3'h4;
+ assign T_7224 = mem_reg_inst[20];
+ assign T_7225 = 3'h1 == 3'h5;
+ assign T_7226 = mem_reg_inst[15];
+ assign T_7228 = T_7226 << 0;
+ assign T_7229 = T_7225 ? T_7228 : 1'h0;
+ assign T_7230 = T_7224 << 0;
+ assign T_7231 = T_7223 ? T_7230 : T_7229;
+ assign T_7232 = T_7222 << 0;
+ assign T_7233 = T_7221 ? T_7232 : T_7231;
+ assign T_7234 = $unsigned(T_7179);
+ assign T_7235 = $unsigned(T_7183);
+ assign T_7236 = $unsigned(T_7189);
+ assign T_7237 = {T_7235,T_7236};
+ assign T_7238 = {T_7234,T_7237};
+ assign T_7239 = $unsigned(T_7202);
+ assign T_7240 = {T_7239,T_7208};
+ assign T_7241 = {T_7220,T_7233};
+ assign T_7242 = {T_7240,T_7241};
+ assign T_7243 = {T_7238,T_7242};
+ assign T_7244 = $signed(T_7243);
+ assign T_7245 = 3'h3 == 3'h5;
+ assign T_7247 = mem_reg_inst[31];
+ assign T_7248 = $signed(T_7247);
+ assign GEN_9 = $signed(1'h0);
+ assign T_7249 = T_7245 ? $signed(GEN_9) : $signed(T_7248);
+ assign T_7250 = 3'h3 == 3'h2;
+ assign T_7251 = mem_reg_inst[30:20];
+ assign T_7252 = $signed(T_7251);
+ assign T_7253 = T_7250 ? $signed(T_7252) : $signed(T_7249);
+ assign T_7254 = 3'h3 != 3'h2;
+ assign T_7255 = 3'h3 != 3'h3;
+ assign T_7256 = T_7254 & T_7255;
+ assign T_7257 = mem_reg_inst[19:12];
+ assign T_7258 = $signed(T_7257);
+ assign T_7259 = T_7256 ? $signed(T_7249) : $signed(T_7258);
+ assign T_7260 = 3'h3 == 3'h2;
+ assign T_7261 = 3'h3 == 3'h5;
+ assign T_7262 = T_7260 | T_7261;
+ assign T_7264 = 3'h3 == 3'h3;
+ assign T_7265 = mem_reg_inst[20];
+ assign T_7266 = $signed(T_7265);
+ assign T_7267 = 3'h3 == 3'h1;
+ assign T_7268 = mem_reg_inst[7];
+ assign T_7269 = $signed(T_7268);
+ assign T_7270 = T_7267 ? $signed(T_7269) : $signed(T_7249);
+ assign T_7271 = T_7264 ? $signed(T_7266) : $signed(T_7270);
+ assign GEN_10 = $signed(1'h0);
+ assign T_7272 = T_7262 ? $signed(GEN_10) : $signed(T_7271);
+ assign T_7273 = 3'h3 == 3'h2;
+ assign T_7274 = 3'h3 == 3'h5;
+ assign T_7275 = T_7273 | T_7274;
+ assign T_7277 = mem_reg_inst[30:25];
+ assign T_7278 = T_7275 ? 1'h0 : T_7277;
+ assign T_7279 = 3'h3 == 3'h2;
+ assign T_7281 = 3'h3 == 3'h0;
+ assign T_7282 = 3'h3 == 3'h1;
+ assign T_7283 = T_7281 | T_7282;
+ assign T_7284 = mem_reg_inst[11:8];
+ assign T_7285 = 3'h3 == 3'h5;
+ assign T_7286 = mem_reg_inst[19:16];
+ assign T_7287 = mem_reg_inst[24:21];
+ assign T_7288 = T_7285 ? T_7286 : T_7287;
+ assign T_7289 = T_7283 ? T_7284 : T_7288;
+ assign T_7290 = T_7279 ? 1'h0 : T_7289;
+ assign T_7291 = 3'h3 == 3'h0;
+ assign T_7292 = mem_reg_inst[7];
+ assign T_7293 = 3'h3 == 3'h4;
+ assign T_7294 = mem_reg_inst[20];
+ assign T_7295 = 3'h3 == 3'h5;
+ assign T_7296 = mem_reg_inst[15];
+ assign T_7298 = T_7296 << 0;
+ assign T_7299 = T_7295 ? T_7298 : 1'h0;
+ assign T_7300 = T_7294 << 0;
+ assign T_7301 = T_7293 ? T_7300 : T_7299;
+ assign T_7302 = T_7292 << 0;
+ assign T_7303 = T_7291 ? T_7302 : T_7301;
+ assign T_7304 = $unsigned(T_7249);
+ assign T_7305 = $unsigned(T_7253);
+ assign T_7306 = $unsigned(T_7259);
+ assign T_7307 = {T_7305,T_7306};
+ assign T_7308 = {T_7304,T_7307};
+ assign T_7309 = $unsigned(T_7272);
+ assign T_7310 = {T_7309,T_7278};
+ assign T_7311 = {T_7290,T_7303};
+ assign T_7312 = {T_7310,T_7311};
+ assign T_7313 = {T_7308,T_7312};
+ assign T_7314 = $signed(T_7313);
+ assign GEN_11 = $signed(4'h4);
+ assign T_7316 = mem_ctrl_jal ? $signed(T_7314) : $signed(GEN_11);
+ assign T_7317 = T_7174 ? $signed(T_7244) : $signed(T_7316);
+ assign T_7318 = $signed(T_7173) + $signed(T_7317);
+ assign T_7319 = T_7318[39:0];
+ assign mem_br_target = $signed(T_7319);
+ assign T_7321 = $signed(mem_reg_wdata);
+ assign T_7322 = mem_ctrl_jalr ? $signed(mem_br_target) : $signed(T_7321);
+ assign mem_int_wdata = $unsigned(T_7322);
+ assign T_7324 = mem_reg_wdata[63:38];
+ assign T_7325 = mem_reg_wdata[39:38];
+ assign T_7327 = T_7324 == 1'h0;
+ assign T_7329 = T_7324 == 1'h1;
+ assign T_7330 = T_7327 | T_7329;
+ assign T_7332 = T_7325 != 1'h0;
+ assign T_7333 = $signed(T_7324);
+ assign GEN_12 = $signed(1'h1);
+ assign T_7335 = $signed(T_7333) == $signed(GEN_12);
+ assign T_7336 = $signed(T_7324);
+ assign GEN_13 = $signed(2'h2);
+ assign T_7338 = $signed(T_7336) == $signed(GEN_13);
+ assign T_7339 = T_7335 | T_7338;
+ assign T_7340 = $signed(T_7325);
+ assign GEN_14 = $signed(1'h1);
+ assign T_7342 = $signed(T_7340) == $signed(GEN_14);
+ assign T_7343 = T_7325[0];
+ assign T_7344 = T_7339 ? T_7342 : T_7343;
+ assign T_7345 = T_7330 ? T_7332 : T_7344;
+ assign T_7346 = mem_reg_wdata[38:0];
+ assign T_7347 = {T_7345,T_7346};
+ assign T_7348 = $signed(T_7347);
+ assign T_7349 = mem_ctrl_jalr ? $signed(T_7348) : $signed(mem_br_target);
+ assign GEN_15 = $signed(2'h2);
+ assign T_7351 = $signed(T_7349) & $signed(GEN_15);
+ assign T_7352 = $signed(T_7351);
+ assign mem_npc = $unsigned(T_7352);
+ assign T_7354 = mem_npc != ex_reg_pc;
+ assign T_7356 = ex_reg_valid == 1'h0;
+ assign mem_wrong_npc = T_7354 | T_7356;
+ assign mem_npc_misaligned = mem_npc[1];
+ assign T_7359 = mem_wrong_npc & mem_reg_valid;
+ assign T_7360 = mem_ctrl_branch | mem_ctrl_jalr;
+ assign T_7361 = T_7360 | mem_ctrl_jal;
+ assign mem_misprediction = T_7359 & T_7361;
+ assign T_7363 = mem_misprediction | mem_reg_flush_pipe;
+ assign want_take_pc_mem = mem_reg_valid & T_7363;
+ assign T_7366 = mem_npc_misaligned == 1'h0;
+ assign T_7367 = want_take_pc_mem & T_7366;
+ assign T_7369 = ctrl_killx == 1'h0;
+ assign T_7371 = take_pc_mem_wb == 1'h0;
+ assign T_7372 = T_7371 & replay_ex;
+ assign T_7374 = ctrl_killx == 1'h0;
+ assign T_7375 = T_7374 & ex_xcpt;
+ assign T_7377 = take_pc_mem_wb == 1'h0;
+ assign T_7378 = T_7377 & ex_reg_xcpt_interrupt;
+ assign T_7379 = ex_reg_valid | ex_reg_xcpt_interrupt;
+ assign T_7380 = ex_ctrl_mem | ex_ctrl_rocc;
+ assign T_7381 = ex_ctrl_rxs2 & T_7380;
+ assign T_7382 = mem_reg_xcpt_interrupt | mem_reg_xcpt;
+ assign T_7383 = want_take_pc_mem & mem_npc_misaligned;
+ assign T_7385 = mem_reg_valid & mem_ctrl_mem;
+ assign T_7386 = T_7385 & io_dmem_xcpt_ma_st;
+ assign T_7388 = mem_reg_valid & mem_ctrl_mem;
+ assign T_7389 = T_7388 & io_dmem_xcpt_ma_ld;
+ assign T_7391 = mem_reg_valid & mem_ctrl_mem;
+ assign T_7392 = T_7391 & io_dmem_xcpt_pf_st;
+ assign T_7394 = mem_reg_valid & mem_ctrl_mem;
+ assign T_7395 = T_7394 & io_dmem_xcpt_pf_ld;
+ assign T_7397 = T_7382 | T_7383;
+ assign T_7398 = T_7397 | T_7386;
+ assign T_7399 = T_7398 | T_7389;
+ assign T_7400 = T_7399 | T_7392;
+ assign mem_xcpt = T_7400 | T_7395;
+ assign T_7402 = T_7392 ? 3'h7 : 3'h5;
+ assign T_7403 = T_7389 ? 3'h4 : T_7402;
+ assign T_7404 = T_7386 ? 3'h6 : T_7403;
+ assign T_7405 = T_7383 ? 1'h0 : T_7404;
+ assign mem_cause = T_7382 ? mem_reg_cause : T_7405;
+ assign T_7407 = mem_reg_valid & mem_ctrl_wxd;
+ assign dcache_kill_mem = T_7407 & io_dmem_replay_next_valid;
+ assign T_7409 = mem_reg_valid & mem_ctrl_fp;
+ assign fpu_kill_mem = T_7409 & io_fpu_nack_mem;
+ assign T_7411 = dcache_kill_mem | mem_reg_replay;
+ assign replay_mem = T_7411 | fpu_kill_mem;
+ assign T_7413 = dcache_kill_mem | take_pc_wb;
+ assign T_7414 = T_7413 | mem_reg_xcpt;
+ assign T_7416 = mem_reg_valid == 1'h0;
+ assign killm_common = T_7414 | T_7416;
+ assign T_7418 = div_io_req_ready & div_io_req_valid;
+ assign T_7420 = killm_common & T_7419;
+ assign T_7421 = killm_common | mem_xcpt;
+ assign ctrl_killm = T_7421 | fpu_kill_mem;
+ assign T_7424 = ctrl_killm == 1'h0;
+ assign T_7426 = take_pc_wb == 1'h0;
+ assign T_7427 = replay_mem & T_7426;
+ assign T_7429 = take_pc_wb == 1'h0;
+ assign T_7430 = mem_xcpt & T_7429;
+ assign T_7431 = mem_reg_valid | mem_reg_replay;
+ assign T_7432 = T_7431 | mem_reg_xcpt_interrupt;
+ assign T_7433 = mem_ctrl_fp & mem_ctrl_wxd;
+ assign T_7434 = T_7433 ? io_fpu_toint_data : mem_int_wdata;
+ assign T_7435 = wb_ctrl_div | wb_dcache_miss;
+ assign wb_set_sboard = T_7435 | wb_ctrl_rocc;
+ assign replay_wb_common = io_dmem_resp_bits_nack | wb_reg_replay;
+ assign T_7438 = wb_reg_valid & wb_ctrl_rocc;
+ assign T_7440 = replay_wb_common == 1'h0;
+ assign wb_rocc_val = T_7438 & T_7440;
+ assign T_7442 = wb_reg_valid & wb_ctrl_rocc;
+ assign T_7444 = io_rocc_cmd_ready == 1'h0;
+ assign T_7445 = T_7442 & T_7444;
+ assign replay_wb = replay_wb_common | T_7445;
+ assign wb_xcpt = wb_reg_xcpt | csr_io_csr_xcpt;
+ assign T_7448 = replay_wb | wb_xcpt;
+ assign T_7449 = T_7448 | csr_io_eret;
+ assign T_7451 = io_rocc_cmd_ready == 1'h0;
+ assign T_7453 = io_dmem_resp_bits_tag[0];
+ assign T_7454 = T_7453;
+ assign dmem_resp_xpu = T_7454 == 1'h0;
+ assign T_7457 = io_dmem_resp_bits_tag[0];
+ assign dmem_resp_fpu = T_7457;
+ assign dmem_resp_waddr = io_dmem_resp_bits_tag[5:1];
+ assign dmem_resp_valid = io_dmem_resp_valid & io_dmem_resp_bits_has_data;
+ assign dmem_resp_replay = io_dmem_resp_bits_replay & io_dmem_resp_bits_has_data;
+ assign T_7462 = wb_reg_valid & wb_ctrl_wxd;
+ assign T_7464 = T_7462 == 1'h0;
+ assign ll_wdata = div_io_resp_bits_data;
+ assign ll_waddr = T_7469 ? dmem_resp_waddr : div_io_resp_bits_tag;
+ assign T_7467 = div_io_resp_ready & div_io_resp_valid;
+ assign ll_wen = T_7469 ? 1'h1 : T_7467;
+ assign T_7469 = dmem_resp_replay & dmem_resp_xpu;
+ assign T_7473 = replay_wb == 1'h0;
+ assign T_7474 = wb_reg_valid & T_7473;
+ assign T_7476 = csr_io_csr_xcpt == 1'h0;
+ assign wb_valid = T_7474 & T_7476;
+ assign wb_wen = wb_valid & wb_ctrl_wxd;
+ assign rf_wen = wb_wen | ll_wen;
+ assign rf_waddr = ll_wen ? ll_waddr : wb_waddr;
+ assign T_7481 = dmem_resp_valid & dmem_resp_xpu;
+ assign T_7482 = wb_ctrl_csr != 3'h0;
+ assign T_7483 = T_7482 ? csr_io_rw_rdata : wb_reg_wdata;
+ assign T_7484 = ll_wen ? ll_wdata : T_7483;
+ assign rf_wdata = T_7481 ? io_dmem_resp_bits_data : T_7484;
+ assign T_7487 = rf_waddr != 1'h0;
+ assign T_7488 = rf_waddr;
+ assign T_7489 = ~ T_7488;
+ assign T_7491 = rf_waddr == id_raddr1;
+ assign T_7492 = rf_waddr == id_raddr2;
+ assign T_7509 = wb_reg_inst[31:20];
+ assign T_7510 = wb_reg_valid ? wb_ctrl_csr : 3'h0;
+ assign T_7512 = id_raddr1 != 1'h0;
+ assign T_7513 = id_ctrl_rxs1 & T_7512;
+ assign T_7515 = id_raddr2 != 1'h0;
+ assign T_7516 = id_ctrl_rxs2 & T_7515;
+ assign T_7518 = id_waddr != 1'h0;
+ assign T_7519 = id_ctrl_wxd & T_7518;
+ assign T_7524 = 1'h1 << ll_waddr;
+ assign T_7526 = ll_wen ? T_7524 : 1'h0;
+ assign T_7527 = ~ T_7526;
+ assign T_7528 = T_7521 & T_7527;
+ assign T_7529 = 1'h0 | ll_wen;
+ assign T_7530 = T_7528 >> id_raddr1;
+ assign T_7531 = T_7530[0];
+ assign T_7532 = T_7513 & T_7531;
+ assign T_7533 = T_7528 >> id_raddr2;
+ assign T_7534 = T_7533[0];
+ assign T_7535 = T_7516 & T_7534;
+ assign T_7536 = T_7528 >> id_waddr;
+ assign T_7537 = T_7536[0];
+ assign T_7538 = T_7519 & T_7537;
+ assign T_7539 = T_7532 | T_7535;
+ assign id_sboard_hazard = T_7539 | T_7538;
+ assign T_7541 = wb_set_sboard & wb_wen;
+ assign T_7543 = 1'h1 << wb_waddr;
+ assign T_7545 = T_7541 ? T_7543 : 1'h0;
+ assign T_7546 = T_7528 | T_7545;
+ assign T_7547 = T_7529 | T_7541;
+ assign T_7548 = ex_ctrl_csr != 3'h0;
+ assign T_7549 = T_7548 | ex_ctrl_jalr;
+ assign T_7550 = T_7549 | ex_ctrl_mem;
+ assign T_7551 = T_7550 | ex_ctrl_div;
+ assign T_7552 = T_7551 | ex_ctrl_fp;
+ assign ex_cannot_bypass = T_7552 | ex_ctrl_rocc;
+ assign T_7554 = id_raddr1 == ex_waddr;
+ assign T_7555 = T_7513 & T_7554;
+ assign T_7556 = id_raddr2 == ex_waddr;
+ assign T_7557 = T_7516 & T_7556;
+ assign T_7558 = id_waddr == ex_waddr;
+ assign T_7559 = T_7519 & T_7558;
+ assign T_7560 = T_7555 | T_7557;
+ assign T_7561 = T_7560 | T_7559;
+ assign data_hazard_ex = ex_ctrl_wxd & T_7561;
+ assign T_7563 = id_raddr1 == ex_waddr;
+ assign T_7564 = io_fpu_dec_ren1 & T_7563;
+ assign T_7565 = id_raddr2 == ex_waddr;
+ assign T_7566 = io_fpu_dec_ren2 & T_7565;
+ assign T_7567 = id_raddr3 == ex_waddr;
+ assign T_7568 = io_fpu_dec_ren3 & T_7567;
+ assign T_7569 = id_waddr == ex_waddr;
+ assign T_7570 = io_fpu_dec_wen & T_7569;
+ assign T_7571 = T_7564 | T_7566;
+ assign T_7572 = T_7571 | T_7568;
+ assign T_7573 = T_7572 | T_7570;
+ assign fp_data_hazard_ex = ex_ctrl_wfd & T_7573;
+ assign T_7575 = data_hazard_ex & ex_cannot_bypass;
+ assign T_7576 = T_7575 | fp_data_hazard_ex;
+ assign id_ex_hazard = ex_reg_valid & T_7576;
+ assign mem_mem_cmd_bh = 1'h1 & mem_reg_slow_bypass;
+ assign T_7580 = mem_ctrl_csr != 3'h0;
+ assign T_7581 = mem_ctrl_mem & mem_mem_cmd_bh;
+ assign T_7582 = T_7580 | T_7581;
+ assign T_7583 = T_7582 | mem_ctrl_div;
+ assign T_7584 = T_7583 | mem_ctrl_fp;
+ assign mem_cannot_bypass = T_7584 | mem_ctrl_rocc;
+ assign T_7586 = id_raddr1 == mem_waddr;
+ assign T_7587 = T_7513 & T_7586;
+ assign T_7588 = id_raddr2 == mem_waddr;
+ assign T_7589 = T_7516 & T_7588;
+ assign T_7590 = id_waddr == mem_waddr;
+ assign T_7591 = T_7519 & T_7590;
+ assign T_7592 = T_7587 | T_7589;
+ assign T_7593 = T_7592 | T_7591;
+ assign data_hazard_mem = mem_ctrl_wxd & T_7593;
+ assign T_7595 = id_raddr1 == mem_waddr;
+ assign T_7596 = io_fpu_dec_ren1 & T_7595;
+ assign T_7597 = id_raddr2 == mem_waddr;
+ assign T_7598 = io_fpu_dec_ren2 & T_7597;
+ assign T_7599 = id_raddr3 == mem_waddr;
+ assign T_7600 = io_fpu_dec_ren3 & T_7599;
+ assign T_7601 = id_waddr == mem_waddr;
+ assign T_7602 = io_fpu_dec_wen & T_7601;
+ assign T_7603 = T_7596 | T_7598;
+ assign T_7604 = T_7603 | T_7600;
+ assign T_7605 = T_7604 | T_7602;
+ assign fp_data_hazard_mem = mem_ctrl_wfd & T_7605;
+ assign T_7607 = data_hazard_mem & mem_cannot_bypass;
+ assign T_7608 = T_7607 | fp_data_hazard_mem;
+ assign id_mem_hazard = mem_reg_valid & T_7608;
+ assign T_7610 = mem_reg_valid & data_hazard_mem;
+ assign T_7611 = T_7610 & mem_ctrl_mem;
+ assign T_7612 = id_raddr1 == wb_waddr;
+ assign T_7613 = T_7513 & T_7612;
+ assign T_7614 = id_raddr2 == wb_waddr;
+ assign T_7615 = T_7516 & T_7614;
+ assign T_7616 = id_waddr == wb_waddr;
+ assign T_7617 = T_7519 & T_7616;
+ assign T_7618 = T_7613 | T_7615;
+ assign T_7619 = T_7618 | T_7617;
+ assign data_hazard_wb = wb_ctrl_wxd & T_7619;
+ assign T_7621 = id_raddr1 == wb_waddr;
+ assign T_7622 = io_fpu_dec_ren1 & T_7621;
+ assign T_7623 = id_raddr2 == wb_waddr;
+ assign T_7624 = io_fpu_dec_ren2 & T_7623;
+ assign T_7625 = id_raddr3 == wb_waddr;
+ assign T_7626 = io_fpu_dec_ren3 & T_7625;
+ assign T_7627 = id_waddr == wb_waddr;
+ assign T_7628 = io_fpu_dec_wen & T_7627;
+ assign T_7629 = T_7622 | T_7624;
+ assign T_7630 = T_7629 | T_7626;
+ assign T_7631 = T_7630 | T_7628;
+ assign fp_data_hazard_wb = wb_ctrl_wfd & T_7631;
+ assign T_7633 = data_hazard_wb & wb_set_sboard;
+ assign T_7634 = T_7633 | fp_data_hazard_wb;
+ assign id_wb_hazard = wb_reg_valid & T_7634;
+ assign T_7639 = wb_dcache_miss & wb_ctrl_wfd;
+ assign T_7640 = T_7639 | io_fpu_sboard_set;
+ assign T_7641 = T_7640 & wb_valid;
+ assign T_7643 = 1'h1 << wb_waddr;
+ assign T_7645 = T_7641 ? T_7643 : 1'h0;
+ assign T_7646 = T_7637 | T_7645;
+ assign T_7647 = 1'h0 | T_7641;
+ assign T_7648 = dmem_resp_replay & dmem_resp_fpu;
+ assign T_7650 = 1'h1 << dmem_resp_waddr;
+ assign T_7652 = T_7648 ? T_7650 : 1'h0;
+ assign T_7653 = ~ T_7652;
+ assign T_7654 = T_7646 & T_7653;
+ assign T_7655 = T_7647 | T_7648;
+ assign T_7657 = 1'h1 << io_fpu_sboard_clra;
+ assign T_7659 = io_fpu_sboard_clr ? T_7657 : 1'h0;
+ assign T_7660 = ~ T_7659;
+ assign T_7661 = T_7654 & T_7660;
+ assign T_7662 = T_7655 | io_fpu_sboard_clr;
+ assign T_7664 = io_fpu_fcsr_rdy == 1'h0;
+ assign T_7665 = id_csr_en & T_7664;
+ assign T_7666 = T_7637 >> id_raddr1;
+ assign T_7667 = T_7666[0];
+ assign T_7668 = io_fpu_dec_ren1 & T_7667;
+ assign T_7669 = T_7637 >> id_raddr2;
+ assign T_7670 = T_7669[0];
+ assign T_7671 = io_fpu_dec_ren2 & T_7670;
+ assign T_7672 = T_7637 >> id_raddr3;
+ assign T_7673 = T_7672[0];
+ assign T_7674 = io_fpu_dec_ren3 & T_7673;
+ assign T_7675 = T_7637 >> id_waddr;
+ assign T_7676 = T_7675[0];
+ assign T_7677 = io_fpu_dec_wen & T_7676;
+ assign T_7678 = T_7668 | T_7671;
+ assign T_7679 = T_7678 | T_7674;
+ assign T_7680 = T_7679 | T_7677;
+ assign id_stall_fpu = T_7665 | T_7680;
+ assign T_7682 = id_ex_hazard | id_mem_hazard;
+ assign T_7683 = T_7682 | id_wb_hazard;
+ assign T_7684 = T_7683 | id_sboard_hazard;
+ assign T_7685 = id_ctrl_fp & id_stall_fpu;
+ assign T_7686 = T_7684 | T_7685;
+ assign T_7688 = io_dmem_req_ready == 1'h0;
+ assign T_7689 = id_ctrl_mem & T_7688;
+ assign T_7690 = T_7686 | T_7689;
+ assign T_7692 = 1'h0 & wb_reg_rocc_pending;
+ assign T_7693 = T_7692 & id_ctrl_rocc;
+ assign T_7695 = io_rocc_cmd_ready == 1'h0;
+ assign T_7696 = T_7693 & T_7695;
+ assign T_7697 = T_7690 | T_7696;
+ assign T_7698 = T_7697 | id_do_fence;
+ assign ctrl_stalld = T_7698 | csr_io_csr_stall;
+ assign T_7701 = io_imem_resp_valid == 1'h0;
+ assign T_7702 = T_7701 | take_pc_mem_wb;
+ assign T_7703 = T_7702 | ctrl_stalld;
+ assign T_7704 = T_7703 | csr_io_interrupt;
+ assign T_7705 = wb_xcpt | csr_io_eret;
+ assign T_7706 = replay_wb ? wb_reg_pc : mem_npc;
+ assign T_7707 = T_7705 ? csr_io_evec : T_7706;
+ assign T_7708 = wb_reg_valid & wb_ctrl_fence_i;
+ assign T_7710 = ctrl_stalld == 1'h0;
+ assign T_7711 = T_7710 | csr_io_interrupt;
+ assign T_7713 = mem_npc_misaligned == 1'h0;
+ assign T_7714 = mem_reg_valid & T_7713;
+ assign T_7715 = T_7714 & mem_wrong_npc;
+ assign T_7716 = mem_ctrl_branch & mem_br_taken;
+ assign T_7717 = T_7716 | mem_ctrl_jalr;
+ assign T_7718 = T_7717 | mem_ctrl_jal;
+ assign T_7719 = T_7715 & T_7718;
+ assign T_7721 = take_pc_wb == 1'h0;
+ assign T_7722 = T_7719 & T_7721;
+ assign T_7723 = mem_ctrl_jal | mem_ctrl_jalr;
+ assign T_7724 = mem_reg_inst[19:15];
+ assign T_7727 = T_7724 & 5'h19;
+ assign T_7728 = 1'h1 == T_7727;
+ assign T_7729 = mem_ctrl_jalr & T_7728;
+ assign T_7730 = mem_reg_valid & mem_ctrl_branch;
+ assign T_7732 = take_pc_wb == 1'h0;
+ assign T_7733 = T_7730 & T_7732;
+ assign T_7734 = mem_reg_valid & io_imem_btb_update_bits_isJump;
+ assign T_7736 = mem_npc_misaligned == 1'h0;
+ assign T_7737 = T_7734 & T_7736;
+ assign T_7739 = take_pc_wb == 1'h0;
+ assign T_7740 = T_7737 & T_7739;
+ assign T_7741 = mem_waddr[0];
+ assign T_7742 = mem_ctrl_wxd & T_7741;
+ assign T_7744 = ctrl_killd == 1'h0;
+ assign T_7745 = T_7744 & id_ctrl_fp;
+ assign T_7746 = dmem_resp_valid & dmem_resp_fpu;
+ assign T_7747 = ex_reg_valid & ex_ctrl_mem;
+ assign T_7748 = killm_common | mem_xcpt;
+ assign T_7750 = T_6992[63:38];
+ assign T_7751 = alu_io_adder_out[39:38];
+ assign T_7753 = T_7750 == 1'h0;
+ assign T_7755 = T_7750 == 1'h1;
+ assign T_7756 = T_7753 | T_7755;
+ assign T_7758 = T_7751 != 1'h0;
+ assign T_7759 = $signed(T_7750);
+ assign GEN_16 = $signed(1'h1);
+ assign T_7761 = $signed(T_7759) == $signed(GEN_16);
+ assign T_7762 = $signed(T_7750);
+ assign GEN_17 = $signed(2'h2);
+ assign T_7764 = $signed(T_7762) == $signed(GEN_17);
+ assign T_7765 = T_7761 | T_7764;
+ assign T_7766 = $signed(T_7751);
+ assign GEN_18 = $signed(1'h1);
+ assign T_7768 = $signed(T_7766) == $signed(GEN_18);
+ assign T_7769 = T_7751[0];
+ assign T_7770 = T_7765 ? T_7768 : T_7769;
+ assign T_7771 = T_7756 ? T_7758 : T_7770;
+ assign T_7772 = alu_io_adder_out[38:0];
+ assign T_7773 = {T_7771,T_7772};
+ assign T_7774 = {ex_waddr,ex_ctrl_fp};
+ assign T_7775 = mem_ctrl_fp ? io_fpu_store_data : mem_reg_rs2;
+ assign T_7777 = csr_io_status_xs != 1'h0;
+ assign T_7778 = wb_xcpt & T_7777;
+ assign T_7780 = csr_io_status_prv != 1'h0;
+ assign T_7799_funct = T_7815;
+ assign T_7799_rs2 = T_7814;
+ assign T_7799_rs1 = T_7813;
+ assign T_7799_xd = T_7812;
+ assign T_7799_xs1 = T_7811;
+ assign T_7799_xs2 = T_7810;
+ assign T_7799_rd = T_7809;
+ assign T_7799_opcode = T_7808;
+ assign T_7808 = wb_reg_inst[6:0];
+ assign T_7809 = wb_reg_inst[11:7];
+ assign T_7810 = wb_reg_inst[12];
+ assign T_7811 = wb_reg_inst[13];
+ assign T_7812 = wb_reg_inst[14];
+ assign T_7813 = wb_reg_inst[19:15];
+ assign T_7814 = wb_reg_inst[24:20];
+ assign T_7815 = wb_reg_inst[31:25];
+ assign T_7816 = csr_io_time[32:0];
+ assign T_7818 = rf_wen ? rf_waddr : 1'h0;
+ assign T_7819 = wb_reg_inst[19:15];
+ assign T_7822 = wb_reg_inst[24:20];
+ assign T_7826 = reset == 1'h0;
+ assign GEN_19 = 2'h3 == ex_reg_rs_lsb_0;
+ assign GEN_20 = 2'h2 == ex_reg_rs_lsb_0;
+ assign GEN_21 = 1'h1 == ex_reg_rs_lsb_0;
+ assign GEN_22 = 2'h3 == ex_reg_rs_lsb_1;
+ assign GEN_23 = 2'h2 == ex_reg_rs_lsb_1;
+ assign GEN_24 = 1'h1 == ex_reg_rs_lsb_1;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ ex_ctrl_legal = {1{$random}};
+ ex_ctrl_fp = {1{$random}};
+ ex_ctrl_rocc = {1{$random}};
+ ex_ctrl_branch = {1{$random}};
+ ex_ctrl_jal = {1{$random}};
+ ex_ctrl_jalr = {1{$random}};
+ ex_ctrl_rxs2 = {1{$random}};
+ ex_ctrl_rxs1 = {1{$random}};
+ ex_ctrl_sel_alu2 = {1{$random}};
+ ex_ctrl_sel_alu1 = {1{$random}};
+ ex_ctrl_sel_imm = {1{$random}};
+ ex_ctrl_alu_dw = {1{$random}};
+ ex_ctrl_alu_fn = {1{$random}};
+ ex_ctrl_mem = {1{$random}};
+ ex_ctrl_mem_cmd = {1{$random}};
+ ex_ctrl_mem_type = {1{$random}};
+ ex_ctrl_rfs1 = {1{$random}};
+ ex_ctrl_rfs2 = {1{$random}};
+ ex_ctrl_rfs3 = {1{$random}};
+ ex_ctrl_wfd = {1{$random}};
+ ex_ctrl_div = {1{$random}};
+ ex_ctrl_wxd = {1{$random}};
+ ex_ctrl_csr = {1{$random}};
+ ex_ctrl_fence_i = {1{$random}};
+ ex_ctrl_fence = {1{$random}};
+ ex_ctrl_amo = {1{$random}};
+ mem_ctrl_legal = {1{$random}};
+ mem_ctrl_fp = {1{$random}};
+ mem_ctrl_rocc = {1{$random}};
+ mem_ctrl_branch = {1{$random}};
+ mem_ctrl_jal = {1{$random}};
+ mem_ctrl_jalr = {1{$random}};
+ mem_ctrl_rxs2 = {1{$random}};
+ mem_ctrl_rxs1 = {1{$random}};
+ mem_ctrl_sel_alu2 = {1{$random}};
+ mem_ctrl_sel_alu1 = {1{$random}};
+ mem_ctrl_sel_imm = {1{$random}};
+ mem_ctrl_alu_dw = {1{$random}};
+ mem_ctrl_alu_fn = {1{$random}};
+ mem_ctrl_mem = {1{$random}};
+ mem_ctrl_mem_cmd = {1{$random}};
+ mem_ctrl_mem_type = {1{$random}};
+ mem_ctrl_rfs1 = {1{$random}};
+ mem_ctrl_rfs2 = {1{$random}};
+ mem_ctrl_rfs3 = {1{$random}};
+ mem_ctrl_wfd = {1{$random}};
+ mem_ctrl_div = {1{$random}};
+ mem_ctrl_wxd = {1{$random}};
+ mem_ctrl_csr = {1{$random}};
+ mem_ctrl_fence_i = {1{$random}};
+ mem_ctrl_fence = {1{$random}};
+ mem_ctrl_amo = {1{$random}};
+ wb_ctrl_legal = {1{$random}};
+ wb_ctrl_fp = {1{$random}};
+ wb_ctrl_rocc = {1{$random}};
+ wb_ctrl_branch = {1{$random}};
+ wb_ctrl_jal = {1{$random}};
+ wb_ctrl_jalr = {1{$random}};
+ wb_ctrl_rxs2 = {1{$random}};
+ wb_ctrl_rxs1 = {1{$random}};
+ wb_ctrl_sel_alu2 = {1{$random}};
+ wb_ctrl_sel_alu1 = {1{$random}};
+ wb_ctrl_sel_imm = {1{$random}};
+ wb_ctrl_alu_dw = {1{$random}};
+ wb_ctrl_alu_fn = {1{$random}};
+ wb_ctrl_mem = {1{$random}};
+ wb_ctrl_mem_cmd = {1{$random}};
+ wb_ctrl_mem_type = {1{$random}};
+ wb_ctrl_rfs1 = {1{$random}};
+ wb_ctrl_rfs2 = {1{$random}};
+ wb_ctrl_rfs3 = {1{$random}};
+ wb_ctrl_wfd = {1{$random}};
+ wb_ctrl_div = {1{$random}};
+ wb_ctrl_wxd = {1{$random}};
+ wb_ctrl_csr = {1{$random}};
+ wb_ctrl_fence_i = {1{$random}};
+ wb_ctrl_fence = {1{$random}};
+ wb_ctrl_amo = {1{$random}};
+ ex_reg_xcpt_interrupt = {1{$random}};
+ ex_reg_valid = {1{$random}};
+ ex_reg_btb_hit = {1{$random}};
+ ex_reg_btb_resp_taken = {1{$random}};
+ ex_reg_btb_resp_mask = {1{$random}};
+ ex_reg_btb_resp_bridx = {1{$random}};
+ ex_reg_btb_resp_target = {2{$random}};
+ ex_reg_btb_resp_entry = {1{$random}};
+ ex_reg_btb_resp_bht_history = {1{$random}};
+ ex_reg_btb_resp_bht_value = {1{$random}};
+ ex_reg_xcpt = {1{$random}};
+ ex_reg_flush_pipe = {1{$random}};
+ ex_reg_load_use = {1{$random}};
+ ex_reg_cause = {2{$random}};
+ ex_reg_pc = {2{$random}};
+ ex_reg_inst = {1{$random}};
+ mem_reg_xcpt_interrupt = {1{$random}};
+ mem_reg_valid = {1{$random}};
+ mem_reg_btb_hit = {1{$random}};
+ mem_reg_btb_resp_taken = {1{$random}};
+ mem_reg_btb_resp_mask = {1{$random}};
+ mem_reg_btb_resp_bridx = {1{$random}};
+ mem_reg_btb_resp_target = {2{$random}};
+ mem_reg_btb_resp_entry = {1{$random}};
+ mem_reg_btb_resp_bht_history = {1{$random}};
+ mem_reg_btb_resp_bht_value = {1{$random}};
+ mem_reg_xcpt = {1{$random}};
+ mem_reg_replay = {1{$random}};
+ mem_reg_flush_pipe = {1{$random}};
+ mem_reg_cause = {2{$random}};
+ mem_reg_slow_bypass = {1{$random}};
+ mem_reg_pc = {2{$random}};
+ mem_reg_inst = {1{$random}};
+ mem_reg_wdata = {2{$random}};
+ mem_reg_rs2 = {2{$random}};
+ wb_reg_valid = {1{$random}};
+ wb_reg_xcpt = {1{$random}};
+ wb_reg_replay = {1{$random}};
+ wb_reg_cause = {2{$random}};
+ wb_reg_rocc_pending = {1{$random}};
+ wb_reg_pc = {2{$random}};
+ wb_reg_inst = {1{$random}};
+ wb_reg_wdata = {2{$random}};
+ wb_reg_rs2 = {2{$random}};
+ id_reg_fence = {1{$random}};
+ for (initvar = 0; initvar < 31; initvar = initvar+1)
+ T_6766[initvar] = {2{$random}};
+ ex_reg_rs_bypass_0 = {1{$random}};
+ ex_reg_rs_bypass_1 = {1{$random}};
+ ex_reg_rs_lsb_0 = {1{$random}};
+ ex_reg_rs_lsb_1 = {1{$random}};
+ ex_reg_rs_msb_0 = {2{$random}};
+ ex_reg_rs_msb_1 = {2{$random}};
+ T_7419 = {1{$random}};
+ T_7521 = {1{$random}};
+ T_7637 = {1{$random}};
+ T_7820 = {2{$random}};
+ T_7821 = {2{$random}};
+ T_7823 = {2{$random}};
+ T_7824 = {2{$random}};
+ GEN_25 = {1{$random}};
+ GEN_26 = {1{$random}};
+ GEN_27 = {1{$random}};
+ GEN_28 = {1{$random}};
+ GEN_29 = {1{$random}};
+ GEN_30 = {1{$random}};
+ GEN_31 = {1{$random}};
+ GEN_32 = {1{$random}};
+ GEN_33 = {1{$random}};
+ GEN_34 = {1{$random}};
+ GEN_35 = {1{$random}};
+ GEN_36 = {1{$random}};
+ GEN_37 = {1{$random}};
+ GEN_38 = {1{$random}};
+ GEN_39 = {1{$random}};
+ GEN_40 = {1{$random}};
+ GEN_41 = {1{$random}};
+ GEN_42 = {1{$random}};
+ GEN_43 = {1{$random}};
+ GEN_44 = {1{$random}};
+ GEN_45 = {1{$random}};
+ GEN_46 = {3{$random}};
+ GEN_47 = {3{$random}};
+ GEN_48 = {3{$random}};
+ GEN_49 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_ctrl_legal <= id_ctrl_legal;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_ctrl_fp <= id_ctrl_fp;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_ctrl_rocc <= id_ctrl_rocc;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_ctrl_branch <= id_ctrl_branch;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_ctrl_jal <= id_ctrl_jal;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_ctrl_jalr <= id_ctrl_jalr;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_ctrl_rxs2 <= id_ctrl_rxs2;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_ctrl_rxs1 <= id_ctrl_rxs1;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_ctrl_sel_alu2 <= id_ctrl_sel_alu2;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_ctrl_sel_alu1 <= id_ctrl_sel_alu1;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_ctrl_sel_imm <= id_ctrl_sel_imm;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_ctrl_alu_dw <= id_ctrl_alu_dw;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_ctrl_alu_fn <= id_ctrl_alu_fn;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_ctrl_mem <= id_ctrl_mem;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_ctrl_mem_cmd <= id_ctrl_mem_cmd;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_ctrl_mem_type <= id_ctrl_mem_type;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_ctrl_rfs1 <= id_ctrl_rfs1;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_ctrl_rfs2 <= id_ctrl_rfs2;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_ctrl_rfs3 <= id_ctrl_rfs3;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_ctrl_wfd <= id_ctrl_wfd;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_ctrl_div <= id_ctrl_div;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_ctrl_wxd <= id_ctrl_wxd;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_ctrl_csr <= id_csr;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_ctrl_fence_i <= id_ctrl_fence_i;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_ctrl_fence <= id_ctrl_fence;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_ctrl_amo <= id_ctrl_amo;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_ctrl_legal <= ex_ctrl_legal;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_ctrl_fp <= ex_ctrl_fp;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_ctrl_rocc <= ex_ctrl_rocc;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_ctrl_branch <= ex_ctrl_branch;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_ctrl_jal <= ex_ctrl_jal;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_ctrl_jalr <= ex_ctrl_jalr;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_ctrl_rxs2 <= ex_ctrl_rxs2;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_ctrl_rxs1 <= ex_ctrl_rxs1;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_ctrl_sel_alu2 <= ex_ctrl_sel_alu2;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_ctrl_sel_alu1 <= ex_ctrl_sel_alu1;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_ctrl_sel_imm <= ex_ctrl_sel_imm;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_ctrl_alu_dw <= ex_ctrl_alu_dw;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_ctrl_alu_fn <= ex_ctrl_alu_fn;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_ctrl_mem <= ex_ctrl_mem;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_ctrl_mem_cmd <= ex_ctrl_mem_cmd;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_ctrl_mem_type <= ex_ctrl_mem_type;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_ctrl_rfs1 <= ex_ctrl_rfs1;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_ctrl_rfs2 <= ex_ctrl_rfs2;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_ctrl_rfs3 <= ex_ctrl_rfs3;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_ctrl_wfd <= ex_ctrl_wfd;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_ctrl_div <= ex_ctrl_div;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_ctrl_wxd <= ex_ctrl_wxd;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_ctrl_csr <= ex_ctrl_csr;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_ctrl_fence_i <= ex_ctrl_fence_i;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_ctrl_fence <= ex_ctrl_fence;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_ctrl_amo <= ex_ctrl_amo;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_ctrl_legal <= mem_ctrl_legal;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_ctrl_fp <= mem_ctrl_fp;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_ctrl_rocc <= mem_ctrl_rocc;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_ctrl_branch <= mem_ctrl_branch;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_ctrl_jal <= mem_ctrl_jal;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_ctrl_jalr <= mem_ctrl_jalr;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_ctrl_rxs2 <= mem_ctrl_rxs2;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_ctrl_rxs1 <= mem_ctrl_rxs1;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_ctrl_sel_alu2 <= mem_ctrl_sel_alu2;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_ctrl_sel_alu1 <= mem_ctrl_sel_alu1;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_ctrl_sel_imm <= mem_ctrl_sel_imm;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_ctrl_alu_dw <= mem_ctrl_alu_dw;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_ctrl_alu_fn <= mem_ctrl_alu_fn;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_ctrl_mem <= mem_ctrl_mem;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_ctrl_mem_cmd <= mem_ctrl_mem_cmd;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_ctrl_mem_type <= mem_ctrl_mem_type;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_ctrl_rfs1 <= mem_ctrl_rfs1;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_ctrl_rfs2 <= mem_ctrl_rfs2;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_ctrl_rfs3 <= mem_ctrl_rfs3;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_ctrl_wfd <= mem_ctrl_wfd;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_ctrl_div <= mem_ctrl_div;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_ctrl_wxd <= mem_ctrl_wxd;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_ctrl_csr <= mem_ctrl_csr;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_ctrl_fence_i <= mem_ctrl_fence_i;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_ctrl_fence <= mem_ctrl_fence;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_ctrl_amo <= mem_ctrl_amo;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ ex_reg_xcpt_interrupt <= T_7095;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ ex_reg_valid <= T_7088;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_reg_btb_hit <= io_imem_btb_resp_valid;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ if(io_imem_btb_resp_valid) begin
+ ex_reg_btb_resp_taken <= io_imem_btb_resp_bits_taken;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ if(io_imem_btb_resp_valid) begin
+ ex_reg_btb_resp_mask <= io_imem_btb_resp_bits_mask;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ if(io_imem_btb_resp_valid) begin
+ ex_reg_btb_resp_bridx <= io_imem_btb_resp_bits_bridx;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ if(io_imem_btb_resp_valid) begin
+ ex_reg_btb_resp_target <= io_imem_btb_resp_bits_target;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ if(io_imem_btb_resp_valid) begin
+ ex_reg_btb_resp_entry <= io_imem_btb_resp_bits_entry;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ if(io_imem_btb_resp_valid) begin
+ ex_reg_btb_resp_bht_history <= io_imem_btb_resp_bits_bht_history;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ if(io_imem_btb_resp_valid) begin
+ ex_reg_btb_resp_bht_value <= io_imem_btb_resp_bits_bht_value;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ ex_reg_xcpt <= T_7091;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_reg_flush_pipe <= T_7098;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_reg_load_use <= id_load_use;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(id_xcpt) begin
+ ex_reg_cause <= id_cause;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7131) begin
+ ex_reg_pc <= io_imem_resp_bits_pc;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7131) begin
+ ex_reg_inst <= io_imem_resp_bits_data_0;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ mem_reg_xcpt_interrupt <= T_7378;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ mem_reg_valid <= T_7369;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_reg_btb_hit <= ex_reg_btb_hit;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ if(ex_reg_btb_hit) begin
+ mem_reg_btb_resp_taken <= ex_reg_btb_resp_taken;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ if(ex_reg_btb_hit) begin
+ mem_reg_btb_resp_mask <= ex_reg_btb_resp_mask;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ if(ex_reg_btb_hit) begin
+ mem_reg_btb_resp_bridx <= ex_reg_btb_resp_bridx;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ if(ex_reg_btb_hit) begin
+ mem_reg_btb_resp_target <= ex_reg_btb_resp_target;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ if(ex_reg_btb_hit) begin
+ mem_reg_btb_resp_entry <= ex_reg_btb_resp_entry;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ if(ex_reg_btb_hit) begin
+ mem_reg_btb_resp_bht_history <= ex_reg_btb_resp_bht_history;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ if(ex_reg_btb_hit) begin
+ mem_reg_btb_resp_bht_value <= ex_reg_btb_resp_bht_value;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ mem_reg_xcpt <= T_7375;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ mem_reg_replay <= T_7372;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_reg_flush_pipe <= ex_reg_flush_pipe;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(ex_xcpt) begin
+ mem_reg_cause <= ex_cause;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_reg_slow_bypass <= ex_slow_bypass;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_reg_pc <= ex_reg_pc;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_reg_inst <= ex_reg_inst;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ mem_reg_wdata <= alu_io_out;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7379) begin
+ if(T_7381) begin
+ mem_reg_rs2 <= T_6995;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ wb_reg_valid <= T_7424;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ wb_reg_xcpt <= T_7430;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ wb_reg_replay <= T_7427;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(mem_xcpt) begin
+ wb_reg_cause <= mem_cause;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ wb_reg_rocc_pending <= 1'h0;
+ end else begin
+ if(wb_reg_xcpt) begin
+ wb_reg_rocc_pending <= 1'h0;
+ end else begin
+ if(wb_rocc_val) begin
+ wb_reg_rocc_pending <= T_7451;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_reg_pc <= mem_reg_pc;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_reg_inst <= mem_reg_inst;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ wb_reg_wdata <= T_7434;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7432) begin
+ if(mem_ctrl_rocc) begin
+ wb_reg_rs2 <= mem_reg_rs2;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ id_reg_fence <= 1'h0;
+ end else begin
+ id_reg_fence <= T_6903;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_reg_rs_bypass_0 <= T_7101;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ ex_reg_rs_bypass_1 <= T_7116;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ if(T_7111) begin
+ ex_reg_rs_lsb_0 <= T_7112;
+ end else begin
+ ex_reg_rs_lsb_0 <= T_7108;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ if(T_7126) begin
+ ex_reg_rs_lsb_1 <= T_7127;
+ end else begin
+ ex_reg_rs_lsb_1 <= T_7123;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ if(T_7111) begin
+ ex_reg_rs_msb_0 <= T_7113;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_7097) begin
+ if(T_7126) begin
+ ex_reg_rs_msb_1 <= T_7128;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ T_7419 <= T_7418;
+ end
+ if(reset) begin
+ T_7521 <= 32'h0;
+ end else begin
+ if(T_7547) begin
+ T_7521 <= T_7546;
+ end else begin
+ if(T_7529) begin
+ T_7521 <= T_7528;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ T_7637 <= 32'h0;
+ end else begin
+ if(T_7662) begin
+ T_7637 <= T_7661;
+ end else begin
+ if(T_7655) begin
+ T_7637 <= T_7654;
+ end else begin
+ if(T_7647) begin
+ T_7637 <= T_7646;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ T_7820 <= T_6992;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ T_7821 <= T_7820;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ T_7823 <= T_6995;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ T_7824 <= T_7823;
+ end
+ `ifndef SYNTHESIS
+ if(T_7826) begin
+ $fwrite(32'h80000002,"C%d: %d [%d] pc=[%h] W[r%d=%h][%d] R[r%d=%h] R[r%d=%h] inst=[%h] DASM(%h)\n",io_host_id,T_7816,wb_valid,wb_reg_pc,T_7818,rf_wdata,rf_wen,T_7819,T_7821,T_7822,T_7824,wb_reg_inst,wb_reg_inst);
+ end
+ `endif
+ end
+ always @(posedge T_6766_T_7490_clk) begin
+ if(T_6766_T_7490_en & T_6766_T_7490_mask) begin
+ T_6766[T_6766_T_7490_addr] <= T_6766_T_7490_data;
+ end
+ end
+endmodule
+module BTB(
+ input clk,
+ input reset,
+ input io_req_valid,
+ input [38:0] io_req_bits_addr,
+ output io_resp_valid,
+ output io_resp_bits_taken,
+ output io_resp_bits_mask,
+ output io_resp_bits_bridx,
+ output [38:0] io_resp_bits_target,
+ output [5:0] io_resp_bits_entry,
+ output [6:0] io_resp_bits_bht_history,
+ output [1:0] io_resp_bits_bht_value,
+ input io_btb_update_valid,
+ input io_btb_update_bits_prediction_valid,
+ input io_btb_update_bits_prediction_bits_taken,
+ input io_btb_update_bits_prediction_bits_mask,
+ input io_btb_update_bits_prediction_bits_bridx,
+ input [38:0] io_btb_update_bits_prediction_bits_target,
+ input [5:0] io_btb_update_bits_prediction_bits_entry,
+ input [6:0] io_btb_update_bits_prediction_bits_bht_history,
+ input [1:0] io_btb_update_bits_prediction_bits_bht_value,
+ input [38:0] io_btb_update_bits_pc,
+ input [38:0] io_btb_update_bits_target,
+ input io_btb_update_bits_taken,
+ input io_btb_update_bits_isJump,
+ input io_btb_update_bits_isReturn,
+ input [38:0] io_btb_update_bits_br_pc,
+ input io_bht_update_valid,
+ input io_bht_update_bits_prediction_valid,
+ input io_bht_update_bits_prediction_bits_taken,
+ input io_bht_update_bits_prediction_bits_mask,
+ input io_bht_update_bits_prediction_bits_bridx,
+ input [38:0] io_bht_update_bits_prediction_bits_target,
+ input [5:0] io_bht_update_bits_prediction_bits_entry,
+ input [6:0] io_bht_update_bits_prediction_bits_bht_history,
+ input [1:0] io_bht_update_bits_prediction_bits_bht_value,
+ input [38:0] io_bht_update_bits_pc,
+ input io_bht_update_bits_taken,
+ input io_bht_update_bits_mispredict,
+ input io_ras_update_valid,
+ input io_ras_update_bits_isCall,
+ input io_ras_update_bits_isReturn,
+ input [38:0] io_ras_update_bits_returnAddr,
+ input io_ras_update_bits_prediction_valid,
+ input io_ras_update_bits_prediction_bits_taken,
+ input io_ras_update_bits_prediction_bits_mask,
+ input io_ras_update_bits_prediction_bits_bridx,
+ input [38:0] io_ras_update_bits_prediction_bits_target,
+ input [5:0] io_ras_update_bits_prediction_bits_entry,
+ input [6:0] io_ras_update_bits_prediction_bits_bht_history,
+ input [1:0] io_ras_update_bits_prediction_bits_bht_value,
+ input io_invalidate
+);
+ reg [61:0] idxValid;
+ reg [11:0] idxs [0:61];
+ wire [11:0] idxs_T_1699_data;
+ wire [5:0] idxs_T_1699_addr;
+ wire idxs_T_1699_en;
+ wire idxs_T_1699_clk;
+ wire [11:0] idxs_T_1702_data;
+ wire [5:0] idxs_T_1702_addr;
+ wire idxs_T_1702_en;
+ wire idxs_T_1702_clk;
+ wire [11:0] idxs_T_1705_data;
+ wire [5:0] idxs_T_1705_addr;
+ wire idxs_T_1705_en;
+ wire idxs_T_1705_clk;
+ wire [11:0] idxs_T_1708_data;
+ wire [5:0] idxs_T_1708_addr;
+ wire idxs_T_1708_en;
+ wire idxs_T_1708_clk;
+ wire [11:0] idxs_T_1711_data;
+ wire [5:0] idxs_T_1711_addr;
+ wire idxs_T_1711_en;
+ wire idxs_T_1711_clk;
+ wire [11:0] idxs_T_1714_data;
+ wire [5:0] idxs_T_1714_addr;
+ wire idxs_T_1714_en;
+ wire idxs_T_1714_clk;
+ wire [11:0] idxs_T_1717_data;
+ wire [5:0] idxs_T_1717_addr;
+ wire idxs_T_1717_en;
+ wire idxs_T_1717_clk;
+ wire [11:0] idxs_T_1720_data;
+ wire [5:0] idxs_T_1720_addr;
+ wire idxs_T_1720_en;
+ wire idxs_T_1720_clk;
+ wire [11:0] idxs_T_1723_data;
+ wire [5:0] idxs_T_1723_addr;
+ wire idxs_T_1723_en;
+ wire idxs_T_1723_clk;
+ wire [11:0] idxs_T_1726_data;
+ wire [5:0] idxs_T_1726_addr;
+ wire idxs_T_1726_en;
+ wire idxs_T_1726_clk;
+ wire [11:0] idxs_T_1729_data;
+ wire [5:0] idxs_T_1729_addr;
+ wire idxs_T_1729_en;
+ wire idxs_T_1729_clk;
+ wire [11:0] idxs_T_1732_data;
+ wire [5:0] idxs_T_1732_addr;
+ wire idxs_T_1732_en;
+ wire idxs_T_1732_clk;
+ wire [11:0] idxs_T_1735_data;
+ wire [5:0] idxs_T_1735_addr;
+ wire idxs_T_1735_en;
+ wire idxs_T_1735_clk;
+ wire [11:0] idxs_T_1738_data;
+ wire [5:0] idxs_T_1738_addr;
+ wire idxs_T_1738_en;
+ wire idxs_T_1738_clk;
+ wire [11:0] idxs_T_1741_data;
+ wire [5:0] idxs_T_1741_addr;
+ wire idxs_T_1741_en;
+ wire idxs_T_1741_clk;
+ wire [11:0] idxs_T_1744_data;
+ wire [5:0] idxs_T_1744_addr;
+ wire idxs_T_1744_en;
+ wire idxs_T_1744_clk;
+ wire [11:0] idxs_T_1747_data;
+ wire [5:0] idxs_T_1747_addr;
+ wire idxs_T_1747_en;
+ wire idxs_T_1747_clk;
+ wire [11:0] idxs_T_1750_data;
+ wire [5:0] idxs_T_1750_addr;
+ wire idxs_T_1750_en;
+ wire idxs_T_1750_clk;
+ wire [11:0] idxs_T_1753_data;
+ wire [5:0] idxs_T_1753_addr;
+ wire idxs_T_1753_en;
+ wire idxs_T_1753_clk;
+ wire [11:0] idxs_T_1756_data;
+ wire [5:0] idxs_T_1756_addr;
+ wire idxs_T_1756_en;
+ wire idxs_T_1756_clk;
+ wire [11:0] idxs_T_1759_data;
+ wire [5:0] idxs_T_1759_addr;
+ wire idxs_T_1759_en;
+ wire idxs_T_1759_clk;
+ wire [11:0] idxs_T_1762_data;
+ wire [5:0] idxs_T_1762_addr;
+ wire idxs_T_1762_en;
+ wire idxs_T_1762_clk;
+ wire [11:0] idxs_T_1765_data;
+ wire [5:0] idxs_T_1765_addr;
+ wire idxs_T_1765_en;
+ wire idxs_T_1765_clk;
+ wire [11:0] idxs_T_1768_data;
+ wire [5:0] idxs_T_1768_addr;
+ wire idxs_T_1768_en;
+ wire idxs_T_1768_clk;
+ wire [11:0] idxs_T_1771_data;
+ wire [5:0] idxs_T_1771_addr;
+ wire idxs_T_1771_en;
+ wire idxs_T_1771_clk;
+ wire [11:0] idxs_T_1774_data;
+ wire [5:0] idxs_T_1774_addr;
+ wire idxs_T_1774_en;
+ wire idxs_T_1774_clk;
+ wire [11:0] idxs_T_1777_data;
+ wire [5:0] idxs_T_1777_addr;
+ wire idxs_T_1777_en;
+ wire idxs_T_1777_clk;
+ wire [11:0] idxs_T_1780_data;
+ wire [5:0] idxs_T_1780_addr;
+ wire idxs_T_1780_en;
+ wire idxs_T_1780_clk;
+ wire [11:0] idxs_T_1783_data;
+ wire [5:0] idxs_T_1783_addr;
+ wire idxs_T_1783_en;
+ wire idxs_T_1783_clk;
+ wire [11:0] idxs_T_1786_data;
+ wire [5:0] idxs_T_1786_addr;
+ wire idxs_T_1786_en;
+ wire idxs_T_1786_clk;
+ wire [11:0] idxs_T_1789_data;
+ wire [5:0] idxs_T_1789_addr;
+ wire idxs_T_1789_en;
+ wire idxs_T_1789_clk;
+ wire [11:0] idxs_T_1792_data;
+ wire [5:0] idxs_T_1792_addr;
+ wire idxs_T_1792_en;
+ wire idxs_T_1792_clk;
+ wire [11:0] idxs_T_1795_data;
+ wire [5:0] idxs_T_1795_addr;
+ wire idxs_T_1795_en;
+ wire idxs_T_1795_clk;
+ wire [11:0] idxs_T_1798_data;
+ wire [5:0] idxs_T_1798_addr;
+ wire idxs_T_1798_en;
+ wire idxs_T_1798_clk;
+ wire [11:0] idxs_T_1801_data;
+ wire [5:0] idxs_T_1801_addr;
+ wire idxs_T_1801_en;
+ wire idxs_T_1801_clk;
+ wire [11:0] idxs_T_1804_data;
+ wire [5:0] idxs_T_1804_addr;
+ wire idxs_T_1804_en;
+ wire idxs_T_1804_clk;
+ wire [11:0] idxs_T_1807_data;
+ wire [5:0] idxs_T_1807_addr;
+ wire idxs_T_1807_en;
+ wire idxs_T_1807_clk;
+ wire [11:0] idxs_T_1810_data;
+ wire [5:0] idxs_T_1810_addr;
+ wire idxs_T_1810_en;
+ wire idxs_T_1810_clk;
+ wire [11:0] idxs_T_1813_data;
+ wire [5:0] idxs_T_1813_addr;
+ wire idxs_T_1813_en;
+ wire idxs_T_1813_clk;
+ wire [11:0] idxs_T_1816_data;
+ wire [5:0] idxs_T_1816_addr;
+ wire idxs_T_1816_en;
+ wire idxs_T_1816_clk;
+ wire [11:0] idxs_T_1819_data;
+ wire [5:0] idxs_T_1819_addr;
+ wire idxs_T_1819_en;
+ wire idxs_T_1819_clk;
+ wire [11:0] idxs_T_1822_data;
+ wire [5:0] idxs_T_1822_addr;
+ wire idxs_T_1822_en;
+ wire idxs_T_1822_clk;
+ wire [11:0] idxs_T_1825_data;
+ wire [5:0] idxs_T_1825_addr;
+ wire idxs_T_1825_en;
+ wire idxs_T_1825_clk;
+ wire [11:0] idxs_T_1828_data;
+ wire [5:0] idxs_T_1828_addr;
+ wire idxs_T_1828_en;
+ wire idxs_T_1828_clk;
+ wire [11:0] idxs_T_1831_data;
+ wire [5:0] idxs_T_1831_addr;
+ wire idxs_T_1831_en;
+ wire idxs_T_1831_clk;
+ wire [11:0] idxs_T_1834_data;
+ wire [5:0] idxs_T_1834_addr;
+ wire idxs_T_1834_en;
+ wire idxs_T_1834_clk;
+ wire [11:0] idxs_T_1837_data;
+ wire [5:0] idxs_T_1837_addr;
+ wire idxs_T_1837_en;
+ wire idxs_T_1837_clk;
+ wire [11:0] idxs_T_1840_data;
+ wire [5:0] idxs_T_1840_addr;
+ wire idxs_T_1840_en;
+ wire idxs_T_1840_clk;
+ wire [11:0] idxs_T_1843_data;
+ wire [5:0] idxs_T_1843_addr;
+ wire idxs_T_1843_en;
+ wire idxs_T_1843_clk;
+ wire [11:0] idxs_T_1846_data;
+ wire [5:0] idxs_T_1846_addr;
+ wire idxs_T_1846_en;
+ wire idxs_T_1846_clk;
+ wire [11:0] idxs_T_1849_data;
+ wire [5:0] idxs_T_1849_addr;
+ wire idxs_T_1849_en;
+ wire idxs_T_1849_clk;
+ wire [11:0] idxs_T_1852_data;
+ wire [5:0] idxs_T_1852_addr;
+ wire idxs_T_1852_en;
+ wire idxs_T_1852_clk;
+ wire [11:0] idxs_T_1855_data;
+ wire [5:0] idxs_T_1855_addr;
+ wire idxs_T_1855_en;
+ wire idxs_T_1855_clk;
+ wire [11:0] idxs_T_1858_data;
+ wire [5:0] idxs_T_1858_addr;
+ wire idxs_T_1858_en;
+ wire idxs_T_1858_clk;
+ wire [11:0] idxs_T_1861_data;
+ wire [5:0] idxs_T_1861_addr;
+ wire idxs_T_1861_en;
+ wire idxs_T_1861_clk;
+ wire [11:0] idxs_T_1864_data;
+ wire [5:0] idxs_T_1864_addr;
+ wire idxs_T_1864_en;
+ wire idxs_T_1864_clk;
+ wire [11:0] idxs_T_1867_data;
+ wire [5:0] idxs_T_1867_addr;
+ wire idxs_T_1867_en;
+ wire idxs_T_1867_clk;
+ wire [11:0] idxs_T_1870_data;
+ wire [5:0] idxs_T_1870_addr;
+ wire idxs_T_1870_en;
+ wire idxs_T_1870_clk;
+ wire [11:0] idxs_T_1873_data;
+ wire [5:0] idxs_T_1873_addr;
+ wire idxs_T_1873_en;
+ wire idxs_T_1873_clk;
+ wire [11:0] idxs_T_1876_data;
+ wire [5:0] idxs_T_1876_addr;
+ wire idxs_T_1876_en;
+ wire idxs_T_1876_clk;
+ wire [11:0] idxs_T_1879_data;
+ wire [5:0] idxs_T_1879_addr;
+ wire idxs_T_1879_en;
+ wire idxs_T_1879_clk;
+ wire [11:0] idxs_T_1882_data;
+ wire [5:0] idxs_T_1882_addr;
+ wire idxs_T_1882_en;
+ wire idxs_T_1882_clk;
+ wire [11:0] idxs_T_2360_data;
+ wire [5:0] idxs_T_2360_addr;
+ wire idxs_T_2360_en;
+ wire idxs_T_2360_clk;
+ wire [11:0] idxs_T_2363_data;
+ wire [5:0] idxs_T_2363_addr;
+ wire idxs_T_2363_en;
+ wire idxs_T_2363_clk;
+ wire [11:0] idxs_T_2366_data;
+ wire [5:0] idxs_T_2366_addr;
+ wire idxs_T_2366_en;
+ wire idxs_T_2366_clk;
+ wire [11:0] idxs_T_2369_data;
+ wire [5:0] idxs_T_2369_addr;
+ wire idxs_T_2369_en;
+ wire idxs_T_2369_clk;
+ wire [11:0] idxs_T_2372_data;
+ wire [5:0] idxs_T_2372_addr;
+ wire idxs_T_2372_en;
+ wire idxs_T_2372_clk;
+ wire [11:0] idxs_T_2375_data;
+ wire [5:0] idxs_T_2375_addr;
+ wire idxs_T_2375_en;
+ wire idxs_T_2375_clk;
+ wire [11:0] idxs_T_2378_data;
+ wire [5:0] idxs_T_2378_addr;
+ wire idxs_T_2378_en;
+ wire idxs_T_2378_clk;
+ wire [11:0] idxs_T_2381_data;
+ wire [5:0] idxs_T_2381_addr;
+ wire idxs_T_2381_en;
+ wire idxs_T_2381_clk;
+ wire [11:0] idxs_T_2384_data;
+ wire [5:0] idxs_T_2384_addr;
+ wire idxs_T_2384_en;
+ wire idxs_T_2384_clk;
+ wire [11:0] idxs_T_2387_data;
+ wire [5:0] idxs_T_2387_addr;
+ wire idxs_T_2387_en;
+ wire idxs_T_2387_clk;
+ wire [11:0] idxs_T_2390_data;
+ wire [5:0] idxs_T_2390_addr;
+ wire idxs_T_2390_en;
+ wire idxs_T_2390_clk;
+ wire [11:0] idxs_T_2393_data;
+ wire [5:0] idxs_T_2393_addr;
+ wire idxs_T_2393_en;
+ wire idxs_T_2393_clk;
+ wire [11:0] idxs_T_2396_data;
+ wire [5:0] idxs_T_2396_addr;
+ wire idxs_T_2396_en;
+ wire idxs_T_2396_clk;
+ wire [11:0] idxs_T_2399_data;
+ wire [5:0] idxs_T_2399_addr;
+ wire idxs_T_2399_en;
+ wire idxs_T_2399_clk;
+ wire [11:0] idxs_T_2402_data;
+ wire [5:0] idxs_T_2402_addr;
+ wire idxs_T_2402_en;
+ wire idxs_T_2402_clk;
+ wire [11:0] idxs_T_2405_data;
+ wire [5:0] idxs_T_2405_addr;
+ wire idxs_T_2405_en;
+ wire idxs_T_2405_clk;
+ wire [11:0] idxs_T_2408_data;
+ wire [5:0] idxs_T_2408_addr;
+ wire idxs_T_2408_en;
+ wire idxs_T_2408_clk;
+ wire [11:0] idxs_T_2411_data;
+ wire [5:0] idxs_T_2411_addr;
+ wire idxs_T_2411_en;
+ wire idxs_T_2411_clk;
+ wire [11:0] idxs_T_2414_data;
+ wire [5:0] idxs_T_2414_addr;
+ wire idxs_T_2414_en;
+ wire idxs_T_2414_clk;
+ wire [11:0] idxs_T_2417_data;
+ wire [5:0] idxs_T_2417_addr;
+ wire idxs_T_2417_en;
+ wire idxs_T_2417_clk;
+ wire [11:0] idxs_T_2420_data;
+ wire [5:0] idxs_T_2420_addr;
+ wire idxs_T_2420_en;
+ wire idxs_T_2420_clk;
+ wire [11:0] idxs_T_2423_data;
+ wire [5:0] idxs_T_2423_addr;
+ wire idxs_T_2423_en;
+ wire idxs_T_2423_clk;
+ wire [11:0] idxs_T_2426_data;
+ wire [5:0] idxs_T_2426_addr;
+ wire idxs_T_2426_en;
+ wire idxs_T_2426_clk;
+ wire [11:0] idxs_T_2429_data;
+ wire [5:0] idxs_T_2429_addr;
+ wire idxs_T_2429_en;
+ wire idxs_T_2429_clk;
+ wire [11:0] idxs_T_2432_data;
+ wire [5:0] idxs_T_2432_addr;
+ wire idxs_T_2432_en;
+ wire idxs_T_2432_clk;
+ wire [11:0] idxs_T_2435_data;
+ wire [5:0] idxs_T_2435_addr;
+ wire idxs_T_2435_en;
+ wire idxs_T_2435_clk;
+ wire [11:0] idxs_T_2438_data;
+ wire [5:0] idxs_T_2438_addr;
+ wire idxs_T_2438_en;
+ wire idxs_T_2438_clk;
+ wire [11:0] idxs_T_2441_data;
+ wire [5:0] idxs_T_2441_addr;
+ wire idxs_T_2441_en;
+ wire idxs_T_2441_clk;
+ wire [11:0] idxs_T_2444_data;
+ wire [5:0] idxs_T_2444_addr;
+ wire idxs_T_2444_en;
+ wire idxs_T_2444_clk;
+ wire [11:0] idxs_T_2447_data;
+ wire [5:0] idxs_T_2447_addr;
+ wire idxs_T_2447_en;
+ wire idxs_T_2447_clk;
+ wire [11:0] idxs_T_2450_data;
+ wire [5:0] idxs_T_2450_addr;
+ wire idxs_T_2450_en;
+ wire idxs_T_2450_clk;
+ wire [11:0] idxs_T_2453_data;
+ wire [5:0] idxs_T_2453_addr;
+ wire idxs_T_2453_en;
+ wire idxs_T_2453_clk;
+ wire [11:0] idxs_T_2456_data;
+ wire [5:0] idxs_T_2456_addr;
+ wire idxs_T_2456_en;
+ wire idxs_T_2456_clk;
+ wire [11:0] idxs_T_2459_data;
+ wire [5:0] idxs_T_2459_addr;
+ wire idxs_T_2459_en;
+ wire idxs_T_2459_clk;
+ wire [11:0] idxs_T_2462_data;
+ wire [5:0] idxs_T_2462_addr;
+ wire idxs_T_2462_en;
+ wire idxs_T_2462_clk;
+ wire [11:0] idxs_T_2465_data;
+ wire [5:0] idxs_T_2465_addr;
+ wire idxs_T_2465_en;
+ wire idxs_T_2465_clk;
+ wire [11:0] idxs_T_2468_data;
+ wire [5:0] idxs_T_2468_addr;
+ wire idxs_T_2468_en;
+ wire idxs_T_2468_clk;
+ wire [11:0] idxs_T_2471_data;
+ wire [5:0] idxs_T_2471_addr;
+ wire idxs_T_2471_en;
+ wire idxs_T_2471_clk;
+ wire [11:0] idxs_T_2474_data;
+ wire [5:0] idxs_T_2474_addr;
+ wire idxs_T_2474_en;
+ wire idxs_T_2474_clk;
+ wire [11:0] idxs_T_2477_data;
+ wire [5:0] idxs_T_2477_addr;
+ wire idxs_T_2477_en;
+ wire idxs_T_2477_clk;
+ wire [11:0] idxs_T_2480_data;
+ wire [5:0] idxs_T_2480_addr;
+ wire idxs_T_2480_en;
+ wire idxs_T_2480_clk;
+ wire [11:0] idxs_T_2483_data;
+ wire [5:0] idxs_T_2483_addr;
+ wire idxs_T_2483_en;
+ wire idxs_T_2483_clk;
+ wire [11:0] idxs_T_2486_data;
+ wire [5:0] idxs_T_2486_addr;
+ wire idxs_T_2486_en;
+ wire idxs_T_2486_clk;
+ wire [11:0] idxs_T_2489_data;
+ wire [5:0] idxs_T_2489_addr;
+ wire idxs_T_2489_en;
+ wire idxs_T_2489_clk;
+ wire [11:0] idxs_T_2492_data;
+ wire [5:0] idxs_T_2492_addr;
+ wire idxs_T_2492_en;
+ wire idxs_T_2492_clk;
+ wire [11:0] idxs_T_2495_data;
+ wire [5:0] idxs_T_2495_addr;
+ wire idxs_T_2495_en;
+ wire idxs_T_2495_clk;
+ wire [11:0] idxs_T_2498_data;
+ wire [5:0] idxs_T_2498_addr;
+ wire idxs_T_2498_en;
+ wire idxs_T_2498_clk;
+ wire [11:0] idxs_T_2501_data;
+ wire [5:0] idxs_T_2501_addr;
+ wire idxs_T_2501_en;
+ wire idxs_T_2501_clk;
+ wire [11:0] idxs_T_2504_data;
+ wire [5:0] idxs_T_2504_addr;
+ wire idxs_T_2504_en;
+ wire idxs_T_2504_clk;
+ wire [11:0] idxs_T_2507_data;
+ wire [5:0] idxs_T_2507_addr;
+ wire idxs_T_2507_en;
+ wire idxs_T_2507_clk;
+ wire [11:0] idxs_T_2510_data;
+ wire [5:0] idxs_T_2510_addr;
+ wire idxs_T_2510_en;
+ wire idxs_T_2510_clk;
+ wire [11:0] idxs_T_2513_data;
+ wire [5:0] idxs_T_2513_addr;
+ wire idxs_T_2513_en;
+ wire idxs_T_2513_clk;
+ wire [11:0] idxs_T_2516_data;
+ wire [5:0] idxs_T_2516_addr;
+ wire idxs_T_2516_en;
+ wire idxs_T_2516_clk;
+ wire [11:0] idxs_T_2519_data;
+ wire [5:0] idxs_T_2519_addr;
+ wire idxs_T_2519_en;
+ wire idxs_T_2519_clk;
+ wire [11:0] idxs_T_2522_data;
+ wire [5:0] idxs_T_2522_addr;
+ wire idxs_T_2522_en;
+ wire idxs_T_2522_clk;
+ wire [11:0] idxs_T_2525_data;
+ wire [5:0] idxs_T_2525_addr;
+ wire idxs_T_2525_en;
+ wire idxs_T_2525_clk;
+ wire [11:0] idxs_T_2528_data;
+ wire [5:0] idxs_T_2528_addr;
+ wire idxs_T_2528_en;
+ wire idxs_T_2528_clk;
+ wire [11:0] idxs_T_2531_data;
+ wire [5:0] idxs_T_2531_addr;
+ wire idxs_T_2531_en;
+ wire idxs_T_2531_clk;
+ wire [11:0] idxs_T_2534_data;
+ wire [5:0] idxs_T_2534_addr;
+ wire idxs_T_2534_en;
+ wire idxs_T_2534_clk;
+ wire [11:0] idxs_T_2537_data;
+ wire [5:0] idxs_T_2537_addr;
+ wire idxs_T_2537_en;
+ wire idxs_T_2537_clk;
+ wire [11:0] idxs_T_2540_data;
+ wire [5:0] idxs_T_2540_addr;
+ wire idxs_T_2540_en;
+ wire idxs_T_2540_clk;
+ wire [11:0] idxs_T_2543_data;
+ wire [5:0] idxs_T_2543_addr;
+ wire idxs_T_2543_en;
+ wire idxs_T_2543_clk;
+ wire [11:0] idxs_T_3470_data;
+ wire [5:0] idxs_T_3470_addr;
+ wire idxs_T_3470_mask;
+ wire idxs_T_3470_en;
+ wire idxs_T_3470_clk;
+ reg [2:0] idxPages [0:61];
+ wire [2:0] idxPages_T_590_data;
+ wire [5:0] idxPages_T_590_addr;
+ wire idxPages_T_590_en;
+ wire idxPages_T_590_clk;
+ wire [2:0] idxPages_T_595_data;
+ wire [5:0] idxPages_T_595_addr;
+ wire idxPages_T_595_en;
+ wire idxPages_T_595_clk;
+ wire [2:0] idxPages_T_600_data;
+ wire [5:0] idxPages_T_600_addr;
+ wire idxPages_T_600_en;
+ wire idxPages_T_600_clk;
+ wire [2:0] idxPages_T_605_data;
+ wire [5:0] idxPages_T_605_addr;
+ wire idxPages_T_605_en;
+ wire idxPages_T_605_clk;
+ wire [2:0] idxPages_T_610_data;
+ wire [5:0] idxPages_T_610_addr;
+ wire idxPages_T_610_en;
+ wire idxPages_T_610_clk;
+ wire [2:0] idxPages_T_615_data;
+ wire [5:0] idxPages_T_615_addr;
+ wire idxPages_T_615_en;
+ wire idxPages_T_615_clk;
+ wire [2:0] idxPages_T_620_data;
+ wire [5:0] idxPages_T_620_addr;
+ wire idxPages_T_620_en;
+ wire idxPages_T_620_clk;
+ wire [2:0] idxPages_T_625_data;
+ wire [5:0] idxPages_T_625_addr;
+ wire idxPages_T_625_en;
+ wire idxPages_T_625_clk;
+ wire [2:0] idxPages_T_630_data;
+ wire [5:0] idxPages_T_630_addr;
+ wire idxPages_T_630_en;
+ wire idxPages_T_630_clk;
+ wire [2:0] idxPages_T_635_data;
+ wire [5:0] idxPages_T_635_addr;
+ wire idxPages_T_635_en;
+ wire idxPages_T_635_clk;
+ wire [2:0] idxPages_T_640_data;
+ wire [5:0] idxPages_T_640_addr;
+ wire idxPages_T_640_en;
+ wire idxPages_T_640_clk;
+ wire [2:0] idxPages_T_645_data;
+ wire [5:0] idxPages_T_645_addr;
+ wire idxPages_T_645_en;
+ wire idxPages_T_645_clk;
+ wire [2:0] idxPages_T_650_data;
+ wire [5:0] idxPages_T_650_addr;
+ wire idxPages_T_650_en;
+ wire idxPages_T_650_clk;
+ wire [2:0] idxPages_T_655_data;
+ wire [5:0] idxPages_T_655_addr;
+ wire idxPages_T_655_en;
+ wire idxPages_T_655_clk;
+ wire [2:0] idxPages_T_660_data;
+ wire [5:0] idxPages_T_660_addr;
+ wire idxPages_T_660_en;
+ wire idxPages_T_660_clk;
+ wire [2:0] idxPages_T_665_data;
+ wire [5:0] idxPages_T_665_addr;
+ wire idxPages_T_665_en;
+ wire idxPages_T_665_clk;
+ wire [2:0] idxPages_T_670_data;
+ wire [5:0] idxPages_T_670_addr;
+ wire idxPages_T_670_en;
+ wire idxPages_T_670_clk;
+ wire [2:0] idxPages_T_675_data;
+ wire [5:0] idxPages_T_675_addr;
+ wire idxPages_T_675_en;
+ wire idxPages_T_675_clk;
+ wire [2:0] idxPages_T_680_data;
+ wire [5:0] idxPages_T_680_addr;
+ wire idxPages_T_680_en;
+ wire idxPages_T_680_clk;
+ wire [2:0] idxPages_T_685_data;
+ wire [5:0] idxPages_T_685_addr;
+ wire idxPages_T_685_en;
+ wire idxPages_T_685_clk;
+ wire [2:0] idxPages_T_690_data;
+ wire [5:0] idxPages_T_690_addr;
+ wire idxPages_T_690_en;
+ wire idxPages_T_690_clk;
+ wire [2:0] idxPages_T_695_data;
+ wire [5:0] idxPages_T_695_addr;
+ wire idxPages_T_695_en;
+ wire idxPages_T_695_clk;
+ wire [2:0] idxPages_T_700_data;
+ wire [5:0] idxPages_T_700_addr;
+ wire idxPages_T_700_en;
+ wire idxPages_T_700_clk;
+ wire [2:0] idxPages_T_705_data;
+ wire [5:0] idxPages_T_705_addr;
+ wire idxPages_T_705_en;
+ wire idxPages_T_705_clk;
+ wire [2:0] idxPages_T_710_data;
+ wire [5:0] idxPages_T_710_addr;
+ wire idxPages_T_710_en;
+ wire idxPages_T_710_clk;
+ wire [2:0] idxPages_T_715_data;
+ wire [5:0] idxPages_T_715_addr;
+ wire idxPages_T_715_en;
+ wire idxPages_T_715_clk;
+ wire [2:0] idxPages_T_720_data;
+ wire [5:0] idxPages_T_720_addr;
+ wire idxPages_T_720_en;
+ wire idxPages_T_720_clk;
+ wire [2:0] idxPages_T_725_data;
+ wire [5:0] idxPages_T_725_addr;
+ wire idxPages_T_725_en;
+ wire idxPages_T_725_clk;
+ wire [2:0] idxPages_T_730_data;
+ wire [5:0] idxPages_T_730_addr;
+ wire idxPages_T_730_en;
+ wire idxPages_T_730_clk;
+ wire [2:0] idxPages_T_735_data;
+ wire [5:0] idxPages_T_735_addr;
+ wire idxPages_T_735_en;
+ wire idxPages_T_735_clk;
+ wire [2:0] idxPages_T_740_data;
+ wire [5:0] idxPages_T_740_addr;
+ wire idxPages_T_740_en;
+ wire idxPages_T_740_clk;
+ wire [2:0] idxPages_T_745_data;
+ wire [5:0] idxPages_T_745_addr;
+ wire idxPages_T_745_en;
+ wire idxPages_T_745_clk;
+ wire [2:0] idxPages_T_750_data;
+ wire [5:0] idxPages_T_750_addr;
+ wire idxPages_T_750_en;
+ wire idxPages_T_750_clk;
+ wire [2:0] idxPages_T_755_data;
+ wire [5:0] idxPages_T_755_addr;
+ wire idxPages_T_755_en;
+ wire idxPages_T_755_clk;
+ wire [2:0] idxPages_T_760_data;
+ wire [5:0] idxPages_T_760_addr;
+ wire idxPages_T_760_en;
+ wire idxPages_T_760_clk;
+ wire [2:0] idxPages_T_765_data;
+ wire [5:0] idxPages_T_765_addr;
+ wire idxPages_T_765_en;
+ wire idxPages_T_765_clk;
+ wire [2:0] idxPages_T_770_data;
+ wire [5:0] idxPages_T_770_addr;
+ wire idxPages_T_770_en;
+ wire idxPages_T_770_clk;
+ wire [2:0] idxPages_T_775_data;
+ wire [5:0] idxPages_T_775_addr;
+ wire idxPages_T_775_en;
+ wire idxPages_T_775_clk;
+ wire [2:0] idxPages_T_780_data;
+ wire [5:0] idxPages_T_780_addr;
+ wire idxPages_T_780_en;
+ wire idxPages_T_780_clk;
+ wire [2:0] idxPages_T_785_data;
+ wire [5:0] idxPages_T_785_addr;
+ wire idxPages_T_785_en;
+ wire idxPages_T_785_clk;
+ wire [2:0] idxPages_T_790_data;
+ wire [5:0] idxPages_T_790_addr;
+ wire idxPages_T_790_en;
+ wire idxPages_T_790_clk;
+ wire [2:0] idxPages_T_795_data;
+ wire [5:0] idxPages_T_795_addr;
+ wire idxPages_T_795_en;
+ wire idxPages_T_795_clk;
+ wire [2:0] idxPages_T_800_data;
+ wire [5:0] idxPages_T_800_addr;
+ wire idxPages_T_800_en;
+ wire idxPages_T_800_clk;
+ wire [2:0] idxPages_T_805_data;
+ wire [5:0] idxPages_T_805_addr;
+ wire idxPages_T_805_en;
+ wire idxPages_T_805_clk;
+ wire [2:0] idxPages_T_810_data;
+ wire [5:0] idxPages_T_810_addr;
+ wire idxPages_T_810_en;
+ wire idxPages_T_810_clk;
+ wire [2:0] idxPages_T_815_data;
+ wire [5:0] idxPages_T_815_addr;
+ wire idxPages_T_815_en;
+ wire idxPages_T_815_clk;
+ wire [2:0] idxPages_T_820_data;
+ wire [5:0] idxPages_T_820_addr;
+ wire idxPages_T_820_en;
+ wire idxPages_T_820_clk;
+ wire [2:0] idxPages_T_825_data;
+ wire [5:0] idxPages_T_825_addr;
+ wire idxPages_T_825_en;
+ wire idxPages_T_825_clk;
+ wire [2:0] idxPages_T_830_data;
+ wire [5:0] idxPages_T_830_addr;
+ wire idxPages_T_830_en;
+ wire idxPages_T_830_clk;
+ wire [2:0] idxPages_T_835_data;
+ wire [5:0] idxPages_T_835_addr;
+ wire idxPages_T_835_en;
+ wire idxPages_T_835_clk;
+ wire [2:0] idxPages_T_840_data;
+ wire [5:0] idxPages_T_840_addr;
+ wire idxPages_T_840_en;
+ wire idxPages_T_840_clk;
+ wire [2:0] idxPages_T_845_data;
+ wire [5:0] idxPages_T_845_addr;
+ wire idxPages_T_845_en;
+ wire idxPages_T_845_clk;
+ wire [2:0] idxPages_T_850_data;
+ wire [5:0] idxPages_T_850_addr;
+ wire idxPages_T_850_en;
+ wire idxPages_T_850_clk;
+ wire [2:0] idxPages_T_855_data;
+ wire [5:0] idxPages_T_855_addr;
+ wire idxPages_T_855_en;
+ wire idxPages_T_855_clk;
+ wire [2:0] idxPages_T_860_data;
+ wire [5:0] idxPages_T_860_addr;
+ wire idxPages_T_860_en;
+ wire idxPages_T_860_clk;
+ wire [2:0] idxPages_T_865_data;
+ wire [5:0] idxPages_T_865_addr;
+ wire idxPages_T_865_en;
+ wire idxPages_T_865_clk;
+ wire [2:0] idxPages_T_870_data;
+ wire [5:0] idxPages_T_870_addr;
+ wire idxPages_T_870_en;
+ wire idxPages_T_870_clk;
+ wire [2:0] idxPages_T_875_data;
+ wire [5:0] idxPages_T_875_addr;
+ wire idxPages_T_875_en;
+ wire idxPages_T_875_clk;
+ wire [2:0] idxPages_T_880_data;
+ wire [5:0] idxPages_T_880_addr;
+ wire idxPages_T_880_en;
+ wire idxPages_T_880_clk;
+ wire [2:0] idxPages_T_885_data;
+ wire [5:0] idxPages_T_885_addr;
+ wire idxPages_T_885_en;
+ wire idxPages_T_885_clk;
+ wire [2:0] idxPages_T_890_data;
+ wire [5:0] idxPages_T_890_addr;
+ wire idxPages_T_890_en;
+ wire idxPages_T_890_clk;
+ wire [2:0] idxPages_T_895_data;
+ wire [5:0] idxPages_T_895_addr;
+ wire idxPages_T_895_en;
+ wire idxPages_T_895_clk;
+ wire [2:0] idxPages_T_3472_data;
+ wire [5:0] idxPages_T_3472_addr;
+ wire idxPages_T_3472_mask;
+ wire idxPages_T_3472_en;
+ wire idxPages_T_3472_clk;
+ reg [11:0] tgts [0:61];
+ wire [11:0] tgts_T_3870_data;
+ wire [5:0] tgts_T_3870_addr;
+ wire tgts_T_3870_en;
+ wire tgts_T_3870_clk;
+ wire [11:0] tgts_T_3872_data;
+ wire [5:0] tgts_T_3872_addr;
+ wire tgts_T_3872_en;
+ wire tgts_T_3872_clk;
+ wire [11:0] tgts_T_3874_data;
+ wire [5:0] tgts_T_3874_addr;
+ wire tgts_T_3874_en;
+ wire tgts_T_3874_clk;
+ wire [11:0] tgts_T_3876_data;
+ wire [5:0] tgts_T_3876_addr;
+ wire tgts_T_3876_en;
+ wire tgts_T_3876_clk;
+ wire [11:0] tgts_T_3878_data;
+ wire [5:0] tgts_T_3878_addr;
+ wire tgts_T_3878_en;
+ wire tgts_T_3878_clk;
+ wire [11:0] tgts_T_3880_data;
+ wire [5:0] tgts_T_3880_addr;
+ wire tgts_T_3880_en;
+ wire tgts_T_3880_clk;
+ wire [11:0] tgts_T_3882_data;
+ wire [5:0] tgts_T_3882_addr;
+ wire tgts_T_3882_en;
+ wire tgts_T_3882_clk;
+ wire [11:0] tgts_T_3884_data;
+ wire [5:0] tgts_T_3884_addr;
+ wire tgts_T_3884_en;
+ wire tgts_T_3884_clk;
+ wire [11:0] tgts_T_3886_data;
+ wire [5:0] tgts_T_3886_addr;
+ wire tgts_T_3886_en;
+ wire tgts_T_3886_clk;
+ wire [11:0] tgts_T_3888_data;
+ wire [5:0] tgts_T_3888_addr;
+ wire tgts_T_3888_en;
+ wire tgts_T_3888_clk;
+ wire [11:0] tgts_T_3890_data;
+ wire [5:0] tgts_T_3890_addr;
+ wire tgts_T_3890_en;
+ wire tgts_T_3890_clk;
+ wire [11:0] tgts_T_3892_data;
+ wire [5:0] tgts_T_3892_addr;
+ wire tgts_T_3892_en;
+ wire tgts_T_3892_clk;
+ wire [11:0] tgts_T_3894_data;
+ wire [5:0] tgts_T_3894_addr;
+ wire tgts_T_3894_en;
+ wire tgts_T_3894_clk;
+ wire [11:0] tgts_T_3896_data;
+ wire [5:0] tgts_T_3896_addr;
+ wire tgts_T_3896_en;
+ wire tgts_T_3896_clk;
+ wire [11:0] tgts_T_3898_data;
+ wire [5:0] tgts_T_3898_addr;
+ wire tgts_T_3898_en;
+ wire tgts_T_3898_clk;
+ wire [11:0] tgts_T_3900_data;
+ wire [5:0] tgts_T_3900_addr;
+ wire tgts_T_3900_en;
+ wire tgts_T_3900_clk;
+ wire [11:0] tgts_T_3902_data;
+ wire [5:0] tgts_T_3902_addr;
+ wire tgts_T_3902_en;
+ wire tgts_T_3902_clk;
+ wire [11:0] tgts_T_3904_data;
+ wire [5:0] tgts_T_3904_addr;
+ wire tgts_T_3904_en;
+ wire tgts_T_3904_clk;
+ wire [11:0] tgts_T_3906_data;
+ wire [5:0] tgts_T_3906_addr;
+ wire tgts_T_3906_en;
+ wire tgts_T_3906_clk;
+ wire [11:0] tgts_T_3908_data;
+ wire [5:0] tgts_T_3908_addr;
+ wire tgts_T_3908_en;
+ wire tgts_T_3908_clk;
+ wire [11:0] tgts_T_3910_data;
+ wire [5:0] tgts_T_3910_addr;
+ wire tgts_T_3910_en;
+ wire tgts_T_3910_clk;
+ wire [11:0] tgts_T_3912_data;
+ wire [5:0] tgts_T_3912_addr;
+ wire tgts_T_3912_en;
+ wire tgts_T_3912_clk;
+ wire [11:0] tgts_T_3914_data;
+ wire [5:0] tgts_T_3914_addr;
+ wire tgts_T_3914_en;
+ wire tgts_T_3914_clk;
+ wire [11:0] tgts_T_3916_data;
+ wire [5:0] tgts_T_3916_addr;
+ wire tgts_T_3916_en;
+ wire tgts_T_3916_clk;
+ wire [11:0] tgts_T_3918_data;
+ wire [5:0] tgts_T_3918_addr;
+ wire tgts_T_3918_en;
+ wire tgts_T_3918_clk;
+ wire [11:0] tgts_T_3920_data;
+ wire [5:0] tgts_T_3920_addr;
+ wire tgts_T_3920_en;
+ wire tgts_T_3920_clk;
+ wire [11:0] tgts_T_3922_data;
+ wire [5:0] tgts_T_3922_addr;
+ wire tgts_T_3922_en;
+ wire tgts_T_3922_clk;
+ wire [11:0] tgts_T_3924_data;
+ wire [5:0] tgts_T_3924_addr;
+ wire tgts_T_3924_en;
+ wire tgts_T_3924_clk;
+ wire [11:0] tgts_T_3926_data;
+ wire [5:0] tgts_T_3926_addr;
+ wire tgts_T_3926_en;
+ wire tgts_T_3926_clk;
+ wire [11:0] tgts_T_3928_data;
+ wire [5:0] tgts_T_3928_addr;
+ wire tgts_T_3928_en;
+ wire tgts_T_3928_clk;
+ wire [11:0] tgts_T_3930_data;
+ wire [5:0] tgts_T_3930_addr;
+ wire tgts_T_3930_en;
+ wire tgts_T_3930_clk;
+ wire [11:0] tgts_T_3932_data;
+ wire [5:0] tgts_T_3932_addr;
+ wire tgts_T_3932_en;
+ wire tgts_T_3932_clk;
+ wire [11:0] tgts_T_3934_data;
+ wire [5:0] tgts_T_3934_addr;
+ wire tgts_T_3934_en;
+ wire tgts_T_3934_clk;
+ wire [11:0] tgts_T_3936_data;
+ wire [5:0] tgts_T_3936_addr;
+ wire tgts_T_3936_en;
+ wire tgts_T_3936_clk;
+ wire [11:0] tgts_T_3938_data;
+ wire [5:0] tgts_T_3938_addr;
+ wire tgts_T_3938_en;
+ wire tgts_T_3938_clk;
+ wire [11:0] tgts_T_3940_data;
+ wire [5:0] tgts_T_3940_addr;
+ wire tgts_T_3940_en;
+ wire tgts_T_3940_clk;
+ wire [11:0] tgts_T_3942_data;
+ wire [5:0] tgts_T_3942_addr;
+ wire tgts_T_3942_en;
+ wire tgts_T_3942_clk;
+ wire [11:0] tgts_T_3944_data;
+ wire [5:0] tgts_T_3944_addr;
+ wire tgts_T_3944_en;
+ wire tgts_T_3944_clk;
+ wire [11:0] tgts_T_3946_data;
+ wire [5:0] tgts_T_3946_addr;
+ wire tgts_T_3946_en;
+ wire tgts_T_3946_clk;
+ wire [11:0] tgts_T_3948_data;
+ wire [5:0] tgts_T_3948_addr;
+ wire tgts_T_3948_en;
+ wire tgts_T_3948_clk;
+ wire [11:0] tgts_T_3950_data;
+ wire [5:0] tgts_T_3950_addr;
+ wire tgts_T_3950_en;
+ wire tgts_T_3950_clk;
+ wire [11:0] tgts_T_3952_data;
+ wire [5:0] tgts_T_3952_addr;
+ wire tgts_T_3952_en;
+ wire tgts_T_3952_clk;
+ wire [11:0] tgts_T_3954_data;
+ wire [5:0] tgts_T_3954_addr;
+ wire tgts_T_3954_en;
+ wire tgts_T_3954_clk;
+ wire [11:0] tgts_T_3956_data;
+ wire [5:0] tgts_T_3956_addr;
+ wire tgts_T_3956_en;
+ wire tgts_T_3956_clk;
+ wire [11:0] tgts_T_3958_data;
+ wire [5:0] tgts_T_3958_addr;
+ wire tgts_T_3958_en;
+ wire tgts_T_3958_clk;
+ wire [11:0] tgts_T_3960_data;
+ wire [5:0] tgts_T_3960_addr;
+ wire tgts_T_3960_en;
+ wire tgts_T_3960_clk;
+ wire [11:0] tgts_T_3962_data;
+ wire [5:0] tgts_T_3962_addr;
+ wire tgts_T_3962_en;
+ wire tgts_T_3962_clk;
+ wire [11:0] tgts_T_3964_data;
+ wire [5:0] tgts_T_3964_addr;
+ wire tgts_T_3964_en;
+ wire tgts_T_3964_clk;
+ wire [11:0] tgts_T_3966_data;
+ wire [5:0] tgts_T_3966_addr;
+ wire tgts_T_3966_en;
+ wire tgts_T_3966_clk;
+ wire [11:0] tgts_T_3968_data;
+ wire [5:0] tgts_T_3968_addr;
+ wire tgts_T_3968_en;
+ wire tgts_T_3968_clk;
+ wire [11:0] tgts_T_3970_data;
+ wire [5:0] tgts_T_3970_addr;
+ wire tgts_T_3970_en;
+ wire tgts_T_3970_clk;
+ wire [11:0] tgts_T_3972_data;
+ wire [5:0] tgts_T_3972_addr;
+ wire tgts_T_3972_en;
+ wire tgts_T_3972_clk;
+ wire [11:0] tgts_T_3974_data;
+ wire [5:0] tgts_T_3974_addr;
+ wire tgts_T_3974_en;
+ wire tgts_T_3974_clk;
+ wire [11:0] tgts_T_3976_data;
+ wire [5:0] tgts_T_3976_addr;
+ wire tgts_T_3976_en;
+ wire tgts_T_3976_clk;
+ wire [11:0] tgts_T_3978_data;
+ wire [5:0] tgts_T_3978_addr;
+ wire tgts_T_3978_en;
+ wire tgts_T_3978_clk;
+ wire [11:0] tgts_T_3980_data;
+ wire [5:0] tgts_T_3980_addr;
+ wire tgts_T_3980_en;
+ wire tgts_T_3980_clk;
+ wire [11:0] tgts_T_3982_data;
+ wire [5:0] tgts_T_3982_addr;
+ wire tgts_T_3982_en;
+ wire tgts_T_3982_clk;
+ wire [11:0] tgts_T_3984_data;
+ wire [5:0] tgts_T_3984_addr;
+ wire tgts_T_3984_en;
+ wire tgts_T_3984_clk;
+ wire [11:0] tgts_T_3986_data;
+ wire [5:0] tgts_T_3986_addr;
+ wire tgts_T_3986_en;
+ wire tgts_T_3986_clk;
+ wire [11:0] tgts_T_3988_data;
+ wire [5:0] tgts_T_3988_addr;
+ wire tgts_T_3988_en;
+ wire tgts_T_3988_clk;
+ wire [11:0] tgts_T_3990_data;
+ wire [5:0] tgts_T_3990_addr;
+ wire tgts_T_3990_en;
+ wire tgts_T_3990_clk;
+ wire [11:0] tgts_T_3992_data;
+ wire [5:0] tgts_T_3992_addr;
+ wire tgts_T_3992_en;
+ wire tgts_T_3992_clk;
+ wire [11:0] tgts_T_3471_data;
+ wire [5:0] tgts_T_3471_addr;
+ wire tgts_T_3471_mask;
+ wire tgts_T_3471_en;
+ wire tgts_T_3471_clk;
+ reg [2:0] tgtPages [0:61];
+ wire [2:0] tgtPages_T_900_data;
+ wire [5:0] tgtPages_T_900_addr;
+ wire tgtPages_T_900_en;
+ wire tgtPages_T_900_clk;
+ wire [2:0] tgtPages_T_905_data;
+ wire [5:0] tgtPages_T_905_addr;
+ wire tgtPages_T_905_en;
+ wire tgtPages_T_905_clk;
+ wire [2:0] tgtPages_T_910_data;
+ wire [5:0] tgtPages_T_910_addr;
+ wire tgtPages_T_910_en;
+ wire tgtPages_T_910_clk;
+ wire [2:0] tgtPages_T_915_data;
+ wire [5:0] tgtPages_T_915_addr;
+ wire tgtPages_T_915_en;
+ wire tgtPages_T_915_clk;
+ wire [2:0] tgtPages_T_920_data;
+ wire [5:0] tgtPages_T_920_addr;
+ wire tgtPages_T_920_en;
+ wire tgtPages_T_920_clk;
+ wire [2:0] tgtPages_T_925_data;
+ wire [5:0] tgtPages_T_925_addr;
+ wire tgtPages_T_925_en;
+ wire tgtPages_T_925_clk;
+ wire [2:0] tgtPages_T_930_data;
+ wire [5:0] tgtPages_T_930_addr;
+ wire tgtPages_T_930_en;
+ wire tgtPages_T_930_clk;
+ wire [2:0] tgtPages_T_935_data;
+ wire [5:0] tgtPages_T_935_addr;
+ wire tgtPages_T_935_en;
+ wire tgtPages_T_935_clk;
+ wire [2:0] tgtPages_T_940_data;
+ wire [5:0] tgtPages_T_940_addr;
+ wire tgtPages_T_940_en;
+ wire tgtPages_T_940_clk;
+ wire [2:0] tgtPages_T_945_data;
+ wire [5:0] tgtPages_T_945_addr;
+ wire tgtPages_T_945_en;
+ wire tgtPages_T_945_clk;
+ wire [2:0] tgtPages_T_950_data;
+ wire [5:0] tgtPages_T_950_addr;
+ wire tgtPages_T_950_en;
+ wire tgtPages_T_950_clk;
+ wire [2:0] tgtPages_T_955_data;
+ wire [5:0] tgtPages_T_955_addr;
+ wire tgtPages_T_955_en;
+ wire tgtPages_T_955_clk;
+ wire [2:0] tgtPages_T_960_data;
+ wire [5:0] tgtPages_T_960_addr;
+ wire tgtPages_T_960_en;
+ wire tgtPages_T_960_clk;
+ wire [2:0] tgtPages_T_965_data;
+ wire [5:0] tgtPages_T_965_addr;
+ wire tgtPages_T_965_en;
+ wire tgtPages_T_965_clk;
+ wire [2:0] tgtPages_T_970_data;
+ wire [5:0] tgtPages_T_970_addr;
+ wire tgtPages_T_970_en;
+ wire tgtPages_T_970_clk;
+ wire [2:0] tgtPages_T_975_data;
+ wire [5:0] tgtPages_T_975_addr;
+ wire tgtPages_T_975_en;
+ wire tgtPages_T_975_clk;
+ wire [2:0] tgtPages_T_980_data;
+ wire [5:0] tgtPages_T_980_addr;
+ wire tgtPages_T_980_en;
+ wire tgtPages_T_980_clk;
+ wire [2:0] tgtPages_T_985_data;
+ wire [5:0] tgtPages_T_985_addr;
+ wire tgtPages_T_985_en;
+ wire tgtPages_T_985_clk;
+ wire [2:0] tgtPages_T_990_data;
+ wire [5:0] tgtPages_T_990_addr;
+ wire tgtPages_T_990_en;
+ wire tgtPages_T_990_clk;
+ wire [2:0] tgtPages_T_995_data;
+ wire [5:0] tgtPages_T_995_addr;
+ wire tgtPages_T_995_en;
+ wire tgtPages_T_995_clk;
+ wire [2:0] tgtPages_T_1000_data;
+ wire [5:0] tgtPages_T_1000_addr;
+ wire tgtPages_T_1000_en;
+ wire tgtPages_T_1000_clk;
+ wire [2:0] tgtPages_T_1005_data;
+ wire [5:0] tgtPages_T_1005_addr;
+ wire tgtPages_T_1005_en;
+ wire tgtPages_T_1005_clk;
+ wire [2:0] tgtPages_T_1010_data;
+ wire [5:0] tgtPages_T_1010_addr;
+ wire tgtPages_T_1010_en;
+ wire tgtPages_T_1010_clk;
+ wire [2:0] tgtPages_T_1015_data;
+ wire [5:0] tgtPages_T_1015_addr;
+ wire tgtPages_T_1015_en;
+ wire tgtPages_T_1015_clk;
+ wire [2:0] tgtPages_T_1020_data;
+ wire [5:0] tgtPages_T_1020_addr;
+ wire tgtPages_T_1020_en;
+ wire tgtPages_T_1020_clk;
+ wire [2:0] tgtPages_T_1025_data;
+ wire [5:0] tgtPages_T_1025_addr;
+ wire tgtPages_T_1025_en;
+ wire tgtPages_T_1025_clk;
+ wire [2:0] tgtPages_T_1030_data;
+ wire [5:0] tgtPages_T_1030_addr;
+ wire tgtPages_T_1030_en;
+ wire tgtPages_T_1030_clk;
+ wire [2:0] tgtPages_T_1035_data;
+ wire [5:0] tgtPages_T_1035_addr;
+ wire tgtPages_T_1035_en;
+ wire tgtPages_T_1035_clk;
+ wire [2:0] tgtPages_T_1040_data;
+ wire [5:0] tgtPages_T_1040_addr;
+ wire tgtPages_T_1040_en;
+ wire tgtPages_T_1040_clk;
+ wire [2:0] tgtPages_T_1045_data;
+ wire [5:0] tgtPages_T_1045_addr;
+ wire tgtPages_T_1045_en;
+ wire tgtPages_T_1045_clk;
+ wire [2:0] tgtPages_T_1050_data;
+ wire [5:0] tgtPages_T_1050_addr;
+ wire tgtPages_T_1050_en;
+ wire tgtPages_T_1050_clk;
+ wire [2:0] tgtPages_T_1055_data;
+ wire [5:0] tgtPages_T_1055_addr;
+ wire tgtPages_T_1055_en;
+ wire tgtPages_T_1055_clk;
+ wire [2:0] tgtPages_T_1060_data;
+ wire [5:0] tgtPages_T_1060_addr;
+ wire tgtPages_T_1060_en;
+ wire tgtPages_T_1060_clk;
+ wire [2:0] tgtPages_T_1065_data;
+ wire [5:0] tgtPages_T_1065_addr;
+ wire tgtPages_T_1065_en;
+ wire tgtPages_T_1065_clk;
+ wire [2:0] tgtPages_T_1070_data;
+ wire [5:0] tgtPages_T_1070_addr;
+ wire tgtPages_T_1070_en;
+ wire tgtPages_T_1070_clk;
+ wire [2:0] tgtPages_T_1075_data;
+ wire [5:0] tgtPages_T_1075_addr;
+ wire tgtPages_T_1075_en;
+ wire tgtPages_T_1075_clk;
+ wire [2:0] tgtPages_T_1080_data;
+ wire [5:0] tgtPages_T_1080_addr;
+ wire tgtPages_T_1080_en;
+ wire tgtPages_T_1080_clk;
+ wire [2:0] tgtPages_T_1085_data;
+ wire [5:0] tgtPages_T_1085_addr;
+ wire tgtPages_T_1085_en;
+ wire tgtPages_T_1085_clk;
+ wire [2:0] tgtPages_T_1090_data;
+ wire [5:0] tgtPages_T_1090_addr;
+ wire tgtPages_T_1090_en;
+ wire tgtPages_T_1090_clk;
+ wire [2:0] tgtPages_T_1095_data;
+ wire [5:0] tgtPages_T_1095_addr;
+ wire tgtPages_T_1095_en;
+ wire tgtPages_T_1095_clk;
+ wire [2:0] tgtPages_T_1100_data;
+ wire [5:0] tgtPages_T_1100_addr;
+ wire tgtPages_T_1100_en;
+ wire tgtPages_T_1100_clk;
+ wire [2:0] tgtPages_T_1105_data;
+ wire [5:0] tgtPages_T_1105_addr;
+ wire tgtPages_T_1105_en;
+ wire tgtPages_T_1105_clk;
+ wire [2:0] tgtPages_T_1110_data;
+ wire [5:0] tgtPages_T_1110_addr;
+ wire tgtPages_T_1110_en;
+ wire tgtPages_T_1110_clk;
+ wire [2:0] tgtPages_T_1115_data;
+ wire [5:0] tgtPages_T_1115_addr;
+ wire tgtPages_T_1115_en;
+ wire tgtPages_T_1115_clk;
+ wire [2:0] tgtPages_T_1120_data;
+ wire [5:0] tgtPages_T_1120_addr;
+ wire tgtPages_T_1120_en;
+ wire tgtPages_T_1120_clk;
+ wire [2:0] tgtPages_T_1125_data;
+ wire [5:0] tgtPages_T_1125_addr;
+ wire tgtPages_T_1125_en;
+ wire tgtPages_T_1125_clk;
+ wire [2:0] tgtPages_T_1130_data;
+ wire [5:0] tgtPages_T_1130_addr;
+ wire tgtPages_T_1130_en;
+ wire tgtPages_T_1130_clk;
+ wire [2:0] tgtPages_T_1135_data;
+ wire [5:0] tgtPages_T_1135_addr;
+ wire tgtPages_T_1135_en;
+ wire tgtPages_T_1135_clk;
+ wire [2:0] tgtPages_T_1140_data;
+ wire [5:0] tgtPages_T_1140_addr;
+ wire tgtPages_T_1140_en;
+ wire tgtPages_T_1140_clk;
+ wire [2:0] tgtPages_T_1145_data;
+ wire [5:0] tgtPages_T_1145_addr;
+ wire tgtPages_T_1145_en;
+ wire tgtPages_T_1145_clk;
+ wire [2:0] tgtPages_T_1150_data;
+ wire [5:0] tgtPages_T_1150_addr;
+ wire tgtPages_T_1150_en;
+ wire tgtPages_T_1150_clk;
+ wire [2:0] tgtPages_T_1155_data;
+ wire [5:0] tgtPages_T_1155_addr;
+ wire tgtPages_T_1155_en;
+ wire tgtPages_T_1155_clk;
+ wire [2:0] tgtPages_T_1160_data;
+ wire [5:0] tgtPages_T_1160_addr;
+ wire tgtPages_T_1160_en;
+ wire tgtPages_T_1160_clk;
+ wire [2:0] tgtPages_T_1165_data;
+ wire [5:0] tgtPages_T_1165_addr;
+ wire tgtPages_T_1165_en;
+ wire tgtPages_T_1165_clk;
+ wire [2:0] tgtPages_T_1170_data;
+ wire [5:0] tgtPages_T_1170_addr;
+ wire tgtPages_T_1170_en;
+ wire tgtPages_T_1170_clk;
+ wire [2:0] tgtPages_T_1175_data;
+ wire [5:0] tgtPages_T_1175_addr;
+ wire tgtPages_T_1175_en;
+ wire tgtPages_T_1175_clk;
+ wire [2:0] tgtPages_T_1180_data;
+ wire [5:0] tgtPages_T_1180_addr;
+ wire tgtPages_T_1180_en;
+ wire tgtPages_T_1180_clk;
+ wire [2:0] tgtPages_T_1185_data;
+ wire [5:0] tgtPages_T_1185_addr;
+ wire tgtPages_T_1185_en;
+ wire tgtPages_T_1185_clk;
+ wire [2:0] tgtPages_T_1190_data;
+ wire [5:0] tgtPages_T_1190_addr;
+ wire tgtPages_T_1190_en;
+ wire tgtPages_T_1190_clk;
+ wire [2:0] tgtPages_T_1195_data;
+ wire [5:0] tgtPages_T_1195_addr;
+ wire tgtPages_T_1195_en;
+ wire tgtPages_T_1195_clk;
+ wire [2:0] tgtPages_T_1200_data;
+ wire [5:0] tgtPages_T_1200_addr;
+ wire tgtPages_T_1200_en;
+ wire tgtPages_T_1200_clk;
+ wire [2:0] tgtPages_T_1205_data;
+ wire [5:0] tgtPages_T_1205_addr;
+ wire tgtPages_T_1205_en;
+ wire tgtPages_T_1205_clk;
+ wire [2:0] tgtPages_T_3473_data;
+ wire [5:0] tgtPages_T_3473_addr;
+ wire tgtPages_T_3473_mask;
+ wire tgtPages_T_3473_en;
+ wire tgtPages_T_3473_clk;
+ reg [26:0] pages [0:5];
+ wire [26:0] pages_T_1665_data;
+ wire [2:0] pages_T_1665_addr;
+ wire pages_T_1665_en;
+ wire pages_T_1665_clk;
+ wire [26:0] pages_T_1668_data;
+ wire [2:0] pages_T_1668_addr;
+ wire pages_T_1668_en;
+ wire pages_T_1668_clk;
+ wire [26:0] pages_T_1671_data;
+ wire [2:0] pages_T_1671_addr;
+ wire pages_T_1671_en;
+ wire pages_T_1671_clk;
+ wire [26:0] pages_T_1674_data;
+ wire [2:0] pages_T_1674_addr;
+ wire pages_T_1674_en;
+ wire pages_T_1674_clk;
+ wire [26:0] pages_T_1677_data;
+ wire [2:0] pages_T_1677_addr;
+ wire pages_T_1677_en;
+ wire pages_T_1677_clk;
+ wire [26:0] pages_T_1680_data;
+ wire [2:0] pages_T_1680_addr;
+ wire pages_T_1680_en;
+ wire pages_T_1680_clk;
+ wire [26:0] pages_T_2326_data;
+ wire [2:0] pages_T_2326_addr;
+ wire pages_T_2326_en;
+ wire pages_T_2326_clk;
+ wire [26:0] pages_T_2329_data;
+ wire [2:0] pages_T_2329_addr;
+ wire pages_T_2329_en;
+ wire pages_T_2329_clk;
+ wire [26:0] pages_T_2332_data;
+ wire [2:0] pages_T_2332_addr;
+ wire pages_T_2332_en;
+ wire pages_T_2332_clk;
+ wire [26:0] pages_T_2335_data;
+ wire [2:0] pages_T_2335_addr;
+ wire pages_T_2335_en;
+ wire pages_T_2335_clk;
+ wire [26:0] pages_T_2338_data;
+ wire [2:0] pages_T_2338_addr;
+ wire pages_T_2338_en;
+ wire pages_T_2338_clk;
+ wire [26:0] pages_T_2341_data;
+ wire [2:0] pages_T_2341_addr;
+ wire pages_T_2341_en;
+ wire pages_T_2341_clk;
+ wire [26:0] pages_T_3777_data;
+ wire [2:0] pages_T_3777_addr;
+ wire pages_T_3777_en;
+ wire pages_T_3777_clk;
+ wire [26:0] pages_T_3779_data;
+ wire [2:0] pages_T_3779_addr;
+ wire pages_T_3779_en;
+ wire pages_T_3779_clk;
+ wire [26:0] pages_T_3781_data;
+ wire [2:0] pages_T_3781_addr;
+ wire pages_T_3781_en;
+ wire pages_T_3781_clk;
+ wire [26:0] pages_T_3783_data;
+ wire [2:0] pages_T_3783_addr;
+ wire pages_T_3783_en;
+ wire pages_T_3783_clk;
+ wire [26:0] pages_T_3785_data;
+ wire [2:0] pages_T_3785_addr;
+ wire pages_T_3785_en;
+ wire pages_T_3785_clk;
+ wire [26:0] pages_T_3787_data;
+ wire [2:0] pages_T_3787_addr;
+ wire pages_T_3787_en;
+ wire pages_T_3787_clk;
+ wire [26:0] pages_T_3491_data;
+ wire [2:0] pages_T_3491_addr;
+ wire pages_T_3491_mask;
+ wire pages_T_3491_en;
+ wire pages_T_3491_clk;
+ wire [26:0] pages_T_3495_data;
+ wire [2:0] pages_T_3495_addr;
+ wire pages_T_3495_mask;
+ wire pages_T_3495_en;
+ wire pages_T_3495_clk;
+ wire [26:0] pages_T_3499_data;
+ wire [2:0] pages_T_3499_addr;
+ wire pages_T_3499_mask;
+ wire pages_T_3499_en;
+ wire pages_T_3499_clk;
+ wire [26:0] pages_T_3507_data;
+ wire [2:0] pages_T_3507_addr;
+ wire pages_T_3507_mask;
+ wire pages_T_3507_en;
+ wire pages_T_3507_clk;
+ wire [26:0] pages_T_3511_data;
+ wire [2:0] pages_T_3511_addr;
+ wire pages_T_3511_mask;
+ wire pages_T_3511_en;
+ wire pages_T_3511_clk;
+ wire [26:0] pages_T_3515_data;
+ wire [2:0] pages_T_3515_addr;
+ wire pages_T_3515_mask;
+ wire pages_T_3515_en;
+ wire pages_T_3515_clk;
+ reg [5:0] pageValid;
+ wire [7:0] T_592;
+ wire [5:0] T_593;
+ wire [7:0] T_597;
+ wire [5:0] T_598;
+ wire [7:0] T_602;
+ wire [5:0] T_603;
+ wire [7:0] T_607;
+ wire [5:0] T_608;
+ wire [7:0] T_612;
+ wire [5:0] T_613;
+ wire [7:0] T_617;
+ wire [5:0] T_618;
+ wire [7:0] T_622;
+ wire [5:0] T_623;
+ wire [7:0] T_627;
+ wire [5:0] T_628;
+ wire [7:0] T_632;
+ wire [5:0] T_633;
+ wire [7:0] T_637;
+ wire [5:0] T_638;
+ wire [7:0] T_642;
+ wire [5:0] T_643;
+ wire [7:0] T_647;
+ wire [5:0] T_648;
+ wire [7:0] T_652;
+ wire [5:0] T_653;
+ wire [7:0] T_657;
+ wire [5:0] T_658;
+ wire [7:0] T_662;
+ wire [5:0] T_663;
+ wire [7:0] T_667;
+ wire [5:0] T_668;
+ wire [7:0] T_672;
+ wire [5:0] T_673;
+ wire [7:0] T_677;
+ wire [5:0] T_678;
+ wire [7:0] T_682;
+ wire [5:0] T_683;
+ wire [7:0] T_687;
+ wire [5:0] T_688;
+ wire [7:0] T_692;
+ wire [5:0] T_693;
+ wire [7:0] T_697;
+ wire [5:0] T_698;
+ wire [7:0] T_702;
+ wire [5:0] T_703;
+ wire [7:0] T_707;
+ wire [5:0] T_708;
+ wire [7:0] T_712;
+ wire [5:0] T_713;
+ wire [7:0] T_717;
+ wire [5:0] T_718;
+ wire [7:0] T_722;
+ wire [5:0] T_723;
+ wire [7:0] T_727;
+ wire [5:0] T_728;
+ wire [7:0] T_732;
+ wire [5:0] T_733;
+ wire [7:0] T_737;
+ wire [5:0] T_738;
+ wire [7:0] T_742;
+ wire [5:0] T_743;
+ wire [7:0] T_747;
+ wire [5:0] T_748;
+ wire [7:0] T_752;
+ wire [5:0] T_753;
+ wire [7:0] T_757;
+ wire [5:0] T_758;
+ wire [7:0] T_762;
+ wire [5:0] T_763;
+ wire [7:0] T_767;
+ wire [5:0] T_768;
+ wire [7:0] T_772;
+ wire [5:0] T_773;
+ wire [7:0] T_777;
+ wire [5:0] T_778;
+ wire [7:0] T_782;
+ wire [5:0] T_783;
+ wire [7:0] T_787;
+ wire [5:0] T_788;
+ wire [7:0] T_792;
+ wire [5:0] T_793;
+ wire [7:0] T_797;
+ wire [5:0] T_798;
+ wire [7:0] T_802;
+ wire [5:0] T_803;
+ wire [7:0] T_807;
+ wire [5:0] T_808;
+ wire [7:0] T_812;
+ wire [5:0] T_813;
+ wire [7:0] T_817;
+ wire [5:0] T_818;
+ wire [7:0] T_822;
+ wire [5:0] T_823;
+ wire [7:0] T_827;
+ wire [5:0] T_828;
+ wire [7:0] T_832;
+ wire [5:0] T_833;
+ wire [7:0] T_837;
+ wire [5:0] T_838;
+ wire [7:0] T_842;
+ wire [5:0] T_843;
+ wire [7:0] T_847;
+ wire [5:0] T_848;
+ wire [7:0] T_852;
+ wire [5:0] T_853;
+ wire [7:0] T_857;
+ wire [5:0] T_858;
+ wire [7:0] T_862;
+ wire [5:0] T_863;
+ wire [7:0] T_867;
+ wire [5:0] T_868;
+ wire [7:0] T_872;
+ wire [5:0] T_873;
+ wire [7:0] T_877;
+ wire [5:0] T_878;
+ wire [7:0] T_882;
+ wire [5:0] T_883;
+ wire [7:0] T_887;
+ wire [5:0] T_888;
+ wire [7:0] T_892;
+ wire [5:0] T_893;
+ wire [7:0] T_897;
+ wire [5:0] T_898;
+ wire [7:0] T_902;
+ wire [5:0] T_903;
+ wire [7:0] T_907;
+ wire [5:0] T_908;
+ wire [7:0] T_912;
+ wire [5:0] T_913;
+ wire [7:0] T_917;
+ wire [5:0] T_918;
+ wire [7:0] T_922;
+ wire [5:0] T_923;
+ wire [7:0] T_927;
+ wire [5:0] T_928;
+ wire [7:0] T_932;
+ wire [5:0] T_933;
+ wire [7:0] T_937;
+ wire [5:0] T_938;
+ wire [7:0] T_942;
+ wire [5:0] T_943;
+ wire [7:0] T_947;
+ wire [5:0] T_948;
+ wire [7:0] T_952;
+ wire [5:0] T_953;
+ wire [7:0] T_957;
+ wire [5:0] T_958;
+ wire [7:0] T_962;
+ wire [5:0] T_963;
+ wire [7:0] T_967;
+ wire [5:0] T_968;
+ wire [7:0] T_972;
+ wire [5:0] T_973;
+ wire [7:0] T_977;
+ wire [5:0] T_978;
+ wire [7:0] T_982;
+ wire [5:0] T_983;
+ wire [7:0] T_987;
+ wire [5:0] T_988;
+ wire [7:0] T_992;
+ wire [5:0] T_993;
+ wire [7:0] T_997;
+ wire [5:0] T_998;
+ wire [7:0] T_1002;
+ wire [5:0] T_1003;
+ wire [7:0] T_1007;
+ wire [5:0] T_1008;
+ wire [7:0] T_1012;
+ wire [5:0] T_1013;
+ wire [7:0] T_1017;
+ wire [5:0] T_1018;
+ wire [7:0] T_1022;
+ wire [5:0] T_1023;
+ wire [7:0] T_1027;
+ wire [5:0] T_1028;
+ wire [7:0] T_1032;
+ wire [5:0] T_1033;
+ wire [7:0] T_1037;
+ wire [5:0] T_1038;
+ wire [7:0] T_1042;
+ wire [5:0] T_1043;
+ wire [7:0] T_1047;
+ wire [5:0] T_1048;
+ wire [7:0] T_1052;
+ wire [5:0] T_1053;
+ wire [7:0] T_1057;
+ wire [5:0] T_1058;
+ wire [7:0] T_1062;
+ wire [5:0] T_1063;
+ wire [7:0] T_1067;
+ wire [5:0] T_1068;
+ wire [7:0] T_1072;
+ wire [5:0] T_1073;
+ wire [7:0] T_1077;
+ wire [5:0] T_1078;
+ wire [7:0] T_1082;
+ wire [5:0] T_1083;
+ wire [7:0] T_1087;
+ wire [5:0] T_1088;
+ wire [7:0] T_1092;
+ wire [5:0] T_1093;
+ wire [7:0] T_1097;
+ wire [5:0] T_1098;
+ wire [7:0] T_1102;
+ wire [5:0] T_1103;
+ wire [7:0] T_1107;
+ wire [5:0] T_1108;
+ wire [7:0] T_1112;
+ wire [5:0] T_1113;
+ wire [7:0] T_1117;
+ wire [5:0] T_1118;
+ wire [7:0] T_1122;
+ wire [5:0] T_1123;
+ wire [7:0] T_1127;
+ wire [5:0] T_1128;
+ wire [7:0] T_1132;
+ wire [5:0] T_1133;
+ wire [7:0] T_1137;
+ wire [5:0] T_1138;
+ wire [7:0] T_1142;
+ wire [5:0] T_1143;
+ wire [7:0] T_1147;
+ wire [5:0] T_1148;
+ wire [7:0] T_1152;
+ wire [5:0] T_1153;
+ wire [7:0] T_1157;
+ wire [5:0] T_1158;
+ wire [7:0] T_1162;
+ wire [5:0] T_1163;
+ wire [7:0] T_1167;
+ wire [5:0] T_1168;
+ wire [7:0] T_1172;
+ wire [5:0] T_1173;
+ wire [7:0] T_1177;
+ wire [5:0] T_1178;
+ wire [7:0] T_1182;
+ wire [5:0] T_1183;
+ wire [7:0] T_1187;
+ wire [5:0] T_1188;
+ wire [7:0] T_1192;
+ wire [5:0] T_1193;
+ wire [7:0] T_1197;
+ wire [5:0] T_1198;
+ wire [7:0] T_1202;
+ wire [5:0] T_1203;
+ wire [7:0] T_1207;
+ wire [5:0] T_1208;
+ reg useRAS_0;
+ reg useRAS_1;
+ reg useRAS_2;
+ reg useRAS_3;
+ reg useRAS_4;
+ reg useRAS_5;
+ reg useRAS_6;
+ reg useRAS_7;
+ reg useRAS_8;
+ reg useRAS_9;
+ reg useRAS_10;
+ reg useRAS_11;
+ reg useRAS_12;
+ reg useRAS_13;
+ reg useRAS_14;
+ reg useRAS_15;
+ reg useRAS_16;
+ reg useRAS_17;
+ reg useRAS_18;
+ reg useRAS_19;
+ reg useRAS_20;
+ reg useRAS_21;
+ reg useRAS_22;
+ reg useRAS_23;
+ reg useRAS_24;
+ reg useRAS_25;
+ reg useRAS_26;
+ reg useRAS_27;
+ reg useRAS_28;
+ reg useRAS_29;
+ reg useRAS_30;
+ reg useRAS_31;
+ reg useRAS_32;
+ reg useRAS_33;
+ reg useRAS_34;
+ reg useRAS_35;
+ reg useRAS_36;
+ reg useRAS_37;
+ reg useRAS_38;
+ reg useRAS_39;
+ reg useRAS_40;
+ reg useRAS_41;
+ reg useRAS_42;
+ reg useRAS_43;
+ reg useRAS_44;
+ reg useRAS_45;
+ reg useRAS_46;
+ reg useRAS_47;
+ reg useRAS_48;
+ reg useRAS_49;
+ reg useRAS_50;
+ reg useRAS_51;
+ reg useRAS_52;
+ reg useRAS_53;
+ reg useRAS_54;
+ reg useRAS_55;
+ reg useRAS_56;
+ reg useRAS_57;
+ reg useRAS_58;
+ reg useRAS_59;
+ reg useRAS_60;
+ reg useRAS_61;
+ reg isJump_0;
+ reg isJump_1;
+ reg isJump_2;
+ reg isJump_3;
+ reg isJump_4;
+ reg isJump_5;
+ reg isJump_6;
+ reg isJump_7;
+ reg isJump_8;
+ reg isJump_9;
+ reg isJump_10;
+ reg isJump_11;
+ reg isJump_12;
+ reg isJump_13;
+ reg isJump_14;
+ reg isJump_15;
+ reg isJump_16;
+ reg isJump_17;
+ reg isJump_18;
+ reg isJump_19;
+ reg isJump_20;
+ reg isJump_21;
+ reg isJump_22;
+ reg isJump_23;
+ reg isJump_24;
+ reg isJump_25;
+ reg isJump_26;
+ reg isJump_27;
+ reg isJump_28;
+ reg isJump_29;
+ reg isJump_30;
+ reg isJump_31;
+ reg isJump_32;
+ reg isJump_33;
+ reg isJump_34;
+ reg isJump_35;
+ reg isJump_36;
+ reg isJump_37;
+ reg isJump_38;
+ reg isJump_39;
+ reg isJump_40;
+ reg isJump_41;
+ reg isJump_42;
+ reg isJump_43;
+ reg isJump_44;
+ reg isJump_45;
+ reg isJump_46;
+ reg isJump_47;
+ reg isJump_48;
+ reg isJump_49;
+ reg isJump_50;
+ reg isJump_51;
+ reg isJump_52;
+ reg isJump_53;
+ reg isJump_54;
+ reg isJump_55;
+ reg isJump_56;
+ reg isJump_57;
+ reg isJump_58;
+ reg isJump_59;
+ reg isJump_60;
+ reg isJump_61;
+ reg brIdx [0:61];
+ wire brIdx_T_4212_data;
+ wire [5:0] brIdx_T_4212_addr;
+ wire brIdx_T_4212_en;
+ wire brIdx_T_4212_clk;
+ wire brIdx_T_3476_data;
+ wire [5:0] brIdx_T_3476_addr;
+ wire brIdx_T_3476_mask;
+ wire brIdx_T_3476_en;
+ wire brIdx_T_3476_clk;
+ reg T_1478;
+ reg T_1479_prediction_valid;
+ reg T_1479_prediction_bits_taken;
+ reg T_1479_prediction_bits_mask;
+ reg T_1479_prediction_bits_bridx;
+ reg [38:0] T_1479_prediction_bits_target;
+ reg [5:0] T_1479_prediction_bits_entry;
+ reg [6:0] T_1479_prediction_bits_bht_history;
+ reg [1:0] T_1479_prediction_bits_bht_value;
+ reg [38:0] T_1479_pc;
+ reg [38:0] T_1479_target;
+ reg T_1479_taken;
+ reg T_1479_isJump;
+ reg T_1479_isReturn;
+ reg [38:0] T_1479_br_pc;
+ wire r_btb_update_valid;
+ wire r_btb_update_bits_prediction_valid;
+ wire r_btb_update_bits_prediction_bits_taken;
+ wire r_btb_update_bits_prediction_bits_mask;
+ wire r_btb_update_bits_prediction_bits_bridx;
+ wire [38:0] r_btb_update_bits_prediction_bits_target;
+ wire [5:0] r_btb_update_bits_prediction_bits_entry;
+ wire [6:0] r_btb_update_bits_prediction_bits_bht_history;
+ wire [1:0] r_btb_update_bits_prediction_bits_bht_value;
+ wire [38:0] r_btb_update_bits_pc;
+ wire [38:0] r_btb_update_bits_target;
+ wire r_btb_update_bits_taken;
+ wire r_btb_update_bits_isJump;
+ wire r_btb_update_bits_isReturn;
+ wire [38:0] r_btb_update_bits_br_pc;
+ wire [26:0] T_1663;
+ wire T_1666;
+ wire T_1669;
+ wire T_1672;
+ wire T_1675;
+ wire T_1678;
+ wire T_1681;
+ wire T_1683_0;
+ wire T_1683_1;
+ wire T_1683_2;
+ wire T_1683_3;
+ wire T_1683_4;
+ wire T_1683_5;
+ wire [1:0] T_1691;
+ wire [2:0] T_1692;
+ wire [1:0] T_1693;
+ wire [2:0] T_1694;
+ wire [5:0] T_1695;
+ wire [5:0] pageHit;
+ wire [11:0] T_1697;
+ wire T_1700;
+ wire T_1703;
+ wire T_1706;
+ wire T_1709;
+ wire T_1712;
+ wire T_1715;
+ wire T_1718;
+ wire T_1721;
+ wire T_1724;
+ wire T_1727;
+ wire T_1730;
+ wire T_1733;
+ wire T_1736;
+ wire T_1739;
+ wire T_1742;
+ wire T_1745;
+ wire T_1748;
+ wire T_1751;
+ wire T_1754;
+ wire T_1757;
+ wire T_1760;
+ wire T_1763;
+ wire T_1766;
+ wire T_1769;
+ wire T_1772;
+ wire T_1775;
+ wire T_1778;
+ wire T_1781;
+ wire T_1784;
+ wire T_1787;
+ wire T_1790;
+ wire T_1793;
+ wire T_1796;
+ wire T_1799;
+ wire T_1802;
+ wire T_1805;
+ wire T_1808;
+ wire T_1811;
+ wire T_1814;
+ wire T_1817;
+ wire T_1820;
+ wire T_1823;
+ wire T_1826;
+ wire T_1829;
+ wire T_1832;
+ wire T_1835;
+ wire T_1838;
+ wire T_1841;
+ wire T_1844;
+ wire T_1847;
+ wire T_1850;
+ wire T_1853;
+ wire T_1856;
+ wire T_1859;
+ wire T_1862;
+ wire T_1865;
+ wire T_1868;
+ wire T_1871;
+ wire T_1874;
+ wire T_1877;
+ wire T_1880;
+ wire T_1883;
+ wire T_1885_0;
+ wire T_1885_1;
+ wire T_1885_2;
+ wire T_1885_3;
+ wire T_1885_4;
+ wire T_1885_5;
+ wire T_1885_6;
+ wire T_1885_7;
+ wire T_1885_8;
+ wire T_1885_9;
+ wire T_1885_10;
+ wire T_1885_11;
+ wire T_1885_12;
+ wire T_1885_13;
+ wire T_1885_14;
+ wire T_1885_15;
+ wire T_1885_16;
+ wire T_1885_17;
+ wire T_1885_18;
+ wire T_1885_19;
+ wire T_1885_20;
+ wire T_1885_21;
+ wire T_1885_22;
+ wire T_1885_23;
+ wire T_1885_24;
+ wire T_1885_25;
+ wire T_1885_26;
+ wire T_1885_27;
+ wire T_1885_28;
+ wire T_1885_29;
+ wire T_1885_30;
+ wire T_1885_31;
+ wire T_1885_32;
+ wire T_1885_33;
+ wire T_1885_34;
+ wire T_1885_35;
+ wire T_1885_36;
+ wire T_1885_37;
+ wire T_1885_38;
+ wire T_1885_39;
+ wire T_1885_40;
+ wire T_1885_41;
+ wire T_1885_42;
+ wire T_1885_43;
+ wire T_1885_44;
+ wire T_1885_45;
+ wire T_1885_46;
+ wire T_1885_47;
+ wire T_1885_48;
+ wire T_1885_49;
+ wire T_1885_50;
+ wire T_1885_51;
+ wire T_1885_52;
+ wire T_1885_53;
+ wire T_1885_54;
+ wire T_1885_55;
+ wire T_1885_56;
+ wire T_1885_57;
+ wire T_1885_58;
+ wire T_1885_59;
+ wire T_1885_60;
+ wire T_1885_61;
+ wire [1:0] T_1949;
+ wire [2:0] T_1950;
+ wire [1:0] T_1951;
+ wire [1:0] T_1952;
+ wire [3:0] T_1953;
+ wire [6:0] T_1954;
+ wire [1:0] T_1955;
+ wire [1:0] T_1956;
+ wire [3:0] T_1957;
+ wire [1:0] T_1958;
+ wire [1:0] T_1959;
+ wire [3:0] T_1960;
+ wire [7:0] T_1961;
+ wire [14:0] T_1962;
+ wire [1:0] T_1963;
+ wire [1:0] T_1964;
+ wire [3:0] T_1965;
+ wire [1:0] T_1966;
+ wire [1:0] T_1967;
+ wire [3:0] T_1968;
+ wire [7:0] T_1969;
+ wire [1:0] T_1970;
+ wire [1:0] T_1971;
+ wire [3:0] T_1972;
+ wire [1:0] T_1973;
+ wire [1:0] T_1974;
+ wire [3:0] T_1975;
+ wire [7:0] T_1976;
+ wire [15:0] T_1977;
+ wire [30:0] T_1978;
+ wire [1:0] T_1979;
+ wire [2:0] T_1980;
+ wire [1:0] T_1981;
+ wire [1:0] T_1982;
+ wire [3:0] T_1983;
+ wire [6:0] T_1984;
+ wire [1:0] T_1985;
+ wire [1:0] T_1986;
+ wire [3:0] T_1987;
+ wire [1:0] T_1988;
+ wire [1:0] T_1989;
+ wire [3:0] T_1990;
+ wire [7:0] T_1991;
+ wire [14:0] T_1992;
+ wire [1:0] T_1993;
+ wire [1:0] T_1994;
+ wire [3:0] T_1995;
+ wire [1:0] T_1996;
+ wire [1:0] T_1997;
+ wire [3:0] T_1998;
+ wire [7:0] T_1999;
+ wire [1:0] T_2000;
+ wire [1:0] T_2001;
+ wire [3:0] T_2002;
+ wire [1:0] T_2003;
+ wire [1:0] T_2004;
+ wire [3:0] T_2005;
+ wire [7:0] T_2006;
+ wire [15:0] T_2007;
+ wire [30:0] T_2008;
+ wire [61:0] T_2009;
+ wire [5:0] T_2010;
+ wire [5:0] T_2011;
+ wire [5:0] T_2012;
+ wire [5:0] T_2013;
+ wire [5:0] T_2014;
+ wire [5:0] T_2015;
+ wire [5:0] T_2016;
+ wire [5:0] T_2017;
+ wire [5:0] T_2018;
+ wire [5:0] T_2019;
+ wire [5:0] T_2020;
+ wire [5:0] T_2021;
+ wire [5:0] T_2022;
+ wire [5:0] T_2023;
+ wire [5:0] T_2024;
+ wire [5:0] T_2025;
+ wire [5:0] T_2026;
+ wire [5:0] T_2027;
+ wire [5:0] T_2028;
+ wire [5:0] T_2029;
+ wire [5:0] T_2030;
+ wire [5:0] T_2031;
+ wire [5:0] T_2032;
+ wire [5:0] T_2033;
+ wire [5:0] T_2034;
+ wire [5:0] T_2035;
+ wire [5:0] T_2036;
+ wire [5:0] T_2037;
+ wire [5:0] T_2038;
+ wire [5:0] T_2039;
+ wire [5:0] T_2040;
+ wire [5:0] T_2041;
+ wire [5:0] T_2042;
+ wire [5:0] T_2043;
+ wire [5:0] T_2044;
+ wire [5:0] T_2045;
+ wire [5:0] T_2046;
+ wire [5:0] T_2047;
+ wire [5:0] T_2048;
+ wire [5:0] T_2049;
+ wire [5:0] T_2050;
+ wire [5:0] T_2051;
+ wire [5:0] T_2052;
+ wire [5:0] T_2053;
+ wire [5:0] T_2054;
+ wire [5:0] T_2055;
+ wire [5:0] T_2056;
+ wire [5:0] T_2057;
+ wire [5:0] T_2058;
+ wire [5:0] T_2059;
+ wire [5:0] T_2060;
+ wire [5:0] T_2061;
+ wire [5:0] T_2062;
+ wire [5:0] T_2063;
+ wire [5:0] T_2064;
+ wire [5:0] T_2065;
+ wire [5:0] T_2066;
+ wire [5:0] T_2067;
+ wire [5:0] T_2068;
+ wire [5:0] T_2069;
+ wire [5:0] T_2070;
+ wire [5:0] T_2071;
+ wire T_2073;
+ wire T_2075;
+ wire T_2077;
+ wire T_2079;
+ wire T_2081;
+ wire T_2083;
+ wire T_2085;
+ wire T_2087;
+ wire T_2089;
+ wire T_2091;
+ wire T_2093;
+ wire T_2095;
+ wire T_2097;
+ wire T_2099;
+ wire T_2101;
+ wire T_2103;
+ wire T_2105;
+ wire T_2107;
+ wire T_2109;
+ wire T_2111;
+ wire T_2113;
+ wire T_2115;
+ wire T_2117;
+ wire T_2119;
+ wire T_2121;
+ wire T_2123;
+ wire T_2125;
+ wire T_2127;
+ wire T_2129;
+ wire T_2131;
+ wire T_2133;
+ wire T_2135;
+ wire T_2137;
+ wire T_2139;
+ wire T_2141;
+ wire T_2143;
+ wire T_2145;
+ wire T_2147;
+ wire T_2149;
+ wire T_2151;
+ wire T_2153;
+ wire T_2155;
+ wire T_2157;
+ wire T_2159;
+ wire T_2161;
+ wire T_2163;
+ wire T_2165;
+ wire T_2167;
+ wire T_2169;
+ wire T_2171;
+ wire T_2173;
+ wire T_2175;
+ wire T_2177;
+ wire T_2179;
+ wire T_2181;
+ wire T_2183;
+ wire T_2185;
+ wire T_2187;
+ wire T_2189;
+ wire T_2191;
+ wire T_2193;
+ wire T_2195;
+ wire T_2197_0;
+ wire T_2197_1;
+ wire T_2197_2;
+ wire T_2197_3;
+ wire T_2197_4;
+ wire T_2197_5;
+ wire T_2197_6;
+ wire T_2197_7;
+ wire T_2197_8;
+ wire T_2197_9;
+ wire T_2197_10;
+ wire T_2197_11;
+ wire T_2197_12;
+ wire T_2197_13;
+ wire T_2197_14;
+ wire T_2197_15;
+ wire T_2197_16;
+ wire T_2197_17;
+ wire T_2197_18;
+ wire T_2197_19;
+ wire T_2197_20;
+ wire T_2197_21;
+ wire T_2197_22;
+ wire T_2197_23;
+ wire T_2197_24;
+ wire T_2197_25;
+ wire T_2197_26;
+ wire T_2197_27;
+ wire T_2197_28;
+ wire T_2197_29;
+ wire T_2197_30;
+ wire T_2197_31;
+ wire T_2197_32;
+ wire T_2197_33;
+ wire T_2197_34;
+ wire T_2197_35;
+ wire T_2197_36;
+ wire T_2197_37;
+ wire T_2197_38;
+ wire T_2197_39;
+ wire T_2197_40;
+ wire T_2197_41;
+ wire T_2197_42;
+ wire T_2197_43;
+ wire T_2197_44;
+ wire T_2197_45;
+ wire T_2197_46;
+ wire T_2197_47;
+ wire T_2197_48;
+ wire T_2197_49;
+ wire T_2197_50;
+ wire T_2197_51;
+ wire T_2197_52;
+ wire T_2197_53;
+ wire T_2197_54;
+ wire T_2197_55;
+ wire T_2197_56;
+ wire T_2197_57;
+ wire T_2197_58;
+ wire T_2197_59;
+ wire T_2197_60;
+ wire T_2197_61;
+ wire [1:0] T_2261;
+ wire [2:0] T_2262;
+ wire [1:0] T_2263;
+ wire [1:0] T_2264;
+ wire [3:0] T_2265;
+ wire [6:0] T_2266;
+ wire [1:0] T_2267;
+ wire [1:0] T_2268;
+ wire [3:0] T_2269;
+ wire [1:0] T_2270;
+ wire [1:0] T_2271;
+ wire [3:0] T_2272;
+ wire [7:0] T_2273;
+ wire [14:0] T_2274;
+ wire [1:0] T_2275;
+ wire [1:0] T_2276;
+ wire [3:0] T_2277;
+ wire [1:0] T_2278;
+ wire [1:0] T_2279;
+ wire [3:0] T_2280;
+ wire [7:0] T_2281;
+ wire [1:0] T_2282;
+ wire [1:0] T_2283;
+ wire [3:0] T_2284;
+ wire [1:0] T_2285;
+ wire [1:0] T_2286;
+ wire [3:0] T_2287;
+ wire [7:0] T_2288;
+ wire [15:0] T_2289;
+ wire [30:0] T_2290;
+ wire [1:0] T_2291;
+ wire [2:0] T_2292;
+ wire [1:0] T_2293;
+ wire [1:0] T_2294;
+ wire [3:0] T_2295;
+ wire [6:0] T_2296;
+ wire [1:0] T_2297;
+ wire [1:0] T_2298;
+ wire [3:0] T_2299;
+ wire [1:0] T_2300;
+ wire [1:0] T_2301;
+ wire [3:0] T_2302;
+ wire [7:0] T_2303;
+ wire [14:0] T_2304;
+ wire [1:0] T_2305;
+ wire [1:0] T_2306;
+ wire [3:0] T_2307;
+ wire [1:0] T_2308;
+ wire [1:0] T_2309;
+ wire [3:0] T_2310;
+ wire [7:0] T_2311;
+ wire [1:0] T_2312;
+ wire [1:0] T_2313;
+ wire [3:0] T_2314;
+ wire [1:0] T_2315;
+ wire [1:0] T_2316;
+ wire [3:0] T_2317;
+ wire [7:0] T_2318;
+ wire [15:0] T_2319;
+ wire [30:0] T_2320;
+ wire [61:0] T_2321;
+ wire [61:0] T_2322;
+ wire [61:0] hits;
+ wire [26:0] T_2324;
+ wire T_2327;
+ wire T_2330;
+ wire T_2333;
+ wire T_2336;
+ wire T_2339;
+ wire T_2342;
+ wire T_2344_0;
+ wire T_2344_1;
+ wire T_2344_2;
+ wire T_2344_3;
+ wire T_2344_4;
+ wire T_2344_5;
+ wire [1:0] T_2352;
+ wire [2:0] T_2353;
+ wire [1:0] T_2354;
+ wire [2:0] T_2355;
+ wire [5:0] T_2356;
+ wire [5:0] updatePageHit;
+ wire [11:0] T_2358;
+ wire T_2361;
+ wire T_2364;
+ wire T_2367;
+ wire T_2370;
+ wire T_2373;
+ wire T_2376;
+ wire T_2379;
+ wire T_2382;
+ wire T_2385;
+ wire T_2388;
+ wire T_2391;
+ wire T_2394;
+ wire T_2397;
+ wire T_2400;
+ wire T_2403;
+ wire T_2406;
+ wire T_2409;
+ wire T_2412;
+ wire T_2415;
+ wire T_2418;
+ wire T_2421;
+ wire T_2424;
+ wire T_2427;
+ wire T_2430;
+ wire T_2433;
+ wire T_2436;
+ wire T_2439;
+ wire T_2442;
+ wire T_2445;
+ wire T_2448;
+ wire T_2451;
+ wire T_2454;
+ wire T_2457;
+ wire T_2460;
+ wire T_2463;
+ wire T_2466;
+ wire T_2469;
+ wire T_2472;
+ wire T_2475;
+ wire T_2478;
+ wire T_2481;
+ wire T_2484;
+ wire T_2487;
+ wire T_2490;
+ wire T_2493;
+ wire T_2496;
+ wire T_2499;
+ wire T_2502;
+ wire T_2505;
+ wire T_2508;
+ wire T_2511;
+ wire T_2514;
+ wire T_2517;
+ wire T_2520;
+ wire T_2523;
+ wire T_2526;
+ wire T_2529;
+ wire T_2532;
+ wire T_2535;
+ wire T_2538;
+ wire T_2541;
+ wire T_2544;
+ wire T_2546_0;
+ wire T_2546_1;
+ wire T_2546_2;
+ wire T_2546_3;
+ wire T_2546_4;
+ wire T_2546_5;
+ wire T_2546_6;
+ wire T_2546_7;
+ wire T_2546_8;
+ wire T_2546_9;
+ wire T_2546_10;
+ wire T_2546_11;
+ wire T_2546_12;
+ wire T_2546_13;
+ wire T_2546_14;
+ wire T_2546_15;
+ wire T_2546_16;
+ wire T_2546_17;
+ wire T_2546_18;
+ wire T_2546_19;
+ wire T_2546_20;
+ wire T_2546_21;
+ wire T_2546_22;
+ wire T_2546_23;
+ wire T_2546_24;
+ wire T_2546_25;
+ wire T_2546_26;
+ wire T_2546_27;
+ wire T_2546_28;
+ wire T_2546_29;
+ wire T_2546_30;
+ wire T_2546_31;
+ wire T_2546_32;
+ wire T_2546_33;
+ wire T_2546_34;
+ wire T_2546_35;
+ wire T_2546_36;
+ wire T_2546_37;
+ wire T_2546_38;
+ wire T_2546_39;
+ wire T_2546_40;
+ wire T_2546_41;
+ wire T_2546_42;
+ wire T_2546_43;
+ wire T_2546_44;
+ wire T_2546_45;
+ wire T_2546_46;
+ wire T_2546_47;
+ wire T_2546_48;
+ wire T_2546_49;
+ wire T_2546_50;
+ wire T_2546_51;
+ wire T_2546_52;
+ wire T_2546_53;
+ wire T_2546_54;
+ wire T_2546_55;
+ wire T_2546_56;
+ wire T_2546_57;
+ wire T_2546_58;
+ wire T_2546_59;
+ wire T_2546_60;
+ wire T_2546_61;
+ wire [1:0] T_2610;
+ wire [2:0] T_2611;
+ wire [1:0] T_2612;
+ wire [1:0] T_2613;
+ wire [3:0] T_2614;
+ wire [6:0] T_2615;
+ wire [1:0] T_2616;
+ wire [1:0] T_2617;
+ wire [3:0] T_2618;
+ wire [1:0] T_2619;
+ wire [1:0] T_2620;
+ wire [3:0] T_2621;
+ wire [7:0] T_2622;
+ wire [14:0] T_2623;
+ wire [1:0] T_2624;
+ wire [1:0] T_2625;
+ wire [3:0] T_2626;
+ wire [1:0] T_2627;
+ wire [1:0] T_2628;
+ wire [3:0] T_2629;
+ wire [7:0] T_2630;
+ wire [1:0] T_2631;
+ wire [1:0] T_2632;
+ wire [3:0] T_2633;
+ wire [1:0] T_2634;
+ wire [1:0] T_2635;
+ wire [3:0] T_2636;
+ wire [7:0] T_2637;
+ wire [15:0] T_2638;
+ wire [30:0] T_2639;
+ wire [1:0] T_2640;
+ wire [2:0] T_2641;
+ wire [1:0] T_2642;
+ wire [1:0] T_2643;
+ wire [3:0] T_2644;
+ wire [6:0] T_2645;
+ wire [1:0] T_2646;
+ wire [1:0] T_2647;
+ wire [3:0] T_2648;
+ wire [1:0] T_2649;
+ wire [1:0] T_2650;
+ wire [3:0] T_2651;
+ wire [7:0] T_2652;
+ wire [14:0] T_2653;
+ wire [1:0] T_2654;
+ wire [1:0] T_2655;
+ wire [3:0] T_2656;
+ wire [1:0] T_2657;
+ wire [1:0] T_2658;
+ wire [3:0] T_2659;
+ wire [7:0] T_2660;
+ wire [1:0] T_2661;
+ wire [1:0] T_2662;
+ wire [3:0] T_2663;
+ wire [1:0] T_2664;
+ wire [1:0] T_2665;
+ wire [3:0] T_2666;
+ wire [7:0] T_2667;
+ wire [15:0] T_2668;
+ wire [30:0] T_2669;
+ wire [61:0] T_2670;
+ wire [5:0] T_2671;
+ wire [5:0] T_2672;
+ wire [5:0] T_2673;
+ wire [5:0] T_2674;
+ wire [5:0] T_2675;
+ wire [5:0] T_2676;
+ wire [5:0] T_2677;
+ wire [5:0] T_2678;
+ wire [5:0] T_2679;
+ wire [5:0] T_2680;
+ wire [5:0] T_2681;
+ wire [5:0] T_2682;
+ wire [5:0] T_2683;
+ wire [5:0] T_2684;
+ wire [5:0] T_2685;
+ wire [5:0] T_2686;
+ wire [5:0] T_2687;
+ wire [5:0] T_2688;
+ wire [5:0] T_2689;
+ wire [5:0] T_2690;
+ wire [5:0] T_2691;
+ wire [5:0] T_2692;
+ wire [5:0] T_2693;
+ wire [5:0] T_2694;
+ wire [5:0] T_2695;
+ wire [5:0] T_2696;
+ wire [5:0] T_2697;
+ wire [5:0] T_2698;
+ wire [5:0] T_2699;
+ wire [5:0] T_2700;
+ wire [5:0] T_2701;
+ wire [5:0] T_2702;
+ wire [5:0] T_2703;
+ wire [5:0] T_2704;
+ wire [5:0] T_2705;
+ wire [5:0] T_2706;
+ wire [5:0] T_2707;
+ wire [5:0] T_2708;
+ wire [5:0] T_2709;
+ wire [5:0] T_2710;
+ wire [5:0] T_2711;
+ wire [5:0] T_2712;
+ wire [5:0] T_2713;
+ wire [5:0] T_2714;
+ wire [5:0] T_2715;
+ wire [5:0] T_2716;
+ wire [5:0] T_2717;
+ wire [5:0] T_2718;
+ wire [5:0] T_2719;
+ wire [5:0] T_2720;
+ wire [5:0] T_2721;
+ wire [5:0] T_2722;
+ wire [5:0] T_2723;
+ wire [5:0] T_2724;
+ wire [5:0] T_2725;
+ wire [5:0] T_2726;
+ wire [5:0] T_2727;
+ wire [5:0] T_2728;
+ wire [5:0] T_2729;
+ wire [5:0] T_2730;
+ wire [5:0] T_2731;
+ wire [5:0] T_2732;
+ wire T_2734;
+ wire T_2736;
+ wire T_2738;
+ wire T_2740;
+ wire T_2742;
+ wire T_2744;
+ wire T_2746;
+ wire T_2748;
+ wire T_2750;
+ wire T_2752;
+ wire T_2754;
+ wire T_2756;
+ wire T_2758;
+ wire T_2760;
+ wire T_2762;
+ wire T_2764;
+ wire T_2766;
+ wire T_2768;
+ wire T_2770;
+ wire T_2772;
+ wire T_2774;
+ wire T_2776;
+ wire T_2778;
+ wire T_2780;
+ wire T_2782;
+ wire T_2784;
+ wire T_2786;
+ wire T_2788;
+ wire T_2790;
+ wire T_2792;
+ wire T_2794;
+ wire T_2796;
+ wire T_2798;
+ wire T_2800;
+ wire T_2802;
+ wire T_2804;
+ wire T_2806;
+ wire T_2808;
+ wire T_2810;
+ wire T_2812;
+ wire T_2814;
+ wire T_2816;
+ wire T_2818;
+ wire T_2820;
+ wire T_2822;
+ wire T_2824;
+ wire T_2826;
+ wire T_2828;
+ wire T_2830;
+ wire T_2832;
+ wire T_2834;
+ wire T_2836;
+ wire T_2838;
+ wire T_2840;
+ wire T_2842;
+ wire T_2844;
+ wire T_2846;
+ wire T_2848;
+ wire T_2850;
+ wire T_2852;
+ wire T_2854;
+ wire T_2856;
+ wire T_2858_0;
+ wire T_2858_1;
+ wire T_2858_2;
+ wire T_2858_3;
+ wire T_2858_4;
+ wire T_2858_5;
+ wire T_2858_6;
+ wire T_2858_7;
+ wire T_2858_8;
+ wire T_2858_9;
+ wire T_2858_10;
+ wire T_2858_11;
+ wire T_2858_12;
+ wire T_2858_13;
+ wire T_2858_14;
+ wire T_2858_15;
+ wire T_2858_16;
+ wire T_2858_17;
+ wire T_2858_18;
+ wire T_2858_19;
+ wire T_2858_20;
+ wire T_2858_21;
+ wire T_2858_22;
+ wire T_2858_23;
+ wire T_2858_24;
+ wire T_2858_25;
+ wire T_2858_26;
+ wire T_2858_27;
+ wire T_2858_28;
+ wire T_2858_29;
+ wire T_2858_30;
+ wire T_2858_31;
+ wire T_2858_32;
+ wire T_2858_33;
+ wire T_2858_34;
+ wire T_2858_35;
+ wire T_2858_36;
+ wire T_2858_37;
+ wire T_2858_38;
+ wire T_2858_39;
+ wire T_2858_40;
+ wire T_2858_41;
+ wire T_2858_42;
+ wire T_2858_43;
+ wire T_2858_44;
+ wire T_2858_45;
+ wire T_2858_46;
+ wire T_2858_47;
+ wire T_2858_48;
+ wire T_2858_49;
+ wire T_2858_50;
+ wire T_2858_51;
+ wire T_2858_52;
+ wire T_2858_53;
+ wire T_2858_54;
+ wire T_2858_55;
+ wire T_2858_56;
+ wire T_2858_57;
+ wire T_2858_58;
+ wire T_2858_59;
+ wire T_2858_60;
+ wire T_2858_61;
+ wire [1:0] T_2922;
+ wire [2:0] T_2923;
+ wire [1:0] T_2924;
+ wire [1:0] T_2925;
+ wire [3:0] T_2926;
+ wire [6:0] T_2927;
+ wire [1:0] T_2928;
+ wire [1:0] T_2929;
+ wire [3:0] T_2930;
+ wire [1:0] T_2931;
+ wire [1:0] T_2932;
+ wire [3:0] T_2933;
+ wire [7:0] T_2934;
+ wire [14:0] T_2935;
+ wire [1:0] T_2936;
+ wire [1:0] T_2937;
+ wire [3:0] T_2938;
+ wire [1:0] T_2939;
+ wire [1:0] T_2940;
+ wire [3:0] T_2941;
+ wire [7:0] T_2942;
+ wire [1:0] T_2943;
+ wire [1:0] T_2944;
+ wire [3:0] T_2945;
+ wire [1:0] T_2946;
+ wire [1:0] T_2947;
+ wire [3:0] T_2948;
+ wire [7:0] T_2949;
+ wire [15:0] T_2950;
+ wire [30:0] T_2951;
+ wire [1:0] T_2952;
+ wire [2:0] T_2953;
+ wire [1:0] T_2954;
+ wire [1:0] T_2955;
+ wire [3:0] T_2956;
+ wire [6:0] T_2957;
+ wire [1:0] T_2958;
+ wire [1:0] T_2959;
+ wire [3:0] T_2960;
+ wire [1:0] T_2961;
+ wire [1:0] T_2962;
+ wire [3:0] T_2963;
+ wire [7:0] T_2964;
+ wire [14:0] T_2965;
+ wire [1:0] T_2966;
+ wire [1:0] T_2967;
+ wire [3:0] T_2968;
+ wire [1:0] T_2969;
+ wire [1:0] T_2970;
+ wire [3:0] T_2971;
+ wire [7:0] T_2972;
+ wire [1:0] T_2973;
+ wire [1:0] T_2974;
+ wire [3:0] T_2975;
+ wire [1:0] T_2976;
+ wire [1:0] T_2977;
+ wire [3:0] T_2978;
+ wire [7:0] T_2979;
+ wire [15:0] T_2980;
+ wire [30:0] T_2981;
+ wire [61:0] T_2982;
+ wire [61:0] T_2983;
+ wire [61:0] updateHits;
+ reg [15:0] T_2986;
+ wire T_2987;
+ wire T_2988;
+ wire T_2989;
+ wire T_2990;
+ wire T_2991;
+ wire T_2992;
+ wire T_2993;
+ wire [14:0] T_2994;
+ wire [15:0] T_2995;
+ wire T_2997;
+ wire T_2998;
+ reg [5:0] nextRepl;
+ wire T_3002;
+ wire T_3004;
+ wire [6:0] T_3007;
+ wire [5:0] T_3008;
+ wire [5:0] T_3009;
+ wire T_3010;
+ wire useUpdatePageHit;
+ wire doIdxPageRepl;
+ wire [5:0] idxPageRepl;
+ wire [5:0] idxPageUpdateOH;
+ wire [1:0] T_3018;
+ wire [3:0] T_3019;
+ wire T_3021;
+ wire [3:0] T_3022;
+ wire [1:0] T_3023;
+ wire [1:0] T_3024;
+ wire T_3026;
+ wire [1:0] T_3027;
+ wire T_3028;
+ wire [1:0] T_3029;
+ wire [2:0] idxPageUpdate;
+ wire [5:0] idxPageReplEn;
+ wire [26:0] T_3033;
+ wire [26:0] T_3034;
+ wire samePage;
+ wire [5:0] T_3036;
+ wire [5:0] T_3037;
+ wire usePageHit;
+ wire T_3041;
+ wire T_3043;
+ wire doTgtPageRepl;
+ wire [4:0] T_3045;
+ wire [5:0] T_3046;
+ wire T_3047;
+ wire [5:0] T_3048;
+ wire [5:0] tgtPageRepl;
+ wire [5:0] T_3050;
+ wire [1:0] T_3051;
+ wire [3:0] T_3052;
+ wire T_3054;
+ wire [3:0] T_3055;
+ wire [1:0] T_3056;
+ wire [1:0] T_3057;
+ wire T_3059;
+ wire [1:0] T_3060;
+ wire T_3061;
+ wire [1:0] T_3062;
+ wire [2:0] tgtPageUpdate;
+ wire [5:0] tgtPageReplEn;
+ wire doPageRepl;
+ wire [5:0] pageReplEn;
+ wire T_3068;
+ reg [2:0] T_3070;
+ wire T_3072;
+ wire T_3074;
+ wire [3:0] T_3077;
+ wire [2:0] T_3078;
+ wire [2:0] T_3079;
+ wire T_3080;
+ wire [7:0] T_3082;
+ wire T_3083;
+ wire T_3085;
+ wire T_3087;
+ wire T_3089;
+ wire [5:0] T_3090;
+ wire [5:0] T_3091;
+ wire [5:0] T_3092;
+ wire T_3094;
+ wire [5:0] T_3095;
+ wire [5:0] T_3096;
+ wire T_3098;
+ wire [5:0] T_3099;
+ wire [5:0] T_3100;
+ wire T_3102;
+ wire [5:0] T_3103;
+ wire [5:0] T_3104;
+ wire T_3106;
+ wire [5:0] T_3107;
+ wire [5:0] T_3108;
+ wire T_3110;
+ wire [5:0] T_3111;
+ wire [5:0] T_3112;
+ wire T_3114;
+ wire [5:0] T_3115;
+ wire [5:0] T_3116;
+ wire T_3118;
+ wire [5:0] T_3119;
+ wire [5:0] T_3120;
+ wire T_3122;
+ wire [5:0] T_3123;
+ wire [5:0] T_3124;
+ wire T_3126;
+ wire [5:0] T_3127;
+ wire [5:0] T_3128;
+ wire T_3130;
+ wire [5:0] T_3131;
+ wire [5:0] T_3132;
+ wire T_3134;
+ wire [5:0] T_3135;
+ wire [5:0] T_3136;
+ wire T_3138;
+ wire [5:0] T_3139;
+ wire [5:0] T_3140;
+ wire T_3142;
+ wire [5:0] T_3143;
+ wire [5:0] T_3144;
+ wire T_3146;
+ wire [5:0] T_3147;
+ wire [5:0] T_3148;
+ wire T_3150;
+ wire [5:0] T_3151;
+ wire [5:0] T_3152;
+ wire T_3154;
+ wire [5:0] T_3155;
+ wire [5:0] T_3156;
+ wire T_3158;
+ wire [5:0] T_3159;
+ wire [5:0] T_3160;
+ wire T_3162;
+ wire [5:0] T_3163;
+ wire [5:0] T_3164;
+ wire T_3166;
+ wire [5:0] T_3167;
+ wire [5:0] T_3168;
+ wire T_3170;
+ wire [5:0] T_3171;
+ wire [5:0] T_3172;
+ wire T_3174;
+ wire [5:0] T_3175;
+ wire [5:0] T_3176;
+ wire T_3178;
+ wire [5:0] T_3179;
+ wire [5:0] T_3180;
+ wire T_3182;
+ wire [5:0] T_3183;
+ wire [5:0] T_3184;
+ wire T_3186;
+ wire [5:0] T_3187;
+ wire [5:0] T_3188;
+ wire T_3190;
+ wire [5:0] T_3191;
+ wire [5:0] T_3192;
+ wire T_3194;
+ wire [5:0] T_3195;
+ wire [5:0] T_3196;
+ wire T_3198;
+ wire [5:0] T_3199;
+ wire [5:0] T_3200;
+ wire T_3202;
+ wire [5:0] T_3203;
+ wire [5:0] T_3204;
+ wire T_3206;
+ wire [5:0] T_3207;
+ wire [5:0] T_3208;
+ wire T_3210;
+ wire [5:0] T_3211;
+ wire [5:0] T_3212;
+ wire T_3214;
+ wire [5:0] T_3215;
+ wire [5:0] T_3216;
+ wire T_3218;
+ wire [5:0] T_3219;
+ wire [5:0] T_3220;
+ wire T_3222;
+ wire [5:0] T_3223;
+ wire [5:0] T_3224;
+ wire T_3226;
+ wire [5:0] T_3227;
+ wire [5:0] T_3228;
+ wire T_3230;
+ wire [5:0] T_3231;
+ wire [5:0] T_3232;
+ wire T_3234;
+ wire [5:0] T_3235;
+ wire [5:0] T_3236;
+ wire T_3238;
+ wire [5:0] T_3239;
+ wire [5:0] T_3240;
+ wire T_3242;
+ wire [5:0] T_3243;
+ wire [5:0] T_3244;
+ wire T_3246;
+ wire [5:0] T_3247;
+ wire [5:0] T_3248;
+ wire T_3250;
+ wire [5:0] T_3251;
+ wire [5:0] T_3252;
+ wire T_3254;
+ wire [5:0] T_3255;
+ wire [5:0] T_3256;
+ wire T_3258;
+ wire [5:0] T_3259;
+ wire [5:0] T_3260;
+ wire T_3262;
+ wire [5:0] T_3263;
+ wire [5:0] T_3264;
+ wire T_3266;
+ wire [5:0] T_3267;
+ wire [5:0] T_3268;
+ wire T_3270;
+ wire [5:0] T_3271;
+ wire [5:0] T_3272;
+ wire T_3274;
+ wire [5:0] T_3275;
+ wire [5:0] T_3276;
+ wire T_3278;
+ wire [5:0] T_3279;
+ wire [5:0] T_3280;
+ wire T_3282;
+ wire [5:0] T_3283;
+ wire [5:0] T_3284;
+ wire T_3286;
+ wire [5:0] T_3287;
+ wire [5:0] T_3288;
+ wire T_3290;
+ wire [5:0] T_3291;
+ wire [5:0] T_3292;
+ wire T_3294;
+ wire [5:0] T_3295;
+ wire [5:0] T_3296;
+ wire T_3298;
+ wire [5:0] T_3299;
+ wire [5:0] T_3300;
+ wire T_3302;
+ wire [5:0] T_3303;
+ wire [5:0] T_3304;
+ wire T_3306;
+ wire [5:0] T_3307;
+ wire [5:0] T_3308;
+ wire T_3310;
+ wire [5:0] T_3311;
+ wire [5:0] T_3312;
+ wire T_3314;
+ wire [5:0] T_3315;
+ wire [5:0] T_3316;
+ wire T_3318;
+ wire [5:0] T_3319;
+ wire [5:0] T_3320;
+ wire T_3322;
+ wire [5:0] T_3323;
+ wire [5:0] T_3324;
+ wire T_3326;
+ wire [5:0] T_3327;
+ wire [5:0] T_3328;
+ wire T_3330;
+ wire [5:0] T_3331;
+ wire [5:0] T_3332;
+ wire T_3334;
+ wire [5:0] T_3335;
+ wire [5:0] T_3336;
+ wire T_3338;
+ wire T_3340_0;
+ wire T_3340_1;
+ wire T_3340_2;
+ wire T_3340_3;
+ wire T_3340_4;
+ wire T_3340_5;
+ wire T_3340_6;
+ wire T_3340_7;
+ wire T_3340_8;
+ wire T_3340_9;
+ wire T_3340_10;
+ wire T_3340_11;
+ wire T_3340_12;
+ wire T_3340_13;
+ wire T_3340_14;
+ wire T_3340_15;
+ wire T_3340_16;
+ wire T_3340_17;
+ wire T_3340_18;
+ wire T_3340_19;
+ wire T_3340_20;
+ wire T_3340_21;
+ wire T_3340_22;
+ wire T_3340_23;
+ wire T_3340_24;
+ wire T_3340_25;
+ wire T_3340_26;
+ wire T_3340_27;
+ wire T_3340_28;
+ wire T_3340_29;
+ wire T_3340_30;
+ wire T_3340_31;
+ wire T_3340_32;
+ wire T_3340_33;
+ wire T_3340_34;
+ wire T_3340_35;
+ wire T_3340_36;
+ wire T_3340_37;
+ wire T_3340_38;
+ wire T_3340_39;
+ wire T_3340_40;
+ wire T_3340_41;
+ wire T_3340_42;
+ wire T_3340_43;
+ wire T_3340_44;
+ wire T_3340_45;
+ wire T_3340_46;
+ wire T_3340_47;
+ wire T_3340_48;
+ wire T_3340_49;
+ wire T_3340_50;
+ wire T_3340_51;
+ wire T_3340_52;
+ wire T_3340_53;
+ wire T_3340_54;
+ wire T_3340_55;
+ wire T_3340_56;
+ wire T_3340_57;
+ wire T_3340_58;
+ wire T_3340_59;
+ wire T_3340_60;
+ wire T_3340_61;
+ wire [1:0] T_3404;
+ wire [2:0] T_3405;
+ wire [1:0] T_3406;
+ wire [1:0] T_3407;
+ wire [3:0] T_3408;
+ wire [6:0] T_3409;
+ wire [1:0] T_3410;
+ wire [1:0] T_3411;
+ wire [3:0] T_3412;
+ wire [1:0] T_3413;
+ wire [1:0] T_3414;
+ wire [3:0] T_3415;
+ wire [7:0] T_3416;
+ wire [14:0] T_3417;
+ wire [1:0] T_3418;
+ wire [1:0] T_3419;
+ wire [3:0] T_3420;
+ wire [1:0] T_3421;
+ wire [1:0] T_3422;
+ wire [3:0] T_3423;
+ wire [7:0] T_3424;
+ wire [1:0] T_3425;
+ wire [1:0] T_3426;
+ wire [3:0] T_3427;
+ wire [1:0] T_3428;
+ wire [1:0] T_3429;
+ wire [3:0] T_3430;
+ wire [7:0] T_3431;
+ wire [15:0] T_3432;
+ wire [30:0] T_3433;
+ wire [1:0] T_3434;
+ wire [2:0] T_3435;
+ wire [1:0] T_3436;
+ wire [1:0] T_3437;
+ wire [3:0] T_3438;
+ wire [6:0] T_3439;
+ wire [1:0] T_3440;
+ wire [1:0] T_3441;
+ wire [3:0] T_3442;
+ wire [1:0] T_3443;
+ wire [1:0] T_3444;
+ wire [3:0] T_3445;
+ wire [7:0] T_3446;
+ wire [14:0] T_3447;
+ wire [1:0] T_3448;
+ wire [1:0] T_3449;
+ wire [3:0] T_3450;
+ wire [1:0] T_3451;
+ wire [1:0] T_3452;
+ wire [3:0] T_3453;
+ wire [7:0] T_3454;
+ wire [1:0] T_3455;
+ wire [1:0] T_3456;
+ wire [3:0] T_3457;
+ wire [1:0] T_3458;
+ wire [1:0] T_3459;
+ wire [3:0] T_3460;
+ wire [7:0] T_3461;
+ wire [15:0] T_3462;
+ wire [30:0] T_3463;
+ wire [61:0] T_3464;
+ wire [63:0] T_3466;
+ wire [61:0] T_3467;
+ wire [61:0] T_3468;
+ wire [63:0] T_3469;
+ wire GEN_0;
+ wire GEN_1;
+ wire [3:0] T_3479;
+ wire [5:0] T_3480;
+ wire [5:0] T_3481;
+ wire T_3483;
+ wire T_3484;
+ wire [26:0] T_3485;
+ wire [26:0] T_3486;
+ wire [26:0] T_3487;
+ wire T_3488;
+ wire T_3489;
+ wire T_3492;
+ wire T_3493;
+ wire T_3496;
+ wire T_3497;
+ wire T_3500;
+ wire [26:0] T_3501;
+ wire [26:0] T_3502;
+ wire [26:0] T_3503;
+ wire T_3504;
+ wire T_3505;
+ wire T_3508;
+ wire T_3509;
+ wire T_3512;
+ wire T_3513;
+ wire [5:0] T_3516;
+ wire T_3520;
+ wire T_3521;
+ wire T_3522;
+ wire T_3523;
+ wire T_3524;
+ wire T_3525;
+ wire T_3526;
+ wire T_3527;
+ wire T_3528;
+ wire T_3529;
+ wire T_3530;
+ wire T_3531;
+ wire T_3532;
+ wire T_3533;
+ wire T_3534;
+ wire T_3535;
+ wire T_3536;
+ wire T_3537;
+ wire T_3538;
+ wire T_3539;
+ wire T_3540;
+ wire T_3541;
+ wire T_3542;
+ wire T_3543;
+ wire T_3544;
+ wire T_3545;
+ wire T_3546;
+ wire T_3547;
+ wire T_3548;
+ wire T_3549;
+ wire T_3550;
+ wire T_3551;
+ wire T_3552;
+ wire T_3553;
+ wire T_3554;
+ wire T_3555;
+ wire T_3556;
+ wire T_3557;
+ wire T_3558;
+ wire T_3559;
+ wire T_3560;
+ wire T_3561;
+ wire T_3562;
+ wire T_3563;
+ wire T_3564;
+ wire T_3565;
+ wire T_3566;
+ wire T_3567;
+ wire T_3568;
+ wire T_3569;
+ wire T_3570;
+ wire T_3571;
+ wire T_3572;
+ wire T_3573;
+ wire T_3574;
+ wire T_3575;
+ wire T_3576;
+ wire T_3577;
+ wire T_3578;
+ wire T_3579;
+ wire T_3580;
+ wire T_3581;
+ wire T_3582;
+ wire [5:0] T_3584;
+ wire [5:0] T_3586;
+ wire [5:0] T_3588;
+ wire [5:0] T_3590;
+ wire [5:0] T_3592;
+ wire [5:0] T_3594;
+ wire [5:0] T_3596;
+ wire [5:0] T_3598;
+ wire [5:0] T_3600;
+ wire [5:0] T_3602;
+ wire [5:0] T_3604;
+ wire [5:0] T_3606;
+ wire [5:0] T_3608;
+ wire [5:0] T_3610;
+ wire [5:0] T_3612;
+ wire [5:0] T_3614;
+ wire [5:0] T_3616;
+ wire [5:0] T_3618;
+ wire [5:0] T_3620;
+ wire [5:0] T_3622;
+ wire [5:0] T_3624;
+ wire [5:0] T_3626;
+ wire [5:0] T_3628;
+ wire [5:0] T_3630;
+ wire [5:0] T_3632;
+ wire [5:0] T_3634;
+ wire [5:0] T_3636;
+ wire [5:0] T_3638;
+ wire [5:0] T_3640;
+ wire [5:0] T_3642;
+ wire [5:0] T_3644;
+ wire [5:0] T_3646;
+ wire [5:0] T_3648;
+ wire [5:0] T_3650;
+ wire [5:0] T_3652;
+ wire [5:0] T_3654;
+ wire [5:0] T_3656;
+ wire [5:0] T_3658;
+ wire [5:0] T_3660;
+ wire [5:0] T_3662;
+ wire [5:0] T_3664;
+ wire [5:0] T_3666;
+ wire [5:0] T_3668;
+ wire [5:0] T_3670;
+ wire [5:0] T_3672;
+ wire [5:0] T_3674;
+ wire [5:0] T_3676;
+ wire [5:0] T_3678;
+ wire [5:0] T_3680;
+ wire [5:0] T_3682;
+ wire [5:0] T_3684;
+ wire [5:0] T_3686;
+ wire [5:0] T_3688;
+ wire [5:0] T_3690;
+ wire [5:0] T_3692;
+ wire [5:0] T_3694;
+ wire [5:0] T_3696;
+ wire [5:0] T_3698;
+ wire [5:0] T_3700;
+ wire [5:0] T_3702;
+ wire [5:0] T_3704;
+ wire [5:0] T_3706;
+ wire [5:0] T_3708;
+ wire [5:0] T_3709;
+ wire [5:0] T_3710;
+ wire [5:0] T_3711;
+ wire [5:0] T_3712;
+ wire [5:0] T_3713;
+ wire [5:0] T_3714;
+ wire [5:0] T_3715;
+ wire [5:0] T_3716;
+ wire [5:0] T_3717;
+ wire [5:0] T_3718;
+ wire [5:0] T_3719;
+ wire [5:0] T_3720;
+ wire [5:0] T_3721;
+ wire [5:0] T_3722;
+ wire [5:0] T_3723;
+ wire [5:0] T_3724;
+ wire [5:0] T_3725;
+ wire [5:0] T_3726;
+ wire [5:0] T_3727;
+ wire [5:0] T_3728;
+ wire [5:0] T_3729;
+ wire [5:0] T_3730;
+ wire [5:0] T_3731;
+ wire [5:0] T_3732;
+ wire [5:0] T_3733;
+ wire [5:0] T_3734;
+ wire [5:0] T_3735;
+ wire [5:0] T_3736;
+ wire [5:0] T_3737;
+ wire [5:0] T_3738;
+ wire [5:0] T_3739;
+ wire [5:0] T_3740;
+ wire [5:0] T_3741;
+ wire [5:0] T_3742;
+ wire [5:0] T_3743;
+ wire [5:0] T_3744;
+ wire [5:0] T_3745;
+ wire [5:0] T_3746;
+ wire [5:0] T_3747;
+ wire [5:0] T_3748;
+ wire [5:0] T_3749;
+ wire [5:0] T_3750;
+ wire [5:0] T_3751;
+ wire [5:0] T_3752;
+ wire [5:0] T_3753;
+ wire [5:0] T_3754;
+ wire [5:0] T_3755;
+ wire [5:0] T_3756;
+ wire [5:0] T_3757;
+ wire [5:0] T_3758;
+ wire [5:0] T_3759;
+ wire [5:0] T_3760;
+ wire [5:0] T_3761;
+ wire [5:0] T_3762;
+ wire [5:0] T_3763;
+ wire [5:0] T_3764;
+ wire [5:0] T_3765;
+ wire [5:0] T_3766;
+ wire [5:0] T_3767;
+ wire [5:0] T_3768;
+ wire [5:0] T_3769;
+ wire T_3770;
+ wire T_3771;
+ wire T_3772;
+ wire T_3773;
+ wire T_3774;
+ wire T_3775;
+ wire [26:0] T_3789;
+ wire [26:0] T_3791;
+ wire [26:0] T_3793;
+ wire [26:0] T_3795;
+ wire [26:0] T_3797;
+ wire [26:0] T_3799;
+ wire [26:0] T_3801;
+ wire [26:0] T_3802;
+ wire [26:0] T_3803;
+ wire [26:0] T_3804;
+ wire [26:0] T_3805;
+ wire [26:0] T_3806;
+ wire T_3807;
+ wire T_3808;
+ wire T_3809;
+ wire T_3810;
+ wire T_3811;
+ wire T_3812;
+ wire T_3813;
+ wire T_3814;
+ wire T_3815;
+ wire T_3816;
+ wire T_3817;
+ wire T_3818;
+ wire T_3819;
+ wire T_3820;
+ wire T_3821;
+ wire T_3822;
+ wire T_3823;
+ wire T_3824;
+ wire T_3825;
+ wire T_3826;
+ wire T_3827;
+ wire T_3828;
+ wire T_3829;
+ wire T_3830;
+ wire T_3831;
+ wire T_3832;
+ wire T_3833;
+ wire T_3834;
+ wire T_3835;
+ wire T_3836;
+ wire T_3837;
+ wire T_3838;
+ wire T_3839;
+ wire T_3840;
+ wire T_3841;
+ wire T_3842;
+ wire T_3843;
+ wire T_3844;
+ wire T_3845;
+ wire T_3846;
+ wire T_3847;
+ wire T_3848;
+ wire T_3849;
+ wire T_3850;
+ wire T_3851;
+ wire T_3852;
+ wire T_3853;
+ wire T_3854;
+ wire T_3855;
+ wire T_3856;
+ wire T_3857;
+ wire T_3858;
+ wire T_3859;
+ wire T_3860;
+ wire T_3861;
+ wire T_3862;
+ wire T_3863;
+ wire T_3864;
+ wire T_3865;
+ wire T_3866;
+ wire T_3867;
+ wire T_3868;
+ wire [11:0] T_3994;
+ wire [11:0] T_3996;
+ wire [11:0] T_3998;
+ wire [11:0] T_4000;
+ wire [11:0] T_4002;
+ wire [11:0] T_4004;
+ wire [11:0] T_4006;
+ wire [11:0] T_4008;
+ wire [11:0] T_4010;
+ wire [11:0] T_4012;
+ wire [11:0] T_4014;
+ wire [11:0] T_4016;
+ wire [11:0] T_4018;
+ wire [11:0] T_4020;
+ wire [11:0] T_4022;
+ wire [11:0] T_4024;
+ wire [11:0] T_4026;
+ wire [11:0] T_4028;
+ wire [11:0] T_4030;
+ wire [11:0] T_4032;
+ wire [11:0] T_4034;
+ wire [11:0] T_4036;
+ wire [11:0] T_4038;
+ wire [11:0] T_4040;
+ wire [11:0] T_4042;
+ wire [11:0] T_4044;
+ wire [11:0] T_4046;
+ wire [11:0] T_4048;
+ wire [11:0] T_4050;
+ wire [11:0] T_4052;
+ wire [11:0] T_4054;
+ wire [11:0] T_4056;
+ wire [11:0] T_4058;
+ wire [11:0] T_4060;
+ wire [11:0] T_4062;
+ wire [11:0] T_4064;
+ wire [11:0] T_4066;
+ wire [11:0] T_4068;
+ wire [11:0] T_4070;
+ wire [11:0] T_4072;
+ wire [11:0] T_4074;
+ wire [11:0] T_4076;
+ wire [11:0] T_4078;
+ wire [11:0] T_4080;
+ wire [11:0] T_4082;
+ wire [11:0] T_4084;
+ wire [11:0] T_4086;
+ wire [11:0] T_4088;
+ wire [11:0] T_4090;
+ wire [11:0] T_4092;
+ wire [11:0] T_4094;
+ wire [11:0] T_4096;
+ wire [11:0] T_4098;
+ wire [11:0] T_4100;
+ wire [11:0] T_4102;
+ wire [11:0] T_4104;
+ wire [11:0] T_4106;
+ wire [11:0] T_4108;
+ wire [11:0] T_4110;
+ wire [11:0] T_4112;
+ wire [11:0] T_4114;
+ wire [11:0] T_4116;
+ wire [11:0] T_4118;
+ wire [11:0] T_4119;
+ wire [11:0] T_4120;
+ wire [11:0] T_4121;
+ wire [11:0] T_4122;
+ wire [11:0] T_4123;
+ wire [11:0] T_4124;
+ wire [11:0] T_4125;
+ wire [11:0] T_4126;
+ wire [11:0] T_4127;
+ wire [11:0] T_4128;
+ wire [11:0] T_4129;
+ wire [11:0] T_4130;
+ wire [11:0] T_4131;
+ wire [11:0] T_4132;
+ wire [11:0] T_4133;
+ wire [11:0] T_4134;
+ wire [11:0] T_4135;
+ wire [11:0] T_4136;
+ wire [11:0] T_4137;
+ wire [11:0] T_4138;
+ wire [11:0] T_4139;
+ wire [11:0] T_4140;
+ wire [11:0] T_4141;
+ wire [11:0] T_4142;
+ wire [11:0] T_4143;
+ wire [11:0] T_4144;
+ wire [11:0] T_4145;
+ wire [11:0] T_4146;
+ wire [11:0] T_4147;
+ wire [11:0] T_4148;
+ wire [11:0] T_4149;
+ wire [11:0] T_4150;
+ wire [11:0] T_4151;
+ wire [11:0] T_4152;
+ wire [11:0] T_4153;
+ wire [11:0] T_4154;
+ wire [11:0] T_4155;
+ wire [11:0] T_4156;
+ wire [11:0] T_4157;
+ wire [11:0] T_4158;
+ wire [11:0] T_4159;
+ wire [11:0] T_4160;
+ wire [11:0] T_4161;
+ wire [11:0] T_4162;
+ wire [11:0] T_4163;
+ wire [11:0] T_4164;
+ wire [11:0] T_4165;
+ wire [11:0] T_4166;
+ wire [11:0] T_4167;
+ wire [11:0] T_4168;
+ wire [11:0] T_4169;
+ wire [11:0] T_4170;
+ wire [11:0] T_4171;
+ wire [11:0] T_4172;
+ wire [11:0] T_4173;
+ wire [11:0] T_4174;
+ wire [11:0] T_4175;
+ wire [11:0] T_4176;
+ wire [11:0] T_4177;
+ wire [11:0] T_4178;
+ wire [11:0] T_4179;
+ wire [38:0] T_4180;
+ wire [29:0] T_4181;
+ wire [31:0] T_4182;
+ wire T_4184;
+ wire [31:0] T_4185;
+ wire [15:0] T_4186;
+ wire [15:0] T_4187;
+ wire T_4189;
+ wire [15:0] T_4190;
+ wire [7:0] T_4191;
+ wire [7:0] T_4192;
+ wire T_4194;
+ wire [7:0] T_4195;
+ wire [3:0] T_4196;
+ wire [3:0] T_4197;
+ wire T_4199;
+ wire [3:0] T_4200;
+ wire [1:0] T_4201;
+ wire [1:0] T_4202;
+ wire T_4204;
+ wire [1:0] T_4205;
+ wire T_4206;
+ wire [1:0] T_4207;
+ wire [2:0] T_4208;
+ wire [3:0] T_4209;
+ wire [4:0] T_4210;
+ wire [5:0] T_4211;
+ reg [1:0] T_4216 [0:127];
+ wire [1:0] T_4216_T_4542_data;
+ wire [6:0] T_4216_T_4542_addr;
+ wire T_4216_T_4542_en;
+ wire T_4216_T_4542_clk;
+ wire [1:0] T_4216_T_4549_data;
+ wire [6:0] T_4216_T_4549_addr;
+ wire T_4216_T_4549_mask;
+ wire T_4216_T_4549_en;
+ wire T_4216_T_4549_clk;
+ reg [6:0] T_4218;
+ wire T_4219;
+ wire T_4220;
+ wire T_4221;
+ wire T_4222;
+ wire T_4223;
+ wire T_4224;
+ wire T_4225;
+ wire T_4226;
+ wire T_4227;
+ wire T_4228;
+ wire T_4229;
+ wire T_4230;
+ wire T_4231;
+ wire T_4232;
+ wire T_4233;
+ wire T_4234;
+ wire T_4235;
+ wire T_4236;
+ wire T_4237;
+ wire T_4238;
+ wire T_4239;
+ wire T_4240;
+ wire T_4241;
+ wire T_4242;
+ wire T_4243;
+ wire T_4244;
+ wire T_4245;
+ wire T_4246;
+ wire T_4247;
+ wire T_4248;
+ wire T_4249;
+ wire T_4250;
+ wire T_4251;
+ wire T_4252;
+ wire T_4253;
+ wire T_4254;
+ wire T_4255;
+ wire T_4256;
+ wire T_4257;
+ wire T_4258;
+ wire T_4259;
+ wire T_4260;
+ wire T_4261;
+ wire T_4262;
+ wire T_4263;
+ wire T_4264;
+ wire T_4265;
+ wire T_4266;
+ wire T_4267;
+ wire T_4268;
+ wire T_4269;
+ wire T_4270;
+ wire T_4271;
+ wire T_4272;
+ wire T_4273;
+ wire T_4274;
+ wire T_4275;
+ wire T_4276;
+ wire T_4277;
+ wire T_4278;
+ wire T_4279;
+ wire T_4280;
+ wire T_4282;
+ wire T_4283;
+ wire T_4285;
+ wire T_4286;
+ wire T_4288;
+ wire T_4289;
+ wire T_4291;
+ wire T_4292;
+ wire T_4294;
+ wire T_4295;
+ wire T_4297;
+ wire T_4298;
+ wire T_4300;
+ wire T_4301;
+ wire T_4303;
+ wire T_4304;
+ wire T_4306;
+ wire T_4307;
+ wire T_4309;
+ wire T_4310;
+ wire T_4312;
+ wire T_4313;
+ wire T_4315;
+ wire T_4316;
+ wire T_4318;
+ wire T_4319;
+ wire T_4321;
+ wire T_4322;
+ wire T_4324;
+ wire T_4325;
+ wire T_4327;
+ wire T_4328;
+ wire T_4330;
+ wire T_4331;
+ wire T_4333;
+ wire T_4334;
+ wire T_4336;
+ wire T_4337;
+ wire T_4339;
+ wire T_4340;
+ wire T_4342;
+ wire T_4343;
+ wire T_4345;
+ wire T_4346;
+ wire T_4348;
+ wire T_4349;
+ wire T_4351;
+ wire T_4352;
+ wire T_4354;
+ wire T_4355;
+ wire T_4357;
+ wire T_4358;
+ wire T_4360;
+ wire T_4361;
+ wire T_4363;
+ wire T_4364;
+ wire T_4366;
+ wire T_4367;
+ wire T_4369;
+ wire T_4370;
+ wire T_4372;
+ wire T_4373;
+ wire T_4375;
+ wire T_4376;
+ wire T_4378;
+ wire T_4379;
+ wire T_4381;
+ wire T_4382;
+ wire T_4384;
+ wire T_4385;
+ wire T_4387;
+ wire T_4388;
+ wire T_4390;
+ wire T_4391;
+ wire T_4393;
+ wire T_4394;
+ wire T_4396;
+ wire T_4397;
+ wire T_4399;
+ wire T_4400;
+ wire T_4402;
+ wire T_4403;
+ wire T_4405;
+ wire T_4406;
+ wire T_4408;
+ wire T_4409;
+ wire T_4411;
+ wire T_4412;
+ wire T_4414;
+ wire T_4415;
+ wire T_4417;
+ wire T_4418;
+ wire T_4420;
+ wire T_4421;
+ wire T_4423;
+ wire T_4424;
+ wire T_4426;
+ wire T_4427;
+ wire T_4429;
+ wire T_4430;
+ wire T_4432;
+ wire T_4433;
+ wire T_4435;
+ wire T_4436;
+ wire T_4438;
+ wire T_4439;
+ wire T_4441;
+ wire T_4442;
+ wire T_4444;
+ wire T_4445;
+ wire T_4447;
+ wire T_4448;
+ wire T_4450;
+ wire T_4451;
+ wire T_4453;
+ wire T_4454;
+ wire T_4456;
+ wire T_4457;
+ wire T_4459;
+ wire T_4460;
+ wire T_4462;
+ wire T_4463;
+ wire T_4465;
+ wire T_4466;
+ wire T_4468;
+ wire T_4469;
+ wire T_4470;
+ wire T_4471;
+ wire T_4472;
+ wire T_4473;
+ wire T_4474;
+ wire T_4475;
+ wire T_4476;
+ wire T_4477;
+ wire T_4478;
+ wire T_4479;
+ wire T_4480;
+ wire T_4481;
+ wire T_4482;
+ wire T_4483;
+ wire T_4484;
+ wire T_4485;
+ wire T_4486;
+ wire T_4487;
+ wire T_4488;
+ wire T_4489;
+ wire T_4490;
+ wire T_4491;
+ wire T_4492;
+ wire T_4493;
+ wire T_4494;
+ wire T_4495;
+ wire T_4496;
+ wire T_4497;
+ wire T_4498;
+ wire T_4499;
+ wire T_4500;
+ wire T_4501;
+ wire T_4502;
+ wire T_4503;
+ wire T_4504;
+ wire T_4505;
+ wire T_4506;
+ wire T_4507;
+ wire T_4508;
+ wire T_4509;
+ wire T_4510;
+ wire T_4511;
+ wire T_4512;
+ wire T_4513;
+ wire T_4514;
+ wire T_4515;
+ wire T_4516;
+ wire T_4517;
+ wire T_4518;
+ wire T_4519;
+ wire T_4520;
+ wire T_4521;
+ wire T_4522;
+ wire T_4523;
+ wire T_4524;
+ wire T_4525;
+ wire T_4526;
+ wire T_4527;
+ wire T_4528;
+ wire T_4529;
+ wire T_4531;
+ wire T_4532;
+ wire T_4533;
+ wire [6:0] T_4537_history;
+ wire [1:0] T_4537_value;
+ wire [6:0] T_4540;
+ wire [6:0] T_4541;
+ wire T_4543;
+ wire [5:0] T_4544;
+ wire [6:0] T_4545;
+ wire T_4546;
+ wire [6:0] T_4547;
+ wire [6:0] T_4548;
+ wire T_4550;
+ wire T_4551;
+ wire T_4552;
+ wire T_4553;
+ wire T_4554;
+ wire T_4555;
+ wire T_4556;
+ wire T_4557;
+ wire [1:0] T_4558;
+ wire [5:0] T_4559;
+ wire [6:0] T_4560;
+ wire T_4561;
+ wire T_4563;
+ wire T_4564;
+ reg [1:0] T_4567;
+ reg T_4569;
+ reg [38:0] T_4578_0;
+ reg [38:0] T_4578_1;
+ wire T_4582;
+ wire T_4583;
+ wire T_4584;
+ wire T_4585;
+ wire T_4586;
+ wire T_4587;
+ wire T_4588;
+ wire T_4589;
+ wire T_4590;
+ wire T_4591;
+ wire T_4592;
+ wire T_4593;
+ wire T_4594;
+ wire T_4595;
+ wire T_4596;
+ wire T_4597;
+ wire T_4598;
+ wire T_4599;
+ wire T_4600;
+ wire T_4601;
+ wire T_4602;
+ wire T_4603;
+ wire T_4604;
+ wire T_4605;
+ wire T_4606;
+ wire T_4607;
+ wire T_4608;
+ wire T_4609;
+ wire T_4610;
+ wire T_4611;
+ wire T_4612;
+ wire T_4613;
+ wire T_4614;
+ wire T_4615;
+ wire T_4616;
+ wire T_4617;
+ wire T_4618;
+ wire T_4619;
+ wire T_4620;
+ wire T_4621;
+ wire T_4622;
+ wire T_4623;
+ wire T_4624;
+ wire T_4625;
+ wire T_4626;
+ wire T_4627;
+ wire T_4628;
+ wire T_4629;
+ wire T_4630;
+ wire T_4631;
+ wire T_4632;
+ wire T_4633;
+ wire T_4634;
+ wire T_4635;
+ wire T_4636;
+ wire T_4637;
+ wire T_4638;
+ wire T_4639;
+ wire T_4640;
+ wire T_4641;
+ wire T_4642;
+ wire T_4643;
+ wire T_4645;
+ wire T_4646;
+ wire T_4648;
+ wire T_4649;
+ wire T_4651;
+ wire T_4652;
+ wire T_4654;
+ wire T_4655;
+ wire T_4657;
+ wire T_4658;
+ wire T_4660;
+ wire T_4661;
+ wire T_4663;
+ wire T_4664;
+ wire T_4666;
+ wire T_4667;
+ wire T_4669;
+ wire T_4670;
+ wire T_4672;
+ wire T_4673;
+ wire T_4675;
+ wire T_4676;
+ wire T_4678;
+ wire T_4679;
+ wire T_4681;
+ wire T_4682;
+ wire T_4684;
+ wire T_4685;
+ wire T_4687;
+ wire T_4688;
+ wire T_4690;
+ wire T_4691;
+ wire T_4693;
+ wire T_4694;
+ wire T_4696;
+ wire T_4697;
+ wire T_4699;
+ wire T_4700;
+ wire T_4702;
+ wire T_4703;
+ wire T_4705;
+ wire T_4706;
+ wire T_4708;
+ wire T_4709;
+ wire T_4711;
+ wire T_4712;
+ wire T_4714;
+ wire T_4715;
+ wire T_4717;
+ wire T_4718;
+ wire T_4720;
+ wire T_4721;
+ wire T_4723;
+ wire T_4724;
+ wire T_4726;
+ wire T_4727;
+ wire T_4729;
+ wire T_4730;
+ wire T_4732;
+ wire T_4733;
+ wire T_4735;
+ wire T_4736;
+ wire T_4738;
+ wire T_4739;
+ wire T_4741;
+ wire T_4742;
+ wire T_4744;
+ wire T_4745;
+ wire T_4747;
+ wire T_4748;
+ wire T_4750;
+ wire T_4751;
+ wire T_4753;
+ wire T_4754;
+ wire T_4756;
+ wire T_4757;
+ wire T_4759;
+ wire T_4760;
+ wire T_4762;
+ wire T_4763;
+ wire T_4765;
+ wire T_4766;
+ wire T_4768;
+ wire T_4769;
+ wire T_4771;
+ wire T_4772;
+ wire T_4774;
+ wire T_4775;
+ wire T_4777;
+ wire T_4778;
+ wire T_4780;
+ wire T_4781;
+ wire T_4783;
+ wire T_4784;
+ wire T_4786;
+ wire T_4787;
+ wire T_4789;
+ wire T_4790;
+ wire T_4792;
+ wire T_4793;
+ wire T_4795;
+ wire T_4796;
+ wire T_4798;
+ wire T_4799;
+ wire T_4801;
+ wire T_4802;
+ wire T_4804;
+ wire T_4805;
+ wire T_4807;
+ wire T_4808;
+ wire T_4810;
+ wire T_4811;
+ wire T_4813;
+ wire T_4814;
+ wire T_4816;
+ wire T_4817;
+ wire T_4819;
+ wire T_4820;
+ wire T_4822;
+ wire T_4823;
+ wire T_4825;
+ wire T_4826;
+ wire T_4828;
+ wire T_4829;
+ wire T_4831;
+ wire T_4832;
+ wire T_4833;
+ wire T_4834;
+ wire T_4835;
+ wire T_4836;
+ wire T_4837;
+ wire T_4838;
+ wire T_4839;
+ wire T_4840;
+ wire T_4841;
+ wire T_4842;
+ wire T_4843;
+ wire T_4844;
+ wire T_4845;
+ wire T_4846;
+ wire T_4847;
+ wire T_4848;
+ wire T_4849;
+ wire T_4850;
+ wire T_4851;
+ wire T_4852;
+ wire T_4853;
+ wire T_4854;
+ wire T_4855;
+ wire T_4856;
+ wire T_4857;
+ wire T_4858;
+ wire T_4859;
+ wire T_4860;
+ wire T_4861;
+ wire T_4862;
+ wire T_4863;
+ wire T_4864;
+ wire T_4865;
+ wire T_4866;
+ wire T_4867;
+ wire T_4868;
+ wire T_4869;
+ wire T_4870;
+ wire T_4871;
+ wire T_4872;
+ wire T_4873;
+ wire T_4874;
+ wire T_4875;
+ wire T_4876;
+ wire T_4877;
+ wire T_4878;
+ wire T_4879;
+ wire T_4880;
+ wire T_4881;
+ wire T_4882;
+ wire T_4883;
+ wire T_4884;
+ wire T_4885;
+ wire T_4886;
+ wire T_4887;
+ wire T_4888;
+ wire T_4889;
+ wire T_4890;
+ wire T_4891;
+ wire T_4892;
+ wire T_4894;
+ wire T_4896;
+ wire T_4897;
+ wire [38:0] GEN_2;
+ wire T_4900;
+ wire [2:0] T_4902;
+ wire [1:0] T_4903;
+ wire T_4906;
+ wire T_4907;
+ wire [1:0] T_4909;
+ wire T_4910;
+ wire T_4912;
+ wire [38:0] GEN_3;
+ wire T_4914;
+ wire T_4916;
+ wire T_4917;
+ wire T_4919;
+ wire T_4921;
+ wire [2:0] T_4923;
+ wire [1:0] T_4924;
+ wire T_4927;
+ wire T_4928;
+ wire [1:0] T_4930;
+ wire T_4931;
+ wire T_4933;
+ wire GEN_4;
+ wire GEN_5;
+ wire GEN_6;
+ wire GEN_7;
+ wire GEN_8;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ wire GEN_17;
+ wire GEN_18;
+ wire GEN_19;
+ wire GEN_20;
+ wire GEN_21;
+ wire GEN_22;
+ wire GEN_23;
+ wire GEN_24;
+ wire GEN_25;
+ wire GEN_26;
+ wire GEN_27;
+ wire GEN_28;
+ wire GEN_29;
+ wire GEN_30;
+ wire GEN_31;
+ wire GEN_32;
+ wire GEN_33;
+ wire GEN_34;
+ wire GEN_35;
+ wire GEN_36;
+ wire GEN_37;
+ wire GEN_38;
+ wire GEN_39;
+ wire GEN_40;
+ wire GEN_41;
+ wire GEN_42;
+ wire GEN_43;
+ wire GEN_44;
+ wire GEN_45;
+ wire GEN_46;
+ wire GEN_47;
+ wire GEN_48;
+ wire GEN_49;
+ wire GEN_50;
+ wire GEN_51;
+ wire GEN_52;
+ wire GEN_53;
+ wire GEN_54;
+ wire GEN_55;
+ wire GEN_56;
+ wire GEN_57;
+ wire GEN_58;
+ wire GEN_59;
+ wire GEN_60;
+ wire GEN_61;
+ wire GEN_62;
+ wire GEN_63;
+ wire GEN_64;
+ wire GEN_65;
+ wire GEN_66;
+ wire GEN_67;
+ wire GEN_68;
+ wire GEN_69;
+ wire GEN_70;
+ wire GEN_71;
+ wire GEN_72;
+ wire GEN_73;
+ wire GEN_74;
+ wire GEN_75;
+ wire GEN_76;
+ wire GEN_77;
+ wire GEN_78;
+ wire GEN_79;
+ wire GEN_80;
+ wire GEN_81;
+ wire GEN_82;
+ wire GEN_83;
+ wire GEN_84;
+ wire GEN_85;
+ wire GEN_86;
+ wire GEN_87;
+ wire GEN_88;
+ wire GEN_89;
+ wire GEN_90;
+ wire GEN_91;
+ wire GEN_92;
+ wire GEN_93;
+ wire GEN_94;
+ wire GEN_95;
+ wire GEN_96;
+ wire GEN_97;
+ wire GEN_98;
+ wire GEN_99;
+ wire GEN_100;
+ wire GEN_101;
+ wire GEN_102;
+ wire GEN_103;
+ wire GEN_104;
+ wire GEN_105;
+ wire GEN_106;
+ wire GEN_107;
+ wire GEN_108;
+ wire GEN_109;
+ wire GEN_110;
+ wire GEN_111;
+ wire GEN_112;
+ wire GEN_113;
+ wire GEN_114;
+ wire GEN_115;
+ wire GEN_116;
+ wire GEN_117;
+ wire GEN_118;
+ wire GEN_119;
+ wire GEN_120;
+ wire GEN_121;
+ wire GEN_122;
+ wire GEN_123;
+ wire GEN_124;
+ wire GEN_125;
+ wire GEN_126;
+ wire GEN_127;
+ wire GEN_128;
+ wire GEN_129;
+ wire GEN_130;
+ wire GEN_131;
+ wire GEN_132;
+ wire GEN_133;
+ assign io_resp_valid = T_3520;
+ assign io_resp_bits_taken = T_4564 ? 1'h0 : io_resp_valid;
+ assign io_resp_bits_mask = 1'h1;
+ assign io_resp_bits_bridx = brIdx_T_4212_data;
+ assign io_resp_bits_target = io_ras_update_valid ? io_ras_update_bits_isCall ? T_4892 ? io_ras_update_bits_returnAddr : T_4897 ? GEN_2 : T_4180 : T_4897 ? GEN_2 : T_4180 : T_4897 ? GEN_2 : T_4180;
+ assign io_resp_bits_entry = T_4211;
+ assign io_resp_bits_bht_history = T_4537_history;
+ assign io_resp_bits_bht_value = T_4537_value;
+ assign idxs_T_1699_addr = 1'h0;
+ assign idxs_T_1699_en = 1'h1;
+ assign idxs_T_1699_clk = clk;
+ assign idxs_T_1699_data = idxs[idxs_T_1699_addr];
+ assign idxs_T_1702_addr = 1'h1;
+ assign idxs_T_1702_en = 1'h1;
+ assign idxs_T_1702_clk = clk;
+ assign idxs_T_1702_data = idxs[idxs_T_1702_addr];
+ assign idxs_T_1705_addr = 2'h2;
+ assign idxs_T_1705_en = 1'h1;
+ assign idxs_T_1705_clk = clk;
+ assign idxs_T_1705_data = idxs[idxs_T_1705_addr];
+ assign idxs_T_1708_addr = 2'h3;
+ assign idxs_T_1708_en = 1'h1;
+ assign idxs_T_1708_clk = clk;
+ assign idxs_T_1708_data = idxs[idxs_T_1708_addr];
+ assign idxs_T_1711_addr = 3'h4;
+ assign idxs_T_1711_en = 1'h1;
+ assign idxs_T_1711_clk = clk;
+ assign idxs_T_1711_data = idxs[idxs_T_1711_addr];
+ assign idxs_T_1714_addr = 3'h5;
+ assign idxs_T_1714_en = 1'h1;
+ assign idxs_T_1714_clk = clk;
+ assign idxs_T_1714_data = idxs[idxs_T_1714_addr];
+ assign idxs_T_1717_addr = 3'h6;
+ assign idxs_T_1717_en = 1'h1;
+ assign idxs_T_1717_clk = clk;
+ assign idxs_T_1717_data = idxs[idxs_T_1717_addr];
+ assign idxs_T_1720_addr = 3'h7;
+ assign idxs_T_1720_en = 1'h1;
+ assign idxs_T_1720_clk = clk;
+ assign idxs_T_1720_data = idxs[idxs_T_1720_addr];
+ assign idxs_T_1723_addr = 4'h8;
+ assign idxs_T_1723_en = 1'h1;
+ assign idxs_T_1723_clk = clk;
+ assign idxs_T_1723_data = idxs[idxs_T_1723_addr];
+ assign idxs_T_1726_addr = 4'h9;
+ assign idxs_T_1726_en = 1'h1;
+ assign idxs_T_1726_clk = clk;
+ assign idxs_T_1726_data = idxs[idxs_T_1726_addr];
+ assign idxs_T_1729_addr = 4'ha;
+ assign idxs_T_1729_en = 1'h1;
+ assign idxs_T_1729_clk = clk;
+ assign idxs_T_1729_data = idxs[idxs_T_1729_addr];
+ assign idxs_T_1732_addr = 4'hb;
+ assign idxs_T_1732_en = 1'h1;
+ assign idxs_T_1732_clk = clk;
+ assign idxs_T_1732_data = idxs[idxs_T_1732_addr];
+ assign idxs_T_1735_addr = 4'hc;
+ assign idxs_T_1735_en = 1'h1;
+ assign idxs_T_1735_clk = clk;
+ assign idxs_T_1735_data = idxs[idxs_T_1735_addr];
+ assign idxs_T_1738_addr = 4'hd;
+ assign idxs_T_1738_en = 1'h1;
+ assign idxs_T_1738_clk = clk;
+ assign idxs_T_1738_data = idxs[idxs_T_1738_addr];
+ assign idxs_T_1741_addr = 4'he;
+ assign idxs_T_1741_en = 1'h1;
+ assign idxs_T_1741_clk = clk;
+ assign idxs_T_1741_data = idxs[idxs_T_1741_addr];
+ assign idxs_T_1744_addr = 4'hf;
+ assign idxs_T_1744_en = 1'h1;
+ assign idxs_T_1744_clk = clk;
+ assign idxs_T_1744_data = idxs[idxs_T_1744_addr];
+ assign idxs_T_1747_addr = 5'h10;
+ assign idxs_T_1747_en = 1'h1;
+ assign idxs_T_1747_clk = clk;
+ assign idxs_T_1747_data = idxs[idxs_T_1747_addr];
+ assign idxs_T_1750_addr = 5'h11;
+ assign idxs_T_1750_en = 1'h1;
+ assign idxs_T_1750_clk = clk;
+ assign idxs_T_1750_data = idxs[idxs_T_1750_addr];
+ assign idxs_T_1753_addr = 5'h12;
+ assign idxs_T_1753_en = 1'h1;
+ assign idxs_T_1753_clk = clk;
+ assign idxs_T_1753_data = idxs[idxs_T_1753_addr];
+ assign idxs_T_1756_addr = 5'h13;
+ assign idxs_T_1756_en = 1'h1;
+ assign idxs_T_1756_clk = clk;
+ assign idxs_T_1756_data = idxs[idxs_T_1756_addr];
+ assign idxs_T_1759_addr = 5'h14;
+ assign idxs_T_1759_en = 1'h1;
+ assign idxs_T_1759_clk = clk;
+ assign idxs_T_1759_data = idxs[idxs_T_1759_addr];
+ assign idxs_T_1762_addr = 5'h15;
+ assign idxs_T_1762_en = 1'h1;
+ assign idxs_T_1762_clk = clk;
+ assign idxs_T_1762_data = idxs[idxs_T_1762_addr];
+ assign idxs_T_1765_addr = 5'h16;
+ assign idxs_T_1765_en = 1'h1;
+ assign idxs_T_1765_clk = clk;
+ assign idxs_T_1765_data = idxs[idxs_T_1765_addr];
+ assign idxs_T_1768_addr = 5'h17;
+ assign idxs_T_1768_en = 1'h1;
+ assign idxs_T_1768_clk = clk;
+ assign idxs_T_1768_data = idxs[idxs_T_1768_addr];
+ assign idxs_T_1771_addr = 5'h18;
+ assign idxs_T_1771_en = 1'h1;
+ assign idxs_T_1771_clk = clk;
+ assign idxs_T_1771_data = idxs[idxs_T_1771_addr];
+ assign idxs_T_1774_addr = 5'h19;
+ assign idxs_T_1774_en = 1'h1;
+ assign idxs_T_1774_clk = clk;
+ assign idxs_T_1774_data = idxs[idxs_T_1774_addr];
+ assign idxs_T_1777_addr = 5'h1a;
+ assign idxs_T_1777_en = 1'h1;
+ assign idxs_T_1777_clk = clk;
+ assign idxs_T_1777_data = idxs[idxs_T_1777_addr];
+ assign idxs_T_1780_addr = 5'h1b;
+ assign idxs_T_1780_en = 1'h1;
+ assign idxs_T_1780_clk = clk;
+ assign idxs_T_1780_data = idxs[idxs_T_1780_addr];
+ assign idxs_T_1783_addr = 5'h1c;
+ assign idxs_T_1783_en = 1'h1;
+ assign idxs_T_1783_clk = clk;
+ assign idxs_T_1783_data = idxs[idxs_T_1783_addr];
+ assign idxs_T_1786_addr = 5'h1d;
+ assign idxs_T_1786_en = 1'h1;
+ assign idxs_T_1786_clk = clk;
+ assign idxs_T_1786_data = idxs[idxs_T_1786_addr];
+ assign idxs_T_1789_addr = 5'h1e;
+ assign idxs_T_1789_en = 1'h1;
+ assign idxs_T_1789_clk = clk;
+ assign idxs_T_1789_data = idxs[idxs_T_1789_addr];
+ assign idxs_T_1792_addr = 5'h1f;
+ assign idxs_T_1792_en = 1'h1;
+ assign idxs_T_1792_clk = clk;
+ assign idxs_T_1792_data = idxs[idxs_T_1792_addr];
+ assign idxs_T_1795_addr = 6'h20;
+ assign idxs_T_1795_en = 1'h1;
+ assign idxs_T_1795_clk = clk;
+ assign idxs_T_1795_data = idxs[idxs_T_1795_addr];
+ assign idxs_T_1798_addr = 6'h21;
+ assign idxs_T_1798_en = 1'h1;
+ assign idxs_T_1798_clk = clk;
+ assign idxs_T_1798_data = idxs[idxs_T_1798_addr];
+ assign idxs_T_1801_addr = 6'h22;
+ assign idxs_T_1801_en = 1'h1;
+ assign idxs_T_1801_clk = clk;
+ assign idxs_T_1801_data = idxs[idxs_T_1801_addr];
+ assign idxs_T_1804_addr = 6'h23;
+ assign idxs_T_1804_en = 1'h1;
+ assign idxs_T_1804_clk = clk;
+ assign idxs_T_1804_data = idxs[idxs_T_1804_addr];
+ assign idxs_T_1807_addr = 6'h24;
+ assign idxs_T_1807_en = 1'h1;
+ assign idxs_T_1807_clk = clk;
+ assign idxs_T_1807_data = idxs[idxs_T_1807_addr];
+ assign idxs_T_1810_addr = 6'h25;
+ assign idxs_T_1810_en = 1'h1;
+ assign idxs_T_1810_clk = clk;
+ assign idxs_T_1810_data = idxs[idxs_T_1810_addr];
+ assign idxs_T_1813_addr = 6'h26;
+ assign idxs_T_1813_en = 1'h1;
+ assign idxs_T_1813_clk = clk;
+ assign idxs_T_1813_data = idxs[idxs_T_1813_addr];
+ assign idxs_T_1816_addr = 6'h27;
+ assign idxs_T_1816_en = 1'h1;
+ assign idxs_T_1816_clk = clk;
+ assign idxs_T_1816_data = idxs[idxs_T_1816_addr];
+ assign idxs_T_1819_addr = 6'h28;
+ assign idxs_T_1819_en = 1'h1;
+ assign idxs_T_1819_clk = clk;
+ assign idxs_T_1819_data = idxs[idxs_T_1819_addr];
+ assign idxs_T_1822_addr = 6'h29;
+ assign idxs_T_1822_en = 1'h1;
+ assign idxs_T_1822_clk = clk;
+ assign idxs_T_1822_data = idxs[idxs_T_1822_addr];
+ assign idxs_T_1825_addr = 6'h2a;
+ assign idxs_T_1825_en = 1'h1;
+ assign idxs_T_1825_clk = clk;
+ assign idxs_T_1825_data = idxs[idxs_T_1825_addr];
+ assign idxs_T_1828_addr = 6'h2b;
+ assign idxs_T_1828_en = 1'h1;
+ assign idxs_T_1828_clk = clk;
+ assign idxs_T_1828_data = idxs[idxs_T_1828_addr];
+ assign idxs_T_1831_addr = 6'h2c;
+ assign idxs_T_1831_en = 1'h1;
+ assign idxs_T_1831_clk = clk;
+ assign idxs_T_1831_data = idxs[idxs_T_1831_addr];
+ assign idxs_T_1834_addr = 6'h2d;
+ assign idxs_T_1834_en = 1'h1;
+ assign idxs_T_1834_clk = clk;
+ assign idxs_T_1834_data = idxs[idxs_T_1834_addr];
+ assign idxs_T_1837_addr = 6'h2e;
+ assign idxs_T_1837_en = 1'h1;
+ assign idxs_T_1837_clk = clk;
+ assign idxs_T_1837_data = idxs[idxs_T_1837_addr];
+ assign idxs_T_1840_addr = 6'h2f;
+ assign idxs_T_1840_en = 1'h1;
+ assign idxs_T_1840_clk = clk;
+ assign idxs_T_1840_data = idxs[idxs_T_1840_addr];
+ assign idxs_T_1843_addr = 6'h30;
+ assign idxs_T_1843_en = 1'h1;
+ assign idxs_T_1843_clk = clk;
+ assign idxs_T_1843_data = idxs[idxs_T_1843_addr];
+ assign idxs_T_1846_addr = 6'h31;
+ assign idxs_T_1846_en = 1'h1;
+ assign idxs_T_1846_clk = clk;
+ assign idxs_T_1846_data = idxs[idxs_T_1846_addr];
+ assign idxs_T_1849_addr = 6'h32;
+ assign idxs_T_1849_en = 1'h1;
+ assign idxs_T_1849_clk = clk;
+ assign idxs_T_1849_data = idxs[idxs_T_1849_addr];
+ assign idxs_T_1852_addr = 6'h33;
+ assign idxs_T_1852_en = 1'h1;
+ assign idxs_T_1852_clk = clk;
+ assign idxs_T_1852_data = idxs[idxs_T_1852_addr];
+ assign idxs_T_1855_addr = 6'h34;
+ assign idxs_T_1855_en = 1'h1;
+ assign idxs_T_1855_clk = clk;
+ assign idxs_T_1855_data = idxs[idxs_T_1855_addr];
+ assign idxs_T_1858_addr = 6'h35;
+ assign idxs_T_1858_en = 1'h1;
+ assign idxs_T_1858_clk = clk;
+ assign idxs_T_1858_data = idxs[idxs_T_1858_addr];
+ assign idxs_T_1861_addr = 6'h36;
+ assign idxs_T_1861_en = 1'h1;
+ assign idxs_T_1861_clk = clk;
+ assign idxs_T_1861_data = idxs[idxs_T_1861_addr];
+ assign idxs_T_1864_addr = 6'h37;
+ assign idxs_T_1864_en = 1'h1;
+ assign idxs_T_1864_clk = clk;
+ assign idxs_T_1864_data = idxs[idxs_T_1864_addr];
+ assign idxs_T_1867_addr = 6'h38;
+ assign idxs_T_1867_en = 1'h1;
+ assign idxs_T_1867_clk = clk;
+ assign idxs_T_1867_data = idxs[idxs_T_1867_addr];
+ assign idxs_T_1870_addr = 6'h39;
+ assign idxs_T_1870_en = 1'h1;
+ assign idxs_T_1870_clk = clk;
+ assign idxs_T_1870_data = idxs[idxs_T_1870_addr];
+ assign idxs_T_1873_addr = 6'h3a;
+ assign idxs_T_1873_en = 1'h1;
+ assign idxs_T_1873_clk = clk;
+ assign idxs_T_1873_data = idxs[idxs_T_1873_addr];
+ assign idxs_T_1876_addr = 6'h3b;
+ assign idxs_T_1876_en = 1'h1;
+ assign idxs_T_1876_clk = clk;
+ assign idxs_T_1876_data = idxs[idxs_T_1876_addr];
+ assign idxs_T_1879_addr = 6'h3c;
+ assign idxs_T_1879_en = 1'h1;
+ assign idxs_T_1879_clk = clk;
+ assign idxs_T_1879_data = idxs[idxs_T_1879_addr];
+ assign idxs_T_1882_addr = 6'h3d;
+ assign idxs_T_1882_en = 1'h1;
+ assign idxs_T_1882_clk = clk;
+ assign idxs_T_1882_data = idxs[idxs_T_1882_addr];
+ assign idxs_T_2360_addr = 1'h0;
+ assign idxs_T_2360_en = 1'h1;
+ assign idxs_T_2360_clk = clk;
+ assign idxs_T_2360_data = idxs[idxs_T_2360_addr];
+ assign idxs_T_2363_addr = 1'h1;
+ assign idxs_T_2363_en = 1'h1;
+ assign idxs_T_2363_clk = clk;
+ assign idxs_T_2363_data = idxs[idxs_T_2363_addr];
+ assign idxs_T_2366_addr = 2'h2;
+ assign idxs_T_2366_en = 1'h1;
+ assign idxs_T_2366_clk = clk;
+ assign idxs_T_2366_data = idxs[idxs_T_2366_addr];
+ assign idxs_T_2369_addr = 2'h3;
+ assign idxs_T_2369_en = 1'h1;
+ assign idxs_T_2369_clk = clk;
+ assign idxs_T_2369_data = idxs[idxs_T_2369_addr];
+ assign idxs_T_2372_addr = 3'h4;
+ assign idxs_T_2372_en = 1'h1;
+ assign idxs_T_2372_clk = clk;
+ assign idxs_T_2372_data = idxs[idxs_T_2372_addr];
+ assign idxs_T_2375_addr = 3'h5;
+ assign idxs_T_2375_en = 1'h1;
+ assign idxs_T_2375_clk = clk;
+ assign idxs_T_2375_data = idxs[idxs_T_2375_addr];
+ assign idxs_T_2378_addr = 3'h6;
+ assign idxs_T_2378_en = 1'h1;
+ assign idxs_T_2378_clk = clk;
+ assign idxs_T_2378_data = idxs[idxs_T_2378_addr];
+ assign idxs_T_2381_addr = 3'h7;
+ assign idxs_T_2381_en = 1'h1;
+ assign idxs_T_2381_clk = clk;
+ assign idxs_T_2381_data = idxs[idxs_T_2381_addr];
+ assign idxs_T_2384_addr = 4'h8;
+ assign idxs_T_2384_en = 1'h1;
+ assign idxs_T_2384_clk = clk;
+ assign idxs_T_2384_data = idxs[idxs_T_2384_addr];
+ assign idxs_T_2387_addr = 4'h9;
+ assign idxs_T_2387_en = 1'h1;
+ assign idxs_T_2387_clk = clk;
+ assign idxs_T_2387_data = idxs[idxs_T_2387_addr];
+ assign idxs_T_2390_addr = 4'ha;
+ assign idxs_T_2390_en = 1'h1;
+ assign idxs_T_2390_clk = clk;
+ assign idxs_T_2390_data = idxs[idxs_T_2390_addr];
+ assign idxs_T_2393_addr = 4'hb;
+ assign idxs_T_2393_en = 1'h1;
+ assign idxs_T_2393_clk = clk;
+ assign idxs_T_2393_data = idxs[idxs_T_2393_addr];
+ assign idxs_T_2396_addr = 4'hc;
+ assign idxs_T_2396_en = 1'h1;
+ assign idxs_T_2396_clk = clk;
+ assign idxs_T_2396_data = idxs[idxs_T_2396_addr];
+ assign idxs_T_2399_addr = 4'hd;
+ assign idxs_T_2399_en = 1'h1;
+ assign idxs_T_2399_clk = clk;
+ assign idxs_T_2399_data = idxs[idxs_T_2399_addr];
+ assign idxs_T_2402_addr = 4'he;
+ assign idxs_T_2402_en = 1'h1;
+ assign idxs_T_2402_clk = clk;
+ assign idxs_T_2402_data = idxs[idxs_T_2402_addr];
+ assign idxs_T_2405_addr = 4'hf;
+ assign idxs_T_2405_en = 1'h1;
+ assign idxs_T_2405_clk = clk;
+ assign idxs_T_2405_data = idxs[idxs_T_2405_addr];
+ assign idxs_T_2408_addr = 5'h10;
+ assign idxs_T_2408_en = 1'h1;
+ assign idxs_T_2408_clk = clk;
+ assign idxs_T_2408_data = idxs[idxs_T_2408_addr];
+ assign idxs_T_2411_addr = 5'h11;
+ assign idxs_T_2411_en = 1'h1;
+ assign idxs_T_2411_clk = clk;
+ assign idxs_T_2411_data = idxs[idxs_T_2411_addr];
+ assign idxs_T_2414_addr = 5'h12;
+ assign idxs_T_2414_en = 1'h1;
+ assign idxs_T_2414_clk = clk;
+ assign idxs_T_2414_data = idxs[idxs_T_2414_addr];
+ assign idxs_T_2417_addr = 5'h13;
+ assign idxs_T_2417_en = 1'h1;
+ assign idxs_T_2417_clk = clk;
+ assign idxs_T_2417_data = idxs[idxs_T_2417_addr];
+ assign idxs_T_2420_addr = 5'h14;
+ assign idxs_T_2420_en = 1'h1;
+ assign idxs_T_2420_clk = clk;
+ assign idxs_T_2420_data = idxs[idxs_T_2420_addr];
+ assign idxs_T_2423_addr = 5'h15;
+ assign idxs_T_2423_en = 1'h1;
+ assign idxs_T_2423_clk = clk;
+ assign idxs_T_2423_data = idxs[idxs_T_2423_addr];
+ assign idxs_T_2426_addr = 5'h16;
+ assign idxs_T_2426_en = 1'h1;
+ assign idxs_T_2426_clk = clk;
+ assign idxs_T_2426_data = idxs[idxs_T_2426_addr];
+ assign idxs_T_2429_addr = 5'h17;
+ assign idxs_T_2429_en = 1'h1;
+ assign idxs_T_2429_clk = clk;
+ assign idxs_T_2429_data = idxs[idxs_T_2429_addr];
+ assign idxs_T_2432_addr = 5'h18;
+ assign idxs_T_2432_en = 1'h1;
+ assign idxs_T_2432_clk = clk;
+ assign idxs_T_2432_data = idxs[idxs_T_2432_addr];
+ assign idxs_T_2435_addr = 5'h19;
+ assign idxs_T_2435_en = 1'h1;
+ assign idxs_T_2435_clk = clk;
+ assign idxs_T_2435_data = idxs[idxs_T_2435_addr];
+ assign idxs_T_2438_addr = 5'h1a;
+ assign idxs_T_2438_en = 1'h1;
+ assign idxs_T_2438_clk = clk;
+ assign idxs_T_2438_data = idxs[idxs_T_2438_addr];
+ assign idxs_T_2441_addr = 5'h1b;
+ assign idxs_T_2441_en = 1'h1;
+ assign idxs_T_2441_clk = clk;
+ assign idxs_T_2441_data = idxs[idxs_T_2441_addr];
+ assign idxs_T_2444_addr = 5'h1c;
+ assign idxs_T_2444_en = 1'h1;
+ assign idxs_T_2444_clk = clk;
+ assign idxs_T_2444_data = idxs[idxs_T_2444_addr];
+ assign idxs_T_2447_addr = 5'h1d;
+ assign idxs_T_2447_en = 1'h1;
+ assign idxs_T_2447_clk = clk;
+ assign idxs_T_2447_data = idxs[idxs_T_2447_addr];
+ assign idxs_T_2450_addr = 5'h1e;
+ assign idxs_T_2450_en = 1'h1;
+ assign idxs_T_2450_clk = clk;
+ assign idxs_T_2450_data = idxs[idxs_T_2450_addr];
+ assign idxs_T_2453_addr = 5'h1f;
+ assign idxs_T_2453_en = 1'h1;
+ assign idxs_T_2453_clk = clk;
+ assign idxs_T_2453_data = idxs[idxs_T_2453_addr];
+ assign idxs_T_2456_addr = 6'h20;
+ assign idxs_T_2456_en = 1'h1;
+ assign idxs_T_2456_clk = clk;
+ assign idxs_T_2456_data = idxs[idxs_T_2456_addr];
+ assign idxs_T_2459_addr = 6'h21;
+ assign idxs_T_2459_en = 1'h1;
+ assign idxs_T_2459_clk = clk;
+ assign idxs_T_2459_data = idxs[idxs_T_2459_addr];
+ assign idxs_T_2462_addr = 6'h22;
+ assign idxs_T_2462_en = 1'h1;
+ assign idxs_T_2462_clk = clk;
+ assign idxs_T_2462_data = idxs[idxs_T_2462_addr];
+ assign idxs_T_2465_addr = 6'h23;
+ assign idxs_T_2465_en = 1'h1;
+ assign idxs_T_2465_clk = clk;
+ assign idxs_T_2465_data = idxs[idxs_T_2465_addr];
+ assign idxs_T_2468_addr = 6'h24;
+ assign idxs_T_2468_en = 1'h1;
+ assign idxs_T_2468_clk = clk;
+ assign idxs_T_2468_data = idxs[idxs_T_2468_addr];
+ assign idxs_T_2471_addr = 6'h25;
+ assign idxs_T_2471_en = 1'h1;
+ assign idxs_T_2471_clk = clk;
+ assign idxs_T_2471_data = idxs[idxs_T_2471_addr];
+ assign idxs_T_2474_addr = 6'h26;
+ assign idxs_T_2474_en = 1'h1;
+ assign idxs_T_2474_clk = clk;
+ assign idxs_T_2474_data = idxs[idxs_T_2474_addr];
+ assign idxs_T_2477_addr = 6'h27;
+ assign idxs_T_2477_en = 1'h1;
+ assign idxs_T_2477_clk = clk;
+ assign idxs_T_2477_data = idxs[idxs_T_2477_addr];
+ assign idxs_T_2480_addr = 6'h28;
+ assign idxs_T_2480_en = 1'h1;
+ assign idxs_T_2480_clk = clk;
+ assign idxs_T_2480_data = idxs[idxs_T_2480_addr];
+ assign idxs_T_2483_addr = 6'h29;
+ assign idxs_T_2483_en = 1'h1;
+ assign idxs_T_2483_clk = clk;
+ assign idxs_T_2483_data = idxs[idxs_T_2483_addr];
+ assign idxs_T_2486_addr = 6'h2a;
+ assign idxs_T_2486_en = 1'h1;
+ assign idxs_T_2486_clk = clk;
+ assign idxs_T_2486_data = idxs[idxs_T_2486_addr];
+ assign idxs_T_2489_addr = 6'h2b;
+ assign idxs_T_2489_en = 1'h1;
+ assign idxs_T_2489_clk = clk;
+ assign idxs_T_2489_data = idxs[idxs_T_2489_addr];
+ assign idxs_T_2492_addr = 6'h2c;
+ assign idxs_T_2492_en = 1'h1;
+ assign idxs_T_2492_clk = clk;
+ assign idxs_T_2492_data = idxs[idxs_T_2492_addr];
+ assign idxs_T_2495_addr = 6'h2d;
+ assign idxs_T_2495_en = 1'h1;
+ assign idxs_T_2495_clk = clk;
+ assign idxs_T_2495_data = idxs[idxs_T_2495_addr];
+ assign idxs_T_2498_addr = 6'h2e;
+ assign idxs_T_2498_en = 1'h1;
+ assign idxs_T_2498_clk = clk;
+ assign idxs_T_2498_data = idxs[idxs_T_2498_addr];
+ assign idxs_T_2501_addr = 6'h2f;
+ assign idxs_T_2501_en = 1'h1;
+ assign idxs_T_2501_clk = clk;
+ assign idxs_T_2501_data = idxs[idxs_T_2501_addr];
+ assign idxs_T_2504_addr = 6'h30;
+ assign idxs_T_2504_en = 1'h1;
+ assign idxs_T_2504_clk = clk;
+ assign idxs_T_2504_data = idxs[idxs_T_2504_addr];
+ assign idxs_T_2507_addr = 6'h31;
+ assign idxs_T_2507_en = 1'h1;
+ assign idxs_T_2507_clk = clk;
+ assign idxs_T_2507_data = idxs[idxs_T_2507_addr];
+ assign idxs_T_2510_addr = 6'h32;
+ assign idxs_T_2510_en = 1'h1;
+ assign idxs_T_2510_clk = clk;
+ assign idxs_T_2510_data = idxs[idxs_T_2510_addr];
+ assign idxs_T_2513_addr = 6'h33;
+ assign idxs_T_2513_en = 1'h1;
+ assign idxs_T_2513_clk = clk;
+ assign idxs_T_2513_data = idxs[idxs_T_2513_addr];
+ assign idxs_T_2516_addr = 6'h34;
+ assign idxs_T_2516_en = 1'h1;
+ assign idxs_T_2516_clk = clk;
+ assign idxs_T_2516_data = idxs[idxs_T_2516_addr];
+ assign idxs_T_2519_addr = 6'h35;
+ assign idxs_T_2519_en = 1'h1;
+ assign idxs_T_2519_clk = clk;
+ assign idxs_T_2519_data = idxs[idxs_T_2519_addr];
+ assign idxs_T_2522_addr = 6'h36;
+ assign idxs_T_2522_en = 1'h1;
+ assign idxs_T_2522_clk = clk;
+ assign idxs_T_2522_data = idxs[idxs_T_2522_addr];
+ assign idxs_T_2525_addr = 6'h37;
+ assign idxs_T_2525_en = 1'h1;
+ assign idxs_T_2525_clk = clk;
+ assign idxs_T_2525_data = idxs[idxs_T_2525_addr];
+ assign idxs_T_2528_addr = 6'h38;
+ assign idxs_T_2528_en = 1'h1;
+ assign idxs_T_2528_clk = clk;
+ assign idxs_T_2528_data = idxs[idxs_T_2528_addr];
+ assign idxs_T_2531_addr = 6'h39;
+ assign idxs_T_2531_en = 1'h1;
+ assign idxs_T_2531_clk = clk;
+ assign idxs_T_2531_data = idxs[idxs_T_2531_addr];
+ assign idxs_T_2534_addr = 6'h3a;
+ assign idxs_T_2534_en = 1'h1;
+ assign idxs_T_2534_clk = clk;
+ assign idxs_T_2534_data = idxs[idxs_T_2534_addr];
+ assign idxs_T_2537_addr = 6'h3b;
+ assign idxs_T_2537_en = 1'h1;
+ assign idxs_T_2537_clk = clk;
+ assign idxs_T_2537_data = idxs[idxs_T_2537_addr];
+ assign idxs_T_2540_addr = 6'h3c;
+ assign idxs_T_2540_en = 1'h1;
+ assign idxs_T_2540_clk = clk;
+ assign idxs_T_2540_data = idxs[idxs_T_2540_addr];
+ assign idxs_T_2543_addr = 6'h3d;
+ assign idxs_T_2543_en = 1'h1;
+ assign idxs_T_2543_clk = clk;
+ assign idxs_T_2543_data = idxs[idxs_T_2543_addr];
+ assign idxs_T_3470_data = r_btb_update_bits_pc;
+ assign idxs_T_3470_addr = T_3090;
+ assign idxs_T_3470_mask = r_btb_update_valid ? 1'h1 : 1'h0;
+ assign idxs_T_3470_en = r_btb_update_valid ? 1'h1 : 1'h0;
+ assign idxs_T_3470_clk = clk;
+ assign idxPages_T_590_addr = 1'h0;
+ assign idxPages_T_590_en = 1'h1;
+ assign idxPages_T_590_clk = clk;
+ assign idxPages_T_590_data = idxPages[idxPages_T_590_addr];
+ assign idxPages_T_595_addr = 1'h1;
+ assign idxPages_T_595_en = 1'h1;
+ assign idxPages_T_595_clk = clk;
+ assign idxPages_T_595_data = idxPages[idxPages_T_595_addr];
+ assign idxPages_T_600_addr = 2'h2;
+ assign idxPages_T_600_en = 1'h1;
+ assign idxPages_T_600_clk = clk;
+ assign idxPages_T_600_data = idxPages[idxPages_T_600_addr];
+ assign idxPages_T_605_addr = 2'h3;
+ assign idxPages_T_605_en = 1'h1;
+ assign idxPages_T_605_clk = clk;
+ assign idxPages_T_605_data = idxPages[idxPages_T_605_addr];
+ assign idxPages_T_610_addr = 3'h4;
+ assign idxPages_T_610_en = 1'h1;
+ assign idxPages_T_610_clk = clk;
+ assign idxPages_T_610_data = idxPages[idxPages_T_610_addr];
+ assign idxPages_T_615_addr = 3'h5;
+ assign idxPages_T_615_en = 1'h1;
+ assign idxPages_T_615_clk = clk;
+ assign idxPages_T_615_data = idxPages[idxPages_T_615_addr];
+ assign idxPages_T_620_addr = 3'h6;
+ assign idxPages_T_620_en = 1'h1;
+ assign idxPages_T_620_clk = clk;
+ assign idxPages_T_620_data = idxPages[idxPages_T_620_addr];
+ assign idxPages_T_625_addr = 3'h7;
+ assign idxPages_T_625_en = 1'h1;
+ assign idxPages_T_625_clk = clk;
+ assign idxPages_T_625_data = idxPages[idxPages_T_625_addr];
+ assign idxPages_T_630_addr = 4'h8;
+ assign idxPages_T_630_en = 1'h1;
+ assign idxPages_T_630_clk = clk;
+ assign idxPages_T_630_data = idxPages[idxPages_T_630_addr];
+ assign idxPages_T_635_addr = 4'h9;
+ assign idxPages_T_635_en = 1'h1;
+ assign idxPages_T_635_clk = clk;
+ assign idxPages_T_635_data = idxPages[idxPages_T_635_addr];
+ assign idxPages_T_640_addr = 4'ha;
+ assign idxPages_T_640_en = 1'h1;
+ assign idxPages_T_640_clk = clk;
+ assign idxPages_T_640_data = idxPages[idxPages_T_640_addr];
+ assign idxPages_T_645_addr = 4'hb;
+ assign idxPages_T_645_en = 1'h1;
+ assign idxPages_T_645_clk = clk;
+ assign idxPages_T_645_data = idxPages[idxPages_T_645_addr];
+ assign idxPages_T_650_addr = 4'hc;
+ assign idxPages_T_650_en = 1'h1;
+ assign idxPages_T_650_clk = clk;
+ assign idxPages_T_650_data = idxPages[idxPages_T_650_addr];
+ assign idxPages_T_655_addr = 4'hd;
+ assign idxPages_T_655_en = 1'h1;
+ assign idxPages_T_655_clk = clk;
+ assign idxPages_T_655_data = idxPages[idxPages_T_655_addr];
+ assign idxPages_T_660_addr = 4'he;
+ assign idxPages_T_660_en = 1'h1;
+ assign idxPages_T_660_clk = clk;
+ assign idxPages_T_660_data = idxPages[idxPages_T_660_addr];
+ assign idxPages_T_665_addr = 4'hf;
+ assign idxPages_T_665_en = 1'h1;
+ assign idxPages_T_665_clk = clk;
+ assign idxPages_T_665_data = idxPages[idxPages_T_665_addr];
+ assign idxPages_T_670_addr = 5'h10;
+ assign idxPages_T_670_en = 1'h1;
+ assign idxPages_T_670_clk = clk;
+ assign idxPages_T_670_data = idxPages[idxPages_T_670_addr];
+ assign idxPages_T_675_addr = 5'h11;
+ assign idxPages_T_675_en = 1'h1;
+ assign idxPages_T_675_clk = clk;
+ assign idxPages_T_675_data = idxPages[idxPages_T_675_addr];
+ assign idxPages_T_680_addr = 5'h12;
+ assign idxPages_T_680_en = 1'h1;
+ assign idxPages_T_680_clk = clk;
+ assign idxPages_T_680_data = idxPages[idxPages_T_680_addr];
+ assign idxPages_T_685_addr = 5'h13;
+ assign idxPages_T_685_en = 1'h1;
+ assign idxPages_T_685_clk = clk;
+ assign idxPages_T_685_data = idxPages[idxPages_T_685_addr];
+ assign idxPages_T_690_addr = 5'h14;
+ assign idxPages_T_690_en = 1'h1;
+ assign idxPages_T_690_clk = clk;
+ assign idxPages_T_690_data = idxPages[idxPages_T_690_addr];
+ assign idxPages_T_695_addr = 5'h15;
+ assign idxPages_T_695_en = 1'h1;
+ assign idxPages_T_695_clk = clk;
+ assign idxPages_T_695_data = idxPages[idxPages_T_695_addr];
+ assign idxPages_T_700_addr = 5'h16;
+ assign idxPages_T_700_en = 1'h1;
+ assign idxPages_T_700_clk = clk;
+ assign idxPages_T_700_data = idxPages[idxPages_T_700_addr];
+ assign idxPages_T_705_addr = 5'h17;
+ assign idxPages_T_705_en = 1'h1;
+ assign idxPages_T_705_clk = clk;
+ assign idxPages_T_705_data = idxPages[idxPages_T_705_addr];
+ assign idxPages_T_710_addr = 5'h18;
+ assign idxPages_T_710_en = 1'h1;
+ assign idxPages_T_710_clk = clk;
+ assign idxPages_T_710_data = idxPages[idxPages_T_710_addr];
+ assign idxPages_T_715_addr = 5'h19;
+ assign idxPages_T_715_en = 1'h1;
+ assign idxPages_T_715_clk = clk;
+ assign idxPages_T_715_data = idxPages[idxPages_T_715_addr];
+ assign idxPages_T_720_addr = 5'h1a;
+ assign idxPages_T_720_en = 1'h1;
+ assign idxPages_T_720_clk = clk;
+ assign idxPages_T_720_data = idxPages[idxPages_T_720_addr];
+ assign idxPages_T_725_addr = 5'h1b;
+ assign idxPages_T_725_en = 1'h1;
+ assign idxPages_T_725_clk = clk;
+ assign idxPages_T_725_data = idxPages[idxPages_T_725_addr];
+ assign idxPages_T_730_addr = 5'h1c;
+ assign idxPages_T_730_en = 1'h1;
+ assign idxPages_T_730_clk = clk;
+ assign idxPages_T_730_data = idxPages[idxPages_T_730_addr];
+ assign idxPages_T_735_addr = 5'h1d;
+ assign idxPages_T_735_en = 1'h1;
+ assign idxPages_T_735_clk = clk;
+ assign idxPages_T_735_data = idxPages[idxPages_T_735_addr];
+ assign idxPages_T_740_addr = 5'h1e;
+ assign idxPages_T_740_en = 1'h1;
+ assign idxPages_T_740_clk = clk;
+ assign idxPages_T_740_data = idxPages[idxPages_T_740_addr];
+ assign idxPages_T_745_addr = 5'h1f;
+ assign idxPages_T_745_en = 1'h1;
+ assign idxPages_T_745_clk = clk;
+ assign idxPages_T_745_data = idxPages[idxPages_T_745_addr];
+ assign idxPages_T_750_addr = 6'h20;
+ assign idxPages_T_750_en = 1'h1;
+ assign idxPages_T_750_clk = clk;
+ assign idxPages_T_750_data = idxPages[idxPages_T_750_addr];
+ assign idxPages_T_755_addr = 6'h21;
+ assign idxPages_T_755_en = 1'h1;
+ assign idxPages_T_755_clk = clk;
+ assign idxPages_T_755_data = idxPages[idxPages_T_755_addr];
+ assign idxPages_T_760_addr = 6'h22;
+ assign idxPages_T_760_en = 1'h1;
+ assign idxPages_T_760_clk = clk;
+ assign idxPages_T_760_data = idxPages[idxPages_T_760_addr];
+ assign idxPages_T_765_addr = 6'h23;
+ assign idxPages_T_765_en = 1'h1;
+ assign idxPages_T_765_clk = clk;
+ assign idxPages_T_765_data = idxPages[idxPages_T_765_addr];
+ assign idxPages_T_770_addr = 6'h24;
+ assign idxPages_T_770_en = 1'h1;
+ assign idxPages_T_770_clk = clk;
+ assign idxPages_T_770_data = idxPages[idxPages_T_770_addr];
+ assign idxPages_T_775_addr = 6'h25;
+ assign idxPages_T_775_en = 1'h1;
+ assign idxPages_T_775_clk = clk;
+ assign idxPages_T_775_data = idxPages[idxPages_T_775_addr];
+ assign idxPages_T_780_addr = 6'h26;
+ assign idxPages_T_780_en = 1'h1;
+ assign idxPages_T_780_clk = clk;
+ assign idxPages_T_780_data = idxPages[idxPages_T_780_addr];
+ assign idxPages_T_785_addr = 6'h27;
+ assign idxPages_T_785_en = 1'h1;
+ assign idxPages_T_785_clk = clk;
+ assign idxPages_T_785_data = idxPages[idxPages_T_785_addr];
+ assign idxPages_T_790_addr = 6'h28;
+ assign idxPages_T_790_en = 1'h1;
+ assign idxPages_T_790_clk = clk;
+ assign idxPages_T_790_data = idxPages[idxPages_T_790_addr];
+ assign idxPages_T_795_addr = 6'h29;
+ assign idxPages_T_795_en = 1'h1;
+ assign idxPages_T_795_clk = clk;
+ assign idxPages_T_795_data = idxPages[idxPages_T_795_addr];
+ assign idxPages_T_800_addr = 6'h2a;
+ assign idxPages_T_800_en = 1'h1;
+ assign idxPages_T_800_clk = clk;
+ assign idxPages_T_800_data = idxPages[idxPages_T_800_addr];
+ assign idxPages_T_805_addr = 6'h2b;
+ assign idxPages_T_805_en = 1'h1;
+ assign idxPages_T_805_clk = clk;
+ assign idxPages_T_805_data = idxPages[idxPages_T_805_addr];
+ assign idxPages_T_810_addr = 6'h2c;
+ assign idxPages_T_810_en = 1'h1;
+ assign idxPages_T_810_clk = clk;
+ assign idxPages_T_810_data = idxPages[idxPages_T_810_addr];
+ assign idxPages_T_815_addr = 6'h2d;
+ assign idxPages_T_815_en = 1'h1;
+ assign idxPages_T_815_clk = clk;
+ assign idxPages_T_815_data = idxPages[idxPages_T_815_addr];
+ assign idxPages_T_820_addr = 6'h2e;
+ assign idxPages_T_820_en = 1'h1;
+ assign idxPages_T_820_clk = clk;
+ assign idxPages_T_820_data = idxPages[idxPages_T_820_addr];
+ assign idxPages_T_825_addr = 6'h2f;
+ assign idxPages_T_825_en = 1'h1;
+ assign idxPages_T_825_clk = clk;
+ assign idxPages_T_825_data = idxPages[idxPages_T_825_addr];
+ assign idxPages_T_830_addr = 6'h30;
+ assign idxPages_T_830_en = 1'h1;
+ assign idxPages_T_830_clk = clk;
+ assign idxPages_T_830_data = idxPages[idxPages_T_830_addr];
+ assign idxPages_T_835_addr = 6'h31;
+ assign idxPages_T_835_en = 1'h1;
+ assign idxPages_T_835_clk = clk;
+ assign idxPages_T_835_data = idxPages[idxPages_T_835_addr];
+ assign idxPages_T_840_addr = 6'h32;
+ assign idxPages_T_840_en = 1'h1;
+ assign idxPages_T_840_clk = clk;
+ assign idxPages_T_840_data = idxPages[idxPages_T_840_addr];
+ assign idxPages_T_845_addr = 6'h33;
+ assign idxPages_T_845_en = 1'h1;
+ assign idxPages_T_845_clk = clk;
+ assign idxPages_T_845_data = idxPages[idxPages_T_845_addr];
+ assign idxPages_T_850_addr = 6'h34;
+ assign idxPages_T_850_en = 1'h1;
+ assign idxPages_T_850_clk = clk;
+ assign idxPages_T_850_data = idxPages[idxPages_T_850_addr];
+ assign idxPages_T_855_addr = 6'h35;
+ assign idxPages_T_855_en = 1'h1;
+ assign idxPages_T_855_clk = clk;
+ assign idxPages_T_855_data = idxPages[idxPages_T_855_addr];
+ assign idxPages_T_860_addr = 6'h36;
+ assign idxPages_T_860_en = 1'h1;
+ assign idxPages_T_860_clk = clk;
+ assign idxPages_T_860_data = idxPages[idxPages_T_860_addr];
+ assign idxPages_T_865_addr = 6'h37;
+ assign idxPages_T_865_en = 1'h1;
+ assign idxPages_T_865_clk = clk;
+ assign idxPages_T_865_data = idxPages[idxPages_T_865_addr];
+ assign idxPages_T_870_addr = 6'h38;
+ assign idxPages_T_870_en = 1'h1;
+ assign idxPages_T_870_clk = clk;
+ assign idxPages_T_870_data = idxPages[idxPages_T_870_addr];
+ assign idxPages_T_875_addr = 6'h39;
+ assign idxPages_T_875_en = 1'h1;
+ assign idxPages_T_875_clk = clk;
+ assign idxPages_T_875_data = idxPages[idxPages_T_875_addr];
+ assign idxPages_T_880_addr = 6'h3a;
+ assign idxPages_T_880_en = 1'h1;
+ assign idxPages_T_880_clk = clk;
+ assign idxPages_T_880_data = idxPages[idxPages_T_880_addr];
+ assign idxPages_T_885_addr = 6'h3b;
+ assign idxPages_T_885_en = 1'h1;
+ assign idxPages_T_885_clk = clk;
+ assign idxPages_T_885_data = idxPages[idxPages_T_885_addr];
+ assign idxPages_T_890_addr = 6'h3c;
+ assign idxPages_T_890_en = 1'h1;
+ assign idxPages_T_890_clk = clk;
+ assign idxPages_T_890_data = idxPages[idxPages_T_890_addr];
+ assign idxPages_T_895_addr = 6'h3d;
+ assign idxPages_T_895_en = 1'h1;
+ assign idxPages_T_895_clk = clk;
+ assign idxPages_T_895_data = idxPages[idxPages_T_895_addr];
+ assign idxPages_T_3472_data = idxPageUpdate;
+ assign idxPages_T_3472_addr = T_3090;
+ assign idxPages_T_3472_mask = r_btb_update_valid ? 1'h1 : 1'h0;
+ assign idxPages_T_3472_en = r_btb_update_valid ? 1'h1 : 1'h0;
+ assign idxPages_T_3472_clk = clk;
+ assign tgts_T_3870_addr = 1'h0;
+ assign tgts_T_3870_en = 1'h1;
+ assign tgts_T_3870_clk = clk;
+ assign tgts_T_3870_data = tgts[tgts_T_3870_addr];
+ assign tgts_T_3872_addr = 1'h1;
+ assign tgts_T_3872_en = 1'h1;
+ assign tgts_T_3872_clk = clk;
+ assign tgts_T_3872_data = tgts[tgts_T_3872_addr];
+ assign tgts_T_3874_addr = 2'h2;
+ assign tgts_T_3874_en = 1'h1;
+ assign tgts_T_3874_clk = clk;
+ assign tgts_T_3874_data = tgts[tgts_T_3874_addr];
+ assign tgts_T_3876_addr = 2'h3;
+ assign tgts_T_3876_en = 1'h1;
+ assign tgts_T_3876_clk = clk;
+ assign tgts_T_3876_data = tgts[tgts_T_3876_addr];
+ assign tgts_T_3878_addr = 3'h4;
+ assign tgts_T_3878_en = 1'h1;
+ assign tgts_T_3878_clk = clk;
+ assign tgts_T_3878_data = tgts[tgts_T_3878_addr];
+ assign tgts_T_3880_addr = 3'h5;
+ assign tgts_T_3880_en = 1'h1;
+ assign tgts_T_3880_clk = clk;
+ assign tgts_T_3880_data = tgts[tgts_T_3880_addr];
+ assign tgts_T_3882_addr = 3'h6;
+ assign tgts_T_3882_en = 1'h1;
+ assign tgts_T_3882_clk = clk;
+ assign tgts_T_3882_data = tgts[tgts_T_3882_addr];
+ assign tgts_T_3884_addr = 3'h7;
+ assign tgts_T_3884_en = 1'h1;
+ assign tgts_T_3884_clk = clk;
+ assign tgts_T_3884_data = tgts[tgts_T_3884_addr];
+ assign tgts_T_3886_addr = 4'h8;
+ assign tgts_T_3886_en = 1'h1;
+ assign tgts_T_3886_clk = clk;
+ assign tgts_T_3886_data = tgts[tgts_T_3886_addr];
+ assign tgts_T_3888_addr = 4'h9;
+ assign tgts_T_3888_en = 1'h1;
+ assign tgts_T_3888_clk = clk;
+ assign tgts_T_3888_data = tgts[tgts_T_3888_addr];
+ assign tgts_T_3890_addr = 4'ha;
+ assign tgts_T_3890_en = 1'h1;
+ assign tgts_T_3890_clk = clk;
+ assign tgts_T_3890_data = tgts[tgts_T_3890_addr];
+ assign tgts_T_3892_addr = 4'hb;
+ assign tgts_T_3892_en = 1'h1;
+ assign tgts_T_3892_clk = clk;
+ assign tgts_T_3892_data = tgts[tgts_T_3892_addr];
+ assign tgts_T_3894_addr = 4'hc;
+ assign tgts_T_3894_en = 1'h1;
+ assign tgts_T_3894_clk = clk;
+ assign tgts_T_3894_data = tgts[tgts_T_3894_addr];
+ assign tgts_T_3896_addr = 4'hd;
+ assign tgts_T_3896_en = 1'h1;
+ assign tgts_T_3896_clk = clk;
+ assign tgts_T_3896_data = tgts[tgts_T_3896_addr];
+ assign tgts_T_3898_addr = 4'he;
+ assign tgts_T_3898_en = 1'h1;
+ assign tgts_T_3898_clk = clk;
+ assign tgts_T_3898_data = tgts[tgts_T_3898_addr];
+ assign tgts_T_3900_addr = 4'hf;
+ assign tgts_T_3900_en = 1'h1;
+ assign tgts_T_3900_clk = clk;
+ assign tgts_T_3900_data = tgts[tgts_T_3900_addr];
+ assign tgts_T_3902_addr = 5'h10;
+ assign tgts_T_3902_en = 1'h1;
+ assign tgts_T_3902_clk = clk;
+ assign tgts_T_3902_data = tgts[tgts_T_3902_addr];
+ assign tgts_T_3904_addr = 5'h11;
+ assign tgts_T_3904_en = 1'h1;
+ assign tgts_T_3904_clk = clk;
+ assign tgts_T_3904_data = tgts[tgts_T_3904_addr];
+ assign tgts_T_3906_addr = 5'h12;
+ assign tgts_T_3906_en = 1'h1;
+ assign tgts_T_3906_clk = clk;
+ assign tgts_T_3906_data = tgts[tgts_T_3906_addr];
+ assign tgts_T_3908_addr = 5'h13;
+ assign tgts_T_3908_en = 1'h1;
+ assign tgts_T_3908_clk = clk;
+ assign tgts_T_3908_data = tgts[tgts_T_3908_addr];
+ assign tgts_T_3910_addr = 5'h14;
+ assign tgts_T_3910_en = 1'h1;
+ assign tgts_T_3910_clk = clk;
+ assign tgts_T_3910_data = tgts[tgts_T_3910_addr];
+ assign tgts_T_3912_addr = 5'h15;
+ assign tgts_T_3912_en = 1'h1;
+ assign tgts_T_3912_clk = clk;
+ assign tgts_T_3912_data = tgts[tgts_T_3912_addr];
+ assign tgts_T_3914_addr = 5'h16;
+ assign tgts_T_3914_en = 1'h1;
+ assign tgts_T_3914_clk = clk;
+ assign tgts_T_3914_data = tgts[tgts_T_3914_addr];
+ assign tgts_T_3916_addr = 5'h17;
+ assign tgts_T_3916_en = 1'h1;
+ assign tgts_T_3916_clk = clk;
+ assign tgts_T_3916_data = tgts[tgts_T_3916_addr];
+ assign tgts_T_3918_addr = 5'h18;
+ assign tgts_T_3918_en = 1'h1;
+ assign tgts_T_3918_clk = clk;
+ assign tgts_T_3918_data = tgts[tgts_T_3918_addr];
+ assign tgts_T_3920_addr = 5'h19;
+ assign tgts_T_3920_en = 1'h1;
+ assign tgts_T_3920_clk = clk;
+ assign tgts_T_3920_data = tgts[tgts_T_3920_addr];
+ assign tgts_T_3922_addr = 5'h1a;
+ assign tgts_T_3922_en = 1'h1;
+ assign tgts_T_3922_clk = clk;
+ assign tgts_T_3922_data = tgts[tgts_T_3922_addr];
+ assign tgts_T_3924_addr = 5'h1b;
+ assign tgts_T_3924_en = 1'h1;
+ assign tgts_T_3924_clk = clk;
+ assign tgts_T_3924_data = tgts[tgts_T_3924_addr];
+ assign tgts_T_3926_addr = 5'h1c;
+ assign tgts_T_3926_en = 1'h1;
+ assign tgts_T_3926_clk = clk;
+ assign tgts_T_3926_data = tgts[tgts_T_3926_addr];
+ assign tgts_T_3928_addr = 5'h1d;
+ assign tgts_T_3928_en = 1'h1;
+ assign tgts_T_3928_clk = clk;
+ assign tgts_T_3928_data = tgts[tgts_T_3928_addr];
+ assign tgts_T_3930_addr = 5'h1e;
+ assign tgts_T_3930_en = 1'h1;
+ assign tgts_T_3930_clk = clk;
+ assign tgts_T_3930_data = tgts[tgts_T_3930_addr];
+ assign tgts_T_3932_addr = 5'h1f;
+ assign tgts_T_3932_en = 1'h1;
+ assign tgts_T_3932_clk = clk;
+ assign tgts_T_3932_data = tgts[tgts_T_3932_addr];
+ assign tgts_T_3934_addr = 6'h20;
+ assign tgts_T_3934_en = 1'h1;
+ assign tgts_T_3934_clk = clk;
+ assign tgts_T_3934_data = tgts[tgts_T_3934_addr];
+ assign tgts_T_3936_addr = 6'h21;
+ assign tgts_T_3936_en = 1'h1;
+ assign tgts_T_3936_clk = clk;
+ assign tgts_T_3936_data = tgts[tgts_T_3936_addr];
+ assign tgts_T_3938_addr = 6'h22;
+ assign tgts_T_3938_en = 1'h1;
+ assign tgts_T_3938_clk = clk;
+ assign tgts_T_3938_data = tgts[tgts_T_3938_addr];
+ assign tgts_T_3940_addr = 6'h23;
+ assign tgts_T_3940_en = 1'h1;
+ assign tgts_T_3940_clk = clk;
+ assign tgts_T_3940_data = tgts[tgts_T_3940_addr];
+ assign tgts_T_3942_addr = 6'h24;
+ assign tgts_T_3942_en = 1'h1;
+ assign tgts_T_3942_clk = clk;
+ assign tgts_T_3942_data = tgts[tgts_T_3942_addr];
+ assign tgts_T_3944_addr = 6'h25;
+ assign tgts_T_3944_en = 1'h1;
+ assign tgts_T_3944_clk = clk;
+ assign tgts_T_3944_data = tgts[tgts_T_3944_addr];
+ assign tgts_T_3946_addr = 6'h26;
+ assign tgts_T_3946_en = 1'h1;
+ assign tgts_T_3946_clk = clk;
+ assign tgts_T_3946_data = tgts[tgts_T_3946_addr];
+ assign tgts_T_3948_addr = 6'h27;
+ assign tgts_T_3948_en = 1'h1;
+ assign tgts_T_3948_clk = clk;
+ assign tgts_T_3948_data = tgts[tgts_T_3948_addr];
+ assign tgts_T_3950_addr = 6'h28;
+ assign tgts_T_3950_en = 1'h1;
+ assign tgts_T_3950_clk = clk;
+ assign tgts_T_3950_data = tgts[tgts_T_3950_addr];
+ assign tgts_T_3952_addr = 6'h29;
+ assign tgts_T_3952_en = 1'h1;
+ assign tgts_T_3952_clk = clk;
+ assign tgts_T_3952_data = tgts[tgts_T_3952_addr];
+ assign tgts_T_3954_addr = 6'h2a;
+ assign tgts_T_3954_en = 1'h1;
+ assign tgts_T_3954_clk = clk;
+ assign tgts_T_3954_data = tgts[tgts_T_3954_addr];
+ assign tgts_T_3956_addr = 6'h2b;
+ assign tgts_T_3956_en = 1'h1;
+ assign tgts_T_3956_clk = clk;
+ assign tgts_T_3956_data = tgts[tgts_T_3956_addr];
+ assign tgts_T_3958_addr = 6'h2c;
+ assign tgts_T_3958_en = 1'h1;
+ assign tgts_T_3958_clk = clk;
+ assign tgts_T_3958_data = tgts[tgts_T_3958_addr];
+ assign tgts_T_3960_addr = 6'h2d;
+ assign tgts_T_3960_en = 1'h1;
+ assign tgts_T_3960_clk = clk;
+ assign tgts_T_3960_data = tgts[tgts_T_3960_addr];
+ assign tgts_T_3962_addr = 6'h2e;
+ assign tgts_T_3962_en = 1'h1;
+ assign tgts_T_3962_clk = clk;
+ assign tgts_T_3962_data = tgts[tgts_T_3962_addr];
+ assign tgts_T_3964_addr = 6'h2f;
+ assign tgts_T_3964_en = 1'h1;
+ assign tgts_T_3964_clk = clk;
+ assign tgts_T_3964_data = tgts[tgts_T_3964_addr];
+ assign tgts_T_3966_addr = 6'h30;
+ assign tgts_T_3966_en = 1'h1;
+ assign tgts_T_3966_clk = clk;
+ assign tgts_T_3966_data = tgts[tgts_T_3966_addr];
+ assign tgts_T_3968_addr = 6'h31;
+ assign tgts_T_3968_en = 1'h1;
+ assign tgts_T_3968_clk = clk;
+ assign tgts_T_3968_data = tgts[tgts_T_3968_addr];
+ assign tgts_T_3970_addr = 6'h32;
+ assign tgts_T_3970_en = 1'h1;
+ assign tgts_T_3970_clk = clk;
+ assign tgts_T_3970_data = tgts[tgts_T_3970_addr];
+ assign tgts_T_3972_addr = 6'h33;
+ assign tgts_T_3972_en = 1'h1;
+ assign tgts_T_3972_clk = clk;
+ assign tgts_T_3972_data = tgts[tgts_T_3972_addr];
+ assign tgts_T_3974_addr = 6'h34;
+ assign tgts_T_3974_en = 1'h1;
+ assign tgts_T_3974_clk = clk;
+ assign tgts_T_3974_data = tgts[tgts_T_3974_addr];
+ assign tgts_T_3976_addr = 6'h35;
+ assign tgts_T_3976_en = 1'h1;
+ assign tgts_T_3976_clk = clk;
+ assign tgts_T_3976_data = tgts[tgts_T_3976_addr];
+ assign tgts_T_3978_addr = 6'h36;
+ assign tgts_T_3978_en = 1'h1;
+ assign tgts_T_3978_clk = clk;
+ assign tgts_T_3978_data = tgts[tgts_T_3978_addr];
+ assign tgts_T_3980_addr = 6'h37;
+ assign tgts_T_3980_en = 1'h1;
+ assign tgts_T_3980_clk = clk;
+ assign tgts_T_3980_data = tgts[tgts_T_3980_addr];
+ assign tgts_T_3982_addr = 6'h38;
+ assign tgts_T_3982_en = 1'h1;
+ assign tgts_T_3982_clk = clk;
+ assign tgts_T_3982_data = tgts[tgts_T_3982_addr];
+ assign tgts_T_3984_addr = 6'h39;
+ assign tgts_T_3984_en = 1'h1;
+ assign tgts_T_3984_clk = clk;
+ assign tgts_T_3984_data = tgts[tgts_T_3984_addr];
+ assign tgts_T_3986_addr = 6'h3a;
+ assign tgts_T_3986_en = 1'h1;
+ assign tgts_T_3986_clk = clk;
+ assign tgts_T_3986_data = tgts[tgts_T_3986_addr];
+ assign tgts_T_3988_addr = 6'h3b;
+ assign tgts_T_3988_en = 1'h1;
+ assign tgts_T_3988_clk = clk;
+ assign tgts_T_3988_data = tgts[tgts_T_3988_addr];
+ assign tgts_T_3990_addr = 6'h3c;
+ assign tgts_T_3990_en = 1'h1;
+ assign tgts_T_3990_clk = clk;
+ assign tgts_T_3990_data = tgts[tgts_T_3990_addr];
+ assign tgts_T_3992_addr = 6'h3d;
+ assign tgts_T_3992_en = 1'h1;
+ assign tgts_T_3992_clk = clk;
+ assign tgts_T_3992_data = tgts[tgts_T_3992_addr];
+ assign tgts_T_3471_data = io_req_bits_addr;
+ assign tgts_T_3471_addr = T_3090;
+ assign tgts_T_3471_mask = r_btb_update_valid ? 1'h1 : 1'h0;
+ assign tgts_T_3471_en = r_btb_update_valid ? 1'h1 : 1'h0;
+ assign tgts_T_3471_clk = clk;
+ assign tgtPages_T_900_addr = 1'h0;
+ assign tgtPages_T_900_en = 1'h1;
+ assign tgtPages_T_900_clk = clk;
+ assign tgtPages_T_900_data = tgtPages[tgtPages_T_900_addr];
+ assign tgtPages_T_905_addr = 1'h1;
+ assign tgtPages_T_905_en = 1'h1;
+ assign tgtPages_T_905_clk = clk;
+ assign tgtPages_T_905_data = tgtPages[tgtPages_T_905_addr];
+ assign tgtPages_T_910_addr = 2'h2;
+ assign tgtPages_T_910_en = 1'h1;
+ assign tgtPages_T_910_clk = clk;
+ assign tgtPages_T_910_data = tgtPages[tgtPages_T_910_addr];
+ assign tgtPages_T_915_addr = 2'h3;
+ assign tgtPages_T_915_en = 1'h1;
+ assign tgtPages_T_915_clk = clk;
+ assign tgtPages_T_915_data = tgtPages[tgtPages_T_915_addr];
+ assign tgtPages_T_920_addr = 3'h4;
+ assign tgtPages_T_920_en = 1'h1;
+ assign tgtPages_T_920_clk = clk;
+ assign tgtPages_T_920_data = tgtPages[tgtPages_T_920_addr];
+ assign tgtPages_T_925_addr = 3'h5;
+ assign tgtPages_T_925_en = 1'h1;
+ assign tgtPages_T_925_clk = clk;
+ assign tgtPages_T_925_data = tgtPages[tgtPages_T_925_addr];
+ assign tgtPages_T_930_addr = 3'h6;
+ assign tgtPages_T_930_en = 1'h1;
+ assign tgtPages_T_930_clk = clk;
+ assign tgtPages_T_930_data = tgtPages[tgtPages_T_930_addr];
+ assign tgtPages_T_935_addr = 3'h7;
+ assign tgtPages_T_935_en = 1'h1;
+ assign tgtPages_T_935_clk = clk;
+ assign tgtPages_T_935_data = tgtPages[tgtPages_T_935_addr];
+ assign tgtPages_T_940_addr = 4'h8;
+ assign tgtPages_T_940_en = 1'h1;
+ assign tgtPages_T_940_clk = clk;
+ assign tgtPages_T_940_data = tgtPages[tgtPages_T_940_addr];
+ assign tgtPages_T_945_addr = 4'h9;
+ assign tgtPages_T_945_en = 1'h1;
+ assign tgtPages_T_945_clk = clk;
+ assign tgtPages_T_945_data = tgtPages[tgtPages_T_945_addr];
+ assign tgtPages_T_950_addr = 4'ha;
+ assign tgtPages_T_950_en = 1'h1;
+ assign tgtPages_T_950_clk = clk;
+ assign tgtPages_T_950_data = tgtPages[tgtPages_T_950_addr];
+ assign tgtPages_T_955_addr = 4'hb;
+ assign tgtPages_T_955_en = 1'h1;
+ assign tgtPages_T_955_clk = clk;
+ assign tgtPages_T_955_data = tgtPages[tgtPages_T_955_addr];
+ assign tgtPages_T_960_addr = 4'hc;
+ assign tgtPages_T_960_en = 1'h1;
+ assign tgtPages_T_960_clk = clk;
+ assign tgtPages_T_960_data = tgtPages[tgtPages_T_960_addr];
+ assign tgtPages_T_965_addr = 4'hd;
+ assign tgtPages_T_965_en = 1'h1;
+ assign tgtPages_T_965_clk = clk;
+ assign tgtPages_T_965_data = tgtPages[tgtPages_T_965_addr];
+ assign tgtPages_T_970_addr = 4'he;
+ assign tgtPages_T_970_en = 1'h1;
+ assign tgtPages_T_970_clk = clk;
+ assign tgtPages_T_970_data = tgtPages[tgtPages_T_970_addr];
+ assign tgtPages_T_975_addr = 4'hf;
+ assign tgtPages_T_975_en = 1'h1;
+ assign tgtPages_T_975_clk = clk;
+ assign tgtPages_T_975_data = tgtPages[tgtPages_T_975_addr];
+ assign tgtPages_T_980_addr = 5'h10;
+ assign tgtPages_T_980_en = 1'h1;
+ assign tgtPages_T_980_clk = clk;
+ assign tgtPages_T_980_data = tgtPages[tgtPages_T_980_addr];
+ assign tgtPages_T_985_addr = 5'h11;
+ assign tgtPages_T_985_en = 1'h1;
+ assign tgtPages_T_985_clk = clk;
+ assign tgtPages_T_985_data = tgtPages[tgtPages_T_985_addr];
+ assign tgtPages_T_990_addr = 5'h12;
+ assign tgtPages_T_990_en = 1'h1;
+ assign tgtPages_T_990_clk = clk;
+ assign tgtPages_T_990_data = tgtPages[tgtPages_T_990_addr];
+ assign tgtPages_T_995_addr = 5'h13;
+ assign tgtPages_T_995_en = 1'h1;
+ assign tgtPages_T_995_clk = clk;
+ assign tgtPages_T_995_data = tgtPages[tgtPages_T_995_addr];
+ assign tgtPages_T_1000_addr = 5'h14;
+ assign tgtPages_T_1000_en = 1'h1;
+ assign tgtPages_T_1000_clk = clk;
+ assign tgtPages_T_1000_data = tgtPages[tgtPages_T_1000_addr];
+ assign tgtPages_T_1005_addr = 5'h15;
+ assign tgtPages_T_1005_en = 1'h1;
+ assign tgtPages_T_1005_clk = clk;
+ assign tgtPages_T_1005_data = tgtPages[tgtPages_T_1005_addr];
+ assign tgtPages_T_1010_addr = 5'h16;
+ assign tgtPages_T_1010_en = 1'h1;
+ assign tgtPages_T_1010_clk = clk;
+ assign tgtPages_T_1010_data = tgtPages[tgtPages_T_1010_addr];
+ assign tgtPages_T_1015_addr = 5'h17;
+ assign tgtPages_T_1015_en = 1'h1;
+ assign tgtPages_T_1015_clk = clk;
+ assign tgtPages_T_1015_data = tgtPages[tgtPages_T_1015_addr];
+ assign tgtPages_T_1020_addr = 5'h18;
+ assign tgtPages_T_1020_en = 1'h1;
+ assign tgtPages_T_1020_clk = clk;
+ assign tgtPages_T_1020_data = tgtPages[tgtPages_T_1020_addr];
+ assign tgtPages_T_1025_addr = 5'h19;
+ assign tgtPages_T_1025_en = 1'h1;
+ assign tgtPages_T_1025_clk = clk;
+ assign tgtPages_T_1025_data = tgtPages[tgtPages_T_1025_addr];
+ assign tgtPages_T_1030_addr = 5'h1a;
+ assign tgtPages_T_1030_en = 1'h1;
+ assign tgtPages_T_1030_clk = clk;
+ assign tgtPages_T_1030_data = tgtPages[tgtPages_T_1030_addr];
+ assign tgtPages_T_1035_addr = 5'h1b;
+ assign tgtPages_T_1035_en = 1'h1;
+ assign tgtPages_T_1035_clk = clk;
+ assign tgtPages_T_1035_data = tgtPages[tgtPages_T_1035_addr];
+ assign tgtPages_T_1040_addr = 5'h1c;
+ assign tgtPages_T_1040_en = 1'h1;
+ assign tgtPages_T_1040_clk = clk;
+ assign tgtPages_T_1040_data = tgtPages[tgtPages_T_1040_addr];
+ assign tgtPages_T_1045_addr = 5'h1d;
+ assign tgtPages_T_1045_en = 1'h1;
+ assign tgtPages_T_1045_clk = clk;
+ assign tgtPages_T_1045_data = tgtPages[tgtPages_T_1045_addr];
+ assign tgtPages_T_1050_addr = 5'h1e;
+ assign tgtPages_T_1050_en = 1'h1;
+ assign tgtPages_T_1050_clk = clk;
+ assign tgtPages_T_1050_data = tgtPages[tgtPages_T_1050_addr];
+ assign tgtPages_T_1055_addr = 5'h1f;
+ assign tgtPages_T_1055_en = 1'h1;
+ assign tgtPages_T_1055_clk = clk;
+ assign tgtPages_T_1055_data = tgtPages[tgtPages_T_1055_addr];
+ assign tgtPages_T_1060_addr = 6'h20;
+ assign tgtPages_T_1060_en = 1'h1;
+ assign tgtPages_T_1060_clk = clk;
+ assign tgtPages_T_1060_data = tgtPages[tgtPages_T_1060_addr];
+ assign tgtPages_T_1065_addr = 6'h21;
+ assign tgtPages_T_1065_en = 1'h1;
+ assign tgtPages_T_1065_clk = clk;
+ assign tgtPages_T_1065_data = tgtPages[tgtPages_T_1065_addr];
+ assign tgtPages_T_1070_addr = 6'h22;
+ assign tgtPages_T_1070_en = 1'h1;
+ assign tgtPages_T_1070_clk = clk;
+ assign tgtPages_T_1070_data = tgtPages[tgtPages_T_1070_addr];
+ assign tgtPages_T_1075_addr = 6'h23;
+ assign tgtPages_T_1075_en = 1'h1;
+ assign tgtPages_T_1075_clk = clk;
+ assign tgtPages_T_1075_data = tgtPages[tgtPages_T_1075_addr];
+ assign tgtPages_T_1080_addr = 6'h24;
+ assign tgtPages_T_1080_en = 1'h1;
+ assign tgtPages_T_1080_clk = clk;
+ assign tgtPages_T_1080_data = tgtPages[tgtPages_T_1080_addr];
+ assign tgtPages_T_1085_addr = 6'h25;
+ assign tgtPages_T_1085_en = 1'h1;
+ assign tgtPages_T_1085_clk = clk;
+ assign tgtPages_T_1085_data = tgtPages[tgtPages_T_1085_addr];
+ assign tgtPages_T_1090_addr = 6'h26;
+ assign tgtPages_T_1090_en = 1'h1;
+ assign tgtPages_T_1090_clk = clk;
+ assign tgtPages_T_1090_data = tgtPages[tgtPages_T_1090_addr];
+ assign tgtPages_T_1095_addr = 6'h27;
+ assign tgtPages_T_1095_en = 1'h1;
+ assign tgtPages_T_1095_clk = clk;
+ assign tgtPages_T_1095_data = tgtPages[tgtPages_T_1095_addr];
+ assign tgtPages_T_1100_addr = 6'h28;
+ assign tgtPages_T_1100_en = 1'h1;
+ assign tgtPages_T_1100_clk = clk;
+ assign tgtPages_T_1100_data = tgtPages[tgtPages_T_1100_addr];
+ assign tgtPages_T_1105_addr = 6'h29;
+ assign tgtPages_T_1105_en = 1'h1;
+ assign tgtPages_T_1105_clk = clk;
+ assign tgtPages_T_1105_data = tgtPages[tgtPages_T_1105_addr];
+ assign tgtPages_T_1110_addr = 6'h2a;
+ assign tgtPages_T_1110_en = 1'h1;
+ assign tgtPages_T_1110_clk = clk;
+ assign tgtPages_T_1110_data = tgtPages[tgtPages_T_1110_addr];
+ assign tgtPages_T_1115_addr = 6'h2b;
+ assign tgtPages_T_1115_en = 1'h1;
+ assign tgtPages_T_1115_clk = clk;
+ assign tgtPages_T_1115_data = tgtPages[tgtPages_T_1115_addr];
+ assign tgtPages_T_1120_addr = 6'h2c;
+ assign tgtPages_T_1120_en = 1'h1;
+ assign tgtPages_T_1120_clk = clk;
+ assign tgtPages_T_1120_data = tgtPages[tgtPages_T_1120_addr];
+ assign tgtPages_T_1125_addr = 6'h2d;
+ assign tgtPages_T_1125_en = 1'h1;
+ assign tgtPages_T_1125_clk = clk;
+ assign tgtPages_T_1125_data = tgtPages[tgtPages_T_1125_addr];
+ assign tgtPages_T_1130_addr = 6'h2e;
+ assign tgtPages_T_1130_en = 1'h1;
+ assign tgtPages_T_1130_clk = clk;
+ assign tgtPages_T_1130_data = tgtPages[tgtPages_T_1130_addr];
+ assign tgtPages_T_1135_addr = 6'h2f;
+ assign tgtPages_T_1135_en = 1'h1;
+ assign tgtPages_T_1135_clk = clk;
+ assign tgtPages_T_1135_data = tgtPages[tgtPages_T_1135_addr];
+ assign tgtPages_T_1140_addr = 6'h30;
+ assign tgtPages_T_1140_en = 1'h1;
+ assign tgtPages_T_1140_clk = clk;
+ assign tgtPages_T_1140_data = tgtPages[tgtPages_T_1140_addr];
+ assign tgtPages_T_1145_addr = 6'h31;
+ assign tgtPages_T_1145_en = 1'h1;
+ assign tgtPages_T_1145_clk = clk;
+ assign tgtPages_T_1145_data = tgtPages[tgtPages_T_1145_addr];
+ assign tgtPages_T_1150_addr = 6'h32;
+ assign tgtPages_T_1150_en = 1'h1;
+ assign tgtPages_T_1150_clk = clk;
+ assign tgtPages_T_1150_data = tgtPages[tgtPages_T_1150_addr];
+ assign tgtPages_T_1155_addr = 6'h33;
+ assign tgtPages_T_1155_en = 1'h1;
+ assign tgtPages_T_1155_clk = clk;
+ assign tgtPages_T_1155_data = tgtPages[tgtPages_T_1155_addr];
+ assign tgtPages_T_1160_addr = 6'h34;
+ assign tgtPages_T_1160_en = 1'h1;
+ assign tgtPages_T_1160_clk = clk;
+ assign tgtPages_T_1160_data = tgtPages[tgtPages_T_1160_addr];
+ assign tgtPages_T_1165_addr = 6'h35;
+ assign tgtPages_T_1165_en = 1'h1;
+ assign tgtPages_T_1165_clk = clk;
+ assign tgtPages_T_1165_data = tgtPages[tgtPages_T_1165_addr];
+ assign tgtPages_T_1170_addr = 6'h36;
+ assign tgtPages_T_1170_en = 1'h1;
+ assign tgtPages_T_1170_clk = clk;
+ assign tgtPages_T_1170_data = tgtPages[tgtPages_T_1170_addr];
+ assign tgtPages_T_1175_addr = 6'h37;
+ assign tgtPages_T_1175_en = 1'h1;
+ assign tgtPages_T_1175_clk = clk;
+ assign tgtPages_T_1175_data = tgtPages[tgtPages_T_1175_addr];
+ assign tgtPages_T_1180_addr = 6'h38;
+ assign tgtPages_T_1180_en = 1'h1;
+ assign tgtPages_T_1180_clk = clk;
+ assign tgtPages_T_1180_data = tgtPages[tgtPages_T_1180_addr];
+ assign tgtPages_T_1185_addr = 6'h39;
+ assign tgtPages_T_1185_en = 1'h1;
+ assign tgtPages_T_1185_clk = clk;
+ assign tgtPages_T_1185_data = tgtPages[tgtPages_T_1185_addr];
+ assign tgtPages_T_1190_addr = 6'h3a;
+ assign tgtPages_T_1190_en = 1'h1;
+ assign tgtPages_T_1190_clk = clk;
+ assign tgtPages_T_1190_data = tgtPages[tgtPages_T_1190_addr];
+ assign tgtPages_T_1195_addr = 6'h3b;
+ assign tgtPages_T_1195_en = 1'h1;
+ assign tgtPages_T_1195_clk = clk;
+ assign tgtPages_T_1195_data = tgtPages[tgtPages_T_1195_addr];
+ assign tgtPages_T_1200_addr = 6'h3c;
+ assign tgtPages_T_1200_en = 1'h1;
+ assign tgtPages_T_1200_clk = clk;
+ assign tgtPages_T_1200_data = tgtPages[tgtPages_T_1200_addr];
+ assign tgtPages_T_1205_addr = 6'h3d;
+ assign tgtPages_T_1205_en = 1'h1;
+ assign tgtPages_T_1205_clk = clk;
+ assign tgtPages_T_1205_data = tgtPages[tgtPages_T_1205_addr];
+ assign tgtPages_T_3473_data = tgtPageUpdate;
+ assign tgtPages_T_3473_addr = T_3090;
+ assign tgtPages_T_3473_mask = r_btb_update_valid ? 1'h1 : 1'h0;
+ assign tgtPages_T_3473_en = r_btb_update_valid ? 1'h1 : 1'h0;
+ assign tgtPages_T_3473_clk = clk;
+ assign pages_T_1665_addr = 1'h0;
+ assign pages_T_1665_en = 1'h1;
+ assign pages_T_1665_clk = clk;
+ assign pages_T_1665_data = pages[pages_T_1665_addr];
+ assign pages_T_1668_addr = 1'h1;
+ assign pages_T_1668_en = 1'h1;
+ assign pages_T_1668_clk = clk;
+ assign pages_T_1668_data = pages[pages_T_1668_addr];
+ assign pages_T_1671_addr = 2'h2;
+ assign pages_T_1671_en = 1'h1;
+ assign pages_T_1671_clk = clk;
+ assign pages_T_1671_data = pages[pages_T_1671_addr];
+ assign pages_T_1674_addr = 2'h3;
+ assign pages_T_1674_en = 1'h1;
+ assign pages_T_1674_clk = clk;
+ assign pages_T_1674_data = pages[pages_T_1674_addr];
+ assign pages_T_1677_addr = 3'h4;
+ assign pages_T_1677_en = 1'h1;
+ assign pages_T_1677_clk = clk;
+ assign pages_T_1677_data = pages[pages_T_1677_addr];
+ assign pages_T_1680_addr = 3'h5;
+ assign pages_T_1680_en = 1'h1;
+ assign pages_T_1680_clk = clk;
+ assign pages_T_1680_data = pages[pages_T_1680_addr];
+ assign pages_T_2326_addr = 1'h0;
+ assign pages_T_2326_en = 1'h1;
+ assign pages_T_2326_clk = clk;
+ assign pages_T_2326_data = pages[pages_T_2326_addr];
+ assign pages_T_2329_addr = 1'h1;
+ assign pages_T_2329_en = 1'h1;
+ assign pages_T_2329_clk = clk;
+ assign pages_T_2329_data = pages[pages_T_2329_addr];
+ assign pages_T_2332_addr = 2'h2;
+ assign pages_T_2332_en = 1'h1;
+ assign pages_T_2332_clk = clk;
+ assign pages_T_2332_data = pages[pages_T_2332_addr];
+ assign pages_T_2335_addr = 2'h3;
+ assign pages_T_2335_en = 1'h1;
+ assign pages_T_2335_clk = clk;
+ assign pages_T_2335_data = pages[pages_T_2335_addr];
+ assign pages_T_2338_addr = 3'h4;
+ assign pages_T_2338_en = 1'h1;
+ assign pages_T_2338_clk = clk;
+ assign pages_T_2338_data = pages[pages_T_2338_addr];
+ assign pages_T_2341_addr = 3'h5;
+ assign pages_T_2341_en = 1'h1;
+ assign pages_T_2341_clk = clk;
+ assign pages_T_2341_data = pages[pages_T_2341_addr];
+ assign pages_T_3777_addr = 1'h0;
+ assign pages_T_3777_en = 1'h1;
+ assign pages_T_3777_clk = clk;
+ assign pages_T_3777_data = pages[pages_T_3777_addr];
+ assign pages_T_3779_addr = 1'h1;
+ assign pages_T_3779_en = 1'h1;
+ assign pages_T_3779_clk = clk;
+ assign pages_T_3779_data = pages[pages_T_3779_addr];
+ assign pages_T_3781_addr = 2'h2;
+ assign pages_T_3781_en = 1'h1;
+ assign pages_T_3781_clk = clk;
+ assign pages_T_3781_data = pages[pages_T_3781_addr];
+ assign pages_T_3783_addr = 2'h3;
+ assign pages_T_3783_en = 1'h1;
+ assign pages_T_3783_clk = clk;
+ assign pages_T_3783_data = pages[pages_T_3783_addr];
+ assign pages_T_3785_addr = 3'h4;
+ assign pages_T_3785_en = 1'h1;
+ assign pages_T_3785_clk = clk;
+ assign pages_T_3785_data = pages[pages_T_3785_addr];
+ assign pages_T_3787_addr = 3'h5;
+ assign pages_T_3787_en = 1'h1;
+ assign pages_T_3787_clk = clk;
+ assign pages_T_3787_data = pages[pages_T_3787_addr];
+ assign pages_T_3491_data = T_3487;
+ assign pages_T_3491_addr = 1'h0;
+ assign pages_T_3491_mask = r_btb_update_valid ? T_3489 ? 1'h1 : 1'h0 : 1'h0;
+ assign pages_T_3491_en = r_btb_update_valid ? T_3489 ? 1'h1 : 1'h0 : 1'h0;
+ assign pages_T_3491_clk = clk;
+ assign pages_T_3495_data = T_3487;
+ assign pages_T_3495_addr = 2'h2;
+ assign pages_T_3495_mask = r_btb_update_valid ? T_3493 ? 1'h1 : 1'h0 : 1'h0;
+ assign pages_T_3495_en = r_btb_update_valid ? T_3493 ? 1'h1 : 1'h0 : 1'h0;
+ assign pages_T_3495_clk = clk;
+ assign pages_T_3499_data = T_3487;
+ assign pages_T_3499_addr = 3'h4;
+ assign pages_T_3499_mask = r_btb_update_valid ? T_3497 ? 1'h1 : 1'h0 : 1'h0;
+ assign pages_T_3499_en = r_btb_update_valid ? T_3497 ? 1'h1 : 1'h0 : 1'h0;
+ assign pages_T_3499_clk = clk;
+ assign pages_T_3507_data = T_3503;
+ assign pages_T_3507_addr = 1'h1;
+ assign pages_T_3507_mask = r_btb_update_valid ? T_3505 ? 1'h1 : 1'h0 : 1'h0;
+ assign pages_T_3507_en = r_btb_update_valid ? T_3505 ? 1'h1 : 1'h0 : 1'h0;
+ assign pages_T_3507_clk = clk;
+ assign pages_T_3511_data = T_3503;
+ assign pages_T_3511_addr = 2'h3;
+ assign pages_T_3511_mask = r_btb_update_valid ? T_3509 ? 1'h1 : 1'h0 : 1'h0;
+ assign pages_T_3511_en = r_btb_update_valid ? T_3509 ? 1'h1 : 1'h0 : 1'h0;
+ assign pages_T_3511_clk = clk;
+ assign pages_T_3515_data = T_3503;
+ assign pages_T_3515_addr = 3'h5;
+ assign pages_T_3515_mask = r_btb_update_valid ? T_3513 ? 1'h1 : 1'h0 : 1'h0;
+ assign pages_T_3515_en = r_btb_update_valid ? T_3513 ? 1'h1 : 1'h0 : 1'h0;
+ assign pages_T_3515_clk = clk;
+ assign T_592 = 1'h1 << idxPages_T_590_data;
+ assign T_593 = T_592[5:0];
+ assign T_597 = 1'h1 << idxPages_T_595_data;
+ assign T_598 = T_597[5:0];
+ assign T_602 = 1'h1 << idxPages_T_600_data;
+ assign T_603 = T_602[5:0];
+ assign T_607 = 1'h1 << idxPages_T_605_data;
+ assign T_608 = T_607[5:0];
+ assign T_612 = 1'h1 << idxPages_T_610_data;
+ assign T_613 = T_612[5:0];
+ assign T_617 = 1'h1 << idxPages_T_615_data;
+ assign T_618 = T_617[5:0];
+ assign T_622 = 1'h1 << idxPages_T_620_data;
+ assign T_623 = T_622[5:0];
+ assign T_627 = 1'h1 << idxPages_T_625_data;
+ assign T_628 = T_627[5:0];
+ assign T_632 = 1'h1 << idxPages_T_630_data;
+ assign T_633 = T_632[5:0];
+ assign T_637 = 1'h1 << idxPages_T_635_data;
+ assign T_638 = T_637[5:0];
+ assign T_642 = 1'h1 << idxPages_T_640_data;
+ assign T_643 = T_642[5:0];
+ assign T_647 = 1'h1 << idxPages_T_645_data;
+ assign T_648 = T_647[5:0];
+ assign T_652 = 1'h1 << idxPages_T_650_data;
+ assign T_653 = T_652[5:0];
+ assign T_657 = 1'h1 << idxPages_T_655_data;
+ assign T_658 = T_657[5:0];
+ assign T_662 = 1'h1 << idxPages_T_660_data;
+ assign T_663 = T_662[5:0];
+ assign T_667 = 1'h1 << idxPages_T_665_data;
+ assign T_668 = T_667[5:0];
+ assign T_672 = 1'h1 << idxPages_T_670_data;
+ assign T_673 = T_672[5:0];
+ assign T_677 = 1'h1 << idxPages_T_675_data;
+ assign T_678 = T_677[5:0];
+ assign T_682 = 1'h1 << idxPages_T_680_data;
+ assign T_683 = T_682[5:0];
+ assign T_687 = 1'h1 << idxPages_T_685_data;
+ assign T_688 = T_687[5:0];
+ assign T_692 = 1'h1 << idxPages_T_690_data;
+ assign T_693 = T_692[5:0];
+ assign T_697 = 1'h1 << idxPages_T_695_data;
+ assign T_698 = T_697[5:0];
+ assign T_702 = 1'h1 << idxPages_T_700_data;
+ assign T_703 = T_702[5:0];
+ assign T_707 = 1'h1 << idxPages_T_705_data;
+ assign T_708 = T_707[5:0];
+ assign T_712 = 1'h1 << idxPages_T_710_data;
+ assign T_713 = T_712[5:0];
+ assign T_717 = 1'h1 << idxPages_T_715_data;
+ assign T_718 = T_717[5:0];
+ assign T_722 = 1'h1 << idxPages_T_720_data;
+ assign T_723 = T_722[5:0];
+ assign T_727 = 1'h1 << idxPages_T_725_data;
+ assign T_728 = T_727[5:0];
+ assign T_732 = 1'h1 << idxPages_T_730_data;
+ assign T_733 = T_732[5:0];
+ assign T_737 = 1'h1 << idxPages_T_735_data;
+ assign T_738 = T_737[5:0];
+ assign T_742 = 1'h1 << idxPages_T_740_data;
+ assign T_743 = T_742[5:0];
+ assign T_747 = 1'h1 << idxPages_T_745_data;
+ assign T_748 = T_747[5:0];
+ assign T_752 = 1'h1 << idxPages_T_750_data;
+ assign T_753 = T_752[5:0];
+ assign T_757 = 1'h1 << idxPages_T_755_data;
+ assign T_758 = T_757[5:0];
+ assign T_762 = 1'h1 << idxPages_T_760_data;
+ assign T_763 = T_762[5:0];
+ assign T_767 = 1'h1 << idxPages_T_765_data;
+ assign T_768 = T_767[5:0];
+ assign T_772 = 1'h1 << idxPages_T_770_data;
+ assign T_773 = T_772[5:0];
+ assign T_777 = 1'h1 << idxPages_T_775_data;
+ assign T_778 = T_777[5:0];
+ assign T_782 = 1'h1 << idxPages_T_780_data;
+ assign T_783 = T_782[5:0];
+ assign T_787 = 1'h1 << idxPages_T_785_data;
+ assign T_788 = T_787[5:0];
+ assign T_792 = 1'h1 << idxPages_T_790_data;
+ assign T_793 = T_792[5:0];
+ assign T_797 = 1'h1 << idxPages_T_795_data;
+ assign T_798 = T_797[5:0];
+ assign T_802 = 1'h1 << idxPages_T_800_data;
+ assign T_803 = T_802[5:0];
+ assign T_807 = 1'h1 << idxPages_T_805_data;
+ assign T_808 = T_807[5:0];
+ assign T_812 = 1'h1 << idxPages_T_810_data;
+ assign T_813 = T_812[5:0];
+ assign T_817 = 1'h1 << idxPages_T_815_data;
+ assign T_818 = T_817[5:0];
+ assign T_822 = 1'h1 << idxPages_T_820_data;
+ assign T_823 = T_822[5:0];
+ assign T_827 = 1'h1 << idxPages_T_825_data;
+ assign T_828 = T_827[5:0];
+ assign T_832 = 1'h1 << idxPages_T_830_data;
+ assign T_833 = T_832[5:0];
+ assign T_837 = 1'h1 << idxPages_T_835_data;
+ assign T_838 = T_837[5:0];
+ assign T_842 = 1'h1 << idxPages_T_840_data;
+ assign T_843 = T_842[5:0];
+ assign T_847 = 1'h1 << idxPages_T_845_data;
+ assign T_848 = T_847[5:0];
+ assign T_852 = 1'h1 << idxPages_T_850_data;
+ assign T_853 = T_852[5:0];
+ assign T_857 = 1'h1 << idxPages_T_855_data;
+ assign T_858 = T_857[5:0];
+ assign T_862 = 1'h1 << idxPages_T_860_data;
+ assign T_863 = T_862[5:0];
+ assign T_867 = 1'h1 << idxPages_T_865_data;
+ assign T_868 = T_867[5:0];
+ assign T_872 = 1'h1 << idxPages_T_870_data;
+ assign T_873 = T_872[5:0];
+ assign T_877 = 1'h1 << idxPages_T_875_data;
+ assign T_878 = T_877[5:0];
+ assign T_882 = 1'h1 << idxPages_T_880_data;
+ assign T_883 = T_882[5:0];
+ assign T_887 = 1'h1 << idxPages_T_885_data;
+ assign T_888 = T_887[5:0];
+ assign T_892 = 1'h1 << idxPages_T_890_data;
+ assign T_893 = T_892[5:0];
+ assign T_897 = 1'h1 << idxPages_T_895_data;
+ assign T_898 = T_897[5:0];
+ assign T_902 = 1'h1 << tgtPages_T_900_data;
+ assign T_903 = T_902[5:0];
+ assign T_907 = 1'h1 << tgtPages_T_905_data;
+ assign T_908 = T_907[5:0];
+ assign T_912 = 1'h1 << tgtPages_T_910_data;
+ assign T_913 = T_912[5:0];
+ assign T_917 = 1'h1 << tgtPages_T_915_data;
+ assign T_918 = T_917[5:0];
+ assign T_922 = 1'h1 << tgtPages_T_920_data;
+ assign T_923 = T_922[5:0];
+ assign T_927 = 1'h1 << tgtPages_T_925_data;
+ assign T_928 = T_927[5:0];
+ assign T_932 = 1'h1 << tgtPages_T_930_data;
+ assign T_933 = T_932[5:0];
+ assign T_937 = 1'h1 << tgtPages_T_935_data;
+ assign T_938 = T_937[5:0];
+ assign T_942 = 1'h1 << tgtPages_T_940_data;
+ assign T_943 = T_942[5:0];
+ assign T_947 = 1'h1 << tgtPages_T_945_data;
+ assign T_948 = T_947[5:0];
+ assign T_952 = 1'h1 << tgtPages_T_950_data;
+ assign T_953 = T_952[5:0];
+ assign T_957 = 1'h1 << tgtPages_T_955_data;
+ assign T_958 = T_957[5:0];
+ assign T_962 = 1'h1 << tgtPages_T_960_data;
+ assign T_963 = T_962[5:0];
+ assign T_967 = 1'h1 << tgtPages_T_965_data;
+ assign T_968 = T_967[5:0];
+ assign T_972 = 1'h1 << tgtPages_T_970_data;
+ assign T_973 = T_972[5:0];
+ assign T_977 = 1'h1 << tgtPages_T_975_data;
+ assign T_978 = T_977[5:0];
+ assign T_982 = 1'h1 << tgtPages_T_980_data;
+ assign T_983 = T_982[5:0];
+ assign T_987 = 1'h1 << tgtPages_T_985_data;
+ assign T_988 = T_987[5:0];
+ assign T_992 = 1'h1 << tgtPages_T_990_data;
+ assign T_993 = T_992[5:0];
+ assign T_997 = 1'h1 << tgtPages_T_995_data;
+ assign T_998 = T_997[5:0];
+ assign T_1002 = 1'h1 << tgtPages_T_1000_data;
+ assign T_1003 = T_1002[5:0];
+ assign T_1007 = 1'h1 << tgtPages_T_1005_data;
+ assign T_1008 = T_1007[5:0];
+ assign T_1012 = 1'h1 << tgtPages_T_1010_data;
+ assign T_1013 = T_1012[5:0];
+ assign T_1017 = 1'h1 << tgtPages_T_1015_data;
+ assign T_1018 = T_1017[5:0];
+ assign T_1022 = 1'h1 << tgtPages_T_1020_data;
+ assign T_1023 = T_1022[5:0];
+ assign T_1027 = 1'h1 << tgtPages_T_1025_data;
+ assign T_1028 = T_1027[5:0];
+ assign T_1032 = 1'h1 << tgtPages_T_1030_data;
+ assign T_1033 = T_1032[5:0];
+ assign T_1037 = 1'h1 << tgtPages_T_1035_data;
+ assign T_1038 = T_1037[5:0];
+ assign T_1042 = 1'h1 << tgtPages_T_1040_data;
+ assign T_1043 = T_1042[5:0];
+ assign T_1047 = 1'h1 << tgtPages_T_1045_data;
+ assign T_1048 = T_1047[5:0];
+ assign T_1052 = 1'h1 << tgtPages_T_1050_data;
+ assign T_1053 = T_1052[5:0];
+ assign T_1057 = 1'h1 << tgtPages_T_1055_data;
+ assign T_1058 = T_1057[5:0];
+ assign T_1062 = 1'h1 << tgtPages_T_1060_data;
+ assign T_1063 = T_1062[5:0];
+ assign T_1067 = 1'h1 << tgtPages_T_1065_data;
+ assign T_1068 = T_1067[5:0];
+ assign T_1072 = 1'h1 << tgtPages_T_1070_data;
+ assign T_1073 = T_1072[5:0];
+ assign T_1077 = 1'h1 << tgtPages_T_1075_data;
+ assign T_1078 = T_1077[5:0];
+ assign T_1082 = 1'h1 << tgtPages_T_1080_data;
+ assign T_1083 = T_1082[5:0];
+ assign T_1087 = 1'h1 << tgtPages_T_1085_data;
+ assign T_1088 = T_1087[5:0];
+ assign T_1092 = 1'h1 << tgtPages_T_1090_data;
+ assign T_1093 = T_1092[5:0];
+ assign T_1097 = 1'h1 << tgtPages_T_1095_data;
+ assign T_1098 = T_1097[5:0];
+ assign T_1102 = 1'h1 << tgtPages_T_1100_data;
+ assign T_1103 = T_1102[5:0];
+ assign T_1107 = 1'h1 << tgtPages_T_1105_data;
+ assign T_1108 = T_1107[5:0];
+ assign T_1112 = 1'h1 << tgtPages_T_1110_data;
+ assign T_1113 = T_1112[5:0];
+ assign T_1117 = 1'h1 << tgtPages_T_1115_data;
+ assign T_1118 = T_1117[5:0];
+ assign T_1122 = 1'h1 << tgtPages_T_1120_data;
+ assign T_1123 = T_1122[5:0];
+ assign T_1127 = 1'h1 << tgtPages_T_1125_data;
+ assign T_1128 = T_1127[5:0];
+ assign T_1132 = 1'h1 << tgtPages_T_1130_data;
+ assign T_1133 = T_1132[5:0];
+ assign T_1137 = 1'h1 << tgtPages_T_1135_data;
+ assign T_1138 = T_1137[5:0];
+ assign T_1142 = 1'h1 << tgtPages_T_1140_data;
+ assign T_1143 = T_1142[5:0];
+ assign T_1147 = 1'h1 << tgtPages_T_1145_data;
+ assign T_1148 = T_1147[5:0];
+ assign T_1152 = 1'h1 << tgtPages_T_1150_data;
+ assign T_1153 = T_1152[5:0];
+ assign T_1157 = 1'h1 << tgtPages_T_1155_data;
+ assign T_1158 = T_1157[5:0];
+ assign T_1162 = 1'h1 << tgtPages_T_1160_data;
+ assign T_1163 = T_1162[5:0];
+ assign T_1167 = 1'h1 << tgtPages_T_1165_data;
+ assign T_1168 = T_1167[5:0];
+ assign T_1172 = 1'h1 << tgtPages_T_1170_data;
+ assign T_1173 = T_1172[5:0];
+ assign T_1177 = 1'h1 << tgtPages_T_1175_data;
+ assign T_1178 = T_1177[5:0];
+ assign T_1182 = 1'h1 << tgtPages_T_1180_data;
+ assign T_1183 = T_1182[5:0];
+ assign T_1187 = 1'h1 << tgtPages_T_1185_data;
+ assign T_1188 = T_1187[5:0];
+ assign T_1192 = 1'h1 << tgtPages_T_1190_data;
+ assign T_1193 = T_1192[5:0];
+ assign T_1197 = 1'h1 << tgtPages_T_1195_data;
+ assign T_1198 = T_1197[5:0];
+ assign T_1202 = 1'h1 << tgtPages_T_1200_data;
+ assign T_1203 = T_1202[5:0];
+ assign T_1207 = 1'h1 << tgtPages_T_1205_data;
+ assign T_1208 = T_1207[5:0];
+ assign brIdx_T_4212_addr = io_resp_bits_entry;
+ assign brIdx_T_4212_en = 1'h1;
+ assign brIdx_T_4212_clk = clk;
+ assign brIdx_T_4212_data = brIdx[brIdx_T_4212_addr];
+ assign brIdx_T_3476_data = 1'h0;
+ assign brIdx_T_3476_addr = T_3090;
+ assign brIdx_T_3476_mask = r_btb_update_valid ? 1'h1 : 1'h0;
+ assign brIdx_T_3476_en = r_btb_update_valid ? 1'h1 : 1'h0;
+ assign brIdx_T_3476_clk = clk;
+ assign r_btb_update_valid = T_1478;
+ assign r_btb_update_bits_prediction_valid = T_1479_prediction_valid;
+ assign r_btb_update_bits_prediction_bits_taken = T_1479_prediction_bits_taken;
+ assign r_btb_update_bits_prediction_bits_mask = T_1479_prediction_bits_mask;
+ assign r_btb_update_bits_prediction_bits_bridx = T_1479_prediction_bits_bridx;
+ assign r_btb_update_bits_prediction_bits_target = T_1479_prediction_bits_target;
+ assign r_btb_update_bits_prediction_bits_entry = T_1479_prediction_bits_entry;
+ assign r_btb_update_bits_prediction_bits_bht_history = T_1479_prediction_bits_bht_history;
+ assign r_btb_update_bits_prediction_bits_bht_value = T_1479_prediction_bits_bht_value;
+ assign r_btb_update_bits_pc = T_1479_pc;
+ assign r_btb_update_bits_target = T_1479_target;
+ assign r_btb_update_bits_taken = T_1479_taken;
+ assign r_btb_update_bits_isJump = T_1479_isJump;
+ assign r_btb_update_bits_isReturn = T_1479_isReturn;
+ assign r_btb_update_bits_br_pc = T_1479_br_pc;
+ assign T_1663 = io_req_bits_addr[38:12];
+ assign T_1666 = pages_T_1665_data == T_1663;
+ assign T_1669 = pages_T_1668_data == T_1663;
+ assign T_1672 = pages_T_1671_data == T_1663;
+ assign T_1675 = pages_T_1674_data == T_1663;
+ assign T_1678 = pages_T_1677_data == T_1663;
+ assign T_1681 = pages_T_1680_data == T_1663;
+ assign T_1683_0 = T_1666;
+ assign T_1683_1 = T_1669;
+ assign T_1683_2 = T_1672;
+ assign T_1683_3 = T_1675;
+ assign T_1683_4 = T_1678;
+ assign T_1683_5 = T_1681;
+ assign T_1691 = {T_1683_4,T_1683_3};
+ assign T_1692 = {T_1683_5,T_1691};
+ assign T_1693 = {T_1683_1,T_1683_0};
+ assign T_1694 = {T_1683_2,T_1693};
+ assign T_1695 = {T_1692,T_1694};
+ assign pageHit = T_1695 & pageValid;
+ assign T_1697 = io_req_bits_addr[11:0];
+ assign T_1700 = idxs_T_1699_data == T_1697;
+ assign T_1703 = idxs_T_1702_data == T_1697;
+ assign T_1706 = idxs_T_1705_data == T_1697;
+ assign T_1709 = idxs_T_1708_data == T_1697;
+ assign T_1712 = idxs_T_1711_data == T_1697;
+ assign T_1715 = idxs_T_1714_data == T_1697;
+ assign T_1718 = idxs_T_1717_data == T_1697;
+ assign T_1721 = idxs_T_1720_data == T_1697;
+ assign T_1724 = idxs_T_1723_data == T_1697;
+ assign T_1727 = idxs_T_1726_data == T_1697;
+ assign T_1730 = idxs_T_1729_data == T_1697;
+ assign T_1733 = idxs_T_1732_data == T_1697;
+ assign T_1736 = idxs_T_1735_data == T_1697;
+ assign T_1739 = idxs_T_1738_data == T_1697;
+ assign T_1742 = idxs_T_1741_data == T_1697;
+ assign T_1745 = idxs_T_1744_data == T_1697;
+ assign T_1748 = idxs_T_1747_data == T_1697;
+ assign T_1751 = idxs_T_1750_data == T_1697;
+ assign T_1754 = idxs_T_1753_data == T_1697;
+ assign T_1757 = idxs_T_1756_data == T_1697;
+ assign T_1760 = idxs_T_1759_data == T_1697;
+ assign T_1763 = idxs_T_1762_data == T_1697;
+ assign T_1766 = idxs_T_1765_data == T_1697;
+ assign T_1769 = idxs_T_1768_data == T_1697;
+ assign T_1772 = idxs_T_1771_data == T_1697;
+ assign T_1775 = idxs_T_1774_data == T_1697;
+ assign T_1778 = idxs_T_1777_data == T_1697;
+ assign T_1781 = idxs_T_1780_data == T_1697;
+ assign T_1784 = idxs_T_1783_data == T_1697;
+ assign T_1787 = idxs_T_1786_data == T_1697;
+ assign T_1790 = idxs_T_1789_data == T_1697;
+ assign T_1793 = idxs_T_1792_data == T_1697;
+ assign T_1796 = idxs_T_1795_data == T_1697;
+ assign T_1799 = idxs_T_1798_data == T_1697;
+ assign T_1802 = idxs_T_1801_data == T_1697;
+ assign T_1805 = idxs_T_1804_data == T_1697;
+ assign T_1808 = idxs_T_1807_data == T_1697;
+ assign T_1811 = idxs_T_1810_data == T_1697;
+ assign T_1814 = idxs_T_1813_data == T_1697;
+ assign T_1817 = idxs_T_1816_data == T_1697;
+ assign T_1820 = idxs_T_1819_data == T_1697;
+ assign T_1823 = idxs_T_1822_data == T_1697;
+ assign T_1826 = idxs_T_1825_data == T_1697;
+ assign T_1829 = idxs_T_1828_data == T_1697;
+ assign T_1832 = idxs_T_1831_data == T_1697;
+ assign T_1835 = idxs_T_1834_data == T_1697;
+ assign T_1838 = idxs_T_1837_data == T_1697;
+ assign T_1841 = idxs_T_1840_data == T_1697;
+ assign T_1844 = idxs_T_1843_data == T_1697;
+ assign T_1847 = idxs_T_1846_data == T_1697;
+ assign T_1850 = idxs_T_1849_data == T_1697;
+ assign T_1853 = idxs_T_1852_data == T_1697;
+ assign T_1856 = idxs_T_1855_data == T_1697;
+ assign T_1859 = idxs_T_1858_data == T_1697;
+ assign T_1862 = idxs_T_1861_data == T_1697;
+ assign T_1865 = idxs_T_1864_data == T_1697;
+ assign T_1868 = idxs_T_1867_data == T_1697;
+ assign T_1871 = idxs_T_1870_data == T_1697;
+ assign T_1874 = idxs_T_1873_data == T_1697;
+ assign T_1877 = idxs_T_1876_data == T_1697;
+ assign T_1880 = idxs_T_1879_data == T_1697;
+ assign T_1883 = idxs_T_1882_data == T_1697;
+ assign T_1885_0 = T_1700;
+ assign T_1885_1 = T_1703;
+ assign T_1885_2 = T_1706;
+ assign T_1885_3 = T_1709;
+ assign T_1885_4 = T_1712;
+ assign T_1885_5 = T_1715;
+ assign T_1885_6 = T_1718;
+ assign T_1885_7 = T_1721;
+ assign T_1885_8 = T_1724;
+ assign T_1885_9 = T_1727;
+ assign T_1885_10 = T_1730;
+ assign T_1885_11 = T_1733;
+ assign T_1885_12 = T_1736;
+ assign T_1885_13 = T_1739;
+ assign T_1885_14 = T_1742;
+ assign T_1885_15 = T_1745;
+ assign T_1885_16 = T_1748;
+ assign T_1885_17 = T_1751;
+ assign T_1885_18 = T_1754;
+ assign T_1885_19 = T_1757;
+ assign T_1885_20 = T_1760;
+ assign T_1885_21 = T_1763;
+ assign T_1885_22 = T_1766;
+ assign T_1885_23 = T_1769;
+ assign T_1885_24 = T_1772;
+ assign T_1885_25 = T_1775;
+ assign T_1885_26 = T_1778;
+ assign T_1885_27 = T_1781;
+ assign T_1885_28 = T_1784;
+ assign T_1885_29 = T_1787;
+ assign T_1885_30 = T_1790;
+ assign T_1885_31 = T_1793;
+ assign T_1885_32 = T_1796;
+ assign T_1885_33 = T_1799;
+ assign T_1885_34 = T_1802;
+ assign T_1885_35 = T_1805;
+ assign T_1885_36 = T_1808;
+ assign T_1885_37 = T_1811;
+ assign T_1885_38 = T_1814;
+ assign T_1885_39 = T_1817;
+ assign T_1885_40 = T_1820;
+ assign T_1885_41 = T_1823;
+ assign T_1885_42 = T_1826;
+ assign T_1885_43 = T_1829;
+ assign T_1885_44 = T_1832;
+ assign T_1885_45 = T_1835;
+ assign T_1885_46 = T_1838;
+ assign T_1885_47 = T_1841;
+ assign T_1885_48 = T_1844;
+ assign T_1885_49 = T_1847;
+ assign T_1885_50 = T_1850;
+ assign T_1885_51 = T_1853;
+ assign T_1885_52 = T_1856;
+ assign T_1885_53 = T_1859;
+ assign T_1885_54 = T_1862;
+ assign T_1885_55 = T_1865;
+ assign T_1885_56 = T_1868;
+ assign T_1885_57 = T_1871;
+ assign T_1885_58 = T_1874;
+ assign T_1885_59 = T_1877;
+ assign T_1885_60 = T_1880;
+ assign T_1885_61 = T_1883;
+ assign T_1949 = {T_1885_60,T_1885_59};
+ assign T_1950 = {T_1885_61,T_1949};
+ assign T_1951 = {T_1885_58,T_1885_57};
+ assign T_1952 = {T_1885_56,T_1885_55};
+ assign T_1953 = {T_1951,T_1952};
+ assign T_1954 = {T_1950,T_1953};
+ assign T_1955 = {T_1885_54,T_1885_53};
+ assign T_1956 = {T_1885_52,T_1885_51};
+ assign T_1957 = {T_1955,T_1956};
+ assign T_1958 = {T_1885_50,T_1885_49};
+ assign T_1959 = {T_1885_48,T_1885_47};
+ assign T_1960 = {T_1958,T_1959};
+ assign T_1961 = {T_1957,T_1960};
+ assign T_1962 = {T_1954,T_1961};
+ assign T_1963 = {T_1885_46,T_1885_45};
+ assign T_1964 = {T_1885_44,T_1885_43};
+ assign T_1965 = {T_1963,T_1964};
+ assign T_1966 = {T_1885_42,T_1885_41};
+ assign T_1967 = {T_1885_40,T_1885_39};
+ assign T_1968 = {T_1966,T_1967};
+ assign T_1969 = {T_1965,T_1968};
+ assign T_1970 = {T_1885_38,T_1885_37};
+ assign T_1971 = {T_1885_36,T_1885_35};
+ assign T_1972 = {T_1970,T_1971};
+ assign T_1973 = {T_1885_34,T_1885_33};
+ assign T_1974 = {T_1885_32,T_1885_31};
+ assign T_1975 = {T_1973,T_1974};
+ assign T_1976 = {T_1972,T_1975};
+ assign T_1977 = {T_1969,T_1976};
+ assign T_1978 = {T_1962,T_1977};
+ assign T_1979 = {T_1885_29,T_1885_28};
+ assign T_1980 = {T_1885_30,T_1979};
+ assign T_1981 = {T_1885_27,T_1885_26};
+ assign T_1982 = {T_1885_25,T_1885_24};
+ assign T_1983 = {T_1981,T_1982};
+ assign T_1984 = {T_1980,T_1983};
+ assign T_1985 = {T_1885_23,T_1885_22};
+ assign T_1986 = {T_1885_21,T_1885_20};
+ assign T_1987 = {T_1985,T_1986};
+ assign T_1988 = {T_1885_19,T_1885_18};
+ assign T_1989 = {T_1885_17,T_1885_16};
+ assign T_1990 = {T_1988,T_1989};
+ assign T_1991 = {T_1987,T_1990};
+ assign T_1992 = {T_1984,T_1991};
+ assign T_1993 = {T_1885_15,T_1885_14};
+ assign T_1994 = {T_1885_13,T_1885_12};
+ assign T_1995 = {T_1993,T_1994};
+ assign T_1996 = {T_1885_11,T_1885_10};
+ assign T_1997 = {T_1885_9,T_1885_8};
+ assign T_1998 = {T_1996,T_1997};
+ assign T_1999 = {T_1995,T_1998};
+ assign T_2000 = {T_1885_7,T_1885_6};
+ assign T_2001 = {T_1885_5,T_1885_4};
+ assign T_2002 = {T_2000,T_2001};
+ assign T_2003 = {T_1885_3,T_1885_2};
+ assign T_2004 = {T_1885_1,T_1885_0};
+ assign T_2005 = {T_2003,T_2004};
+ assign T_2006 = {T_2002,T_2005};
+ assign T_2007 = {T_1999,T_2006};
+ assign T_2008 = {T_1992,T_2007};
+ assign T_2009 = {T_1978,T_2008};
+ assign T_2010 = T_593 & pageHit;
+ assign T_2011 = T_598 & pageHit;
+ assign T_2012 = T_603 & pageHit;
+ assign T_2013 = T_608 & pageHit;
+ assign T_2014 = T_613 & pageHit;
+ assign T_2015 = T_618 & pageHit;
+ assign T_2016 = T_623 & pageHit;
+ assign T_2017 = T_628 & pageHit;
+ assign T_2018 = T_633 & pageHit;
+ assign T_2019 = T_638 & pageHit;
+ assign T_2020 = T_643 & pageHit;
+ assign T_2021 = T_648 & pageHit;
+ assign T_2022 = T_653 & pageHit;
+ assign T_2023 = T_658 & pageHit;
+ assign T_2024 = T_663 & pageHit;
+ assign T_2025 = T_668 & pageHit;
+ assign T_2026 = T_673 & pageHit;
+ assign T_2027 = T_678 & pageHit;
+ assign T_2028 = T_683 & pageHit;
+ assign T_2029 = T_688 & pageHit;
+ assign T_2030 = T_693 & pageHit;
+ assign T_2031 = T_698 & pageHit;
+ assign T_2032 = T_703 & pageHit;
+ assign T_2033 = T_708 & pageHit;
+ assign T_2034 = T_713 & pageHit;
+ assign T_2035 = T_718 & pageHit;
+ assign T_2036 = T_723 & pageHit;
+ assign T_2037 = T_728 & pageHit;
+ assign T_2038 = T_733 & pageHit;
+ assign T_2039 = T_738 & pageHit;
+ assign T_2040 = T_743 & pageHit;
+ assign T_2041 = T_748 & pageHit;
+ assign T_2042 = T_753 & pageHit;
+ assign T_2043 = T_758 & pageHit;
+ assign T_2044 = T_763 & pageHit;
+ assign T_2045 = T_768 & pageHit;
+ assign T_2046 = T_773 & pageHit;
+ assign T_2047 = T_778 & pageHit;
+ assign T_2048 = T_783 & pageHit;
+ assign T_2049 = T_788 & pageHit;
+ assign T_2050 = T_793 & pageHit;
+ assign T_2051 = T_798 & pageHit;
+ assign T_2052 = T_803 & pageHit;
+ assign T_2053 = T_808 & pageHit;
+ assign T_2054 = T_813 & pageHit;
+ assign T_2055 = T_818 & pageHit;
+ assign T_2056 = T_823 & pageHit;
+ assign T_2057 = T_828 & pageHit;
+ assign T_2058 = T_833 & pageHit;
+ assign T_2059 = T_838 & pageHit;
+ assign T_2060 = T_843 & pageHit;
+ assign T_2061 = T_848 & pageHit;
+ assign T_2062 = T_853 & pageHit;
+ assign T_2063 = T_858 & pageHit;
+ assign T_2064 = T_863 & pageHit;
+ assign T_2065 = T_868 & pageHit;
+ assign T_2066 = T_873 & pageHit;
+ assign T_2067 = T_878 & pageHit;
+ assign T_2068 = T_883 & pageHit;
+ assign T_2069 = T_888 & pageHit;
+ assign T_2070 = T_893 & pageHit;
+ assign T_2071 = T_898 & pageHit;
+ assign T_2073 = T_2010 != 1'h0;
+ assign T_2075 = T_2011 != 1'h0;
+ assign T_2077 = T_2012 != 1'h0;
+ assign T_2079 = T_2013 != 1'h0;
+ assign T_2081 = T_2014 != 1'h0;
+ assign T_2083 = T_2015 != 1'h0;
+ assign T_2085 = T_2016 != 1'h0;
+ assign T_2087 = T_2017 != 1'h0;
+ assign T_2089 = T_2018 != 1'h0;
+ assign T_2091 = T_2019 != 1'h0;
+ assign T_2093 = T_2020 != 1'h0;
+ assign T_2095 = T_2021 != 1'h0;
+ assign T_2097 = T_2022 != 1'h0;
+ assign T_2099 = T_2023 != 1'h0;
+ assign T_2101 = T_2024 != 1'h0;
+ assign T_2103 = T_2025 != 1'h0;
+ assign T_2105 = T_2026 != 1'h0;
+ assign T_2107 = T_2027 != 1'h0;
+ assign T_2109 = T_2028 != 1'h0;
+ assign T_2111 = T_2029 != 1'h0;
+ assign T_2113 = T_2030 != 1'h0;
+ assign T_2115 = T_2031 != 1'h0;
+ assign T_2117 = T_2032 != 1'h0;
+ assign T_2119 = T_2033 != 1'h0;
+ assign T_2121 = T_2034 != 1'h0;
+ assign T_2123 = T_2035 != 1'h0;
+ assign T_2125 = T_2036 != 1'h0;
+ assign T_2127 = T_2037 != 1'h0;
+ assign T_2129 = T_2038 != 1'h0;
+ assign T_2131 = T_2039 != 1'h0;
+ assign T_2133 = T_2040 != 1'h0;
+ assign T_2135 = T_2041 != 1'h0;
+ assign T_2137 = T_2042 != 1'h0;
+ assign T_2139 = T_2043 != 1'h0;
+ assign T_2141 = T_2044 != 1'h0;
+ assign T_2143 = T_2045 != 1'h0;
+ assign T_2145 = T_2046 != 1'h0;
+ assign T_2147 = T_2047 != 1'h0;
+ assign T_2149 = T_2048 != 1'h0;
+ assign T_2151 = T_2049 != 1'h0;
+ assign T_2153 = T_2050 != 1'h0;
+ assign T_2155 = T_2051 != 1'h0;
+ assign T_2157 = T_2052 != 1'h0;
+ assign T_2159 = T_2053 != 1'h0;
+ assign T_2161 = T_2054 != 1'h0;
+ assign T_2163 = T_2055 != 1'h0;
+ assign T_2165 = T_2056 != 1'h0;
+ assign T_2167 = T_2057 != 1'h0;
+ assign T_2169 = T_2058 != 1'h0;
+ assign T_2171 = T_2059 != 1'h0;
+ assign T_2173 = T_2060 != 1'h0;
+ assign T_2175 = T_2061 != 1'h0;
+ assign T_2177 = T_2062 != 1'h0;
+ assign T_2179 = T_2063 != 1'h0;
+ assign T_2181 = T_2064 != 1'h0;
+ assign T_2183 = T_2065 != 1'h0;
+ assign T_2185 = T_2066 != 1'h0;
+ assign T_2187 = T_2067 != 1'h0;
+ assign T_2189 = T_2068 != 1'h0;
+ assign T_2191 = T_2069 != 1'h0;
+ assign T_2193 = T_2070 != 1'h0;
+ assign T_2195 = T_2071 != 1'h0;
+ assign T_2197_0 = T_2073;
+ assign T_2197_1 = T_2075;
+ assign T_2197_2 = T_2077;
+ assign T_2197_3 = T_2079;
+ assign T_2197_4 = T_2081;
+ assign T_2197_5 = T_2083;
+ assign T_2197_6 = T_2085;
+ assign T_2197_7 = T_2087;
+ assign T_2197_8 = T_2089;
+ assign T_2197_9 = T_2091;
+ assign T_2197_10 = T_2093;
+ assign T_2197_11 = T_2095;
+ assign T_2197_12 = T_2097;
+ assign T_2197_13 = T_2099;
+ assign T_2197_14 = T_2101;
+ assign T_2197_15 = T_2103;
+ assign T_2197_16 = T_2105;
+ assign T_2197_17 = T_2107;
+ assign T_2197_18 = T_2109;
+ assign T_2197_19 = T_2111;
+ assign T_2197_20 = T_2113;
+ assign T_2197_21 = T_2115;
+ assign T_2197_22 = T_2117;
+ assign T_2197_23 = T_2119;
+ assign T_2197_24 = T_2121;
+ assign T_2197_25 = T_2123;
+ assign T_2197_26 = T_2125;
+ assign T_2197_27 = T_2127;
+ assign T_2197_28 = T_2129;
+ assign T_2197_29 = T_2131;
+ assign T_2197_30 = T_2133;
+ assign T_2197_31 = T_2135;
+ assign T_2197_32 = T_2137;
+ assign T_2197_33 = T_2139;
+ assign T_2197_34 = T_2141;
+ assign T_2197_35 = T_2143;
+ assign T_2197_36 = T_2145;
+ assign T_2197_37 = T_2147;
+ assign T_2197_38 = T_2149;
+ assign T_2197_39 = T_2151;
+ assign T_2197_40 = T_2153;
+ assign T_2197_41 = T_2155;
+ assign T_2197_42 = T_2157;
+ assign T_2197_43 = T_2159;
+ assign T_2197_44 = T_2161;
+ assign T_2197_45 = T_2163;
+ assign T_2197_46 = T_2165;
+ assign T_2197_47 = T_2167;
+ assign T_2197_48 = T_2169;
+ assign T_2197_49 = T_2171;
+ assign T_2197_50 = T_2173;
+ assign T_2197_51 = T_2175;
+ assign T_2197_52 = T_2177;
+ assign T_2197_53 = T_2179;
+ assign T_2197_54 = T_2181;
+ assign T_2197_55 = T_2183;
+ assign T_2197_56 = T_2185;
+ assign T_2197_57 = T_2187;
+ assign T_2197_58 = T_2189;
+ assign T_2197_59 = T_2191;
+ assign T_2197_60 = T_2193;
+ assign T_2197_61 = T_2195;
+ assign T_2261 = {T_2197_60,T_2197_59};
+ assign T_2262 = {T_2197_61,T_2261};
+ assign T_2263 = {T_2197_58,T_2197_57};
+ assign T_2264 = {T_2197_56,T_2197_55};
+ assign T_2265 = {T_2263,T_2264};
+ assign T_2266 = {T_2262,T_2265};
+ assign T_2267 = {T_2197_54,T_2197_53};
+ assign T_2268 = {T_2197_52,T_2197_51};
+ assign T_2269 = {T_2267,T_2268};
+ assign T_2270 = {T_2197_50,T_2197_49};
+ assign T_2271 = {T_2197_48,T_2197_47};
+ assign T_2272 = {T_2270,T_2271};
+ assign T_2273 = {T_2269,T_2272};
+ assign T_2274 = {T_2266,T_2273};
+ assign T_2275 = {T_2197_46,T_2197_45};
+ assign T_2276 = {T_2197_44,T_2197_43};
+ assign T_2277 = {T_2275,T_2276};
+ assign T_2278 = {T_2197_42,T_2197_41};
+ assign T_2279 = {T_2197_40,T_2197_39};
+ assign T_2280 = {T_2278,T_2279};
+ assign T_2281 = {T_2277,T_2280};
+ assign T_2282 = {T_2197_38,T_2197_37};
+ assign T_2283 = {T_2197_36,T_2197_35};
+ assign T_2284 = {T_2282,T_2283};
+ assign T_2285 = {T_2197_34,T_2197_33};
+ assign T_2286 = {T_2197_32,T_2197_31};
+ assign T_2287 = {T_2285,T_2286};
+ assign T_2288 = {T_2284,T_2287};
+ assign T_2289 = {T_2281,T_2288};
+ assign T_2290 = {T_2274,T_2289};
+ assign T_2291 = {T_2197_29,T_2197_28};
+ assign T_2292 = {T_2197_30,T_2291};
+ assign T_2293 = {T_2197_27,T_2197_26};
+ assign T_2294 = {T_2197_25,T_2197_24};
+ assign T_2295 = {T_2293,T_2294};
+ assign T_2296 = {T_2292,T_2295};
+ assign T_2297 = {T_2197_23,T_2197_22};
+ assign T_2298 = {T_2197_21,T_2197_20};
+ assign T_2299 = {T_2297,T_2298};
+ assign T_2300 = {T_2197_19,T_2197_18};
+ assign T_2301 = {T_2197_17,T_2197_16};
+ assign T_2302 = {T_2300,T_2301};
+ assign T_2303 = {T_2299,T_2302};
+ assign T_2304 = {T_2296,T_2303};
+ assign T_2305 = {T_2197_15,T_2197_14};
+ assign T_2306 = {T_2197_13,T_2197_12};
+ assign T_2307 = {T_2305,T_2306};
+ assign T_2308 = {T_2197_11,T_2197_10};
+ assign T_2309 = {T_2197_9,T_2197_8};
+ assign T_2310 = {T_2308,T_2309};
+ assign T_2311 = {T_2307,T_2310};
+ assign T_2312 = {T_2197_7,T_2197_6};
+ assign T_2313 = {T_2197_5,T_2197_4};
+ assign T_2314 = {T_2312,T_2313};
+ assign T_2315 = {T_2197_3,T_2197_2};
+ assign T_2316 = {T_2197_1,T_2197_0};
+ assign T_2317 = {T_2315,T_2316};
+ assign T_2318 = {T_2314,T_2317};
+ assign T_2319 = {T_2311,T_2318};
+ assign T_2320 = {T_2304,T_2319};
+ assign T_2321 = {T_2290,T_2320};
+ assign T_2322 = idxValid & T_2009;
+ assign hits = T_2322 & T_2321;
+ assign T_2324 = r_btb_update_bits_pc[38:12];
+ assign T_2327 = pages_T_2326_data == T_2324;
+ assign T_2330 = pages_T_2329_data == T_2324;
+ assign T_2333 = pages_T_2332_data == T_2324;
+ assign T_2336 = pages_T_2335_data == T_2324;
+ assign T_2339 = pages_T_2338_data == T_2324;
+ assign T_2342 = pages_T_2341_data == T_2324;
+ assign T_2344_0 = T_2327;
+ assign T_2344_1 = T_2330;
+ assign T_2344_2 = T_2333;
+ assign T_2344_3 = T_2336;
+ assign T_2344_4 = T_2339;
+ assign T_2344_5 = T_2342;
+ assign T_2352 = {T_2344_4,T_2344_3};
+ assign T_2353 = {T_2344_5,T_2352};
+ assign T_2354 = {T_2344_1,T_2344_0};
+ assign T_2355 = {T_2344_2,T_2354};
+ assign T_2356 = {T_2353,T_2355};
+ assign updatePageHit = T_2356 & pageValid;
+ assign T_2358 = r_btb_update_bits_pc[11:0];
+ assign T_2361 = idxs_T_2360_data == T_2358;
+ assign T_2364 = idxs_T_2363_data == T_2358;
+ assign T_2367 = idxs_T_2366_data == T_2358;
+ assign T_2370 = idxs_T_2369_data == T_2358;
+ assign T_2373 = idxs_T_2372_data == T_2358;
+ assign T_2376 = idxs_T_2375_data == T_2358;
+ assign T_2379 = idxs_T_2378_data == T_2358;
+ assign T_2382 = idxs_T_2381_data == T_2358;
+ assign T_2385 = idxs_T_2384_data == T_2358;
+ assign T_2388 = idxs_T_2387_data == T_2358;
+ assign T_2391 = idxs_T_2390_data == T_2358;
+ assign T_2394 = idxs_T_2393_data == T_2358;
+ assign T_2397 = idxs_T_2396_data == T_2358;
+ assign T_2400 = idxs_T_2399_data == T_2358;
+ assign T_2403 = idxs_T_2402_data == T_2358;
+ assign T_2406 = idxs_T_2405_data == T_2358;
+ assign T_2409 = idxs_T_2408_data == T_2358;
+ assign T_2412 = idxs_T_2411_data == T_2358;
+ assign T_2415 = idxs_T_2414_data == T_2358;
+ assign T_2418 = idxs_T_2417_data == T_2358;
+ assign T_2421 = idxs_T_2420_data == T_2358;
+ assign T_2424 = idxs_T_2423_data == T_2358;
+ assign T_2427 = idxs_T_2426_data == T_2358;
+ assign T_2430 = idxs_T_2429_data == T_2358;
+ assign T_2433 = idxs_T_2432_data == T_2358;
+ assign T_2436 = idxs_T_2435_data == T_2358;
+ assign T_2439 = idxs_T_2438_data == T_2358;
+ assign T_2442 = idxs_T_2441_data == T_2358;
+ assign T_2445 = idxs_T_2444_data == T_2358;
+ assign T_2448 = idxs_T_2447_data == T_2358;
+ assign T_2451 = idxs_T_2450_data == T_2358;
+ assign T_2454 = idxs_T_2453_data == T_2358;
+ assign T_2457 = idxs_T_2456_data == T_2358;
+ assign T_2460 = idxs_T_2459_data == T_2358;
+ assign T_2463 = idxs_T_2462_data == T_2358;
+ assign T_2466 = idxs_T_2465_data == T_2358;
+ assign T_2469 = idxs_T_2468_data == T_2358;
+ assign T_2472 = idxs_T_2471_data == T_2358;
+ assign T_2475 = idxs_T_2474_data == T_2358;
+ assign T_2478 = idxs_T_2477_data == T_2358;
+ assign T_2481 = idxs_T_2480_data == T_2358;
+ assign T_2484 = idxs_T_2483_data == T_2358;
+ assign T_2487 = idxs_T_2486_data == T_2358;
+ assign T_2490 = idxs_T_2489_data == T_2358;
+ assign T_2493 = idxs_T_2492_data == T_2358;
+ assign T_2496 = idxs_T_2495_data == T_2358;
+ assign T_2499 = idxs_T_2498_data == T_2358;
+ assign T_2502 = idxs_T_2501_data == T_2358;
+ assign T_2505 = idxs_T_2504_data == T_2358;
+ assign T_2508 = idxs_T_2507_data == T_2358;
+ assign T_2511 = idxs_T_2510_data == T_2358;
+ assign T_2514 = idxs_T_2513_data == T_2358;
+ assign T_2517 = idxs_T_2516_data == T_2358;
+ assign T_2520 = idxs_T_2519_data == T_2358;
+ assign T_2523 = idxs_T_2522_data == T_2358;
+ assign T_2526 = idxs_T_2525_data == T_2358;
+ assign T_2529 = idxs_T_2528_data == T_2358;
+ assign T_2532 = idxs_T_2531_data == T_2358;
+ assign T_2535 = idxs_T_2534_data == T_2358;
+ assign T_2538 = idxs_T_2537_data == T_2358;
+ assign T_2541 = idxs_T_2540_data == T_2358;
+ assign T_2544 = idxs_T_2543_data == T_2358;
+ assign T_2546_0 = T_2361;
+ assign T_2546_1 = T_2364;
+ assign T_2546_2 = T_2367;
+ assign T_2546_3 = T_2370;
+ assign T_2546_4 = T_2373;
+ assign T_2546_5 = T_2376;
+ assign T_2546_6 = T_2379;
+ assign T_2546_7 = T_2382;
+ assign T_2546_8 = T_2385;
+ assign T_2546_9 = T_2388;
+ assign T_2546_10 = T_2391;
+ assign T_2546_11 = T_2394;
+ assign T_2546_12 = T_2397;
+ assign T_2546_13 = T_2400;
+ assign T_2546_14 = T_2403;
+ assign T_2546_15 = T_2406;
+ assign T_2546_16 = T_2409;
+ assign T_2546_17 = T_2412;
+ assign T_2546_18 = T_2415;
+ assign T_2546_19 = T_2418;
+ assign T_2546_20 = T_2421;
+ assign T_2546_21 = T_2424;
+ assign T_2546_22 = T_2427;
+ assign T_2546_23 = T_2430;
+ assign T_2546_24 = T_2433;
+ assign T_2546_25 = T_2436;
+ assign T_2546_26 = T_2439;
+ assign T_2546_27 = T_2442;
+ assign T_2546_28 = T_2445;
+ assign T_2546_29 = T_2448;
+ assign T_2546_30 = T_2451;
+ assign T_2546_31 = T_2454;
+ assign T_2546_32 = T_2457;
+ assign T_2546_33 = T_2460;
+ assign T_2546_34 = T_2463;
+ assign T_2546_35 = T_2466;
+ assign T_2546_36 = T_2469;
+ assign T_2546_37 = T_2472;
+ assign T_2546_38 = T_2475;
+ assign T_2546_39 = T_2478;
+ assign T_2546_40 = T_2481;
+ assign T_2546_41 = T_2484;
+ assign T_2546_42 = T_2487;
+ assign T_2546_43 = T_2490;
+ assign T_2546_44 = T_2493;
+ assign T_2546_45 = T_2496;
+ assign T_2546_46 = T_2499;
+ assign T_2546_47 = T_2502;
+ assign T_2546_48 = T_2505;
+ assign T_2546_49 = T_2508;
+ assign T_2546_50 = T_2511;
+ assign T_2546_51 = T_2514;
+ assign T_2546_52 = T_2517;
+ assign T_2546_53 = T_2520;
+ assign T_2546_54 = T_2523;
+ assign T_2546_55 = T_2526;
+ assign T_2546_56 = T_2529;
+ assign T_2546_57 = T_2532;
+ assign T_2546_58 = T_2535;
+ assign T_2546_59 = T_2538;
+ assign T_2546_60 = T_2541;
+ assign T_2546_61 = T_2544;
+ assign T_2610 = {T_2546_60,T_2546_59};
+ assign T_2611 = {T_2546_61,T_2610};
+ assign T_2612 = {T_2546_58,T_2546_57};
+ assign T_2613 = {T_2546_56,T_2546_55};
+ assign T_2614 = {T_2612,T_2613};
+ assign T_2615 = {T_2611,T_2614};
+ assign T_2616 = {T_2546_54,T_2546_53};
+ assign T_2617 = {T_2546_52,T_2546_51};
+ assign T_2618 = {T_2616,T_2617};
+ assign T_2619 = {T_2546_50,T_2546_49};
+ assign T_2620 = {T_2546_48,T_2546_47};
+ assign T_2621 = {T_2619,T_2620};
+ assign T_2622 = {T_2618,T_2621};
+ assign T_2623 = {T_2615,T_2622};
+ assign T_2624 = {T_2546_46,T_2546_45};
+ assign T_2625 = {T_2546_44,T_2546_43};
+ assign T_2626 = {T_2624,T_2625};
+ assign T_2627 = {T_2546_42,T_2546_41};
+ assign T_2628 = {T_2546_40,T_2546_39};
+ assign T_2629 = {T_2627,T_2628};
+ assign T_2630 = {T_2626,T_2629};
+ assign T_2631 = {T_2546_38,T_2546_37};
+ assign T_2632 = {T_2546_36,T_2546_35};
+ assign T_2633 = {T_2631,T_2632};
+ assign T_2634 = {T_2546_34,T_2546_33};
+ assign T_2635 = {T_2546_32,T_2546_31};
+ assign T_2636 = {T_2634,T_2635};
+ assign T_2637 = {T_2633,T_2636};
+ assign T_2638 = {T_2630,T_2637};
+ assign T_2639 = {T_2623,T_2638};
+ assign T_2640 = {T_2546_29,T_2546_28};
+ assign T_2641 = {T_2546_30,T_2640};
+ assign T_2642 = {T_2546_27,T_2546_26};
+ assign T_2643 = {T_2546_25,T_2546_24};
+ assign T_2644 = {T_2642,T_2643};
+ assign T_2645 = {T_2641,T_2644};
+ assign T_2646 = {T_2546_23,T_2546_22};
+ assign T_2647 = {T_2546_21,T_2546_20};
+ assign T_2648 = {T_2646,T_2647};
+ assign T_2649 = {T_2546_19,T_2546_18};
+ assign T_2650 = {T_2546_17,T_2546_16};
+ assign T_2651 = {T_2649,T_2650};
+ assign T_2652 = {T_2648,T_2651};
+ assign T_2653 = {T_2645,T_2652};
+ assign T_2654 = {T_2546_15,T_2546_14};
+ assign T_2655 = {T_2546_13,T_2546_12};
+ assign T_2656 = {T_2654,T_2655};
+ assign T_2657 = {T_2546_11,T_2546_10};
+ assign T_2658 = {T_2546_9,T_2546_8};
+ assign T_2659 = {T_2657,T_2658};
+ assign T_2660 = {T_2656,T_2659};
+ assign T_2661 = {T_2546_7,T_2546_6};
+ assign T_2662 = {T_2546_5,T_2546_4};
+ assign T_2663 = {T_2661,T_2662};
+ assign T_2664 = {T_2546_3,T_2546_2};
+ assign T_2665 = {T_2546_1,T_2546_0};
+ assign T_2666 = {T_2664,T_2665};
+ assign T_2667 = {T_2663,T_2666};
+ assign T_2668 = {T_2660,T_2667};
+ assign T_2669 = {T_2653,T_2668};
+ assign T_2670 = {T_2639,T_2669};
+ assign T_2671 = T_593 & updatePageHit;
+ assign T_2672 = T_598 & updatePageHit;
+ assign T_2673 = T_603 & updatePageHit;
+ assign T_2674 = T_608 & updatePageHit;
+ assign T_2675 = T_613 & updatePageHit;
+ assign T_2676 = T_618 & updatePageHit;
+ assign T_2677 = T_623 & updatePageHit;
+ assign T_2678 = T_628 & updatePageHit;
+ assign T_2679 = T_633 & updatePageHit;
+ assign T_2680 = T_638 & updatePageHit;
+ assign T_2681 = T_643 & updatePageHit;
+ assign T_2682 = T_648 & updatePageHit;
+ assign T_2683 = T_653 & updatePageHit;
+ assign T_2684 = T_658 & updatePageHit;
+ assign T_2685 = T_663 & updatePageHit;
+ assign T_2686 = T_668 & updatePageHit;
+ assign T_2687 = T_673 & updatePageHit;
+ assign T_2688 = T_678 & updatePageHit;
+ assign T_2689 = T_683 & updatePageHit;
+ assign T_2690 = T_688 & updatePageHit;
+ assign T_2691 = T_693 & updatePageHit;
+ assign T_2692 = T_698 & updatePageHit;
+ assign T_2693 = T_703 & updatePageHit;
+ assign T_2694 = T_708 & updatePageHit;
+ assign T_2695 = T_713 & updatePageHit;
+ assign T_2696 = T_718 & updatePageHit;
+ assign T_2697 = T_723 & updatePageHit;
+ assign T_2698 = T_728 & updatePageHit;
+ assign T_2699 = T_733 & updatePageHit;
+ assign T_2700 = T_738 & updatePageHit;
+ assign T_2701 = T_743 & updatePageHit;
+ assign T_2702 = T_748 & updatePageHit;
+ assign T_2703 = T_753 & updatePageHit;
+ assign T_2704 = T_758 & updatePageHit;
+ assign T_2705 = T_763 & updatePageHit;
+ assign T_2706 = T_768 & updatePageHit;
+ assign T_2707 = T_773 & updatePageHit;
+ assign T_2708 = T_778 & updatePageHit;
+ assign T_2709 = T_783 & updatePageHit;
+ assign T_2710 = T_788 & updatePageHit;
+ assign T_2711 = T_793 & updatePageHit;
+ assign T_2712 = T_798 & updatePageHit;
+ assign T_2713 = T_803 & updatePageHit;
+ assign T_2714 = T_808 & updatePageHit;
+ assign T_2715 = T_813 & updatePageHit;
+ assign T_2716 = T_818 & updatePageHit;
+ assign T_2717 = T_823 & updatePageHit;
+ assign T_2718 = T_828 & updatePageHit;
+ assign T_2719 = T_833 & updatePageHit;
+ assign T_2720 = T_838 & updatePageHit;
+ assign T_2721 = T_843 & updatePageHit;
+ assign T_2722 = T_848 & updatePageHit;
+ assign T_2723 = T_853 & updatePageHit;
+ assign T_2724 = T_858 & updatePageHit;
+ assign T_2725 = T_863 & updatePageHit;
+ assign T_2726 = T_868 & updatePageHit;
+ assign T_2727 = T_873 & updatePageHit;
+ assign T_2728 = T_878 & updatePageHit;
+ assign T_2729 = T_883 & updatePageHit;
+ assign T_2730 = T_888 & updatePageHit;
+ assign T_2731 = T_893 & updatePageHit;
+ assign T_2732 = T_898 & updatePageHit;
+ assign T_2734 = T_2671 != 1'h0;
+ assign T_2736 = T_2672 != 1'h0;
+ assign T_2738 = T_2673 != 1'h0;
+ assign T_2740 = T_2674 != 1'h0;
+ assign T_2742 = T_2675 != 1'h0;
+ assign T_2744 = T_2676 != 1'h0;
+ assign T_2746 = T_2677 != 1'h0;
+ assign T_2748 = T_2678 != 1'h0;
+ assign T_2750 = T_2679 != 1'h0;
+ assign T_2752 = T_2680 != 1'h0;
+ assign T_2754 = T_2681 != 1'h0;
+ assign T_2756 = T_2682 != 1'h0;
+ assign T_2758 = T_2683 != 1'h0;
+ assign T_2760 = T_2684 != 1'h0;
+ assign T_2762 = T_2685 != 1'h0;
+ assign T_2764 = T_2686 != 1'h0;
+ assign T_2766 = T_2687 != 1'h0;
+ assign T_2768 = T_2688 != 1'h0;
+ assign T_2770 = T_2689 != 1'h0;
+ assign T_2772 = T_2690 != 1'h0;
+ assign T_2774 = T_2691 != 1'h0;
+ assign T_2776 = T_2692 != 1'h0;
+ assign T_2778 = T_2693 != 1'h0;
+ assign T_2780 = T_2694 != 1'h0;
+ assign T_2782 = T_2695 != 1'h0;
+ assign T_2784 = T_2696 != 1'h0;
+ assign T_2786 = T_2697 != 1'h0;
+ assign T_2788 = T_2698 != 1'h0;
+ assign T_2790 = T_2699 != 1'h0;
+ assign T_2792 = T_2700 != 1'h0;
+ assign T_2794 = T_2701 != 1'h0;
+ assign T_2796 = T_2702 != 1'h0;
+ assign T_2798 = T_2703 != 1'h0;
+ assign T_2800 = T_2704 != 1'h0;
+ assign T_2802 = T_2705 != 1'h0;
+ assign T_2804 = T_2706 != 1'h0;
+ assign T_2806 = T_2707 != 1'h0;
+ assign T_2808 = T_2708 != 1'h0;
+ assign T_2810 = T_2709 != 1'h0;
+ assign T_2812 = T_2710 != 1'h0;
+ assign T_2814 = T_2711 != 1'h0;
+ assign T_2816 = T_2712 != 1'h0;
+ assign T_2818 = T_2713 != 1'h0;
+ assign T_2820 = T_2714 != 1'h0;
+ assign T_2822 = T_2715 != 1'h0;
+ assign T_2824 = T_2716 != 1'h0;
+ assign T_2826 = T_2717 != 1'h0;
+ assign T_2828 = T_2718 != 1'h0;
+ assign T_2830 = T_2719 != 1'h0;
+ assign T_2832 = T_2720 != 1'h0;
+ assign T_2834 = T_2721 != 1'h0;
+ assign T_2836 = T_2722 != 1'h0;
+ assign T_2838 = T_2723 != 1'h0;
+ assign T_2840 = T_2724 != 1'h0;
+ assign T_2842 = T_2725 != 1'h0;
+ assign T_2844 = T_2726 != 1'h0;
+ assign T_2846 = T_2727 != 1'h0;
+ assign T_2848 = T_2728 != 1'h0;
+ assign T_2850 = T_2729 != 1'h0;
+ assign T_2852 = T_2730 != 1'h0;
+ assign T_2854 = T_2731 != 1'h0;
+ assign T_2856 = T_2732 != 1'h0;
+ assign T_2858_0 = T_2734;
+ assign T_2858_1 = T_2736;
+ assign T_2858_2 = T_2738;
+ assign T_2858_3 = T_2740;
+ assign T_2858_4 = T_2742;
+ assign T_2858_5 = T_2744;
+ assign T_2858_6 = T_2746;
+ assign T_2858_7 = T_2748;
+ assign T_2858_8 = T_2750;
+ assign T_2858_9 = T_2752;
+ assign T_2858_10 = T_2754;
+ assign T_2858_11 = T_2756;
+ assign T_2858_12 = T_2758;
+ assign T_2858_13 = T_2760;
+ assign T_2858_14 = T_2762;
+ assign T_2858_15 = T_2764;
+ assign T_2858_16 = T_2766;
+ assign T_2858_17 = T_2768;
+ assign T_2858_18 = T_2770;
+ assign T_2858_19 = T_2772;
+ assign T_2858_20 = T_2774;
+ assign T_2858_21 = T_2776;
+ assign T_2858_22 = T_2778;
+ assign T_2858_23 = T_2780;
+ assign T_2858_24 = T_2782;
+ assign T_2858_25 = T_2784;
+ assign T_2858_26 = T_2786;
+ assign T_2858_27 = T_2788;
+ assign T_2858_28 = T_2790;
+ assign T_2858_29 = T_2792;
+ assign T_2858_30 = T_2794;
+ assign T_2858_31 = T_2796;
+ assign T_2858_32 = T_2798;
+ assign T_2858_33 = T_2800;
+ assign T_2858_34 = T_2802;
+ assign T_2858_35 = T_2804;
+ assign T_2858_36 = T_2806;
+ assign T_2858_37 = T_2808;
+ assign T_2858_38 = T_2810;
+ assign T_2858_39 = T_2812;
+ assign T_2858_40 = T_2814;
+ assign T_2858_41 = T_2816;
+ assign T_2858_42 = T_2818;
+ assign T_2858_43 = T_2820;
+ assign T_2858_44 = T_2822;
+ assign T_2858_45 = T_2824;
+ assign T_2858_46 = T_2826;
+ assign T_2858_47 = T_2828;
+ assign T_2858_48 = T_2830;
+ assign T_2858_49 = T_2832;
+ assign T_2858_50 = T_2834;
+ assign T_2858_51 = T_2836;
+ assign T_2858_52 = T_2838;
+ assign T_2858_53 = T_2840;
+ assign T_2858_54 = T_2842;
+ assign T_2858_55 = T_2844;
+ assign T_2858_56 = T_2846;
+ assign T_2858_57 = T_2848;
+ assign T_2858_58 = T_2850;
+ assign T_2858_59 = T_2852;
+ assign T_2858_60 = T_2854;
+ assign T_2858_61 = T_2856;
+ assign T_2922 = {T_2858_60,T_2858_59};
+ assign T_2923 = {T_2858_61,T_2922};
+ assign T_2924 = {T_2858_58,T_2858_57};
+ assign T_2925 = {T_2858_56,T_2858_55};
+ assign T_2926 = {T_2924,T_2925};
+ assign T_2927 = {T_2923,T_2926};
+ assign T_2928 = {T_2858_54,T_2858_53};
+ assign T_2929 = {T_2858_52,T_2858_51};
+ assign T_2930 = {T_2928,T_2929};
+ assign T_2931 = {T_2858_50,T_2858_49};
+ assign T_2932 = {T_2858_48,T_2858_47};
+ assign T_2933 = {T_2931,T_2932};
+ assign T_2934 = {T_2930,T_2933};
+ assign T_2935 = {T_2927,T_2934};
+ assign T_2936 = {T_2858_46,T_2858_45};
+ assign T_2937 = {T_2858_44,T_2858_43};
+ assign T_2938 = {T_2936,T_2937};
+ assign T_2939 = {T_2858_42,T_2858_41};
+ assign T_2940 = {T_2858_40,T_2858_39};
+ assign T_2941 = {T_2939,T_2940};
+ assign T_2942 = {T_2938,T_2941};
+ assign T_2943 = {T_2858_38,T_2858_37};
+ assign T_2944 = {T_2858_36,T_2858_35};
+ assign T_2945 = {T_2943,T_2944};
+ assign T_2946 = {T_2858_34,T_2858_33};
+ assign T_2947 = {T_2858_32,T_2858_31};
+ assign T_2948 = {T_2946,T_2947};
+ assign T_2949 = {T_2945,T_2948};
+ assign T_2950 = {T_2942,T_2949};
+ assign T_2951 = {T_2935,T_2950};
+ assign T_2952 = {T_2858_29,T_2858_28};
+ assign T_2953 = {T_2858_30,T_2952};
+ assign T_2954 = {T_2858_27,T_2858_26};
+ assign T_2955 = {T_2858_25,T_2858_24};
+ assign T_2956 = {T_2954,T_2955};
+ assign T_2957 = {T_2953,T_2956};
+ assign T_2958 = {T_2858_23,T_2858_22};
+ assign T_2959 = {T_2858_21,T_2858_20};
+ assign T_2960 = {T_2958,T_2959};
+ assign T_2961 = {T_2858_19,T_2858_18};
+ assign T_2962 = {T_2858_17,T_2858_16};
+ assign T_2963 = {T_2961,T_2962};
+ assign T_2964 = {T_2960,T_2963};
+ assign T_2965 = {T_2957,T_2964};
+ assign T_2966 = {T_2858_15,T_2858_14};
+ assign T_2967 = {T_2858_13,T_2858_12};
+ assign T_2968 = {T_2966,T_2967};
+ assign T_2969 = {T_2858_11,T_2858_10};
+ assign T_2970 = {T_2858_9,T_2858_8};
+ assign T_2971 = {T_2969,T_2970};
+ assign T_2972 = {T_2968,T_2971};
+ assign T_2973 = {T_2858_7,T_2858_6};
+ assign T_2974 = {T_2858_5,T_2858_4};
+ assign T_2975 = {T_2973,T_2974};
+ assign T_2976 = {T_2858_3,T_2858_2};
+ assign T_2977 = {T_2858_1,T_2858_0};
+ assign T_2978 = {T_2976,T_2977};
+ assign T_2979 = {T_2975,T_2978};
+ assign T_2980 = {T_2972,T_2979};
+ assign T_2981 = {T_2965,T_2980};
+ assign T_2982 = {T_2951,T_2981};
+ assign T_2983 = idxValid & T_2670;
+ assign updateHits = T_2983 & T_2982;
+ assign T_2987 = T_2986[0];
+ assign T_2988 = T_2986[2];
+ assign T_2989 = T_2987 ^ T_2988;
+ assign T_2990 = T_2986[3];
+ assign T_2991 = T_2989 ^ T_2990;
+ assign T_2992 = T_2986[5];
+ assign T_2993 = T_2991 ^ T_2992;
+ assign T_2994 = T_2986[15:1];
+ assign T_2995 = {T_2993,T_2994};
+ assign T_2997 = r_btb_update_bits_prediction_valid == 1'h0;
+ assign T_2998 = r_btb_update_valid & T_2997;
+ assign T_3002 = nextRepl == 6'h3d;
+ assign T_3004 = 1'h1 & T_3002;
+ assign T_3007 = nextRepl + 1'h1;
+ assign T_3008 = T_3007[5:0];
+ assign T_3009 = T_3004 ? 1'h0 : T_3008;
+ assign T_3010 = T_2998 & T_3002;
+ assign useUpdatePageHit = updatePageHit != 1'h0;
+ assign doIdxPageRepl = useUpdatePageHit == 1'h0;
+ assign idxPageRepl = T_3082;
+ assign idxPageUpdateOH = useUpdatePageHit ? updatePageHit : idxPageRepl;
+ assign T_3018 = idxPageUpdateOH[5:4];
+ assign T_3019 = idxPageUpdateOH[3:0];
+ assign T_3021 = T_3018 != 1'h0;
+ assign T_3022 = T_3018 | T_3019;
+ assign T_3023 = T_3022[3:2];
+ assign T_3024 = T_3022[1:0];
+ assign T_3026 = T_3023 != 1'h0;
+ assign T_3027 = T_3023 | T_3024;
+ assign T_3028 = T_3027[1];
+ assign T_3029 = {T_3026,T_3028};
+ assign idxPageUpdate = {T_3021,T_3029};
+ assign idxPageReplEn = doIdxPageRepl ? idxPageRepl : 1'h0;
+ assign T_3033 = r_btb_update_bits_pc[38:12];
+ assign T_3034 = io_req_bits_addr[38:12];
+ assign samePage = T_3033 == T_3034;
+ assign T_3036 = ~ idxPageReplEn;
+ assign T_3037 = pageHit & T_3036;
+ assign usePageHit = T_3037 != 1'h0;
+ assign T_3041 = samePage == 1'h0;
+ assign T_3043 = usePageHit == 1'h0;
+ assign doTgtPageRepl = T_3041 & T_3043;
+ assign T_3045 = idxPageUpdateOH[4:0];
+ assign T_3046 = T_3045 << 1;
+ assign T_3047 = idxPageUpdateOH[5];
+ assign T_3048 = T_3046 | T_3047;
+ assign tgtPageRepl = samePage ? idxPageUpdateOH : T_3048;
+ assign T_3050 = usePageHit ? pageHit : tgtPageRepl;
+ assign T_3051 = T_3050[5:4];
+ assign T_3052 = T_3050[3:0];
+ assign T_3054 = T_3051 != 1'h0;
+ assign T_3055 = T_3051 | T_3052;
+ assign T_3056 = T_3055[3:2];
+ assign T_3057 = T_3055[1:0];
+ assign T_3059 = T_3056 != 1'h0;
+ assign T_3060 = T_3056 | T_3057;
+ assign T_3061 = T_3060[1];
+ assign T_3062 = {T_3059,T_3061};
+ assign tgtPageUpdate = {T_3054,T_3062};
+ assign tgtPageReplEn = doTgtPageRepl ? tgtPageRepl : 1'h0;
+ assign doPageRepl = doIdxPageRepl | doTgtPageRepl;
+ assign pageReplEn = idxPageReplEn | tgtPageReplEn;
+ assign T_3068 = r_btb_update_valid & doPageRepl;
+ assign T_3072 = T_3070 == 3'h5;
+ assign T_3074 = 1'h1 & T_3072;
+ assign T_3077 = T_3070 + 1'h1;
+ assign T_3078 = T_3077[2:0];
+ assign T_3079 = T_3074 ? 1'h0 : T_3078;
+ assign T_3080 = T_3068 & T_3072;
+ assign T_3082 = 1'h1 << T_3070;
+ assign T_3083 = io_req_bits_addr == r_btb_update_bits_target;
+ assign T_3085 = reset == 1'h0;
+ assign T_3087 = T_3083 == 1'h0;
+ assign T_3089 = reset == 1'h0;
+ assign T_3090 = r_btb_update_bits_prediction_valid ? r_btb_update_bits_prediction_bits_entry : nextRepl;
+ assign T_3091 = T_593 | T_903;
+ assign T_3092 = pageReplEn & T_3091;
+ assign T_3094 = T_3092 != 1'h0;
+ assign T_3095 = T_598 | T_908;
+ assign T_3096 = pageReplEn & T_3095;
+ assign T_3098 = T_3096 != 1'h0;
+ assign T_3099 = T_603 | T_913;
+ assign T_3100 = pageReplEn & T_3099;
+ assign T_3102 = T_3100 != 1'h0;
+ assign T_3103 = T_608 | T_918;
+ assign T_3104 = pageReplEn & T_3103;
+ assign T_3106 = T_3104 != 1'h0;
+ assign T_3107 = T_613 | T_923;
+ assign T_3108 = pageReplEn & T_3107;
+ assign T_3110 = T_3108 != 1'h0;
+ assign T_3111 = T_618 | T_928;
+ assign T_3112 = pageReplEn & T_3111;
+ assign T_3114 = T_3112 != 1'h0;
+ assign T_3115 = T_623 | T_933;
+ assign T_3116 = pageReplEn & T_3115;
+ assign T_3118 = T_3116 != 1'h0;
+ assign T_3119 = T_628 | T_938;
+ assign T_3120 = pageReplEn & T_3119;
+ assign T_3122 = T_3120 != 1'h0;
+ assign T_3123 = T_633 | T_943;
+ assign T_3124 = pageReplEn & T_3123;
+ assign T_3126 = T_3124 != 1'h0;
+ assign T_3127 = T_638 | T_948;
+ assign T_3128 = pageReplEn & T_3127;
+ assign T_3130 = T_3128 != 1'h0;
+ assign T_3131 = T_643 | T_953;
+ assign T_3132 = pageReplEn & T_3131;
+ assign T_3134 = T_3132 != 1'h0;
+ assign T_3135 = T_648 | T_958;
+ assign T_3136 = pageReplEn & T_3135;
+ assign T_3138 = T_3136 != 1'h0;
+ assign T_3139 = T_653 | T_963;
+ assign T_3140 = pageReplEn & T_3139;
+ assign T_3142 = T_3140 != 1'h0;
+ assign T_3143 = T_658 | T_968;
+ assign T_3144 = pageReplEn & T_3143;
+ assign T_3146 = T_3144 != 1'h0;
+ assign T_3147 = T_663 | T_973;
+ assign T_3148 = pageReplEn & T_3147;
+ assign T_3150 = T_3148 != 1'h0;
+ assign T_3151 = T_668 | T_978;
+ assign T_3152 = pageReplEn & T_3151;
+ assign T_3154 = T_3152 != 1'h0;
+ assign T_3155 = T_673 | T_983;
+ assign T_3156 = pageReplEn & T_3155;
+ assign T_3158 = T_3156 != 1'h0;
+ assign T_3159 = T_678 | T_988;
+ assign T_3160 = pageReplEn & T_3159;
+ assign T_3162 = T_3160 != 1'h0;
+ assign T_3163 = T_683 | T_993;
+ assign T_3164 = pageReplEn & T_3163;
+ assign T_3166 = T_3164 != 1'h0;
+ assign T_3167 = T_688 | T_998;
+ assign T_3168 = pageReplEn & T_3167;
+ assign T_3170 = T_3168 != 1'h0;
+ assign T_3171 = T_693 | T_1003;
+ assign T_3172 = pageReplEn & T_3171;
+ assign T_3174 = T_3172 != 1'h0;
+ assign T_3175 = T_698 | T_1008;
+ assign T_3176 = pageReplEn & T_3175;
+ assign T_3178 = T_3176 != 1'h0;
+ assign T_3179 = T_703 | T_1013;
+ assign T_3180 = pageReplEn & T_3179;
+ assign T_3182 = T_3180 != 1'h0;
+ assign T_3183 = T_708 | T_1018;
+ assign T_3184 = pageReplEn & T_3183;
+ assign T_3186 = T_3184 != 1'h0;
+ assign T_3187 = T_713 | T_1023;
+ assign T_3188 = pageReplEn & T_3187;
+ assign T_3190 = T_3188 != 1'h0;
+ assign T_3191 = T_718 | T_1028;
+ assign T_3192 = pageReplEn & T_3191;
+ assign T_3194 = T_3192 != 1'h0;
+ assign T_3195 = T_723 | T_1033;
+ assign T_3196 = pageReplEn & T_3195;
+ assign T_3198 = T_3196 != 1'h0;
+ assign T_3199 = T_728 | T_1038;
+ assign T_3200 = pageReplEn & T_3199;
+ assign T_3202 = T_3200 != 1'h0;
+ assign T_3203 = T_733 | T_1043;
+ assign T_3204 = pageReplEn & T_3203;
+ assign T_3206 = T_3204 != 1'h0;
+ assign T_3207 = T_738 | T_1048;
+ assign T_3208 = pageReplEn & T_3207;
+ assign T_3210 = T_3208 != 1'h0;
+ assign T_3211 = T_743 | T_1053;
+ assign T_3212 = pageReplEn & T_3211;
+ assign T_3214 = T_3212 != 1'h0;
+ assign T_3215 = T_748 | T_1058;
+ assign T_3216 = pageReplEn & T_3215;
+ assign T_3218 = T_3216 != 1'h0;
+ assign T_3219 = T_753 | T_1063;
+ assign T_3220 = pageReplEn & T_3219;
+ assign T_3222 = T_3220 != 1'h0;
+ assign T_3223 = T_758 | T_1068;
+ assign T_3224 = pageReplEn & T_3223;
+ assign T_3226 = T_3224 != 1'h0;
+ assign T_3227 = T_763 | T_1073;
+ assign T_3228 = pageReplEn & T_3227;
+ assign T_3230 = T_3228 != 1'h0;
+ assign T_3231 = T_768 | T_1078;
+ assign T_3232 = pageReplEn & T_3231;
+ assign T_3234 = T_3232 != 1'h0;
+ assign T_3235 = T_773 | T_1083;
+ assign T_3236 = pageReplEn & T_3235;
+ assign T_3238 = T_3236 != 1'h0;
+ assign T_3239 = T_778 | T_1088;
+ assign T_3240 = pageReplEn & T_3239;
+ assign T_3242 = T_3240 != 1'h0;
+ assign T_3243 = T_783 | T_1093;
+ assign T_3244 = pageReplEn & T_3243;
+ assign T_3246 = T_3244 != 1'h0;
+ assign T_3247 = T_788 | T_1098;
+ assign T_3248 = pageReplEn & T_3247;
+ assign T_3250 = T_3248 != 1'h0;
+ assign T_3251 = T_793 | T_1103;
+ assign T_3252 = pageReplEn & T_3251;
+ assign T_3254 = T_3252 != 1'h0;
+ assign T_3255 = T_798 | T_1108;
+ assign T_3256 = pageReplEn & T_3255;
+ assign T_3258 = T_3256 != 1'h0;
+ assign T_3259 = T_803 | T_1113;
+ assign T_3260 = pageReplEn & T_3259;
+ assign T_3262 = T_3260 != 1'h0;
+ assign T_3263 = T_808 | T_1118;
+ assign T_3264 = pageReplEn & T_3263;
+ assign T_3266 = T_3264 != 1'h0;
+ assign T_3267 = T_813 | T_1123;
+ assign T_3268 = pageReplEn & T_3267;
+ assign T_3270 = T_3268 != 1'h0;
+ assign T_3271 = T_818 | T_1128;
+ assign T_3272 = pageReplEn & T_3271;
+ assign T_3274 = T_3272 != 1'h0;
+ assign T_3275 = T_823 | T_1133;
+ assign T_3276 = pageReplEn & T_3275;
+ assign T_3278 = T_3276 != 1'h0;
+ assign T_3279 = T_828 | T_1138;
+ assign T_3280 = pageReplEn & T_3279;
+ assign T_3282 = T_3280 != 1'h0;
+ assign T_3283 = T_833 | T_1143;
+ assign T_3284 = pageReplEn & T_3283;
+ assign T_3286 = T_3284 != 1'h0;
+ assign T_3287 = T_838 | T_1148;
+ assign T_3288 = pageReplEn & T_3287;
+ assign T_3290 = T_3288 != 1'h0;
+ assign T_3291 = T_843 | T_1153;
+ assign T_3292 = pageReplEn & T_3291;
+ assign T_3294 = T_3292 != 1'h0;
+ assign T_3295 = T_848 | T_1158;
+ assign T_3296 = pageReplEn & T_3295;
+ assign T_3298 = T_3296 != 1'h0;
+ assign T_3299 = T_853 | T_1163;
+ assign T_3300 = pageReplEn & T_3299;
+ assign T_3302 = T_3300 != 1'h0;
+ assign T_3303 = T_858 | T_1168;
+ assign T_3304 = pageReplEn & T_3303;
+ assign T_3306 = T_3304 != 1'h0;
+ assign T_3307 = T_863 | T_1173;
+ assign T_3308 = pageReplEn & T_3307;
+ assign T_3310 = T_3308 != 1'h0;
+ assign T_3311 = T_868 | T_1178;
+ assign T_3312 = pageReplEn & T_3311;
+ assign T_3314 = T_3312 != 1'h0;
+ assign T_3315 = T_873 | T_1183;
+ assign T_3316 = pageReplEn & T_3315;
+ assign T_3318 = T_3316 != 1'h0;
+ assign T_3319 = T_878 | T_1188;
+ assign T_3320 = pageReplEn & T_3319;
+ assign T_3322 = T_3320 != 1'h0;
+ assign T_3323 = T_883 | T_1193;
+ assign T_3324 = pageReplEn & T_3323;
+ assign T_3326 = T_3324 != 1'h0;
+ assign T_3327 = T_888 | T_1198;
+ assign T_3328 = pageReplEn & T_3327;
+ assign T_3330 = T_3328 != 1'h0;
+ assign T_3331 = T_893 | T_1203;
+ assign T_3332 = pageReplEn & T_3331;
+ assign T_3334 = T_3332 != 1'h0;
+ assign T_3335 = T_898 | T_1208;
+ assign T_3336 = pageReplEn & T_3335;
+ assign T_3338 = T_3336 != 1'h0;
+ assign T_3340_0 = T_3094;
+ assign T_3340_1 = T_3098;
+ assign T_3340_2 = T_3102;
+ assign T_3340_3 = T_3106;
+ assign T_3340_4 = T_3110;
+ assign T_3340_5 = T_3114;
+ assign T_3340_6 = T_3118;
+ assign T_3340_7 = T_3122;
+ assign T_3340_8 = T_3126;
+ assign T_3340_9 = T_3130;
+ assign T_3340_10 = T_3134;
+ assign T_3340_11 = T_3138;
+ assign T_3340_12 = T_3142;
+ assign T_3340_13 = T_3146;
+ assign T_3340_14 = T_3150;
+ assign T_3340_15 = T_3154;
+ assign T_3340_16 = T_3158;
+ assign T_3340_17 = T_3162;
+ assign T_3340_18 = T_3166;
+ assign T_3340_19 = T_3170;
+ assign T_3340_20 = T_3174;
+ assign T_3340_21 = T_3178;
+ assign T_3340_22 = T_3182;
+ assign T_3340_23 = T_3186;
+ assign T_3340_24 = T_3190;
+ assign T_3340_25 = T_3194;
+ assign T_3340_26 = T_3198;
+ assign T_3340_27 = T_3202;
+ assign T_3340_28 = T_3206;
+ assign T_3340_29 = T_3210;
+ assign T_3340_30 = T_3214;
+ assign T_3340_31 = T_3218;
+ assign T_3340_32 = T_3222;
+ assign T_3340_33 = T_3226;
+ assign T_3340_34 = T_3230;
+ assign T_3340_35 = T_3234;
+ assign T_3340_36 = T_3238;
+ assign T_3340_37 = T_3242;
+ assign T_3340_38 = T_3246;
+ assign T_3340_39 = T_3250;
+ assign T_3340_40 = T_3254;
+ assign T_3340_41 = T_3258;
+ assign T_3340_42 = T_3262;
+ assign T_3340_43 = T_3266;
+ assign T_3340_44 = T_3270;
+ assign T_3340_45 = T_3274;
+ assign T_3340_46 = T_3278;
+ assign T_3340_47 = T_3282;
+ assign T_3340_48 = T_3286;
+ assign T_3340_49 = T_3290;
+ assign T_3340_50 = T_3294;
+ assign T_3340_51 = T_3298;
+ assign T_3340_52 = T_3302;
+ assign T_3340_53 = T_3306;
+ assign T_3340_54 = T_3310;
+ assign T_3340_55 = T_3314;
+ assign T_3340_56 = T_3318;
+ assign T_3340_57 = T_3322;
+ assign T_3340_58 = T_3326;
+ assign T_3340_59 = T_3330;
+ assign T_3340_60 = T_3334;
+ assign T_3340_61 = T_3338;
+ assign T_3404 = {T_3340_60,T_3340_59};
+ assign T_3405 = {T_3340_61,T_3404};
+ assign T_3406 = {T_3340_58,T_3340_57};
+ assign T_3407 = {T_3340_56,T_3340_55};
+ assign T_3408 = {T_3406,T_3407};
+ assign T_3409 = {T_3405,T_3408};
+ assign T_3410 = {T_3340_54,T_3340_53};
+ assign T_3411 = {T_3340_52,T_3340_51};
+ assign T_3412 = {T_3410,T_3411};
+ assign T_3413 = {T_3340_50,T_3340_49};
+ assign T_3414 = {T_3340_48,T_3340_47};
+ assign T_3415 = {T_3413,T_3414};
+ assign T_3416 = {T_3412,T_3415};
+ assign T_3417 = {T_3409,T_3416};
+ assign T_3418 = {T_3340_46,T_3340_45};
+ assign T_3419 = {T_3340_44,T_3340_43};
+ assign T_3420 = {T_3418,T_3419};
+ assign T_3421 = {T_3340_42,T_3340_41};
+ assign T_3422 = {T_3340_40,T_3340_39};
+ assign T_3423 = {T_3421,T_3422};
+ assign T_3424 = {T_3420,T_3423};
+ assign T_3425 = {T_3340_38,T_3340_37};
+ assign T_3426 = {T_3340_36,T_3340_35};
+ assign T_3427 = {T_3425,T_3426};
+ assign T_3428 = {T_3340_34,T_3340_33};
+ assign T_3429 = {T_3340_32,T_3340_31};
+ assign T_3430 = {T_3428,T_3429};
+ assign T_3431 = {T_3427,T_3430};
+ assign T_3432 = {T_3424,T_3431};
+ assign T_3433 = {T_3417,T_3432};
+ assign T_3434 = {T_3340_29,T_3340_28};
+ assign T_3435 = {T_3340_30,T_3434};
+ assign T_3436 = {T_3340_27,T_3340_26};
+ assign T_3437 = {T_3340_25,T_3340_24};
+ assign T_3438 = {T_3436,T_3437};
+ assign T_3439 = {T_3435,T_3438};
+ assign T_3440 = {T_3340_23,T_3340_22};
+ assign T_3441 = {T_3340_21,T_3340_20};
+ assign T_3442 = {T_3440,T_3441};
+ assign T_3443 = {T_3340_19,T_3340_18};
+ assign T_3444 = {T_3340_17,T_3340_16};
+ assign T_3445 = {T_3443,T_3444};
+ assign T_3446 = {T_3442,T_3445};
+ assign T_3447 = {T_3439,T_3446};
+ assign T_3448 = {T_3340_15,T_3340_14};
+ assign T_3449 = {T_3340_13,T_3340_12};
+ assign T_3450 = {T_3448,T_3449};
+ assign T_3451 = {T_3340_11,T_3340_10};
+ assign T_3452 = {T_3340_9,T_3340_8};
+ assign T_3453 = {T_3451,T_3452};
+ assign T_3454 = {T_3450,T_3453};
+ assign T_3455 = {T_3340_7,T_3340_6};
+ assign T_3456 = {T_3340_5,T_3340_4};
+ assign T_3457 = {T_3455,T_3456};
+ assign T_3458 = {T_3340_3,T_3340_2};
+ assign T_3459 = {T_3340_1,T_3340_0};
+ assign T_3460 = {T_3458,T_3459};
+ assign T_3461 = {T_3457,T_3460};
+ assign T_3462 = {T_3454,T_3461};
+ assign T_3463 = {T_3447,T_3462};
+ assign T_3464 = {T_3433,T_3463};
+ assign T_3466 = 1'h1 << T_3090;
+ assign T_3467 = ~ T_3464;
+ assign T_3468 = idxValid & T_3467;
+ assign T_3469 = T_3468 | T_3466;
+ assign GEN_0 = r_btb_update_bits_isReturn;
+ assign GEN_1 = r_btb_update_bits_isJump;
+ assign T_3479 = {2'h1,2'h1};
+ assign T_3480 = {2'h1,T_3479};
+ assign T_3481 = idxPageUpdateOH & T_3480;
+ assign T_3483 = T_3481 != 1'h0;
+ assign T_3484 = T_3483 ? doIdxPageRepl : doTgtPageRepl;
+ assign T_3485 = r_btb_update_bits_pc[38:12];
+ assign T_3486 = io_req_bits_addr[38:12];
+ assign T_3487 = T_3483 ? T_3485 : T_3486;
+ assign T_3488 = pageReplEn[0];
+ assign T_3489 = T_3484 & T_3488;
+ assign T_3492 = pageReplEn[2];
+ assign T_3493 = T_3484 & T_3492;
+ assign T_3496 = pageReplEn[4];
+ assign T_3497 = T_3484 & T_3496;
+ assign T_3500 = T_3483 ? doTgtPageRepl : doIdxPageRepl;
+ assign T_3501 = io_req_bits_addr[38:12];
+ assign T_3502 = r_btb_update_bits_pc[38:12];
+ assign T_3503 = T_3483 ? T_3501 : T_3502;
+ assign T_3504 = pageReplEn[1];
+ assign T_3505 = T_3500 & T_3504;
+ assign T_3508 = pageReplEn[3];
+ assign T_3509 = T_3500 & T_3508;
+ assign T_3512 = pageReplEn[5];
+ assign T_3513 = T_3500 & T_3512;
+ assign T_3516 = pageValid | pageReplEn;
+ assign T_3520 = hits != 1'h0;
+ assign T_3521 = hits[0];
+ assign T_3522 = hits[1];
+ assign T_3523 = hits[2];
+ assign T_3524 = hits[3];
+ assign T_3525 = hits[4];
+ assign T_3526 = hits[5];
+ assign T_3527 = hits[6];
+ assign T_3528 = hits[7];
+ assign T_3529 = hits[8];
+ assign T_3530 = hits[9];
+ assign T_3531 = hits[10];
+ assign T_3532 = hits[11];
+ assign T_3533 = hits[12];
+ assign T_3534 = hits[13];
+ assign T_3535 = hits[14];
+ assign T_3536 = hits[15];
+ assign T_3537 = hits[16];
+ assign T_3538 = hits[17];
+ assign T_3539 = hits[18];
+ assign T_3540 = hits[19];
+ assign T_3541 = hits[20];
+ assign T_3542 = hits[21];
+ assign T_3543 = hits[22];
+ assign T_3544 = hits[23];
+ assign T_3545 = hits[24];
+ assign T_3546 = hits[25];
+ assign T_3547 = hits[26];
+ assign T_3548 = hits[27];
+ assign T_3549 = hits[28];
+ assign T_3550 = hits[29];
+ assign T_3551 = hits[30];
+ assign T_3552 = hits[31];
+ assign T_3553 = hits[32];
+ assign T_3554 = hits[33];
+ assign T_3555 = hits[34];
+ assign T_3556 = hits[35];
+ assign T_3557 = hits[36];
+ assign T_3558 = hits[37];
+ assign T_3559 = hits[38];
+ assign T_3560 = hits[39];
+ assign T_3561 = hits[40];
+ assign T_3562 = hits[41];
+ assign T_3563 = hits[42];
+ assign T_3564 = hits[43];
+ assign T_3565 = hits[44];
+ assign T_3566 = hits[45];
+ assign T_3567 = hits[46];
+ assign T_3568 = hits[47];
+ assign T_3569 = hits[48];
+ assign T_3570 = hits[49];
+ assign T_3571 = hits[50];
+ assign T_3572 = hits[51];
+ assign T_3573 = hits[52];
+ assign T_3574 = hits[53];
+ assign T_3575 = hits[54];
+ assign T_3576 = hits[55];
+ assign T_3577 = hits[56];
+ assign T_3578 = hits[57];
+ assign T_3579 = hits[58];
+ assign T_3580 = hits[59];
+ assign T_3581 = hits[60];
+ assign T_3582 = hits[61];
+ assign T_3584 = T_3521 ? T_903 : 1'h0;
+ assign T_3586 = T_3522 ? T_908 : 1'h0;
+ assign T_3588 = T_3523 ? T_913 : 1'h0;
+ assign T_3590 = T_3524 ? T_918 : 1'h0;
+ assign T_3592 = T_3525 ? T_923 : 1'h0;
+ assign T_3594 = T_3526 ? T_928 : 1'h0;
+ assign T_3596 = T_3527 ? T_933 : 1'h0;
+ assign T_3598 = T_3528 ? T_938 : 1'h0;
+ assign T_3600 = T_3529 ? T_943 : 1'h0;
+ assign T_3602 = T_3530 ? T_948 : 1'h0;
+ assign T_3604 = T_3531 ? T_953 : 1'h0;
+ assign T_3606 = T_3532 ? T_958 : 1'h0;
+ assign T_3608 = T_3533 ? T_963 : 1'h0;
+ assign T_3610 = T_3534 ? T_968 : 1'h0;
+ assign T_3612 = T_3535 ? T_973 : 1'h0;
+ assign T_3614 = T_3536 ? T_978 : 1'h0;
+ assign T_3616 = T_3537 ? T_983 : 1'h0;
+ assign T_3618 = T_3538 ? T_988 : 1'h0;
+ assign T_3620 = T_3539 ? T_993 : 1'h0;
+ assign T_3622 = T_3540 ? T_998 : 1'h0;
+ assign T_3624 = T_3541 ? T_1003 : 1'h0;
+ assign T_3626 = T_3542 ? T_1008 : 1'h0;
+ assign T_3628 = T_3543 ? T_1013 : 1'h0;
+ assign T_3630 = T_3544 ? T_1018 : 1'h0;
+ assign T_3632 = T_3545 ? T_1023 : 1'h0;
+ assign T_3634 = T_3546 ? T_1028 : 1'h0;
+ assign T_3636 = T_3547 ? T_1033 : 1'h0;
+ assign T_3638 = T_3548 ? T_1038 : 1'h0;
+ assign T_3640 = T_3549 ? T_1043 : 1'h0;
+ assign T_3642 = T_3550 ? T_1048 : 1'h0;
+ assign T_3644 = T_3551 ? T_1053 : 1'h0;
+ assign T_3646 = T_3552 ? T_1058 : 1'h0;
+ assign T_3648 = T_3553 ? T_1063 : 1'h0;
+ assign T_3650 = T_3554 ? T_1068 : 1'h0;
+ assign T_3652 = T_3555 ? T_1073 : 1'h0;
+ assign T_3654 = T_3556 ? T_1078 : 1'h0;
+ assign T_3656 = T_3557 ? T_1083 : 1'h0;
+ assign T_3658 = T_3558 ? T_1088 : 1'h0;
+ assign T_3660 = T_3559 ? T_1093 : 1'h0;
+ assign T_3662 = T_3560 ? T_1098 : 1'h0;
+ assign T_3664 = T_3561 ? T_1103 : 1'h0;
+ assign T_3666 = T_3562 ? T_1108 : 1'h0;
+ assign T_3668 = T_3563 ? T_1113 : 1'h0;
+ assign T_3670 = T_3564 ? T_1118 : 1'h0;
+ assign T_3672 = T_3565 ? T_1123 : 1'h0;
+ assign T_3674 = T_3566 ? T_1128 : 1'h0;
+ assign T_3676 = T_3567 ? T_1133 : 1'h0;
+ assign T_3678 = T_3568 ? T_1138 : 1'h0;
+ assign T_3680 = T_3569 ? T_1143 : 1'h0;
+ assign T_3682 = T_3570 ? T_1148 : 1'h0;
+ assign T_3684 = T_3571 ? T_1153 : 1'h0;
+ assign T_3686 = T_3572 ? T_1158 : 1'h0;
+ assign T_3688 = T_3573 ? T_1163 : 1'h0;
+ assign T_3690 = T_3574 ? T_1168 : 1'h0;
+ assign T_3692 = T_3575 ? T_1173 : 1'h0;
+ assign T_3694 = T_3576 ? T_1178 : 1'h0;
+ assign T_3696 = T_3577 ? T_1183 : 1'h0;
+ assign T_3698 = T_3578 ? T_1188 : 1'h0;
+ assign T_3700 = T_3579 ? T_1193 : 1'h0;
+ assign T_3702 = T_3580 ? T_1198 : 1'h0;
+ assign T_3704 = T_3581 ? T_1203 : 1'h0;
+ assign T_3706 = T_3582 ? T_1208 : 1'h0;
+ assign T_3708 = T_3584 | T_3586;
+ assign T_3709 = T_3708 | T_3588;
+ assign T_3710 = T_3709 | T_3590;
+ assign T_3711 = T_3710 | T_3592;
+ assign T_3712 = T_3711 | T_3594;
+ assign T_3713 = T_3712 | T_3596;
+ assign T_3714 = T_3713 | T_3598;
+ assign T_3715 = T_3714 | T_3600;
+ assign T_3716 = T_3715 | T_3602;
+ assign T_3717 = T_3716 | T_3604;
+ assign T_3718 = T_3717 | T_3606;
+ assign T_3719 = T_3718 | T_3608;
+ assign T_3720 = T_3719 | T_3610;
+ assign T_3721 = T_3720 | T_3612;
+ assign T_3722 = T_3721 | T_3614;
+ assign T_3723 = T_3722 | T_3616;
+ assign T_3724 = T_3723 | T_3618;
+ assign T_3725 = T_3724 | T_3620;
+ assign T_3726 = T_3725 | T_3622;
+ assign T_3727 = T_3726 | T_3624;
+ assign T_3728 = T_3727 | T_3626;
+ assign T_3729 = T_3728 | T_3628;
+ assign T_3730 = T_3729 | T_3630;
+ assign T_3731 = T_3730 | T_3632;
+ assign T_3732 = T_3731 | T_3634;
+ assign T_3733 = T_3732 | T_3636;
+ assign T_3734 = T_3733 | T_3638;
+ assign T_3735 = T_3734 | T_3640;
+ assign T_3736 = T_3735 | T_3642;
+ assign T_3737 = T_3736 | T_3644;
+ assign T_3738 = T_3737 | T_3646;
+ assign T_3739 = T_3738 | T_3648;
+ assign T_3740 = T_3739 | T_3650;
+ assign T_3741 = T_3740 | T_3652;
+ assign T_3742 = T_3741 | T_3654;
+ assign T_3743 = T_3742 | T_3656;
+ assign T_3744 = T_3743 | T_3658;
+ assign T_3745 = T_3744 | T_3660;
+ assign T_3746 = T_3745 | T_3662;
+ assign T_3747 = T_3746 | T_3664;
+ assign T_3748 = T_3747 | T_3666;
+ assign T_3749 = T_3748 | T_3668;
+ assign T_3750 = T_3749 | T_3670;
+ assign T_3751 = T_3750 | T_3672;
+ assign T_3752 = T_3751 | T_3674;
+ assign T_3753 = T_3752 | T_3676;
+ assign T_3754 = T_3753 | T_3678;
+ assign T_3755 = T_3754 | T_3680;
+ assign T_3756 = T_3755 | T_3682;
+ assign T_3757 = T_3756 | T_3684;
+ assign T_3758 = T_3757 | T_3686;
+ assign T_3759 = T_3758 | T_3688;
+ assign T_3760 = T_3759 | T_3690;
+ assign T_3761 = T_3760 | T_3692;
+ assign T_3762 = T_3761 | T_3694;
+ assign T_3763 = T_3762 | T_3696;
+ assign T_3764 = T_3763 | T_3698;
+ assign T_3765 = T_3764 | T_3700;
+ assign T_3766 = T_3765 | T_3702;
+ assign T_3767 = T_3766 | T_3704;
+ assign T_3768 = T_3767 | T_3706;
+ assign T_3769 = T_3768;
+ assign T_3770 = T_3769[0];
+ assign T_3771 = T_3769[1];
+ assign T_3772 = T_3769[2];
+ assign T_3773 = T_3769[3];
+ assign T_3774 = T_3769[4];
+ assign T_3775 = T_3769[5];
+ assign T_3789 = T_3770 ? pages_T_3777_data : 1'h0;
+ assign T_3791 = T_3771 ? pages_T_3779_data : 1'h0;
+ assign T_3793 = T_3772 ? pages_T_3781_data : 1'h0;
+ assign T_3795 = T_3773 ? pages_T_3783_data : 1'h0;
+ assign T_3797 = T_3774 ? pages_T_3785_data : 1'h0;
+ assign T_3799 = T_3775 ? pages_T_3787_data : 1'h0;
+ assign T_3801 = T_3789 | T_3791;
+ assign T_3802 = T_3801 | T_3793;
+ assign T_3803 = T_3802 | T_3795;
+ assign T_3804 = T_3803 | T_3797;
+ assign T_3805 = T_3804 | T_3799;
+ assign T_3806 = T_3805;
+ assign T_3807 = hits[0];
+ assign T_3808 = hits[1];
+ assign T_3809 = hits[2];
+ assign T_3810 = hits[3];
+ assign T_3811 = hits[4];
+ assign T_3812 = hits[5];
+ assign T_3813 = hits[6];
+ assign T_3814 = hits[7];
+ assign T_3815 = hits[8];
+ assign T_3816 = hits[9];
+ assign T_3817 = hits[10];
+ assign T_3818 = hits[11];
+ assign T_3819 = hits[12];
+ assign T_3820 = hits[13];
+ assign T_3821 = hits[14];
+ assign T_3822 = hits[15];
+ assign T_3823 = hits[16];
+ assign T_3824 = hits[17];
+ assign T_3825 = hits[18];
+ assign T_3826 = hits[19];
+ assign T_3827 = hits[20];
+ assign T_3828 = hits[21];
+ assign T_3829 = hits[22];
+ assign T_3830 = hits[23];
+ assign T_3831 = hits[24];
+ assign T_3832 = hits[25];
+ assign T_3833 = hits[26];
+ assign T_3834 = hits[27];
+ assign T_3835 = hits[28];
+ assign T_3836 = hits[29];
+ assign T_3837 = hits[30];
+ assign T_3838 = hits[31];
+ assign T_3839 = hits[32];
+ assign T_3840 = hits[33];
+ assign T_3841 = hits[34];
+ assign T_3842 = hits[35];
+ assign T_3843 = hits[36];
+ assign T_3844 = hits[37];
+ assign T_3845 = hits[38];
+ assign T_3846 = hits[39];
+ assign T_3847 = hits[40];
+ assign T_3848 = hits[41];
+ assign T_3849 = hits[42];
+ assign T_3850 = hits[43];
+ assign T_3851 = hits[44];
+ assign T_3852 = hits[45];
+ assign T_3853 = hits[46];
+ assign T_3854 = hits[47];
+ assign T_3855 = hits[48];
+ assign T_3856 = hits[49];
+ assign T_3857 = hits[50];
+ assign T_3858 = hits[51];
+ assign T_3859 = hits[52];
+ assign T_3860 = hits[53];
+ assign T_3861 = hits[54];
+ assign T_3862 = hits[55];
+ assign T_3863 = hits[56];
+ assign T_3864 = hits[57];
+ assign T_3865 = hits[58];
+ assign T_3866 = hits[59];
+ assign T_3867 = hits[60];
+ assign T_3868 = hits[61];
+ assign T_3994 = T_3807 ? tgts_T_3870_data : 1'h0;
+ assign T_3996 = T_3808 ? tgts_T_3872_data : 1'h0;
+ assign T_3998 = T_3809 ? tgts_T_3874_data : 1'h0;
+ assign T_4000 = T_3810 ? tgts_T_3876_data : 1'h0;
+ assign T_4002 = T_3811 ? tgts_T_3878_data : 1'h0;
+ assign T_4004 = T_3812 ? tgts_T_3880_data : 1'h0;
+ assign T_4006 = T_3813 ? tgts_T_3882_data : 1'h0;
+ assign T_4008 = T_3814 ? tgts_T_3884_data : 1'h0;
+ assign T_4010 = T_3815 ? tgts_T_3886_data : 1'h0;
+ assign T_4012 = T_3816 ? tgts_T_3888_data : 1'h0;
+ assign T_4014 = T_3817 ? tgts_T_3890_data : 1'h0;
+ assign T_4016 = T_3818 ? tgts_T_3892_data : 1'h0;
+ assign T_4018 = T_3819 ? tgts_T_3894_data : 1'h0;
+ assign T_4020 = T_3820 ? tgts_T_3896_data : 1'h0;
+ assign T_4022 = T_3821 ? tgts_T_3898_data : 1'h0;
+ assign T_4024 = T_3822 ? tgts_T_3900_data : 1'h0;
+ assign T_4026 = T_3823 ? tgts_T_3902_data : 1'h0;
+ assign T_4028 = T_3824 ? tgts_T_3904_data : 1'h0;
+ assign T_4030 = T_3825 ? tgts_T_3906_data : 1'h0;
+ assign T_4032 = T_3826 ? tgts_T_3908_data : 1'h0;
+ assign T_4034 = T_3827 ? tgts_T_3910_data : 1'h0;
+ assign T_4036 = T_3828 ? tgts_T_3912_data : 1'h0;
+ assign T_4038 = T_3829 ? tgts_T_3914_data : 1'h0;
+ assign T_4040 = T_3830 ? tgts_T_3916_data : 1'h0;
+ assign T_4042 = T_3831 ? tgts_T_3918_data : 1'h0;
+ assign T_4044 = T_3832 ? tgts_T_3920_data : 1'h0;
+ assign T_4046 = T_3833 ? tgts_T_3922_data : 1'h0;
+ assign T_4048 = T_3834 ? tgts_T_3924_data : 1'h0;
+ assign T_4050 = T_3835 ? tgts_T_3926_data : 1'h0;
+ assign T_4052 = T_3836 ? tgts_T_3928_data : 1'h0;
+ assign T_4054 = T_3837 ? tgts_T_3930_data : 1'h0;
+ assign T_4056 = T_3838 ? tgts_T_3932_data : 1'h0;
+ assign T_4058 = T_3839 ? tgts_T_3934_data : 1'h0;
+ assign T_4060 = T_3840 ? tgts_T_3936_data : 1'h0;
+ assign T_4062 = T_3841 ? tgts_T_3938_data : 1'h0;
+ assign T_4064 = T_3842 ? tgts_T_3940_data : 1'h0;
+ assign T_4066 = T_3843 ? tgts_T_3942_data : 1'h0;
+ assign T_4068 = T_3844 ? tgts_T_3944_data : 1'h0;
+ assign T_4070 = T_3845 ? tgts_T_3946_data : 1'h0;
+ assign T_4072 = T_3846 ? tgts_T_3948_data : 1'h0;
+ assign T_4074 = T_3847 ? tgts_T_3950_data : 1'h0;
+ assign T_4076 = T_3848 ? tgts_T_3952_data : 1'h0;
+ assign T_4078 = T_3849 ? tgts_T_3954_data : 1'h0;
+ assign T_4080 = T_3850 ? tgts_T_3956_data : 1'h0;
+ assign T_4082 = T_3851 ? tgts_T_3958_data : 1'h0;
+ assign T_4084 = T_3852 ? tgts_T_3960_data : 1'h0;
+ assign T_4086 = T_3853 ? tgts_T_3962_data : 1'h0;
+ assign T_4088 = T_3854 ? tgts_T_3964_data : 1'h0;
+ assign T_4090 = T_3855 ? tgts_T_3966_data : 1'h0;
+ assign T_4092 = T_3856 ? tgts_T_3968_data : 1'h0;
+ assign T_4094 = T_3857 ? tgts_T_3970_data : 1'h0;
+ assign T_4096 = T_3858 ? tgts_T_3972_data : 1'h0;
+ assign T_4098 = T_3859 ? tgts_T_3974_data : 1'h0;
+ assign T_4100 = T_3860 ? tgts_T_3976_data : 1'h0;
+ assign T_4102 = T_3861 ? tgts_T_3978_data : 1'h0;
+ assign T_4104 = T_3862 ? tgts_T_3980_data : 1'h0;
+ assign T_4106 = T_3863 ? tgts_T_3982_data : 1'h0;
+ assign T_4108 = T_3864 ? tgts_T_3984_data : 1'h0;
+ assign T_4110 = T_3865 ? tgts_T_3986_data : 1'h0;
+ assign T_4112 = T_3866 ? tgts_T_3988_data : 1'h0;
+ assign T_4114 = T_3867 ? tgts_T_3990_data : 1'h0;
+ assign T_4116 = T_3868 ? tgts_T_3992_data : 1'h0;
+ assign T_4118 = T_3994 | T_3996;
+ assign T_4119 = T_4118 | T_3998;
+ assign T_4120 = T_4119 | T_4000;
+ assign T_4121 = T_4120 | T_4002;
+ assign T_4122 = T_4121 | T_4004;
+ assign T_4123 = T_4122 | T_4006;
+ assign T_4124 = T_4123 | T_4008;
+ assign T_4125 = T_4124 | T_4010;
+ assign T_4126 = T_4125 | T_4012;
+ assign T_4127 = T_4126 | T_4014;
+ assign T_4128 = T_4127 | T_4016;
+ assign T_4129 = T_4128 | T_4018;
+ assign T_4130 = T_4129 | T_4020;
+ assign T_4131 = T_4130 | T_4022;
+ assign T_4132 = T_4131 | T_4024;
+ assign T_4133 = T_4132 | T_4026;
+ assign T_4134 = T_4133 | T_4028;
+ assign T_4135 = T_4134 | T_4030;
+ assign T_4136 = T_4135 | T_4032;
+ assign T_4137 = T_4136 | T_4034;
+ assign T_4138 = T_4137 | T_4036;
+ assign T_4139 = T_4138 | T_4038;
+ assign T_4140 = T_4139 | T_4040;
+ assign T_4141 = T_4140 | T_4042;
+ assign T_4142 = T_4141 | T_4044;
+ assign T_4143 = T_4142 | T_4046;
+ assign T_4144 = T_4143 | T_4048;
+ assign T_4145 = T_4144 | T_4050;
+ assign T_4146 = T_4145 | T_4052;
+ assign T_4147 = T_4146 | T_4054;
+ assign T_4148 = T_4147 | T_4056;
+ assign T_4149 = T_4148 | T_4058;
+ assign T_4150 = T_4149 | T_4060;
+ assign T_4151 = T_4150 | T_4062;
+ assign T_4152 = T_4151 | T_4064;
+ assign T_4153 = T_4152 | T_4066;
+ assign T_4154 = T_4153 | T_4068;
+ assign T_4155 = T_4154 | T_4070;
+ assign T_4156 = T_4155 | T_4072;
+ assign T_4157 = T_4156 | T_4074;
+ assign T_4158 = T_4157 | T_4076;
+ assign T_4159 = T_4158 | T_4078;
+ assign T_4160 = T_4159 | T_4080;
+ assign T_4161 = T_4160 | T_4082;
+ assign T_4162 = T_4161 | T_4084;
+ assign T_4163 = T_4162 | T_4086;
+ assign T_4164 = T_4163 | T_4088;
+ assign T_4165 = T_4164 | T_4090;
+ assign T_4166 = T_4165 | T_4092;
+ assign T_4167 = T_4166 | T_4094;
+ assign T_4168 = T_4167 | T_4096;
+ assign T_4169 = T_4168 | T_4098;
+ assign T_4170 = T_4169 | T_4100;
+ assign T_4171 = T_4170 | T_4102;
+ assign T_4172 = T_4171 | T_4104;
+ assign T_4173 = T_4172 | T_4106;
+ assign T_4174 = T_4173 | T_4108;
+ assign T_4175 = T_4174 | T_4110;
+ assign T_4176 = T_4175 | T_4112;
+ assign T_4177 = T_4176 | T_4114;
+ assign T_4178 = T_4177 | T_4116;
+ assign T_4179 = T_4178;
+ assign T_4180 = {T_3806,T_4179};
+ assign T_4181 = hits[61:32];
+ assign T_4182 = hits[31:0];
+ assign T_4184 = T_4181 != 1'h0;
+ assign T_4185 = T_4181 | T_4182;
+ assign T_4186 = T_4185[31:16];
+ assign T_4187 = T_4185[15:0];
+ assign T_4189 = T_4186 != 1'h0;
+ assign T_4190 = T_4186 | T_4187;
+ assign T_4191 = T_4190[15:8];
+ assign T_4192 = T_4190[7:0];
+ assign T_4194 = T_4191 != 1'h0;
+ assign T_4195 = T_4191 | T_4192;
+ assign T_4196 = T_4195[7:4];
+ assign T_4197 = T_4195[3:0];
+ assign T_4199 = T_4196 != 1'h0;
+ assign T_4200 = T_4196 | T_4197;
+ assign T_4201 = T_4200[3:2];
+ assign T_4202 = T_4200[1:0];
+ assign T_4204 = T_4201 != 1'h0;
+ assign T_4205 = T_4201 | T_4202;
+ assign T_4206 = T_4205[1];
+ assign T_4207 = {T_4204,T_4206};
+ assign T_4208 = {T_4199,T_4207};
+ assign T_4209 = {T_4194,T_4208};
+ assign T_4210 = {T_4189,T_4209};
+ assign T_4211 = {T_4184,T_4210};
+ assign T_4216_T_4542_addr = T_4541;
+ assign T_4216_T_4542_en = 1'h1;
+ assign T_4216_T_4542_clk = clk;
+ assign T_4216_T_4542_data = T_4216[T_4216_T_4542_addr];
+ assign T_4216_T_4549_data = T_4558;
+ assign T_4216_T_4549_addr = T_4548;
+ assign T_4216_T_4549_mask = T_4546 ? 1'h1 : 1'h0;
+ assign T_4216_T_4549_en = T_4546 ? 1'h1 : 1'h0;
+ assign T_4216_T_4549_clk = clk;
+ assign T_4219 = hits[0];
+ assign T_4220 = hits[1];
+ assign T_4221 = hits[2];
+ assign T_4222 = hits[3];
+ assign T_4223 = hits[4];
+ assign T_4224 = hits[5];
+ assign T_4225 = hits[6];
+ assign T_4226 = hits[7];
+ assign T_4227 = hits[8];
+ assign T_4228 = hits[9];
+ assign T_4229 = hits[10];
+ assign T_4230 = hits[11];
+ assign T_4231 = hits[12];
+ assign T_4232 = hits[13];
+ assign T_4233 = hits[14];
+ assign T_4234 = hits[15];
+ assign T_4235 = hits[16];
+ assign T_4236 = hits[17];
+ assign T_4237 = hits[18];
+ assign T_4238 = hits[19];
+ assign T_4239 = hits[20];
+ assign T_4240 = hits[21];
+ assign T_4241 = hits[22];
+ assign T_4242 = hits[23];
+ assign T_4243 = hits[24];
+ assign T_4244 = hits[25];
+ assign T_4245 = hits[26];
+ assign T_4246 = hits[27];
+ assign T_4247 = hits[28];
+ assign T_4248 = hits[29];
+ assign T_4249 = hits[30];
+ assign T_4250 = hits[31];
+ assign T_4251 = hits[32];
+ assign T_4252 = hits[33];
+ assign T_4253 = hits[34];
+ assign T_4254 = hits[35];
+ assign T_4255 = hits[36];
+ assign T_4256 = hits[37];
+ assign T_4257 = hits[38];
+ assign T_4258 = hits[39];
+ assign T_4259 = hits[40];
+ assign T_4260 = hits[41];
+ assign T_4261 = hits[42];
+ assign T_4262 = hits[43];
+ assign T_4263 = hits[44];
+ assign T_4264 = hits[45];
+ assign T_4265 = hits[46];
+ assign T_4266 = hits[47];
+ assign T_4267 = hits[48];
+ assign T_4268 = hits[49];
+ assign T_4269 = hits[50];
+ assign T_4270 = hits[51];
+ assign T_4271 = hits[52];
+ assign T_4272 = hits[53];
+ assign T_4273 = hits[54];
+ assign T_4274 = hits[55];
+ assign T_4275 = hits[56];
+ assign T_4276 = hits[57];
+ assign T_4277 = hits[58];
+ assign T_4278 = hits[59];
+ assign T_4279 = hits[60];
+ assign T_4280 = hits[61];
+ assign T_4282 = isJump_0 << 0;
+ assign T_4283 = T_4219 ? T_4282 : 1'h0;
+ assign T_4285 = isJump_1 << 0;
+ assign T_4286 = T_4220 ? T_4285 : 1'h0;
+ assign T_4288 = isJump_2 << 0;
+ assign T_4289 = T_4221 ? T_4288 : 1'h0;
+ assign T_4291 = isJump_3 << 0;
+ assign T_4292 = T_4222 ? T_4291 : 1'h0;
+ assign T_4294 = isJump_4 << 0;
+ assign T_4295 = T_4223 ? T_4294 : 1'h0;
+ assign T_4297 = isJump_5 << 0;
+ assign T_4298 = T_4224 ? T_4297 : 1'h0;
+ assign T_4300 = isJump_6 << 0;
+ assign T_4301 = T_4225 ? T_4300 : 1'h0;
+ assign T_4303 = isJump_7 << 0;
+ assign T_4304 = T_4226 ? T_4303 : 1'h0;
+ assign T_4306 = isJump_8 << 0;
+ assign T_4307 = T_4227 ? T_4306 : 1'h0;
+ assign T_4309 = isJump_9 << 0;
+ assign T_4310 = T_4228 ? T_4309 : 1'h0;
+ assign T_4312 = isJump_10 << 0;
+ assign T_4313 = T_4229 ? T_4312 : 1'h0;
+ assign T_4315 = isJump_11 << 0;
+ assign T_4316 = T_4230 ? T_4315 : 1'h0;
+ assign T_4318 = isJump_12 << 0;
+ assign T_4319 = T_4231 ? T_4318 : 1'h0;
+ assign T_4321 = isJump_13 << 0;
+ assign T_4322 = T_4232 ? T_4321 : 1'h0;
+ assign T_4324 = isJump_14 << 0;
+ assign T_4325 = T_4233 ? T_4324 : 1'h0;
+ assign T_4327 = isJump_15 << 0;
+ assign T_4328 = T_4234 ? T_4327 : 1'h0;
+ assign T_4330 = isJump_16 << 0;
+ assign T_4331 = T_4235 ? T_4330 : 1'h0;
+ assign T_4333 = isJump_17 << 0;
+ assign T_4334 = T_4236 ? T_4333 : 1'h0;
+ assign T_4336 = isJump_18 << 0;
+ assign T_4337 = T_4237 ? T_4336 : 1'h0;
+ assign T_4339 = isJump_19 << 0;
+ assign T_4340 = T_4238 ? T_4339 : 1'h0;
+ assign T_4342 = isJump_20 << 0;
+ assign T_4343 = T_4239 ? T_4342 : 1'h0;
+ assign T_4345 = isJump_21 << 0;
+ assign T_4346 = T_4240 ? T_4345 : 1'h0;
+ assign T_4348 = isJump_22 << 0;
+ assign T_4349 = T_4241 ? T_4348 : 1'h0;
+ assign T_4351 = isJump_23 << 0;
+ assign T_4352 = T_4242 ? T_4351 : 1'h0;
+ assign T_4354 = isJump_24 << 0;
+ assign T_4355 = T_4243 ? T_4354 : 1'h0;
+ assign T_4357 = isJump_25 << 0;
+ assign T_4358 = T_4244 ? T_4357 : 1'h0;
+ assign T_4360 = isJump_26 << 0;
+ assign T_4361 = T_4245 ? T_4360 : 1'h0;
+ assign T_4363 = isJump_27 << 0;
+ assign T_4364 = T_4246 ? T_4363 : 1'h0;
+ assign T_4366 = isJump_28 << 0;
+ assign T_4367 = T_4247 ? T_4366 : 1'h0;
+ assign T_4369 = isJump_29 << 0;
+ assign T_4370 = T_4248 ? T_4369 : 1'h0;
+ assign T_4372 = isJump_30 << 0;
+ assign T_4373 = T_4249 ? T_4372 : 1'h0;
+ assign T_4375 = isJump_31 << 0;
+ assign T_4376 = T_4250 ? T_4375 : 1'h0;
+ assign T_4378 = isJump_32 << 0;
+ assign T_4379 = T_4251 ? T_4378 : 1'h0;
+ assign T_4381 = isJump_33 << 0;
+ assign T_4382 = T_4252 ? T_4381 : 1'h0;
+ assign T_4384 = isJump_34 << 0;
+ assign T_4385 = T_4253 ? T_4384 : 1'h0;
+ assign T_4387 = isJump_35 << 0;
+ assign T_4388 = T_4254 ? T_4387 : 1'h0;
+ assign T_4390 = isJump_36 << 0;
+ assign T_4391 = T_4255 ? T_4390 : 1'h0;
+ assign T_4393 = isJump_37 << 0;
+ assign T_4394 = T_4256 ? T_4393 : 1'h0;
+ assign T_4396 = isJump_38 << 0;
+ assign T_4397 = T_4257 ? T_4396 : 1'h0;
+ assign T_4399 = isJump_39 << 0;
+ assign T_4400 = T_4258 ? T_4399 : 1'h0;
+ assign T_4402 = isJump_40 << 0;
+ assign T_4403 = T_4259 ? T_4402 : 1'h0;
+ assign T_4405 = isJump_41 << 0;
+ assign T_4406 = T_4260 ? T_4405 : 1'h0;
+ assign T_4408 = isJump_42 << 0;
+ assign T_4409 = T_4261 ? T_4408 : 1'h0;
+ assign T_4411 = isJump_43 << 0;
+ assign T_4412 = T_4262 ? T_4411 : 1'h0;
+ assign T_4414 = isJump_44 << 0;
+ assign T_4415 = T_4263 ? T_4414 : 1'h0;
+ assign T_4417 = isJump_45 << 0;
+ assign T_4418 = T_4264 ? T_4417 : 1'h0;
+ assign T_4420 = isJump_46 << 0;
+ assign T_4421 = T_4265 ? T_4420 : 1'h0;
+ assign T_4423 = isJump_47 << 0;
+ assign T_4424 = T_4266 ? T_4423 : 1'h0;
+ assign T_4426 = isJump_48 << 0;
+ assign T_4427 = T_4267 ? T_4426 : 1'h0;
+ assign T_4429 = isJump_49 << 0;
+ assign T_4430 = T_4268 ? T_4429 : 1'h0;
+ assign T_4432 = isJump_50 << 0;
+ assign T_4433 = T_4269 ? T_4432 : 1'h0;
+ assign T_4435 = isJump_51 << 0;
+ assign T_4436 = T_4270 ? T_4435 : 1'h0;
+ assign T_4438 = isJump_52 << 0;
+ assign T_4439 = T_4271 ? T_4438 : 1'h0;
+ assign T_4441 = isJump_53 << 0;
+ assign T_4442 = T_4272 ? T_4441 : 1'h0;
+ assign T_4444 = isJump_54 << 0;
+ assign T_4445 = T_4273 ? T_4444 : 1'h0;
+ assign T_4447 = isJump_55 << 0;
+ assign T_4448 = T_4274 ? T_4447 : 1'h0;
+ assign T_4450 = isJump_56 << 0;
+ assign T_4451 = T_4275 ? T_4450 : 1'h0;
+ assign T_4453 = isJump_57 << 0;
+ assign T_4454 = T_4276 ? T_4453 : 1'h0;
+ assign T_4456 = isJump_58 << 0;
+ assign T_4457 = T_4277 ? T_4456 : 1'h0;
+ assign T_4459 = isJump_59 << 0;
+ assign T_4460 = T_4278 ? T_4459 : 1'h0;
+ assign T_4462 = isJump_60 << 0;
+ assign T_4463 = T_4279 ? T_4462 : 1'h0;
+ assign T_4465 = isJump_61 << 0;
+ assign T_4466 = T_4280 ? T_4465 : 1'h0;
+ assign T_4468 = T_4283 | T_4286;
+ assign T_4469 = T_4468 | T_4289;
+ assign T_4470 = T_4469 | T_4292;
+ assign T_4471 = T_4470 | T_4295;
+ assign T_4472 = T_4471 | T_4298;
+ assign T_4473 = T_4472 | T_4301;
+ assign T_4474 = T_4473 | T_4304;
+ assign T_4475 = T_4474 | T_4307;
+ assign T_4476 = T_4475 | T_4310;
+ assign T_4477 = T_4476 | T_4313;
+ assign T_4478 = T_4477 | T_4316;
+ assign T_4479 = T_4478 | T_4319;
+ assign T_4480 = T_4479 | T_4322;
+ assign T_4481 = T_4480 | T_4325;
+ assign T_4482 = T_4481 | T_4328;
+ assign T_4483 = T_4482 | T_4331;
+ assign T_4484 = T_4483 | T_4334;
+ assign T_4485 = T_4484 | T_4337;
+ assign T_4486 = T_4485 | T_4340;
+ assign T_4487 = T_4486 | T_4343;
+ assign T_4488 = T_4487 | T_4346;
+ assign T_4489 = T_4488 | T_4349;
+ assign T_4490 = T_4489 | T_4352;
+ assign T_4491 = T_4490 | T_4355;
+ assign T_4492 = T_4491 | T_4358;
+ assign T_4493 = T_4492 | T_4361;
+ assign T_4494 = T_4493 | T_4364;
+ assign T_4495 = T_4494 | T_4367;
+ assign T_4496 = T_4495 | T_4370;
+ assign T_4497 = T_4496 | T_4373;
+ assign T_4498 = T_4497 | T_4376;
+ assign T_4499 = T_4498 | T_4379;
+ assign T_4500 = T_4499 | T_4382;
+ assign T_4501 = T_4500 | T_4385;
+ assign T_4502 = T_4501 | T_4388;
+ assign T_4503 = T_4502 | T_4391;
+ assign T_4504 = T_4503 | T_4394;
+ assign T_4505 = T_4504 | T_4397;
+ assign T_4506 = T_4505 | T_4400;
+ assign T_4507 = T_4506 | T_4403;
+ assign T_4508 = T_4507 | T_4406;
+ assign T_4509 = T_4508 | T_4409;
+ assign T_4510 = T_4509 | T_4412;
+ assign T_4511 = T_4510 | T_4415;
+ assign T_4512 = T_4511 | T_4418;
+ assign T_4513 = T_4512 | T_4421;
+ assign T_4514 = T_4513 | T_4424;
+ assign T_4515 = T_4514 | T_4427;
+ assign T_4516 = T_4515 | T_4430;
+ assign T_4517 = T_4516 | T_4433;
+ assign T_4518 = T_4517 | T_4436;
+ assign T_4519 = T_4518 | T_4439;
+ assign T_4520 = T_4519 | T_4442;
+ assign T_4521 = T_4520 | T_4445;
+ assign T_4522 = T_4521 | T_4448;
+ assign T_4523 = T_4522 | T_4451;
+ assign T_4524 = T_4523 | T_4454;
+ assign T_4525 = T_4524 | T_4457;
+ assign T_4526 = T_4525 | T_4460;
+ assign T_4527 = T_4526 | T_4463;
+ assign T_4528 = T_4527 | T_4466;
+ assign T_4529 = T_4528;
+ assign T_4531 = T_4529 == 1'h0;
+ assign T_4532 = io_req_valid & io_resp_valid;
+ assign T_4533 = T_4532 & T_4531;
+ assign T_4537_history = T_4218;
+ assign T_4537_value = T_4216_T_4542_data;
+ assign T_4540 = io_req_bits_addr[8:2];
+ assign T_4541 = T_4540 ^ T_4218;
+ assign T_4543 = T_4537_value[0];
+ assign T_4544 = T_4218[6:1];
+ assign T_4545 = {T_4543,T_4544};
+ assign T_4546 = io_bht_update_valid & io_bht_update_bits_prediction_valid;
+ assign T_4547 = io_bht_update_bits_pc[8:2];
+ assign T_4548 = T_4547 ^ io_bht_update_bits_prediction_bits_bht_history;
+ assign T_4550 = io_bht_update_bits_prediction_bits_bht_value[1];
+ assign T_4551 = io_bht_update_bits_prediction_bits_bht_value[0];
+ assign T_4552 = T_4550 & T_4551;
+ assign T_4553 = io_bht_update_bits_prediction_bits_bht_value[1];
+ assign T_4554 = io_bht_update_bits_prediction_bits_bht_value[0];
+ assign T_4555 = T_4553 | T_4554;
+ assign T_4556 = T_4555 & io_bht_update_bits_taken;
+ assign T_4557 = T_4552 | T_4556;
+ assign T_4558 = {io_bht_update_bits_taken,T_4557};
+ assign T_4559 = io_bht_update_bits_prediction_bits_bht_history[6:1];
+ assign T_4560 = {io_bht_update_bits_taken,T_4559};
+ assign T_4561 = T_4537_value[0];
+ assign T_4563 = T_4561 == 1'h0;
+ assign T_4564 = T_4563 & T_4531;
+ assign T_4582 = hits[0];
+ assign T_4583 = hits[1];
+ assign T_4584 = hits[2];
+ assign T_4585 = hits[3];
+ assign T_4586 = hits[4];
+ assign T_4587 = hits[5];
+ assign T_4588 = hits[6];
+ assign T_4589 = hits[7];
+ assign T_4590 = hits[8];
+ assign T_4591 = hits[9];
+ assign T_4592 = hits[10];
+ assign T_4593 = hits[11];
+ assign T_4594 = hits[12];
+ assign T_4595 = hits[13];
+ assign T_4596 = hits[14];
+ assign T_4597 = hits[15];
+ assign T_4598 = hits[16];
+ assign T_4599 = hits[17];
+ assign T_4600 = hits[18];
+ assign T_4601 = hits[19];
+ assign T_4602 = hits[20];
+ assign T_4603 = hits[21];
+ assign T_4604 = hits[22];
+ assign T_4605 = hits[23];
+ assign T_4606 = hits[24];
+ assign T_4607 = hits[25];
+ assign T_4608 = hits[26];
+ assign T_4609 = hits[27];
+ assign T_4610 = hits[28];
+ assign T_4611 = hits[29];
+ assign T_4612 = hits[30];
+ assign T_4613 = hits[31];
+ assign T_4614 = hits[32];
+ assign T_4615 = hits[33];
+ assign T_4616 = hits[34];
+ assign T_4617 = hits[35];
+ assign T_4618 = hits[36];
+ assign T_4619 = hits[37];
+ assign T_4620 = hits[38];
+ assign T_4621 = hits[39];
+ assign T_4622 = hits[40];
+ assign T_4623 = hits[41];
+ assign T_4624 = hits[42];
+ assign T_4625 = hits[43];
+ assign T_4626 = hits[44];
+ assign T_4627 = hits[45];
+ assign T_4628 = hits[46];
+ assign T_4629 = hits[47];
+ assign T_4630 = hits[48];
+ assign T_4631 = hits[49];
+ assign T_4632 = hits[50];
+ assign T_4633 = hits[51];
+ assign T_4634 = hits[52];
+ assign T_4635 = hits[53];
+ assign T_4636 = hits[54];
+ assign T_4637 = hits[55];
+ assign T_4638 = hits[56];
+ assign T_4639 = hits[57];
+ assign T_4640 = hits[58];
+ assign T_4641 = hits[59];
+ assign T_4642 = hits[60];
+ assign T_4643 = hits[61];
+ assign T_4645 = useRAS_0 << 0;
+ assign T_4646 = T_4582 ? T_4645 : 1'h0;
+ assign T_4648 = useRAS_1 << 0;
+ assign T_4649 = T_4583 ? T_4648 : 1'h0;
+ assign T_4651 = useRAS_2 << 0;
+ assign T_4652 = T_4584 ? T_4651 : 1'h0;
+ assign T_4654 = useRAS_3 << 0;
+ assign T_4655 = T_4585 ? T_4654 : 1'h0;
+ assign T_4657 = useRAS_4 << 0;
+ assign T_4658 = T_4586 ? T_4657 : 1'h0;
+ assign T_4660 = useRAS_5 << 0;
+ assign T_4661 = T_4587 ? T_4660 : 1'h0;
+ assign T_4663 = useRAS_6 << 0;
+ assign T_4664 = T_4588 ? T_4663 : 1'h0;
+ assign T_4666 = useRAS_7 << 0;
+ assign T_4667 = T_4589 ? T_4666 : 1'h0;
+ assign T_4669 = useRAS_8 << 0;
+ assign T_4670 = T_4590 ? T_4669 : 1'h0;
+ assign T_4672 = useRAS_9 << 0;
+ assign T_4673 = T_4591 ? T_4672 : 1'h0;
+ assign T_4675 = useRAS_10 << 0;
+ assign T_4676 = T_4592 ? T_4675 : 1'h0;
+ assign T_4678 = useRAS_11 << 0;
+ assign T_4679 = T_4593 ? T_4678 : 1'h0;
+ assign T_4681 = useRAS_12 << 0;
+ assign T_4682 = T_4594 ? T_4681 : 1'h0;
+ assign T_4684 = useRAS_13 << 0;
+ assign T_4685 = T_4595 ? T_4684 : 1'h0;
+ assign T_4687 = useRAS_14 << 0;
+ assign T_4688 = T_4596 ? T_4687 : 1'h0;
+ assign T_4690 = useRAS_15 << 0;
+ assign T_4691 = T_4597 ? T_4690 : 1'h0;
+ assign T_4693 = useRAS_16 << 0;
+ assign T_4694 = T_4598 ? T_4693 : 1'h0;
+ assign T_4696 = useRAS_17 << 0;
+ assign T_4697 = T_4599 ? T_4696 : 1'h0;
+ assign T_4699 = useRAS_18 << 0;
+ assign T_4700 = T_4600 ? T_4699 : 1'h0;
+ assign T_4702 = useRAS_19 << 0;
+ assign T_4703 = T_4601 ? T_4702 : 1'h0;
+ assign T_4705 = useRAS_20 << 0;
+ assign T_4706 = T_4602 ? T_4705 : 1'h0;
+ assign T_4708 = useRAS_21 << 0;
+ assign T_4709 = T_4603 ? T_4708 : 1'h0;
+ assign T_4711 = useRAS_22 << 0;
+ assign T_4712 = T_4604 ? T_4711 : 1'h0;
+ assign T_4714 = useRAS_23 << 0;
+ assign T_4715 = T_4605 ? T_4714 : 1'h0;
+ assign T_4717 = useRAS_24 << 0;
+ assign T_4718 = T_4606 ? T_4717 : 1'h0;
+ assign T_4720 = useRAS_25 << 0;
+ assign T_4721 = T_4607 ? T_4720 : 1'h0;
+ assign T_4723 = useRAS_26 << 0;
+ assign T_4724 = T_4608 ? T_4723 : 1'h0;
+ assign T_4726 = useRAS_27 << 0;
+ assign T_4727 = T_4609 ? T_4726 : 1'h0;
+ assign T_4729 = useRAS_28 << 0;
+ assign T_4730 = T_4610 ? T_4729 : 1'h0;
+ assign T_4732 = useRAS_29 << 0;
+ assign T_4733 = T_4611 ? T_4732 : 1'h0;
+ assign T_4735 = useRAS_30 << 0;
+ assign T_4736 = T_4612 ? T_4735 : 1'h0;
+ assign T_4738 = useRAS_31 << 0;
+ assign T_4739 = T_4613 ? T_4738 : 1'h0;
+ assign T_4741 = useRAS_32 << 0;
+ assign T_4742 = T_4614 ? T_4741 : 1'h0;
+ assign T_4744 = useRAS_33 << 0;
+ assign T_4745 = T_4615 ? T_4744 : 1'h0;
+ assign T_4747 = useRAS_34 << 0;
+ assign T_4748 = T_4616 ? T_4747 : 1'h0;
+ assign T_4750 = useRAS_35 << 0;
+ assign T_4751 = T_4617 ? T_4750 : 1'h0;
+ assign T_4753 = useRAS_36 << 0;
+ assign T_4754 = T_4618 ? T_4753 : 1'h0;
+ assign T_4756 = useRAS_37 << 0;
+ assign T_4757 = T_4619 ? T_4756 : 1'h0;
+ assign T_4759 = useRAS_38 << 0;
+ assign T_4760 = T_4620 ? T_4759 : 1'h0;
+ assign T_4762 = useRAS_39 << 0;
+ assign T_4763 = T_4621 ? T_4762 : 1'h0;
+ assign T_4765 = useRAS_40 << 0;
+ assign T_4766 = T_4622 ? T_4765 : 1'h0;
+ assign T_4768 = useRAS_41 << 0;
+ assign T_4769 = T_4623 ? T_4768 : 1'h0;
+ assign T_4771 = useRAS_42 << 0;
+ assign T_4772 = T_4624 ? T_4771 : 1'h0;
+ assign T_4774 = useRAS_43 << 0;
+ assign T_4775 = T_4625 ? T_4774 : 1'h0;
+ assign T_4777 = useRAS_44 << 0;
+ assign T_4778 = T_4626 ? T_4777 : 1'h0;
+ assign T_4780 = useRAS_45 << 0;
+ assign T_4781 = T_4627 ? T_4780 : 1'h0;
+ assign T_4783 = useRAS_46 << 0;
+ assign T_4784 = T_4628 ? T_4783 : 1'h0;
+ assign T_4786 = useRAS_47 << 0;
+ assign T_4787 = T_4629 ? T_4786 : 1'h0;
+ assign T_4789 = useRAS_48 << 0;
+ assign T_4790 = T_4630 ? T_4789 : 1'h0;
+ assign T_4792 = useRAS_49 << 0;
+ assign T_4793 = T_4631 ? T_4792 : 1'h0;
+ assign T_4795 = useRAS_50 << 0;
+ assign T_4796 = T_4632 ? T_4795 : 1'h0;
+ assign T_4798 = useRAS_51 << 0;
+ assign T_4799 = T_4633 ? T_4798 : 1'h0;
+ assign T_4801 = useRAS_52 << 0;
+ assign T_4802 = T_4634 ? T_4801 : 1'h0;
+ assign T_4804 = useRAS_53 << 0;
+ assign T_4805 = T_4635 ? T_4804 : 1'h0;
+ assign T_4807 = useRAS_54 << 0;
+ assign T_4808 = T_4636 ? T_4807 : 1'h0;
+ assign T_4810 = useRAS_55 << 0;
+ assign T_4811 = T_4637 ? T_4810 : 1'h0;
+ assign T_4813 = useRAS_56 << 0;
+ assign T_4814 = T_4638 ? T_4813 : 1'h0;
+ assign T_4816 = useRAS_57 << 0;
+ assign T_4817 = T_4639 ? T_4816 : 1'h0;
+ assign T_4819 = useRAS_58 << 0;
+ assign T_4820 = T_4640 ? T_4819 : 1'h0;
+ assign T_4822 = useRAS_59 << 0;
+ assign T_4823 = T_4641 ? T_4822 : 1'h0;
+ assign T_4825 = useRAS_60 << 0;
+ assign T_4826 = T_4642 ? T_4825 : 1'h0;
+ assign T_4828 = useRAS_61 << 0;
+ assign T_4829 = T_4643 ? T_4828 : 1'h0;
+ assign T_4831 = T_4646 | T_4649;
+ assign T_4832 = T_4831 | T_4652;
+ assign T_4833 = T_4832 | T_4655;
+ assign T_4834 = T_4833 | T_4658;
+ assign T_4835 = T_4834 | T_4661;
+ assign T_4836 = T_4835 | T_4664;
+ assign T_4837 = T_4836 | T_4667;
+ assign T_4838 = T_4837 | T_4670;
+ assign T_4839 = T_4838 | T_4673;
+ assign T_4840 = T_4839 | T_4676;
+ assign T_4841 = T_4840 | T_4679;
+ assign T_4842 = T_4841 | T_4682;
+ assign T_4843 = T_4842 | T_4685;
+ assign T_4844 = T_4843 | T_4688;
+ assign T_4845 = T_4844 | T_4691;
+ assign T_4846 = T_4845 | T_4694;
+ assign T_4847 = T_4846 | T_4697;
+ assign T_4848 = T_4847 | T_4700;
+ assign T_4849 = T_4848 | T_4703;
+ assign T_4850 = T_4849 | T_4706;
+ assign T_4851 = T_4850 | T_4709;
+ assign T_4852 = T_4851 | T_4712;
+ assign T_4853 = T_4852 | T_4715;
+ assign T_4854 = T_4853 | T_4718;
+ assign T_4855 = T_4854 | T_4721;
+ assign T_4856 = T_4855 | T_4724;
+ assign T_4857 = T_4856 | T_4727;
+ assign T_4858 = T_4857 | T_4730;
+ assign T_4859 = T_4858 | T_4733;
+ assign T_4860 = T_4859 | T_4736;
+ assign T_4861 = T_4860 | T_4739;
+ assign T_4862 = T_4861 | T_4742;
+ assign T_4863 = T_4862 | T_4745;
+ assign T_4864 = T_4863 | T_4748;
+ assign T_4865 = T_4864 | T_4751;
+ assign T_4866 = T_4865 | T_4754;
+ assign T_4867 = T_4866 | T_4757;
+ assign T_4868 = T_4867 | T_4760;
+ assign T_4869 = T_4868 | T_4763;
+ assign T_4870 = T_4869 | T_4766;
+ assign T_4871 = T_4870 | T_4769;
+ assign T_4872 = T_4871 | T_4772;
+ assign T_4873 = T_4872 | T_4775;
+ assign T_4874 = T_4873 | T_4778;
+ assign T_4875 = T_4874 | T_4781;
+ assign T_4876 = T_4875 | T_4784;
+ assign T_4877 = T_4876 | T_4787;
+ assign T_4878 = T_4877 | T_4790;
+ assign T_4879 = T_4878 | T_4793;
+ assign T_4880 = T_4879 | T_4796;
+ assign T_4881 = T_4880 | T_4799;
+ assign T_4882 = T_4881 | T_4802;
+ assign T_4883 = T_4882 | T_4805;
+ assign T_4884 = T_4883 | T_4808;
+ assign T_4885 = T_4884 | T_4811;
+ assign T_4886 = T_4885 | T_4814;
+ assign T_4887 = T_4886 | T_4817;
+ assign T_4888 = T_4887 | T_4820;
+ assign T_4889 = T_4888 | T_4823;
+ assign T_4890 = T_4889 | T_4826;
+ assign T_4891 = T_4890 | T_4829;
+ assign T_4892 = T_4891;
+ assign T_4894 = T_4567 == 1'h0;
+ assign T_4896 = T_4894 == 1'h0;
+ assign T_4897 = T_4896 & T_4892;
+ assign GEN_2 = GEN_133 ? T_4578_1 : T_4578_0;
+ assign T_4900 = T_4567 < 2'h2;
+ assign T_4902 = T_4567 + 1'h1;
+ assign T_4903 = T_4902[1:0];
+ assign T_4906 = T_4569 < 1'h1;
+ assign T_4907 = 1'h1 | T_4906;
+ assign T_4909 = T_4569 + 1'h1;
+ assign T_4910 = T_4909[0:0];
+ assign T_4912 = T_4907 ? T_4910 : 1'h0;
+ assign GEN_3 = io_ras_update_bits_returnAddr;
+ assign T_4914 = io_ras_update_bits_isReturn & io_ras_update_bits_prediction_valid;
+ assign T_4916 = io_ras_update_bits_isCall == 1'h0;
+ assign T_4917 = T_4916 & T_4914;
+ assign T_4919 = T_4567 == 1'h0;
+ assign T_4921 = T_4919 == 1'h0;
+ assign T_4923 = T_4567 - 1'h1;
+ assign T_4924 = T_4923[1:0];
+ assign T_4927 = T_4569 > 1'h0;
+ assign T_4928 = 1'h1 | T_4927;
+ assign T_4930 = T_4569 - 1'h1;
+ assign T_4931 = T_4930[0:0];
+ assign T_4933 = T_4928 ? T_4931 : 1'h1;
+ assign GEN_4 = r_btb_update_valid & T_3085;
+ assign GEN_5 = GEN_4 & T_3087;
+ assign GEN_6 = r_btb_update_valid & T_3085;
+ assign GEN_7 = 1'h0 == T_3090;
+ assign GEN_8 = 1'h1 == T_3090;
+ assign GEN_9 = 2'h2 == T_3090;
+ assign GEN_10 = 2'h3 == T_3090;
+ assign GEN_11 = 3'h4 == T_3090;
+ assign GEN_12 = 3'h5 == T_3090;
+ assign GEN_13 = 3'h6 == T_3090;
+ assign GEN_14 = 3'h7 == T_3090;
+ assign GEN_15 = 4'h8 == T_3090;
+ assign GEN_16 = 4'h9 == T_3090;
+ assign GEN_17 = 4'ha == T_3090;
+ assign GEN_18 = 4'hb == T_3090;
+ assign GEN_19 = 4'hc == T_3090;
+ assign GEN_20 = 4'hd == T_3090;
+ assign GEN_21 = 4'he == T_3090;
+ assign GEN_22 = 4'hf == T_3090;
+ assign GEN_23 = 5'h10 == T_3090;
+ assign GEN_24 = 5'h11 == T_3090;
+ assign GEN_25 = 5'h12 == T_3090;
+ assign GEN_26 = 5'h13 == T_3090;
+ assign GEN_27 = 5'h14 == T_3090;
+ assign GEN_28 = 5'h15 == T_3090;
+ assign GEN_29 = 5'h16 == T_3090;
+ assign GEN_30 = 5'h17 == T_3090;
+ assign GEN_31 = 5'h18 == T_3090;
+ assign GEN_32 = 5'h19 == T_3090;
+ assign GEN_33 = 5'h1a == T_3090;
+ assign GEN_34 = 5'h1b == T_3090;
+ assign GEN_35 = 5'h1c == T_3090;
+ assign GEN_36 = 5'h1d == T_3090;
+ assign GEN_37 = 5'h1e == T_3090;
+ assign GEN_38 = 5'h1f == T_3090;
+ assign GEN_39 = 6'h20 == T_3090;
+ assign GEN_40 = 6'h21 == T_3090;
+ assign GEN_41 = 6'h22 == T_3090;
+ assign GEN_42 = 6'h23 == T_3090;
+ assign GEN_43 = 6'h24 == T_3090;
+ assign GEN_44 = 6'h25 == T_3090;
+ assign GEN_45 = 6'h26 == T_3090;
+ assign GEN_46 = 6'h27 == T_3090;
+ assign GEN_47 = 6'h28 == T_3090;
+ assign GEN_48 = 6'h29 == T_3090;
+ assign GEN_49 = 6'h2a == T_3090;
+ assign GEN_50 = 6'h2b == T_3090;
+ assign GEN_51 = 6'h2c == T_3090;
+ assign GEN_52 = 6'h2d == T_3090;
+ assign GEN_53 = 6'h2e == T_3090;
+ assign GEN_54 = 6'h2f == T_3090;
+ assign GEN_55 = 6'h30 == T_3090;
+ assign GEN_56 = 6'h31 == T_3090;
+ assign GEN_57 = 6'h32 == T_3090;
+ assign GEN_58 = 6'h33 == T_3090;
+ assign GEN_59 = 6'h34 == T_3090;
+ assign GEN_60 = 6'h35 == T_3090;
+ assign GEN_61 = 6'h36 == T_3090;
+ assign GEN_62 = 6'h37 == T_3090;
+ assign GEN_63 = 6'h38 == T_3090;
+ assign GEN_64 = 6'h39 == T_3090;
+ assign GEN_65 = 6'h3a == T_3090;
+ assign GEN_66 = 6'h3b == T_3090;
+ assign GEN_67 = 6'h3c == T_3090;
+ assign GEN_68 = 6'h3d == T_3090;
+ assign GEN_69 = 1'h0 == T_3090;
+ assign GEN_70 = 1'h1 == T_3090;
+ assign GEN_71 = 2'h2 == T_3090;
+ assign GEN_72 = 2'h3 == T_3090;
+ assign GEN_73 = 3'h4 == T_3090;
+ assign GEN_74 = 3'h5 == T_3090;
+ assign GEN_75 = 3'h6 == T_3090;
+ assign GEN_76 = 3'h7 == T_3090;
+ assign GEN_77 = 4'h8 == T_3090;
+ assign GEN_78 = 4'h9 == T_3090;
+ assign GEN_79 = 4'ha == T_3090;
+ assign GEN_80 = 4'hb == T_3090;
+ assign GEN_81 = 4'hc == T_3090;
+ assign GEN_82 = 4'hd == T_3090;
+ assign GEN_83 = 4'he == T_3090;
+ assign GEN_84 = 4'hf == T_3090;
+ assign GEN_85 = 5'h10 == T_3090;
+ assign GEN_86 = 5'h11 == T_3090;
+ assign GEN_87 = 5'h12 == T_3090;
+ assign GEN_88 = 5'h13 == T_3090;
+ assign GEN_89 = 5'h14 == T_3090;
+ assign GEN_90 = 5'h15 == T_3090;
+ assign GEN_91 = 5'h16 == T_3090;
+ assign GEN_92 = 5'h17 == T_3090;
+ assign GEN_93 = 5'h18 == T_3090;
+ assign GEN_94 = 5'h19 == T_3090;
+ assign GEN_95 = 5'h1a == T_3090;
+ assign GEN_96 = 5'h1b == T_3090;
+ assign GEN_97 = 5'h1c == T_3090;
+ assign GEN_98 = 5'h1d == T_3090;
+ assign GEN_99 = 5'h1e == T_3090;
+ assign GEN_100 = 5'h1f == T_3090;
+ assign GEN_101 = 6'h20 == T_3090;
+ assign GEN_102 = 6'h21 == T_3090;
+ assign GEN_103 = 6'h22 == T_3090;
+ assign GEN_104 = 6'h23 == T_3090;
+ assign GEN_105 = 6'h24 == T_3090;
+ assign GEN_106 = 6'h25 == T_3090;
+ assign GEN_107 = 6'h26 == T_3090;
+ assign GEN_108 = 6'h27 == T_3090;
+ assign GEN_109 = 6'h28 == T_3090;
+ assign GEN_110 = 6'h29 == T_3090;
+ assign GEN_111 = 6'h2a == T_3090;
+ assign GEN_112 = 6'h2b == T_3090;
+ assign GEN_113 = 6'h2c == T_3090;
+ assign GEN_114 = 6'h2d == T_3090;
+ assign GEN_115 = 6'h2e == T_3090;
+ assign GEN_116 = 6'h2f == T_3090;
+ assign GEN_117 = 6'h30 == T_3090;
+ assign GEN_118 = 6'h31 == T_3090;
+ assign GEN_119 = 6'h32 == T_3090;
+ assign GEN_120 = 6'h33 == T_3090;
+ assign GEN_121 = 6'h34 == T_3090;
+ assign GEN_122 = 6'h35 == T_3090;
+ assign GEN_123 = 6'h36 == T_3090;
+ assign GEN_124 = 6'h37 == T_3090;
+ assign GEN_125 = 6'h38 == T_3090;
+ assign GEN_126 = 6'h39 == T_3090;
+ assign GEN_127 = 6'h3a == T_3090;
+ assign GEN_128 = 6'h3b == T_3090;
+ assign GEN_129 = 6'h3c == T_3090;
+ assign GEN_130 = 6'h3d == T_3090;
+ assign GEN_131 = 1'h0 == T_4912;
+ assign GEN_132 = 1'h1 == T_4912;
+ assign GEN_133 = 1'h1 == T_4569;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ idxValid = {2{$random}};
+ for (initvar = 0; initvar < 62; initvar = initvar+1)
+ idxs[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 62; initvar = initvar+1)
+ idxPages[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 62; initvar = initvar+1)
+ tgts[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 62; initvar = initvar+1)
+ tgtPages[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 6; initvar = initvar+1)
+ pages[initvar] = {1{$random}};
+ pageValid = {1{$random}};
+ useRAS_0 = {1{$random}};
+ useRAS_1 = {1{$random}};
+ useRAS_2 = {1{$random}};
+ useRAS_3 = {1{$random}};
+ useRAS_4 = {1{$random}};
+ useRAS_5 = {1{$random}};
+ useRAS_6 = {1{$random}};
+ useRAS_7 = {1{$random}};
+ useRAS_8 = {1{$random}};
+ useRAS_9 = {1{$random}};
+ useRAS_10 = {1{$random}};
+ useRAS_11 = {1{$random}};
+ useRAS_12 = {1{$random}};
+ useRAS_13 = {1{$random}};
+ useRAS_14 = {1{$random}};
+ useRAS_15 = {1{$random}};
+ useRAS_16 = {1{$random}};
+ useRAS_17 = {1{$random}};
+ useRAS_18 = {1{$random}};
+ useRAS_19 = {1{$random}};
+ useRAS_20 = {1{$random}};
+ useRAS_21 = {1{$random}};
+ useRAS_22 = {1{$random}};
+ useRAS_23 = {1{$random}};
+ useRAS_24 = {1{$random}};
+ useRAS_25 = {1{$random}};
+ useRAS_26 = {1{$random}};
+ useRAS_27 = {1{$random}};
+ useRAS_28 = {1{$random}};
+ useRAS_29 = {1{$random}};
+ useRAS_30 = {1{$random}};
+ useRAS_31 = {1{$random}};
+ useRAS_32 = {1{$random}};
+ useRAS_33 = {1{$random}};
+ useRAS_34 = {1{$random}};
+ useRAS_35 = {1{$random}};
+ useRAS_36 = {1{$random}};
+ useRAS_37 = {1{$random}};
+ useRAS_38 = {1{$random}};
+ useRAS_39 = {1{$random}};
+ useRAS_40 = {1{$random}};
+ useRAS_41 = {1{$random}};
+ useRAS_42 = {1{$random}};
+ useRAS_43 = {1{$random}};
+ useRAS_44 = {1{$random}};
+ useRAS_45 = {1{$random}};
+ useRAS_46 = {1{$random}};
+ useRAS_47 = {1{$random}};
+ useRAS_48 = {1{$random}};
+ useRAS_49 = {1{$random}};
+ useRAS_50 = {1{$random}};
+ useRAS_51 = {1{$random}};
+ useRAS_52 = {1{$random}};
+ useRAS_53 = {1{$random}};
+ useRAS_54 = {1{$random}};
+ useRAS_55 = {1{$random}};
+ useRAS_56 = {1{$random}};
+ useRAS_57 = {1{$random}};
+ useRAS_58 = {1{$random}};
+ useRAS_59 = {1{$random}};
+ useRAS_60 = {1{$random}};
+ useRAS_61 = {1{$random}};
+ isJump_0 = {1{$random}};
+ isJump_1 = {1{$random}};
+ isJump_2 = {1{$random}};
+ isJump_3 = {1{$random}};
+ isJump_4 = {1{$random}};
+ isJump_5 = {1{$random}};
+ isJump_6 = {1{$random}};
+ isJump_7 = {1{$random}};
+ isJump_8 = {1{$random}};
+ isJump_9 = {1{$random}};
+ isJump_10 = {1{$random}};
+ isJump_11 = {1{$random}};
+ isJump_12 = {1{$random}};
+ isJump_13 = {1{$random}};
+ isJump_14 = {1{$random}};
+ isJump_15 = {1{$random}};
+ isJump_16 = {1{$random}};
+ isJump_17 = {1{$random}};
+ isJump_18 = {1{$random}};
+ isJump_19 = {1{$random}};
+ isJump_20 = {1{$random}};
+ isJump_21 = {1{$random}};
+ isJump_22 = {1{$random}};
+ isJump_23 = {1{$random}};
+ isJump_24 = {1{$random}};
+ isJump_25 = {1{$random}};
+ isJump_26 = {1{$random}};
+ isJump_27 = {1{$random}};
+ isJump_28 = {1{$random}};
+ isJump_29 = {1{$random}};
+ isJump_30 = {1{$random}};
+ isJump_31 = {1{$random}};
+ isJump_32 = {1{$random}};
+ isJump_33 = {1{$random}};
+ isJump_34 = {1{$random}};
+ isJump_35 = {1{$random}};
+ isJump_36 = {1{$random}};
+ isJump_37 = {1{$random}};
+ isJump_38 = {1{$random}};
+ isJump_39 = {1{$random}};
+ isJump_40 = {1{$random}};
+ isJump_41 = {1{$random}};
+ isJump_42 = {1{$random}};
+ isJump_43 = {1{$random}};
+ isJump_44 = {1{$random}};
+ isJump_45 = {1{$random}};
+ isJump_46 = {1{$random}};
+ isJump_47 = {1{$random}};
+ isJump_48 = {1{$random}};
+ isJump_49 = {1{$random}};
+ isJump_50 = {1{$random}};
+ isJump_51 = {1{$random}};
+ isJump_52 = {1{$random}};
+ isJump_53 = {1{$random}};
+ isJump_54 = {1{$random}};
+ isJump_55 = {1{$random}};
+ isJump_56 = {1{$random}};
+ isJump_57 = {1{$random}};
+ isJump_58 = {1{$random}};
+ isJump_59 = {1{$random}};
+ isJump_60 = {1{$random}};
+ isJump_61 = {1{$random}};
+ for (initvar = 0; initvar < 62; initvar = initvar+1)
+ brIdx[initvar] = {1{$random}};
+ T_1478 = {1{$random}};
+ T_1479_prediction_valid = {1{$random}};
+ T_1479_prediction_bits_taken = {1{$random}};
+ T_1479_prediction_bits_mask = {1{$random}};
+ T_1479_prediction_bits_bridx = {1{$random}};
+ T_1479_prediction_bits_target = {2{$random}};
+ T_1479_prediction_bits_entry = {1{$random}};
+ T_1479_prediction_bits_bht_history = {1{$random}};
+ T_1479_prediction_bits_bht_value = {1{$random}};
+ T_1479_pc = {2{$random}};
+ T_1479_target = {2{$random}};
+ T_1479_taken = {1{$random}};
+ T_1479_isJump = {1{$random}};
+ T_1479_isReturn = {1{$random}};
+ T_1479_br_pc = {2{$random}};
+ T_2986 = {1{$random}};
+ nextRepl = {1{$random}};
+ T_3070 = {1{$random}};
+ for (initvar = 0; initvar < 128; initvar = initvar+1)
+ T_4216[initvar] = {1{$random}};
+ T_4218 = {1{$random}};
+ T_4567 = {1{$random}};
+ T_4569 = {1{$random}};
+ T_4578_0 = {2{$random}};
+ T_4578_1 = {2{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ idxValid <= 62'h0;
+ end else begin
+ if(io_invalidate) begin
+ idxValid <= 1'h0;
+ end else begin
+ if(r_btb_update_valid) begin
+ idxValid <= T_3469;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ pageValid <= 6'h0;
+ end else begin
+ if(io_invalidate) begin
+ pageValid <= 1'h0;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(doPageRepl) begin
+ pageValid <= T_3516;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_7) begin
+ useRAS_0 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_8) begin
+ useRAS_1 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_9) begin
+ useRAS_2 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_10) begin
+ useRAS_3 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_11) begin
+ useRAS_4 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_12) begin
+ useRAS_5 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_13) begin
+ useRAS_6 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_14) begin
+ useRAS_7 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_15) begin
+ useRAS_8 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_16) begin
+ useRAS_9 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_17) begin
+ useRAS_10 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_18) begin
+ useRAS_11 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_19) begin
+ useRAS_12 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_20) begin
+ useRAS_13 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_21) begin
+ useRAS_14 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_22) begin
+ useRAS_15 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_23) begin
+ useRAS_16 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_24) begin
+ useRAS_17 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_25) begin
+ useRAS_18 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_26) begin
+ useRAS_19 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_27) begin
+ useRAS_20 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_28) begin
+ useRAS_21 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_29) begin
+ useRAS_22 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_30) begin
+ useRAS_23 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_31) begin
+ useRAS_24 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_32) begin
+ useRAS_25 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_33) begin
+ useRAS_26 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_34) begin
+ useRAS_27 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_35) begin
+ useRAS_28 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_36) begin
+ useRAS_29 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_37) begin
+ useRAS_30 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_38) begin
+ useRAS_31 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_39) begin
+ useRAS_32 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_40) begin
+ useRAS_33 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_41) begin
+ useRAS_34 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_42) begin
+ useRAS_35 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_43) begin
+ useRAS_36 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_44) begin
+ useRAS_37 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_45) begin
+ useRAS_38 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_46) begin
+ useRAS_39 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_47) begin
+ useRAS_40 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_48) begin
+ useRAS_41 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_49) begin
+ useRAS_42 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_50) begin
+ useRAS_43 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_51) begin
+ useRAS_44 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_52) begin
+ useRAS_45 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_53) begin
+ useRAS_46 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_54) begin
+ useRAS_47 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_55) begin
+ useRAS_48 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_56) begin
+ useRAS_49 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_57) begin
+ useRAS_50 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_58) begin
+ useRAS_51 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_59) begin
+ useRAS_52 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_60) begin
+ useRAS_53 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_61) begin
+ useRAS_54 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_62) begin
+ useRAS_55 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_63) begin
+ useRAS_56 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_64) begin
+ useRAS_57 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_65) begin
+ useRAS_58 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_66) begin
+ useRAS_59 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_67) begin
+ useRAS_60 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_68) begin
+ useRAS_61 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_69) begin
+ isJump_0 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_70) begin
+ isJump_1 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_71) begin
+ isJump_2 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_72) begin
+ isJump_3 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_73) begin
+ isJump_4 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_74) begin
+ isJump_5 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_75) begin
+ isJump_6 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_76) begin
+ isJump_7 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_77) begin
+ isJump_8 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_78) begin
+ isJump_9 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_79) begin
+ isJump_10 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_80) begin
+ isJump_11 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_81) begin
+ isJump_12 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_82) begin
+ isJump_13 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_83) begin
+ isJump_14 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_84) begin
+ isJump_15 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_85) begin
+ isJump_16 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_86) begin
+ isJump_17 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_87) begin
+ isJump_18 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_88) begin
+ isJump_19 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_89) begin
+ isJump_20 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_90) begin
+ isJump_21 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_91) begin
+ isJump_22 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_92) begin
+ isJump_23 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_93) begin
+ isJump_24 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_94) begin
+ isJump_25 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_95) begin
+ isJump_26 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_96) begin
+ isJump_27 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_97) begin
+ isJump_28 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_98) begin
+ isJump_29 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_99) begin
+ isJump_30 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_100) begin
+ isJump_31 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_101) begin
+ isJump_32 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_102) begin
+ isJump_33 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_103) begin
+ isJump_34 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_104) begin
+ isJump_35 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_105) begin
+ isJump_36 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_106) begin
+ isJump_37 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_107) begin
+ isJump_38 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_108) begin
+ isJump_39 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_109) begin
+ isJump_40 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_110) begin
+ isJump_41 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_111) begin
+ isJump_42 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_112) begin
+ isJump_43 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_113) begin
+ isJump_44 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_114) begin
+ isJump_45 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_115) begin
+ isJump_46 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_116) begin
+ isJump_47 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_117) begin
+ isJump_48 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_118) begin
+ isJump_49 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_119) begin
+ isJump_50 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_120) begin
+ isJump_51 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_121) begin
+ isJump_52 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_122) begin
+ isJump_53 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_123) begin
+ isJump_54 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_124) begin
+ isJump_55 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_125) begin
+ isJump_56 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_126) begin
+ isJump_57 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_127) begin
+ isJump_58 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_128) begin
+ isJump_59 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_129) begin
+ isJump_60 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(r_btb_update_valid) begin
+ if(GEN_130) begin
+ isJump_61 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_1478 <= 1'h0;
+ end else begin
+ T_1478 <= io_btb_update_valid;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_btb_update_valid) begin
+ T_1479_prediction_valid <= io_btb_update_bits_prediction_valid;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_btb_update_valid) begin
+ T_1479_prediction_bits_taken <= io_btb_update_bits_prediction_bits_taken;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_btb_update_valid) begin
+ T_1479_prediction_bits_mask <= io_btb_update_bits_prediction_bits_mask;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_btb_update_valid) begin
+ T_1479_prediction_bits_bridx <= io_btb_update_bits_prediction_bits_bridx;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_btb_update_valid) begin
+ T_1479_prediction_bits_target <= io_btb_update_bits_prediction_bits_target;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_btb_update_valid) begin
+ T_1479_prediction_bits_entry <= io_btb_update_bits_prediction_bits_entry;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_btb_update_valid) begin
+ T_1479_prediction_bits_bht_history <= io_btb_update_bits_prediction_bits_bht_history;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_btb_update_valid) begin
+ T_1479_prediction_bits_bht_value <= io_btb_update_bits_prediction_bits_bht_value;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_btb_update_valid) begin
+ T_1479_pc <= io_btb_update_bits_pc;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_btb_update_valid) begin
+ T_1479_target <= io_btb_update_bits_target;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_btb_update_valid) begin
+ T_1479_taken <= io_btb_update_bits_taken;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_btb_update_valid) begin
+ T_1479_isJump <= io_btb_update_bits_isJump;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_btb_update_valid) begin
+ T_1479_isReturn <= io_btb_update_bits_isReturn;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_btb_update_valid) begin
+ T_1479_br_pc <= io_btb_update_bits_br_pc;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_2986 <= 16'h1;
+ end else begin
+ if(r_btb_update_valid) begin
+ T_2986 <= T_2995;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ nextRepl <= 6'h0;
+ end else begin
+ if(T_2998) begin
+ nextRepl <= T_3009;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_3070 <= 3'h0;
+ end else begin
+ if(T_3068) begin
+ T_3070 <= T_3079;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_4546) begin
+ if(io_bht_update_bits_mispredict) begin
+ T_4218 <= T_4560;
+ end else begin
+ if(T_4533) begin
+ T_4218 <= T_4545;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_4533) begin
+ T_4218 <= T_4545;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ T_4567 <= 2'h0;
+ end else begin
+ if(io_invalidate) begin
+ T_4567 <= 1'h0;
+ end else begin
+ if(io_ras_update_valid) begin
+ if(T_4917) begin
+ if(T_4921) begin
+ T_4567 <= T_4924;
+ end else begin
+ if(io_ras_update_bits_isCall) begin
+ if(T_4900) begin
+ T_4567 <= T_4903;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(io_ras_update_bits_isCall) begin
+ if(T_4900) begin
+ T_4567 <= T_4903;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ T_4569 <= 1'h0;
+ end else begin
+ if(io_ras_update_valid) begin
+ if(T_4917) begin
+ if(T_4921) begin
+ T_4569 <= T_4933;
+ end else begin
+ if(io_ras_update_bits_isCall) begin
+ T_4569 <= T_4912;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(io_ras_update_bits_isCall) begin
+ T_4569 <= T_4912;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ras_update_valid) begin
+ if(io_ras_update_bits_isCall) begin
+ if(GEN_131) begin
+ T_4578_0 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ras_update_valid) begin
+ if(io_ras_update_bits_isCall) begin
+ if(GEN_132) begin
+ T_4578_1 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ `ifndef SYNTHESIS
+ if(GEN_5 & T_3089) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): BTB request != I$ target");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(GEN_6 & T_3087) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ end
+ always @(posedge idxs_T_3470_clk) begin
+ if(idxs_T_3470_en & idxs_T_3470_mask) begin
+ idxs[idxs_T_3470_addr] <= idxs_T_3470_data;
+ end
+ end
+ always @(posedge idxPages_T_3472_clk) begin
+ if(idxPages_T_3472_en & idxPages_T_3472_mask) begin
+ idxPages[idxPages_T_3472_addr] <= idxPages_T_3472_data;
+ end
+ end
+ always @(posedge tgts_T_3471_clk) begin
+ if(tgts_T_3471_en & tgts_T_3471_mask) begin
+ tgts[tgts_T_3471_addr] <= tgts_T_3471_data;
+ end
+ end
+ always @(posedge tgtPages_T_3473_clk) begin
+ if(tgtPages_T_3473_en & tgtPages_T_3473_mask) begin
+ tgtPages[tgtPages_T_3473_addr] <= tgtPages_T_3473_data;
+ end
+ end
+ always @(posedge pages_T_3491_clk) begin
+ if(pages_T_3491_en & pages_T_3491_mask) begin
+ pages[pages_T_3491_addr] <= pages_T_3491_data;
+ end
+ end
+ always @(posedge pages_T_3495_clk) begin
+ if(pages_T_3495_en & pages_T_3495_mask) begin
+ pages[pages_T_3495_addr] <= pages_T_3495_data;
+ end
+ end
+ always @(posedge pages_T_3499_clk) begin
+ if(pages_T_3499_en & pages_T_3499_mask) begin
+ pages[pages_T_3499_addr] <= pages_T_3499_data;
+ end
+ end
+ always @(posedge pages_T_3507_clk) begin
+ if(pages_T_3507_en & pages_T_3507_mask) begin
+ pages[pages_T_3507_addr] <= pages_T_3507_data;
+ end
+ end
+ always @(posedge pages_T_3511_clk) begin
+ if(pages_T_3511_en & pages_T_3511_mask) begin
+ pages[pages_T_3511_addr] <= pages_T_3511_data;
+ end
+ end
+ always @(posedge pages_T_3515_clk) begin
+ if(pages_T_3515_en & pages_T_3515_mask) begin
+ pages[pages_T_3515_addr] <= pages_T_3515_data;
+ end
+ end
+ always @(posedge brIdx_T_3476_clk) begin
+ if(brIdx_T_3476_en & brIdx_T_3476_mask) begin
+ brIdx[brIdx_T_3476_addr] <= brIdx_T_3476_data;
+ end
+ end
+ always @(posedge T_4216_T_4549_clk) begin
+ if(T_4216_T_4549_en & T_4216_T_4549_mask) begin
+ T_4216[T_4216_T_4549_addr] <= T_4216_T_4549_data;
+ end
+ end
+endmodule
+module FlowThroughSerializer(
+ input clk,
+ input reset,
+ output io_in_ready,
+ input io_in_valid,
+ input [1:0] io_in_bits_addr_beat,
+ input [1:0] io_in_bits_client_xact_id,
+ input [3:0] io_in_bits_manager_xact_id,
+ input io_in_bits_is_builtin_type,
+ input [3:0] io_in_bits_g_type,
+ input [127:0] io_in_bits_data,
+ input io_out_ready,
+ output io_out_valid,
+ output [1:0] io_out_bits_addr_beat,
+ output [1:0] io_out_bits_client_xact_id,
+ output [3:0] io_out_bits_manager_xact_id,
+ output io_out_bits_is_builtin_type,
+ output [3:0] io_out_bits_g_type,
+ output [127:0] io_out_bits_data,
+ output io_cnt,
+ output io_done
+);
+ assign io_in_ready = io_out_ready;
+ assign io_out_valid = io_in_valid;
+ assign io_out_bits_addr_beat = io_in_bits_addr_beat;
+ assign io_out_bits_client_xact_id = io_in_bits_client_xact_id;
+ assign io_out_bits_manager_xact_id = io_in_bits_manager_xact_id;
+ assign io_out_bits_is_builtin_type = io_in_bits_is_builtin_type;
+ assign io_out_bits_g_type = io_in_bits_g_type;
+ assign io_out_bits_data = io_in_bits_data;
+ assign io_cnt = 1'h0;
+ assign io_done = 1'h1;
+endmodule
+module ICache(
+ input clk,
+ input reset,
+ input io_req_valid,
+ input [11:0] io_req_bits_idx,
+ input [19:0] io_req_bits_ppn,
+ input io_req_bits_kill,
+ input io_resp_ready,
+ output io_resp_valid,
+ output [31:0] io_resp_bits_data,
+ output [127:0] io_resp_bits_datablock,
+ input io_invalidate,
+ input io_mem_acquire_ready,
+ output io_mem_acquire_valid,
+ output [25:0] io_mem_acquire_bits_addr_block,
+ output [1:0] io_mem_acquire_bits_client_xact_id,
+ output [1:0] io_mem_acquire_bits_addr_beat,
+ output io_mem_acquire_bits_is_builtin_type,
+ output [2:0] io_mem_acquire_bits_a_type,
+ output [16:0] io_mem_acquire_bits_union,
+ output [127:0] io_mem_acquire_bits_data,
+ output io_mem_grant_ready,
+ input io_mem_grant_valid,
+ input [1:0] io_mem_grant_bits_addr_beat,
+ input [1:0] io_mem_grant_bits_client_xact_id,
+ input [3:0] io_mem_grant_bits_manager_xact_id,
+ input io_mem_grant_bits_is_builtin_type,
+ input [3:0] io_mem_grant_bits_g_type,
+ input [127:0] io_mem_grant_bits_data
+);
+ reg [1:0] state;
+ reg invalidated;
+ wire stall;
+ wire rdy;
+ reg [31:0] refill_addr;
+ wire s1_any_tag_hit;
+ reg s1_valid;
+ reg [11:0] s1_pgoff;
+ wire [31:0] s1_addr;
+ wire [19:0] s1_tag;
+ wire T_523;
+ wire s0_valid;
+ wire T_525;
+ wire [11:0] s0_pgoff;
+ wire T_527;
+ wire T_528;
+ wire T_530;
+ wire T_531;
+ wire T_532;
+ wire T_533;
+ wire T_535;
+ wire T_536;
+ wire T_537;
+ wire out_valid;
+ wire [5:0] s1_idx;
+ wire [5:0] s1_offset;
+ wire s1_hit;
+ wire T_543;
+ wire s1_miss;
+ wire T_545;
+ wire T_547;
+ wire T_548;
+ wire T_549;
+ wire T_550;
+ wire T_551;
+ wire [19:0] refill_tag;
+ wire T_553_clk;
+ wire T_553_reset;
+ wire T_553_io_in_ready;
+ wire T_553_io_in_valid;
+ wire [1:0] T_553_io_in_bits_addr_beat;
+ wire [1:0] T_553_io_in_bits_client_xact_id;
+ wire [3:0] T_553_io_in_bits_manager_xact_id;
+ wire T_553_io_in_bits_is_builtin_type;
+ wire [3:0] T_553_io_in_bits_g_type;
+ wire [127:0] T_553_io_in_bits_data;
+ wire T_553_io_out_ready;
+ wire T_553_io_out_valid;
+ wire [1:0] T_553_io_out_bits_addr_beat;
+ wire [1:0] T_553_io_out_bits_client_xact_id;
+ wire [3:0] T_553_io_out_bits_manager_xact_id;
+ wire T_553_io_out_bits_is_builtin_type;
+ wire [3:0] T_553_io_out_bits_g_type;
+ wire [127:0] T_553_io_out_bits_data;
+ wire T_553_io_cnt;
+ wire T_553_io_done;
+ wire T_554;
+ reg [1:0] refill_cnt;
+ wire T_558;
+ wire T_560;
+ wire [2:0] T_563;
+ wire [1:0] T_564;
+ wire [1:0] T_565;
+ wire refill_wrap;
+ wire T_567;
+ wire refill_done;
+ reg [15:0] T_571;
+ wire T_572;
+ wire T_573;
+ wire T_574;
+ wire T_575;
+ wire T_576;
+ wire T_577;
+ wire T_578;
+ wire [14:0] T_579;
+ wire [15:0] T_580;
+ wire [1:0] repl_way;
+ reg [19:0] tag_array_0 [0:63];
+ wire [19:0] tag_array_0_tag_rdata_data;
+ wire [5:0] tag_array_0_tag_rdata_addr;
+ wire tag_array_0_tag_rdata_en;
+ wire tag_array_0_tag_rdata_clk;
+ reg [5:0] GEN_1;
+ reg GEN_2;
+ wire [19:0] tag_array_0_T_637_data;
+ wire [5:0] tag_array_0_T_637_addr;
+ wire tag_array_0_T_637_mask;
+ wire tag_array_0_T_637_en;
+ wire tag_array_0_T_637_clk;
+ reg [19:0] tag_array_1 [0:63];
+ wire [19:0] tag_array_1_tag_rdata_data;
+ wire [5:0] tag_array_1_tag_rdata_addr;
+ wire tag_array_1_tag_rdata_en;
+ wire tag_array_1_tag_rdata_clk;
+ reg [5:0] GEN_3;
+ reg GEN_4;
+ wire [19:0] tag_array_1_T_637_data;
+ wire [5:0] tag_array_1_T_637_addr;
+ wire tag_array_1_T_637_mask;
+ wire tag_array_1_T_637_en;
+ wire tag_array_1_T_637_clk;
+ reg [19:0] tag_array_2 [0:63];
+ wire [19:0] tag_array_2_tag_rdata_data;
+ wire [5:0] tag_array_2_tag_rdata_addr;
+ wire tag_array_2_tag_rdata_en;
+ wire tag_array_2_tag_rdata_clk;
+ reg [5:0] GEN_5;
+ reg GEN_6;
+ wire [19:0] tag_array_2_T_637_data;
+ wire [5:0] tag_array_2_T_637_addr;
+ wire tag_array_2_T_637_mask;
+ wire tag_array_2_T_637_en;
+ wire tag_array_2_T_637_clk;
+ reg [19:0] tag_array_3 [0:63];
+ wire [19:0] tag_array_3_tag_rdata_data;
+ wire [5:0] tag_array_3_tag_rdata_addr;
+ wire tag_array_3_tag_rdata_en;
+ wire tag_array_3_tag_rdata_clk;
+ reg [5:0] GEN_7;
+ reg GEN_8;
+ wire [19:0] tag_array_3_T_637_data;
+ wire [5:0] tag_array_3_T_637_addr;
+ wire tag_array_3_T_637_mask;
+ wire tag_array_3_T_637_en;
+ wire tag_array_3_T_637_clk;
+ wire [5:0] T_599;
+ wire T_601;
+ wire T_602;
+ wire [5:0] T_604;
+ wire [19:0] T_614_0;
+ wire [19:0] T_614_1;
+ wire [19:0] T_614_2;
+ wire [19:0] T_614_3;
+ wire T_621;
+ wire T_623;
+ wire T_625;
+ wire T_627;
+ wire T_629_0;
+ wire T_629_1;
+ wire T_629_2;
+ wire T_629_3;
+ reg [255:0] vb_array;
+ wire T_646;
+ wire T_647;
+ wire [7:0] T_648;
+ wire [255:0] T_651;
+ wire [255:0] T_652;
+ wire [255:0] T_653;
+ wire [255:0] T_654;
+ wire [255:0] T_655;
+ wire [255:0] T_656;
+ wire s1_disparity_0;
+ wire s1_disparity_1;
+ wire s1_disparity_2;
+ wire s1_disparity_3;
+ wire T_675;
+ wire [6:0] T_677;
+ wire [127:0] T_680;
+ wire [255:0] T_681;
+ wire [255:0] T_682;
+ wire [255:0] T_683;
+ wire [255:0] T_684;
+ wire [255:0] T_685;
+ wire T_686;
+ wire [6:0] T_688;
+ wire [127:0] T_691;
+ wire [255:0] T_692;
+ wire [255:0] T_693;
+ wire [255:0] T_694;
+ wire [255:0] T_695;
+ wire [255:0] T_696;
+ wire T_697;
+ wire [7:0] T_699;
+ wire [255:0] T_702;
+ wire [255:0] T_703;
+ wire [255:0] T_704;
+ wire [255:0] T_705;
+ wire [255:0] T_706;
+ wire [255:0] T_707;
+ wire T_708;
+ wire [7:0] T_710;
+ wire [255:0] T_713;
+ wire [255:0] T_714;
+ wire [255:0] T_715;
+ wire [255:0] T_716;
+ wire [255:0] T_717;
+ wire [255:0] T_718;
+ wire s1_tag_match_0;
+ wire s1_tag_match_1;
+ wire s1_tag_match_2;
+ wire s1_tag_match_3;
+ wire s1_tag_hit_0;
+ wire s1_tag_hit_1;
+ wire s1_tag_hit_2;
+ wire s1_tag_hit_3;
+ wire [127:0] s1_dout_0;
+ wire [127:0] s1_dout_1;
+ wire [127:0] s1_dout_2;
+ wire [127:0] s1_dout_3;
+ wire T_768;
+ wire [5:0] T_770;
+ wire [6:0] T_771;
+ wire [255:0] T_772;
+ wire T_773;
+ wire T_774;
+ wire T_775;
+ wire T_778;
+ wire T_779;
+ wire T_781;
+ wire T_782;
+ wire [19:0] T_783;
+ wire T_784;
+ wire T_785;
+ wire T_788;
+ wire T_789;
+ wire T_790;
+ wire T_792;
+ wire [5:0] T_794;
+ wire [6:0] T_795;
+ wire [255:0] T_796;
+ wire T_797;
+ wire T_798;
+ wire T_799;
+ wire T_802;
+ wire T_803;
+ wire T_805;
+ wire T_806;
+ wire [19:0] T_807;
+ wire T_808;
+ wire T_809;
+ wire T_812;
+ wire T_813;
+ wire T_814;
+ wire T_816;
+ wire [5:0] T_818;
+ wire [7:0] T_819;
+ wire [255:0] T_820;
+ wire T_821;
+ wire T_822;
+ wire T_823;
+ wire T_826;
+ wire T_827;
+ wire T_829;
+ wire T_830;
+ wire [19:0] T_831;
+ wire T_832;
+ wire T_833;
+ wire T_836;
+ wire T_837;
+ wire T_838;
+ wire T_840;
+ wire [5:0] T_842;
+ wire [7:0] T_843;
+ wire [255:0] T_844;
+ wire T_845;
+ wire T_846;
+ wire T_847;
+ wire T_850;
+ wire T_851;
+ wire T_853;
+ wire T_854;
+ wire [19:0] T_855;
+ wire T_856;
+ wire T_857;
+ wire T_860;
+ wire T_861;
+ wire T_862;
+ wire T_863;
+ wire T_864;
+ wire T_865;
+ wire T_866;
+ wire T_867;
+ wire T_868;
+ wire T_870;
+ wire T_871;
+ reg [127:0] T_874 [0:255];
+ wire [127:0] T_874_T_886_data;
+ wire [7:0] T_874_T_886_addr;
+ wire T_874_T_886_en;
+ wire T_874_T_886_clk;
+ reg [7:0] GEN_9;
+ reg GEN_10;
+ wire [127:0] T_874_T_879_data;
+ wire [7:0] T_874_T_879_addr;
+ wire T_874_T_879_mask;
+ wire T_874_T_879_en;
+ wire T_874_T_879_clk;
+ wire T_876;
+ wire T_877;
+ wire [7:0] T_878;
+ wire [7:0] T_880;
+ wire T_882;
+ wire T_883;
+ wire [7:0] T_885;
+ reg [127:0] T_889 [0:255];
+ wire [127:0] T_889_T_901_data;
+ wire [7:0] T_889_T_901_addr;
+ wire T_889_T_901_en;
+ wire T_889_T_901_clk;
+ reg [7:0] GEN_11;
+ reg GEN_12;
+ wire [127:0] T_889_T_894_data;
+ wire [7:0] T_889_T_894_addr;
+ wire T_889_T_894_mask;
+ wire T_889_T_894_en;
+ wire T_889_T_894_clk;
+ wire T_891;
+ wire T_892;
+ wire [7:0] T_893;
+ wire [7:0] T_895;
+ wire T_897;
+ wire T_898;
+ wire [7:0] T_900;
+ reg [127:0] T_904 [0:255];
+ wire [127:0] T_904_T_916_data;
+ wire [7:0] T_904_T_916_addr;
+ wire T_904_T_916_en;
+ wire T_904_T_916_clk;
+ reg [7:0] GEN_13;
+ reg GEN_14;
+ wire [127:0] T_904_T_909_data;
+ wire [7:0] T_904_T_909_addr;
+ wire T_904_T_909_mask;
+ wire T_904_T_909_en;
+ wire T_904_T_909_clk;
+ wire T_906;
+ wire T_907;
+ wire [7:0] T_908;
+ wire [7:0] T_910;
+ wire T_912;
+ wire T_913;
+ wire [7:0] T_915;
+ reg [127:0] T_919 [0:255];
+ wire [127:0] T_919_T_931_data;
+ wire [7:0] T_919_T_931_addr;
+ wire T_919_T_931_en;
+ wire T_919_T_931_clk;
+ reg [7:0] GEN_15;
+ reg GEN_16;
+ wire [127:0] T_919_T_924_data;
+ wire [7:0] T_919_T_924_addr;
+ wire T_919_T_924_mask;
+ wire T_919_T_924_en;
+ wire T_919_T_924_clk;
+ wire T_921;
+ wire T_922;
+ wire [7:0] T_923;
+ wire [7:0] T_925;
+ wire T_927;
+ wire T_928;
+ wire [7:0] T_930;
+ wire [127:0] T_933;
+ wire [127:0] T_935;
+ wire [127:0] T_937;
+ wire [127:0] T_939;
+ wire [127:0] T_941;
+ wire [127:0] T_942;
+ wire [127:0] T_943;
+ wire [127:0] T_944;
+ wire T_945;
+ wire [25:0] T_946;
+ wire [3:0] T_957;
+ wire [5:0] T_958;
+ wire [9:0] T_959;
+ wire [5:0] T_961;
+ wire [8:0] T_962;
+ wire [1:0] T_964;
+ wire [1:0] T_966;
+ wire [3:0] T_968;
+ wire [5:0] T_969;
+ wire [9:0] T_970;
+ wire [5:0] T_972;
+ wire [5:0] T_974;
+ wire T_975;
+ wire [5:0] T_976;
+ wire T_977;
+ wire [5:0] T_978;
+ wire T_979;
+ wire [9:0] T_980;
+ wire T_981;
+ wire [9:0] T_982;
+ wire T_983;
+ wire [9:0] T_984;
+ wire T_985;
+ wire [9:0] T_986;
+ wire T_987;
+ wire [9:0] T_988;
+ wire [25:0] T_1020_addr_block;
+ wire [1:0] T_1020_client_xact_id;
+ wire [1:0] T_1020_addr_beat;
+ wire T_1020_is_builtin_type;
+ wire [2:0] T_1020_a_type;
+ wire [16:0] T_1020_union;
+ wire [127:0] T_1020_data;
+ wire T_1051;
+ wire T_1053;
+ wire T_1054;
+ wire T_1055;
+ reg [31:0] GEN_0;
+ FlowThroughSerializer T_553 (
+ .clk(T_553_clk),
+ .reset(T_553_reset),
+ .io_in_ready(T_553_io_in_ready),
+ .io_in_valid(T_553_io_in_valid),
+ .io_in_bits_addr_beat(T_553_io_in_bits_addr_beat),
+ .io_in_bits_client_xact_id(T_553_io_in_bits_client_xact_id),
+ .io_in_bits_manager_xact_id(T_553_io_in_bits_manager_xact_id),
+ .io_in_bits_is_builtin_type(T_553_io_in_bits_is_builtin_type),
+ .io_in_bits_g_type(T_553_io_in_bits_g_type),
+ .io_in_bits_data(T_553_io_in_bits_data),
+ .io_out_ready(T_553_io_out_ready),
+ .io_out_valid(T_553_io_out_valid),
+ .io_out_bits_addr_beat(T_553_io_out_bits_addr_beat),
+ .io_out_bits_client_xact_id(T_553_io_out_bits_client_xact_id),
+ .io_out_bits_manager_xact_id(T_553_io_out_bits_manager_xact_id),
+ .io_out_bits_is_builtin_type(T_553_io_out_bits_is_builtin_type),
+ .io_out_bits_g_type(T_553_io_out_bits_g_type),
+ .io_out_bits_data(T_553_io_out_bits_data),
+ .io_cnt(T_553_io_cnt),
+ .io_done(T_553_io_done)
+ );
+ assign io_resp_valid = s1_hit;
+ assign io_resp_bits_data = GEN_0;
+ assign io_resp_bits_datablock = T_944;
+ assign io_mem_acquire_valid = T_945;
+ assign io_mem_acquire_bits_addr_block = T_1020_addr_block;
+ assign io_mem_acquire_bits_client_xact_id = T_1020_client_xact_id;
+ assign io_mem_acquire_bits_addr_beat = T_1020_addr_beat;
+ assign io_mem_acquire_bits_is_builtin_type = T_1020_is_builtin_type;
+ assign io_mem_acquire_bits_a_type = T_1020_a_type;
+ assign io_mem_acquire_bits_union = T_1020_union;
+ assign io_mem_acquire_bits_data = T_1020_data;
+ assign io_mem_grant_ready = T_553_io_in_ready;
+ assign stall = io_resp_ready == 1'h0;
+ assign rdy = T_548;
+ assign s1_any_tag_hit = T_871;
+ assign s1_addr = {io_req_bits_ppn,s1_pgoff};
+ assign s1_tag = s1_addr[31:12];
+ assign T_523 = s1_valid & stall;
+ assign s0_valid = io_req_valid | T_523;
+ assign T_525 = s1_valid & stall;
+ assign s0_pgoff = T_525 ? s1_pgoff : io_req_bits_idx;
+ assign T_527 = io_req_valid & rdy;
+ assign T_528 = s1_valid & stall;
+ assign T_530 = io_req_bits_kill == 1'h0;
+ assign T_531 = T_528 & T_530;
+ assign T_532 = T_527 | T_531;
+ assign T_533 = io_req_valid & rdy;
+ assign T_535 = io_req_bits_kill == 1'h0;
+ assign T_536 = s1_valid & T_535;
+ assign T_537 = state == 1'h0;
+ assign out_valid = T_536 & T_537;
+ assign s1_idx = s1_addr[11:6];
+ assign s1_offset = s1_addr[5:0];
+ assign s1_hit = out_valid & s1_any_tag_hit;
+ assign T_543 = s1_any_tag_hit == 1'h0;
+ assign s1_miss = out_valid & T_543;
+ assign T_545 = state == 1'h0;
+ assign T_547 = s1_miss == 1'h0;
+ assign T_548 = T_545 & T_547;
+ assign T_549 = state == 1'h0;
+ assign T_550 = s1_valid & T_549;
+ assign T_551 = T_550 & s1_miss;
+ assign refill_tag = refill_addr[31:12];
+ assign T_553_clk = clk;
+ assign T_553_reset = reset;
+ assign T_553_io_in_valid = io_mem_grant_valid;
+ assign T_553_io_in_bits_addr_beat = io_mem_grant_bits_addr_beat;
+ assign T_553_io_in_bits_client_xact_id = io_mem_grant_bits_client_xact_id;
+ assign T_553_io_in_bits_manager_xact_id = io_mem_grant_bits_manager_xact_id;
+ assign T_553_io_in_bits_is_builtin_type = io_mem_grant_bits_is_builtin_type;
+ assign T_553_io_in_bits_g_type = io_mem_grant_bits_g_type;
+ assign T_553_io_in_bits_data = io_mem_grant_bits_data;
+ assign T_553_io_out_ready = 1'h1;
+ assign T_554 = T_553_io_out_ready & T_553_io_out_valid;
+ assign T_558 = refill_cnt == 2'h3;
+ assign T_560 = 1'h0 & T_558;
+ assign T_563 = refill_cnt + 1'h1;
+ assign T_564 = T_563[1:0];
+ assign T_565 = T_560 ? 1'h0 : T_564;
+ assign refill_wrap = T_554 & T_558;
+ assign T_567 = state == 2'h3;
+ assign refill_done = T_567 & refill_wrap;
+ assign T_572 = T_571[0];
+ assign T_573 = T_571[2];
+ assign T_574 = T_572 ^ T_573;
+ assign T_575 = T_571[3];
+ assign T_576 = T_574 ^ T_575;
+ assign T_577 = T_571[5];
+ assign T_578 = T_576 ^ T_577;
+ assign T_579 = T_571[15:1];
+ assign T_580 = {T_578,T_579};
+ assign repl_way = T_571[1:0];
+ assign tag_array_0_tag_rdata_addr = T_604;
+ assign tag_array_0_tag_rdata_en = 1'h1;
+ assign tag_array_0_tag_rdata_clk = clk;
+ assign tag_array_0_tag_rdata_data = tag_array_0[GEN_1];
+ assign tag_array_0_T_637_data = T_614_0;
+ assign tag_array_0_T_637_addr = s1_idx;
+ assign tag_array_0_T_637_mask = refill_done ? T_629_0 ? 1'h1 : 1'h0 : 1'h0;
+ assign tag_array_0_T_637_en = refill_done ? 1'h1 : 1'h0;
+ assign tag_array_0_T_637_clk = clk;
+ assign tag_array_1_tag_rdata_addr = T_604;
+ assign tag_array_1_tag_rdata_en = 1'h1;
+ assign tag_array_1_tag_rdata_clk = clk;
+ assign tag_array_1_tag_rdata_data = tag_array_1[GEN_3];
+ assign tag_array_1_T_637_data = T_614_1;
+ assign tag_array_1_T_637_addr = s1_idx;
+ assign tag_array_1_T_637_mask = refill_done ? T_629_1 ? 1'h1 : 1'h0 : 1'h0;
+ assign tag_array_1_T_637_en = refill_done ? 1'h1 : 1'h0;
+ assign tag_array_1_T_637_clk = clk;
+ assign tag_array_2_tag_rdata_addr = T_604;
+ assign tag_array_2_tag_rdata_en = 1'h1;
+ assign tag_array_2_tag_rdata_clk = clk;
+ assign tag_array_2_tag_rdata_data = tag_array_2[GEN_5];
+ assign tag_array_2_T_637_data = T_614_2;
+ assign tag_array_2_T_637_addr = s1_idx;
+ assign tag_array_2_T_637_mask = refill_done ? T_629_2 ? 1'h1 : 1'h0 : 1'h0;
+ assign tag_array_2_T_637_en = refill_done ? 1'h1 : 1'h0;
+ assign tag_array_2_T_637_clk = clk;
+ assign tag_array_3_tag_rdata_addr = T_604;
+ assign tag_array_3_tag_rdata_en = 1'h1;
+ assign tag_array_3_tag_rdata_clk = clk;
+ assign tag_array_3_tag_rdata_data = tag_array_3[GEN_7];
+ assign tag_array_3_T_637_data = T_614_3;
+ assign tag_array_3_T_637_addr = s1_idx;
+ assign tag_array_3_T_637_mask = refill_done ? T_629_3 ? 1'h1 : 1'h0 : 1'h0;
+ assign tag_array_3_T_637_en = refill_done ? 1'h1 : 1'h0;
+ assign tag_array_3_T_637_clk = clk;
+ assign T_599 = s0_pgoff[11:6];
+ assign T_601 = refill_done == 1'h0;
+ assign T_602 = T_601 & s0_valid;
+ assign T_604 = T_599;
+ assign T_614_0 = refill_tag;
+ assign T_614_1 = refill_tag;
+ assign T_614_2 = refill_tag;
+ assign T_614_3 = refill_tag;
+ assign T_621 = repl_way == 1'h0;
+ assign T_623 = repl_way == 1'h1;
+ assign T_625 = repl_way == 2'h2;
+ assign T_627 = repl_way == 2'h3;
+ assign T_629_0 = T_621;
+ assign T_629_1 = T_623;
+ assign T_629_2 = T_625;
+ assign T_629_3 = T_627;
+ assign T_646 = invalidated == 1'h0;
+ assign T_647 = refill_done & T_646;
+ assign T_648 = {repl_way,s1_idx};
+ assign T_651 = 1'h1 << T_648;
+ assign T_652 = vb_array | T_651;
+ assign T_653 = ~ vb_array;
+ assign T_654 = T_653 | T_651;
+ assign T_655 = ~ T_654;
+ assign T_656 = 1'h1 ? T_652 : T_655;
+ assign s1_disparity_0 = T_790;
+ assign s1_disparity_1 = T_814;
+ assign s1_disparity_2 = T_838;
+ assign s1_disparity_3 = T_862;
+ assign T_675 = s1_valid & s1_disparity_0;
+ assign T_677 = {1'h0,s1_idx};
+ assign T_680 = 1'h1 << T_677;
+ assign T_681 = vb_array | T_680;
+ assign T_682 = ~ vb_array;
+ assign T_683 = T_682 | T_680;
+ assign T_684 = ~ T_683;
+ assign T_685 = 1'h0 ? T_681 : T_684;
+ assign T_686 = s1_valid & s1_disparity_1;
+ assign T_688 = {1'h1,s1_idx};
+ assign T_691 = 1'h1 << T_688;
+ assign T_692 = vb_array | T_691;
+ assign T_693 = ~ vb_array;
+ assign T_694 = T_693 | T_691;
+ assign T_695 = ~ T_694;
+ assign T_696 = 1'h0 ? T_692 : T_695;
+ assign T_697 = s1_valid & s1_disparity_2;
+ assign T_699 = {2'h2,s1_idx};
+ assign T_702 = 1'h1 << T_699;
+ assign T_703 = vb_array | T_702;
+ assign T_704 = ~ vb_array;
+ assign T_705 = T_704 | T_702;
+ assign T_706 = ~ T_705;
+ assign T_707 = 1'h0 ? T_703 : T_706;
+ assign T_708 = s1_valid & s1_disparity_3;
+ assign T_710 = {2'h3,s1_idx};
+ assign T_713 = 1'h1 << T_710;
+ assign T_714 = vb_array | T_713;
+ assign T_715 = ~ vb_array;
+ assign T_716 = T_715 | T_713;
+ assign T_717 = ~ T_716;
+ assign T_718 = 1'h0 ? T_714 : T_717;
+ assign s1_tag_match_0 = T_784;
+ assign s1_tag_match_1 = T_808;
+ assign s1_tag_match_2 = T_832;
+ assign s1_tag_match_3 = T_856;
+ assign s1_tag_hit_0 = T_785;
+ assign s1_tag_hit_1 = T_809;
+ assign s1_tag_hit_2 = T_833;
+ assign s1_tag_hit_3 = T_857;
+ assign s1_dout_0 = T_874_T_886_data;
+ assign s1_dout_1 = T_889_T_901_data;
+ assign s1_dout_2 = T_904_T_916_data;
+ assign s1_dout_3 = T_919_T_931_data;
+ assign T_768 = io_invalidate == 1'h0;
+ assign T_770 = s1_pgoff[11:6];
+ assign T_771 = {1'h0,T_770};
+ assign T_772 = vb_array >> T_771;
+ assign T_773 = T_772[0];
+ assign T_774 = T_773;
+ assign T_775 = T_768 & T_774;
+ assign T_778 = 1'h0 | 1'h0;
+ assign T_779 = s1_valid & rdy;
+ assign T_781 = stall == 1'h0;
+ assign T_782 = T_779 & T_781;
+ assign T_783 = tag_array_0_tag_rdata_data;
+ assign T_784 = T_783 == s1_tag;
+ assign T_785 = T_775 & s1_tag_match_0;
+ assign T_788 = 1'h0 | 1'h0;
+ assign T_789 = T_778 | T_788;
+ assign T_790 = T_775 & T_789;
+ assign T_792 = io_invalidate == 1'h0;
+ assign T_794 = s1_pgoff[11:6];
+ assign T_795 = {1'h1,T_794};
+ assign T_796 = vb_array >> T_795;
+ assign T_797 = T_796[0];
+ assign T_798 = T_797;
+ assign T_799 = T_792 & T_798;
+ assign T_802 = 1'h0 | 1'h0;
+ assign T_803 = s1_valid & rdy;
+ assign T_805 = stall == 1'h0;
+ assign T_806 = T_803 & T_805;
+ assign T_807 = tag_array_1_tag_rdata_data;
+ assign T_808 = T_807 == s1_tag;
+ assign T_809 = T_799 & s1_tag_match_1;
+ assign T_812 = 1'h0 | 1'h0;
+ assign T_813 = T_802 | T_812;
+ assign T_814 = T_799 & T_813;
+ assign T_816 = io_invalidate == 1'h0;
+ assign T_818 = s1_pgoff[11:6];
+ assign T_819 = {2'h2,T_818};
+ assign T_820 = vb_array >> T_819;
+ assign T_821 = T_820[0];
+ assign T_822 = T_821;
+ assign T_823 = T_816 & T_822;
+ assign T_826 = 1'h0 | 1'h0;
+ assign T_827 = s1_valid & rdy;
+ assign T_829 = stall == 1'h0;
+ assign T_830 = T_827 & T_829;
+ assign T_831 = tag_array_2_tag_rdata_data;
+ assign T_832 = T_831 == s1_tag;
+ assign T_833 = T_823 & s1_tag_match_2;
+ assign T_836 = 1'h0 | 1'h0;
+ assign T_837 = T_826 | T_836;
+ assign T_838 = T_823 & T_837;
+ assign T_840 = io_invalidate == 1'h0;
+ assign T_842 = s1_pgoff[11:6];
+ assign T_843 = {2'h3,T_842};
+ assign T_844 = vb_array >> T_843;
+ assign T_845 = T_844[0];
+ assign T_846 = T_845;
+ assign T_847 = T_840 & T_846;
+ assign T_850 = 1'h0 | 1'h0;
+ assign T_851 = s1_valid & rdy;
+ assign T_853 = stall == 1'h0;
+ assign T_854 = T_851 & T_853;
+ assign T_855 = tag_array_3_tag_rdata_data;
+ assign T_856 = T_855 == s1_tag;
+ assign T_857 = T_847 & s1_tag_match_3;
+ assign T_860 = 1'h0 | 1'h0;
+ assign T_861 = T_850 | T_860;
+ assign T_862 = T_847 & T_861;
+ assign T_863 = s1_tag_hit_0 | s1_tag_hit_1;
+ assign T_864 = T_863 | s1_tag_hit_2;
+ assign T_865 = T_864 | s1_tag_hit_3;
+ assign T_866 = s1_disparity_0 | s1_disparity_1;
+ assign T_867 = T_866 | s1_disparity_2;
+ assign T_868 = T_867 | s1_disparity_3;
+ assign T_870 = T_868 == 1'h0;
+ assign T_871 = T_865 & T_870;
+ assign T_874_T_886_addr = T_885;
+ assign T_874_T_886_en = 1'h1;
+ assign T_874_T_886_clk = clk;
+ assign T_874_T_886_data = T_874[GEN_9];
+ assign T_874_T_879_data = T_553_io_out_bits_data;
+ assign T_874_T_879_addr = T_878;
+ assign T_874_T_879_mask = T_877 ? 1'h1 : 1'h0;
+ assign T_874_T_879_en = T_877 ? 1'h1 : 1'h0;
+ assign T_874_T_879_clk = clk;
+ assign T_876 = repl_way == 1'h0;
+ assign T_877 = T_553_io_out_valid & T_876;
+ assign T_878 = {s1_idx,refill_cnt};
+ assign T_880 = s0_pgoff[11:4];
+ assign T_882 = T_877 == 1'h0;
+ assign T_883 = T_882 & s0_valid;
+ assign T_885 = T_880;
+ assign T_889_T_901_addr = T_900;
+ assign T_889_T_901_en = 1'h1;
+ assign T_889_T_901_clk = clk;
+ assign T_889_T_901_data = T_889[GEN_11];
+ assign T_889_T_894_data = T_553_io_out_bits_data;
+ assign T_889_T_894_addr = T_893;
+ assign T_889_T_894_mask = T_892 ? 1'h1 : 1'h0;
+ assign T_889_T_894_en = T_892 ? 1'h1 : 1'h0;
+ assign T_889_T_894_clk = clk;
+ assign T_891 = repl_way == 1'h1;
+ assign T_892 = T_553_io_out_valid & T_891;
+ assign T_893 = {s1_idx,refill_cnt};
+ assign T_895 = s0_pgoff[11:4];
+ assign T_897 = T_892 == 1'h0;
+ assign T_898 = T_897 & s0_valid;
+ assign T_900 = T_895;
+ assign T_904_T_916_addr = T_915;
+ assign T_904_T_916_en = 1'h1;
+ assign T_904_T_916_clk = clk;
+ assign T_904_T_916_data = T_904[GEN_13];
+ assign T_904_T_909_data = T_553_io_out_bits_data;
+ assign T_904_T_909_addr = T_908;
+ assign T_904_T_909_mask = T_907 ? 1'h1 : 1'h0;
+ assign T_904_T_909_en = T_907 ? 1'h1 : 1'h0;
+ assign T_904_T_909_clk = clk;
+ assign T_906 = repl_way == 2'h2;
+ assign T_907 = T_553_io_out_valid & T_906;
+ assign T_908 = {s1_idx,refill_cnt};
+ assign T_910 = s0_pgoff[11:4];
+ assign T_912 = T_907 == 1'h0;
+ assign T_913 = T_912 & s0_valid;
+ assign T_915 = T_910;
+ assign T_919_T_931_addr = T_930;
+ assign T_919_T_931_en = 1'h1;
+ assign T_919_T_931_clk = clk;
+ assign T_919_T_931_data = T_919[GEN_15];
+ assign T_919_T_924_data = T_553_io_out_bits_data;
+ assign T_919_T_924_addr = T_923;
+ assign T_919_T_924_mask = T_922 ? 1'h1 : 1'h0;
+ assign T_919_T_924_en = T_922 ? 1'h1 : 1'h0;
+ assign T_919_T_924_clk = clk;
+ assign T_921 = repl_way == 2'h3;
+ assign T_922 = T_553_io_out_valid & T_921;
+ assign T_923 = {s1_idx,refill_cnt};
+ assign T_925 = s0_pgoff[11:4];
+ assign T_927 = T_922 == 1'h0;
+ assign T_928 = T_927 & s0_valid;
+ assign T_930 = T_925;
+ assign T_933 = s1_tag_hit_0 ? s1_dout_0 : 1'h0;
+ assign T_935 = s1_tag_hit_1 ? s1_dout_1 : 1'h0;
+ assign T_937 = s1_tag_hit_2 ? s1_dout_2 : 1'h0;
+ assign T_939 = s1_tag_hit_3 ? s1_dout_3 : 1'h0;
+ assign T_941 = T_933 | T_935;
+ assign T_942 = T_941 | T_937;
+ assign T_943 = T_942 | T_939;
+ assign T_944 = T_943;
+ assign T_945 = state == 1'h1;
+ assign T_946 = refill_addr[31:6];
+ assign T_957 = {1'h0,3'h7};
+ assign T_958 = {5'h0,1'h1};
+ assign T_959 = {T_957,T_958};
+ assign T_961 = {5'h0,1'h1};
+ assign T_962 = {3'h7,T_961};
+ assign T_964 = {1'h0,1'h1};
+ assign T_966 = {1'h0,1'h1};
+ assign T_968 = {1'h0,3'h7};
+ assign T_969 = {5'h0,1'h1};
+ assign T_970 = {T_968,T_969};
+ assign T_972 = {5'h0,1'h1};
+ assign T_974 = {5'h1,1'h1};
+ assign T_975 = 3'h6 == 3'h1;
+ assign T_976 = T_975 ? T_974 : 1'h0;
+ assign T_977 = 3'h5 == 3'h1;
+ assign T_978 = T_977 ? T_972 : T_976;
+ assign T_979 = 3'h4 == 3'h1;
+ assign T_980 = T_979 ? T_970 : T_978;
+ assign T_981 = 3'h3 == 3'h1;
+ assign T_982 = T_981 ? T_966 : T_980;
+ assign T_983 = 3'h2 == 3'h1;
+ assign T_984 = T_983 ? T_964 : T_982;
+ assign T_985 = 3'h1 == 3'h1;
+ assign T_986 = T_985 ? T_962 : T_984;
+ assign T_987 = 3'h0 == 3'h1;
+ assign T_988 = T_987 ? T_959 : T_986;
+ assign T_1020_addr_block = T_946;
+ assign T_1020_client_xact_id = 1'h0;
+ assign T_1020_addr_beat = 1'h0;
+ assign T_1020_is_builtin_type = 1'h1;
+ assign T_1020_a_type = 3'h1;
+ assign T_1020_union = T_988;
+ assign T_1020_data = 1'h0;
+ assign T_1051 = 1'h0 == state;
+ assign T_1053 = 1'h1 == state;
+ assign T_1054 = 2'h2 == state;
+ assign T_1055 = 2'h3 == state;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ state = {1{$random}};
+ invalidated = {1{$random}};
+ refill_addr = {1{$random}};
+ s1_valid = {1{$random}};
+ s1_pgoff = {1{$random}};
+ refill_cnt = {1{$random}};
+ T_571 = {1{$random}};
+ for (initvar = 0; initvar < 64; initvar = initvar+1)
+ tag_array_0[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 64; initvar = initvar+1)
+ tag_array_1[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 64; initvar = initvar+1)
+ tag_array_2[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 64; initvar = initvar+1)
+ tag_array_3[initvar] = {1{$random}};
+ vb_array = {8{$random}};
+ for (initvar = 0; initvar < 256; initvar = initvar+1)
+ T_874[initvar] = {4{$random}};
+ for (initvar = 0; initvar < 256; initvar = initvar+1)
+ T_889[initvar] = {4{$random}};
+ for (initvar = 0; initvar < 256; initvar = initvar+1)
+ T_904[initvar] = {4{$random}};
+ for (initvar = 0; initvar < 256; initvar = initvar+1)
+ T_919[initvar] = {4{$random}};
+ GEN_0 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1055) begin
+ if(refill_done) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1054) begin
+ if(io_mem_grant_valid) begin
+ state <= 2'h3;
+ end else begin
+ if(T_1053) begin
+ if(io_mem_acquire_ready) begin
+ state <= 2'h2;
+ end else begin
+ if(T_1051) begin
+ if(s1_miss) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1051) begin
+ if(s1_miss) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1053) begin
+ if(io_mem_acquire_ready) begin
+ state <= 2'h2;
+ end else begin
+ if(T_1051) begin
+ if(s1_miss) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1051) begin
+ if(s1_miss) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1054) begin
+ if(io_mem_grant_valid) begin
+ state <= 2'h3;
+ end else begin
+ if(T_1053) begin
+ if(io_mem_acquire_ready) begin
+ state <= 2'h2;
+ end else begin
+ if(T_1051) begin
+ if(s1_miss) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1051) begin
+ if(s1_miss) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1053) begin
+ if(io_mem_acquire_ready) begin
+ state <= 2'h2;
+ end else begin
+ if(T_1051) begin
+ if(s1_miss) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1051) begin
+ if(s1_miss) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1051) begin
+ invalidated <= 1'h0;
+ end else begin
+ if(io_invalidate) begin
+ invalidated <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_551) begin
+ refill_addr <= s1_addr;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ s1_valid <= 1'h0;
+ end else begin
+ s1_valid <= T_532;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_533) begin
+ s1_pgoff <= io_req_bits_idx;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ refill_cnt <= 2'h0;
+ end else begin
+ if(T_554) begin
+ refill_cnt <= T_565;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_571 <= 16'h1;
+ end else begin
+ if(s1_miss) begin
+ T_571 <= T_580;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ vb_array <= 256'h0;
+ end else begin
+ if(T_708) begin
+ vb_array <= T_718;
+ end else begin
+ if(T_697) begin
+ vb_array <= T_707;
+ end else begin
+ if(T_686) begin
+ vb_array <= T_696;
+ end else begin
+ if(T_675) begin
+ vb_array <= T_685;
+ end else begin
+ if(io_invalidate) begin
+ vb_array <= 1'h0;
+ end else begin
+ if(T_647) begin
+ vb_array <= T_656;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ always @(posedge tag_array_0_tag_rdata_clk) begin
+ GEN_1 <= tag_array_0_tag_rdata_addr;
+ GEN_2 <= tag_array_0_tag_rdata_en;
+ end
+ always @(posedge tag_array_0_T_637_clk) begin
+ if(tag_array_0_T_637_en & tag_array_0_T_637_mask) begin
+ tag_array_0[tag_array_0_T_637_addr] <= tag_array_0_T_637_data;
+ end
+ end
+ always @(posedge tag_array_1_tag_rdata_clk) begin
+ GEN_3 <= tag_array_1_tag_rdata_addr;
+ GEN_4 <= tag_array_1_tag_rdata_en;
+ end
+ always @(posedge tag_array_1_T_637_clk) begin
+ if(tag_array_1_T_637_en & tag_array_1_T_637_mask) begin
+ tag_array_1[tag_array_1_T_637_addr] <= tag_array_1_T_637_data;
+ end
+ end
+ always @(posedge tag_array_2_tag_rdata_clk) begin
+ GEN_5 <= tag_array_2_tag_rdata_addr;
+ GEN_6 <= tag_array_2_tag_rdata_en;
+ end
+ always @(posedge tag_array_2_T_637_clk) begin
+ if(tag_array_2_T_637_en & tag_array_2_T_637_mask) begin
+ tag_array_2[tag_array_2_T_637_addr] <= tag_array_2_T_637_data;
+ end
+ end
+ always @(posedge tag_array_3_tag_rdata_clk) begin
+ GEN_7 <= tag_array_3_tag_rdata_addr;
+ GEN_8 <= tag_array_3_tag_rdata_en;
+ end
+ always @(posedge tag_array_3_T_637_clk) begin
+ if(tag_array_3_T_637_en & tag_array_3_T_637_mask) begin
+ tag_array_3[tag_array_3_T_637_addr] <= tag_array_3_T_637_data;
+ end
+ end
+ always @(posedge T_874_T_886_clk) begin
+ GEN_9 <= T_874_T_886_addr;
+ GEN_10 <= T_874_T_886_en;
+ end
+ always @(posedge T_874_T_879_clk) begin
+ if(T_874_T_879_en & T_874_T_879_mask) begin
+ T_874[T_874_T_879_addr] <= T_874_T_879_data;
+ end
+ end
+ always @(posedge T_889_T_901_clk) begin
+ GEN_11 <= T_889_T_901_addr;
+ GEN_12 <= T_889_T_901_en;
+ end
+ always @(posedge T_889_T_894_clk) begin
+ if(T_889_T_894_en & T_889_T_894_mask) begin
+ T_889[T_889_T_894_addr] <= T_889_T_894_data;
+ end
+ end
+ always @(posedge T_904_T_916_clk) begin
+ GEN_13 <= T_904_T_916_addr;
+ GEN_14 <= T_904_T_916_en;
+ end
+ always @(posedge T_904_T_909_clk) begin
+ if(T_904_T_909_en & T_904_T_909_mask) begin
+ T_904[T_904_T_909_addr] <= T_904_T_909_data;
+ end
+ end
+ always @(posedge T_919_T_931_clk) begin
+ GEN_15 <= T_919_T_931_addr;
+ GEN_16 <= T_919_T_931_en;
+ end
+ always @(posedge T_919_T_924_clk) begin
+ if(T_919_T_924_en & T_919_T_924_mask) begin
+ T_919[T_919_T_924_addr] <= T_919_T_924_data;
+ end
+ end
+endmodule
+module RocketCAM(
+ input clk,
+ input reset,
+ input io_clear,
+ input [7:0] io_clear_mask,
+ input [33:0] io_tag,
+ output io_hit,
+ output [7:0] io_hits,
+ output [7:0] io_valid_bits,
+ input io_write,
+ input [33:0] io_write_tag,
+ input [2:0] io_write_addr
+);
+ reg [33:0] cam_tags [0:7];
+ wire [33:0] cam_tags_T_32_data;
+ wire [2:0] cam_tags_T_32_addr;
+ wire cam_tags_T_32_en;
+ wire cam_tags_T_32_clk;
+ wire [33:0] cam_tags_T_37_data;
+ wire [2:0] cam_tags_T_37_addr;
+ wire cam_tags_T_37_en;
+ wire cam_tags_T_37_clk;
+ wire [33:0] cam_tags_T_42_data;
+ wire [2:0] cam_tags_T_42_addr;
+ wire cam_tags_T_42_en;
+ wire cam_tags_T_42_clk;
+ wire [33:0] cam_tags_T_47_data;
+ wire [2:0] cam_tags_T_47_addr;
+ wire cam_tags_T_47_en;
+ wire cam_tags_T_47_clk;
+ wire [33:0] cam_tags_T_52_data;
+ wire [2:0] cam_tags_T_52_addr;
+ wire cam_tags_T_52_en;
+ wire cam_tags_T_52_clk;
+ wire [33:0] cam_tags_T_57_data;
+ wire [2:0] cam_tags_T_57_addr;
+ wire cam_tags_T_57_en;
+ wire cam_tags_T_57_clk;
+ wire [33:0] cam_tags_T_62_data;
+ wire [2:0] cam_tags_T_62_addr;
+ wire cam_tags_T_62_en;
+ wire cam_tags_T_62_clk;
+ wire [33:0] cam_tags_T_67_data;
+ wire [2:0] cam_tags_T_67_addr;
+ wire cam_tags_T_67_en;
+ wire cam_tags_T_67_clk;
+ wire [33:0] cam_tags_T_27_data;
+ wire [2:0] cam_tags_T_27_addr;
+ wire cam_tags_T_27_mask;
+ wire cam_tags_T_27_en;
+ wire cam_tags_T_27_clk;
+ reg [7:0] vb_array;
+ wire [7:0] T_21;
+ wire [7:0] T_22;
+ wire [7:0] T_23;
+ wire [7:0] T_24;
+ wire [7:0] T_25;
+ wire [7:0] T_26;
+ wire [7:0] T_28;
+ wire [7:0] T_29;
+ wire T_30;
+ wire T_33;
+ wire T_34;
+ wire T_35;
+ wire T_38;
+ wire T_39;
+ wire T_40;
+ wire T_43;
+ wire T_44;
+ wire T_45;
+ wire T_48;
+ wire T_49;
+ wire T_50;
+ wire T_53;
+ wire T_54;
+ wire T_55;
+ wire T_58;
+ wire T_59;
+ wire T_60;
+ wire T_63;
+ wire T_64;
+ wire T_65;
+ wire T_68;
+ wire T_69;
+ wire T_71_0;
+ wire T_71_1;
+ wire T_71_2;
+ wire T_71_3;
+ wire T_71_4;
+ wire T_71_5;
+ wire T_71_6;
+ wire T_71_7;
+ wire [1:0] T_81;
+ wire [1:0] T_82;
+ wire [3:0] T_83;
+ wire [1:0] T_84;
+ wire [1:0] T_85;
+ wire [3:0] T_86;
+ wire [7:0] T_87;
+ wire T_89;
+ assign io_hit = T_89;
+ assign io_hits = T_87;
+ assign io_valid_bits = vb_array;
+ assign cam_tags_T_32_addr = 1'h0;
+ assign cam_tags_T_32_en = 1'h1;
+ assign cam_tags_T_32_clk = clk;
+ assign cam_tags_T_32_data = cam_tags[cam_tags_T_32_addr];
+ assign cam_tags_T_37_addr = 1'h1;
+ assign cam_tags_T_37_en = 1'h1;
+ assign cam_tags_T_37_clk = clk;
+ assign cam_tags_T_37_data = cam_tags[cam_tags_T_37_addr];
+ assign cam_tags_T_42_addr = 2'h2;
+ assign cam_tags_T_42_en = 1'h1;
+ assign cam_tags_T_42_clk = clk;
+ assign cam_tags_T_42_data = cam_tags[cam_tags_T_42_addr];
+ assign cam_tags_T_47_addr = 2'h3;
+ assign cam_tags_T_47_en = 1'h1;
+ assign cam_tags_T_47_clk = clk;
+ assign cam_tags_T_47_data = cam_tags[cam_tags_T_47_addr];
+ assign cam_tags_T_52_addr = 3'h4;
+ assign cam_tags_T_52_en = 1'h1;
+ assign cam_tags_T_52_clk = clk;
+ assign cam_tags_T_52_data = cam_tags[cam_tags_T_52_addr];
+ assign cam_tags_T_57_addr = 3'h5;
+ assign cam_tags_T_57_en = 1'h1;
+ assign cam_tags_T_57_clk = clk;
+ assign cam_tags_T_57_data = cam_tags[cam_tags_T_57_addr];
+ assign cam_tags_T_62_addr = 3'h6;
+ assign cam_tags_T_62_en = 1'h1;
+ assign cam_tags_T_62_clk = clk;
+ assign cam_tags_T_62_data = cam_tags[cam_tags_T_62_addr];
+ assign cam_tags_T_67_addr = 3'h7;
+ assign cam_tags_T_67_en = 1'h1;
+ assign cam_tags_T_67_clk = clk;
+ assign cam_tags_T_67_data = cam_tags[cam_tags_T_67_addr];
+ assign cam_tags_T_27_data = io_write_tag;
+ assign cam_tags_T_27_addr = io_write_addr;
+ assign cam_tags_T_27_mask = io_write ? 1'h1 : 1'h0;
+ assign cam_tags_T_27_en = io_write ? 1'h1 : 1'h0;
+ assign cam_tags_T_27_clk = clk;
+ assign T_21 = 1'h1 << io_write_addr;
+ assign T_22 = vb_array | T_21;
+ assign T_23 = ~ vb_array;
+ assign T_24 = T_23 | T_21;
+ assign T_25 = ~ T_24;
+ assign T_26 = 1'h1 ? T_22 : T_25;
+ assign T_28 = ~ io_clear_mask;
+ assign T_29 = vb_array & T_28;
+ assign T_30 = vb_array[0];
+ assign T_33 = cam_tags_T_32_data == io_tag;
+ assign T_34 = T_30 & T_33;
+ assign T_35 = vb_array[1];
+ assign T_38 = cam_tags_T_37_data == io_tag;
+ assign T_39 = T_35 & T_38;
+ assign T_40 = vb_array[2];
+ assign T_43 = cam_tags_T_42_data == io_tag;
+ assign T_44 = T_40 & T_43;
+ assign T_45 = vb_array[3];
+ assign T_48 = cam_tags_T_47_data == io_tag;
+ assign T_49 = T_45 & T_48;
+ assign T_50 = vb_array[4];
+ assign T_53 = cam_tags_T_52_data == io_tag;
+ assign T_54 = T_50 & T_53;
+ assign T_55 = vb_array[5];
+ assign T_58 = cam_tags_T_57_data == io_tag;
+ assign T_59 = T_55 & T_58;
+ assign T_60 = vb_array[6];
+ assign T_63 = cam_tags_T_62_data == io_tag;
+ assign T_64 = T_60 & T_63;
+ assign T_65 = vb_array[7];
+ assign T_68 = cam_tags_T_67_data == io_tag;
+ assign T_69 = T_65 & T_68;
+ assign T_71_0 = T_34;
+ assign T_71_1 = T_39;
+ assign T_71_2 = T_44;
+ assign T_71_3 = T_49;
+ assign T_71_4 = T_54;
+ assign T_71_5 = T_59;
+ assign T_71_6 = T_64;
+ assign T_71_7 = T_69;
+ assign T_81 = {T_71_7,T_71_6};
+ assign T_82 = {T_71_5,T_71_4};
+ assign T_83 = {T_81,T_82};
+ assign T_84 = {T_71_3,T_71_2};
+ assign T_85 = {T_71_1,T_71_0};
+ assign T_86 = {T_84,T_85};
+ assign T_87 = {T_83,T_86};
+ assign T_89 = io_hits != 1'h0;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ for (initvar = 0; initvar < 8; initvar = initvar+1)
+ cam_tags[initvar] = {2{$random}};
+ vb_array = {1{$random}};
+ end
+`endif
+ always @(posedge cam_tags_T_27_clk) begin
+ if(cam_tags_T_27_en & cam_tags_T_27_mask) begin
+ cam_tags[cam_tags_T_27_addr] <= cam_tags_T_27_data;
+ end
+ end
+ always @(posedge clk) begin
+ if(reset) begin
+ vb_array <= 8'h0;
+ end else begin
+ if(io_clear) begin
+ vb_array <= T_29;
+ end else begin
+ if(io_write) begin
+ vb_array <= T_26;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+endmodule
+module TLB(
+ input clk,
+ input reset,
+ output io_req_ready,
+ input io_req_valid,
+ input [6:0] io_req_bits_asid,
+ input [27:0] io_req_bits_vpn,
+ input io_req_bits_passthrough,
+ input io_req_bits_instruction,
+ input io_req_bits_store,
+ output io_resp_miss,
+ output [19:0] io_resp_ppn,
+ output io_resp_xcpt_ld,
+ output io_resp_xcpt_st,
+ output io_resp_xcpt_if,
+ output [7:0] io_resp_hit_idx,
+ input io_ptw_req_ready,
+ output io_ptw_req_valid,
+ output [26:0] io_ptw_req_bits_addr,
+ output [1:0] io_ptw_req_bits_prv,
+ output io_ptw_req_bits_store,
+ output io_ptw_req_bits_fetch,
+ input io_ptw_resp_valid,
+ input io_ptw_resp_bits_error,
+ input [19:0] io_ptw_resp_bits_pte_ppn,
+ input [2:0] io_ptw_resp_bits_pte_reserved_for_software,
+ input io_ptw_resp_bits_pte_d,
+ input io_ptw_resp_bits_pte_r,
+ input [3:0] io_ptw_resp_bits_pte_typ,
+ input io_ptw_resp_bits_pte_v,
+ input io_ptw_status_sd,
+ input [30:0] io_ptw_status_zero2,
+ input io_ptw_status_sd_rv32,
+ input [8:0] io_ptw_status_zero1,
+ input [4:0] io_ptw_status_vm,
+ input io_ptw_status_mprv,
+ input [1:0] io_ptw_status_xs,
+ input [1:0] io_ptw_status_fs,
+ input [1:0] io_ptw_status_prv3,
+ input io_ptw_status_ie3,
+ input [1:0] io_ptw_status_prv2,
+ input io_ptw_status_ie2,
+ input [1:0] io_ptw_status_prv1,
+ input io_ptw_status_ie1,
+ input [1:0] io_ptw_status_prv,
+ input io_ptw_status_ie,
+ input io_ptw_invalidate
+);
+ reg [1:0] state;
+ reg [34:0] r_refill_tag;
+ reg [2:0] r_refill_waddr;
+ reg [6:0] r_req_asid;
+ reg [27:0] r_req_vpn;
+ reg r_req_passthrough;
+ reg r_req_instruction;
+ reg r_req_store;
+ wire tag_cam_clk;
+ wire tag_cam_reset;
+ wire tag_cam_io_clear;
+ wire [7:0] tag_cam_io_clear_mask;
+ wire [33:0] tag_cam_io_tag;
+ wire tag_cam_io_hit;
+ wire [7:0] tag_cam_io_hits;
+ wire [7:0] tag_cam_io_valid_bits;
+ wire tag_cam_io_write;
+ wire [33:0] tag_cam_io_write_tag;
+ wire [2:0] tag_cam_io_write_addr;
+ reg [19:0] tag_ram [0:7];
+ wire [19:0] tag_ram_T_859_data;
+ wire [2:0] tag_ram_T_859_addr;
+ wire tag_ram_T_859_en;
+ wire tag_ram_T_859_clk;
+ wire [19:0] tag_ram_T_861_data;
+ wire [2:0] tag_ram_T_861_addr;
+ wire tag_ram_T_861_en;
+ wire tag_ram_T_861_clk;
+ wire [19:0] tag_ram_T_863_data;
+ wire [2:0] tag_ram_T_863_addr;
+ wire tag_ram_T_863_en;
+ wire tag_ram_T_863_clk;
+ wire [19:0] tag_ram_T_865_data;
+ wire [2:0] tag_ram_T_865_addr;
+ wire tag_ram_T_865_en;
+ wire tag_ram_T_865_clk;
+ wire [19:0] tag_ram_T_867_data;
+ wire [2:0] tag_ram_T_867_addr;
+ wire tag_ram_T_867_en;
+ wire tag_ram_T_867_clk;
+ wire [19:0] tag_ram_T_869_data;
+ wire [2:0] tag_ram_T_869_addr;
+ wire tag_ram_T_869_en;
+ wire tag_ram_T_869_clk;
+ wire [19:0] tag_ram_T_871_data;
+ wire [2:0] tag_ram_T_871_addr;
+ wire tag_ram_T_871_en;
+ wire tag_ram_T_871_clk;
+ wire [19:0] tag_ram_T_873_data;
+ wire [2:0] tag_ram_T_873_addr;
+ wire tag_ram_T_873_en;
+ wire tag_ram_T_873_clk;
+ wire [19:0] tag_ram_T_383_data;
+ wire [2:0] tag_ram_T_383_addr;
+ wire tag_ram_T_383_mask;
+ wire tag_ram_T_383_en;
+ wire tag_ram_T_383_clk;
+ wire [34:0] lookup_tag;
+ wire T_176;
+ wire T_177;
+ wire [3:0] T_178;
+ wire [3:0] T_179;
+ wire T_181;
+ wire [3:0] T_182;
+ wire [1:0] T_183;
+ wire [1:0] T_184;
+ wire T_186;
+ wire [1:0] T_187;
+ wire T_188;
+ wire [1:0] T_189;
+ wire [2:0] tag_hit_addr;
+ reg valid_array_0;
+ reg valid_array_1;
+ reg valid_array_2;
+ reg valid_array_3;
+ reg valid_array_4;
+ reg valid_array_5;
+ reg valid_array_6;
+ reg valid_array_7;
+ reg ur_array_0;
+ reg ur_array_1;
+ reg ur_array_2;
+ reg ur_array_3;
+ reg ur_array_4;
+ reg ur_array_5;
+ reg ur_array_6;
+ reg ur_array_7;
+ reg uw_array_0;
+ reg uw_array_1;
+ reg uw_array_2;
+ reg uw_array_3;
+ reg uw_array_4;
+ reg uw_array_5;
+ reg uw_array_6;
+ reg uw_array_7;
+ reg ux_array_0;
+ reg ux_array_1;
+ reg ux_array_2;
+ reg ux_array_3;
+ reg ux_array_4;
+ reg ux_array_5;
+ reg ux_array_6;
+ reg ux_array_7;
+ reg sr_array_0;
+ reg sr_array_1;
+ reg sr_array_2;
+ reg sr_array_3;
+ reg sr_array_4;
+ reg sr_array_5;
+ reg sr_array_6;
+ reg sr_array_7;
+ reg sw_array_0;
+ reg sw_array_1;
+ reg sw_array_2;
+ reg sw_array_3;
+ reg sw_array_4;
+ reg sw_array_5;
+ reg sw_array_6;
+ reg sw_array_7;
+ reg sx_array_0;
+ reg sx_array_1;
+ reg sx_array_2;
+ reg sx_array_3;
+ reg sx_array_4;
+ reg sx_array_5;
+ reg sx_array_6;
+ reg sx_array_7;
+ reg dirty_array_0;
+ reg dirty_array_1;
+ reg dirty_array_2;
+ reg dirty_array_3;
+ reg dirty_array_4;
+ reg dirty_array_5;
+ reg dirty_array_6;
+ reg dirty_array_7;
+ wire T_386;
+ wire GEN_0;
+ wire T_389;
+ wire T_390;
+ wire T_392;
+ wire T_393;
+ wire T_395;
+ wire T_396;
+ wire GEN_1;
+ wire T_399;
+ wire T_400;
+ wire T_402;
+ wire T_403;
+ wire T_404;
+ wire T_405;
+ wire T_407;
+ wire T_408;
+ wire GEN_2;
+ wire T_411;
+ wire T_412;
+ wire T_414;
+ wire T_415;
+ wire T_416;
+ wire T_417;
+ wire T_419;
+ wire T_420;
+ wire GEN_3;
+ wire T_423;
+ wire T_424;
+ wire T_426;
+ wire T_427;
+ wire GEN_4;
+ wire T_430;
+ wire T_431;
+ wire T_432;
+ wire T_433;
+ wire T_435;
+ wire T_436;
+ wire GEN_5;
+ wire T_439;
+ wire T_440;
+ wire T_441;
+ wire T_442;
+ wire T_444;
+ wire T_445;
+ wire GEN_6;
+ wire GEN_7;
+ wire [7:0] T_447;
+ wire T_449;
+ wire has_invalid_entry;
+ wire [7:0] T_452;
+ wire T_453;
+ wire T_454;
+ wire T_455;
+ wire T_456;
+ wire T_457;
+ wire T_458;
+ wire T_459;
+ wire T_460;
+ wire T_462_0;
+ wire T_462_1;
+ wire T_462_2;
+ wire T_462_3;
+ wire T_462_4;
+ wire T_462_5;
+ wire T_462_6;
+ wire T_462_7;
+ wire [2:0] T_480;
+ wire [2:0] T_481;
+ wire [2:0] T_482;
+ wire [2:0] T_483;
+ wire [2:0] T_484;
+ wire [2:0] T_485;
+ wire [2:0] invalid_entry;
+ reg [7:0] T_488;
+ wire [7:0] T_490;
+ wire T_491;
+ wire [1:0] T_492;
+ wire [7:0] T_493;
+ wire T_494;
+ wire [2:0] T_495;
+ wire [7:0] T_496;
+ wire T_497;
+ wire [3:0] T_498;
+ wire [2:0] T_499;
+ wire [2:0] repl_waddr;
+ wire T_502;
+ wire T_503;
+ wire [1:0] priv;
+ wire priv_s;
+ wire priv_uses_vm;
+ wire T_510;
+ wire T_511;
+ wire T_513;
+ wire [1:0] T_514;
+ wire [2:0] req_xwr;
+ wire [1:0] T_516;
+ wire [1:0] T_517;
+ wire [3:0] T_518;
+ wire [1:0] T_519;
+ wire [1:0] T_520;
+ wire [3:0] T_521;
+ wire [7:0] T_522;
+ wire [1:0] T_523;
+ wire [1:0] T_524;
+ wire [3:0] T_525;
+ wire [1:0] T_526;
+ wire [1:0] T_527;
+ wire [3:0] T_528;
+ wire [7:0] T_529;
+ wire [7:0] r_array;
+ wire [1:0] T_531;
+ wire [1:0] T_532;
+ wire [3:0] T_533;
+ wire [1:0] T_534;
+ wire [1:0] T_535;
+ wire [3:0] T_536;
+ wire [7:0] T_537;
+ wire [1:0] T_538;
+ wire [1:0] T_539;
+ wire [3:0] T_540;
+ wire [1:0] T_541;
+ wire [1:0] T_542;
+ wire [3:0] T_543;
+ wire [7:0] T_544;
+ wire [7:0] w_array;
+ wire [1:0] T_546;
+ wire [1:0] T_547;
+ wire [3:0] T_548;
+ wire [1:0] T_549;
+ wire [1:0] T_550;
+ wire [3:0] T_551;
+ wire [7:0] T_552;
+ wire [1:0] T_553;
+ wire [1:0] T_554;
+ wire [3:0] T_555;
+ wire [1:0] T_556;
+ wire [1:0] T_557;
+ wire [3:0] T_558;
+ wire [7:0] T_559;
+ wire [7:0] x_array;
+ wire T_561;
+ wire T_562;
+ wire T_564;
+ wire vm_enabled;
+ wire T_566;
+ wire T_567;
+ wire bad_va;
+ wire [1:0] T_569;
+ wire [1:0] T_570;
+ wire [3:0] T_571;
+ wire [1:0] T_572;
+ wire [1:0] T_573;
+ wire [3:0] T_574;
+ wire [7:0] T_575;
+ wire [7:0] T_577;
+ wire [7:0] T_578;
+ wire [7:0] T_579;
+ wire [7:0] tag_hits;
+ wire tag_hit;
+ wire tlb_hit;
+ wire T_585;
+ wire T_586;
+ wire T_588;
+ wire tlb_miss;
+ wire T_590;
+ wire [3:0] T_591;
+ wire [3:0] T_592;
+ wire T_594;
+ wire [3:0] T_595;
+ wire [1:0] T_596;
+ wire [1:0] T_597;
+ wire T_599;
+ wire [1:0] T_600;
+ wire T_601;
+ wire [1:0] T_602;
+ wire [2:0] T_603;
+ wire T_605;
+ wire [8:0] T_607;
+ wire [7:0] T_608;
+ wire [7:0] T_609;
+ wire [7:0] T_610;
+ wire [7:0] T_612;
+ wire [7:0] T_613;
+ wire [1:0] T_614;
+ wire T_615;
+ wire [10:0] T_617;
+ wire [7:0] T_618;
+ wire [7:0] T_619;
+ wire [7:0] T_620;
+ wire [7:0] T_622;
+ wire [7:0] T_623;
+ wire [2:0] T_624;
+ wire T_625;
+ wire [14:0] T_627;
+ wire [7:0] T_628;
+ wire [7:0] T_629;
+ wire [7:0] T_630;
+ wire [7:0] T_632;
+ wire [7:0] T_633;
+ wire [3:0] T_634;
+ wire [31:0] paddr;
+ wire T_638;
+ wire T_640;
+ wire T_641;
+ wire T_643;
+ wire T_645;
+ wire T_646;
+ wire T_648;
+ wire T_650;
+ wire T_651;
+ wire T_653;
+ wire T_655;
+ wire T_656;
+ wire T_658;
+ wire T_660;
+ wire T_661;
+ wire T_662;
+ wire T_663;
+ wire T_664;
+ wire addr_ok;
+ wire T_667;
+ wire T_669;
+ wire T_670;
+ wire T_680_x;
+ wire T_680_w;
+ wire T_680_r;
+ wire T_688;
+ wire T_690;
+ wire T_691;
+ wire T_701_x;
+ wire T_701_w;
+ wire T_701_r;
+ wire T_709;
+ wire T_711;
+ wire T_712;
+ wire T_722_x;
+ wire T_722_w;
+ wire T_722_r;
+ wire T_730;
+ wire T_732;
+ wire T_733;
+ wire T_743_x;
+ wire T_743_w;
+ wire T_743_r;
+ wire T_751;
+ wire T_753;
+ wire T_754;
+ wire T_764_x;
+ wire T_764_w;
+ wire T_764_r;
+ wire [1:0] T_771;
+ wire [2:0] T_772;
+ wire [2:0] T_774;
+ wire [1:0] T_775;
+ wire [2:0] T_776;
+ wire [2:0] T_778;
+ wire [1:0] T_779;
+ wire [2:0] T_780;
+ wire [2:0] T_782;
+ wire [1:0] T_783;
+ wire [2:0] T_784;
+ wire [2:0] T_786;
+ wire [1:0] T_787;
+ wire [2:0] T_788;
+ wire [2:0] T_790;
+ wire [2:0] T_795;
+ wire [2:0] T_796;
+ wire [2:0] T_797;
+ wire [2:0] T_798;
+ wire addr_prot_x;
+ wire addr_prot_w;
+ wire addr_prot_r;
+ wire T_807;
+ wire T_808;
+ wire T_809;
+ wire T_810;
+ wire T_812;
+ wire T_814;
+ wire T_815;
+ wire T_816;
+ wire [7:0] T_817;
+ wire T_819;
+ wire T_821;
+ wire T_822;
+ wire T_823;
+ wire T_825;
+ wire T_827;
+ wire T_828;
+ wire T_829;
+ wire [7:0] T_830;
+ wire T_832;
+ wire T_834;
+ wire T_835;
+ wire T_836;
+ wire T_838;
+ wire T_840;
+ wire T_841;
+ wire T_842;
+ wire [7:0] T_843;
+ wire T_845;
+ wire T_847;
+ wire T_848;
+ wire T_849;
+ wire T_850;
+ wire T_851;
+ wire T_852;
+ wire T_853;
+ wire T_854;
+ wire T_855;
+ wire T_856;
+ wire T_857;
+ wire [19:0] T_875;
+ wire [19:0] T_877;
+ wire [19:0] T_879;
+ wire [19:0] T_881;
+ wire [19:0] T_883;
+ wire [19:0] T_885;
+ wire [19:0] T_887;
+ wire [19:0] T_889;
+ wire [19:0] T_891;
+ wire [19:0] T_892;
+ wire [19:0] T_893;
+ wire [19:0] T_894;
+ wire [19:0] T_895;
+ wire [19:0] T_896;
+ wire [19:0] T_897;
+ wire [19:0] T_898;
+ wire [19:0] T_899;
+ wire [19:0] T_900;
+ wire T_901;
+ wire T_902;
+ wire [1:0] T_903;
+ wire [1:0] T_904;
+ wire [3:0] T_905;
+ wire [1:0] T_906;
+ wire [1:0] T_907;
+ wire [3:0] T_908;
+ wire [7:0] T_909;
+ wire [7:0] T_910;
+ wire [7:0] T_911;
+ wire [7:0] T_912;
+ wire [7:0] T_913;
+ wire [7:0] T_915;
+ wire T_916;
+ wire T_917;
+ wire T_918;
+ wire T_919;
+ wire T_920;
+ wire T_921;
+ wire GEN_8;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ wire GEN_17;
+ wire GEN_18;
+ wire GEN_19;
+ wire GEN_20;
+ wire GEN_21;
+ wire GEN_22;
+ wire GEN_23;
+ wire GEN_24;
+ wire GEN_25;
+ wire GEN_26;
+ wire GEN_27;
+ wire GEN_28;
+ wire GEN_29;
+ wire GEN_30;
+ wire GEN_31;
+ wire GEN_32;
+ wire GEN_33;
+ wire GEN_34;
+ wire GEN_35;
+ wire GEN_36;
+ wire GEN_37;
+ wire GEN_38;
+ wire GEN_39;
+ wire GEN_40;
+ wire GEN_41;
+ wire GEN_42;
+ wire GEN_43;
+ wire GEN_44;
+ wire GEN_45;
+ wire GEN_46;
+ wire GEN_47;
+ wire GEN_48;
+ wire GEN_49;
+ wire GEN_50;
+ wire GEN_51;
+ wire GEN_52;
+ wire GEN_53;
+ wire GEN_54;
+ wire GEN_55;
+ wire GEN_56;
+ wire GEN_57;
+ wire GEN_58;
+ wire GEN_59;
+ wire GEN_60;
+ wire GEN_61;
+ wire GEN_62;
+ wire GEN_63;
+ wire GEN_64;
+ wire GEN_65;
+ wire GEN_66;
+ wire GEN_67;
+ wire GEN_68;
+ wire GEN_69;
+ wire GEN_70;
+ wire GEN_71;
+ RocketCAM tag_cam (
+ .clk(tag_cam_clk),
+ .reset(tag_cam_reset),
+ .io_clear(tag_cam_io_clear),
+ .io_clear_mask(tag_cam_io_clear_mask),
+ .io_tag(tag_cam_io_tag),
+ .io_hit(tag_cam_io_hit),
+ .io_hits(tag_cam_io_hits),
+ .io_valid_bits(tag_cam_io_valid_bits),
+ .io_write(tag_cam_io_write),
+ .io_write_tag(tag_cam_io_write_tag),
+ .io_write_addr(tag_cam_io_write_addr)
+ );
+ assign io_req_ready = T_810;
+ assign io_resp_miss = tlb_miss;
+ assign io_resp_ppn = T_900;
+ assign io_resp_xcpt_ld = T_823;
+ assign io_resp_xcpt_st = T_836;
+ assign io_resp_xcpt_if = T_849;
+ assign io_resp_hit_idx = tag_cam_io_hits;
+ assign io_ptw_req_valid = T_916;
+ assign io_ptw_req_bits_addr = r_refill_tag;
+ assign io_ptw_req_bits_prv = io_ptw_status_prv;
+ assign io_ptw_req_bits_store = r_req_store;
+ assign io_ptw_req_bits_fetch = r_req_instruction;
+ assign tag_cam_clk = clk;
+ assign tag_cam_reset = reset;
+ assign tag_cam_io_clear = T_902;
+ assign tag_cam_io_clear_mask = io_ptw_invalidate ? T_915 : T_913;
+ assign tag_cam_io_tag = lookup_tag;
+ assign tag_cam_io_write = T_177;
+ assign tag_cam_io_write_tag = r_refill_tag;
+ assign tag_cam_io_write_addr = r_refill_waddr;
+ assign tag_ram_T_859_addr = 1'h0;
+ assign tag_ram_T_859_en = 1'h1;
+ assign tag_ram_T_859_clk = clk;
+ assign tag_ram_T_859_data = tag_ram[tag_ram_T_859_addr];
+ assign tag_ram_T_861_addr = 1'h1;
+ assign tag_ram_T_861_en = 1'h1;
+ assign tag_ram_T_861_clk = clk;
+ assign tag_ram_T_861_data = tag_ram[tag_ram_T_861_addr];
+ assign tag_ram_T_863_addr = 2'h2;
+ assign tag_ram_T_863_en = 1'h1;
+ assign tag_ram_T_863_clk = clk;
+ assign tag_ram_T_863_data = tag_ram[tag_ram_T_863_addr];
+ assign tag_ram_T_865_addr = 2'h3;
+ assign tag_ram_T_865_en = 1'h1;
+ assign tag_ram_T_865_clk = clk;
+ assign tag_ram_T_865_data = tag_ram[tag_ram_T_865_addr];
+ assign tag_ram_T_867_addr = 3'h4;
+ assign tag_ram_T_867_en = 1'h1;
+ assign tag_ram_T_867_clk = clk;
+ assign tag_ram_T_867_data = tag_ram[tag_ram_T_867_addr];
+ assign tag_ram_T_869_addr = 3'h5;
+ assign tag_ram_T_869_en = 1'h1;
+ assign tag_ram_T_869_clk = clk;
+ assign tag_ram_T_869_data = tag_ram[tag_ram_T_869_addr];
+ assign tag_ram_T_871_addr = 3'h6;
+ assign tag_ram_T_871_en = 1'h1;
+ assign tag_ram_T_871_clk = clk;
+ assign tag_ram_T_871_data = tag_ram[tag_ram_T_871_addr];
+ assign tag_ram_T_873_addr = 3'h7;
+ assign tag_ram_T_873_en = 1'h1;
+ assign tag_ram_T_873_clk = clk;
+ assign tag_ram_T_873_data = tag_ram[tag_ram_T_873_addr];
+ assign tag_ram_T_383_data = io_ptw_resp_bits_pte_ppn;
+ assign tag_ram_T_383_addr = r_refill_waddr;
+ assign tag_ram_T_383_mask = io_ptw_resp_valid ? 1'h1 : 1'h0;
+ assign tag_ram_T_383_en = io_ptw_resp_valid ? 1'h1 : 1'h0;
+ assign tag_ram_T_383_clk = clk;
+ assign lookup_tag = {io_req_bits_asid,io_req_bits_vpn};
+ assign T_176 = state == 2'h2;
+ assign T_177 = T_176 & io_ptw_resp_valid;
+ assign T_178 = tag_cam_io_hits[7:4];
+ assign T_179 = tag_cam_io_hits[3:0];
+ assign T_181 = T_178 != 1'h0;
+ assign T_182 = T_178 | T_179;
+ assign T_183 = T_182[3:2];
+ assign T_184 = T_182[1:0];
+ assign T_186 = T_183 != 1'h0;
+ assign T_187 = T_183 | T_184;
+ assign T_188 = T_187[1];
+ assign T_189 = {T_186,T_188};
+ assign tag_hit_addr = {T_181,T_189};
+ assign T_386 = io_ptw_resp_bits_error == 1'h0;
+ assign GEN_0 = T_386;
+ assign T_389 = io_ptw_resp_bits_pte_typ >= 2'h2;
+ assign T_390 = io_ptw_resp_bits_pte_v & T_389;
+ assign T_392 = io_ptw_resp_bits_pte_typ < 4'h8;
+ assign T_393 = T_390 & T_392;
+ assign T_395 = io_ptw_resp_bits_error == 1'h0;
+ assign T_396 = T_393 & T_395;
+ assign GEN_1 = T_396;
+ assign T_399 = io_ptw_resp_bits_pte_typ >= 2'h2;
+ assign T_400 = io_ptw_resp_bits_pte_v & T_399;
+ assign T_402 = io_ptw_resp_bits_pte_typ < 4'h8;
+ assign T_403 = T_400 & T_402;
+ assign T_404 = io_ptw_resp_bits_pte_typ[0];
+ assign T_405 = T_403 & T_404;
+ assign T_407 = io_ptw_resp_bits_error == 1'h0;
+ assign T_408 = T_405 & T_407;
+ assign GEN_2 = T_408;
+ assign T_411 = io_ptw_resp_bits_pte_typ >= 2'h2;
+ assign T_412 = io_ptw_resp_bits_pte_v & T_411;
+ assign T_414 = io_ptw_resp_bits_pte_typ < 4'h8;
+ assign T_415 = T_412 & T_414;
+ assign T_416 = io_ptw_resp_bits_pte_typ[1];
+ assign T_417 = T_415 & T_416;
+ assign T_419 = io_ptw_resp_bits_error == 1'h0;
+ assign T_420 = T_417 & T_419;
+ assign GEN_3 = T_420;
+ assign T_423 = io_ptw_resp_bits_pte_typ >= 2'h2;
+ assign T_424 = io_ptw_resp_bits_pte_v & T_423;
+ assign T_426 = io_ptw_resp_bits_error == 1'h0;
+ assign T_427 = T_424 & T_426;
+ assign GEN_4 = T_427;
+ assign T_430 = io_ptw_resp_bits_pte_typ >= 2'h2;
+ assign T_431 = io_ptw_resp_bits_pte_v & T_430;
+ assign T_432 = io_ptw_resp_bits_pte_typ[0];
+ assign T_433 = T_431 & T_432;
+ assign T_435 = io_ptw_resp_bits_error == 1'h0;
+ assign T_436 = T_433 & T_435;
+ assign GEN_5 = T_436;
+ assign T_439 = io_ptw_resp_bits_pte_typ >= 3'h4;
+ assign T_440 = io_ptw_resp_bits_pte_v & T_439;
+ assign T_441 = io_ptw_resp_bits_pte_typ[1];
+ assign T_442 = T_440 & T_441;
+ assign T_444 = io_ptw_resp_bits_error == 1'h0;
+ assign T_445 = T_442 & T_444;
+ assign GEN_6 = T_445;
+ assign GEN_7 = io_ptw_resp_bits_pte_d;
+ assign T_447 = ~ tag_cam_io_valid_bits;
+ assign T_449 = T_447 == 1'h0;
+ assign has_invalid_entry = T_449 == 1'h0;
+ assign T_452 = ~ tag_cam_io_valid_bits;
+ assign T_453 = T_452[0];
+ assign T_454 = T_452[1];
+ assign T_455 = T_452[2];
+ assign T_456 = T_452[3];
+ assign T_457 = T_452[4];
+ assign T_458 = T_452[5];
+ assign T_459 = T_452[6];
+ assign T_460 = T_452[7];
+ assign T_462_0 = T_453;
+ assign T_462_1 = T_454;
+ assign T_462_2 = T_455;
+ assign T_462_3 = T_456;
+ assign T_462_4 = T_457;
+ assign T_462_5 = T_458;
+ assign T_462_6 = T_459;
+ assign T_462_7 = T_460;
+ assign T_480 = T_462_6 ? 3'h6 : 3'h7;
+ assign T_481 = T_462_5 ? 3'h5 : T_480;
+ assign T_482 = T_462_4 ? 3'h4 : T_481;
+ assign T_483 = T_462_3 ? 2'h3 : T_482;
+ assign T_484 = T_462_2 ? 2'h2 : T_483;
+ assign T_485 = T_462_1 ? 1'h1 : T_484;
+ assign invalid_entry = T_462_0 ? 1'h0 : T_485;
+ assign T_490 = T_488 >> 1'h1;
+ assign T_491 = T_490[0];
+ assign T_492 = {1'h1,T_491};
+ assign T_493 = T_488 >> T_492;
+ assign T_494 = T_493[0];
+ assign T_495 = {T_492,T_494};
+ assign T_496 = T_488 >> T_495;
+ assign T_497 = T_496[0];
+ assign T_498 = {T_495,T_497};
+ assign T_499 = T_498[2:0];
+ assign repl_waddr = has_invalid_entry ? invalid_entry : T_499;
+ assign T_502 = io_req_bits_instruction == 1'h0;
+ assign T_503 = io_ptw_status_mprv & T_502;
+ assign priv = T_503 ? io_ptw_status_prv1 : io_ptw_status_prv;
+ assign priv_s = priv == 1'h1;
+ assign priv_uses_vm = priv <= 1'h1;
+ assign T_510 = r_req_store == 1'h0;
+ assign T_511 = r_req_instruction | r_req_store;
+ assign T_513 = T_511 == 1'h0;
+ assign T_514 = {r_req_store,T_513};
+ assign req_xwr = {T_510,T_514};
+ assign T_516 = {sr_array_7,sr_array_6};
+ assign T_517 = {sr_array_5,sr_array_4};
+ assign T_518 = {T_516,T_517};
+ assign T_519 = {sr_array_3,sr_array_2};
+ assign T_520 = {sr_array_1,sr_array_0};
+ assign T_521 = {T_519,T_520};
+ assign T_522 = {T_518,T_521};
+ assign T_523 = {ur_array_7,ur_array_6};
+ assign T_524 = {ur_array_5,ur_array_4};
+ assign T_525 = {T_523,T_524};
+ assign T_526 = {ur_array_3,ur_array_2};
+ assign T_527 = {ur_array_1,ur_array_0};
+ assign T_528 = {T_526,T_527};
+ assign T_529 = {T_525,T_528};
+ assign r_array = priv_s ? T_522 : T_529;
+ assign T_531 = {sw_array_7,sw_array_6};
+ assign T_532 = {sw_array_5,sw_array_4};
+ assign T_533 = {T_531,T_532};
+ assign T_534 = {sw_array_3,sw_array_2};
+ assign T_535 = {sw_array_1,sw_array_0};
+ assign T_536 = {T_534,T_535};
+ assign T_537 = {T_533,T_536};
+ assign T_538 = {uw_array_7,uw_array_6};
+ assign T_539 = {uw_array_5,uw_array_4};
+ assign T_540 = {T_538,T_539};
+ assign T_541 = {uw_array_3,uw_array_2};
+ assign T_542 = {uw_array_1,uw_array_0};
+ assign T_543 = {T_541,T_542};
+ assign T_544 = {T_540,T_543};
+ assign w_array = priv_s ? T_537 : T_544;
+ assign T_546 = {sx_array_7,sx_array_6};
+ assign T_547 = {sx_array_5,sx_array_4};
+ assign T_548 = {T_546,T_547};
+ assign T_549 = {sx_array_3,sx_array_2};
+ assign T_550 = {sx_array_1,sx_array_0};
+ assign T_551 = {T_549,T_550};
+ assign T_552 = {T_548,T_551};
+ assign T_553 = {ux_array_7,ux_array_6};
+ assign T_554 = {ux_array_5,ux_array_4};
+ assign T_555 = {T_553,T_554};
+ assign T_556 = {ux_array_3,ux_array_2};
+ assign T_557 = {ux_array_1,ux_array_0};
+ assign T_558 = {T_556,T_557};
+ assign T_559 = {T_555,T_558};
+ assign x_array = priv_s ? T_552 : T_559;
+ assign T_561 = io_ptw_status_vm[3];
+ assign T_562 = T_561 & priv_uses_vm;
+ assign T_564 = io_req_bits_passthrough == 1'h0;
+ assign vm_enabled = T_562 & T_564;
+ assign T_566 = io_req_bits_vpn[27];
+ assign T_567 = io_req_bits_vpn[26];
+ assign bad_va = T_566 != T_567;
+ assign T_569 = {dirty_array_7,dirty_array_6};
+ assign T_570 = {dirty_array_5,dirty_array_4};
+ assign T_571 = {T_569,T_570};
+ assign T_572 = {dirty_array_3,dirty_array_2};
+ assign T_573 = {dirty_array_1,dirty_array_0};
+ assign T_574 = {T_572,T_573};
+ assign T_575 = {T_571,T_574};
+ assign T_577 = io_req_bits_store ? w_array : 1'h0;
+ assign T_578 = ~ T_577;
+ assign T_579 = T_575 | T_578;
+ assign tag_hits = tag_cam_io_hits & T_579;
+ assign tag_hit = tag_hits != 1'h0;
+ assign tlb_hit = vm_enabled & tag_hit;
+ assign T_585 = tag_hit == 1'h0;
+ assign T_586 = vm_enabled & T_585;
+ assign T_588 = bad_va == 1'h0;
+ assign tlb_miss = T_586 & T_588;
+ assign T_590 = io_req_valid & tlb_hit;
+ assign T_591 = tag_cam_io_hits[7:4];
+ assign T_592 = tag_cam_io_hits[3:0];
+ assign T_594 = T_591 != 1'h0;
+ assign T_595 = T_591 | T_592;
+ assign T_596 = T_595[3:2];
+ assign T_597 = T_595[1:0];
+ assign T_599 = T_596 != 1'h0;
+ assign T_600 = T_596 | T_597;
+ assign T_601 = T_600[1];
+ assign T_602 = {T_599,T_601};
+ assign T_603 = {T_594,T_602};
+ assign T_605 = T_603[2];
+ assign T_607 = 8'h1 << 1'h1;
+ assign T_608 = T_607[7:0];
+ assign T_609 = ~ T_608;
+ assign T_610 = T_488 & T_609;
+ assign T_612 = T_605 ? 1'h0 : T_608;
+ assign T_613 = T_610 | T_612;
+ assign T_614 = {1'h1,T_605};
+ assign T_615 = T_603[1];
+ assign T_617 = 8'h1 << T_614;
+ assign T_618 = T_617[7:0];
+ assign T_619 = ~ T_618;
+ assign T_620 = T_613 & T_619;
+ assign T_622 = T_615 ? 1'h0 : T_618;
+ assign T_623 = T_620 | T_622;
+ assign T_624 = {T_614,T_615};
+ assign T_625 = T_603[0];
+ assign T_627 = 8'h1 << T_624;
+ assign T_628 = T_627[7:0];
+ assign T_629 = ~ T_628;
+ assign T_630 = T_623 & T_629;
+ assign T_632 = T_625 ? 1'h0 : T_628;
+ assign T_633 = T_630 | T_632;
+ assign T_634 = {T_624,T_625};
+ assign paddr = {io_resp_ppn,12'h0};
+ assign T_638 = paddr >= 1'h0;
+ assign T_640 = paddr < 31'h40000000;
+ assign T_641 = T_638 & T_640;
+ assign T_643 = paddr >= 31'h40000000;
+ assign T_645 = paddr < 31'h40008000;
+ assign T_646 = T_643 & T_645;
+ assign T_648 = paddr >= 31'h40008000;
+ assign T_650 = paddr < 31'h40010000;
+ assign T_651 = T_648 & T_650;
+ assign T_653 = paddr >= 31'h40010000;
+ assign T_655 = paddr < 31'h40010200;
+ assign T_656 = T_653 & T_655;
+ assign T_658 = paddr >= 32'h80000000;
+ assign T_660 = paddr < 33'h100000000;
+ assign T_661 = T_658 & T_660;
+ assign T_662 = T_641 | T_646;
+ assign T_663 = T_662 | T_651;
+ assign T_664 = T_663 | T_656;
+ assign addr_ok = T_664 | T_661;
+ assign T_667 = paddr >= 1'h0;
+ assign T_669 = paddr < 31'h40000000;
+ assign T_670 = T_667 & T_669;
+ assign T_680_x = 1'h1;
+ assign T_680_w = 1'h1;
+ assign T_680_r = 1'h1;
+ assign T_688 = paddr >= 31'h40000000;
+ assign T_690 = paddr < 31'h40008000;
+ assign T_691 = T_688 & T_690;
+ assign T_701_x = 1'h0;
+ assign T_701_w = 1'h0;
+ assign T_701_r = 1'h1;
+ assign T_709 = paddr >= 31'h40008000;
+ assign T_711 = paddr < 31'h40010000;
+ assign T_712 = T_709 & T_711;
+ assign T_722_x = 1'h0;
+ assign T_722_w = 1'h1;
+ assign T_722_r = 1'h1;
+ assign T_730 = paddr >= 31'h40010000;
+ assign T_732 = paddr < 31'h40010200;
+ assign T_733 = T_730 & T_732;
+ assign T_743_x = 1'h0;
+ assign T_743_w = 1'h1;
+ assign T_743_r = 1'h1;
+ assign T_751 = paddr >= 32'h80000000;
+ assign T_753 = paddr < 33'h100000000;
+ assign T_754 = T_751 & T_753;
+ assign T_764_x = 1'h0;
+ assign T_764_w = 1'h1;
+ assign T_764_r = 1'h1;
+ assign T_771 = {T_680_w,T_680_r};
+ assign T_772 = {T_680_x,T_771};
+ assign T_774 = T_670 ? T_772 : 1'h0;
+ assign T_775 = {T_701_w,T_701_r};
+ assign T_776 = {T_701_x,T_775};
+ assign T_778 = T_691 ? T_776 : 1'h0;
+ assign T_779 = {T_722_w,T_722_r};
+ assign T_780 = {T_722_x,T_779};
+ assign T_782 = T_712 ? T_780 : 1'h0;
+ assign T_783 = {T_743_w,T_743_r};
+ assign T_784 = {T_743_x,T_783};
+ assign T_786 = T_733 ? T_784 : 1'h0;
+ assign T_787 = {T_764_w,T_764_r};
+ assign T_788 = {T_764_x,T_787};
+ assign T_790 = T_754 ? T_788 : 1'h0;
+ assign T_795 = T_774 | T_778;
+ assign T_796 = T_795 | T_782;
+ assign T_797 = T_796 | T_786;
+ assign T_798 = T_797 | T_790;
+ assign addr_prot_x = T_809;
+ assign addr_prot_w = T_808;
+ assign addr_prot_r = T_807;
+ assign T_807 = T_798[0];
+ assign T_808 = T_798[1];
+ assign T_809 = T_798[2];
+ assign T_810 = state == 1'h0;
+ assign T_812 = addr_ok == 1'h0;
+ assign T_814 = addr_prot_r == 1'h0;
+ assign T_815 = T_812 | T_814;
+ assign T_816 = T_815 | bad_va;
+ assign T_817 = r_array & tag_cam_io_hits;
+ assign T_819 = T_817 != 1'h0;
+ assign T_821 = T_819 == 1'h0;
+ assign T_822 = tlb_hit & T_821;
+ assign T_823 = T_816 | T_822;
+ assign T_825 = addr_ok == 1'h0;
+ assign T_827 = addr_prot_w == 1'h0;
+ assign T_828 = T_825 | T_827;
+ assign T_829 = T_828 | bad_va;
+ assign T_830 = w_array & tag_cam_io_hits;
+ assign T_832 = T_830 != 1'h0;
+ assign T_834 = T_832 == 1'h0;
+ assign T_835 = tlb_hit & T_834;
+ assign T_836 = T_829 | T_835;
+ assign T_838 = addr_ok == 1'h0;
+ assign T_840 = addr_prot_x == 1'h0;
+ assign T_841 = T_838 | T_840;
+ assign T_842 = T_841 | bad_va;
+ assign T_843 = x_array & tag_cam_io_hits;
+ assign T_845 = T_843 != 1'h0;
+ assign T_847 = T_845 == 1'h0;
+ assign T_848 = tlb_hit & T_847;
+ assign T_849 = T_842 | T_848;
+ assign T_850 = tag_cam_io_hits[0];
+ assign T_851 = tag_cam_io_hits[1];
+ assign T_852 = tag_cam_io_hits[2];
+ assign T_853 = tag_cam_io_hits[3];
+ assign T_854 = tag_cam_io_hits[4];
+ assign T_855 = tag_cam_io_hits[5];
+ assign T_856 = tag_cam_io_hits[6];
+ assign T_857 = tag_cam_io_hits[7];
+ assign T_875 = T_850 ? tag_ram_T_859_data : 1'h0;
+ assign T_877 = T_851 ? tag_ram_T_861_data : 1'h0;
+ assign T_879 = T_852 ? tag_ram_T_863_data : 1'h0;
+ assign T_881 = T_853 ? tag_ram_T_865_data : 1'h0;
+ assign T_883 = T_854 ? tag_ram_T_867_data : 1'h0;
+ assign T_885 = T_855 ? tag_ram_T_869_data : 1'h0;
+ assign T_887 = T_856 ? tag_ram_T_871_data : 1'h0;
+ assign T_889 = T_857 ? tag_ram_T_873_data : 1'h0;
+ assign T_891 = T_875 | T_877;
+ assign T_892 = T_891 | T_879;
+ assign T_893 = T_892 | T_881;
+ assign T_894 = T_893 | T_883;
+ assign T_895 = T_894 | T_885;
+ assign T_896 = T_895 | T_887;
+ assign T_897 = T_896 | T_889;
+ assign T_898 = T_897;
+ assign T_899 = io_req_bits_vpn[19:0];
+ assign T_900 = vm_enabled ? T_898 : T_899;
+ assign T_901 = io_req_ready & io_req_valid;
+ assign T_902 = io_ptw_invalidate | T_901;
+ assign T_903 = {valid_array_7,valid_array_6};
+ assign T_904 = {valid_array_5,valid_array_4};
+ assign T_905 = {T_903,T_904};
+ assign T_906 = {valid_array_3,valid_array_2};
+ assign T_907 = {valid_array_1,valid_array_0};
+ assign T_908 = {T_906,T_907};
+ assign T_909 = {T_905,T_908};
+ assign T_910 = ~ T_909;
+ assign T_911 = ~ tag_hits;
+ assign T_912 = tag_cam_io_hits & T_911;
+ assign T_913 = T_910 | T_912;
+ assign T_915 = ~ 8'h0;
+ assign T_916 = state == 1'h1;
+ assign T_917 = io_req_ready & io_req_valid;
+ assign T_918 = T_917 & tlb_miss;
+ assign T_919 = state == 1'h1;
+ assign T_920 = state == 2'h2;
+ assign T_921 = T_920 & io_ptw_invalidate;
+ assign GEN_8 = 1'h0 == r_refill_waddr;
+ assign GEN_9 = 1'h1 == r_refill_waddr;
+ assign GEN_10 = 2'h2 == r_refill_waddr;
+ assign GEN_11 = 2'h3 == r_refill_waddr;
+ assign GEN_12 = 3'h4 == r_refill_waddr;
+ assign GEN_13 = 3'h5 == r_refill_waddr;
+ assign GEN_14 = 3'h6 == r_refill_waddr;
+ assign GEN_15 = 3'h7 == r_refill_waddr;
+ assign GEN_16 = 1'h0 == r_refill_waddr;
+ assign GEN_17 = 1'h1 == r_refill_waddr;
+ assign GEN_18 = 2'h2 == r_refill_waddr;
+ assign GEN_19 = 2'h3 == r_refill_waddr;
+ assign GEN_20 = 3'h4 == r_refill_waddr;
+ assign GEN_21 = 3'h5 == r_refill_waddr;
+ assign GEN_22 = 3'h6 == r_refill_waddr;
+ assign GEN_23 = 3'h7 == r_refill_waddr;
+ assign GEN_24 = 1'h0 == r_refill_waddr;
+ assign GEN_25 = 1'h1 == r_refill_waddr;
+ assign GEN_26 = 2'h2 == r_refill_waddr;
+ assign GEN_27 = 2'h3 == r_refill_waddr;
+ assign GEN_28 = 3'h4 == r_refill_waddr;
+ assign GEN_29 = 3'h5 == r_refill_waddr;
+ assign GEN_30 = 3'h6 == r_refill_waddr;
+ assign GEN_31 = 3'h7 == r_refill_waddr;
+ assign GEN_32 = 1'h0 == r_refill_waddr;
+ assign GEN_33 = 1'h1 == r_refill_waddr;
+ assign GEN_34 = 2'h2 == r_refill_waddr;
+ assign GEN_35 = 2'h3 == r_refill_waddr;
+ assign GEN_36 = 3'h4 == r_refill_waddr;
+ assign GEN_37 = 3'h5 == r_refill_waddr;
+ assign GEN_38 = 3'h6 == r_refill_waddr;
+ assign GEN_39 = 3'h7 == r_refill_waddr;
+ assign GEN_40 = 1'h0 == r_refill_waddr;
+ assign GEN_41 = 1'h1 == r_refill_waddr;
+ assign GEN_42 = 2'h2 == r_refill_waddr;
+ assign GEN_43 = 2'h3 == r_refill_waddr;
+ assign GEN_44 = 3'h4 == r_refill_waddr;
+ assign GEN_45 = 3'h5 == r_refill_waddr;
+ assign GEN_46 = 3'h6 == r_refill_waddr;
+ assign GEN_47 = 3'h7 == r_refill_waddr;
+ assign GEN_48 = 1'h0 == r_refill_waddr;
+ assign GEN_49 = 1'h1 == r_refill_waddr;
+ assign GEN_50 = 2'h2 == r_refill_waddr;
+ assign GEN_51 = 2'h3 == r_refill_waddr;
+ assign GEN_52 = 3'h4 == r_refill_waddr;
+ assign GEN_53 = 3'h5 == r_refill_waddr;
+ assign GEN_54 = 3'h6 == r_refill_waddr;
+ assign GEN_55 = 3'h7 == r_refill_waddr;
+ assign GEN_56 = 1'h0 == r_refill_waddr;
+ assign GEN_57 = 1'h1 == r_refill_waddr;
+ assign GEN_58 = 2'h2 == r_refill_waddr;
+ assign GEN_59 = 2'h3 == r_refill_waddr;
+ assign GEN_60 = 3'h4 == r_refill_waddr;
+ assign GEN_61 = 3'h5 == r_refill_waddr;
+ assign GEN_62 = 3'h6 == r_refill_waddr;
+ assign GEN_63 = 3'h7 == r_refill_waddr;
+ assign GEN_64 = 1'h0 == r_refill_waddr;
+ assign GEN_65 = 1'h1 == r_refill_waddr;
+ assign GEN_66 = 2'h2 == r_refill_waddr;
+ assign GEN_67 = 2'h3 == r_refill_waddr;
+ assign GEN_68 = 3'h4 == r_refill_waddr;
+ assign GEN_69 = 3'h5 == r_refill_waddr;
+ assign GEN_70 = 3'h6 == r_refill_waddr;
+ assign GEN_71 = 3'h7 == r_refill_waddr;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ state = {1{$random}};
+ r_refill_tag = {2{$random}};
+ r_refill_waddr = {1{$random}};
+ r_req_asid = {1{$random}};
+ r_req_vpn = {1{$random}};
+ r_req_passthrough = {1{$random}};
+ r_req_instruction = {1{$random}};
+ r_req_store = {1{$random}};
+ for (initvar = 0; initvar < 8; initvar = initvar+1)
+ tag_ram[initvar] = {1{$random}};
+ valid_array_0 = {1{$random}};
+ valid_array_1 = {1{$random}};
+ valid_array_2 = {1{$random}};
+ valid_array_3 = {1{$random}};
+ valid_array_4 = {1{$random}};
+ valid_array_5 = {1{$random}};
+ valid_array_6 = {1{$random}};
+ valid_array_7 = {1{$random}};
+ ur_array_0 = {1{$random}};
+ ur_array_1 = {1{$random}};
+ ur_array_2 = {1{$random}};
+ ur_array_3 = {1{$random}};
+ ur_array_4 = {1{$random}};
+ ur_array_5 = {1{$random}};
+ ur_array_6 = {1{$random}};
+ ur_array_7 = {1{$random}};
+ uw_array_0 = {1{$random}};
+ uw_array_1 = {1{$random}};
+ uw_array_2 = {1{$random}};
+ uw_array_3 = {1{$random}};
+ uw_array_4 = {1{$random}};
+ uw_array_5 = {1{$random}};
+ uw_array_6 = {1{$random}};
+ uw_array_7 = {1{$random}};
+ ux_array_0 = {1{$random}};
+ ux_array_1 = {1{$random}};
+ ux_array_2 = {1{$random}};
+ ux_array_3 = {1{$random}};
+ ux_array_4 = {1{$random}};
+ ux_array_5 = {1{$random}};
+ ux_array_6 = {1{$random}};
+ ux_array_7 = {1{$random}};
+ sr_array_0 = {1{$random}};
+ sr_array_1 = {1{$random}};
+ sr_array_2 = {1{$random}};
+ sr_array_3 = {1{$random}};
+ sr_array_4 = {1{$random}};
+ sr_array_5 = {1{$random}};
+ sr_array_6 = {1{$random}};
+ sr_array_7 = {1{$random}};
+ sw_array_0 = {1{$random}};
+ sw_array_1 = {1{$random}};
+ sw_array_2 = {1{$random}};
+ sw_array_3 = {1{$random}};
+ sw_array_4 = {1{$random}};
+ sw_array_5 = {1{$random}};
+ sw_array_6 = {1{$random}};
+ sw_array_7 = {1{$random}};
+ sx_array_0 = {1{$random}};
+ sx_array_1 = {1{$random}};
+ sx_array_2 = {1{$random}};
+ sx_array_3 = {1{$random}};
+ sx_array_4 = {1{$random}};
+ sx_array_5 = {1{$random}};
+ sx_array_6 = {1{$random}};
+ sx_array_7 = {1{$random}};
+ dirty_array_0 = {1{$random}};
+ dirty_array_1 = {1{$random}};
+ dirty_array_2 = {1{$random}};
+ dirty_array_3 = {1{$random}};
+ dirty_array_4 = {1{$random}};
+ dirty_array_5 = {1{$random}};
+ dirty_array_6 = {1{$random}};
+ dirty_array_7 = {1{$random}};
+ T_488 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ state <= 1'h0;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ state <= 1'h0;
+ end else begin
+ if(T_921) begin
+ state <= 2'h3;
+ end else begin
+ if(T_919) begin
+ if(io_ptw_req_ready) begin
+ if(io_ptw_invalidate) begin
+ state <= 2'h3;
+ end else begin
+ state <= 2'h2;
+ end
+ end else begin
+ if(io_ptw_invalidate) begin
+ state <= 1'h0;
+ end else begin
+ if(T_918) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_918) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_918) begin
+ r_refill_tag <= lookup_tag;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_918) begin
+ r_refill_waddr <= repl_waddr;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_918) begin
+ r_req_asid <= io_req_bits_asid;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_918) begin
+ r_req_vpn <= io_req_bits_vpn;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_918) begin
+ r_req_passthrough <= io_req_bits_passthrough;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_918) begin
+ r_req_instruction <= io_req_bits_instruction;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_918) begin
+ r_req_store <= io_req_bits_store;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_8) begin
+ valid_array_0 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_9) begin
+ valid_array_1 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_10) begin
+ valid_array_2 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_11) begin
+ valid_array_3 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_12) begin
+ valid_array_4 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_13) begin
+ valid_array_5 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_14) begin
+ valid_array_6 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_15) begin
+ valid_array_7 <= GEN_0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_16) begin
+ ur_array_0 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_17) begin
+ ur_array_1 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_18) begin
+ ur_array_2 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_19) begin
+ ur_array_3 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_20) begin
+ ur_array_4 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_21) begin
+ ur_array_5 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_22) begin
+ ur_array_6 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_23) begin
+ ur_array_7 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_24) begin
+ uw_array_0 <= GEN_2;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_25) begin
+ uw_array_1 <= GEN_2;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_26) begin
+ uw_array_2 <= GEN_2;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_27) begin
+ uw_array_3 <= GEN_2;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_28) begin
+ uw_array_4 <= GEN_2;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_29) begin
+ uw_array_5 <= GEN_2;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_30) begin
+ uw_array_6 <= GEN_2;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_31) begin
+ uw_array_7 <= GEN_2;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_32) begin
+ ux_array_0 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_33) begin
+ ux_array_1 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_34) begin
+ ux_array_2 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_35) begin
+ ux_array_3 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_36) begin
+ ux_array_4 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_37) begin
+ ux_array_5 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_38) begin
+ ux_array_6 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_39) begin
+ ux_array_7 <= GEN_3;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_40) begin
+ sr_array_0 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_41) begin
+ sr_array_1 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_42) begin
+ sr_array_2 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_43) begin
+ sr_array_3 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_44) begin
+ sr_array_4 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_45) begin
+ sr_array_5 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_46) begin
+ sr_array_6 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_47) begin
+ sr_array_7 <= GEN_4;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_48) begin
+ sw_array_0 <= GEN_5;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_49) begin
+ sw_array_1 <= GEN_5;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_50) begin
+ sw_array_2 <= GEN_5;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_51) begin
+ sw_array_3 <= GEN_5;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_52) begin
+ sw_array_4 <= GEN_5;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_53) begin
+ sw_array_5 <= GEN_5;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_54) begin
+ sw_array_6 <= GEN_5;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_55) begin
+ sw_array_7 <= GEN_5;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_56) begin
+ sx_array_0 <= GEN_6;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_57) begin
+ sx_array_1 <= GEN_6;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_58) begin
+ sx_array_2 <= GEN_6;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_59) begin
+ sx_array_3 <= GEN_6;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_60) begin
+ sx_array_4 <= GEN_6;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_61) begin
+ sx_array_5 <= GEN_6;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_62) begin
+ sx_array_6 <= GEN_6;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_63) begin
+ sx_array_7 <= GEN_6;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_64) begin
+ dirty_array_0 <= GEN_7;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_65) begin
+ dirty_array_1 <= GEN_7;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_66) begin
+ dirty_array_2 <= GEN_7;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_67) begin
+ dirty_array_3 <= GEN_7;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_68) begin
+ dirty_array_4 <= GEN_7;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_69) begin
+ dirty_array_5 <= GEN_7;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_70) begin
+ dirty_array_6 <= GEN_7;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_ptw_resp_valid) begin
+ if(GEN_71) begin
+ dirty_array_7 <= GEN_7;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_590) begin
+ T_488 <= T_633;
+ end else begin
+ ;
+ end
+ end
+ end
+ always @(posedge tag_ram_T_383_clk) begin
+ if(tag_ram_T_383_en & tag_ram_T_383_mask) begin
+ tag_ram[tag_ram_T_383_addr] <= tag_ram_T_383_data;
+ end
+ end
+endmodule
+module Queue_92(
+ input clk,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [31:0] io_enq_bits_data,
+ input [127:0] io_enq_bits_datablock,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [31:0] io_deq_bits_data,
+ output [127:0] io_deq_bits_datablock,
+ output io_count
+);
+ reg [31:0] ram_data [0:0];
+ wire [31:0] ram_data_T_539_data;
+ wire ram_data_T_539_addr;
+ wire ram_data_T_539_en;
+ wire ram_data_T_539_clk;
+ wire [31:0] ram_data_T_477_data;
+ wire ram_data_T_477_addr;
+ wire ram_data_T_477_mask;
+ wire ram_data_T_477_en;
+ wire ram_data_T_477_clk;
+ reg [127:0] ram_datablock [0:0];
+ wire [127:0] ram_datablock_T_539_data;
+ wire ram_datablock_T_539_addr;
+ wire ram_datablock_T_539_en;
+ wire ram_datablock_T_539_clk;
+ wire [127:0] ram_datablock_T_477_data;
+ wire ram_datablock_T_477_addr;
+ wire ram_datablock_T_477_mask;
+ wire ram_datablock_T_477_en;
+ wire ram_datablock_T_477_clk;
+ reg maybe_full;
+ wire ptr_match;
+ wire T_463;
+ wire empty;
+ wire full;
+ wire maybe_flow;
+ wire do_flow;
+ wire T_469;
+ wire T_471;
+ wire do_enq;
+ wire T_473;
+ wire T_475;
+ wire do_deq;
+ wire T_528;
+ wire T_530;
+ wire T_532;
+ wire T_533;
+ wire T_535;
+ wire T_537;
+ wire T_538;
+ wire [31:0] T_588_data;
+ wire [127:0] T_588_datablock;
+ wire [1:0] T_637;
+ wire ptr_diff;
+ wire T_639;
+ wire [1:0] T_640;
+ assign io_enq_ready = T_538;
+ assign io_deq_valid = T_533;
+ assign io_deq_bits_data = T_588_data;
+ assign io_deq_bits_datablock = T_588_datablock;
+ assign io_count = T_640;
+ assign ram_data_T_539_addr = 1'h0;
+ assign ram_data_T_539_en = 1'h1;
+ assign ram_data_T_539_clk = clk;
+ assign ram_data_T_539_data = ram_data[ram_data_T_539_addr];
+ assign ram_data_T_477_data = io_enq_bits_data;
+ assign ram_data_T_477_addr = 1'h0;
+ assign ram_data_T_477_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_data_T_477_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_data_T_477_clk = clk;
+ assign ram_datablock_T_539_addr = 1'h0;
+ assign ram_datablock_T_539_en = 1'h1;
+ assign ram_datablock_T_539_clk = clk;
+ assign ram_datablock_T_539_data = ram_datablock[ram_datablock_T_539_addr];
+ assign ram_datablock_T_477_data = io_enq_bits_datablock;
+ assign ram_datablock_T_477_addr = 1'h0;
+ assign ram_datablock_T_477_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_datablock_T_477_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_datablock_T_477_clk = clk;
+ assign ptr_match = 1'h0 == 1'h0;
+ assign T_463 = maybe_full == 1'h0;
+ assign empty = ptr_match & T_463;
+ assign full = ptr_match & maybe_full;
+ assign maybe_flow = 1'h0 & empty;
+ assign do_flow = maybe_flow & io_deq_ready;
+ assign T_469 = io_enq_ready & io_enq_valid;
+ assign T_471 = do_flow == 1'h0;
+ assign do_enq = T_469 & T_471;
+ assign T_473 = io_deq_ready & io_deq_valid;
+ assign T_475 = do_flow == 1'h0;
+ assign do_deq = T_473 & T_475;
+ assign T_528 = do_enq != do_deq;
+ assign T_530 = empty == 1'h0;
+ assign T_532 = 1'h0 & io_enq_valid;
+ assign T_533 = T_530 | T_532;
+ assign T_535 = full == 1'h0;
+ assign T_537 = 1'h1 & io_deq_ready;
+ assign T_538 = T_535 | T_537;
+ assign T_588_data = maybe_flow ? io_enq_bits_data : ram_data_T_539_data;
+ assign T_588_datablock = maybe_flow ? io_enq_bits_datablock : ram_datablock_T_539_data;
+ assign T_637 = 1'h0 - 1'h0;
+ assign ptr_diff = T_637[0:0];
+ assign T_639 = maybe_full & ptr_match;
+ assign T_640 = {T_639,ptr_diff};
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_data[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_datablock[initvar] = {4{$random}};
+ maybe_full = {1{$random}};
+ end
+`endif
+ always @(posedge ram_data_T_477_clk) begin
+ if(ram_data_T_477_en & ram_data_T_477_mask) begin
+ ram_data[ram_data_T_477_addr] <= ram_data_T_477_data;
+ end
+ end
+ always @(posedge ram_datablock_T_477_clk) begin
+ if(ram_datablock_T_477_en & ram_datablock_T_477_mask) begin
+ ram_datablock[ram_datablock_T_477_addr] <= ram_datablock_T_477_data;
+ end
+ end
+ always @(posedge clk) begin
+ if(reset) begin
+ maybe_full <= 1'h0;
+ end else begin
+ if(T_528) begin
+ maybe_full <= do_enq;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module Frontend(
+ input clk,
+ input reset,
+ input io_cpu_req_valid,
+ input [39:0] io_cpu_req_bits_pc,
+ input io_cpu_resp_ready,
+ output io_cpu_resp_valid,
+ output [39:0] io_cpu_resp_bits_pc,
+ output [31:0] io_cpu_resp_bits_data_0,
+ output io_cpu_resp_bits_mask,
+ output io_cpu_resp_bits_xcpt_if,
+ output io_cpu_btb_resp_valid,
+ output io_cpu_btb_resp_bits_taken,
+ output io_cpu_btb_resp_bits_mask,
+ output io_cpu_btb_resp_bits_bridx,
+ output [38:0] io_cpu_btb_resp_bits_target,
+ output [5:0] io_cpu_btb_resp_bits_entry,
+ output [6:0] io_cpu_btb_resp_bits_bht_history,
+ output [1:0] io_cpu_btb_resp_bits_bht_value,
+ input io_cpu_btb_update_valid,
+ input io_cpu_btb_update_bits_prediction_valid,
+ input io_cpu_btb_update_bits_prediction_bits_taken,
+ input io_cpu_btb_update_bits_prediction_bits_mask,
+ input io_cpu_btb_update_bits_prediction_bits_bridx,
+ input [38:0] io_cpu_btb_update_bits_prediction_bits_target,
+ input [5:0] io_cpu_btb_update_bits_prediction_bits_entry,
+ input [6:0] io_cpu_btb_update_bits_prediction_bits_bht_history,
+ input [1:0] io_cpu_btb_update_bits_prediction_bits_bht_value,
+ input [38:0] io_cpu_btb_update_bits_pc,
+ input [38:0] io_cpu_btb_update_bits_target,
+ input io_cpu_btb_update_bits_taken,
+ input io_cpu_btb_update_bits_isJump,
+ input io_cpu_btb_update_bits_isReturn,
+ input [38:0] io_cpu_btb_update_bits_br_pc,
+ input io_cpu_bht_update_valid,
+ input io_cpu_bht_update_bits_prediction_valid,
+ input io_cpu_bht_update_bits_prediction_bits_taken,
+ input io_cpu_bht_update_bits_prediction_bits_mask,
+ input io_cpu_bht_update_bits_prediction_bits_bridx,
+ input [38:0] io_cpu_bht_update_bits_prediction_bits_target,
+ input [5:0] io_cpu_bht_update_bits_prediction_bits_entry,
+ input [6:0] io_cpu_bht_update_bits_prediction_bits_bht_history,
+ input [1:0] io_cpu_bht_update_bits_prediction_bits_bht_value,
+ input [38:0] io_cpu_bht_update_bits_pc,
+ input io_cpu_bht_update_bits_taken,
+ input io_cpu_bht_update_bits_mispredict,
+ input io_cpu_ras_update_valid,
+ input io_cpu_ras_update_bits_isCall,
+ input io_cpu_ras_update_bits_isReturn,
+ input [38:0] io_cpu_ras_update_bits_returnAddr,
+ input io_cpu_ras_update_bits_prediction_valid,
+ input io_cpu_ras_update_bits_prediction_bits_taken,
+ input io_cpu_ras_update_bits_prediction_bits_mask,
+ input io_cpu_ras_update_bits_prediction_bits_bridx,
+ input [38:0] io_cpu_ras_update_bits_prediction_bits_target,
+ input [5:0] io_cpu_ras_update_bits_prediction_bits_entry,
+ input [6:0] io_cpu_ras_update_bits_prediction_bits_bht_history,
+ input [1:0] io_cpu_ras_update_bits_prediction_bits_bht_value,
+ input io_cpu_invalidate,
+ output [39:0] io_cpu_npc,
+ input io_ptw_req_ready,
+ output io_ptw_req_valid,
+ output [26:0] io_ptw_req_bits_addr,
+ output [1:0] io_ptw_req_bits_prv,
+ output io_ptw_req_bits_store,
+ output io_ptw_req_bits_fetch,
+ input io_ptw_resp_valid,
+ input io_ptw_resp_bits_error,
+ input [19:0] io_ptw_resp_bits_pte_ppn,
+ input [2:0] io_ptw_resp_bits_pte_reserved_for_software,
+ input io_ptw_resp_bits_pte_d,
+ input io_ptw_resp_bits_pte_r,
+ input [3:0] io_ptw_resp_bits_pte_typ,
+ input io_ptw_resp_bits_pte_v,
+ input io_ptw_status_sd,
+ input [30:0] io_ptw_status_zero2,
+ input io_ptw_status_sd_rv32,
+ input [8:0] io_ptw_status_zero1,
+ input [4:0] io_ptw_status_vm,
+ input io_ptw_status_mprv,
+ input [1:0] io_ptw_status_xs,
+ input [1:0] io_ptw_status_fs,
+ input [1:0] io_ptw_status_prv3,
+ input io_ptw_status_ie3,
+ input [1:0] io_ptw_status_prv2,
+ input io_ptw_status_ie2,
+ input [1:0] io_ptw_status_prv1,
+ input io_ptw_status_ie1,
+ input [1:0] io_ptw_status_prv,
+ input io_ptw_status_ie,
+ input io_ptw_invalidate,
+ input io_mem_acquire_ready,
+ output io_mem_acquire_valid,
+ output [25:0] io_mem_acquire_bits_addr_block,
+ output [1:0] io_mem_acquire_bits_client_xact_id,
+ output [1:0] io_mem_acquire_bits_addr_beat,
+ output io_mem_acquire_bits_is_builtin_type,
+ output [2:0] io_mem_acquire_bits_a_type,
+ output [16:0] io_mem_acquire_bits_union,
+ output [127:0] io_mem_acquire_bits_data,
+ output io_mem_grant_ready,
+ input io_mem_grant_valid,
+ input [1:0] io_mem_grant_bits_addr_beat,
+ input [1:0] io_mem_grant_bits_client_xact_id,
+ input [3:0] io_mem_grant_bits_manager_xact_id,
+ input io_mem_grant_bits_is_builtin_type,
+ input [3:0] io_mem_grant_bits_g_type,
+ input [127:0] io_mem_grant_bits_data
+);
+ wire btb_clk;
+ wire btb_reset;
+ wire btb_io_req_valid;
+ wire [38:0] btb_io_req_bits_addr;
+ wire btb_io_resp_valid;
+ wire btb_io_resp_bits_taken;
+ wire btb_io_resp_bits_mask;
+ wire btb_io_resp_bits_bridx;
+ wire [38:0] btb_io_resp_bits_target;
+ wire [5:0] btb_io_resp_bits_entry;
+ wire [6:0] btb_io_resp_bits_bht_history;
+ wire [1:0] btb_io_resp_bits_bht_value;
+ wire btb_io_btb_update_valid;
+ wire btb_io_btb_update_bits_prediction_valid;
+ wire btb_io_btb_update_bits_prediction_bits_taken;
+ wire btb_io_btb_update_bits_prediction_bits_mask;
+ wire btb_io_btb_update_bits_prediction_bits_bridx;
+ wire [38:0] btb_io_btb_update_bits_prediction_bits_target;
+ wire [5:0] btb_io_btb_update_bits_prediction_bits_entry;
+ wire [6:0] btb_io_btb_update_bits_prediction_bits_bht_history;
+ wire [1:0] btb_io_btb_update_bits_prediction_bits_bht_value;
+ wire [38:0] btb_io_btb_update_bits_pc;
+ wire [38:0] btb_io_btb_update_bits_target;
+ wire btb_io_btb_update_bits_taken;
+ wire btb_io_btb_update_bits_isJump;
+ wire btb_io_btb_update_bits_isReturn;
+ wire [38:0] btb_io_btb_update_bits_br_pc;
+ wire btb_io_bht_update_valid;
+ wire btb_io_bht_update_bits_prediction_valid;
+ wire btb_io_bht_update_bits_prediction_bits_taken;
+ wire btb_io_bht_update_bits_prediction_bits_mask;
+ wire btb_io_bht_update_bits_prediction_bits_bridx;
+ wire [38:0] btb_io_bht_update_bits_prediction_bits_target;
+ wire [5:0] btb_io_bht_update_bits_prediction_bits_entry;
+ wire [6:0] btb_io_bht_update_bits_prediction_bits_bht_history;
+ wire [1:0] btb_io_bht_update_bits_prediction_bits_bht_value;
+ wire [38:0] btb_io_bht_update_bits_pc;
+ wire btb_io_bht_update_bits_taken;
+ wire btb_io_bht_update_bits_mispredict;
+ wire btb_io_ras_update_valid;
+ wire btb_io_ras_update_bits_isCall;
+ wire btb_io_ras_update_bits_isReturn;
+ wire [38:0] btb_io_ras_update_bits_returnAddr;
+ wire btb_io_ras_update_bits_prediction_valid;
+ wire btb_io_ras_update_bits_prediction_bits_taken;
+ wire btb_io_ras_update_bits_prediction_bits_mask;
+ wire btb_io_ras_update_bits_prediction_bits_bridx;
+ wire [38:0] btb_io_ras_update_bits_prediction_bits_target;
+ wire [5:0] btb_io_ras_update_bits_prediction_bits_entry;
+ wire [6:0] btb_io_ras_update_bits_prediction_bits_bht_history;
+ wire [1:0] btb_io_ras_update_bits_prediction_bits_bht_value;
+ wire btb_io_invalidate;
+ wire icache_clk;
+ wire icache_reset;
+ wire icache_io_req_valid;
+ wire [11:0] icache_io_req_bits_idx;
+ wire [19:0] icache_io_req_bits_ppn;
+ wire icache_io_req_bits_kill;
+ wire icache_io_resp_ready;
+ wire icache_io_resp_valid;
+ wire [31:0] icache_io_resp_bits_data;
+ wire [127:0] icache_io_resp_bits_datablock;
+ wire icache_io_invalidate;
+ wire icache_io_mem_acquire_ready;
+ wire icache_io_mem_acquire_valid;
+ wire [25:0] icache_io_mem_acquire_bits_addr_block;
+ wire [1:0] icache_io_mem_acquire_bits_client_xact_id;
+ wire [1:0] icache_io_mem_acquire_bits_addr_beat;
+ wire icache_io_mem_acquire_bits_is_builtin_type;
+ wire [2:0] icache_io_mem_acquire_bits_a_type;
+ wire [16:0] icache_io_mem_acquire_bits_union;
+ wire [127:0] icache_io_mem_acquire_bits_data;
+ wire icache_io_mem_grant_ready;
+ wire icache_io_mem_grant_valid;
+ wire [1:0] icache_io_mem_grant_bits_addr_beat;
+ wire [1:0] icache_io_mem_grant_bits_client_xact_id;
+ wire [3:0] icache_io_mem_grant_bits_manager_xact_id;
+ wire icache_io_mem_grant_bits_is_builtin_type;
+ wire [3:0] icache_io_mem_grant_bits_g_type;
+ wire [127:0] icache_io_mem_grant_bits_data;
+ wire tlb_clk;
+ wire tlb_reset;
+ wire tlb_io_req_ready;
+ wire tlb_io_req_valid;
+ wire [6:0] tlb_io_req_bits_asid;
+ wire [27:0] tlb_io_req_bits_vpn;
+ wire tlb_io_req_bits_passthrough;
+ wire tlb_io_req_bits_instruction;
+ wire tlb_io_req_bits_store;
+ wire tlb_io_resp_miss;
+ wire [19:0] tlb_io_resp_ppn;
+ wire tlb_io_resp_xcpt_ld;
+ wire tlb_io_resp_xcpt_st;
+ wire tlb_io_resp_xcpt_if;
+ wire [7:0] tlb_io_resp_hit_idx;
+ wire tlb_io_ptw_req_ready;
+ wire tlb_io_ptw_req_valid;
+ wire [26:0] tlb_io_ptw_req_bits_addr;
+ wire [1:0] tlb_io_ptw_req_bits_prv;
+ wire tlb_io_ptw_req_bits_store;
+ wire tlb_io_ptw_req_bits_fetch;
+ wire tlb_io_ptw_resp_valid;
+ wire tlb_io_ptw_resp_bits_error;
+ wire [19:0] tlb_io_ptw_resp_bits_pte_ppn;
+ wire [2:0] tlb_io_ptw_resp_bits_pte_reserved_for_software;
+ wire tlb_io_ptw_resp_bits_pte_d;
+ wire tlb_io_ptw_resp_bits_pte_r;
+ wire [3:0] tlb_io_ptw_resp_bits_pte_typ;
+ wire tlb_io_ptw_resp_bits_pte_v;
+ wire tlb_io_ptw_status_sd;
+ wire [30:0] tlb_io_ptw_status_zero2;
+ wire tlb_io_ptw_status_sd_rv32;
+ wire [8:0] tlb_io_ptw_status_zero1;
+ wire [4:0] tlb_io_ptw_status_vm;
+ wire tlb_io_ptw_status_mprv;
+ wire [1:0] tlb_io_ptw_status_xs;
+ wire [1:0] tlb_io_ptw_status_fs;
+ wire [1:0] tlb_io_ptw_status_prv3;
+ wire tlb_io_ptw_status_ie3;
+ wire [1:0] tlb_io_ptw_status_prv2;
+ wire tlb_io_ptw_status_ie2;
+ wire [1:0] tlb_io_ptw_status_prv1;
+ wire tlb_io_ptw_status_ie1;
+ wire [1:0] tlb_io_ptw_status_prv;
+ wire tlb_io_ptw_status_ie;
+ wire tlb_io_ptw_invalidate;
+ reg [39:0] s1_pc_;
+ wire [39:0] T_1280;
+ wire [39:0] T_1282;
+ wire [39:0] s1_pc;
+ reg s1_same_block;
+ reg s2_valid;
+ reg [39:0] s2_pc;
+ reg s2_btb_resp_valid;
+ reg s2_btb_resp_bits_taken;
+ reg s2_btb_resp_bits_mask;
+ reg s2_btb_resp_bits_bridx;
+ reg [38:0] s2_btb_resp_bits_target;
+ reg [5:0] s2_btb_resp_bits_entry;
+ reg [6:0] s2_btb_resp_bits_bht_history;
+ reg [1:0] s2_btb_resp_bits_bht_value;
+ reg s2_xcpt_if;
+ wire s2_resp_valid;
+ wire [127:0] s2_resp_data;
+ wire T_1307;
+ wire [39:0] btbTarget;
+ wire [40:0] T_1310;
+ wire [39:0] ntpc_0;
+ wire T_1312;
+ wire T_1313;
+ wire T_1314;
+ wire [36:0] T_1315;
+ wire [38:0] T_1317;
+ wire [39:0] ntpc;
+ wire T_1320;
+ wire icmiss;
+ wire [39:0] predicted_npc;
+ wire [39:0] npc;
+ wire T_1325;
+ wire T_1327;
+ wire T_1328;
+ wire T_1330;
+ wire T_1331;
+ wire [39:0] T_1333;
+ wire [39:0] T_1335;
+ wire T_1336;
+ wire s0_same_block;
+ wire T_1339;
+ wire stall;
+ wire T_1342;
+ wire T_1344;
+ wire T_1345;
+ wire T_1347;
+ wire T_1349;
+ wire T_1353;
+ wire T_1355;
+ wire T_1356;
+ wire T_1357;
+ wire T_1359;
+ wire T_1361;
+ wire T_1362;
+ wire [27:0] T_1363;
+ wire T_1369;
+ wire T_1371;
+ wire T_1372;
+ wire T_1373;
+ wire T_1374;
+ wire T_1375;
+ wire T_1376;
+ wire T_1377;
+ wire T_1378;
+ wire [39:0] T_1379;
+ wire T_1429_clk;
+ wire T_1429_reset;
+ wire T_1429_io_enq_ready;
+ wire T_1429_io_enq_valid;
+ wire [31:0] T_1429_io_enq_bits_data;
+ wire [127:0] T_1429_io_enq_bits_datablock;
+ wire T_1429_io_deq_ready;
+ wire T_1429_io_deq_valid;
+ wire [31:0] T_1429_io_deq_bits_data;
+ wire [127:0] T_1429_io_deq_bits_datablock;
+ wire T_1429_io_count;
+ wire T_1431;
+ wire T_1433;
+ wire T_1434;
+ wire [1:0] T_1435;
+ wire [6:0] T_1436;
+ wire [127:0] fetch_data;
+ wire [31:0] T_1438;
+ wire [1:0] T_1440;
+ wire [1:0] T_1441;
+ BTB btb (
+ .clk(btb_clk),
+ .reset(btb_reset),
+ .io_req_valid(btb_io_req_valid),
+ .io_req_bits_addr(btb_io_req_bits_addr),
+ .io_resp_valid(btb_io_resp_valid),
+ .io_resp_bits_taken(btb_io_resp_bits_taken),
+ .io_resp_bits_mask(btb_io_resp_bits_mask),
+ .io_resp_bits_bridx(btb_io_resp_bits_bridx),
+ .io_resp_bits_target(btb_io_resp_bits_target),
+ .io_resp_bits_entry(btb_io_resp_bits_entry),
+ .io_resp_bits_bht_history(btb_io_resp_bits_bht_history),
+ .io_resp_bits_bht_value(btb_io_resp_bits_bht_value),
+ .io_btb_update_valid(btb_io_btb_update_valid),
+ .io_btb_update_bits_prediction_valid(btb_io_btb_update_bits_prediction_valid),
+ .io_btb_update_bits_prediction_bits_taken(btb_io_btb_update_bits_prediction_bits_taken),
+ .io_btb_update_bits_prediction_bits_mask(btb_io_btb_update_bits_prediction_bits_mask),
+ .io_btb_update_bits_prediction_bits_bridx(btb_io_btb_update_bits_prediction_bits_bridx),
+ .io_btb_update_bits_prediction_bits_target(btb_io_btb_update_bits_prediction_bits_target),
+ .io_btb_update_bits_prediction_bits_entry(btb_io_btb_update_bits_prediction_bits_entry),
+ .io_btb_update_bits_prediction_bits_bht_history(btb_io_btb_update_bits_prediction_bits_bht_history),
+ .io_btb_update_bits_prediction_bits_bht_value(btb_io_btb_update_bits_prediction_bits_bht_value),
+ .io_btb_update_bits_pc(btb_io_btb_update_bits_pc),
+ .io_btb_update_bits_target(btb_io_btb_update_bits_target),
+ .io_btb_update_bits_taken(btb_io_btb_update_bits_taken),
+ .io_btb_update_bits_isJump(btb_io_btb_update_bits_isJump),
+ .io_btb_update_bits_isReturn(btb_io_btb_update_bits_isReturn),
+ .io_btb_update_bits_br_pc(btb_io_btb_update_bits_br_pc),
+ .io_bht_update_valid(btb_io_bht_update_valid),
+ .io_bht_update_bits_prediction_valid(btb_io_bht_update_bits_prediction_valid),
+ .io_bht_update_bits_prediction_bits_taken(btb_io_bht_update_bits_prediction_bits_taken),
+ .io_bht_update_bits_prediction_bits_mask(btb_io_bht_update_bits_prediction_bits_mask),
+ .io_bht_update_bits_prediction_bits_bridx(btb_io_bht_update_bits_prediction_bits_bridx),
+ .io_bht_update_bits_prediction_bits_target(btb_io_bht_update_bits_prediction_bits_target),
+ .io_bht_update_bits_prediction_bits_entry(btb_io_bht_update_bits_prediction_bits_entry),
+ .io_bht_update_bits_prediction_bits_bht_history(btb_io_bht_update_bits_prediction_bits_bht_history),
+ .io_bht_update_bits_prediction_bits_bht_value(btb_io_bht_update_bits_prediction_bits_bht_value),
+ .io_bht_update_bits_pc(btb_io_bht_update_bits_pc),
+ .io_bht_update_bits_taken(btb_io_bht_update_bits_taken),
+ .io_bht_update_bits_mispredict(btb_io_bht_update_bits_mispredict),
+ .io_ras_update_valid(btb_io_ras_update_valid),
+ .io_ras_update_bits_isCall(btb_io_ras_update_bits_isCall),
+ .io_ras_update_bits_isReturn(btb_io_ras_update_bits_isReturn),
+ .io_ras_update_bits_returnAddr(btb_io_ras_update_bits_returnAddr),
+ .io_ras_update_bits_prediction_valid(btb_io_ras_update_bits_prediction_valid),
+ .io_ras_update_bits_prediction_bits_taken(btb_io_ras_update_bits_prediction_bits_taken),
+ .io_ras_update_bits_prediction_bits_mask(btb_io_ras_update_bits_prediction_bits_mask),
+ .io_ras_update_bits_prediction_bits_bridx(btb_io_ras_update_bits_prediction_bits_bridx),
+ .io_ras_update_bits_prediction_bits_target(btb_io_ras_update_bits_prediction_bits_target),
+ .io_ras_update_bits_prediction_bits_entry(btb_io_ras_update_bits_prediction_bits_entry),
+ .io_ras_update_bits_prediction_bits_bht_history(btb_io_ras_update_bits_prediction_bits_bht_history),
+ .io_ras_update_bits_prediction_bits_bht_value(btb_io_ras_update_bits_prediction_bits_bht_value),
+ .io_invalidate(btb_io_invalidate)
+ );
+ ICache icache (
+ .clk(icache_clk),
+ .reset(icache_reset),
+ .io_req_valid(icache_io_req_valid),
+ .io_req_bits_idx(icache_io_req_bits_idx),
+ .io_req_bits_ppn(icache_io_req_bits_ppn),
+ .io_req_bits_kill(icache_io_req_bits_kill),
+ .io_resp_ready(icache_io_resp_ready),
+ .io_resp_valid(icache_io_resp_valid),
+ .io_resp_bits_data(icache_io_resp_bits_data),
+ .io_resp_bits_datablock(icache_io_resp_bits_datablock),
+ .io_invalidate(icache_io_invalidate),
+ .io_mem_acquire_ready(icache_io_mem_acquire_ready),
+ .io_mem_acquire_valid(icache_io_mem_acquire_valid),
+ .io_mem_acquire_bits_addr_block(icache_io_mem_acquire_bits_addr_block),
+ .io_mem_acquire_bits_client_xact_id(icache_io_mem_acquire_bits_client_xact_id),
+ .io_mem_acquire_bits_addr_beat(icache_io_mem_acquire_bits_addr_beat),
+ .io_mem_acquire_bits_is_builtin_type(icache_io_mem_acquire_bits_is_builtin_type),
+ .io_mem_acquire_bits_a_type(icache_io_mem_acquire_bits_a_type),
+ .io_mem_acquire_bits_union(icache_io_mem_acquire_bits_union),
+ .io_mem_acquire_bits_data(icache_io_mem_acquire_bits_data),
+ .io_mem_grant_ready(icache_io_mem_grant_ready),
+ .io_mem_grant_valid(icache_io_mem_grant_valid),
+ .io_mem_grant_bits_addr_beat(icache_io_mem_grant_bits_addr_beat),
+ .io_mem_grant_bits_client_xact_id(icache_io_mem_grant_bits_client_xact_id),
+ .io_mem_grant_bits_manager_xact_id(icache_io_mem_grant_bits_manager_xact_id),
+ .io_mem_grant_bits_is_builtin_type(icache_io_mem_grant_bits_is_builtin_type),
+ .io_mem_grant_bits_g_type(icache_io_mem_grant_bits_g_type),
+ .io_mem_grant_bits_data(icache_io_mem_grant_bits_data)
+ );
+ TLB tlb (
+ .clk(tlb_clk),
+ .reset(tlb_reset),
+ .io_req_ready(tlb_io_req_ready),
+ .io_req_valid(tlb_io_req_valid),
+ .io_req_bits_asid(tlb_io_req_bits_asid),
+ .io_req_bits_vpn(tlb_io_req_bits_vpn),
+ .io_req_bits_passthrough(tlb_io_req_bits_passthrough),
+ .io_req_bits_instruction(tlb_io_req_bits_instruction),
+ .io_req_bits_store(tlb_io_req_bits_store),
+ .io_resp_miss(tlb_io_resp_miss),
+ .io_resp_ppn(tlb_io_resp_ppn),
+ .io_resp_xcpt_ld(tlb_io_resp_xcpt_ld),
+ .io_resp_xcpt_st(tlb_io_resp_xcpt_st),
+ .io_resp_xcpt_if(tlb_io_resp_xcpt_if),
+ .io_resp_hit_idx(tlb_io_resp_hit_idx),
+ .io_ptw_req_ready(tlb_io_ptw_req_ready),
+ .io_ptw_req_valid(tlb_io_ptw_req_valid),
+ .io_ptw_req_bits_addr(tlb_io_ptw_req_bits_addr),
+ .io_ptw_req_bits_prv(tlb_io_ptw_req_bits_prv),
+ .io_ptw_req_bits_store(tlb_io_ptw_req_bits_store),
+ .io_ptw_req_bits_fetch(tlb_io_ptw_req_bits_fetch),
+ .io_ptw_resp_valid(tlb_io_ptw_resp_valid),
+ .io_ptw_resp_bits_error(tlb_io_ptw_resp_bits_error),
+ .io_ptw_resp_bits_pte_ppn(tlb_io_ptw_resp_bits_pte_ppn),
+ .io_ptw_resp_bits_pte_reserved_for_software(tlb_io_ptw_resp_bits_pte_reserved_for_software),
+ .io_ptw_resp_bits_pte_d(tlb_io_ptw_resp_bits_pte_d),
+ .io_ptw_resp_bits_pte_r(tlb_io_ptw_resp_bits_pte_r),
+ .io_ptw_resp_bits_pte_typ(tlb_io_ptw_resp_bits_pte_typ),
+ .io_ptw_resp_bits_pte_v(tlb_io_ptw_resp_bits_pte_v),
+ .io_ptw_status_sd(tlb_io_ptw_status_sd),
+ .io_ptw_status_zero2(tlb_io_ptw_status_zero2),
+ .io_ptw_status_sd_rv32(tlb_io_ptw_status_sd_rv32),
+ .io_ptw_status_zero1(tlb_io_ptw_status_zero1),
+ .io_ptw_status_vm(tlb_io_ptw_status_vm),
+ .io_ptw_status_mprv(tlb_io_ptw_status_mprv),
+ .io_ptw_status_xs(tlb_io_ptw_status_xs),
+ .io_ptw_status_fs(tlb_io_ptw_status_fs),
+ .io_ptw_status_prv3(tlb_io_ptw_status_prv3),
+ .io_ptw_status_ie3(tlb_io_ptw_status_ie3),
+ .io_ptw_status_prv2(tlb_io_ptw_status_prv2),
+ .io_ptw_status_ie2(tlb_io_ptw_status_ie2),
+ .io_ptw_status_prv1(tlb_io_ptw_status_prv1),
+ .io_ptw_status_ie1(tlb_io_ptw_status_ie1),
+ .io_ptw_status_prv(tlb_io_ptw_status_prv),
+ .io_ptw_status_ie(tlb_io_ptw_status_ie),
+ .io_ptw_invalidate(tlb_io_ptw_invalidate)
+ );
+ Queue_92 T_1429 (
+ .clk(T_1429_clk),
+ .reset(T_1429_reset),
+ .io_enq_ready(T_1429_io_enq_ready),
+ .io_enq_valid(T_1429_io_enq_valid),
+ .io_enq_bits_data(T_1429_io_enq_bits_data),
+ .io_enq_bits_datablock(T_1429_io_enq_bits_datablock),
+ .io_deq_ready(T_1429_io_deq_ready),
+ .io_deq_valid(T_1429_io_deq_valid),
+ .io_deq_bits_data(T_1429_io_deq_bits_data),
+ .io_deq_bits_datablock(T_1429_io_deq_bits_datablock),
+ .io_count(T_1429_io_count)
+ );
+ assign io_cpu_resp_valid = T_1378;
+ assign io_cpu_resp_bits_pc = s2_pc;
+ assign io_cpu_resp_bits_data_0 = T_1438;
+ assign io_cpu_resp_bits_mask = T_1441;
+ assign io_cpu_resp_bits_xcpt_if = s2_xcpt_if;
+ assign io_cpu_btb_resp_valid = s2_btb_resp_valid;
+ assign io_cpu_btb_resp_bits_taken = s2_btb_resp_bits_taken;
+ assign io_cpu_btb_resp_bits_mask = s2_btb_resp_bits_mask;
+ assign io_cpu_btb_resp_bits_bridx = s2_btb_resp_bits_bridx;
+ assign io_cpu_btb_resp_bits_target = s2_btb_resp_bits_target;
+ assign io_cpu_btb_resp_bits_entry = s2_btb_resp_bits_entry;
+ assign io_cpu_btb_resp_bits_bht_history = s2_btb_resp_bits_bht_history;
+ assign io_cpu_btb_resp_bits_bht_value = s2_btb_resp_bits_bht_value;
+ assign io_cpu_npc = T_1379;
+ assign io_ptw_req_valid = tlb_io_ptw_req_valid;
+ assign io_ptw_req_bits_addr = tlb_io_ptw_req_bits_addr;
+ assign io_ptw_req_bits_prv = tlb_io_ptw_req_bits_prv;
+ assign io_ptw_req_bits_store = tlb_io_ptw_req_bits_store;
+ assign io_ptw_req_bits_fetch = tlb_io_ptw_req_bits_fetch;
+ assign io_mem_acquire_valid = icache_io_mem_acquire_valid;
+ assign io_mem_acquire_bits_addr_block = icache_io_mem_acquire_bits_addr_block;
+ assign io_mem_acquire_bits_client_xact_id = icache_io_mem_acquire_bits_client_xact_id;
+ assign io_mem_acquire_bits_addr_beat = icache_io_mem_acquire_bits_addr_beat;
+ assign io_mem_acquire_bits_is_builtin_type = icache_io_mem_acquire_bits_is_builtin_type;
+ assign io_mem_acquire_bits_a_type = icache_io_mem_acquire_bits_a_type;
+ assign io_mem_acquire_bits_union = icache_io_mem_acquire_bits_union;
+ assign io_mem_acquire_bits_data = icache_io_mem_acquire_bits_data;
+ assign io_mem_grant_ready = icache_io_mem_grant_ready;
+ assign btb_clk = clk;
+ assign btb_reset = reset;
+ assign btb_io_req_valid = T_1356;
+ assign btb_io_req_bits_addr = s1_pc;
+ assign btb_io_btb_update_valid = io_cpu_btb_update_valid;
+ assign btb_io_btb_update_bits_prediction_valid = io_cpu_btb_update_bits_prediction_valid;
+ assign btb_io_btb_update_bits_prediction_bits_taken = io_cpu_btb_update_bits_prediction_bits_taken;
+ assign btb_io_btb_update_bits_prediction_bits_mask = io_cpu_btb_update_bits_prediction_bits_mask;
+ assign btb_io_btb_update_bits_prediction_bits_bridx = io_cpu_btb_update_bits_prediction_bits_bridx;
+ assign btb_io_btb_update_bits_prediction_bits_target = io_cpu_btb_update_bits_prediction_bits_target;
+ assign btb_io_btb_update_bits_prediction_bits_entry = io_cpu_btb_update_bits_prediction_bits_entry;
+ assign btb_io_btb_update_bits_prediction_bits_bht_history = io_cpu_btb_update_bits_prediction_bits_bht_history;
+ assign btb_io_btb_update_bits_prediction_bits_bht_value = io_cpu_btb_update_bits_prediction_bits_bht_value;
+ assign btb_io_btb_update_bits_pc = io_cpu_btb_update_bits_pc;
+ assign btb_io_btb_update_bits_target = io_cpu_btb_update_bits_target;
+ assign btb_io_btb_update_bits_taken = io_cpu_btb_update_bits_taken;
+ assign btb_io_btb_update_bits_isJump = io_cpu_btb_update_bits_isJump;
+ assign btb_io_btb_update_bits_isReturn = io_cpu_btb_update_bits_isReturn;
+ assign btb_io_btb_update_bits_br_pc = io_cpu_btb_update_bits_br_pc;
+ assign btb_io_bht_update_valid = io_cpu_bht_update_valid;
+ assign btb_io_bht_update_bits_prediction_valid = io_cpu_bht_update_bits_prediction_valid;
+ assign btb_io_bht_update_bits_prediction_bits_taken = io_cpu_bht_update_bits_prediction_bits_taken;
+ assign btb_io_bht_update_bits_prediction_bits_mask = io_cpu_bht_update_bits_prediction_bits_mask;
+ assign btb_io_bht_update_bits_prediction_bits_bridx = io_cpu_bht_update_bits_prediction_bits_bridx;
+ assign btb_io_bht_update_bits_prediction_bits_target = io_cpu_bht_update_bits_prediction_bits_target;
+ assign btb_io_bht_update_bits_prediction_bits_entry = io_cpu_bht_update_bits_prediction_bits_entry;
+ assign btb_io_bht_update_bits_prediction_bits_bht_history = io_cpu_bht_update_bits_prediction_bits_bht_history;
+ assign btb_io_bht_update_bits_prediction_bits_bht_value = io_cpu_bht_update_bits_prediction_bits_bht_value;
+ assign btb_io_bht_update_bits_pc = io_cpu_bht_update_bits_pc;
+ assign btb_io_bht_update_bits_taken = io_cpu_bht_update_bits_taken;
+ assign btb_io_bht_update_bits_mispredict = io_cpu_bht_update_bits_mispredict;
+ assign btb_io_ras_update_valid = io_cpu_ras_update_valid;
+ assign btb_io_ras_update_bits_isCall = io_cpu_ras_update_bits_isCall;
+ assign btb_io_ras_update_bits_isReturn = io_cpu_ras_update_bits_isReturn;
+ assign btb_io_ras_update_bits_returnAddr = io_cpu_ras_update_bits_returnAddr;
+ assign btb_io_ras_update_bits_prediction_valid = io_cpu_ras_update_bits_prediction_valid;
+ assign btb_io_ras_update_bits_prediction_bits_taken = io_cpu_ras_update_bits_prediction_bits_taken;
+ assign btb_io_ras_update_bits_prediction_bits_mask = io_cpu_ras_update_bits_prediction_bits_mask;
+ assign btb_io_ras_update_bits_prediction_bits_bridx = io_cpu_ras_update_bits_prediction_bits_bridx;
+ assign btb_io_ras_update_bits_prediction_bits_target = io_cpu_ras_update_bits_prediction_bits_target;
+ assign btb_io_ras_update_bits_prediction_bits_entry = io_cpu_ras_update_bits_prediction_bits_entry;
+ assign btb_io_ras_update_bits_prediction_bits_bht_history = io_cpu_ras_update_bits_prediction_bits_bht_history;
+ assign btb_io_ras_update_bits_prediction_bits_bht_value = io_cpu_ras_update_bits_prediction_bits_bht_value;
+ assign btb_io_invalidate = T_1357;
+ assign icache_clk = clk;
+ assign icache_reset = reset;
+ assign icache_io_req_valid = T_1372;
+ assign icache_io_req_bits_idx = io_cpu_npc;
+ assign icache_io_req_bits_ppn = tlb_io_resp_ppn;
+ assign icache_io_req_bits_kill = T_1376;
+ assign icache_io_resp_ready = T_1429_io_enq_ready;
+ assign icache_io_invalidate = io_cpu_invalidate;
+ assign icache_io_mem_acquire_ready = io_mem_acquire_ready;
+ assign icache_io_mem_grant_valid = io_mem_grant_valid;
+ assign icache_io_mem_grant_bits_addr_beat = io_mem_grant_bits_addr_beat;
+ assign icache_io_mem_grant_bits_client_xact_id = io_mem_grant_bits_client_xact_id;
+ assign icache_io_mem_grant_bits_manager_xact_id = io_mem_grant_bits_manager_xact_id;
+ assign icache_io_mem_grant_bits_is_builtin_type = io_mem_grant_bits_is_builtin_type;
+ assign icache_io_mem_grant_bits_g_type = io_mem_grant_bits_g_type;
+ assign icache_io_mem_grant_bits_data = io_mem_grant_bits_data;
+ assign tlb_clk = clk;
+ assign tlb_reset = reset;
+ assign tlb_io_req_valid = T_1362;
+ assign tlb_io_req_bits_asid = 1'h0;
+ assign tlb_io_req_bits_vpn = T_1363;
+ assign tlb_io_req_bits_passthrough = 1'h0;
+ assign tlb_io_req_bits_instruction = 1'h1;
+ assign tlb_io_req_bits_store = 1'h0;
+ assign tlb_io_ptw_req_ready = io_ptw_req_ready;
+ assign tlb_io_ptw_resp_valid = io_ptw_resp_valid;
+ assign tlb_io_ptw_resp_bits_error = io_ptw_resp_bits_error;
+ assign tlb_io_ptw_resp_bits_pte_ppn = io_ptw_resp_bits_pte_ppn;
+ assign tlb_io_ptw_resp_bits_pte_reserved_for_software = io_ptw_resp_bits_pte_reserved_for_software;
+ assign tlb_io_ptw_resp_bits_pte_d = io_ptw_resp_bits_pte_d;
+ assign tlb_io_ptw_resp_bits_pte_r = io_ptw_resp_bits_pte_r;
+ assign tlb_io_ptw_resp_bits_pte_typ = io_ptw_resp_bits_pte_typ;
+ assign tlb_io_ptw_resp_bits_pte_v = io_ptw_resp_bits_pte_v;
+ assign tlb_io_ptw_status_sd = io_ptw_status_sd;
+ assign tlb_io_ptw_status_zero2 = io_ptw_status_zero2;
+ assign tlb_io_ptw_status_sd_rv32 = io_ptw_status_sd_rv32;
+ assign tlb_io_ptw_status_zero1 = io_ptw_status_zero1;
+ assign tlb_io_ptw_status_vm = io_ptw_status_vm;
+ assign tlb_io_ptw_status_mprv = io_ptw_status_mprv;
+ assign tlb_io_ptw_status_xs = io_ptw_status_xs;
+ assign tlb_io_ptw_status_fs = io_ptw_status_fs;
+ assign tlb_io_ptw_status_prv3 = io_ptw_status_prv3;
+ assign tlb_io_ptw_status_ie3 = io_ptw_status_ie3;
+ assign tlb_io_ptw_status_prv2 = io_ptw_status_prv2;
+ assign tlb_io_ptw_status_ie2 = io_ptw_status_ie2;
+ assign tlb_io_ptw_status_prv1 = io_ptw_status_prv1;
+ assign tlb_io_ptw_status_ie1 = io_ptw_status_ie1;
+ assign tlb_io_ptw_status_prv = io_ptw_status_prv;
+ assign tlb_io_ptw_status_ie = io_ptw_status_ie;
+ assign tlb_io_ptw_invalidate = io_ptw_invalidate;
+ assign T_1280 = ~ s1_pc_;
+ assign T_1282 = T_1280 | 2'h3;
+ assign s1_pc = ~ T_1282;
+ assign s2_resp_valid = T_1429_io_deq_valid;
+ assign s2_resp_data = T_1429_io_deq_bits_datablock;
+ assign T_1307 = btb_io_resp_bits_target[38];
+ assign btbTarget = {T_1307,btb_io_resp_bits_target};
+ assign T_1310 = s1_pc + 3'h4;
+ assign ntpc_0 = T_1310[39:0];
+ assign T_1312 = s1_pc[38];
+ assign T_1313 = ntpc_0[38];
+ assign T_1314 = T_1312 & T_1313;
+ assign T_1315 = ntpc_0[38:2];
+ assign T_1317 = {T_1315,2'h0};
+ assign ntpc = {T_1314,T_1317};
+ assign T_1320 = s2_resp_valid == 1'h0;
+ assign icmiss = s2_valid & T_1320;
+ assign predicted_npc = btb_io_resp_bits_taken ? btbTarget : ntpc;
+ assign npc = icmiss ? s2_pc : predicted_npc;
+ assign T_1325 = icmiss == 1'h0;
+ assign T_1327 = io_cpu_req_valid == 1'h0;
+ assign T_1328 = T_1325 & T_1327;
+ assign T_1330 = btb_io_resp_bits_taken == 1'h0;
+ assign T_1331 = T_1328 & T_1330;
+ assign T_1333 = ntpc & 5'h10;
+ assign T_1335 = s1_pc & 5'h10;
+ assign T_1336 = T_1333 == T_1335;
+ assign s0_same_block = T_1331 & T_1336;
+ assign T_1339 = io_cpu_resp_ready == 1'h0;
+ assign stall = io_cpu_resp_valid & T_1339;
+ assign T_1342 = stall == 1'h0;
+ assign T_1344 = tlb_io_resp_miss == 1'h0;
+ assign T_1345 = s0_same_block & T_1344;
+ assign T_1347 = icmiss == 1'h0;
+ assign T_1349 = icmiss == 1'h0;
+ assign T_1353 = stall == 1'h0;
+ assign T_1355 = icmiss == 1'h0;
+ assign T_1356 = T_1353 & T_1355;
+ assign T_1357 = io_cpu_invalidate | io_ptw_invalidate;
+ assign T_1359 = stall == 1'h0;
+ assign T_1361 = icmiss == 1'h0;
+ assign T_1362 = T_1359 & T_1361;
+ assign T_1363 = s1_pc[39:12];
+ assign T_1369 = stall == 1'h0;
+ assign T_1371 = s0_same_block == 1'h0;
+ assign T_1372 = T_1369 & T_1371;
+ assign T_1373 = io_cpu_req_valid | tlb_io_resp_miss;
+ assign T_1374 = T_1373 | tlb_io_resp_xcpt_if;
+ assign T_1375 = T_1374 | icmiss;
+ assign T_1376 = T_1375 | io_ptw_invalidate;
+ assign T_1377 = s2_xcpt_if | s2_resp_valid;
+ assign T_1378 = s2_valid & T_1377;
+ assign T_1379 = io_cpu_req_valid ? io_cpu_req_bits_pc : npc;
+ assign T_1429_clk = clk;
+ assign T_1429_reset = reset;
+ assign T_1429_io_enq_valid = icache_io_resp_valid;
+ assign T_1429_io_enq_bits_data = icache_io_resp_bits_data;
+ assign T_1429_io_enq_bits_datablock = icache_io_resp_bits_datablock;
+ assign T_1429_io_deq_ready = T_1434;
+ assign T_1431 = stall == 1'h0;
+ assign T_1433 = s1_same_block == 1'h0;
+ assign T_1434 = T_1431 & T_1433;
+ assign T_1435 = s2_pc[3:2];
+ assign T_1436 = T_1435 << 5;
+ assign fetch_data = s2_resp_data >> T_1436;
+ assign T_1438 = fetch_data[31:0];
+ assign T_1440 = 2'h3 & s2_btb_resp_bits_mask;
+ assign T_1441 = s2_btb_resp_valid ? T_1440 : 2'h3;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ s1_pc_ = {2{$random}};
+ s1_same_block = {1{$random}};
+ s2_valid = {1{$random}};
+ s2_pc = {2{$random}};
+ s2_btb_resp_valid = {1{$random}};
+ s2_btb_resp_bits_taken = {1{$random}};
+ s2_btb_resp_bits_mask = {1{$random}};
+ s2_btb_resp_bits_bridx = {1{$random}};
+ s2_btb_resp_bits_target = {2{$random}};
+ s2_btb_resp_bits_entry = {1{$random}};
+ s2_btb_resp_bits_bht_history = {1{$random}};
+ s2_btb_resp_bits_bht_value = {1{$random}};
+ s2_xcpt_if = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_cpu_req_valid) begin
+ s1_pc_ <= io_cpu_req_bits_pc;
+ end else begin
+ if(T_1342) begin
+ s1_pc_ <= npc;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_cpu_req_valid) begin
+ s1_same_block <= 1'h0;
+ end else begin
+ if(T_1342) begin
+ s1_same_block <= T_1345;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ s2_valid <= 1'h1;
+ end else begin
+ if(io_cpu_req_valid) begin
+ s2_valid <= 1'h0;
+ end else begin
+ if(T_1342) begin
+ s2_valid <= T_1347;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ s2_pc <= 10'h200;
+ end else begin
+ if(T_1342) begin
+ if(T_1349) begin
+ s2_pc <= s1_pc;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ s2_btb_resp_valid <= 1'h0;
+ end else begin
+ if(T_1342) begin
+ if(T_1349) begin
+ s2_btb_resp_valid <= btb_io_resp_valid;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1342) begin
+ if(T_1349) begin
+ if(btb_io_resp_valid) begin
+ s2_btb_resp_bits_taken <= btb_io_resp_bits_taken;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1342) begin
+ if(T_1349) begin
+ if(btb_io_resp_valid) begin
+ s2_btb_resp_bits_mask <= btb_io_resp_bits_mask;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1342) begin
+ if(T_1349) begin
+ if(btb_io_resp_valid) begin
+ s2_btb_resp_bits_bridx <= btb_io_resp_bits_bridx;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1342) begin
+ if(T_1349) begin
+ if(btb_io_resp_valid) begin
+ s2_btb_resp_bits_target <= btb_io_resp_bits_target;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1342) begin
+ if(T_1349) begin
+ if(btb_io_resp_valid) begin
+ s2_btb_resp_bits_entry <= btb_io_resp_bits_entry;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1342) begin
+ if(T_1349) begin
+ if(btb_io_resp_valid) begin
+ s2_btb_resp_bits_bht_history <= btb_io_resp_bits_bht_history;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1342) begin
+ if(T_1349) begin
+ if(btb_io_resp_valid) begin
+ s2_btb_resp_bits_bht_value <= btb_io_resp_bits_bht_value;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ s2_xcpt_if <= 1'h0;
+ end else begin
+ if(T_1342) begin
+ if(T_1349) begin
+ s2_xcpt_if <= tlb_io_resp_xcpt_if;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module WritebackUnit(
+ input clk,
+ input reset,
+ output io_req_ready,
+ input io_req_valid,
+ input [1:0] io_req_bits_addr_beat,
+ input [25:0] io_req_bits_addr_block,
+ input [1:0] io_req_bits_client_xact_id,
+ input io_req_bits_voluntary,
+ input [2:0] io_req_bits_r_type,
+ input [127:0] io_req_bits_data,
+ input [3:0] io_req_bits_way_en,
+ input io_meta_read_ready,
+ output io_meta_read_valid,
+ output [5:0] io_meta_read_bits_idx,
+ output [19:0] io_meta_read_bits_tag,
+ input io_data_req_ready,
+ output io_data_req_valid,
+ output [3:0] io_data_req_bits_way_en,
+ output [11:0] io_data_req_bits_addr,
+ input [127:0] io_data_resp,
+ input io_release_ready,
+ output io_release_valid,
+ output [1:0] io_release_bits_addr_beat,
+ output [25:0] io_release_bits_addr_block,
+ output [1:0] io_release_bits_client_xact_id,
+ output io_release_bits_voluntary,
+ output [2:0] io_release_bits_r_type,
+ output [127:0] io_release_bits_data
+);
+ reg active;
+ reg r1_data_req_fired;
+ reg r2_data_req_fired;
+ reg [2:0] data_req_cnt;
+ wire T_476;
+ wire beat_done;
+ wire T_479;
+ reg [1:0] beat_cnt;
+ wire T_483;
+ wire T_485;
+ wire [2:0] T_488;
+ wire [1:0] T_489;
+ wire [1:0] T_490;
+ wire all_beats_done;
+ reg [1:0] req_addr_beat;
+ reg [25:0] req_addr_block;
+ reg [1:0] req_client_xact_id;
+ reg req_voluntary;
+ reg [2:0] req_r_type;
+ reg [127:0] req_data;
+ reg [3:0] req_way_en;
+ wire T_556;
+ wire T_557;
+ wire T_558;
+ wire [3:0] T_561;
+ wire [2:0] T_562;
+ wire T_564;
+ wire T_568;
+ wire [1:0] T_571;
+ wire [3:0] T_572;
+ wire [2:0] T_573;
+ wire T_575;
+ wire T_577;
+ wire T_579;
+ wire T_581;
+ wire T_582;
+ wire T_583;
+ wire T_587;
+ wire [5:0] req_idx;
+ wire T_590;
+ wire fire;
+ wire [19:0] T_592;
+ wire [1:0] T_593;
+ wire [7:0] T_594;
+ wire [11:0] T_595;
+ assign io_req_ready = T_587;
+ assign io_meta_read_valid = fire;
+ assign io_meta_read_bits_idx = req_idx;
+ assign io_meta_read_bits_tag = T_592;
+ assign io_data_req_valid = fire;
+ assign io_data_req_bits_way_en = req_way_en;
+ assign io_data_req_bits_addr = T_595;
+ assign io_release_valid = active ? r2_data_req_fired ? beat_done : 1'h0 : 1'h0;
+ assign io_release_bits_addr_beat = beat_cnt;
+ assign io_release_bits_addr_block = req_addr_block;
+ assign io_release_bits_client_xact_id = req_client_xact_id;
+ assign io_release_bits_voluntary = req_voluntary;
+ assign io_release_bits_r_type = req_r_type;
+ assign io_release_bits_data = io_data_resp;
+ assign T_476 = ~ 1'h1;
+ assign beat_done = T_476 == 1'h0;
+ assign T_479 = io_release_ready & io_release_valid;
+ assign T_483 = beat_cnt == 2'h3;
+ assign T_485 = 1'h0 & T_483;
+ assign T_488 = beat_cnt + 1'h1;
+ assign T_489 = T_488[1:0];
+ assign T_490 = T_485 ? 1'h0 : T_489;
+ assign all_beats_done = T_479 & T_483;
+ assign T_556 = io_data_req_ready & io_data_req_valid;
+ assign T_557 = io_meta_read_ready & io_meta_read_valid;
+ assign T_558 = T_556 & T_557;
+ assign T_561 = data_req_cnt + 1'h1;
+ assign T_562 = T_561[2:0];
+ assign T_564 = io_release_ready == 1'h0;
+ assign T_568 = 1'h1 & r1_data_req_fired;
+ assign T_571 = T_568 ? 2'h2 : 1'h1;
+ assign T_572 = data_req_cnt - T_571;
+ assign T_573 = T_572[2:0];
+ assign T_575 = T_564 == 1'h0;
+ assign T_577 = r1_data_req_fired == 1'h0;
+ assign T_579 = data_req_cnt < 3'h4;
+ assign T_581 = io_release_ready == 1'h0;
+ assign T_582 = T_579 | T_581;
+ assign T_583 = io_req_ready & io_req_valid;
+ assign T_587 = active == 1'h0;
+ assign req_idx = req_addr_block[5:0];
+ assign T_590 = data_req_cnt < 3'h4;
+ assign fire = active & T_590;
+ assign T_592 = req_addr_block[25:6];
+ assign T_593 = data_req_cnt[1:0];
+ assign T_594 = {req_idx,T_593};
+ assign T_595 = T_594 << 4;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ active = {1{$random}};
+ r1_data_req_fired = {1{$random}};
+ r2_data_req_fired = {1{$random}};
+ data_req_cnt = {1{$random}};
+ beat_cnt = {1{$random}};
+ req_addr_beat = {1{$random}};
+ req_addr_block = {1{$random}};
+ req_client_xact_id = {1{$random}};
+ req_voluntary = {1{$random}};
+ req_r_type = {1{$random}};
+ req_data = {4{$random}};
+ req_way_en = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ active <= 1'h0;
+ end else begin
+ if(T_583) begin
+ active <= 1'h1;
+ end else begin
+ if(active) begin
+ if(r2_data_req_fired) begin
+ if(T_577) begin
+ active <= T_582;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ r1_data_req_fired <= 1'h0;
+ end else begin
+ if(active) begin
+ if(r2_data_req_fired) begin
+ if(beat_done) begin
+ if(T_564) begin
+ r1_data_req_fired <= 1'h0;
+ end else begin
+ if(T_558) begin
+ r1_data_req_fired <= 1'h1;
+ end else begin
+ r1_data_req_fired <= 1'h0;
+ end
+ end
+ end else begin
+ if(T_558) begin
+ r1_data_req_fired <= 1'h1;
+ end else begin
+ r1_data_req_fired <= 1'h0;
+ end
+ end
+ end else begin
+ if(T_558) begin
+ r1_data_req_fired <= 1'h1;
+ end else begin
+ r1_data_req_fired <= 1'h0;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ r2_data_req_fired <= 1'h0;
+ end else begin
+ if(active) begin
+ if(r2_data_req_fired) begin
+ if(beat_done) begin
+ if(T_564) begin
+ r2_data_req_fired <= 1'h0;
+ end else begin
+ r2_data_req_fired <= r1_data_req_fired;
+ end
+ end else begin
+ r2_data_req_fired <= r1_data_req_fired;
+ end
+ end else begin
+ r2_data_req_fired <= r1_data_req_fired;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ data_req_cnt <= 3'h0;
+ end else begin
+ if(T_583) begin
+ data_req_cnt <= 1'h0;
+ end else begin
+ if(active) begin
+ if(r2_data_req_fired) begin
+ if(beat_done) begin
+ if(T_564) begin
+ data_req_cnt <= T_573;
+ end else begin
+ if(T_558) begin
+ data_req_cnt <= T_562;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_558) begin
+ data_req_cnt <= T_562;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_558) begin
+ data_req_cnt <= T_562;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(reset) begin
+ beat_cnt <= 2'h0;
+ end else begin
+ if(T_479) begin
+ beat_cnt <= T_490;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_583) begin
+ req_addr_beat <= io_req_bits_addr_beat;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_583) begin
+ req_addr_block <= io_req_bits_addr_block;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_583) begin
+ req_client_xact_id <= io_req_bits_client_xact_id;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_583) begin
+ req_voluntary <= io_req_bits_voluntary;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_583) begin
+ req_r_type <= io_req_bits_r_type;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_583) begin
+ req_data <= io_req_bits_data;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_583) begin
+ req_way_en <= io_req_bits_way_en;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module ProbeUnit(
+ input clk,
+ input reset,
+ output io_req_ready,
+ input io_req_valid,
+ input [25:0] io_req_bits_addr_block,
+ input [1:0] io_req_bits_p_type,
+ input [1:0] io_req_bits_client_xact_id,
+ input io_rep_ready,
+ output io_rep_valid,
+ output [1:0] io_rep_bits_addr_beat,
+ output [25:0] io_rep_bits_addr_block,
+ output [1:0] io_rep_bits_client_xact_id,
+ output io_rep_bits_voluntary,
+ output [2:0] io_rep_bits_r_type,
+ output [127:0] io_rep_bits_data,
+ input io_meta_read_ready,
+ output io_meta_read_valid,
+ output [5:0] io_meta_read_bits_idx,
+ output [19:0] io_meta_read_bits_tag,
+ input io_meta_write_ready,
+ output io_meta_write_valid,
+ output [5:0] io_meta_write_bits_idx,
+ output [3:0] io_meta_write_bits_way_en,
+ output [19:0] io_meta_write_bits_data_tag,
+ output [1:0] io_meta_write_bits_data_coh_state,
+ input io_wb_req_ready,
+ output io_wb_req_valid,
+ output [1:0] io_wb_req_bits_addr_beat,
+ output [25:0] io_wb_req_bits_addr_block,
+ output [1:0] io_wb_req_bits_client_xact_id,
+ output io_wb_req_bits_voluntary,
+ output [2:0] io_wb_req_bits_r_type,
+ output [127:0] io_wb_req_bits_data,
+ output [3:0] io_wb_req_bits_way_en,
+ input [3:0] io_way_en,
+ input io_mshr_rdy,
+ input [1:0] io_block_state_state
+);
+ reg [3:0] state;
+ reg [1:0] old_coh_state;
+ reg [3:0] way_en;
+ reg [25:0] req_addr_block;
+ reg [1:0] req_p_type;
+ reg [1:0] req_client_xact_id;
+ wire tag_matches;
+ wire [1:0] miss_coh_state;
+ wire [1:0] reply_coh_state;
+ wire [1:0] T_947_0;
+ wire T_950;
+ wire T_952;
+ wire [1:0] T_953;
+ wire [2:0] T_954;
+ wire [2:0] T_955;
+ wire T_956;
+ wire [2:0] T_957;
+ wire T_958;
+ wire [2:0] T_959;
+ wire T_960;
+ wire [2:0] T_961;
+ wire [1:0] T_963_0;
+ wire T_966;
+ wire T_968;
+ wire [1:0] T_969;
+ wire [2:0] T_970;
+ wire [2:0] T_971;
+ wire T_972;
+ wire [2:0] T_973;
+ wire T_974;
+ wire [2:0] T_975;
+ wire T_976;
+ wire [2:0] T_977;
+ wire [1:0] T_979_0;
+ wire T_982;
+ wire T_984;
+ wire [1:0] T_985;
+ wire [2:0] T_986;
+ wire [2:0] T_987;
+ wire T_988;
+ wire [2:0] T_989;
+ wire T_990;
+ wire [2:0] T_991;
+ wire T_992;
+ wire [2:0] T_993;
+ wire T_994;
+ wire [2:0] T_995;
+ wire T_996;
+ wire [2:0] T_997;
+ wire T_998;
+ wire [2:0] T_999;
+ wire [1:0] reply_addr_beat;
+ wire [25:0] reply_addr_block;
+ wire [1:0] reply_client_xact_id;
+ wire reply_voluntary;
+ wire [2:0] reply_r_type;
+ wire [127:0] reply_data;
+ wire T_1061;
+ wire T_1062;
+ wire T_1064;
+ wire [1:0] T_1066_0;
+ wire [1:0] T_1066_1;
+ wire [1:0] T_1066_2;
+ wire T_1071;
+ wire T_1072;
+ wire T_1073;
+ wire T_1075;
+ wire T_1076;
+ wire T_1077;
+ wire T_1079;
+ wire T_1080;
+ wire T_1082;
+ wire T_1084;
+ wire T_1086;
+ wire T_1087;
+ wire [19:0] T_1088;
+ wire T_1089;
+ wire [19:0] T_1090;
+ wire T_1091;
+ wire [1:0] T_1092;
+ wire T_1093;
+ wire [1:0] T_1094;
+ wire T_1095;
+ wire [1:0] T_1096;
+ wire [1:0] T_1122_state;
+ wire T_1147;
+ wire T_1148;
+ wire T_1149;
+ wire T_1150;
+ wire T_1151;
+ wire T_1153;
+ wire T_1154;
+ wire [1:0] T_1156_0;
+ wire T_1159;
+ wire T_1161;
+ wire T_1162;
+ wire [2:0] T_1163;
+ wire T_1164;
+ wire T_1165;
+ wire [3:0] T_1166;
+ wire T_1167;
+ wire T_1168;
+ wire T_1169;
+ wire T_1170;
+ wire GEN_0;
+ assign io_req_ready = T_1061;
+ assign io_rep_valid = T_1062;
+ assign io_rep_bits_addr_beat = reply_addr_beat;
+ assign io_rep_bits_addr_block = reply_addr_block;
+ assign io_rep_bits_client_xact_id = reply_client_xact_id;
+ assign io_rep_bits_voluntary = reply_voluntary;
+ assign io_rep_bits_r_type = reply_r_type;
+ assign io_rep_bits_data = reply_data;
+ assign io_meta_read_valid = T_1087;
+ assign io_meta_read_bits_idx = req_addr_block;
+ assign io_meta_read_bits_tag = T_1088;
+ assign io_meta_write_valid = T_1089;
+ assign io_meta_write_bits_idx = req_addr_block;
+ assign io_meta_write_bits_way_en = way_en;
+ assign io_meta_write_bits_data_tag = T_1090;
+ assign io_meta_write_bits_data_coh_state = T_1122_state;
+ assign io_wb_req_valid = T_1147;
+ assign io_wb_req_bits_addr_beat = reply_addr_beat;
+ assign io_wb_req_bits_addr_block = reply_addr_block;
+ assign io_wb_req_bits_client_xact_id = reply_client_xact_id;
+ assign io_wb_req_bits_voluntary = reply_voluntary;
+ assign io_wb_req_bits_r_type = reply_r_type;
+ assign io_wb_req_bits_data = reply_data;
+ assign io_wb_req_bits_way_en = way_en;
+ assign tag_matches = way_en != 1'h0;
+ assign miss_coh_state = 1'h0;
+ assign reply_coh_state = tag_matches ? old_coh_state : miss_coh_state;
+ assign T_947_0 = 2'h3;
+ assign T_950 = T_947_0 == reply_coh_state;
+ assign T_952 = 1'h0 | T_950;
+ assign T_953 = T_952 ? 1'h0 : 2'h3;
+ assign T_954 = T_952 ? 1'h1 : 3'h4;
+ assign T_955 = T_952 ? 2'h2 : 3'h5;
+ assign T_956 = 5'h13 == 5'h10;
+ assign T_957 = T_956 ? T_955 : 3'h5;
+ assign T_958 = 5'h11 == 5'h10;
+ assign T_959 = T_958 ? T_954 : T_957;
+ assign T_960 = 5'h10 == 5'h10;
+ assign T_961 = T_960 ? T_953 : T_959;
+ assign T_963_0 = 2'h3;
+ assign T_966 = T_963_0 == reply_coh_state;
+ assign T_968 = 1'h0 | T_966;
+ assign T_969 = T_968 ? 1'h0 : 2'h3;
+ assign T_970 = T_968 ? 1'h1 : 3'h4;
+ assign T_971 = T_968 ? 2'h2 : 3'h5;
+ assign T_972 = 5'h13 == 5'h11;
+ assign T_973 = T_972 ? T_971 : 3'h5;
+ assign T_974 = 5'h11 == 5'h11;
+ assign T_975 = T_974 ? T_970 : T_973;
+ assign T_976 = 5'h10 == 5'h11;
+ assign T_977 = T_976 ? T_969 : T_975;
+ assign T_979_0 = 2'h3;
+ assign T_982 = T_979_0 == reply_coh_state;
+ assign T_984 = 1'h0 | T_982;
+ assign T_985 = T_984 ? 1'h0 : 2'h3;
+ assign T_986 = T_984 ? 1'h1 : 3'h4;
+ assign T_987 = T_984 ? 2'h2 : 3'h5;
+ assign T_988 = 5'h13 == 5'h13;
+ assign T_989 = T_988 ? T_987 : 3'h5;
+ assign T_990 = 5'h11 == 5'h13;
+ assign T_991 = T_990 ? T_986 : T_989;
+ assign T_992 = 5'h10 == 5'h13;
+ assign T_993 = T_992 ? T_985 : T_991;
+ assign T_994 = 2'h2 == req_p_type;
+ assign T_995 = T_994 ? T_993 : 2'h3;
+ assign T_996 = 1'h1 == req_p_type;
+ assign T_997 = T_996 ? T_977 : T_995;
+ assign T_998 = 1'h0 == req_p_type;
+ assign T_999 = T_998 ? T_961 : T_997;
+ assign reply_addr_beat = 1'h0;
+ assign reply_addr_block = req_addr_block;
+ assign reply_client_xact_id = 1'h0;
+ assign reply_voluntary = 1'h0;
+ assign reply_r_type = T_999;
+ assign reply_data = 1'h0;
+ assign T_1061 = state == 1'h0;
+ assign T_1062 = state == 3'h5;
+ assign T_1064 = io_rep_valid == 1'h0;
+ assign T_1066_0 = 1'h0;
+ assign T_1066_1 = 1'h1;
+ assign T_1066_2 = 2'h2;
+ assign T_1071 = T_1066_0 == io_rep_bits_r_type;
+ assign T_1072 = T_1066_1 == io_rep_bits_r_type;
+ assign T_1073 = T_1066_2 == io_rep_bits_r_type;
+ assign T_1075 = 1'h0 | T_1071;
+ assign T_1076 = T_1075 | T_1072;
+ assign T_1077 = T_1076 | T_1073;
+ assign T_1079 = T_1077 == 1'h0;
+ assign T_1080 = T_1064 | T_1079;
+ assign T_1082 = reset == 1'h0;
+ assign T_1084 = T_1080 == 1'h0;
+ assign T_1086 = reset == 1'h0;
+ assign T_1087 = state == 1'h1;
+ assign T_1088 = req_addr_block[25:6];
+ assign T_1089 = state == 4'h8;
+ assign T_1090 = req_addr_block[25:6];
+ assign T_1091 = 2'h2 == req_p_type;
+ assign T_1092 = T_1091 ? old_coh_state : old_coh_state;
+ assign T_1093 = 1'h1 == req_p_type;
+ assign T_1094 = T_1093 ? 1'h1 : T_1092;
+ assign T_1095 = 1'h0 == req_p_type;
+ assign T_1096 = T_1095 ? 1'h0 : T_1094;
+ assign T_1122_state = T_1096;
+ assign T_1147 = state == 3'h6;
+ assign T_1148 = io_req_ready & io_req_valid;
+ assign T_1149 = io_meta_read_ready & io_meta_read_valid;
+ assign T_1150 = state == 2'h2;
+ assign T_1151 = state == 2'h3;
+ assign T_1153 = io_mshr_rdy == 1'h0;
+ assign T_1154 = state == 3'h4;
+ assign T_1156_0 = 2'h3;
+ assign T_1159 = T_1156_0 == old_coh_state;
+ assign T_1161 = 1'h0 | T_1159;
+ assign T_1162 = tag_matches & T_1161;
+ assign T_1163 = T_1162 ? 3'h6 : 3'h5;
+ assign T_1164 = state == 3'h5;
+ assign T_1165 = T_1164 & io_rep_ready;
+ assign T_1166 = tag_matches ? 4'h8 : 1'h0;
+ assign T_1167 = io_wb_req_ready & io_wb_req_valid;
+ assign T_1168 = state == 3'h7;
+ assign T_1169 = T_1168 & io_wb_req_ready;
+ assign T_1170 = io_meta_write_ready & io_meta_write_valid;
+ assign GEN_0 = T_1082 & T_1084;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ state = {1{$random}};
+ old_coh_state = {1{$random}};
+ way_en = {1{$random}};
+ req_addr_block = {1{$random}};
+ req_p_type = {1{$random}};
+ req_client_xact_id = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1170) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1169) begin
+ state <= 4'h8;
+ end else begin
+ if(T_1167) begin
+ state <= 3'h7;
+ end else begin
+ if(T_1165) begin
+ state <= T_1166;
+ end else begin
+ if(T_1154) begin
+ state <= T_1163;
+ end else begin
+ if(T_1151) begin
+ if(T_1153) begin
+ state <= 1'h1;
+ end else begin
+ state <= 3'h4;
+ end
+ end else begin
+ if(T_1150) begin
+ state <= 2'h3;
+ end else begin
+ if(T_1149) begin
+ state <= 2'h2;
+ end else begin
+ if(T_1148) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1151) begin
+ old_coh_state <= io_block_state_state;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1151) begin
+ way_en <= io_way_en;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1148) begin
+ req_addr_block <= io_req_bits_addr_block;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1148) begin
+ req_p_type <= io_req_bits_p_type;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1148) begin
+ req_client_xact_id <= io_req_bits_client_xact_id;
+ end else begin
+ ;
+ end
+ end
+ `ifndef SYNTHESIS
+ if(GEN_0 & T_1086) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): ProbeUnit should not send releases with data");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_1082 & T_1084) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ end
+endmodule
+module Arbiter_93(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input [5:0] io_in_0_bits_idx,
+ input [19:0] io_in_0_bits_tag,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input [5:0] io_in_1_bits_idx,
+ input [19:0] io_in_1_bits_tag,
+ input io_out_ready,
+ output io_out_valid,
+ output [5:0] io_out_bits_idx,
+ output [19:0] io_out_bits_tag,
+ output io_chosen
+);
+ wire T_108;
+ wire GEN_0;
+ wire [5:0] GEN_1;
+ wire [19:0] GEN_2;
+ wire GEN_3;
+ wire T_139;
+ wire T_141;
+ wire T_143;
+ wire T_144;
+ wire T_145;
+ wire T_147;
+ wire T_148;
+ wire T_149;
+ wire T_152;
+ wire T_153;
+ wire GEN_4;
+ wire GEN_5;
+ wire GEN_6;
+ assign io_in_0_ready = T_145;
+ assign io_in_1_ready = T_149;
+ assign io_out_valid = GEN_0;
+ assign io_out_bits_idx = GEN_1;
+ assign io_out_bits_tag = GEN_2;
+ assign io_chosen = T_108;
+ assign T_108 = T_153;
+ assign GEN_0 = GEN_4 ? io_in_1_valid : io_in_0_valid;
+ assign GEN_1 = GEN_5 ? io_in_1_bits_idx : io_in_0_bits_idx;
+ assign GEN_2 = GEN_6 ? io_in_1_bits_tag : io_in_0_bits_tag;
+ assign GEN_3 = 1'h0;
+ assign T_139 = 1'h0 | io_in_0_valid;
+ assign T_141 = T_139 == 1'h0;
+ assign T_143 = 1'h1 == 1'h0;
+ assign T_144 = 1'h0 ? T_143 : 1'h1;
+ assign T_145 = T_144 & io_out_ready;
+ assign T_147 = 1'h1 == 1'h1;
+ assign T_148 = 1'h0 ? T_147 : T_141;
+ assign T_149 = T_148 & io_out_ready;
+ assign T_152 = io_in_0_valid ? 1'h0 : 1'h1;
+ assign T_153 = 1'h0 ? 1'h1 : T_152;
+ assign GEN_4 = 1'h1 == T_108;
+ assign GEN_5 = 1'h1 == T_108;
+ assign GEN_6 = 1'h1 == T_108;
+endmodule
+module Arbiter_94(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input [5:0] io_in_0_bits_idx,
+ input [3:0] io_in_0_bits_way_en,
+ input [19:0] io_in_0_bits_data_tag,
+ input [1:0] io_in_0_bits_data_coh_state,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input [5:0] io_in_1_bits_idx,
+ input [3:0] io_in_1_bits_way_en,
+ input [19:0] io_in_1_bits_data_tag,
+ input [1:0] io_in_1_bits_data_coh_state,
+ input io_out_ready,
+ output io_out_valid,
+ output [5:0] io_out_bits_idx,
+ output [3:0] io_out_bits_way_en,
+ output [19:0] io_out_bits_data_tag,
+ output [1:0] io_out_bits_data_coh_state,
+ output io_chosen
+);
+ wire T_1714;
+ wire GEN_0;
+ wire [5:0] GEN_1;
+ wire [3:0] GEN_2;
+ wire [19:0] GEN_3;
+ wire [1:0] GEN_4;
+ wire GEN_5;
+ wire T_2183;
+ wire T_2185;
+ wire T_2187;
+ wire T_2188;
+ wire T_2189;
+ wire T_2191;
+ wire T_2192;
+ wire T_2193;
+ wire T_2196;
+ wire T_2197;
+ wire GEN_6;
+ wire GEN_7;
+ wire GEN_8;
+ wire GEN_9;
+ wire GEN_10;
+ assign io_in_0_ready = T_2189;
+ assign io_in_1_ready = T_2193;
+ assign io_out_valid = GEN_0;
+ assign io_out_bits_idx = GEN_1;
+ assign io_out_bits_way_en = GEN_2;
+ assign io_out_bits_data_tag = GEN_3;
+ assign io_out_bits_data_coh_state = GEN_4;
+ assign io_chosen = T_1714;
+ assign T_1714 = T_2197;
+ assign GEN_0 = GEN_6 ? io_in_1_valid : io_in_0_valid;
+ assign GEN_1 = GEN_7 ? io_in_1_bits_idx : io_in_0_bits_idx;
+ assign GEN_2 = GEN_8 ? io_in_1_bits_way_en : io_in_0_bits_way_en;
+ assign GEN_3 = GEN_9 ? io_in_1_bits_data_tag : io_in_0_bits_data_tag;
+ assign GEN_4 = GEN_10 ? io_in_1_bits_data_coh_state : io_in_0_bits_data_coh_state;
+ assign GEN_5 = 1'h0;
+ assign T_2183 = 1'h0 | io_in_0_valid;
+ assign T_2185 = T_2183 == 1'h0;
+ assign T_2187 = 1'h1 == 1'h0;
+ assign T_2188 = 1'h0 ? T_2187 : 1'h1;
+ assign T_2189 = T_2188 & io_out_ready;
+ assign T_2191 = 1'h1 == 1'h1;
+ assign T_2192 = 1'h0 ? T_2191 : T_2185;
+ assign T_2193 = T_2192 & io_out_ready;
+ assign T_2196 = io_in_0_valid ? 1'h0 : 1'h1;
+ assign T_2197 = 1'h0 ? 1'h1 : T_2196;
+ assign GEN_6 = 1'h1 == T_1714;
+ assign GEN_7 = 1'h1 == T_1714;
+ assign GEN_8 = 1'h1 == T_1714;
+ assign GEN_9 = 1'h1 == T_1714;
+ assign GEN_10 = 1'h1 == T_1714;
+endmodule
+module LockingArbiter(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input [25:0] io_in_0_bits_addr_block,
+ input [1:0] io_in_0_bits_client_xact_id,
+ input [1:0] io_in_0_bits_addr_beat,
+ input io_in_0_bits_is_builtin_type,
+ input [2:0] io_in_0_bits_a_type,
+ input [16:0] io_in_0_bits_union,
+ input [127:0] io_in_0_bits_data,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input [25:0] io_in_1_bits_addr_block,
+ input [1:0] io_in_1_bits_client_xact_id,
+ input [1:0] io_in_1_bits_addr_beat,
+ input io_in_1_bits_is_builtin_type,
+ input [2:0] io_in_1_bits_a_type,
+ input [16:0] io_in_1_bits_union,
+ input [127:0] io_in_1_bits_data,
+ output io_in_2_ready,
+ input io_in_2_valid,
+ input [25:0] io_in_2_bits_addr_block,
+ input [1:0] io_in_2_bits_client_xact_id,
+ input [1:0] io_in_2_bits_addr_beat,
+ input io_in_2_bits_is_builtin_type,
+ input [2:0] io_in_2_bits_a_type,
+ input [16:0] io_in_2_bits_union,
+ input [127:0] io_in_2_bits_data,
+ input io_out_ready,
+ output io_out_valid,
+ output [25:0] io_out_bits_addr_block,
+ output [1:0] io_out_bits_client_xact_id,
+ output [1:0] io_out_bits_addr_beat,
+ output io_out_bits_is_builtin_type,
+ output [2:0] io_out_bits_a_type,
+ output [16:0] io_out_bits_union,
+ output [127:0] io_out_bits_data,
+ output [1:0] io_chosen
+);
+ reg T_852;
+ reg [1:0] T_854;
+ wire [1:0] T_856;
+ wire GEN_0;
+ wire [25:0] GEN_1;
+ wire [1:0] GEN_2;
+ wire [1:0] GEN_3;
+ wire GEN_4;
+ wire [2:0] GEN_5;
+ wire [16:0] GEN_6;
+ wire [127:0] GEN_7;
+ wire GEN_8;
+ wire T_1055;
+ wire T_1057;
+ wire T_1059;
+ wire T_1060;
+ wire T_1062;
+ wire T_1064;
+ wire T_1065;
+ wire T_1066;
+ wire T_1068;
+ wire T_1069;
+ wire T_1070;
+ wire T_1072;
+ wire T_1073;
+ wire T_1074;
+ reg [1:0] T_1076;
+ wire [2:0] T_1078;
+ wire [1:0] T_1079;
+ wire T_1080;
+ wire T_1082;
+ wire [2:0] T_1085_0;
+ wire T_1088;
+ wire T_1090;
+ wire T_1091;
+ wire T_1093;
+ wire T_1095;
+ wire T_1096;
+ wire T_1097;
+ wire T_1099_0;
+ wire T_1099_1;
+ wire T_1099_2;
+ wire [1:0] T_1107;
+ wire [1:0] T_1108;
+ wire T_1110;
+ wire [1:0] T_1114;
+ wire [1:0] choose;
+ wire [1:0] T_1117;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ wire GEN_17;
+ wire GEN_18;
+ wire GEN_19;
+ wire GEN_20;
+ wire GEN_21;
+ wire GEN_22;
+ wire GEN_23;
+ wire GEN_24;
+ assign io_in_0_ready = T_1066;
+ assign io_in_1_ready = T_1070;
+ assign io_in_2_ready = T_1074;
+ assign io_out_valid = GEN_0;
+ assign io_out_bits_addr_block = GEN_1;
+ assign io_out_bits_client_xact_id = GEN_2;
+ assign io_out_bits_addr_beat = GEN_3;
+ assign io_out_bits_is_builtin_type = GEN_4;
+ assign io_out_bits_a_type = GEN_5;
+ assign io_out_bits_union = GEN_6;
+ assign io_out_bits_data = GEN_7;
+ assign io_chosen = T_856;
+ assign T_856 = T_1117;
+ assign GEN_0 = GEN_9 ? io_in_2_valid : GEN_10 ? io_in_1_valid : io_in_0_valid;
+ assign GEN_1 = GEN_11 ? io_in_2_bits_addr_block : GEN_12 ? io_in_1_bits_addr_block : io_in_0_bits_addr_block;
+ assign GEN_2 = GEN_13 ? io_in_2_bits_client_xact_id : GEN_14 ? io_in_1_bits_client_xact_id : io_in_0_bits_client_xact_id;
+ assign GEN_3 = GEN_15 ? io_in_2_bits_addr_beat : GEN_16 ? io_in_1_bits_addr_beat : io_in_0_bits_addr_beat;
+ assign GEN_4 = GEN_17 ? io_in_2_bits_is_builtin_type : GEN_18 ? io_in_1_bits_is_builtin_type : io_in_0_bits_is_builtin_type;
+ assign GEN_5 = GEN_19 ? io_in_2_bits_a_type : GEN_20 ? io_in_1_bits_a_type : io_in_0_bits_a_type;
+ assign GEN_6 = GEN_21 ? io_in_2_bits_union : GEN_22 ? io_in_1_bits_union : io_in_0_bits_union;
+ assign GEN_7 = GEN_23 ? io_in_2_bits_data : GEN_24 ? io_in_1_bits_data : io_in_0_bits_data;
+ assign GEN_8 = 1'h0;
+ assign T_1055 = 1'h0 | io_in_0_valid;
+ assign T_1057 = T_1055 == 1'h0;
+ assign T_1059 = 1'h0 | io_in_0_valid;
+ assign T_1060 = T_1059 | io_in_1_valid;
+ assign T_1062 = T_1060 == 1'h0;
+ assign T_1064 = T_854 == 1'h0;
+ assign T_1065 = T_852 ? T_1064 : 1'h1;
+ assign T_1066 = T_1065 & io_out_ready;
+ assign T_1068 = T_854 == 1'h1;
+ assign T_1069 = T_852 ? T_1068 : T_1057;
+ assign T_1070 = T_1069 & io_out_ready;
+ assign T_1072 = T_854 == 2'h2;
+ assign T_1073 = T_852 ? T_1072 : T_1062;
+ assign T_1074 = T_1073 & io_out_ready;
+ assign T_1078 = T_1076 + 1'h1;
+ assign T_1079 = T_1078[1:0];
+ assign T_1080 = io_out_ready & io_out_valid;
+ assign T_1082 = 1'h1 & io_out_bits_is_builtin_type;
+ assign T_1085_0 = 3'h3;
+ assign T_1088 = T_1085_0 == io_out_bits_a_type;
+ assign T_1090 = 1'h0 | T_1088;
+ assign T_1091 = T_1082 & T_1090;
+ assign T_1093 = T_852 == 1'h0;
+ assign T_1095 = io_in_0_ready & io_in_0_valid;
+ assign T_1096 = io_in_1_ready & io_in_1_valid;
+ assign T_1097 = io_in_2_ready & io_in_2_valid;
+ assign T_1099_0 = T_1095;
+ assign T_1099_1 = T_1096;
+ assign T_1099_2 = T_1097;
+ assign T_1107 = T_1099_1 ? 1'h1 : 2'h2;
+ assign T_1108 = T_1099_0 ? 1'h0 : T_1107;
+ assign T_1110 = T_1079 == 1'h0;
+ assign T_1114 = io_in_1_valid ? 1'h1 : 2'h2;
+ assign choose = io_in_0_valid ? 1'h0 : T_1114;
+ assign T_1117 = T_852 ? T_854 : choose;
+ assign GEN_9 = 2'h2 == T_856;
+ assign GEN_10 = 1'h1 == T_856;
+ assign GEN_11 = 2'h2 == T_856;
+ assign GEN_12 = 1'h1 == T_856;
+ assign GEN_13 = 2'h2 == T_856;
+ assign GEN_14 = 1'h1 == T_856;
+ assign GEN_15 = 2'h2 == T_856;
+ assign GEN_16 = 1'h1 == T_856;
+ assign GEN_17 = 2'h2 == T_856;
+ assign GEN_18 = 1'h1 == T_856;
+ assign GEN_19 = 2'h2 == T_856;
+ assign GEN_20 = 1'h1 == T_856;
+ assign GEN_21 = 2'h2 == T_856;
+ assign GEN_22 = 1'h1 == T_856;
+ assign GEN_23 = 2'h2 == T_856;
+ assign GEN_24 = 1'h1 == T_856;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_852 = {1{$random}};
+ T_854 = {1{$random}};
+ T_1076 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ T_852 <= 1'h0;
+ end else begin
+ if(T_1080) begin
+ if(T_1110) begin
+ T_852 <= 1'h0;
+ end else begin
+ if(T_1091) begin
+ if(T_1093) begin
+ T_852 <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_854 <= 2'h2;
+ end else begin
+ if(T_1080) begin
+ if(T_1091) begin
+ if(T_1093) begin
+ T_854 <= T_1108;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_1076 <= 2'h0;
+ end else begin
+ if(T_1080) begin
+ if(T_1091) begin
+ T_1076 <= T_1079;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module Arbiter_95(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input [1:0] io_in_0_bits_addr_beat,
+ input [25:0] io_in_0_bits_addr_block,
+ input [1:0] io_in_0_bits_client_xact_id,
+ input io_in_0_bits_voluntary,
+ input [2:0] io_in_0_bits_r_type,
+ input [127:0] io_in_0_bits_data,
+ input [3:0] io_in_0_bits_way_en,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input [1:0] io_in_1_bits_addr_beat,
+ input [25:0] io_in_1_bits_addr_block,
+ input [1:0] io_in_1_bits_client_xact_id,
+ input io_in_1_bits_voluntary,
+ input [2:0] io_in_1_bits_r_type,
+ input [127:0] io_in_1_bits_data,
+ input [3:0] io_in_1_bits_way_en,
+ input io_out_ready,
+ output io_out_valid,
+ output [1:0] io_out_bits_addr_beat,
+ output [25:0] io_out_bits_addr_block,
+ output [1:0] io_out_bits_client_xact_id,
+ output io_out_bits_voluntary,
+ output [2:0] io_out_bits_r_type,
+ output [127:0] io_out_bits_data,
+ output [3:0] io_out_bits_way_en,
+ output io_chosen
+);
+ wire T_724;
+ wire GEN_0;
+ wire [1:0] GEN_1;
+ wire [25:0] GEN_2;
+ wire [1:0] GEN_3;
+ wire GEN_4;
+ wire [2:0] GEN_5;
+ wire [127:0] GEN_6;
+ wire [3:0] GEN_7;
+ wire GEN_8;
+ wire T_923;
+ wire T_925;
+ wire T_927;
+ wire T_928;
+ wire T_929;
+ wire T_931;
+ wire T_932;
+ wire T_933;
+ wire T_936;
+ wire T_937;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ assign io_in_0_ready = T_929;
+ assign io_in_1_ready = T_933;
+ assign io_out_valid = GEN_0;
+ assign io_out_bits_addr_beat = GEN_1;
+ assign io_out_bits_addr_block = GEN_2;
+ assign io_out_bits_client_xact_id = GEN_3;
+ assign io_out_bits_voluntary = GEN_4;
+ assign io_out_bits_r_type = GEN_5;
+ assign io_out_bits_data = GEN_6;
+ assign io_out_bits_way_en = GEN_7;
+ assign io_chosen = T_724;
+ assign T_724 = T_937;
+ assign GEN_0 = GEN_9 ? io_in_1_valid : io_in_0_valid;
+ assign GEN_1 = GEN_10 ? io_in_1_bits_addr_beat : io_in_0_bits_addr_beat;
+ assign GEN_2 = GEN_11 ? io_in_1_bits_addr_block : io_in_0_bits_addr_block;
+ assign GEN_3 = GEN_12 ? io_in_1_bits_client_xact_id : io_in_0_bits_client_xact_id;
+ assign GEN_4 = GEN_13 ? io_in_1_bits_voluntary : io_in_0_bits_voluntary;
+ assign GEN_5 = GEN_14 ? io_in_1_bits_r_type : io_in_0_bits_r_type;
+ assign GEN_6 = GEN_15 ? io_in_1_bits_data : io_in_0_bits_data;
+ assign GEN_7 = GEN_16 ? io_in_1_bits_way_en : io_in_0_bits_way_en;
+ assign GEN_8 = 1'h0;
+ assign T_923 = 1'h0 | io_in_0_valid;
+ assign T_925 = T_923 == 1'h0;
+ assign T_927 = 1'h1 == 1'h0;
+ assign T_928 = 1'h0 ? T_927 : 1'h1;
+ assign T_929 = T_928 & io_out_ready;
+ assign T_931 = 1'h1 == 1'h1;
+ assign T_932 = 1'h0 ? T_931 : T_925;
+ assign T_933 = T_932 & io_out_ready;
+ assign T_936 = io_in_0_valid ? 1'h0 : 1'h1;
+ assign T_937 = 1'h0 ? 1'h1 : T_936;
+ assign GEN_9 = 1'h1 == T_724;
+ assign GEN_10 = 1'h1 == T_724;
+ assign GEN_11 = 1'h1 == T_724;
+ assign GEN_12 = 1'h1 == T_724;
+ assign GEN_13 = 1'h1 == T_724;
+ assign GEN_14 = 1'h1 == T_724;
+ assign GEN_15 = 1'h1 == T_724;
+ assign GEN_16 = 1'h1 == T_724;
+endmodule
+module Arbiter_96(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input [39:0] io_in_0_bits_addr,
+ input [8:0] io_in_0_bits_tag,
+ input [4:0] io_in_0_bits_cmd,
+ input [2:0] io_in_0_bits_typ,
+ input io_in_0_bits_kill,
+ input io_in_0_bits_phys,
+ input [4:0] io_in_0_bits_sdq_id,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input [39:0] io_in_1_bits_addr,
+ input [8:0] io_in_1_bits_tag,
+ input [4:0] io_in_1_bits_cmd,
+ input [2:0] io_in_1_bits_typ,
+ input io_in_1_bits_kill,
+ input io_in_1_bits_phys,
+ input [4:0] io_in_1_bits_sdq_id,
+ input io_out_ready,
+ output io_out_valid,
+ output [39:0] io_out_bits_addr,
+ output [8:0] io_out_bits_tag,
+ output [4:0] io_out_bits_cmd,
+ output [2:0] io_out_bits_typ,
+ output io_out_bits_kill,
+ output io_out_bits_phys,
+ output [4:0] io_out_bits_sdq_id,
+ output io_chosen
+);
+ wire T_1230;
+ wire GEN_0;
+ wire [39:0] GEN_1;
+ wire [8:0] GEN_2;
+ wire [4:0] GEN_3;
+ wire [2:0] GEN_4;
+ wire GEN_5;
+ wire GEN_6;
+ wire [4:0] GEN_7;
+ wire GEN_8;
+ wire T_1567;
+ wire T_1569;
+ wire T_1571;
+ wire T_1572;
+ wire T_1573;
+ wire T_1575;
+ wire T_1576;
+ wire T_1577;
+ wire T_1580;
+ wire T_1581;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ wire GEN_15;
+ wire GEN_16;
+ assign io_in_0_ready = T_1573;
+ assign io_in_1_ready = T_1577;
+ assign io_out_valid = GEN_0;
+ assign io_out_bits_addr = GEN_1;
+ assign io_out_bits_tag = GEN_2;
+ assign io_out_bits_cmd = GEN_3;
+ assign io_out_bits_typ = GEN_4;
+ assign io_out_bits_kill = GEN_5;
+ assign io_out_bits_phys = GEN_6;
+ assign io_out_bits_sdq_id = GEN_7;
+ assign io_chosen = T_1230;
+ assign T_1230 = T_1581;
+ assign GEN_0 = GEN_9 ? io_in_1_valid : io_in_0_valid;
+ assign GEN_1 = GEN_10 ? io_in_1_bits_addr : io_in_0_bits_addr;
+ assign GEN_2 = GEN_11 ? io_in_1_bits_tag : io_in_0_bits_tag;
+ assign GEN_3 = GEN_12 ? io_in_1_bits_cmd : io_in_0_bits_cmd;
+ assign GEN_4 = GEN_13 ? io_in_1_bits_typ : io_in_0_bits_typ;
+ assign GEN_5 = GEN_14 ? io_in_1_bits_kill : io_in_0_bits_kill;
+ assign GEN_6 = GEN_15 ? io_in_1_bits_phys : io_in_0_bits_phys;
+ assign GEN_7 = GEN_16 ? io_in_1_bits_sdq_id : io_in_0_bits_sdq_id;
+ assign GEN_8 = 1'h0;
+ assign T_1567 = 1'h0 | io_in_0_valid;
+ assign T_1569 = T_1567 == 1'h0;
+ assign T_1571 = 1'h1 == 1'h0;
+ assign T_1572 = 1'h0 ? T_1571 : 1'h1;
+ assign T_1573 = T_1572 & io_out_ready;
+ assign T_1575 = 1'h1 == 1'h1;
+ assign T_1576 = 1'h0 ? T_1575 : T_1569;
+ assign T_1577 = T_1576 & io_out_ready;
+ assign T_1580 = io_in_0_valid ? 1'h0 : 1'h1;
+ assign T_1581 = 1'h0 ? 1'h1 : T_1580;
+ assign GEN_9 = 1'h1 == T_1230;
+ assign GEN_10 = 1'h1 == T_1230;
+ assign GEN_11 = 1'h1 == T_1230;
+ assign GEN_12 = 1'h1 == T_1230;
+ assign GEN_13 = 1'h1 == T_1230;
+ assign GEN_14 = 1'h1 == T_1230;
+ assign GEN_15 = 1'h1 == T_1230;
+ assign GEN_16 = 1'h1 == T_1230;
+endmodule
+module Arbiter_97(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input io_in_0_bits,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input io_in_1_bits,
+ input io_out_ready,
+ output io_out_valid,
+ output io_out_bits,
+ output io_chosen
+);
+ wire T_64;
+ wire GEN_0;
+ wire GEN_1;
+ wire GEN_2;
+ wire T_83;
+ wire T_85;
+ wire T_87;
+ wire T_88;
+ wire T_89;
+ wire T_91;
+ wire T_92;
+ wire T_93;
+ wire T_96;
+ wire T_97;
+ wire GEN_3;
+ wire GEN_4;
+ assign io_in_0_ready = T_89;
+ assign io_in_1_ready = T_93;
+ assign io_out_valid = GEN_0;
+ assign io_out_bits = GEN_1;
+ assign io_chosen = T_64;
+ assign T_64 = T_97;
+ assign GEN_0 = GEN_3 ? io_in_1_valid : io_in_0_valid;
+ assign GEN_1 = GEN_4 ? io_in_1_bits : io_in_0_bits;
+ assign GEN_2 = 1'h0;
+ assign T_83 = 1'h0 | io_in_0_valid;
+ assign T_85 = T_83 == 1'h0;
+ assign T_87 = 1'h1 == 1'h0;
+ assign T_88 = 1'h0 ? T_87 : 1'h1;
+ assign T_89 = T_88 & io_out_ready;
+ assign T_91 = 1'h1 == 1'h1;
+ assign T_92 = 1'h0 ? T_91 : T_85;
+ assign T_93 = T_92 & io_out_ready;
+ assign T_96 = io_in_0_valid ? 1'h0 : 1'h1;
+ assign T_97 = 1'h0 ? 1'h1 : T_96;
+ assign GEN_3 = 1'h1 == T_64;
+ assign GEN_4 = 1'h1 == T_64;
+endmodule
+module Queue_98(
+ input clk,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [39:0] io_enq_bits_addr,
+ input [8:0] io_enq_bits_tag,
+ input [4:0] io_enq_bits_cmd,
+ input [2:0] io_enq_bits_typ,
+ input io_enq_bits_kill,
+ input io_enq_bits_phys,
+ input [4:0] io_enq_bits_sdq_id,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [39:0] io_deq_bits_addr,
+ output [8:0] io_deq_bits_tag,
+ output [4:0] io_deq_bits_cmd,
+ output [2:0] io_deq_bits_typ,
+ output io_deq_bits_kill,
+ output io_deq_bits_phys,
+ output [4:0] io_deq_bits_sdq_id,
+ output [4:0] io_count
+);
+ reg [39:0] ram_addr [0:15];
+ wire [39:0] ram_addr_T_607_data;
+ wire [3:0] ram_addr_T_607_addr;
+ wire ram_addr_T_607_en;
+ wire ram_addr_T_607_clk;
+ wire [39:0] ram_addr_T_524_data;
+ wire [3:0] ram_addr_T_524_addr;
+ wire ram_addr_T_524_mask;
+ wire ram_addr_T_524_en;
+ wire ram_addr_T_524_clk;
+ reg [8:0] ram_tag [0:15];
+ wire [8:0] ram_tag_T_607_data;
+ wire [3:0] ram_tag_T_607_addr;
+ wire ram_tag_T_607_en;
+ wire ram_tag_T_607_clk;
+ wire [8:0] ram_tag_T_524_data;
+ wire [3:0] ram_tag_T_524_addr;
+ wire ram_tag_T_524_mask;
+ wire ram_tag_T_524_en;
+ wire ram_tag_T_524_clk;
+ reg [4:0] ram_cmd [0:15];
+ wire [4:0] ram_cmd_T_607_data;
+ wire [3:0] ram_cmd_T_607_addr;
+ wire ram_cmd_T_607_en;
+ wire ram_cmd_T_607_clk;
+ wire [4:0] ram_cmd_T_524_data;
+ wire [3:0] ram_cmd_T_524_addr;
+ wire ram_cmd_T_524_mask;
+ wire ram_cmd_T_524_en;
+ wire ram_cmd_T_524_clk;
+ reg [2:0] ram_typ [0:15];
+ wire [2:0] ram_typ_T_607_data;
+ wire [3:0] ram_typ_T_607_addr;
+ wire ram_typ_T_607_en;
+ wire ram_typ_T_607_clk;
+ wire [2:0] ram_typ_T_524_data;
+ wire [3:0] ram_typ_T_524_addr;
+ wire ram_typ_T_524_mask;
+ wire ram_typ_T_524_en;
+ wire ram_typ_T_524_clk;
+ reg ram_kill [0:15];
+ wire ram_kill_T_607_data;
+ wire [3:0] ram_kill_T_607_addr;
+ wire ram_kill_T_607_en;
+ wire ram_kill_T_607_clk;
+ wire ram_kill_T_524_data;
+ wire [3:0] ram_kill_T_524_addr;
+ wire ram_kill_T_524_mask;
+ wire ram_kill_T_524_en;
+ wire ram_kill_T_524_clk;
+ reg ram_phys [0:15];
+ wire ram_phys_T_607_data;
+ wire [3:0] ram_phys_T_607_addr;
+ wire ram_phys_T_607_en;
+ wire ram_phys_T_607_clk;
+ wire ram_phys_T_524_data;
+ wire [3:0] ram_phys_T_524_addr;
+ wire ram_phys_T_524_mask;
+ wire ram_phys_T_524_en;
+ wire ram_phys_T_524_clk;
+ reg [4:0] ram_sdq_id [0:15];
+ wire [4:0] ram_sdq_id_T_607_data;
+ wire [3:0] ram_sdq_id_T_607_addr;
+ wire ram_sdq_id_T_607_en;
+ wire ram_sdq_id_T_607_clk;
+ wire [4:0] ram_sdq_id_T_524_data;
+ wire [3:0] ram_sdq_id_T_524_addr;
+ wire ram_sdq_id_T_524_mask;
+ wire ram_sdq_id_T_524_en;
+ wire ram_sdq_id_T_524_clk;
+ reg [3:0] T_503;
+ reg [3:0] T_505;
+ reg maybe_full;
+ wire ptr_match;
+ wire T_510;
+ wire empty;
+ wire full;
+ wire maybe_flow;
+ wire do_flow;
+ wire T_516;
+ wire T_518;
+ wire do_enq;
+ wire T_520;
+ wire T_522;
+ wire do_deq;
+ wire T_579;
+ wire T_581;
+ wire [4:0] T_584;
+ wire [3:0] T_585;
+ wire [3:0] T_586;
+ wire T_588;
+ wire T_590;
+ wire [4:0] T_593;
+ wire [3:0] T_594;
+ wire [3:0] T_595;
+ wire T_596;
+ wire T_598;
+ wire T_600;
+ wire T_601;
+ wire T_603;
+ wire T_605;
+ wire T_606;
+ wire [39:0] T_661_addr;
+ wire [8:0] T_661_tag;
+ wire [4:0] T_661_cmd;
+ wire [2:0] T_661_typ;
+ wire T_661_kill;
+ wire T_661_phys;
+ wire [4:0] T_661_sdq_id;
+ wire [4:0] T_715;
+ wire [3:0] ptr_diff;
+ wire T_717;
+ wire [4:0] T_718;
+ assign io_enq_ready = T_606;
+ assign io_deq_valid = T_601;
+ assign io_deq_bits_addr = T_661_addr;
+ assign io_deq_bits_tag = T_661_tag;
+ assign io_deq_bits_cmd = T_661_cmd;
+ assign io_deq_bits_typ = T_661_typ;
+ assign io_deq_bits_kill = T_661_kill;
+ assign io_deq_bits_phys = T_661_phys;
+ assign io_deq_bits_sdq_id = T_661_sdq_id;
+ assign io_count = T_718;
+ assign ram_addr_T_607_addr = T_505;
+ assign ram_addr_T_607_en = 1'h1;
+ assign ram_addr_T_607_clk = clk;
+ assign ram_addr_T_607_data = ram_addr[ram_addr_T_607_addr];
+ assign ram_addr_T_524_data = io_enq_bits_addr;
+ assign ram_addr_T_524_addr = T_503;
+ assign ram_addr_T_524_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_addr_T_524_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_addr_T_524_clk = clk;
+ assign ram_tag_T_607_addr = T_505;
+ assign ram_tag_T_607_en = 1'h1;
+ assign ram_tag_T_607_clk = clk;
+ assign ram_tag_T_607_data = ram_tag[ram_tag_T_607_addr];
+ assign ram_tag_T_524_data = io_enq_bits_tag;
+ assign ram_tag_T_524_addr = T_503;
+ assign ram_tag_T_524_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_tag_T_524_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_tag_T_524_clk = clk;
+ assign ram_cmd_T_607_addr = T_505;
+ assign ram_cmd_T_607_en = 1'h1;
+ assign ram_cmd_T_607_clk = clk;
+ assign ram_cmd_T_607_data = ram_cmd[ram_cmd_T_607_addr];
+ assign ram_cmd_T_524_data = io_enq_bits_cmd;
+ assign ram_cmd_T_524_addr = T_503;
+ assign ram_cmd_T_524_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_cmd_T_524_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_cmd_T_524_clk = clk;
+ assign ram_typ_T_607_addr = T_505;
+ assign ram_typ_T_607_en = 1'h1;
+ assign ram_typ_T_607_clk = clk;
+ assign ram_typ_T_607_data = ram_typ[ram_typ_T_607_addr];
+ assign ram_typ_T_524_data = io_enq_bits_typ;
+ assign ram_typ_T_524_addr = T_503;
+ assign ram_typ_T_524_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_typ_T_524_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_typ_T_524_clk = clk;
+ assign ram_kill_T_607_addr = T_505;
+ assign ram_kill_T_607_en = 1'h1;
+ assign ram_kill_T_607_clk = clk;
+ assign ram_kill_T_607_data = ram_kill[ram_kill_T_607_addr];
+ assign ram_kill_T_524_data = io_enq_bits_kill;
+ assign ram_kill_T_524_addr = T_503;
+ assign ram_kill_T_524_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_kill_T_524_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_kill_T_524_clk = clk;
+ assign ram_phys_T_607_addr = T_505;
+ assign ram_phys_T_607_en = 1'h1;
+ assign ram_phys_T_607_clk = clk;
+ assign ram_phys_T_607_data = ram_phys[ram_phys_T_607_addr];
+ assign ram_phys_T_524_data = io_enq_bits_phys;
+ assign ram_phys_T_524_addr = T_503;
+ assign ram_phys_T_524_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_phys_T_524_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_phys_T_524_clk = clk;
+ assign ram_sdq_id_T_607_addr = T_505;
+ assign ram_sdq_id_T_607_en = 1'h1;
+ assign ram_sdq_id_T_607_clk = clk;
+ assign ram_sdq_id_T_607_data = ram_sdq_id[ram_sdq_id_T_607_addr];
+ assign ram_sdq_id_T_524_data = io_enq_bits_sdq_id;
+ assign ram_sdq_id_T_524_addr = T_503;
+ assign ram_sdq_id_T_524_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_sdq_id_T_524_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_sdq_id_T_524_clk = clk;
+ assign ptr_match = T_503 == T_505;
+ assign T_510 = maybe_full == 1'h0;
+ assign empty = ptr_match & T_510;
+ assign full = ptr_match & maybe_full;
+ assign maybe_flow = 1'h0 & empty;
+ assign do_flow = maybe_flow & io_deq_ready;
+ assign T_516 = io_enq_ready & io_enq_valid;
+ assign T_518 = do_flow == 1'h0;
+ assign do_enq = T_516 & T_518;
+ assign T_520 = io_deq_ready & io_deq_valid;
+ assign T_522 = do_flow == 1'h0;
+ assign do_deq = T_520 & T_522;
+ assign T_579 = T_503 == 4'hf;
+ assign T_581 = 1'h0 & T_579;
+ assign T_584 = T_503 + 1'h1;
+ assign T_585 = T_584[3:0];
+ assign T_586 = T_581 ? 1'h0 : T_585;
+ assign T_588 = T_505 == 4'hf;
+ assign T_590 = 1'h0 & T_588;
+ assign T_593 = T_505 + 1'h1;
+ assign T_594 = T_593[3:0];
+ assign T_595 = T_590 ? 1'h0 : T_594;
+ assign T_596 = do_enq != do_deq;
+ assign T_598 = empty == 1'h0;
+ assign T_600 = 1'h0 & io_enq_valid;
+ assign T_601 = T_598 | T_600;
+ assign T_603 = full == 1'h0;
+ assign T_605 = 1'h0 & io_deq_ready;
+ assign T_606 = T_603 | T_605;
+ assign T_661_addr = maybe_flow ? io_enq_bits_addr : ram_addr_T_607_data;
+ assign T_661_tag = maybe_flow ? io_enq_bits_tag : ram_tag_T_607_data;
+ assign T_661_cmd = maybe_flow ? io_enq_bits_cmd : ram_cmd_T_607_data;
+ assign T_661_typ = maybe_flow ? io_enq_bits_typ : ram_typ_T_607_data;
+ assign T_661_kill = maybe_flow ? io_enq_bits_kill : ram_kill_T_607_data;
+ assign T_661_phys = maybe_flow ? io_enq_bits_phys : ram_phys_T_607_data;
+ assign T_661_sdq_id = maybe_flow ? io_enq_bits_sdq_id : ram_sdq_id_T_607_data;
+ assign T_715 = T_503 - T_505;
+ assign ptr_diff = T_715[3:0];
+ assign T_717 = maybe_full & ptr_match;
+ assign T_718 = {T_717,ptr_diff};
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ for (initvar = 0; initvar < 16; initvar = initvar+1)
+ ram_addr[initvar] = {2{$random}};
+ for (initvar = 0; initvar < 16; initvar = initvar+1)
+ ram_tag[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 16; initvar = initvar+1)
+ ram_cmd[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 16; initvar = initvar+1)
+ ram_typ[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 16; initvar = initvar+1)
+ ram_kill[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 16; initvar = initvar+1)
+ ram_phys[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 16; initvar = initvar+1)
+ ram_sdq_id[initvar] = {1{$random}};
+ T_503 = {1{$random}};
+ T_505 = {1{$random}};
+ maybe_full = {1{$random}};
+ end
+`endif
+ always @(posedge ram_addr_T_524_clk) begin
+ if(ram_addr_T_524_en & ram_addr_T_524_mask) begin
+ ram_addr[ram_addr_T_524_addr] <= ram_addr_T_524_data;
+ end
+ end
+ always @(posedge ram_tag_T_524_clk) begin
+ if(ram_tag_T_524_en & ram_tag_T_524_mask) begin
+ ram_tag[ram_tag_T_524_addr] <= ram_tag_T_524_data;
+ end
+ end
+ always @(posedge ram_cmd_T_524_clk) begin
+ if(ram_cmd_T_524_en & ram_cmd_T_524_mask) begin
+ ram_cmd[ram_cmd_T_524_addr] <= ram_cmd_T_524_data;
+ end
+ end
+ always @(posedge ram_typ_T_524_clk) begin
+ if(ram_typ_T_524_en & ram_typ_T_524_mask) begin
+ ram_typ[ram_typ_T_524_addr] <= ram_typ_T_524_data;
+ end
+ end
+ always @(posedge ram_kill_T_524_clk) begin
+ if(ram_kill_T_524_en & ram_kill_T_524_mask) begin
+ ram_kill[ram_kill_T_524_addr] <= ram_kill_T_524_data;
+ end
+ end
+ always @(posedge ram_phys_T_524_clk) begin
+ if(ram_phys_T_524_en & ram_phys_T_524_mask) begin
+ ram_phys[ram_phys_T_524_addr] <= ram_phys_T_524_data;
+ end
+ end
+ always @(posedge ram_sdq_id_T_524_clk) begin
+ if(ram_sdq_id_T_524_en & ram_sdq_id_T_524_mask) begin
+ ram_sdq_id[ram_sdq_id_T_524_addr] <= ram_sdq_id_T_524_data;
+ end
+ end
+ always @(posedge clk) begin
+ if(reset) begin
+ T_503 <= 4'h0;
+ end else begin
+ if(do_enq) begin
+ T_503 <= T_586;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_505 <= 4'h0;
+ end else begin
+ if(do_deq) begin
+ T_505 <= T_595;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ maybe_full <= 1'h0;
+ end else begin
+ if(T_596) begin
+ maybe_full <= do_enq;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module MSHR(
+ input clk,
+ input reset,
+ input io_req_pri_val,
+ output io_req_pri_rdy,
+ input io_req_sec_val,
+ output io_req_sec_rdy,
+ input [39:0] io_req_bits_addr,
+ input [8:0] io_req_bits_tag,
+ input [4:0] io_req_bits_cmd,
+ input [2:0] io_req_bits_typ,
+ input io_req_bits_kill,
+ input io_req_bits_phys,
+ input [4:0] io_req_bits_sdq_id,
+ input io_req_bits_tag_match,
+ input [19:0] io_req_bits_old_meta_tag,
+ input [1:0] io_req_bits_old_meta_coh_state,
+ input [3:0] io_req_bits_way_en,
+ output io_idx_match,
+ output [19:0] io_tag,
+ input io_mem_req_ready,
+ output io_mem_req_valid,
+ output [25:0] io_mem_req_bits_addr_block,
+ output [1:0] io_mem_req_bits_client_xact_id,
+ output [1:0] io_mem_req_bits_addr_beat,
+ output io_mem_req_bits_is_builtin_type,
+ output [2:0] io_mem_req_bits_a_type,
+ output [16:0] io_mem_req_bits_union,
+ output [127:0] io_mem_req_bits_data,
+ output [3:0] io_refill_way_en,
+ output [11:0] io_refill_addr,
+ input io_meta_read_ready,
+ output io_meta_read_valid,
+ output [5:0] io_meta_read_bits_idx,
+ output [19:0] io_meta_read_bits_tag,
+ input io_meta_write_ready,
+ output io_meta_write_valid,
+ output [5:0] io_meta_write_bits_idx,
+ output [3:0] io_meta_write_bits_way_en,
+ output [19:0] io_meta_write_bits_data_tag,
+ output [1:0] io_meta_write_bits_data_coh_state,
+ input io_replay_ready,
+ output io_replay_valid,
+ output [39:0] io_replay_bits_addr,
+ output [8:0] io_replay_bits_tag,
+ output [4:0] io_replay_bits_cmd,
+ output [2:0] io_replay_bits_typ,
+ output io_replay_bits_kill,
+ output io_replay_bits_phys,
+ output [4:0] io_replay_bits_sdq_id,
+ input io_mem_grant_valid,
+ input [1:0] io_mem_grant_bits_addr_beat,
+ input [1:0] io_mem_grant_bits_client_xact_id,
+ input [3:0] io_mem_grant_bits_manager_xact_id,
+ input io_mem_grant_bits_is_builtin_type,
+ input [3:0] io_mem_grant_bits_g_type,
+ input [127:0] io_mem_grant_bits_data,
+ input io_wb_req_ready,
+ output io_wb_req_valid,
+ output [1:0] io_wb_req_bits_addr_beat,
+ output [25:0] io_wb_req_bits_addr_block,
+ output [1:0] io_wb_req_bits_client_xact_id,
+ output io_wb_req_bits_voluntary,
+ output [2:0] io_wb_req_bits_r_type,
+ output [127:0] io_wb_req_bits_data,
+ output [3:0] io_wb_req_bits_way_en,
+ output io_probe_rdy
+);
+ reg [3:0] state;
+ wire [1:0] T_1277_state;
+ reg [1:0] new_coh_state_state;
+ reg [39:0] req_addr;
+ reg [8:0] req_tag;
+ reg [4:0] req_cmd;
+ reg [2:0] req_typ;
+ reg req_kill;
+ reg req_phys;
+ reg [4:0] req_sdq_id;
+ reg req_tag_match;
+ reg [19:0] req_old_meta_tag;
+ reg [1:0] req_old_meta_coh_state;
+ reg [3:0] req_way_en;
+ wire [5:0] req_idx;
+ wire [5:0] T_1586;
+ wire idx_match;
+ wire T_1588;
+ wire T_1589;
+ wire T_1590;
+ wire T_1591;
+ wire T_1592;
+ wire T_1593;
+ wire T_1594;
+ wire T_1595;
+ wire T_1596;
+ wire T_1597;
+ wire T_1598;
+ wire T_1599;
+ wire T_1600;
+ wire T_1601;
+ wire T_1602;
+ wire T_1603;
+ wire T_1604;
+ wire T_1605;
+ wire T_1606;
+ wire T_1607;
+ wire T_1608;
+ wire T_1609;
+ wire T_1611;
+ wire cmd_requires_second_acquire;
+ wire [1:0] states_before_refill_0;
+ wire [1:0] states_before_refill_1;
+ wire [1:0] states_before_refill_2;
+ wire T_1619;
+ wire T_1620;
+ wire T_1621;
+ wire T_1623;
+ wire T_1624;
+ wire T_1625;
+ wire [2:0] T_1627_0;
+ wire [2:0] T_1627_1;
+ wire T_1631;
+ wire T_1632;
+ wire T_1634;
+ wire T_1635;
+ wire T_1637;
+ wire T_1638;
+ wire T_1639;
+ wire sec_rdy;
+ wire [2:0] T_1644_0;
+ wire T_1647;
+ wire T_1649;
+ wire T_1651_0;
+ wire T_1651_1;
+ wire T_1655;
+ wire T_1656;
+ wire T_1658;
+ wire T_1659;
+ wire T_1660;
+ wire gnt_multi_data;
+ wire T_1662;
+ reg [1:0] refill_cnt;
+ wire T_1666;
+ wire T_1668;
+ wire [2:0] T_1671;
+ wire [1:0] T_1672;
+ wire [1:0] T_1673;
+ wire refill_count_done;
+ wire T_1676;
+ wire T_1677;
+ wire refill_done;
+ wire rpq_clk;
+ wire rpq_reset;
+ wire rpq_io_enq_ready;
+ wire rpq_io_enq_valid;
+ wire [39:0] rpq_io_enq_bits_addr;
+ wire [8:0] rpq_io_enq_bits_tag;
+ wire [4:0] rpq_io_enq_bits_cmd;
+ wire [2:0] rpq_io_enq_bits_typ;
+ wire rpq_io_enq_bits_kill;
+ wire rpq_io_enq_bits_phys;
+ wire [4:0] rpq_io_enq_bits_sdq_id;
+ wire rpq_io_deq_ready;
+ wire rpq_io_deq_valid;
+ wire [39:0] rpq_io_deq_bits_addr;
+ wire [8:0] rpq_io_deq_bits_tag;
+ wire [4:0] rpq_io_deq_bits_cmd;
+ wire [2:0] rpq_io_deq_bits_typ;
+ wire rpq_io_deq_bits_kill;
+ wire rpq_io_deq_bits_phys;
+ wire [4:0] rpq_io_deq_bits_sdq_id;
+ wire [4:0] rpq_io_count;
+ wire T_1734;
+ wire T_1735;
+ wire T_1736;
+ wire T_1737;
+ wire T_1738;
+ wire T_1739;
+ wire T_1741;
+ wire T_1742;
+ wire T_1743;
+ wire T_1744;
+ wire T_1745;
+ wire T_1746;
+ wire T_1747;
+ wire T_1748;
+ wire T_1749;
+ wire T_1750;
+ wire T_1751;
+ wire T_1752;
+ wire T_1753;
+ wire [1:0] T_1754;
+ wire T_1755;
+ wire [1:0] T_1756;
+ wire T_1757;
+ wire [1:0] T_1758;
+ wire T_1759;
+ wire [1:0] T_1760;
+ wire [1:0] T_1761;
+ wire [1:0] coh_on_grant_state;
+ wire T_1812;
+ wire T_1813;
+ wire T_1814;
+ wire T_1815;
+ wire T_1816;
+ wire T_1817;
+ wire T_1818;
+ wire [1:0] T_1819;
+ wire [1:0] coh_on_hit_state;
+ wire T_1870;
+ wire T_1872;
+ wire T_1873;
+ wire T_1874;
+ wire T_1875;
+ wire T_1876;
+ wire T_1877;
+ wire T_1878;
+ wire T_1879;
+ wire T_1880;
+ wire T_1881;
+ wire T_1882;
+ wire T_1883;
+ wire T_1886;
+ wire [1:0] T_1887;
+ wire T_1888;
+ wire T_1889;
+ wire T_1890;
+ wire T_1891;
+ wire T_1892;
+ wire T_1893;
+ wire T_1894;
+ wire T_1895;
+ wire T_1896;
+ wire T_1897;
+ wire T_1898;
+ wire T_1899;
+ wire T_1900;
+ wire [1:0] T_1902_0;
+ wire [1:0] T_1902_1;
+ wire T_1906;
+ wire T_1907;
+ wire T_1909;
+ wire T_1910;
+ wire [1:0] T_1912_0;
+ wire [1:0] T_1912_1;
+ wire [1:0] T_1912_2;
+ wire T_1917;
+ wire T_1918;
+ wire T_1919;
+ wire T_1921;
+ wire T_1922;
+ wire T_1923;
+ wire T_1924;
+ wire T_1926;
+ wire T_1928;
+ wire [1:0] T_1930_0;
+ wire T_1933;
+ wire T_1935;
+ wire [1:0] T_1936;
+ wire T_1937;
+ wire T_1938;
+ wire [7:0] T_1939;
+ wire [11:0] T_1940;
+ wire [27:0] T_1941;
+ wire T_1942;
+ wire T_1943;
+ reg [1:0] meta_hazard;
+ wire T_1947;
+ wire [2:0] T_1949;
+ wire [1:0] T_1950;
+ wire T_1951;
+ wire T_1954;
+ wire T_1955;
+ wire T_1956;
+ wire T_1957;
+ wire T_1959;
+ wire T_1960;
+ wire T_1961;
+ wire T_1963;
+ wire T_1965;
+ wire T_1966;
+ wire T_1967;
+ wire T_1968;
+ wire T_1969;
+ wire T_1970;
+ wire T_1971;
+ wire [1:0] T_1973_0;
+ wire [1:0] T_1973_1;
+ wire T_1977;
+ wire T_1978;
+ wire T_1980;
+ wire T_1981;
+ wire [1:0] T_1982;
+ wire T_1983;
+ wire [1:0] T_1984;
+ wire T_1985;
+ wire [1:0] T_1986;
+ wire T_1987;
+ wire [1:0] T_1988;
+ wire T_1989;
+ wire [1:0] T_1990;
+ wire [1:0] T_2016_state;
+ wire [1:0] T_2041_state;
+ wire T_2066;
+ wire [25:0] T_2068;
+ wire [1:0] T_2073_0;
+ wire T_2076;
+ wire T_2078;
+ wire [1:0] T_2079;
+ wire [2:0] T_2080;
+ wire [2:0] T_2081;
+ wire T_2082;
+ wire [2:0] T_2083;
+ wire T_2084;
+ wire [2:0] T_2085;
+ wire T_2086;
+ wire [2:0] T_2087;
+ wire [1:0] T_2118_addr_beat;
+ wire [25:0] T_2118_addr_block;
+ wire [1:0] T_2118_client_xact_id;
+ wire T_2118_voluntary;
+ wire [2:0] T_2118_r_type;
+ wire [127:0] T_2118_data;
+ wire T_2148;
+ wire [25:0] T_2149;
+ wire T_2152;
+ wire T_2153;
+ wire T_2154;
+ wire T_2155;
+ wire T_2156;
+ wire T_2157;
+ wire T_2158;
+ wire T_2159;
+ wire T_2160;
+ wire T_2161;
+ wire T_2162;
+ wire T_2163;
+ wire [5:0] T_2165;
+ wire [25:0] T_2199_addr_block;
+ wire [1:0] T_2199_client_xact_id;
+ wire [1:0] T_2199_addr_beat;
+ wire T_2199_is_builtin_type;
+ wire [2:0] T_2199_a_type;
+ wire [16:0] T_2199_union;
+ wire [127:0] T_2199_data;
+ wire T_2230;
+ wire T_2231;
+ wire T_2232;
+ wire [5:0] T_2234;
+ wire [11:0] T_2235;
+ wire [31:0] T_2236;
+ wire T_2238;
+ Queue_98 rpq (
+ .clk(rpq_clk),
+ .reset(rpq_reset),
+ .io_enq_ready(rpq_io_enq_ready),
+ .io_enq_valid(rpq_io_enq_valid),
+ .io_enq_bits_addr(rpq_io_enq_bits_addr),
+ .io_enq_bits_tag(rpq_io_enq_bits_tag),
+ .io_enq_bits_cmd(rpq_io_enq_bits_cmd),
+ .io_enq_bits_typ(rpq_io_enq_bits_typ),
+ .io_enq_bits_kill(rpq_io_enq_bits_kill),
+ .io_enq_bits_phys(rpq_io_enq_bits_phys),
+ .io_enq_bits_sdq_id(rpq_io_enq_bits_sdq_id),
+ .io_deq_ready(rpq_io_deq_ready),
+ .io_deq_valid(rpq_io_deq_valid),
+ .io_deq_bits_addr(rpq_io_deq_bits_addr),
+ .io_deq_bits_tag(rpq_io_deq_bits_tag),
+ .io_deq_bits_cmd(rpq_io_deq_bits_cmd),
+ .io_deq_bits_typ(rpq_io_deq_bits_typ),
+ .io_deq_bits_kill(rpq_io_deq_bits_kill),
+ .io_deq_bits_phys(rpq_io_deq_bits_phys),
+ .io_deq_bits_sdq_id(rpq_io_deq_bits_sdq_id),
+ .io_count(rpq_io_count)
+ );
+ assign io_req_pri_rdy = T_1942;
+ assign io_req_sec_rdy = T_1943;
+ assign io_idx_match = T_1938;
+ assign io_tag = T_1941;
+ assign io_mem_req_valid = T_2148;
+ assign io_mem_req_bits_addr_block = T_2199_addr_block;
+ assign io_mem_req_bits_client_xact_id = T_2199_client_xact_id;
+ assign io_mem_req_bits_addr_beat = T_2199_addr_beat;
+ assign io_mem_req_bits_is_builtin_type = T_2199_is_builtin_type;
+ assign io_mem_req_bits_a_type = T_2199_a_type;
+ assign io_mem_req_bits_union = T_2199_union;
+ assign io_mem_req_bits_data = T_2199_data;
+ assign io_refill_way_en = req_way_en;
+ assign io_refill_addr = T_1940;
+ assign io_meta_read_valid = T_2230;
+ assign io_meta_read_bits_idx = req_idx;
+ assign io_meta_read_bits_tag = io_tag;
+ assign io_meta_write_valid = T_1970;
+ assign io_meta_write_bits_idx = req_idx;
+ assign io_meta_write_bits_way_en = req_way_en;
+ assign io_meta_write_bits_data_tag = io_tag;
+ assign io_meta_write_bits_data_coh_state = T_2041_state;
+ assign io_replay_valid = T_2232;
+ assign io_replay_bits_addr = T_2236;
+ assign io_replay_bits_tag = rpq_io_deq_bits_tag;
+ assign io_replay_bits_cmd = T_2238 ? 5'h5 : rpq_io_deq_bits_cmd;
+ assign io_replay_bits_typ = rpq_io_deq_bits_typ;
+ assign io_replay_bits_kill = rpq_io_deq_bits_kill;
+ assign io_replay_bits_phys = 1'h1;
+ assign io_replay_bits_sdq_id = rpq_io_deq_bits_sdq_id;
+ assign io_wb_req_valid = T_2066;
+ assign io_wb_req_bits_addr_beat = T_2118_addr_beat;
+ assign io_wb_req_bits_addr_block = T_2118_addr_block;
+ assign io_wb_req_bits_client_xact_id = T_2118_client_xact_id;
+ assign io_wb_req_bits_voluntary = T_2118_voluntary;
+ assign io_wb_req_bits_r_type = T_2118_r_type;
+ assign io_wb_req_bits_data = T_2118_data;
+ assign io_wb_req_bits_way_en = req_way_en;
+ assign io_probe_rdy = T_1967;
+ assign T_1277_state = 1'h0;
+ assign req_idx = req_addr[11:6];
+ assign T_1586 = io_req_bits_addr[11:6];
+ assign idx_match = req_idx == T_1586;
+ assign T_1588 = io_req_bits_cmd == 5'h1;
+ assign T_1589 = io_req_bits_cmd == 5'h7;
+ assign T_1590 = T_1588 | T_1589;
+ assign T_1591 = io_req_bits_cmd[3];
+ assign T_1592 = io_req_bits_cmd == 5'h4;
+ assign T_1593 = T_1591 | T_1592;
+ assign T_1594 = T_1590 | T_1593;
+ assign T_1595 = io_req_bits_cmd == 5'h3;
+ assign T_1596 = T_1594 | T_1595;
+ assign T_1597 = io_req_bits_cmd == 5'h6;
+ assign T_1598 = T_1596 | T_1597;
+ assign T_1599 = req_cmd == 5'h1;
+ assign T_1600 = req_cmd == 5'h7;
+ assign T_1601 = T_1599 | T_1600;
+ assign T_1602 = req_cmd[3];
+ assign T_1603 = req_cmd == 5'h4;
+ assign T_1604 = T_1602 | T_1603;
+ assign T_1605 = T_1601 | T_1604;
+ assign T_1606 = req_cmd == 5'h3;
+ assign T_1607 = T_1605 | T_1606;
+ assign T_1608 = req_cmd == 5'h6;
+ assign T_1609 = T_1607 | T_1608;
+ assign T_1611 = T_1609 == 1'h0;
+ assign cmd_requires_second_acquire = T_1598 & T_1611;
+ assign states_before_refill_0 = 1'h1;
+ assign states_before_refill_1 = 2'h2;
+ assign states_before_refill_2 = 2'h3;
+ assign T_1619 = states_before_refill_0 == state;
+ assign T_1620 = states_before_refill_1 == state;
+ assign T_1621 = states_before_refill_2 == state;
+ assign T_1623 = 1'h0 | T_1619;
+ assign T_1624 = T_1623 | T_1620;
+ assign T_1625 = T_1624 | T_1621;
+ assign T_1627_0 = 3'h4;
+ assign T_1627_1 = 3'h5;
+ assign T_1631 = T_1627_0 == state;
+ assign T_1632 = T_1627_1 == state;
+ assign T_1634 = 1'h0 | T_1631;
+ assign T_1635 = T_1634 | T_1632;
+ assign T_1637 = cmd_requires_second_acquire == 1'h0;
+ assign T_1638 = T_1635 & T_1637;
+ assign T_1639 = T_1625 | T_1638;
+ assign sec_rdy = idx_match & T_1639;
+ assign T_1644_0 = 3'h5;
+ assign T_1647 = T_1644_0 == io_mem_grant_bits_g_type;
+ assign T_1649 = 1'h0 | T_1647;
+ assign T_1651_0 = 1'h0;
+ assign T_1651_1 = 1'h1;
+ assign T_1655 = T_1651_0 == io_mem_grant_bits_g_type;
+ assign T_1656 = T_1651_1 == io_mem_grant_bits_g_type;
+ assign T_1658 = 1'h0 | T_1655;
+ assign T_1659 = T_1658 | T_1656;
+ assign T_1660 = io_mem_grant_bits_is_builtin_type ? T_1649 : T_1659;
+ assign gnt_multi_data = 1'h1 & T_1660;
+ assign T_1662 = io_mem_grant_valid & gnt_multi_data;
+ assign T_1666 = refill_cnt == 2'h3;
+ assign T_1668 = 1'h0 & T_1666;
+ assign T_1671 = refill_cnt + 1'h1;
+ assign T_1672 = T_1671[1:0];
+ assign T_1673 = T_1668 ? 1'h0 : T_1672;
+ assign refill_count_done = T_1662 & T_1666;
+ assign T_1676 = gnt_multi_data == 1'h0;
+ assign T_1677 = T_1676 | refill_count_done;
+ assign refill_done = io_mem_grant_valid & T_1677;
+ assign rpq_clk = clk;
+ assign rpq_reset = reset;
+ assign rpq_io_enq_valid = T_1742;
+ assign rpq_io_enq_bits_addr = io_req_bits_addr;
+ assign rpq_io_enq_bits_tag = io_req_bits_tag;
+ assign rpq_io_enq_bits_cmd = io_req_bits_cmd;
+ assign rpq_io_enq_bits_typ = io_req_bits_typ;
+ assign rpq_io_enq_bits_kill = io_req_bits_kill;
+ assign rpq_io_enq_bits_phys = io_req_bits_phys;
+ assign rpq_io_enq_bits_sdq_id = io_req_bits_sdq_id;
+ assign rpq_io_deq_ready = T_2238 ? 1'h0 : T_1746;
+ assign T_1734 = io_req_pri_val & io_req_pri_rdy;
+ assign T_1735 = io_req_sec_val & sec_rdy;
+ assign T_1736 = T_1734 | T_1735;
+ assign T_1737 = io_req_bits_cmd == 5'h2;
+ assign T_1738 = io_req_bits_cmd == 5'h3;
+ assign T_1739 = T_1737 | T_1738;
+ assign T_1741 = T_1739 == 1'h0;
+ assign T_1742 = T_1736 & T_1741;
+ assign T_1743 = state == 4'h8;
+ assign T_1744 = io_replay_ready & T_1743;
+ assign T_1745 = state == 1'h0;
+ assign T_1746 = T_1744 | T_1745;
+ assign T_1747 = req_cmd == 5'h1;
+ assign T_1748 = req_cmd == 5'h7;
+ assign T_1749 = T_1747 | T_1748;
+ assign T_1750 = req_cmd[3];
+ assign T_1751 = req_cmd == 5'h4;
+ assign T_1752 = T_1750 | T_1751;
+ assign T_1753 = T_1749 | T_1752;
+ assign T_1754 = T_1753 ? 2'h3 : 2'h2;
+ assign T_1755 = 2'h2 == io_mem_grant_bits_g_type;
+ assign T_1756 = T_1755 ? 2'h3 : 1'h0;
+ assign T_1757 = 1'h1 == io_mem_grant_bits_g_type;
+ assign T_1758 = T_1757 ? T_1754 : T_1756;
+ assign T_1759 = 1'h0 == io_mem_grant_bits_g_type;
+ assign T_1760 = T_1759 ? 1'h1 : T_1758;
+ assign T_1761 = io_mem_grant_bits_is_builtin_type ? 1'h0 : T_1760;
+ assign coh_on_grant_state = T_1761;
+ assign T_1812 = io_req_bits_cmd == 5'h1;
+ assign T_1813 = io_req_bits_cmd == 5'h7;
+ assign T_1814 = T_1812 | T_1813;
+ assign T_1815 = io_req_bits_cmd[3];
+ assign T_1816 = io_req_bits_cmd == 5'h4;
+ assign T_1817 = T_1815 | T_1816;
+ assign T_1818 = T_1814 | T_1817;
+ assign T_1819 = T_1818 ? 2'h3 : io_req_bits_old_meta_coh_state;
+ assign coh_on_hit_state = T_1819;
+ assign T_1870 = state == 4'h8;
+ assign T_1872 = rpq_io_deq_valid == 1'h0;
+ assign T_1873 = T_1870 & T_1872;
+ assign T_1874 = state == 3'h7;
+ assign T_1875 = state == 3'h6;
+ assign T_1876 = T_1875 & io_meta_write_ready;
+ assign T_1877 = state == 3'h5;
+ assign T_1878 = io_mem_req_ready & io_mem_req_valid;
+ assign T_1879 = state == 2'h3;
+ assign T_1880 = T_1879 & io_meta_write_ready;
+ assign T_1881 = state == 2'h2;
+ assign T_1882 = T_1881 & io_mem_grant_valid;
+ assign T_1883 = io_wb_req_ready & io_wb_req_valid;
+ assign T_1886 = 1'h0 == 1'h0;
+ assign T_1887 = T_1886 ? 2'h2 : 2'h3;
+ assign T_1888 = io_req_sec_val & io_req_sec_rdy;
+ assign T_1889 = io_req_pri_val & io_req_pri_rdy;
+ assign T_1890 = io_req_bits_cmd == 5'h1;
+ assign T_1891 = io_req_bits_cmd == 5'h7;
+ assign T_1892 = T_1890 | T_1891;
+ assign T_1893 = io_req_bits_cmd[3];
+ assign T_1894 = io_req_bits_cmd == 5'h4;
+ assign T_1895 = T_1893 | T_1894;
+ assign T_1896 = T_1892 | T_1895;
+ assign T_1897 = io_req_bits_cmd == 5'h3;
+ assign T_1898 = T_1896 | T_1897;
+ assign T_1899 = io_req_bits_cmd == 5'h6;
+ assign T_1900 = T_1898 | T_1899;
+ assign T_1902_0 = 2'h2;
+ assign T_1902_1 = 2'h3;
+ assign T_1906 = T_1902_0 == io_req_bits_old_meta_coh_state;
+ assign T_1907 = T_1902_1 == io_req_bits_old_meta_coh_state;
+ assign T_1909 = 1'h0 | T_1906;
+ assign T_1910 = T_1909 | T_1907;
+ assign T_1912_0 = 1'h1;
+ assign T_1912_1 = 2'h2;
+ assign T_1912_2 = 2'h3;
+ assign T_1917 = T_1912_0 == io_req_bits_old_meta_coh_state;
+ assign T_1918 = T_1912_1 == io_req_bits_old_meta_coh_state;
+ assign T_1919 = T_1912_2 == io_req_bits_old_meta_coh_state;
+ assign T_1921 = 1'h0 | T_1917;
+ assign T_1922 = T_1921 | T_1918;
+ assign T_1923 = T_1922 | T_1919;
+ assign T_1924 = T_1900 ? T_1910 : T_1923;
+ assign T_1926 = T_1924 == 1'h0;
+ assign T_1928 = io_req_bits_tag_match == 1'h0;
+ assign T_1930_0 = 2'h3;
+ assign T_1933 = T_1930_0 == io_req_bits_old_meta_coh_state;
+ assign T_1935 = 1'h0 | T_1933;
+ assign T_1936 = T_1935 ? 1'h1 : 2'h3;
+ assign T_1937 = state != 1'h0;
+ assign T_1938 = T_1937 & idx_match;
+ assign T_1939 = {req_idx,refill_cnt};
+ assign T_1940 = T_1939 << 4;
+ assign T_1941 = req_addr[39:12];
+ assign T_1942 = state == 1'h0;
+ assign T_1943 = sec_rdy & rpq_io_enq_ready;
+ assign T_1947 = meta_hazard != 1'h0;
+ assign T_1949 = meta_hazard + 1'h1;
+ assign T_1950 = T_1949[1:0];
+ assign T_1951 = io_meta_write_ready & io_meta_write_valid;
+ assign T_1954 = idx_match == 1'h0;
+ assign T_1955 = states_before_refill_0 == state;
+ assign T_1956 = states_before_refill_1 == state;
+ assign T_1957 = states_before_refill_2 == state;
+ assign T_1959 = 1'h0 | T_1955;
+ assign T_1960 = T_1959 | T_1956;
+ assign T_1961 = T_1960 | T_1957;
+ assign T_1963 = T_1961 == 1'h0;
+ assign T_1965 = meta_hazard == 1'h0;
+ assign T_1966 = T_1963 & T_1965;
+ assign T_1967 = T_1954 | T_1966;
+ assign T_1968 = state == 3'h6;
+ assign T_1969 = state == 2'h3;
+ assign T_1970 = T_1968 | T_1969;
+ assign T_1971 = state == 2'h3;
+ assign T_1973_0 = 2'h2;
+ assign T_1973_1 = 2'h3;
+ assign T_1977 = T_1973_0 == req_old_meta_coh_state;
+ assign T_1978 = T_1973_1 == req_old_meta_coh_state;
+ assign T_1980 = 1'h0 | T_1977;
+ assign T_1981 = T_1980 | T_1978;
+ assign T_1982 = T_1981 ? 1'h1 : req_old_meta_coh_state;
+ assign T_1983 = req_old_meta_coh_state == 2'h3;
+ assign T_1984 = T_1983 ? 2'h2 : req_old_meta_coh_state;
+ assign T_1985 = 5'h13 == 5'h10;
+ assign T_1986 = T_1985 ? T_1984 : req_old_meta_coh_state;
+ assign T_1987 = 5'h11 == 5'h10;
+ assign T_1988 = T_1987 ? T_1982 : T_1986;
+ assign T_1989 = 5'h10 == 5'h10;
+ assign T_1990 = T_1989 ? 1'h0 : T_1988;
+ assign T_2016_state = T_1990;
+ assign T_2041_state = T_1971 ? T_2016_state : new_coh_state_state;
+ assign T_2066 = state == 1'h1;
+ assign T_2068 = {req_old_meta_tag,req_idx};
+ assign T_2073_0 = 2'h3;
+ assign T_2076 = T_2073_0 == req_old_meta_coh_state;
+ assign T_2078 = 1'h0 | T_2076;
+ assign T_2079 = T_2078 ? 1'h0 : 2'h3;
+ assign T_2080 = T_2078 ? 1'h1 : 3'h4;
+ assign T_2081 = T_2078 ? 2'h2 : 3'h5;
+ assign T_2082 = 5'h13 == 5'h10;
+ assign T_2083 = T_2082 ? T_2081 : 3'h5;
+ assign T_2084 = 5'h11 == 5'h10;
+ assign T_2085 = T_2084 ? T_2080 : T_2083;
+ assign T_2086 = 5'h10 == 5'h10;
+ assign T_2087 = T_2086 ? T_2079 : T_2085;
+ assign T_2118_addr_beat = 1'h0;
+ assign T_2118_addr_block = T_2068;
+ assign T_2118_client_xact_id = 1'h0;
+ assign T_2118_voluntary = 1'h1;
+ assign T_2118_r_type = T_2087;
+ assign T_2118_data = 1'h0;
+ assign T_2148 = state == 3'h4;
+ assign T_2149 = {io_tag,req_idx};
+ assign T_2152 = req_cmd == 5'h1;
+ assign T_2153 = req_cmd == 5'h7;
+ assign T_2154 = T_2152 | T_2153;
+ assign T_2155 = req_cmd[3];
+ assign T_2156 = req_cmd == 5'h4;
+ assign T_2157 = T_2155 | T_2156;
+ assign T_2158 = T_2154 | T_2157;
+ assign T_2159 = req_cmd == 5'h3;
+ assign T_2160 = T_2158 | T_2159;
+ assign T_2161 = req_cmd == 5'h6;
+ assign T_2162 = T_2160 | T_2161;
+ assign T_2163 = T_2162 ? 1'h1 : 1'h0;
+ assign T_2165 = {req_cmd,1'h1};
+ assign T_2199_addr_block = T_2149;
+ assign T_2199_client_xact_id = 1'h0;
+ assign T_2199_addr_beat = 1'h0;
+ assign T_2199_is_builtin_type = 1'h0;
+ assign T_2199_a_type = T_2163;
+ assign T_2199_union = T_2165;
+ assign T_2199_data = 1'h0;
+ assign T_2230 = state == 4'h8;
+ assign T_2231 = state == 4'h8;
+ assign T_2232 = T_2231 & rpq_io_deq_valid;
+ assign T_2234 = rpq_io_deq_bits_addr[5:0];
+ assign T_2235 = {req_idx,T_2234};
+ assign T_2236 = {io_tag,T_2235};
+ assign T_2238 = io_meta_read_ready == 1'h0;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ state = {1{$random}};
+ new_coh_state_state = {1{$random}};
+ req_addr = {2{$random}};
+ req_tag = {1{$random}};
+ req_cmd = {1{$random}};
+ req_typ = {1{$random}};
+ req_kill = {1{$random}};
+ req_phys = {1{$random}};
+ req_sdq_id = {1{$random}};
+ req_tag_match = {1{$random}};
+ req_old_meta_tag = {1{$random}};
+ req_old_meta_coh_state = {1{$random}};
+ req_way_en = {1{$random}};
+ refill_cnt = {1{$random}};
+ meta_hazard = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1889) begin
+ if(T_1928) begin
+ state <= T_1936;
+ end else begin
+ if(io_req_bits_tag_match) begin
+ if(T_1926) begin
+ state <= 3'h4;
+ end else begin
+ if(T_1924) begin
+ state <= 3'h6;
+ end else begin
+ if(T_1883) begin
+ state <= T_1887;
+ end else begin
+ if(T_1882) begin
+ state <= 2'h3;
+ end else begin
+ if(T_1880) begin
+ state <= 3'h4;
+ end else begin
+ if(T_1878) begin
+ state <= 3'h5;
+ end else begin
+ if(T_1877) begin
+ if(refill_done) begin
+ state <= 3'h6;
+ end else begin
+ if(T_1876) begin
+ state <= 3'h7;
+ end else begin
+ if(T_1874) begin
+ state <= 4'h8;
+ end else begin
+ if(T_1873) begin
+ state <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1876) begin
+ state <= 3'h7;
+ end else begin
+ if(T_1874) begin
+ state <= 4'h8;
+ end else begin
+ if(T_1873) begin
+ state <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1883) begin
+ state <= T_1887;
+ end else begin
+ if(T_1882) begin
+ state <= 2'h3;
+ end else begin
+ if(T_1880) begin
+ state <= 3'h4;
+ end else begin
+ if(T_1878) begin
+ state <= 3'h5;
+ end else begin
+ if(T_1877) begin
+ if(refill_done) begin
+ state <= 3'h6;
+ end else begin
+ if(T_1876) begin
+ state <= 3'h7;
+ end else begin
+ if(T_1874) begin
+ state <= 4'h8;
+ end else begin
+ if(T_1873) begin
+ state <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1876) begin
+ state <= 3'h7;
+ end else begin
+ if(T_1874) begin
+ state <= 4'h8;
+ end else begin
+ if(T_1873) begin
+ state <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1883) begin
+ state <= T_1887;
+ end else begin
+ if(T_1882) begin
+ state <= 2'h3;
+ end else begin
+ if(T_1880) begin
+ state <= 3'h4;
+ end else begin
+ if(T_1878) begin
+ state <= 3'h5;
+ end else begin
+ if(T_1877) begin
+ if(refill_done) begin
+ state <= 3'h6;
+ end else begin
+ if(T_1876) begin
+ state <= 3'h7;
+ end else begin
+ if(T_1874) begin
+ state <= 4'h8;
+ end else begin
+ if(T_1873) begin
+ state <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1876) begin
+ state <= 3'h7;
+ end else begin
+ if(T_1874) begin
+ state <= 4'h8;
+ end else begin
+ if(T_1873) begin
+ state <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ if(reset) begin
+ new_coh_state_state <= T_1277_state;
+ end else begin
+ if(T_1889) begin
+ if(io_req_bits_tag_match) begin
+ if(T_1924) begin
+ new_coh_state_state <= coh_on_hit_state;
+ end else begin
+ if(T_1877) begin
+ if(io_mem_grant_valid) begin
+ new_coh_state_state <= coh_on_grant_state;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1877) begin
+ if(io_mem_grant_valid) begin
+ new_coh_state_state <= coh_on_grant_state;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1877) begin
+ if(io_mem_grant_valid) begin
+ new_coh_state_state <= coh_on_grant_state;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1889) begin
+ req_addr <= io_req_bits_addr;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1889) begin
+ req_tag <= io_req_bits_tag;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1889) begin
+ req_cmd <= io_req_bits_cmd;
+ end else begin
+ if(T_1888) begin
+ if(cmd_requires_second_acquire) begin
+ req_cmd <= io_req_bits_cmd;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1889) begin
+ req_typ <= io_req_bits_typ;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1889) begin
+ req_kill <= io_req_bits_kill;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1889) begin
+ req_phys <= io_req_bits_phys;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1889) begin
+ req_sdq_id <= io_req_bits_sdq_id;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1889) begin
+ req_tag_match <= io_req_bits_tag_match;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1889) begin
+ req_old_meta_tag <= io_req_bits_old_meta_tag;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1889) begin
+ req_old_meta_coh_state <= io_req_bits_old_meta_coh_state;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1889) begin
+ req_way_en <= io_req_bits_way_en;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ refill_cnt <= 2'h0;
+ end else begin
+ if(T_1662) begin
+ refill_cnt <= T_1673;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ meta_hazard <= 2'h0;
+ end else begin
+ if(T_1951) begin
+ meta_hazard <= 1'h1;
+ end else begin
+ if(T_1947) begin
+ meta_hazard <= T_1950;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+endmodule
+module MSHR_99(
+ input clk,
+ input reset,
+ input io_req_pri_val,
+ output io_req_pri_rdy,
+ input io_req_sec_val,
+ output io_req_sec_rdy,
+ input [39:0] io_req_bits_addr,
+ input [8:0] io_req_bits_tag,
+ input [4:0] io_req_bits_cmd,
+ input [2:0] io_req_bits_typ,
+ input io_req_bits_kill,
+ input io_req_bits_phys,
+ input [4:0] io_req_bits_sdq_id,
+ input io_req_bits_tag_match,
+ input [19:0] io_req_bits_old_meta_tag,
+ input [1:0] io_req_bits_old_meta_coh_state,
+ input [3:0] io_req_bits_way_en,
+ output io_idx_match,
+ output [19:0] io_tag,
+ input io_mem_req_ready,
+ output io_mem_req_valid,
+ output [25:0] io_mem_req_bits_addr_block,
+ output [1:0] io_mem_req_bits_client_xact_id,
+ output [1:0] io_mem_req_bits_addr_beat,
+ output io_mem_req_bits_is_builtin_type,
+ output [2:0] io_mem_req_bits_a_type,
+ output [16:0] io_mem_req_bits_union,
+ output [127:0] io_mem_req_bits_data,
+ output [3:0] io_refill_way_en,
+ output [11:0] io_refill_addr,
+ input io_meta_read_ready,
+ output io_meta_read_valid,
+ output [5:0] io_meta_read_bits_idx,
+ output [19:0] io_meta_read_bits_tag,
+ input io_meta_write_ready,
+ output io_meta_write_valid,
+ output [5:0] io_meta_write_bits_idx,
+ output [3:0] io_meta_write_bits_way_en,
+ output [19:0] io_meta_write_bits_data_tag,
+ output [1:0] io_meta_write_bits_data_coh_state,
+ input io_replay_ready,
+ output io_replay_valid,
+ output [39:0] io_replay_bits_addr,
+ output [8:0] io_replay_bits_tag,
+ output [4:0] io_replay_bits_cmd,
+ output [2:0] io_replay_bits_typ,
+ output io_replay_bits_kill,
+ output io_replay_bits_phys,
+ output [4:0] io_replay_bits_sdq_id,
+ input io_mem_grant_valid,
+ input [1:0] io_mem_grant_bits_addr_beat,
+ input [1:0] io_mem_grant_bits_client_xact_id,
+ input [3:0] io_mem_grant_bits_manager_xact_id,
+ input io_mem_grant_bits_is_builtin_type,
+ input [3:0] io_mem_grant_bits_g_type,
+ input [127:0] io_mem_grant_bits_data,
+ input io_wb_req_ready,
+ output io_wb_req_valid,
+ output [1:0] io_wb_req_bits_addr_beat,
+ output [25:0] io_wb_req_bits_addr_block,
+ output [1:0] io_wb_req_bits_client_xact_id,
+ output io_wb_req_bits_voluntary,
+ output [2:0] io_wb_req_bits_r_type,
+ output [127:0] io_wb_req_bits_data,
+ output [3:0] io_wb_req_bits_way_en,
+ output io_probe_rdy
+);
+ reg [3:0] state;
+ wire [1:0] T_1277_state;
+ reg [1:0] new_coh_state_state;
+ reg [39:0] req_addr;
+ reg [8:0] req_tag;
+ reg [4:0] req_cmd;
+ reg [2:0] req_typ;
+ reg req_kill;
+ reg req_phys;
+ reg [4:0] req_sdq_id;
+ reg req_tag_match;
+ reg [19:0] req_old_meta_tag;
+ reg [1:0] req_old_meta_coh_state;
+ reg [3:0] req_way_en;
+ wire [5:0] req_idx;
+ wire [5:0] T_1586;
+ wire idx_match;
+ wire T_1588;
+ wire T_1589;
+ wire T_1590;
+ wire T_1591;
+ wire T_1592;
+ wire T_1593;
+ wire T_1594;
+ wire T_1595;
+ wire T_1596;
+ wire T_1597;
+ wire T_1598;
+ wire T_1599;
+ wire T_1600;
+ wire T_1601;
+ wire T_1602;
+ wire T_1603;
+ wire T_1604;
+ wire T_1605;
+ wire T_1606;
+ wire T_1607;
+ wire T_1608;
+ wire T_1609;
+ wire T_1611;
+ wire cmd_requires_second_acquire;
+ wire [1:0] states_before_refill_0;
+ wire [1:0] states_before_refill_1;
+ wire [1:0] states_before_refill_2;
+ wire T_1619;
+ wire T_1620;
+ wire T_1621;
+ wire T_1623;
+ wire T_1624;
+ wire T_1625;
+ wire [2:0] T_1627_0;
+ wire [2:0] T_1627_1;
+ wire T_1631;
+ wire T_1632;
+ wire T_1634;
+ wire T_1635;
+ wire T_1637;
+ wire T_1638;
+ wire T_1639;
+ wire sec_rdy;
+ wire [2:0] T_1644_0;
+ wire T_1647;
+ wire T_1649;
+ wire T_1651_0;
+ wire T_1651_1;
+ wire T_1655;
+ wire T_1656;
+ wire T_1658;
+ wire T_1659;
+ wire T_1660;
+ wire gnt_multi_data;
+ wire T_1662;
+ reg [1:0] refill_cnt;
+ wire T_1666;
+ wire T_1668;
+ wire [2:0] T_1671;
+ wire [1:0] T_1672;
+ wire [1:0] T_1673;
+ wire refill_count_done;
+ wire T_1676;
+ wire T_1677;
+ wire refill_done;
+ wire rpq_clk;
+ wire rpq_reset;
+ wire rpq_io_enq_ready;
+ wire rpq_io_enq_valid;
+ wire [39:0] rpq_io_enq_bits_addr;
+ wire [8:0] rpq_io_enq_bits_tag;
+ wire [4:0] rpq_io_enq_bits_cmd;
+ wire [2:0] rpq_io_enq_bits_typ;
+ wire rpq_io_enq_bits_kill;
+ wire rpq_io_enq_bits_phys;
+ wire [4:0] rpq_io_enq_bits_sdq_id;
+ wire rpq_io_deq_ready;
+ wire rpq_io_deq_valid;
+ wire [39:0] rpq_io_deq_bits_addr;
+ wire [8:0] rpq_io_deq_bits_tag;
+ wire [4:0] rpq_io_deq_bits_cmd;
+ wire [2:0] rpq_io_deq_bits_typ;
+ wire rpq_io_deq_bits_kill;
+ wire rpq_io_deq_bits_phys;
+ wire [4:0] rpq_io_deq_bits_sdq_id;
+ wire [4:0] rpq_io_count;
+ wire T_1734;
+ wire T_1735;
+ wire T_1736;
+ wire T_1737;
+ wire T_1738;
+ wire T_1739;
+ wire T_1741;
+ wire T_1742;
+ wire T_1743;
+ wire T_1744;
+ wire T_1745;
+ wire T_1746;
+ wire T_1747;
+ wire T_1748;
+ wire T_1749;
+ wire T_1750;
+ wire T_1751;
+ wire T_1752;
+ wire T_1753;
+ wire [1:0] T_1754;
+ wire T_1755;
+ wire [1:0] T_1756;
+ wire T_1757;
+ wire [1:0] T_1758;
+ wire T_1759;
+ wire [1:0] T_1760;
+ wire [1:0] T_1761;
+ wire [1:0] coh_on_grant_state;
+ wire T_1812;
+ wire T_1813;
+ wire T_1814;
+ wire T_1815;
+ wire T_1816;
+ wire T_1817;
+ wire T_1818;
+ wire [1:0] T_1819;
+ wire [1:0] coh_on_hit_state;
+ wire T_1870;
+ wire T_1872;
+ wire T_1873;
+ wire T_1874;
+ wire T_1875;
+ wire T_1876;
+ wire T_1877;
+ wire T_1878;
+ wire T_1879;
+ wire T_1880;
+ wire T_1881;
+ wire T_1882;
+ wire T_1883;
+ wire T_1886;
+ wire [1:0] T_1887;
+ wire T_1888;
+ wire T_1889;
+ wire T_1890;
+ wire T_1891;
+ wire T_1892;
+ wire T_1893;
+ wire T_1894;
+ wire T_1895;
+ wire T_1896;
+ wire T_1897;
+ wire T_1898;
+ wire T_1899;
+ wire T_1900;
+ wire [1:0] T_1902_0;
+ wire [1:0] T_1902_1;
+ wire T_1906;
+ wire T_1907;
+ wire T_1909;
+ wire T_1910;
+ wire [1:0] T_1912_0;
+ wire [1:0] T_1912_1;
+ wire [1:0] T_1912_2;
+ wire T_1917;
+ wire T_1918;
+ wire T_1919;
+ wire T_1921;
+ wire T_1922;
+ wire T_1923;
+ wire T_1924;
+ wire T_1926;
+ wire T_1928;
+ wire [1:0] T_1930_0;
+ wire T_1933;
+ wire T_1935;
+ wire [1:0] T_1936;
+ wire T_1937;
+ wire T_1938;
+ wire [7:0] T_1939;
+ wire [11:0] T_1940;
+ wire [27:0] T_1941;
+ wire T_1942;
+ wire T_1943;
+ reg [1:0] meta_hazard;
+ wire T_1947;
+ wire [2:0] T_1949;
+ wire [1:0] T_1950;
+ wire T_1951;
+ wire T_1954;
+ wire T_1955;
+ wire T_1956;
+ wire T_1957;
+ wire T_1959;
+ wire T_1960;
+ wire T_1961;
+ wire T_1963;
+ wire T_1965;
+ wire T_1966;
+ wire T_1967;
+ wire T_1968;
+ wire T_1969;
+ wire T_1970;
+ wire T_1971;
+ wire [1:0] T_1973_0;
+ wire [1:0] T_1973_1;
+ wire T_1977;
+ wire T_1978;
+ wire T_1980;
+ wire T_1981;
+ wire [1:0] T_1982;
+ wire T_1983;
+ wire [1:0] T_1984;
+ wire T_1985;
+ wire [1:0] T_1986;
+ wire T_1987;
+ wire [1:0] T_1988;
+ wire T_1989;
+ wire [1:0] T_1990;
+ wire [1:0] T_2016_state;
+ wire [1:0] T_2041_state;
+ wire T_2066;
+ wire [25:0] T_2068;
+ wire [1:0] T_2073_0;
+ wire T_2076;
+ wire T_2078;
+ wire [1:0] T_2079;
+ wire [2:0] T_2080;
+ wire [2:0] T_2081;
+ wire T_2082;
+ wire [2:0] T_2083;
+ wire T_2084;
+ wire [2:0] T_2085;
+ wire T_2086;
+ wire [2:0] T_2087;
+ wire [1:0] T_2118_addr_beat;
+ wire [25:0] T_2118_addr_block;
+ wire [1:0] T_2118_client_xact_id;
+ wire T_2118_voluntary;
+ wire [2:0] T_2118_r_type;
+ wire [127:0] T_2118_data;
+ wire T_2148;
+ wire [25:0] T_2149;
+ wire T_2152;
+ wire T_2153;
+ wire T_2154;
+ wire T_2155;
+ wire T_2156;
+ wire T_2157;
+ wire T_2158;
+ wire T_2159;
+ wire T_2160;
+ wire T_2161;
+ wire T_2162;
+ wire T_2163;
+ wire [5:0] T_2165;
+ wire [25:0] T_2199_addr_block;
+ wire [1:0] T_2199_client_xact_id;
+ wire [1:0] T_2199_addr_beat;
+ wire T_2199_is_builtin_type;
+ wire [2:0] T_2199_a_type;
+ wire [16:0] T_2199_union;
+ wire [127:0] T_2199_data;
+ wire T_2230;
+ wire T_2231;
+ wire T_2232;
+ wire [5:0] T_2234;
+ wire [11:0] T_2235;
+ wire [31:0] T_2236;
+ wire T_2238;
+ Queue_98 rpq (
+ .clk(rpq_clk),
+ .reset(rpq_reset),
+ .io_enq_ready(rpq_io_enq_ready),
+ .io_enq_valid(rpq_io_enq_valid),
+ .io_enq_bits_addr(rpq_io_enq_bits_addr),
+ .io_enq_bits_tag(rpq_io_enq_bits_tag),
+ .io_enq_bits_cmd(rpq_io_enq_bits_cmd),
+ .io_enq_bits_typ(rpq_io_enq_bits_typ),
+ .io_enq_bits_kill(rpq_io_enq_bits_kill),
+ .io_enq_bits_phys(rpq_io_enq_bits_phys),
+ .io_enq_bits_sdq_id(rpq_io_enq_bits_sdq_id),
+ .io_deq_ready(rpq_io_deq_ready),
+ .io_deq_valid(rpq_io_deq_valid),
+ .io_deq_bits_addr(rpq_io_deq_bits_addr),
+ .io_deq_bits_tag(rpq_io_deq_bits_tag),
+ .io_deq_bits_cmd(rpq_io_deq_bits_cmd),
+ .io_deq_bits_typ(rpq_io_deq_bits_typ),
+ .io_deq_bits_kill(rpq_io_deq_bits_kill),
+ .io_deq_bits_phys(rpq_io_deq_bits_phys),
+ .io_deq_bits_sdq_id(rpq_io_deq_bits_sdq_id),
+ .io_count(rpq_io_count)
+ );
+ assign io_req_pri_rdy = T_1942;
+ assign io_req_sec_rdy = T_1943;
+ assign io_idx_match = T_1938;
+ assign io_tag = T_1941;
+ assign io_mem_req_valid = T_2148;
+ assign io_mem_req_bits_addr_block = T_2199_addr_block;
+ assign io_mem_req_bits_client_xact_id = T_2199_client_xact_id;
+ assign io_mem_req_bits_addr_beat = T_2199_addr_beat;
+ assign io_mem_req_bits_is_builtin_type = T_2199_is_builtin_type;
+ assign io_mem_req_bits_a_type = T_2199_a_type;
+ assign io_mem_req_bits_union = T_2199_union;
+ assign io_mem_req_bits_data = T_2199_data;
+ assign io_refill_way_en = req_way_en;
+ assign io_refill_addr = T_1940;
+ assign io_meta_read_valid = T_2230;
+ assign io_meta_read_bits_idx = req_idx;
+ assign io_meta_read_bits_tag = io_tag;
+ assign io_meta_write_valid = T_1970;
+ assign io_meta_write_bits_idx = req_idx;
+ assign io_meta_write_bits_way_en = req_way_en;
+ assign io_meta_write_bits_data_tag = io_tag;
+ assign io_meta_write_bits_data_coh_state = T_2041_state;
+ assign io_replay_valid = T_2232;
+ assign io_replay_bits_addr = T_2236;
+ assign io_replay_bits_tag = rpq_io_deq_bits_tag;
+ assign io_replay_bits_cmd = T_2238 ? 5'h5 : rpq_io_deq_bits_cmd;
+ assign io_replay_bits_typ = rpq_io_deq_bits_typ;
+ assign io_replay_bits_kill = rpq_io_deq_bits_kill;
+ assign io_replay_bits_phys = 1'h1;
+ assign io_replay_bits_sdq_id = rpq_io_deq_bits_sdq_id;
+ assign io_wb_req_valid = T_2066;
+ assign io_wb_req_bits_addr_beat = T_2118_addr_beat;
+ assign io_wb_req_bits_addr_block = T_2118_addr_block;
+ assign io_wb_req_bits_client_xact_id = T_2118_client_xact_id;
+ assign io_wb_req_bits_voluntary = T_2118_voluntary;
+ assign io_wb_req_bits_r_type = T_2118_r_type;
+ assign io_wb_req_bits_data = T_2118_data;
+ assign io_wb_req_bits_way_en = req_way_en;
+ assign io_probe_rdy = T_1967;
+ assign T_1277_state = 1'h0;
+ assign req_idx = req_addr[11:6];
+ assign T_1586 = io_req_bits_addr[11:6];
+ assign idx_match = req_idx == T_1586;
+ assign T_1588 = io_req_bits_cmd == 5'h1;
+ assign T_1589 = io_req_bits_cmd == 5'h7;
+ assign T_1590 = T_1588 | T_1589;
+ assign T_1591 = io_req_bits_cmd[3];
+ assign T_1592 = io_req_bits_cmd == 5'h4;
+ assign T_1593 = T_1591 | T_1592;
+ assign T_1594 = T_1590 | T_1593;
+ assign T_1595 = io_req_bits_cmd == 5'h3;
+ assign T_1596 = T_1594 | T_1595;
+ assign T_1597 = io_req_bits_cmd == 5'h6;
+ assign T_1598 = T_1596 | T_1597;
+ assign T_1599 = req_cmd == 5'h1;
+ assign T_1600 = req_cmd == 5'h7;
+ assign T_1601 = T_1599 | T_1600;
+ assign T_1602 = req_cmd[3];
+ assign T_1603 = req_cmd == 5'h4;
+ assign T_1604 = T_1602 | T_1603;
+ assign T_1605 = T_1601 | T_1604;
+ assign T_1606 = req_cmd == 5'h3;
+ assign T_1607 = T_1605 | T_1606;
+ assign T_1608 = req_cmd == 5'h6;
+ assign T_1609 = T_1607 | T_1608;
+ assign T_1611 = T_1609 == 1'h0;
+ assign cmd_requires_second_acquire = T_1598 & T_1611;
+ assign states_before_refill_0 = 1'h1;
+ assign states_before_refill_1 = 2'h2;
+ assign states_before_refill_2 = 2'h3;
+ assign T_1619 = states_before_refill_0 == state;
+ assign T_1620 = states_before_refill_1 == state;
+ assign T_1621 = states_before_refill_2 == state;
+ assign T_1623 = 1'h0 | T_1619;
+ assign T_1624 = T_1623 | T_1620;
+ assign T_1625 = T_1624 | T_1621;
+ assign T_1627_0 = 3'h4;
+ assign T_1627_1 = 3'h5;
+ assign T_1631 = T_1627_0 == state;
+ assign T_1632 = T_1627_1 == state;
+ assign T_1634 = 1'h0 | T_1631;
+ assign T_1635 = T_1634 | T_1632;
+ assign T_1637 = cmd_requires_second_acquire == 1'h0;
+ assign T_1638 = T_1635 & T_1637;
+ assign T_1639 = T_1625 | T_1638;
+ assign sec_rdy = idx_match & T_1639;
+ assign T_1644_0 = 3'h5;
+ assign T_1647 = T_1644_0 == io_mem_grant_bits_g_type;
+ assign T_1649 = 1'h0 | T_1647;
+ assign T_1651_0 = 1'h0;
+ assign T_1651_1 = 1'h1;
+ assign T_1655 = T_1651_0 == io_mem_grant_bits_g_type;
+ assign T_1656 = T_1651_1 == io_mem_grant_bits_g_type;
+ assign T_1658 = 1'h0 | T_1655;
+ assign T_1659 = T_1658 | T_1656;
+ assign T_1660 = io_mem_grant_bits_is_builtin_type ? T_1649 : T_1659;
+ assign gnt_multi_data = 1'h1 & T_1660;
+ assign T_1662 = io_mem_grant_valid & gnt_multi_data;
+ assign T_1666 = refill_cnt == 2'h3;
+ assign T_1668 = 1'h0 & T_1666;
+ assign T_1671 = refill_cnt + 1'h1;
+ assign T_1672 = T_1671[1:0];
+ assign T_1673 = T_1668 ? 1'h0 : T_1672;
+ assign refill_count_done = T_1662 & T_1666;
+ assign T_1676 = gnt_multi_data == 1'h0;
+ assign T_1677 = T_1676 | refill_count_done;
+ assign refill_done = io_mem_grant_valid & T_1677;
+ assign rpq_clk = clk;
+ assign rpq_reset = reset;
+ assign rpq_io_enq_valid = T_1742;
+ assign rpq_io_enq_bits_addr = io_req_bits_addr;
+ assign rpq_io_enq_bits_tag = io_req_bits_tag;
+ assign rpq_io_enq_bits_cmd = io_req_bits_cmd;
+ assign rpq_io_enq_bits_typ = io_req_bits_typ;
+ assign rpq_io_enq_bits_kill = io_req_bits_kill;
+ assign rpq_io_enq_bits_phys = io_req_bits_phys;
+ assign rpq_io_enq_bits_sdq_id = io_req_bits_sdq_id;
+ assign rpq_io_deq_ready = T_2238 ? 1'h0 : T_1746;
+ assign T_1734 = io_req_pri_val & io_req_pri_rdy;
+ assign T_1735 = io_req_sec_val & sec_rdy;
+ assign T_1736 = T_1734 | T_1735;
+ assign T_1737 = io_req_bits_cmd == 5'h2;
+ assign T_1738 = io_req_bits_cmd == 5'h3;
+ assign T_1739 = T_1737 | T_1738;
+ assign T_1741 = T_1739 == 1'h0;
+ assign T_1742 = T_1736 & T_1741;
+ assign T_1743 = state == 4'h8;
+ assign T_1744 = io_replay_ready & T_1743;
+ assign T_1745 = state == 1'h0;
+ assign T_1746 = T_1744 | T_1745;
+ assign T_1747 = req_cmd == 5'h1;
+ assign T_1748 = req_cmd == 5'h7;
+ assign T_1749 = T_1747 | T_1748;
+ assign T_1750 = req_cmd[3];
+ assign T_1751 = req_cmd == 5'h4;
+ assign T_1752 = T_1750 | T_1751;
+ assign T_1753 = T_1749 | T_1752;
+ assign T_1754 = T_1753 ? 2'h3 : 2'h2;
+ assign T_1755 = 2'h2 == io_mem_grant_bits_g_type;
+ assign T_1756 = T_1755 ? 2'h3 : 1'h0;
+ assign T_1757 = 1'h1 == io_mem_grant_bits_g_type;
+ assign T_1758 = T_1757 ? T_1754 : T_1756;
+ assign T_1759 = 1'h0 == io_mem_grant_bits_g_type;
+ assign T_1760 = T_1759 ? 1'h1 : T_1758;
+ assign T_1761 = io_mem_grant_bits_is_builtin_type ? 1'h0 : T_1760;
+ assign coh_on_grant_state = T_1761;
+ assign T_1812 = io_req_bits_cmd == 5'h1;
+ assign T_1813 = io_req_bits_cmd == 5'h7;
+ assign T_1814 = T_1812 | T_1813;
+ assign T_1815 = io_req_bits_cmd[3];
+ assign T_1816 = io_req_bits_cmd == 5'h4;
+ assign T_1817 = T_1815 | T_1816;
+ assign T_1818 = T_1814 | T_1817;
+ assign T_1819 = T_1818 ? 2'h3 : io_req_bits_old_meta_coh_state;
+ assign coh_on_hit_state = T_1819;
+ assign T_1870 = state == 4'h8;
+ assign T_1872 = rpq_io_deq_valid == 1'h0;
+ assign T_1873 = T_1870 & T_1872;
+ assign T_1874 = state == 3'h7;
+ assign T_1875 = state == 3'h6;
+ assign T_1876 = T_1875 & io_meta_write_ready;
+ assign T_1877 = state == 3'h5;
+ assign T_1878 = io_mem_req_ready & io_mem_req_valid;
+ assign T_1879 = state == 2'h3;
+ assign T_1880 = T_1879 & io_meta_write_ready;
+ assign T_1881 = state == 2'h2;
+ assign T_1882 = T_1881 & io_mem_grant_valid;
+ assign T_1883 = io_wb_req_ready & io_wb_req_valid;
+ assign T_1886 = 1'h0 == 1'h0;
+ assign T_1887 = T_1886 ? 2'h2 : 2'h3;
+ assign T_1888 = io_req_sec_val & io_req_sec_rdy;
+ assign T_1889 = io_req_pri_val & io_req_pri_rdy;
+ assign T_1890 = io_req_bits_cmd == 5'h1;
+ assign T_1891 = io_req_bits_cmd == 5'h7;
+ assign T_1892 = T_1890 | T_1891;
+ assign T_1893 = io_req_bits_cmd[3];
+ assign T_1894 = io_req_bits_cmd == 5'h4;
+ assign T_1895 = T_1893 | T_1894;
+ assign T_1896 = T_1892 | T_1895;
+ assign T_1897 = io_req_bits_cmd == 5'h3;
+ assign T_1898 = T_1896 | T_1897;
+ assign T_1899 = io_req_bits_cmd == 5'h6;
+ assign T_1900 = T_1898 | T_1899;
+ assign T_1902_0 = 2'h2;
+ assign T_1902_1 = 2'h3;
+ assign T_1906 = T_1902_0 == io_req_bits_old_meta_coh_state;
+ assign T_1907 = T_1902_1 == io_req_bits_old_meta_coh_state;
+ assign T_1909 = 1'h0 | T_1906;
+ assign T_1910 = T_1909 | T_1907;
+ assign T_1912_0 = 1'h1;
+ assign T_1912_1 = 2'h2;
+ assign T_1912_2 = 2'h3;
+ assign T_1917 = T_1912_0 == io_req_bits_old_meta_coh_state;
+ assign T_1918 = T_1912_1 == io_req_bits_old_meta_coh_state;
+ assign T_1919 = T_1912_2 == io_req_bits_old_meta_coh_state;
+ assign T_1921 = 1'h0 | T_1917;
+ assign T_1922 = T_1921 | T_1918;
+ assign T_1923 = T_1922 | T_1919;
+ assign T_1924 = T_1900 ? T_1910 : T_1923;
+ assign T_1926 = T_1924 == 1'h0;
+ assign T_1928 = io_req_bits_tag_match == 1'h0;
+ assign T_1930_0 = 2'h3;
+ assign T_1933 = T_1930_0 == io_req_bits_old_meta_coh_state;
+ assign T_1935 = 1'h0 | T_1933;
+ assign T_1936 = T_1935 ? 1'h1 : 2'h3;
+ assign T_1937 = state != 1'h0;
+ assign T_1938 = T_1937 & idx_match;
+ assign T_1939 = {req_idx,refill_cnt};
+ assign T_1940 = T_1939 << 4;
+ assign T_1941 = req_addr[39:12];
+ assign T_1942 = state == 1'h0;
+ assign T_1943 = sec_rdy & rpq_io_enq_ready;
+ assign T_1947 = meta_hazard != 1'h0;
+ assign T_1949 = meta_hazard + 1'h1;
+ assign T_1950 = T_1949[1:0];
+ assign T_1951 = io_meta_write_ready & io_meta_write_valid;
+ assign T_1954 = idx_match == 1'h0;
+ assign T_1955 = states_before_refill_0 == state;
+ assign T_1956 = states_before_refill_1 == state;
+ assign T_1957 = states_before_refill_2 == state;
+ assign T_1959 = 1'h0 | T_1955;
+ assign T_1960 = T_1959 | T_1956;
+ assign T_1961 = T_1960 | T_1957;
+ assign T_1963 = T_1961 == 1'h0;
+ assign T_1965 = meta_hazard == 1'h0;
+ assign T_1966 = T_1963 & T_1965;
+ assign T_1967 = T_1954 | T_1966;
+ assign T_1968 = state == 3'h6;
+ assign T_1969 = state == 2'h3;
+ assign T_1970 = T_1968 | T_1969;
+ assign T_1971 = state == 2'h3;
+ assign T_1973_0 = 2'h2;
+ assign T_1973_1 = 2'h3;
+ assign T_1977 = T_1973_0 == req_old_meta_coh_state;
+ assign T_1978 = T_1973_1 == req_old_meta_coh_state;
+ assign T_1980 = 1'h0 | T_1977;
+ assign T_1981 = T_1980 | T_1978;
+ assign T_1982 = T_1981 ? 1'h1 : req_old_meta_coh_state;
+ assign T_1983 = req_old_meta_coh_state == 2'h3;
+ assign T_1984 = T_1983 ? 2'h2 : req_old_meta_coh_state;
+ assign T_1985 = 5'h13 == 5'h10;
+ assign T_1986 = T_1985 ? T_1984 : req_old_meta_coh_state;
+ assign T_1987 = 5'h11 == 5'h10;
+ assign T_1988 = T_1987 ? T_1982 : T_1986;
+ assign T_1989 = 5'h10 == 5'h10;
+ assign T_1990 = T_1989 ? 1'h0 : T_1988;
+ assign T_2016_state = T_1990;
+ assign T_2041_state = T_1971 ? T_2016_state : new_coh_state_state;
+ assign T_2066 = state == 1'h1;
+ assign T_2068 = {req_old_meta_tag,req_idx};
+ assign T_2073_0 = 2'h3;
+ assign T_2076 = T_2073_0 == req_old_meta_coh_state;
+ assign T_2078 = 1'h0 | T_2076;
+ assign T_2079 = T_2078 ? 1'h0 : 2'h3;
+ assign T_2080 = T_2078 ? 1'h1 : 3'h4;
+ assign T_2081 = T_2078 ? 2'h2 : 3'h5;
+ assign T_2082 = 5'h13 == 5'h10;
+ assign T_2083 = T_2082 ? T_2081 : 3'h5;
+ assign T_2084 = 5'h11 == 5'h10;
+ assign T_2085 = T_2084 ? T_2080 : T_2083;
+ assign T_2086 = 5'h10 == 5'h10;
+ assign T_2087 = T_2086 ? T_2079 : T_2085;
+ assign T_2118_addr_beat = 1'h0;
+ assign T_2118_addr_block = T_2068;
+ assign T_2118_client_xact_id = 1'h1;
+ assign T_2118_voluntary = 1'h1;
+ assign T_2118_r_type = T_2087;
+ assign T_2118_data = 1'h0;
+ assign T_2148 = state == 3'h4;
+ assign T_2149 = {io_tag,req_idx};
+ assign T_2152 = req_cmd == 5'h1;
+ assign T_2153 = req_cmd == 5'h7;
+ assign T_2154 = T_2152 | T_2153;
+ assign T_2155 = req_cmd[3];
+ assign T_2156 = req_cmd == 5'h4;
+ assign T_2157 = T_2155 | T_2156;
+ assign T_2158 = T_2154 | T_2157;
+ assign T_2159 = req_cmd == 5'h3;
+ assign T_2160 = T_2158 | T_2159;
+ assign T_2161 = req_cmd == 5'h6;
+ assign T_2162 = T_2160 | T_2161;
+ assign T_2163 = T_2162 ? 1'h1 : 1'h0;
+ assign T_2165 = {req_cmd,1'h1};
+ assign T_2199_addr_block = T_2149;
+ assign T_2199_client_xact_id = 1'h1;
+ assign T_2199_addr_beat = 1'h0;
+ assign T_2199_is_builtin_type = 1'h0;
+ assign T_2199_a_type = T_2163;
+ assign T_2199_union = T_2165;
+ assign T_2199_data = 1'h0;
+ assign T_2230 = state == 4'h8;
+ assign T_2231 = state == 4'h8;
+ assign T_2232 = T_2231 & rpq_io_deq_valid;
+ assign T_2234 = rpq_io_deq_bits_addr[5:0];
+ assign T_2235 = {req_idx,T_2234};
+ assign T_2236 = {io_tag,T_2235};
+ assign T_2238 = io_meta_read_ready == 1'h0;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ state = {1{$random}};
+ new_coh_state_state = {1{$random}};
+ req_addr = {2{$random}};
+ req_tag = {1{$random}};
+ req_cmd = {1{$random}};
+ req_typ = {1{$random}};
+ req_kill = {1{$random}};
+ req_phys = {1{$random}};
+ req_sdq_id = {1{$random}};
+ req_tag_match = {1{$random}};
+ req_old_meta_tag = {1{$random}};
+ req_old_meta_coh_state = {1{$random}};
+ req_way_en = {1{$random}};
+ refill_cnt = {1{$random}};
+ meta_hazard = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1889) begin
+ if(T_1928) begin
+ state <= T_1936;
+ end else begin
+ if(io_req_bits_tag_match) begin
+ if(T_1926) begin
+ state <= 3'h4;
+ end else begin
+ if(T_1924) begin
+ state <= 3'h6;
+ end else begin
+ if(T_1883) begin
+ state <= T_1887;
+ end else begin
+ if(T_1882) begin
+ state <= 2'h3;
+ end else begin
+ if(T_1880) begin
+ state <= 3'h4;
+ end else begin
+ if(T_1878) begin
+ state <= 3'h5;
+ end else begin
+ if(T_1877) begin
+ if(refill_done) begin
+ state <= 3'h6;
+ end else begin
+ if(T_1876) begin
+ state <= 3'h7;
+ end else begin
+ if(T_1874) begin
+ state <= 4'h8;
+ end else begin
+ if(T_1873) begin
+ state <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1876) begin
+ state <= 3'h7;
+ end else begin
+ if(T_1874) begin
+ state <= 4'h8;
+ end else begin
+ if(T_1873) begin
+ state <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1883) begin
+ state <= T_1887;
+ end else begin
+ if(T_1882) begin
+ state <= 2'h3;
+ end else begin
+ if(T_1880) begin
+ state <= 3'h4;
+ end else begin
+ if(T_1878) begin
+ state <= 3'h5;
+ end else begin
+ if(T_1877) begin
+ if(refill_done) begin
+ state <= 3'h6;
+ end else begin
+ if(T_1876) begin
+ state <= 3'h7;
+ end else begin
+ if(T_1874) begin
+ state <= 4'h8;
+ end else begin
+ if(T_1873) begin
+ state <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1876) begin
+ state <= 3'h7;
+ end else begin
+ if(T_1874) begin
+ state <= 4'h8;
+ end else begin
+ if(T_1873) begin
+ state <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1883) begin
+ state <= T_1887;
+ end else begin
+ if(T_1882) begin
+ state <= 2'h3;
+ end else begin
+ if(T_1880) begin
+ state <= 3'h4;
+ end else begin
+ if(T_1878) begin
+ state <= 3'h5;
+ end else begin
+ if(T_1877) begin
+ if(refill_done) begin
+ state <= 3'h6;
+ end else begin
+ if(T_1876) begin
+ state <= 3'h7;
+ end else begin
+ if(T_1874) begin
+ state <= 4'h8;
+ end else begin
+ if(T_1873) begin
+ state <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1876) begin
+ state <= 3'h7;
+ end else begin
+ if(T_1874) begin
+ state <= 4'h8;
+ end else begin
+ if(T_1873) begin
+ state <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ if(reset) begin
+ new_coh_state_state <= T_1277_state;
+ end else begin
+ if(T_1889) begin
+ if(io_req_bits_tag_match) begin
+ if(T_1924) begin
+ new_coh_state_state <= coh_on_hit_state;
+ end else begin
+ if(T_1877) begin
+ if(io_mem_grant_valid) begin
+ new_coh_state_state <= coh_on_grant_state;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1877) begin
+ if(io_mem_grant_valid) begin
+ new_coh_state_state <= coh_on_grant_state;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1877) begin
+ if(io_mem_grant_valid) begin
+ new_coh_state_state <= coh_on_grant_state;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1889) begin
+ req_addr <= io_req_bits_addr;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1889) begin
+ req_tag <= io_req_bits_tag;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1889) begin
+ req_cmd <= io_req_bits_cmd;
+ end else begin
+ if(T_1888) begin
+ if(cmd_requires_second_acquire) begin
+ req_cmd <= io_req_bits_cmd;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1889) begin
+ req_typ <= io_req_bits_typ;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1889) begin
+ req_kill <= io_req_bits_kill;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1889) begin
+ req_phys <= io_req_bits_phys;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1889) begin
+ req_sdq_id <= io_req_bits_sdq_id;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1889) begin
+ req_tag_match <= io_req_bits_tag_match;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1889) begin
+ req_old_meta_tag <= io_req_bits_old_meta_tag;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1889) begin
+ req_old_meta_coh_state <= io_req_bits_old_meta_coh_state;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1889) begin
+ req_way_en <= io_req_bits_way_en;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ refill_cnt <= 2'h0;
+ end else begin
+ if(T_1662) begin
+ refill_cnt <= T_1673;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ meta_hazard <= 2'h0;
+ end else begin
+ if(T_1951) begin
+ meta_hazard <= 1'h1;
+ end else begin
+ if(T_1947) begin
+ meta_hazard <= T_1950;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+endmodule
+module Arbiter_101(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input io_in_0_bits,
+ input io_out_ready,
+ output io_out_valid,
+ output io_out_bits,
+ output io_chosen
+);
+ wire T_54;
+ wire GEN_0;
+ wire GEN_1;
+ wire GEN_2;
+ wire T_73;
+ wire T_74;
+ wire T_75;
+ wire T_77;
+ assign io_in_0_ready = T_75;
+ assign io_out_valid = GEN_0;
+ assign io_out_bits = GEN_1;
+ assign io_chosen = T_54;
+ assign T_54 = T_77;
+ assign GEN_0 = io_in_0_valid;
+ assign GEN_1 = io_in_0_bits;
+ assign GEN_2 = 1'h0;
+ assign T_73 = 1'h0 == 1'h0;
+ assign T_74 = 1'h0 ? T_73 : 1'h1;
+ assign T_75 = T_74 & io_out_ready;
+ assign T_77 = 1'h0 ? 1'h0 : 1'h0;
+endmodule
+module Arbiter_102(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input [39:0] io_in_0_bits_addr,
+ input [8:0] io_in_0_bits_tag,
+ input [4:0] io_in_0_bits_cmd,
+ input [2:0] io_in_0_bits_typ,
+ input [63:0] io_in_0_bits_data,
+ input io_in_0_bits_nack,
+ input io_in_0_bits_replay,
+ input io_in_0_bits_has_data,
+ input [63:0] io_in_0_bits_data_word_bypass,
+ input [63:0] io_in_0_bits_store_data,
+ input io_out_ready,
+ output io_out_valid,
+ output [39:0] io_out_bits_addr,
+ output [8:0] io_out_bits_tag,
+ output [4:0] io_out_bits_cmd,
+ output [2:0] io_out_bits_typ,
+ output [63:0] io_out_bits_data,
+ output io_out_bits_nack,
+ output io_out_bits_replay,
+ output io_out_bits_has_data,
+ output [63:0] io_out_bits_data_word_bypass,
+ output [63:0] io_out_bits_store_data,
+ output io_chosen
+);
+ wire T_1062;
+ wire GEN_0;
+ wire [39:0] GEN_1;
+ wire [8:0] GEN_2;
+ wire [4:0] GEN_3;
+ wire [2:0] GEN_4;
+ wire [63:0] GEN_5;
+ wire GEN_6;
+ wire GEN_7;
+ wire GEN_8;
+ wire [63:0] GEN_9;
+ wire [63:0] GEN_10;
+ wire GEN_11;
+ wire T_1417;
+ wire T_1418;
+ wire T_1419;
+ wire T_1421;
+ assign io_in_0_ready = T_1419;
+ assign io_out_valid = GEN_0;
+ assign io_out_bits_addr = GEN_1;
+ assign io_out_bits_tag = GEN_2;
+ assign io_out_bits_cmd = GEN_3;
+ assign io_out_bits_typ = GEN_4;
+ assign io_out_bits_data = GEN_5;
+ assign io_out_bits_nack = GEN_6;
+ assign io_out_bits_replay = GEN_7;
+ assign io_out_bits_has_data = GEN_8;
+ assign io_out_bits_data_word_bypass = GEN_9;
+ assign io_out_bits_store_data = GEN_10;
+ assign io_chosen = T_1062;
+ assign T_1062 = T_1421;
+ assign GEN_0 = io_in_0_valid;
+ assign GEN_1 = io_in_0_bits_addr;
+ assign GEN_2 = io_in_0_bits_tag;
+ assign GEN_3 = io_in_0_bits_cmd;
+ assign GEN_4 = io_in_0_bits_typ;
+ assign GEN_5 = io_in_0_bits_data;
+ assign GEN_6 = io_in_0_bits_nack;
+ assign GEN_7 = io_in_0_bits_replay;
+ assign GEN_8 = io_in_0_bits_has_data;
+ assign GEN_9 = io_in_0_bits_data_word_bypass;
+ assign GEN_10 = io_in_0_bits_store_data;
+ assign GEN_11 = 1'h0;
+ assign T_1417 = 1'h0 == 1'h0;
+ assign T_1418 = 1'h0 ? T_1417 : 1'h1;
+ assign T_1419 = T_1418 & io_out_ready;
+ assign T_1421 = 1'h0 ? 1'h0 : 1'h0;
+endmodule
+module IOMSHR(
+ input clk,
+ input reset,
+ output io_req_ready,
+ input io_req_valid,
+ input [39:0] io_req_bits_addr,
+ input [8:0] io_req_bits_tag,
+ input [4:0] io_req_bits_cmd,
+ input [2:0] io_req_bits_typ,
+ input io_req_bits_kill,
+ input io_req_bits_phys,
+ input [63:0] io_req_bits_data,
+ input io_acquire_ready,
+ output io_acquire_valid,
+ output [25:0] io_acquire_bits_addr_block,
+ output [1:0] io_acquire_bits_client_xact_id,
+ output [1:0] io_acquire_bits_addr_beat,
+ output io_acquire_bits_is_builtin_type,
+ output [2:0] io_acquire_bits_a_type,
+ output [16:0] io_acquire_bits_union,
+ output [127:0] io_acquire_bits_data,
+ input io_grant_valid,
+ input [1:0] io_grant_bits_addr_beat,
+ input [1:0] io_grant_bits_client_xact_id,
+ input [3:0] io_grant_bits_manager_xact_id,
+ input io_grant_bits_is_builtin_type,
+ input [3:0] io_grant_bits_g_type,
+ input [127:0] io_grant_bits_data,
+ input io_resp_ready,
+ output io_resp_valid,
+ output [39:0] io_resp_bits_addr,
+ output [8:0] io_resp_bits_tag,
+ output [4:0] io_resp_bits_cmd,
+ output [2:0] io_resp_bits_typ,
+ output [63:0] io_resp_bits_data,
+ output io_resp_bits_nack,
+ output io_resp_bits_replay,
+ output io_resp_bits_has_data,
+ output [63:0] io_resp_bits_data_word_bypass,
+ output [63:0] io_resp_bits_store_data
+);
+ reg [39:0] req_addr;
+ reg [8:0] req_tag;
+ reg [4:0] req_cmd;
+ reg [2:0] req_typ;
+ reg req_kill;
+ reg req_phys;
+ reg [63:0] req_data;
+ wire req_cmd_sc;
+ reg [63:0] grant_word;
+ wire [1:0] T_861;
+ wire [1:0] T_862;
+ wire [2:0] T_863;
+ wire GEN_0;
+ wire T_865;
+ wire beat_offset;
+ wire T_868;
+ wire T_870;
+ wire T_872;
+ wire T_875;
+ wire T_876;
+ wire T_877;
+ wire T_879;
+ wire [1:0] T_880;
+ wire T_881;
+ wire [1:0] T_883;
+ wire T_885;
+ wire [1:0] T_888;
+ wire [1:0] T_889;
+ wire T_890;
+ wire [1:0] T_892;
+ wire [3:0] T_893;
+ wire T_894;
+ wire [3:0] T_896;
+ wire T_898;
+ wire [3:0] T_901;
+ wire [3:0] T_902;
+ wire T_903;
+ wire [3:0] T_905;
+ wire [7:0] T_906;
+ wire [3:0] T_908;
+ wire [22:0] beat_mask;
+ wire T_911;
+ wire [7:0] T_912;
+ wire [15:0] T_913;
+ wire [31:0] T_914;
+ wire [63:0] T_915;
+ wire T_917;
+ wire [15:0] T_918;
+ wire [31:0] T_919;
+ wire [63:0] T_920;
+ wire T_922;
+ wire [31:0] T_923;
+ wire [63:0] T_924;
+ wire [63:0] T_925;
+ wire [63:0] T_926;
+ wire [63:0] T_927;
+ wire [127:0] beat_data;
+ reg [1:0] state;
+ wire T_935;
+ wire [25:0] addr_block;
+ wire [1:0] addr_beat;
+ wire [3:0] addr_byte;
+ wire [6:0] T_947;
+ wire [5:0] T_948;
+ wire [12:0] T_949;
+ wire [5:0] T_951;
+ wire [8:0] T_952;
+ wire [1:0] T_954;
+ wire [1:0] T_956;
+ wire [6:0] T_958;
+ wire [5:0] T_959;
+ wire [12:0] T_960;
+ wire [5:0] T_962;
+ wire [5:0] T_964;
+ wire T_965;
+ wire [5:0] T_966;
+ wire T_967;
+ wire [5:0] T_968;
+ wire T_969;
+ wire [12:0] T_970;
+ wire T_971;
+ wire [12:0] T_972;
+ wire T_973;
+ wire [12:0] T_974;
+ wire T_975;
+ wire [12:0] T_976;
+ wire T_977;
+ wire [12:0] T_978;
+ wire [25:0] get_acquire_addr_block;
+ wire [1:0] get_acquire_client_xact_id;
+ wire [1:0] get_acquire_addr_beat;
+ wire get_acquire_is_builtin_type;
+ wire [2:0] get_acquire_a_type;
+ wire [16:0] get_acquire_union;
+ wire [127:0] get_acquire_data;
+ wire [3:0] T_1049;
+ wire [1:0] T_1050;
+ wire [5:0] T_1051;
+ wire [1:0] T_1053;
+ wire [4:0] T_1054;
+ wire [23:0] T_1056;
+ wire [23:0] T_1058;
+ wire [3:0] T_1060;
+ wire [1:0] T_1061;
+ wire [5:0] T_1062;
+ wire [5:0] T_1064;
+ wire [5:0] T_1066;
+ wire T_1067;
+ wire [5:0] T_1068;
+ wire T_1069;
+ wire [5:0] T_1070;
+ wire T_1071;
+ wire [5:0] T_1072;
+ wire T_1073;
+ wire [23:0] T_1074;
+ wire T_1075;
+ wire [23:0] T_1076;
+ wire T_1077;
+ wire [23:0] T_1078;
+ wire T_1079;
+ wire [23:0] T_1080;
+ wire [25:0] put_acquire_addr_block;
+ wire [1:0] put_acquire_client_xact_id;
+ wire [1:0] put_acquire_addr_beat;
+ wire put_acquire_is_builtin_type;
+ wire [2:0] put_acquire_a_type;
+ wire [16:0] put_acquire_union;
+ wire [127:0] put_acquire_data;
+ wire T_1143;
+ wire T_1144;
+ wire T_1145;
+ wire T_1146;
+ wire T_1147;
+ wire T_1148;
+ wire T_1149;
+ wire T_1150;
+ wire T_1151;
+ wire T_1152;
+ wire [25:0] T_1153_addr_block;
+ wire [1:0] T_1153_client_xact_id;
+ wire [1:0] T_1153_addr_beat;
+ wire T_1153_is_builtin_type;
+ wire [2:0] T_1153_a_type;
+ wire [16:0] T_1153_union;
+ wire [127:0] T_1153_data;
+ wire T_1184;
+ wire T_1185;
+ wire T_1186;
+ wire T_1187;
+ wire T_1188;
+ wire T_1189;
+ wire T_1190;
+ wire T_1191;
+ wire T_1192;
+ wire T_1193;
+ wire T_1194;
+ wire [31:0] T_1195;
+ wire [31:0] T_1196;
+ wire [31:0] T_1197;
+ wire T_1199;
+ wire [31:0] T_1201;
+ wire T_1203;
+ wire T_1204;
+ wire T_1205;
+ wire T_1206;
+ wire [32:0] T_1208;
+ wire [31:0] T_1209;
+ wire [31:0] T_1210;
+ wire [31:0] T_1211;
+ wire [63:0] T_1212;
+ wire T_1213;
+ wire [15:0] T_1214;
+ wire [15:0] T_1215;
+ wire [15:0] T_1216;
+ wire T_1218;
+ wire [15:0] T_1220;
+ wire T_1222;
+ wire T_1223;
+ wire T_1224;
+ wire T_1225;
+ wire [48:0] T_1227;
+ wire [47:0] T_1228;
+ wire [47:0] T_1229;
+ wire [47:0] T_1230;
+ wire [63:0] T_1231;
+ wire T_1232;
+ wire [7:0] T_1233;
+ wire [7:0] T_1234;
+ wire [7:0] T_1235;
+ wire T_1237;
+ wire [7:0] T_1239;
+ wire T_1241;
+ wire T_1242;
+ wire T_1243;
+ wire T_1244;
+ wire [56:0] T_1246;
+ wire [55:0] T_1247;
+ wire [55:0] T_1248;
+ wire [55:0] T_1249;
+ wire [63:0] T_1250;
+ wire [63:0] T_1251;
+ wire T_1253;
+ wire T_1254;
+ wire T_1255;
+ wire T_1256;
+ wire T_1257;
+ wire T_1258;
+ wire T_1259;
+ wire T_1260;
+ wire T_1261;
+ wire T_1262;
+ wire T_1263;
+ wire T_1264;
+ wire T_1265;
+ wire T_1266;
+ wire [6:0] T_1268;
+ wire [127:0] T_1269;
+ wire [63:0] T_1270;
+ wire T_1272;
+ wire T_1273;
+ reg [63:0] GEN_1;
+ assign io_req_ready = T_935;
+ assign io_acquire_valid = T_1143;
+ assign io_acquire_bits_addr_block = T_1153_addr_block;
+ assign io_acquire_bits_client_xact_id = T_1153_client_xact_id;
+ assign io_acquire_bits_addr_beat = T_1153_addr_beat;
+ assign io_acquire_bits_is_builtin_type = T_1153_is_builtin_type;
+ assign io_acquire_bits_a_type = T_1153_a_type;
+ assign io_acquire_bits_union = T_1153_union;
+ assign io_acquire_bits_data = T_1153_data;
+ assign io_resp_valid = T_1184;
+ assign io_resp_bits_addr = req_addr;
+ assign io_resp_bits_tag = req_tag;
+ assign io_resp_bits_cmd = req_cmd;
+ assign io_resp_bits_typ = req_typ;
+ assign io_resp_bits_data = T_1251;
+ assign io_resp_bits_nack = 1'h0;
+ assign io_resp_bits_replay = io_resp_valid;
+ assign io_resp_bits_has_data = T_1193;
+ assign io_resp_bits_data_word_bypass = GEN_1;
+ assign io_resp_bits_store_data = req_data;
+ assign req_cmd_sc = req_cmd == 5'h7;
+ assign T_861 = req_typ[1:0];
+ assign T_862 = req_typ[1:0];
+ assign T_863 = $signed(req_typ);
+ assign GEN_0 = $signed(1'h0);
+ assign T_865 = $signed(T_863) >= $signed(GEN_0);
+ assign beat_offset = req_addr[3];
+ assign T_868 = req_addr[0];
+ assign T_870 = T_868 ? 1'h1 : 1'h0;
+ assign T_872 = T_861 >= 1'h1;
+ assign T_875 = T_872 ? 1'h1 : 1'h0;
+ assign T_876 = T_870 | T_875;
+ assign T_877 = req_addr[0];
+ assign T_879 = T_877 ? 1'h0 : 1'h1;
+ assign T_880 = {T_876,T_879};
+ assign T_881 = req_addr[1];
+ assign T_883 = T_881 ? T_880 : 1'h0;
+ assign T_885 = T_861 >= 2'h2;
+ assign T_888 = T_885 ? 2'h3 : 1'h0;
+ assign T_889 = T_883 | T_888;
+ assign T_890 = req_addr[1];
+ assign T_892 = T_890 ? 1'h0 : T_880;
+ assign T_893 = {T_889,T_892};
+ assign T_894 = req_addr[2];
+ assign T_896 = T_894 ? T_893 : 1'h0;
+ assign T_898 = T_861 >= 2'h3;
+ assign T_901 = T_898 ? 4'hf : 1'h0;
+ assign T_902 = T_896 | T_901;
+ assign T_903 = req_addr[2];
+ assign T_905 = T_903 ? 1'h0 : T_893;
+ assign T_906 = {T_902,T_905};
+ assign T_908 = {beat_offset,3'h0};
+ assign beat_mask = T_906 << T_908;
+ assign T_911 = T_861 == 1'h0;
+ assign T_912 = req_data[7:0];
+ assign T_913 = {T_912,T_912};
+ assign T_914 = {T_913,T_913};
+ assign T_915 = {T_914,T_914};
+ assign T_917 = T_861 == 1'h1;
+ assign T_918 = req_data[15:0];
+ assign T_919 = {T_918,T_918};
+ assign T_920 = {T_919,T_919};
+ assign T_922 = T_861 == 2'h2;
+ assign T_923 = req_data[31:0];
+ assign T_924 = {T_923,T_923};
+ assign T_925 = T_922 ? T_924 : req_data;
+ assign T_926 = T_917 ? T_920 : T_925;
+ assign T_927 = T_911 ? T_915 : T_926;
+ assign beat_data = {T_927,T_927};
+ assign T_935 = state == 1'h0;
+ assign addr_block = req_addr[31:6];
+ assign addr_beat = req_addr[5:4];
+ assign addr_byte = req_addr[3:0];
+ assign T_947 = {addr_byte,req_typ};
+ assign T_948 = {5'h0,1'h0};
+ assign T_949 = {T_947,T_948};
+ assign T_951 = {5'h0,1'h0};
+ assign T_952 = {req_typ,T_951};
+ assign T_954 = {1'h0,1'h0};
+ assign T_956 = {1'h0,1'h0};
+ assign T_958 = {addr_byte,req_typ};
+ assign T_959 = {5'h0,1'h0};
+ assign T_960 = {T_958,T_959};
+ assign T_962 = {5'h0,1'h0};
+ assign T_964 = {5'h1,1'h0};
+ assign T_965 = 3'h6 == 3'h0;
+ assign T_966 = T_965 ? T_964 : 1'h0;
+ assign T_967 = 3'h5 == 3'h0;
+ assign T_968 = T_967 ? T_962 : T_966;
+ assign T_969 = 3'h4 == 3'h0;
+ assign T_970 = T_969 ? T_960 : T_968;
+ assign T_971 = 3'h3 == 3'h0;
+ assign T_972 = T_971 ? T_956 : T_970;
+ assign T_973 = 3'h2 == 3'h0;
+ assign T_974 = T_973 ? T_954 : T_972;
+ assign T_975 = 3'h1 == 3'h0;
+ assign T_976 = T_975 ? T_952 : T_974;
+ assign T_977 = 3'h0 == 3'h0;
+ assign T_978 = T_977 ? T_949 : T_976;
+ assign get_acquire_addr_block = addr_block;
+ assign get_acquire_client_xact_id = 2'h2;
+ assign get_acquire_addr_beat = addr_beat;
+ assign get_acquire_is_builtin_type = 1'h1;
+ assign get_acquire_a_type = 3'h0;
+ assign get_acquire_union = T_978;
+ assign get_acquire_data = 1'h0;
+ assign T_1049 = {1'h0,3'h7};
+ assign T_1050 = {1'h0,1'h0};
+ assign T_1051 = {T_1049,T_1050};
+ assign T_1053 = {1'h0,1'h0};
+ assign T_1054 = {3'h7,T_1053};
+ assign T_1056 = {beat_mask,1'h0};
+ assign T_1058 = {beat_mask,1'h0};
+ assign T_1060 = {1'h0,3'h7};
+ assign T_1061 = {1'h0,1'h0};
+ assign T_1062 = {T_1060,T_1061};
+ assign T_1064 = {5'h0,1'h0};
+ assign T_1066 = {5'h1,1'h0};
+ assign T_1067 = 3'h6 == 3'h2;
+ assign T_1068 = T_1067 ? T_1066 : 1'h0;
+ assign T_1069 = 3'h5 == 3'h2;
+ assign T_1070 = T_1069 ? T_1064 : T_1068;
+ assign T_1071 = 3'h4 == 3'h2;
+ assign T_1072 = T_1071 ? T_1062 : T_1070;
+ assign T_1073 = 3'h3 == 3'h2;
+ assign T_1074 = T_1073 ? T_1058 : T_1072;
+ assign T_1075 = 3'h2 == 3'h2;
+ assign T_1076 = T_1075 ? T_1056 : T_1074;
+ assign T_1077 = 3'h1 == 3'h2;
+ assign T_1078 = T_1077 ? T_1054 : T_1076;
+ assign T_1079 = 3'h0 == 3'h2;
+ assign T_1080 = T_1079 ? T_1051 : T_1078;
+ assign put_acquire_addr_block = addr_block;
+ assign put_acquire_client_xact_id = 2'h2;
+ assign put_acquire_addr_beat = addr_beat;
+ assign put_acquire_is_builtin_type = 1'h1;
+ assign put_acquire_a_type = 3'h2;
+ assign put_acquire_union = T_1080;
+ assign put_acquire_data = beat_data;
+ assign T_1143 = state == 1'h1;
+ assign T_1144 = req_cmd == 5'h0;
+ assign T_1145 = req_cmd == 5'h6;
+ assign T_1146 = T_1144 | T_1145;
+ assign T_1147 = req_cmd == 5'h7;
+ assign T_1148 = T_1146 | T_1147;
+ assign T_1149 = req_cmd[3];
+ assign T_1150 = req_cmd == 5'h4;
+ assign T_1151 = T_1149 | T_1150;
+ assign T_1152 = T_1148 | T_1151;
+ assign T_1153_addr_block = T_1152 ? get_acquire_addr_block : put_acquire_addr_block;
+ assign T_1153_client_xact_id = T_1152 ? get_acquire_client_xact_id : put_acquire_client_xact_id;
+ assign T_1153_addr_beat = T_1152 ? get_acquire_addr_beat : put_acquire_addr_beat;
+ assign T_1153_is_builtin_type = T_1152 ? get_acquire_is_builtin_type : put_acquire_is_builtin_type;
+ assign T_1153_a_type = T_1152 ? get_acquire_a_type : put_acquire_a_type;
+ assign T_1153_union = T_1152 ? get_acquire_union : put_acquire_union;
+ assign T_1153_data = T_1152 ? get_acquire_data : put_acquire_data;
+ assign T_1184 = state == 2'h3;
+ assign T_1185 = req_cmd == 5'h0;
+ assign T_1186 = req_cmd == 5'h6;
+ assign T_1187 = T_1185 | T_1186;
+ assign T_1188 = req_cmd == 5'h7;
+ assign T_1189 = T_1187 | T_1188;
+ assign T_1190 = req_cmd[3];
+ assign T_1191 = req_cmd == 5'h4;
+ assign T_1192 = T_1190 | T_1191;
+ assign T_1193 = T_1189 | T_1192;
+ assign T_1194 = req_addr[2];
+ assign T_1195 = grant_word[63:32];
+ assign T_1196 = grant_word[31:0];
+ assign T_1197 = T_1194 ? T_1195 : T_1196;
+ assign T_1199 = 1'h0 & req_cmd_sc;
+ assign T_1201 = T_1199 ? 1'h0 : T_1197;
+ assign T_1203 = T_862 == 2'h2;
+ assign T_1204 = T_1203 | T_1199;
+ assign T_1205 = T_1201[31];
+ assign T_1206 = T_865 & T_1205;
+ assign T_1208 = 32'h0 - T_1206;
+ assign T_1209 = T_1208[31:0];
+ assign T_1210 = grant_word[63:32];
+ assign T_1211 = T_1204 ? T_1209 : T_1210;
+ assign T_1212 = {T_1211,T_1201};
+ assign T_1213 = req_addr[1];
+ assign T_1214 = T_1212[31:16];
+ assign T_1215 = T_1212[15:0];
+ assign T_1216 = T_1213 ? T_1214 : T_1215;
+ assign T_1218 = 1'h0 & req_cmd_sc;
+ assign T_1220 = T_1218 ? 1'h0 : T_1216;
+ assign T_1222 = T_862 == 1'h1;
+ assign T_1223 = T_1222 | T_1218;
+ assign T_1224 = T_1220[15];
+ assign T_1225 = T_865 & T_1224;
+ assign T_1227 = 48'h0 - T_1225;
+ assign T_1228 = T_1227[47:0];
+ assign T_1229 = T_1212[63:16];
+ assign T_1230 = T_1223 ? T_1228 : T_1229;
+ assign T_1231 = {T_1230,T_1220};
+ assign T_1232 = req_addr[0];
+ assign T_1233 = T_1231[15:8];
+ assign T_1234 = T_1231[7:0];
+ assign T_1235 = T_1232 ? T_1233 : T_1234;
+ assign T_1237 = 1'h1 & req_cmd_sc;
+ assign T_1239 = T_1237 ? 1'h0 : T_1235;
+ assign T_1241 = T_862 == 1'h0;
+ assign T_1242 = T_1241 | T_1237;
+ assign T_1243 = T_1239[7];
+ assign T_1244 = T_865 & T_1243;
+ assign T_1246 = 56'h0 - T_1244;
+ assign T_1247 = T_1246[55:0];
+ assign T_1248 = T_1231[63:8];
+ assign T_1249 = T_1242 ? T_1247 : T_1248;
+ assign T_1250 = {T_1249,T_1239};
+ assign T_1251 = T_1250 | req_cmd_sc;
+ assign T_1253 = io_req_ready & io_req_valid;
+ assign T_1254 = io_acquire_ready & io_acquire_valid;
+ assign T_1255 = state == 2'h2;
+ assign T_1256 = T_1255 & io_grant_valid;
+ assign T_1257 = req_cmd == 5'h0;
+ assign T_1258 = req_cmd == 5'h6;
+ assign T_1259 = T_1257 | T_1258;
+ assign T_1260 = req_cmd == 5'h7;
+ assign T_1261 = T_1259 | T_1260;
+ assign T_1262 = req_cmd[3];
+ assign T_1263 = req_cmd == 5'h4;
+ assign T_1264 = T_1262 | T_1263;
+ assign T_1265 = T_1261 | T_1264;
+ assign T_1266 = req_addr[3];
+ assign T_1268 = {T_1266,6'h0};
+ assign T_1269 = io_grant_bits_data >> T_1268;
+ assign T_1270 = T_1269[63:0];
+ assign T_1272 = T_1265 == 1'h0;
+ assign T_1273 = io_resp_ready & io_resp_valid;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ req_addr = {2{$random}};
+ req_tag = {1{$random}};
+ req_cmd = {1{$random}};
+ req_typ = {1{$random}};
+ req_kill = {1{$random}};
+ req_phys = {1{$random}};
+ req_data = {2{$random}};
+ grant_word = {2{$random}};
+ state = {1{$random}};
+ GEN_1 = {2{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1253) begin
+ req_addr <= io_req_bits_addr;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1253) begin
+ req_tag <= io_req_bits_tag;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1253) begin
+ req_cmd <= io_req_bits_cmd;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1253) begin
+ req_typ <= io_req_bits_typ;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1253) begin
+ req_kill <= io_req_bits_kill;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1253) begin
+ req_phys <= io_req_bits_phys;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1253) begin
+ req_data <= io_req_bits_data;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1256) begin
+ if(T_1265) begin
+ grant_word <= T_1270;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1273) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1256) begin
+ if(T_1272) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1265) begin
+ state <= 2'h3;
+ end else begin
+ if(T_1254) begin
+ state <= 2'h2;
+ end else begin
+ if(T_1253) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1254) begin
+ state <= 2'h2;
+ end else begin
+ if(T_1253) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+endmodule
+module MSHRFile(
+ input clk,
+ input reset,
+ output io_req_ready,
+ input io_req_valid,
+ input [39:0] io_req_bits_addr,
+ input [8:0] io_req_bits_tag,
+ input [4:0] io_req_bits_cmd,
+ input [2:0] io_req_bits_typ,
+ input io_req_bits_kill,
+ input io_req_bits_phys,
+ input [63:0] io_req_bits_data,
+ input io_req_bits_tag_match,
+ input [19:0] io_req_bits_old_meta_tag,
+ input [1:0] io_req_bits_old_meta_coh_state,
+ input [3:0] io_req_bits_way_en,
+ input io_resp_ready,
+ output io_resp_valid,
+ output [39:0] io_resp_bits_addr,
+ output [8:0] io_resp_bits_tag,
+ output [4:0] io_resp_bits_cmd,
+ output [2:0] io_resp_bits_typ,
+ output [63:0] io_resp_bits_data,
+ output io_resp_bits_nack,
+ output io_resp_bits_replay,
+ output io_resp_bits_has_data,
+ output [63:0] io_resp_bits_data_word_bypass,
+ output [63:0] io_resp_bits_store_data,
+ output io_secondary_miss,
+ input io_mem_req_ready,
+ output io_mem_req_valid,
+ output [25:0] io_mem_req_bits_addr_block,
+ output [1:0] io_mem_req_bits_client_xact_id,
+ output [1:0] io_mem_req_bits_addr_beat,
+ output io_mem_req_bits_is_builtin_type,
+ output [2:0] io_mem_req_bits_a_type,
+ output [16:0] io_mem_req_bits_union,
+ output [127:0] io_mem_req_bits_data,
+ output [3:0] io_refill_way_en,
+ output [11:0] io_refill_addr,
+ input io_meta_read_ready,
+ output io_meta_read_valid,
+ output [5:0] io_meta_read_bits_idx,
+ output [19:0] io_meta_read_bits_tag,
+ input io_meta_write_ready,
+ output io_meta_write_valid,
+ output [5:0] io_meta_write_bits_idx,
+ output [3:0] io_meta_write_bits_way_en,
+ output [19:0] io_meta_write_bits_data_tag,
+ output [1:0] io_meta_write_bits_data_coh_state,
+ input io_replay_ready,
+ output io_replay_valid,
+ output [39:0] io_replay_bits_addr,
+ output [8:0] io_replay_bits_tag,
+ output [4:0] io_replay_bits_cmd,
+ output [2:0] io_replay_bits_typ,
+ output io_replay_bits_kill,
+ output io_replay_bits_phys,
+ output [63:0] io_replay_bits_data,
+ input io_mem_grant_valid,
+ input [1:0] io_mem_grant_bits_addr_beat,
+ input [1:0] io_mem_grant_bits_client_xact_id,
+ input [3:0] io_mem_grant_bits_manager_xact_id,
+ input io_mem_grant_bits_is_builtin_type,
+ input [3:0] io_mem_grant_bits_g_type,
+ input [127:0] io_mem_grant_bits_data,
+ input io_wb_req_ready,
+ output io_wb_req_valid,
+ output [1:0] io_wb_req_bits_addr_beat,
+ output [25:0] io_wb_req_bits_addr_block,
+ output [1:0] io_wb_req_bits_client_xact_id,
+ output io_wb_req_bits_voluntary,
+ output [2:0] io_wb_req_bits_r_type,
+ output [127:0] io_wb_req_bits_data,
+ output [3:0] io_wb_req_bits_way_en,
+ output io_probe_rdy,
+ output io_fence_rdy
+);
+ wire cacheable;
+ reg [16:0] sdq_val;
+ wire [16:0] T_1807;
+ wire [16:0] T_1808;
+ wire T_1809;
+ wire T_1810;
+ wire T_1811;
+ wire T_1812;
+ wire T_1813;
+ wire T_1814;
+ wire T_1815;
+ wire T_1816;
+ wire T_1817;
+ wire T_1818;
+ wire T_1819;
+ wire T_1820;
+ wire T_1821;
+ wire T_1822;
+ wire T_1823;
+ wire T_1824;
+ wire T_1825;
+ wire T_1827_0;
+ wire T_1827_1;
+ wire T_1827_2;
+ wire T_1827_3;
+ wire T_1827_4;
+ wire T_1827_5;
+ wire T_1827_6;
+ wire T_1827_7;
+ wire T_1827_8;
+ wire T_1827_9;
+ wire T_1827_10;
+ wire T_1827_11;
+ wire T_1827_12;
+ wire T_1827_13;
+ wire T_1827_14;
+ wire T_1827_15;
+ wire T_1827_16;
+ wire [4:0] T_1863;
+ wire [4:0] T_1864;
+ wire [4:0] T_1865;
+ wire [4:0] T_1866;
+ wire [4:0] T_1867;
+ wire [4:0] T_1868;
+ wire [4:0] T_1869;
+ wire [4:0] T_1870;
+ wire [4:0] T_1871;
+ wire [4:0] T_1872;
+ wire [4:0] T_1873;
+ wire [4:0] T_1874;
+ wire [4:0] T_1875;
+ wire [4:0] T_1876;
+ wire [4:0] T_1877;
+ wire [4:0] sdq_alloc_id;
+ wire [16:0] T_1879;
+ wire T_1881;
+ wire sdq_rdy;
+ wire T_1884;
+ wire T_1885;
+ wire T_1886;
+ wire T_1887;
+ wire T_1888;
+ wire T_1889;
+ wire T_1890;
+ wire T_1891;
+ wire T_1892;
+ wire sdq_enq;
+ reg [63:0] sdq [0:16];
+ wire [63:0] sdq_T_2888_data;
+ wire [4:0] sdq_T_2888_addr;
+ wire sdq_T_2888_en;
+ wire sdq_T_2888_clk;
+ wire [63:0] sdq_T_1896_data;
+ wire [4:0] sdq_T_1896_addr;
+ wire sdq_T_1896_mask;
+ wire sdq_T_1896_en;
+ wire sdq_T_1896_clk;
+ wire idxMatch_0;
+ wire idxMatch_1;
+ wire [19:0] tagList_0;
+ wire [19:0] tagList_1;
+ wire [19:0] T_1922;
+ wire [19:0] T_1924;
+ wire [19:0] T_1926;
+ wire [19:0] T_1927;
+ wire [27:0] T_1928;
+ wire tag_match;
+ wire [19:0] wbTagList_0;
+ wire [19:0] wbTagList_1;
+ wire [3:0] refillMux_0_way_en;
+ wire [11:0] refillMux_0_addr;
+ wire [3:0] refillMux_1_way_en;
+ wire [11:0] refillMux_1_addr;
+ wire meta_read_arb_clk;
+ wire meta_read_arb_reset;
+ wire meta_read_arb_io_in_0_ready;
+ wire meta_read_arb_io_in_0_valid;
+ wire [5:0] meta_read_arb_io_in_0_bits_idx;
+ wire [19:0] meta_read_arb_io_in_0_bits_tag;
+ wire meta_read_arb_io_in_1_ready;
+ wire meta_read_arb_io_in_1_valid;
+ wire [5:0] meta_read_arb_io_in_1_bits_idx;
+ wire [19:0] meta_read_arb_io_in_1_bits_tag;
+ wire meta_read_arb_io_out_ready;
+ wire meta_read_arb_io_out_valid;
+ wire [5:0] meta_read_arb_io_out_bits_idx;
+ wire [19:0] meta_read_arb_io_out_bits_tag;
+ wire meta_read_arb_io_chosen;
+ wire meta_write_arb_clk;
+ wire meta_write_arb_reset;
+ wire meta_write_arb_io_in_0_ready;
+ wire meta_write_arb_io_in_0_valid;
+ wire [5:0] meta_write_arb_io_in_0_bits_idx;
+ wire [3:0] meta_write_arb_io_in_0_bits_way_en;
+ wire [19:0] meta_write_arb_io_in_0_bits_data_tag;
+ wire [1:0] meta_write_arb_io_in_0_bits_data_coh_state;
+ wire meta_write_arb_io_in_1_ready;
+ wire meta_write_arb_io_in_1_valid;
+ wire [5:0] meta_write_arb_io_in_1_bits_idx;
+ wire [3:0] meta_write_arb_io_in_1_bits_way_en;
+ wire [19:0] meta_write_arb_io_in_1_bits_data_tag;
+ wire [1:0] meta_write_arb_io_in_1_bits_data_coh_state;
+ wire meta_write_arb_io_out_ready;
+ wire meta_write_arb_io_out_valid;
+ wire [5:0] meta_write_arb_io_out_bits_idx;
+ wire [3:0] meta_write_arb_io_out_bits_way_en;
+ wire [19:0] meta_write_arb_io_out_bits_data_tag;
+ wire [1:0] meta_write_arb_io_out_bits_data_coh_state;
+ wire meta_write_arb_io_chosen;
+ wire mem_req_arb_clk;
+ wire mem_req_arb_reset;
+ wire mem_req_arb_io_in_0_ready;
+ wire mem_req_arb_io_in_0_valid;
+ wire [25:0] mem_req_arb_io_in_0_bits_addr_block;
+ wire [1:0] mem_req_arb_io_in_0_bits_client_xact_id;
+ wire [1:0] mem_req_arb_io_in_0_bits_addr_beat;
+ wire mem_req_arb_io_in_0_bits_is_builtin_type;
+ wire [2:0] mem_req_arb_io_in_0_bits_a_type;
+ wire [16:0] mem_req_arb_io_in_0_bits_union;
+ wire [127:0] mem_req_arb_io_in_0_bits_data;
+ wire mem_req_arb_io_in_1_ready;
+ wire mem_req_arb_io_in_1_valid;
+ wire [25:0] mem_req_arb_io_in_1_bits_addr_block;
+ wire [1:0] mem_req_arb_io_in_1_bits_client_xact_id;
+ wire [1:0] mem_req_arb_io_in_1_bits_addr_beat;
+ wire mem_req_arb_io_in_1_bits_is_builtin_type;
+ wire [2:0] mem_req_arb_io_in_1_bits_a_type;
+ wire [16:0] mem_req_arb_io_in_1_bits_union;
+ wire [127:0] mem_req_arb_io_in_1_bits_data;
+ wire mem_req_arb_io_in_2_ready;
+ wire mem_req_arb_io_in_2_valid;
+ wire [25:0] mem_req_arb_io_in_2_bits_addr_block;
+ wire [1:0] mem_req_arb_io_in_2_bits_client_xact_id;
+ wire [1:0] mem_req_arb_io_in_2_bits_addr_beat;
+ wire mem_req_arb_io_in_2_bits_is_builtin_type;
+ wire [2:0] mem_req_arb_io_in_2_bits_a_type;
+ wire [16:0] mem_req_arb_io_in_2_bits_union;
+ wire [127:0] mem_req_arb_io_in_2_bits_data;
+ wire mem_req_arb_io_out_ready;
+ wire mem_req_arb_io_out_valid;
+ wire [25:0] mem_req_arb_io_out_bits_addr_block;
+ wire [1:0] mem_req_arb_io_out_bits_client_xact_id;
+ wire [1:0] mem_req_arb_io_out_bits_addr_beat;
+ wire mem_req_arb_io_out_bits_is_builtin_type;
+ wire [2:0] mem_req_arb_io_out_bits_a_type;
+ wire [16:0] mem_req_arb_io_out_bits_union;
+ wire [127:0] mem_req_arb_io_out_bits_data;
+ wire [1:0] mem_req_arb_io_chosen;
+ wire wb_req_arb_clk;
+ wire wb_req_arb_reset;
+ wire wb_req_arb_io_in_0_ready;
+ wire wb_req_arb_io_in_0_valid;
+ wire [1:0] wb_req_arb_io_in_0_bits_addr_beat;
+ wire [25:0] wb_req_arb_io_in_0_bits_addr_block;
+ wire [1:0] wb_req_arb_io_in_0_bits_client_xact_id;
+ wire wb_req_arb_io_in_0_bits_voluntary;
+ wire [2:0] wb_req_arb_io_in_0_bits_r_type;
+ wire [127:0] wb_req_arb_io_in_0_bits_data;
+ wire [3:0] wb_req_arb_io_in_0_bits_way_en;
+ wire wb_req_arb_io_in_1_ready;
+ wire wb_req_arb_io_in_1_valid;
+ wire [1:0] wb_req_arb_io_in_1_bits_addr_beat;
+ wire [25:0] wb_req_arb_io_in_1_bits_addr_block;
+ wire [1:0] wb_req_arb_io_in_1_bits_client_xact_id;
+ wire wb_req_arb_io_in_1_bits_voluntary;
+ wire [2:0] wb_req_arb_io_in_1_bits_r_type;
+ wire [127:0] wb_req_arb_io_in_1_bits_data;
+ wire [3:0] wb_req_arb_io_in_1_bits_way_en;
+ wire wb_req_arb_io_out_ready;
+ wire wb_req_arb_io_out_valid;
+ wire [1:0] wb_req_arb_io_out_bits_addr_beat;
+ wire [25:0] wb_req_arb_io_out_bits_addr_block;
+ wire [1:0] wb_req_arb_io_out_bits_client_xact_id;
+ wire wb_req_arb_io_out_bits_voluntary;
+ wire [2:0] wb_req_arb_io_out_bits_r_type;
+ wire [127:0] wb_req_arb_io_out_bits_data;
+ wire [3:0] wb_req_arb_io_out_bits_way_en;
+ wire wb_req_arb_io_chosen;
+ wire replay_arb_clk;
+ wire replay_arb_reset;
+ wire replay_arb_io_in_0_ready;
+ wire replay_arb_io_in_0_valid;
+ wire [39:0] replay_arb_io_in_0_bits_addr;
+ wire [8:0] replay_arb_io_in_0_bits_tag;
+ wire [4:0] replay_arb_io_in_0_bits_cmd;
+ wire [2:0] replay_arb_io_in_0_bits_typ;
+ wire replay_arb_io_in_0_bits_kill;
+ wire replay_arb_io_in_0_bits_phys;
+ wire [4:0] replay_arb_io_in_0_bits_sdq_id;
+ wire replay_arb_io_in_1_ready;
+ wire replay_arb_io_in_1_valid;
+ wire [39:0] replay_arb_io_in_1_bits_addr;
+ wire [8:0] replay_arb_io_in_1_bits_tag;
+ wire [4:0] replay_arb_io_in_1_bits_cmd;
+ wire [2:0] replay_arb_io_in_1_bits_typ;
+ wire replay_arb_io_in_1_bits_kill;
+ wire replay_arb_io_in_1_bits_phys;
+ wire [4:0] replay_arb_io_in_1_bits_sdq_id;
+ wire replay_arb_io_out_ready;
+ wire replay_arb_io_out_valid;
+ wire [39:0] replay_arb_io_out_bits_addr;
+ wire [8:0] replay_arb_io_out_bits_tag;
+ wire [4:0] replay_arb_io_out_bits_cmd;
+ wire [2:0] replay_arb_io_out_bits_typ;
+ wire replay_arb_io_out_bits_kill;
+ wire replay_arb_io_out_bits_phys;
+ wire [4:0] replay_arb_io_out_bits_sdq_id;
+ wire replay_arb_io_chosen;
+ wire alloc_arb_clk;
+ wire alloc_arb_reset;
+ wire alloc_arb_io_in_0_ready;
+ wire alloc_arb_io_in_0_valid;
+ wire alloc_arb_io_in_0_bits;
+ wire alloc_arb_io_in_1_ready;
+ wire alloc_arb_io_in_1_valid;
+ wire alloc_arb_io_in_1_bits;
+ wire alloc_arb_io_out_ready;
+ wire alloc_arb_io_out_valid;
+ wire alloc_arb_io_out_bits;
+ wire alloc_arb_io_chosen;
+ wire T_2714_clk;
+ wire T_2714_reset;
+ wire T_2714_io_req_pri_val;
+ wire T_2714_io_req_pri_rdy;
+ wire T_2714_io_req_sec_val;
+ wire T_2714_io_req_sec_rdy;
+ wire [39:0] T_2714_io_req_bits_addr;
+ wire [8:0] T_2714_io_req_bits_tag;
+ wire [4:0] T_2714_io_req_bits_cmd;
+ wire [2:0] T_2714_io_req_bits_typ;
+ wire T_2714_io_req_bits_kill;
+ wire T_2714_io_req_bits_phys;
+ wire [4:0] T_2714_io_req_bits_sdq_id;
+ wire T_2714_io_req_bits_tag_match;
+ wire [19:0] T_2714_io_req_bits_old_meta_tag;
+ wire [1:0] T_2714_io_req_bits_old_meta_coh_state;
+ wire [3:0] T_2714_io_req_bits_way_en;
+ wire T_2714_io_idx_match;
+ wire [19:0] T_2714_io_tag;
+ wire T_2714_io_mem_req_ready;
+ wire T_2714_io_mem_req_valid;
+ wire [25:0] T_2714_io_mem_req_bits_addr_block;
+ wire [1:0] T_2714_io_mem_req_bits_client_xact_id;
+ wire [1:0] T_2714_io_mem_req_bits_addr_beat;
+ wire T_2714_io_mem_req_bits_is_builtin_type;
+ wire [2:0] T_2714_io_mem_req_bits_a_type;
+ wire [16:0] T_2714_io_mem_req_bits_union;
+ wire [127:0] T_2714_io_mem_req_bits_data;
+ wire [3:0] T_2714_io_refill_way_en;
+ wire [11:0] T_2714_io_refill_addr;
+ wire T_2714_io_meta_read_ready;
+ wire T_2714_io_meta_read_valid;
+ wire [5:0] T_2714_io_meta_read_bits_idx;
+ wire [19:0] T_2714_io_meta_read_bits_tag;
+ wire T_2714_io_meta_write_ready;
+ wire T_2714_io_meta_write_valid;
+ wire [5:0] T_2714_io_meta_write_bits_idx;
+ wire [3:0] T_2714_io_meta_write_bits_way_en;
+ wire [19:0] T_2714_io_meta_write_bits_data_tag;
+ wire [1:0] T_2714_io_meta_write_bits_data_coh_state;
+ wire T_2714_io_replay_ready;
+ wire T_2714_io_replay_valid;
+ wire [39:0] T_2714_io_replay_bits_addr;
+ wire [8:0] T_2714_io_replay_bits_tag;
+ wire [4:0] T_2714_io_replay_bits_cmd;
+ wire [2:0] T_2714_io_replay_bits_typ;
+ wire T_2714_io_replay_bits_kill;
+ wire T_2714_io_replay_bits_phys;
+ wire [4:0] T_2714_io_replay_bits_sdq_id;
+ wire T_2714_io_mem_grant_valid;
+ wire [1:0] T_2714_io_mem_grant_bits_addr_beat;
+ wire [1:0] T_2714_io_mem_grant_bits_client_xact_id;
+ wire [3:0] T_2714_io_mem_grant_bits_manager_xact_id;
+ wire T_2714_io_mem_grant_bits_is_builtin_type;
+ wire [3:0] T_2714_io_mem_grant_bits_g_type;
+ wire [127:0] T_2714_io_mem_grant_bits_data;
+ wire T_2714_io_wb_req_ready;
+ wire T_2714_io_wb_req_valid;
+ wire [1:0] T_2714_io_wb_req_bits_addr_beat;
+ wire [25:0] T_2714_io_wb_req_bits_addr_block;
+ wire [1:0] T_2714_io_wb_req_bits_client_xact_id;
+ wire T_2714_io_wb_req_bits_voluntary;
+ wire [2:0] T_2714_io_wb_req_bits_r_type;
+ wire [127:0] T_2714_io_wb_req_bits_data;
+ wire [3:0] T_2714_io_wb_req_bits_way_en;
+ wire T_2714_io_probe_rdy;
+ wire [19:0] T_2715;
+ wire T_2716;
+ wire T_2717;
+ wire T_2719;
+ wire T_2720;
+ wire T_2721;
+ wire T_2722;
+ wire T_2723;
+ wire T_2725;
+ wire T_2728;
+ wire T_2730_clk;
+ wire T_2730_reset;
+ wire T_2730_io_req_pri_val;
+ wire T_2730_io_req_pri_rdy;
+ wire T_2730_io_req_sec_val;
+ wire T_2730_io_req_sec_rdy;
+ wire [39:0] T_2730_io_req_bits_addr;
+ wire [8:0] T_2730_io_req_bits_tag;
+ wire [4:0] T_2730_io_req_bits_cmd;
+ wire [2:0] T_2730_io_req_bits_typ;
+ wire T_2730_io_req_bits_kill;
+ wire T_2730_io_req_bits_phys;
+ wire [4:0] T_2730_io_req_bits_sdq_id;
+ wire T_2730_io_req_bits_tag_match;
+ wire [19:0] T_2730_io_req_bits_old_meta_tag;
+ wire [1:0] T_2730_io_req_bits_old_meta_coh_state;
+ wire [3:0] T_2730_io_req_bits_way_en;
+ wire T_2730_io_idx_match;
+ wire [19:0] T_2730_io_tag;
+ wire T_2730_io_mem_req_ready;
+ wire T_2730_io_mem_req_valid;
+ wire [25:0] T_2730_io_mem_req_bits_addr_block;
+ wire [1:0] T_2730_io_mem_req_bits_client_xact_id;
+ wire [1:0] T_2730_io_mem_req_bits_addr_beat;
+ wire T_2730_io_mem_req_bits_is_builtin_type;
+ wire [2:0] T_2730_io_mem_req_bits_a_type;
+ wire [16:0] T_2730_io_mem_req_bits_union;
+ wire [127:0] T_2730_io_mem_req_bits_data;
+ wire [3:0] T_2730_io_refill_way_en;
+ wire [11:0] T_2730_io_refill_addr;
+ wire T_2730_io_meta_read_ready;
+ wire T_2730_io_meta_read_valid;
+ wire [5:0] T_2730_io_meta_read_bits_idx;
+ wire [19:0] T_2730_io_meta_read_bits_tag;
+ wire T_2730_io_meta_write_ready;
+ wire T_2730_io_meta_write_valid;
+ wire [5:0] T_2730_io_meta_write_bits_idx;
+ wire [3:0] T_2730_io_meta_write_bits_way_en;
+ wire [19:0] T_2730_io_meta_write_bits_data_tag;
+ wire [1:0] T_2730_io_meta_write_bits_data_coh_state;
+ wire T_2730_io_replay_ready;
+ wire T_2730_io_replay_valid;
+ wire [39:0] T_2730_io_replay_bits_addr;
+ wire [8:0] T_2730_io_replay_bits_tag;
+ wire [4:0] T_2730_io_replay_bits_cmd;
+ wire [2:0] T_2730_io_replay_bits_typ;
+ wire T_2730_io_replay_bits_kill;
+ wire T_2730_io_replay_bits_phys;
+ wire [4:0] T_2730_io_replay_bits_sdq_id;
+ wire T_2730_io_mem_grant_valid;
+ wire [1:0] T_2730_io_mem_grant_bits_addr_beat;
+ wire [1:0] T_2730_io_mem_grant_bits_client_xact_id;
+ wire [3:0] T_2730_io_mem_grant_bits_manager_xact_id;
+ wire T_2730_io_mem_grant_bits_is_builtin_type;
+ wire [3:0] T_2730_io_mem_grant_bits_g_type;
+ wire [127:0] T_2730_io_mem_grant_bits_data;
+ wire T_2730_io_wb_req_ready;
+ wire T_2730_io_wb_req_valid;
+ wire [1:0] T_2730_io_wb_req_bits_addr_beat;
+ wire [25:0] T_2730_io_wb_req_bits_addr_block;
+ wire [1:0] T_2730_io_wb_req_bits_client_xact_id;
+ wire T_2730_io_wb_req_bits_voluntary;
+ wire [2:0] T_2730_io_wb_req_bits_r_type;
+ wire [127:0] T_2730_io_wb_req_bits_data;
+ wire [3:0] T_2730_io_wb_req_bits_way_en;
+ wire T_2730_io_probe_rdy;
+ wire [19:0] T_2731;
+ wire T_2732;
+ wire T_2733;
+ wire T_2735;
+ wire T_2736;
+ wire pri_rdy;
+ wire sec_rdy;
+ wire idx_match;
+ wire T_2741;
+ wire T_2744;
+ wire T_2746;
+ wire T_2747;
+ wire T_2749;
+ wire T_2750;
+ wire mmio_alloc_arb_clk;
+ wire mmio_alloc_arb_reset;
+ wire mmio_alloc_arb_io_in_0_ready;
+ wire mmio_alloc_arb_io_in_0_valid;
+ wire mmio_alloc_arb_io_in_0_bits;
+ wire mmio_alloc_arb_io_out_ready;
+ wire mmio_alloc_arb_io_out_valid;
+ wire mmio_alloc_arb_io_out_bits;
+ wire mmio_alloc_arb_io_chosen;
+ wire resp_arb_clk;
+ wire resp_arb_reset;
+ wire resp_arb_io_in_0_ready;
+ wire resp_arb_io_in_0_valid;
+ wire [39:0] resp_arb_io_in_0_bits_addr;
+ wire [8:0] resp_arb_io_in_0_bits_tag;
+ wire [4:0] resp_arb_io_in_0_bits_cmd;
+ wire [2:0] resp_arb_io_in_0_bits_typ;
+ wire [63:0] resp_arb_io_in_0_bits_data;
+ wire resp_arb_io_in_0_bits_nack;
+ wire resp_arb_io_in_0_bits_replay;
+ wire resp_arb_io_in_0_bits_has_data;
+ wire [63:0] resp_arb_io_in_0_bits_data_word_bypass;
+ wire [63:0] resp_arb_io_in_0_bits_store_data;
+ wire resp_arb_io_out_ready;
+ wire resp_arb_io_out_valid;
+ wire [39:0] resp_arb_io_out_bits_addr;
+ wire [8:0] resp_arb_io_out_bits_tag;
+ wire [4:0] resp_arb_io_out_bits_cmd;
+ wire [2:0] resp_arb_io_out_bits_typ;
+ wire [63:0] resp_arb_io_out_bits_data;
+ wire resp_arb_io_out_bits_nack;
+ wire resp_arb_io_out_bits_replay;
+ wire resp_arb_io_out_bits_has_data;
+ wire [63:0] resp_arb_io_out_bits_data_word_bypass;
+ wire [63:0] resp_arb_io_out_bits_store_data;
+ wire resp_arb_io_chosen;
+ wire T_2812_clk;
+ wire T_2812_reset;
+ wire T_2812_io_req_ready;
+ wire T_2812_io_req_valid;
+ wire [39:0] T_2812_io_req_bits_addr;
+ wire [8:0] T_2812_io_req_bits_tag;
+ wire [4:0] T_2812_io_req_bits_cmd;
+ wire [2:0] T_2812_io_req_bits_typ;
+ wire T_2812_io_req_bits_kill;
+ wire T_2812_io_req_bits_phys;
+ wire [63:0] T_2812_io_req_bits_data;
+ wire T_2812_io_acquire_ready;
+ wire T_2812_io_acquire_valid;
+ wire [25:0] T_2812_io_acquire_bits_addr_block;
+ wire [1:0] T_2812_io_acquire_bits_client_xact_id;
+ wire [1:0] T_2812_io_acquire_bits_addr_beat;
+ wire T_2812_io_acquire_bits_is_builtin_type;
+ wire [2:0] T_2812_io_acquire_bits_a_type;
+ wire [16:0] T_2812_io_acquire_bits_union;
+ wire [127:0] T_2812_io_acquire_bits_data;
+ wire T_2812_io_grant_valid;
+ wire [1:0] T_2812_io_grant_bits_addr_beat;
+ wire [1:0] T_2812_io_grant_bits_client_xact_id;
+ wire [3:0] T_2812_io_grant_bits_manager_xact_id;
+ wire T_2812_io_grant_bits_is_builtin_type;
+ wire [3:0] T_2812_io_grant_bits_g_type;
+ wire [127:0] T_2812_io_grant_bits_data;
+ wire T_2812_io_resp_ready;
+ wire T_2812_io_resp_valid;
+ wire [39:0] T_2812_io_resp_bits_addr;
+ wire [8:0] T_2812_io_resp_bits_tag;
+ wire [4:0] T_2812_io_resp_bits_cmd;
+ wire [2:0] T_2812_io_resp_bits_typ;
+ wire [63:0] T_2812_io_resp_bits_data;
+ wire T_2812_io_resp_bits_nack;
+ wire T_2812_io_resp_bits_replay;
+ wire T_2812_io_resp_bits_has_data;
+ wire [63:0] T_2812_io_resp_bits_data_word_bypass;
+ wire [63:0] T_2812_io_resp_bits_store_data;
+ wire mmio_rdy;
+ wire T_2815;
+ wire T_2816;
+ wire T_2818;
+ wire T_2821;
+ wire T_2822;
+ wire T_2824;
+ wire T_2825;
+ wire T_2826;
+ wire T_2827;
+ wire T_2828;
+ wire [3:0] GEN_0;
+ wire [11:0] GEN_1;
+ wire T_2878;
+ wire T_2879;
+ wire T_2880;
+ wire T_2881;
+ wire T_2882;
+ wire T_2883;
+ wire T_2884;
+ wire T_2885;
+ wire free_sdq;
+ reg [4:0] T_2887;
+ wire T_2889;
+ wire [31:0] T_2891;
+ wire [17:0] T_2893;
+ wire [16:0] T_2894;
+ wire [31:0] T_2895;
+ wire [31:0] T_2896;
+ wire [31:0] T_2897;
+ wire [16:0] T_2898;
+ wire [16:0] T_2899;
+ wire T_2900;
+ wire T_2901;
+ wire T_2902;
+ wire T_2903;
+ wire T_2904;
+ wire T_2905;
+ wire T_2906;
+ wire T_2907;
+ wire T_2908;
+ wire T_2909;
+ wire T_2910;
+ wire T_2911;
+ wire T_2912;
+ wire T_2913;
+ wire T_2914;
+ wire T_2915;
+ wire T_2916;
+ wire [16:0] T_2935_0;
+ wire [16:0] T_2935_1;
+ wire [16:0] T_2935_2;
+ wire [16:0] T_2935_3;
+ wire [16:0] T_2935_4;
+ wire [16:0] T_2935_5;
+ wire [16:0] T_2935_6;
+ wire [16:0] T_2935_7;
+ wire [16:0] T_2935_8;
+ wire [16:0] T_2935_9;
+ wire [16:0] T_2935_10;
+ wire [16:0] T_2935_11;
+ wire [16:0] T_2935_12;
+ wire [16:0] T_2935_13;
+ wire [16:0] T_2935_14;
+ wire [16:0] T_2935_15;
+ wire [16:0] T_2935_16;
+ wire [16:0] T_2956;
+ wire [16:0] T_2957;
+ wire [16:0] T_2958;
+ wire [16:0] T_2959;
+ wire [16:0] T_2960;
+ wire [16:0] T_2961;
+ wire [16:0] T_2962;
+ wire [16:0] T_2963;
+ wire [16:0] T_2964;
+ wire [16:0] T_2965;
+ wire [16:0] T_2966;
+ wire [16:0] T_2967;
+ wire [16:0] T_2968;
+ wire [16:0] T_2969;
+ wire [16:0] T_2970;
+ wire [16:0] T_2971;
+ wire [16:0] T_2972;
+ wire [17:0] T_2974;
+ wire [16:0] T_2975;
+ wire [16:0] T_2976;
+ wire [31:0] T_2977;
+ reg GEN_4;
+ reg GEN_5;
+ reg GEN_6;
+ wire GEN_2;
+ wire GEN_3;
+ Arbiter_93 meta_read_arb (
+ .clk(meta_read_arb_clk),
+ .reset(meta_read_arb_reset),
+ .io_in_0_ready(meta_read_arb_io_in_0_ready),
+ .io_in_0_valid(meta_read_arb_io_in_0_valid),
+ .io_in_0_bits_idx(meta_read_arb_io_in_0_bits_idx),
+ .io_in_0_bits_tag(meta_read_arb_io_in_0_bits_tag),
+ .io_in_1_ready(meta_read_arb_io_in_1_ready),
+ .io_in_1_valid(meta_read_arb_io_in_1_valid),
+ .io_in_1_bits_idx(meta_read_arb_io_in_1_bits_idx),
+ .io_in_1_bits_tag(meta_read_arb_io_in_1_bits_tag),
+ .io_out_ready(meta_read_arb_io_out_ready),
+ .io_out_valid(meta_read_arb_io_out_valid),
+ .io_out_bits_idx(meta_read_arb_io_out_bits_idx),
+ .io_out_bits_tag(meta_read_arb_io_out_bits_tag),
+ .io_chosen(meta_read_arb_io_chosen)
+ );
+ Arbiter_94 meta_write_arb (
+ .clk(meta_write_arb_clk),
+ .reset(meta_write_arb_reset),
+ .io_in_0_ready(meta_write_arb_io_in_0_ready),
+ .io_in_0_valid(meta_write_arb_io_in_0_valid),
+ .io_in_0_bits_idx(meta_write_arb_io_in_0_bits_idx),
+ .io_in_0_bits_way_en(meta_write_arb_io_in_0_bits_way_en),
+ .io_in_0_bits_data_tag(meta_write_arb_io_in_0_bits_data_tag),
+ .io_in_0_bits_data_coh_state(meta_write_arb_io_in_0_bits_data_coh_state),
+ .io_in_1_ready(meta_write_arb_io_in_1_ready),
+ .io_in_1_valid(meta_write_arb_io_in_1_valid),
+ .io_in_1_bits_idx(meta_write_arb_io_in_1_bits_idx),
+ .io_in_1_bits_way_en(meta_write_arb_io_in_1_bits_way_en),
+ .io_in_1_bits_data_tag(meta_write_arb_io_in_1_bits_data_tag),
+ .io_in_1_bits_data_coh_state(meta_write_arb_io_in_1_bits_data_coh_state),
+ .io_out_ready(meta_write_arb_io_out_ready),
+ .io_out_valid(meta_write_arb_io_out_valid),
+ .io_out_bits_idx(meta_write_arb_io_out_bits_idx),
+ .io_out_bits_way_en(meta_write_arb_io_out_bits_way_en),
+ .io_out_bits_data_tag(meta_write_arb_io_out_bits_data_tag),
+ .io_out_bits_data_coh_state(meta_write_arb_io_out_bits_data_coh_state),
+ .io_chosen(meta_write_arb_io_chosen)
+ );
+ LockingArbiter mem_req_arb (
+ .clk(mem_req_arb_clk),
+ .reset(mem_req_arb_reset),
+ .io_in_0_ready(mem_req_arb_io_in_0_ready),
+ .io_in_0_valid(mem_req_arb_io_in_0_valid),
+ .io_in_0_bits_addr_block(mem_req_arb_io_in_0_bits_addr_block),
+ .io_in_0_bits_client_xact_id(mem_req_arb_io_in_0_bits_client_xact_id),
+ .io_in_0_bits_addr_beat(mem_req_arb_io_in_0_bits_addr_beat),
+ .io_in_0_bits_is_builtin_type(mem_req_arb_io_in_0_bits_is_builtin_type),
+ .io_in_0_bits_a_type(mem_req_arb_io_in_0_bits_a_type),
+ .io_in_0_bits_union(mem_req_arb_io_in_0_bits_union),
+ .io_in_0_bits_data(mem_req_arb_io_in_0_bits_data),
+ .io_in_1_ready(mem_req_arb_io_in_1_ready),
+ .io_in_1_valid(mem_req_arb_io_in_1_valid),
+ .io_in_1_bits_addr_block(mem_req_arb_io_in_1_bits_addr_block),
+ .io_in_1_bits_client_xact_id(mem_req_arb_io_in_1_bits_client_xact_id),
+ .io_in_1_bits_addr_beat(mem_req_arb_io_in_1_bits_addr_beat),
+ .io_in_1_bits_is_builtin_type(mem_req_arb_io_in_1_bits_is_builtin_type),
+ .io_in_1_bits_a_type(mem_req_arb_io_in_1_bits_a_type),
+ .io_in_1_bits_union(mem_req_arb_io_in_1_bits_union),
+ .io_in_1_bits_data(mem_req_arb_io_in_1_bits_data),
+ .io_in_2_ready(mem_req_arb_io_in_2_ready),
+ .io_in_2_valid(mem_req_arb_io_in_2_valid),
+ .io_in_2_bits_addr_block(mem_req_arb_io_in_2_bits_addr_block),
+ .io_in_2_bits_client_xact_id(mem_req_arb_io_in_2_bits_client_xact_id),
+ .io_in_2_bits_addr_beat(mem_req_arb_io_in_2_bits_addr_beat),
+ .io_in_2_bits_is_builtin_type(mem_req_arb_io_in_2_bits_is_builtin_type),
+ .io_in_2_bits_a_type(mem_req_arb_io_in_2_bits_a_type),
+ .io_in_2_bits_union(mem_req_arb_io_in_2_bits_union),
+ .io_in_2_bits_data(mem_req_arb_io_in_2_bits_data),
+ .io_out_ready(mem_req_arb_io_out_ready),
+ .io_out_valid(mem_req_arb_io_out_valid),
+ .io_out_bits_addr_block(mem_req_arb_io_out_bits_addr_block),
+ .io_out_bits_client_xact_id(mem_req_arb_io_out_bits_client_xact_id),
+ .io_out_bits_addr_beat(mem_req_arb_io_out_bits_addr_beat),
+ .io_out_bits_is_builtin_type(mem_req_arb_io_out_bits_is_builtin_type),
+ .io_out_bits_a_type(mem_req_arb_io_out_bits_a_type),
+ .io_out_bits_union(mem_req_arb_io_out_bits_union),
+ .io_out_bits_data(mem_req_arb_io_out_bits_data),
+ .io_chosen(mem_req_arb_io_chosen)
+ );
+ Arbiter_95 wb_req_arb (
+ .clk(wb_req_arb_clk),
+ .reset(wb_req_arb_reset),
+ .io_in_0_ready(wb_req_arb_io_in_0_ready),
+ .io_in_0_valid(wb_req_arb_io_in_0_valid),
+ .io_in_0_bits_addr_beat(wb_req_arb_io_in_0_bits_addr_beat),
+ .io_in_0_bits_addr_block(wb_req_arb_io_in_0_bits_addr_block),
+ .io_in_0_bits_client_xact_id(wb_req_arb_io_in_0_bits_client_xact_id),
+ .io_in_0_bits_voluntary(wb_req_arb_io_in_0_bits_voluntary),
+ .io_in_0_bits_r_type(wb_req_arb_io_in_0_bits_r_type),
+ .io_in_0_bits_data(wb_req_arb_io_in_0_bits_data),
+ .io_in_0_bits_way_en(wb_req_arb_io_in_0_bits_way_en),
+ .io_in_1_ready(wb_req_arb_io_in_1_ready),
+ .io_in_1_valid(wb_req_arb_io_in_1_valid),
+ .io_in_1_bits_addr_beat(wb_req_arb_io_in_1_bits_addr_beat),
+ .io_in_1_bits_addr_block(wb_req_arb_io_in_1_bits_addr_block),
+ .io_in_1_bits_client_xact_id(wb_req_arb_io_in_1_bits_client_xact_id),
+ .io_in_1_bits_voluntary(wb_req_arb_io_in_1_bits_voluntary),
+ .io_in_1_bits_r_type(wb_req_arb_io_in_1_bits_r_type),
+ .io_in_1_bits_data(wb_req_arb_io_in_1_bits_data),
+ .io_in_1_bits_way_en(wb_req_arb_io_in_1_bits_way_en),
+ .io_out_ready(wb_req_arb_io_out_ready),
+ .io_out_valid(wb_req_arb_io_out_valid),
+ .io_out_bits_addr_beat(wb_req_arb_io_out_bits_addr_beat),
+ .io_out_bits_addr_block(wb_req_arb_io_out_bits_addr_block),
+ .io_out_bits_client_xact_id(wb_req_arb_io_out_bits_client_xact_id),
+ .io_out_bits_voluntary(wb_req_arb_io_out_bits_voluntary),
+ .io_out_bits_r_type(wb_req_arb_io_out_bits_r_type),
+ .io_out_bits_data(wb_req_arb_io_out_bits_data),
+ .io_out_bits_way_en(wb_req_arb_io_out_bits_way_en),
+ .io_chosen(wb_req_arb_io_chosen)
+ );
+ Arbiter_96 replay_arb (
+ .clk(replay_arb_clk),
+ .reset(replay_arb_reset),
+ .io_in_0_ready(replay_arb_io_in_0_ready),
+ .io_in_0_valid(replay_arb_io_in_0_valid),
+ .io_in_0_bits_addr(replay_arb_io_in_0_bits_addr),
+ .io_in_0_bits_tag(replay_arb_io_in_0_bits_tag),
+ .io_in_0_bits_cmd(replay_arb_io_in_0_bits_cmd),
+ .io_in_0_bits_typ(replay_arb_io_in_0_bits_typ),
+ .io_in_0_bits_kill(replay_arb_io_in_0_bits_kill),
+ .io_in_0_bits_phys(replay_arb_io_in_0_bits_phys),
+ .io_in_0_bits_sdq_id(replay_arb_io_in_0_bits_sdq_id),
+ .io_in_1_ready(replay_arb_io_in_1_ready),
+ .io_in_1_valid(replay_arb_io_in_1_valid),
+ .io_in_1_bits_addr(replay_arb_io_in_1_bits_addr),
+ .io_in_1_bits_tag(replay_arb_io_in_1_bits_tag),
+ .io_in_1_bits_cmd(replay_arb_io_in_1_bits_cmd),
+ .io_in_1_bits_typ(replay_arb_io_in_1_bits_typ),
+ .io_in_1_bits_kill(replay_arb_io_in_1_bits_kill),
+ .io_in_1_bits_phys(replay_arb_io_in_1_bits_phys),
+ .io_in_1_bits_sdq_id(replay_arb_io_in_1_bits_sdq_id),
+ .io_out_ready(replay_arb_io_out_ready),
+ .io_out_valid(replay_arb_io_out_valid),
+ .io_out_bits_addr(replay_arb_io_out_bits_addr),
+ .io_out_bits_tag(replay_arb_io_out_bits_tag),
+ .io_out_bits_cmd(replay_arb_io_out_bits_cmd),
+ .io_out_bits_typ(replay_arb_io_out_bits_typ),
+ .io_out_bits_kill(replay_arb_io_out_bits_kill),
+ .io_out_bits_phys(replay_arb_io_out_bits_phys),
+ .io_out_bits_sdq_id(replay_arb_io_out_bits_sdq_id),
+ .io_chosen(replay_arb_io_chosen)
+ );
+ Arbiter_97 alloc_arb (
+ .clk(alloc_arb_clk),
+ .reset(alloc_arb_reset),
+ .io_in_0_ready(alloc_arb_io_in_0_ready),
+ .io_in_0_valid(alloc_arb_io_in_0_valid),
+ .io_in_0_bits(alloc_arb_io_in_0_bits),
+ .io_in_1_ready(alloc_arb_io_in_1_ready),
+ .io_in_1_valid(alloc_arb_io_in_1_valid),
+ .io_in_1_bits(alloc_arb_io_in_1_bits),
+ .io_out_ready(alloc_arb_io_out_ready),
+ .io_out_valid(alloc_arb_io_out_valid),
+ .io_out_bits(alloc_arb_io_out_bits),
+ .io_chosen(alloc_arb_io_chosen)
+ );
+ MSHR T_2714 (
+ .clk(T_2714_clk),
+ .reset(T_2714_reset),
+ .io_req_pri_val(T_2714_io_req_pri_val),
+ .io_req_pri_rdy(T_2714_io_req_pri_rdy),
+ .io_req_sec_val(T_2714_io_req_sec_val),
+ .io_req_sec_rdy(T_2714_io_req_sec_rdy),
+ .io_req_bits_addr(T_2714_io_req_bits_addr),
+ .io_req_bits_tag(T_2714_io_req_bits_tag),
+ .io_req_bits_cmd(T_2714_io_req_bits_cmd),
+ .io_req_bits_typ(T_2714_io_req_bits_typ),
+ .io_req_bits_kill(T_2714_io_req_bits_kill),
+ .io_req_bits_phys(T_2714_io_req_bits_phys),
+ .io_req_bits_sdq_id(T_2714_io_req_bits_sdq_id),
+ .io_req_bits_tag_match(T_2714_io_req_bits_tag_match),
+ .io_req_bits_old_meta_tag(T_2714_io_req_bits_old_meta_tag),
+ .io_req_bits_old_meta_coh_state(T_2714_io_req_bits_old_meta_coh_state),
+ .io_req_bits_way_en(T_2714_io_req_bits_way_en),
+ .io_idx_match(T_2714_io_idx_match),
+ .io_tag(T_2714_io_tag),
+ .io_mem_req_ready(T_2714_io_mem_req_ready),
+ .io_mem_req_valid(T_2714_io_mem_req_valid),
+ .io_mem_req_bits_addr_block(T_2714_io_mem_req_bits_addr_block),
+ .io_mem_req_bits_client_xact_id(T_2714_io_mem_req_bits_client_xact_id),
+ .io_mem_req_bits_addr_beat(T_2714_io_mem_req_bits_addr_beat),
+ .io_mem_req_bits_is_builtin_type(T_2714_io_mem_req_bits_is_builtin_type),
+ .io_mem_req_bits_a_type(T_2714_io_mem_req_bits_a_type),
+ .io_mem_req_bits_union(T_2714_io_mem_req_bits_union),
+ .io_mem_req_bits_data(T_2714_io_mem_req_bits_data),
+ .io_refill_way_en(T_2714_io_refill_way_en),
+ .io_refill_addr(T_2714_io_refill_addr),
+ .io_meta_read_ready(T_2714_io_meta_read_ready),
+ .io_meta_read_valid(T_2714_io_meta_read_valid),
+ .io_meta_read_bits_idx(T_2714_io_meta_read_bits_idx),
+ .io_meta_read_bits_tag(T_2714_io_meta_read_bits_tag),
+ .io_meta_write_ready(T_2714_io_meta_write_ready),
+ .io_meta_write_valid(T_2714_io_meta_write_valid),
+ .io_meta_write_bits_idx(T_2714_io_meta_write_bits_idx),
+ .io_meta_write_bits_way_en(T_2714_io_meta_write_bits_way_en),
+ .io_meta_write_bits_data_tag(T_2714_io_meta_write_bits_data_tag),
+ .io_meta_write_bits_data_coh_state(T_2714_io_meta_write_bits_data_coh_state),
+ .io_replay_ready(T_2714_io_replay_ready),
+ .io_replay_valid(T_2714_io_replay_valid),
+ .io_replay_bits_addr(T_2714_io_replay_bits_addr),
+ .io_replay_bits_tag(T_2714_io_replay_bits_tag),
+ .io_replay_bits_cmd(T_2714_io_replay_bits_cmd),
+ .io_replay_bits_typ(T_2714_io_replay_bits_typ),
+ .io_replay_bits_kill(T_2714_io_replay_bits_kill),
+ .io_replay_bits_phys(T_2714_io_replay_bits_phys),
+ .io_replay_bits_sdq_id(T_2714_io_replay_bits_sdq_id),
+ .io_mem_grant_valid(T_2714_io_mem_grant_valid),
+ .io_mem_grant_bits_addr_beat(T_2714_io_mem_grant_bits_addr_beat),
+ .io_mem_grant_bits_client_xact_id(T_2714_io_mem_grant_bits_client_xact_id),
+ .io_mem_grant_bits_manager_xact_id(T_2714_io_mem_grant_bits_manager_xact_id),
+ .io_mem_grant_bits_is_builtin_type(T_2714_io_mem_grant_bits_is_builtin_type),
+ .io_mem_grant_bits_g_type(T_2714_io_mem_grant_bits_g_type),
+ .io_mem_grant_bits_data(T_2714_io_mem_grant_bits_data),
+ .io_wb_req_ready(T_2714_io_wb_req_ready),
+ .io_wb_req_valid(T_2714_io_wb_req_valid),
+ .io_wb_req_bits_addr_beat(T_2714_io_wb_req_bits_addr_beat),
+ .io_wb_req_bits_addr_block(T_2714_io_wb_req_bits_addr_block),
+ .io_wb_req_bits_client_xact_id(T_2714_io_wb_req_bits_client_xact_id),
+ .io_wb_req_bits_voluntary(T_2714_io_wb_req_bits_voluntary),
+ .io_wb_req_bits_r_type(T_2714_io_wb_req_bits_r_type),
+ .io_wb_req_bits_data(T_2714_io_wb_req_bits_data),
+ .io_wb_req_bits_way_en(T_2714_io_wb_req_bits_way_en),
+ .io_probe_rdy(T_2714_io_probe_rdy)
+ );
+ MSHR_99 T_2730 (
+ .clk(T_2730_clk),
+ .reset(T_2730_reset),
+ .io_req_pri_val(T_2730_io_req_pri_val),
+ .io_req_pri_rdy(T_2730_io_req_pri_rdy),
+ .io_req_sec_val(T_2730_io_req_sec_val),
+ .io_req_sec_rdy(T_2730_io_req_sec_rdy),
+ .io_req_bits_addr(T_2730_io_req_bits_addr),
+ .io_req_bits_tag(T_2730_io_req_bits_tag),
+ .io_req_bits_cmd(T_2730_io_req_bits_cmd),
+ .io_req_bits_typ(T_2730_io_req_bits_typ),
+ .io_req_bits_kill(T_2730_io_req_bits_kill),
+ .io_req_bits_phys(T_2730_io_req_bits_phys),
+ .io_req_bits_sdq_id(T_2730_io_req_bits_sdq_id),
+ .io_req_bits_tag_match(T_2730_io_req_bits_tag_match),
+ .io_req_bits_old_meta_tag(T_2730_io_req_bits_old_meta_tag),
+ .io_req_bits_old_meta_coh_state(T_2730_io_req_bits_old_meta_coh_state),
+ .io_req_bits_way_en(T_2730_io_req_bits_way_en),
+ .io_idx_match(T_2730_io_idx_match),
+ .io_tag(T_2730_io_tag),
+ .io_mem_req_ready(T_2730_io_mem_req_ready),
+ .io_mem_req_valid(T_2730_io_mem_req_valid),
+ .io_mem_req_bits_addr_block(T_2730_io_mem_req_bits_addr_block),
+ .io_mem_req_bits_client_xact_id(T_2730_io_mem_req_bits_client_xact_id),
+ .io_mem_req_bits_addr_beat(T_2730_io_mem_req_bits_addr_beat),
+ .io_mem_req_bits_is_builtin_type(T_2730_io_mem_req_bits_is_builtin_type),
+ .io_mem_req_bits_a_type(T_2730_io_mem_req_bits_a_type),
+ .io_mem_req_bits_union(T_2730_io_mem_req_bits_union),
+ .io_mem_req_bits_data(T_2730_io_mem_req_bits_data),
+ .io_refill_way_en(T_2730_io_refill_way_en),
+ .io_refill_addr(T_2730_io_refill_addr),
+ .io_meta_read_ready(T_2730_io_meta_read_ready),
+ .io_meta_read_valid(T_2730_io_meta_read_valid),
+ .io_meta_read_bits_idx(T_2730_io_meta_read_bits_idx),
+ .io_meta_read_bits_tag(T_2730_io_meta_read_bits_tag),
+ .io_meta_write_ready(T_2730_io_meta_write_ready),
+ .io_meta_write_valid(T_2730_io_meta_write_valid),
+ .io_meta_write_bits_idx(T_2730_io_meta_write_bits_idx),
+ .io_meta_write_bits_way_en(T_2730_io_meta_write_bits_way_en),
+ .io_meta_write_bits_data_tag(T_2730_io_meta_write_bits_data_tag),
+ .io_meta_write_bits_data_coh_state(T_2730_io_meta_write_bits_data_coh_state),
+ .io_replay_ready(T_2730_io_replay_ready),
+ .io_replay_valid(T_2730_io_replay_valid),
+ .io_replay_bits_addr(T_2730_io_replay_bits_addr),
+ .io_replay_bits_tag(T_2730_io_replay_bits_tag),
+ .io_replay_bits_cmd(T_2730_io_replay_bits_cmd),
+ .io_replay_bits_typ(T_2730_io_replay_bits_typ),
+ .io_replay_bits_kill(T_2730_io_replay_bits_kill),
+ .io_replay_bits_phys(T_2730_io_replay_bits_phys),
+ .io_replay_bits_sdq_id(T_2730_io_replay_bits_sdq_id),
+ .io_mem_grant_valid(T_2730_io_mem_grant_valid),
+ .io_mem_grant_bits_addr_beat(T_2730_io_mem_grant_bits_addr_beat),
+ .io_mem_grant_bits_client_xact_id(T_2730_io_mem_grant_bits_client_xact_id),
+ .io_mem_grant_bits_manager_xact_id(T_2730_io_mem_grant_bits_manager_xact_id),
+ .io_mem_grant_bits_is_builtin_type(T_2730_io_mem_grant_bits_is_builtin_type),
+ .io_mem_grant_bits_g_type(T_2730_io_mem_grant_bits_g_type),
+ .io_mem_grant_bits_data(T_2730_io_mem_grant_bits_data),
+ .io_wb_req_ready(T_2730_io_wb_req_ready),
+ .io_wb_req_valid(T_2730_io_wb_req_valid),
+ .io_wb_req_bits_addr_beat(T_2730_io_wb_req_bits_addr_beat),
+ .io_wb_req_bits_addr_block(T_2730_io_wb_req_bits_addr_block),
+ .io_wb_req_bits_client_xact_id(T_2730_io_wb_req_bits_client_xact_id),
+ .io_wb_req_bits_voluntary(T_2730_io_wb_req_bits_voluntary),
+ .io_wb_req_bits_r_type(T_2730_io_wb_req_bits_r_type),
+ .io_wb_req_bits_data(T_2730_io_wb_req_bits_data),
+ .io_wb_req_bits_way_en(T_2730_io_wb_req_bits_way_en),
+ .io_probe_rdy(T_2730_io_probe_rdy)
+ );
+ Arbiter_101 mmio_alloc_arb (
+ .clk(mmio_alloc_arb_clk),
+ .reset(mmio_alloc_arb_reset),
+ .io_in_0_ready(mmio_alloc_arb_io_in_0_ready),
+ .io_in_0_valid(mmio_alloc_arb_io_in_0_valid),
+ .io_in_0_bits(mmio_alloc_arb_io_in_0_bits),
+ .io_out_ready(mmio_alloc_arb_io_out_ready),
+ .io_out_valid(mmio_alloc_arb_io_out_valid),
+ .io_out_bits(mmio_alloc_arb_io_out_bits),
+ .io_chosen(mmio_alloc_arb_io_chosen)
+ );
+ Arbiter_102 resp_arb (
+ .clk(resp_arb_clk),
+ .reset(resp_arb_reset),
+ .io_in_0_ready(resp_arb_io_in_0_ready),
+ .io_in_0_valid(resp_arb_io_in_0_valid),
+ .io_in_0_bits_addr(resp_arb_io_in_0_bits_addr),
+ .io_in_0_bits_tag(resp_arb_io_in_0_bits_tag),
+ .io_in_0_bits_cmd(resp_arb_io_in_0_bits_cmd),
+ .io_in_0_bits_typ(resp_arb_io_in_0_bits_typ),
+ .io_in_0_bits_data(resp_arb_io_in_0_bits_data),
+ .io_in_0_bits_nack(resp_arb_io_in_0_bits_nack),
+ .io_in_0_bits_replay(resp_arb_io_in_0_bits_replay),
+ .io_in_0_bits_has_data(resp_arb_io_in_0_bits_has_data),
+ .io_in_0_bits_data_word_bypass(resp_arb_io_in_0_bits_data_word_bypass),
+ .io_in_0_bits_store_data(resp_arb_io_in_0_bits_store_data),
+ .io_out_ready(resp_arb_io_out_ready),
+ .io_out_valid(resp_arb_io_out_valid),
+ .io_out_bits_addr(resp_arb_io_out_bits_addr),
+ .io_out_bits_tag(resp_arb_io_out_bits_tag),
+ .io_out_bits_cmd(resp_arb_io_out_bits_cmd),
+ .io_out_bits_typ(resp_arb_io_out_bits_typ),
+ .io_out_bits_data(resp_arb_io_out_bits_data),
+ .io_out_bits_nack(resp_arb_io_out_bits_nack),
+ .io_out_bits_replay(resp_arb_io_out_bits_replay),
+ .io_out_bits_has_data(resp_arb_io_out_bits_has_data),
+ .io_out_bits_data_word_bypass(resp_arb_io_out_bits_data_word_bypass),
+ .io_out_bits_store_data(resp_arb_io_out_bits_store_data),
+ .io_chosen(resp_arb_io_chosen)
+ );
+ IOMSHR T_2812 (
+ .clk(T_2812_clk),
+ .reset(T_2812_reset),
+ .io_req_ready(T_2812_io_req_ready),
+ .io_req_valid(T_2812_io_req_valid),
+ .io_req_bits_addr(T_2812_io_req_bits_addr),
+ .io_req_bits_tag(T_2812_io_req_bits_tag),
+ .io_req_bits_cmd(T_2812_io_req_bits_cmd),
+ .io_req_bits_typ(T_2812_io_req_bits_typ),
+ .io_req_bits_kill(T_2812_io_req_bits_kill),
+ .io_req_bits_phys(T_2812_io_req_bits_phys),
+ .io_req_bits_data(T_2812_io_req_bits_data),
+ .io_acquire_ready(T_2812_io_acquire_ready),
+ .io_acquire_valid(T_2812_io_acquire_valid),
+ .io_acquire_bits_addr_block(T_2812_io_acquire_bits_addr_block),
+ .io_acquire_bits_client_xact_id(T_2812_io_acquire_bits_client_xact_id),
+ .io_acquire_bits_addr_beat(T_2812_io_acquire_bits_addr_beat),
+ .io_acquire_bits_is_builtin_type(T_2812_io_acquire_bits_is_builtin_type),
+ .io_acquire_bits_a_type(T_2812_io_acquire_bits_a_type),
+ .io_acquire_bits_union(T_2812_io_acquire_bits_union),
+ .io_acquire_bits_data(T_2812_io_acquire_bits_data),
+ .io_grant_valid(T_2812_io_grant_valid),
+ .io_grant_bits_addr_beat(T_2812_io_grant_bits_addr_beat),
+ .io_grant_bits_client_xact_id(T_2812_io_grant_bits_client_xact_id),
+ .io_grant_bits_manager_xact_id(T_2812_io_grant_bits_manager_xact_id),
+ .io_grant_bits_is_builtin_type(T_2812_io_grant_bits_is_builtin_type),
+ .io_grant_bits_g_type(T_2812_io_grant_bits_g_type),
+ .io_grant_bits_data(T_2812_io_grant_bits_data),
+ .io_resp_ready(T_2812_io_resp_ready),
+ .io_resp_valid(T_2812_io_resp_valid),
+ .io_resp_bits_addr(T_2812_io_resp_bits_addr),
+ .io_resp_bits_tag(T_2812_io_resp_bits_tag),
+ .io_resp_bits_cmd(T_2812_io_resp_bits_cmd),
+ .io_resp_bits_typ(T_2812_io_resp_bits_typ),
+ .io_resp_bits_data(T_2812_io_resp_bits_data),
+ .io_resp_bits_nack(T_2812_io_resp_bits_nack),
+ .io_resp_bits_replay(T_2812_io_resp_bits_replay),
+ .io_resp_bits_has_data(T_2812_io_resp_bits_has_data),
+ .io_resp_bits_data_word_bypass(T_2812_io_resp_bits_data_word_bypass),
+ .io_resp_bits_store_data(T_2812_io_resp_bits_store_data)
+ );
+ assign io_req_ready = T_2828;
+ assign io_resp_valid = resp_arb_io_out_valid;
+ assign io_resp_bits_addr = resp_arb_io_out_bits_addr;
+ assign io_resp_bits_tag = resp_arb_io_out_bits_tag;
+ assign io_resp_bits_cmd = resp_arb_io_out_bits_cmd;
+ assign io_resp_bits_typ = resp_arb_io_out_bits_typ;
+ assign io_resp_bits_data = resp_arb_io_out_bits_data;
+ assign io_resp_bits_nack = resp_arb_io_out_bits_nack;
+ assign io_resp_bits_replay = resp_arb_io_out_bits_replay;
+ assign io_resp_bits_has_data = resp_arb_io_out_bits_has_data;
+ assign io_resp_bits_data_word_bypass = resp_arb_io_out_bits_data_word_bypass;
+ assign io_resp_bits_store_data = resp_arb_io_out_bits_store_data;
+ assign io_secondary_miss = idx_match;
+ assign io_mem_req_valid = mem_req_arb_io_out_valid;
+ assign io_mem_req_bits_addr_block = mem_req_arb_io_out_bits_addr_block;
+ assign io_mem_req_bits_client_xact_id = mem_req_arb_io_out_bits_client_xact_id;
+ assign io_mem_req_bits_addr_beat = mem_req_arb_io_out_bits_addr_beat;
+ assign io_mem_req_bits_is_builtin_type = mem_req_arb_io_out_bits_is_builtin_type;
+ assign io_mem_req_bits_a_type = mem_req_arb_io_out_bits_a_type;
+ assign io_mem_req_bits_union = mem_req_arb_io_out_bits_union;
+ assign io_mem_req_bits_data = mem_req_arb_io_out_bits_data;
+ assign io_refill_way_en = GEN_0;
+ assign io_refill_addr = GEN_1;
+ assign io_meta_read_valid = meta_read_arb_io_out_valid;
+ assign io_meta_read_bits_idx = meta_read_arb_io_out_bits_idx;
+ assign io_meta_read_bits_tag = meta_read_arb_io_out_bits_tag;
+ assign io_meta_write_valid = meta_write_arb_io_out_valid;
+ assign io_meta_write_bits_idx = meta_write_arb_io_out_bits_idx;
+ assign io_meta_write_bits_way_en = meta_write_arb_io_out_bits_way_en;
+ assign io_meta_write_bits_data_tag = meta_write_arb_io_out_bits_data_tag;
+ assign io_meta_write_bits_data_coh_state = meta_write_arb_io_out_bits_data_coh_state;
+ assign io_replay_valid = replay_arb_io_out_valid;
+ assign io_replay_bits_addr = replay_arb_io_out_bits_addr;
+ assign io_replay_bits_tag = replay_arb_io_out_bits_tag;
+ assign io_replay_bits_cmd = replay_arb_io_out_bits_cmd;
+ assign io_replay_bits_typ = replay_arb_io_out_bits_typ;
+ assign io_replay_bits_kill = replay_arb_io_out_bits_kill;
+ assign io_replay_bits_phys = replay_arb_io_out_bits_phys;
+ assign io_replay_bits_data = sdq_T_2888_data;
+ assign io_wb_req_valid = wb_req_arb_io_out_valid;
+ assign io_wb_req_bits_addr_beat = wb_req_arb_io_out_bits_addr_beat;
+ assign io_wb_req_bits_addr_block = wb_req_arb_io_out_bits_addr_block;
+ assign io_wb_req_bits_client_xact_id = wb_req_arb_io_out_bits_client_xact_id;
+ assign io_wb_req_bits_voluntary = wb_req_arb_io_out_bits_voluntary;
+ assign io_wb_req_bits_r_type = wb_req_arb_io_out_bits_r_type;
+ assign io_wb_req_bits_data = wb_req_arb_io_out_bits_data;
+ assign io_wb_req_bits_way_en = wb_req_arb_io_out_bits_way_en;
+ assign io_probe_rdy = T_2744 ? 1'h0 : T_2728 ? 1'h0 : 1'h1;
+ assign io_fence_rdy = T_2818 ? 1'h0 : T_2741 ? 1'h0 : T_2725 ? 1'h0 : 1'h1;
+ assign cacheable = io_req_bits_addr < 31'h40000000;
+ assign T_1807 = sdq_val;
+ assign T_1808 = ~ T_1807;
+ assign T_1809 = T_1808[0];
+ assign T_1810 = T_1808[1];
+ assign T_1811 = T_1808[2];
+ assign T_1812 = T_1808[3];
+ assign T_1813 = T_1808[4];
+ assign T_1814 = T_1808[5];
+ assign T_1815 = T_1808[6];
+ assign T_1816 = T_1808[7];
+ assign T_1817 = T_1808[8];
+ assign T_1818 = T_1808[9];
+ assign T_1819 = T_1808[10];
+ assign T_1820 = T_1808[11];
+ assign T_1821 = T_1808[12];
+ assign T_1822 = T_1808[13];
+ assign T_1823 = T_1808[14];
+ assign T_1824 = T_1808[15];
+ assign T_1825 = T_1808[16];
+ assign T_1827_0 = T_1809;
+ assign T_1827_1 = T_1810;
+ assign T_1827_2 = T_1811;
+ assign T_1827_3 = T_1812;
+ assign T_1827_4 = T_1813;
+ assign T_1827_5 = T_1814;
+ assign T_1827_6 = T_1815;
+ assign T_1827_7 = T_1816;
+ assign T_1827_8 = T_1817;
+ assign T_1827_9 = T_1818;
+ assign T_1827_10 = T_1819;
+ assign T_1827_11 = T_1820;
+ assign T_1827_12 = T_1821;
+ assign T_1827_13 = T_1822;
+ assign T_1827_14 = T_1823;
+ assign T_1827_15 = T_1824;
+ assign T_1827_16 = T_1825;
+ assign T_1863 = T_1827_15 ? 4'hf : 5'h10;
+ assign T_1864 = T_1827_14 ? 4'he : T_1863;
+ assign T_1865 = T_1827_13 ? 4'hd : T_1864;
+ assign T_1866 = T_1827_12 ? 4'hc : T_1865;
+ assign T_1867 = T_1827_11 ? 4'hb : T_1866;
+ assign T_1868 = T_1827_10 ? 4'ha : T_1867;
+ assign T_1869 = T_1827_9 ? 4'h9 : T_1868;
+ assign T_1870 = T_1827_8 ? 4'h8 : T_1869;
+ assign T_1871 = T_1827_7 ? 3'h7 : T_1870;
+ assign T_1872 = T_1827_6 ? 3'h6 : T_1871;
+ assign T_1873 = T_1827_5 ? 3'h5 : T_1872;
+ assign T_1874 = T_1827_4 ? 3'h4 : T_1873;
+ assign T_1875 = T_1827_3 ? 2'h3 : T_1874;
+ assign T_1876 = T_1827_2 ? 2'h2 : T_1875;
+ assign T_1877 = T_1827_1 ? 1'h1 : T_1876;
+ assign sdq_alloc_id = T_1827_0 ? 1'h0 : T_1877;
+ assign T_1879 = ~ sdq_val;
+ assign T_1881 = T_1879 == 1'h0;
+ assign sdq_rdy = T_1881 == 1'h0;
+ assign T_1884 = io_req_valid & io_req_ready;
+ assign T_1885 = T_1884 & cacheable;
+ assign T_1886 = io_req_bits_cmd == 5'h1;
+ assign T_1887 = io_req_bits_cmd == 5'h7;
+ assign T_1888 = T_1886 | T_1887;
+ assign T_1889 = io_req_bits_cmd[3];
+ assign T_1890 = io_req_bits_cmd == 5'h4;
+ assign T_1891 = T_1889 | T_1890;
+ assign T_1892 = T_1888 | T_1891;
+ assign sdq_enq = T_1885 & T_1892;
+ assign sdq_T_2888_addr = T_2887;
+ assign sdq_T_2888_en = 1'h1;
+ assign sdq_T_2888_clk = clk;
+ assign sdq_T_2888_data = sdq[sdq_T_2888_addr];
+ assign sdq_T_1896_data = io_req_bits_data;
+ assign sdq_T_1896_addr = sdq_alloc_id;
+ assign sdq_T_1896_mask = sdq_enq ? 1'h1 : 1'h0;
+ assign sdq_T_1896_en = sdq_enq ? 1'h1 : 1'h0;
+ assign sdq_T_1896_clk = clk;
+ assign idxMatch_0 = T_2714_io_idx_match;
+ assign idxMatch_1 = T_2730_io_idx_match;
+ assign tagList_0 = T_2714_io_tag;
+ assign tagList_1 = T_2730_io_tag;
+ assign T_1922 = idxMatch_0 ? tagList_0 : 1'h0;
+ assign T_1924 = idxMatch_1 ? tagList_1 : 1'h0;
+ assign T_1926 = T_1922 | T_1924;
+ assign T_1927 = T_1926;
+ assign T_1928 = io_req_bits_addr[39:12];
+ assign tag_match = T_1927 == T_1928;
+ assign wbTagList_0 = T_2715;
+ assign wbTagList_1 = T_2731;
+ assign refillMux_0_way_en = T_2714_io_refill_way_en;
+ assign refillMux_0_addr = T_2714_io_refill_addr;
+ assign refillMux_1_way_en = T_2730_io_refill_way_en;
+ assign refillMux_1_addr = T_2730_io_refill_addr;
+ assign meta_read_arb_clk = clk;
+ assign meta_read_arb_reset = reset;
+ assign meta_read_arb_io_in_0_valid = T_2714_io_meta_read_valid;
+ assign meta_read_arb_io_in_0_bits_idx = T_2714_io_meta_read_bits_idx;
+ assign meta_read_arb_io_in_0_bits_tag = T_2714_io_meta_read_bits_tag;
+ assign meta_read_arb_io_in_1_valid = T_2730_io_meta_read_valid;
+ assign meta_read_arb_io_in_1_bits_idx = T_2730_io_meta_read_bits_idx;
+ assign meta_read_arb_io_in_1_bits_tag = T_2730_io_meta_read_bits_tag;
+ assign meta_read_arb_io_out_ready = io_meta_read_ready;
+ assign meta_write_arb_clk = clk;
+ assign meta_write_arb_reset = reset;
+ assign meta_write_arb_io_in_0_valid = T_2714_io_meta_write_valid;
+ assign meta_write_arb_io_in_0_bits_idx = T_2714_io_meta_write_bits_idx;
+ assign meta_write_arb_io_in_0_bits_way_en = T_2714_io_meta_write_bits_way_en;
+ assign meta_write_arb_io_in_0_bits_data_tag = T_2714_io_meta_write_bits_data_tag;
+ assign meta_write_arb_io_in_0_bits_data_coh_state = T_2714_io_meta_write_bits_data_coh_state;
+ assign meta_write_arb_io_in_1_valid = T_2730_io_meta_write_valid;
+ assign meta_write_arb_io_in_1_bits_idx = T_2730_io_meta_write_bits_idx;
+ assign meta_write_arb_io_in_1_bits_way_en = T_2730_io_meta_write_bits_way_en;
+ assign meta_write_arb_io_in_1_bits_data_tag = T_2730_io_meta_write_bits_data_tag;
+ assign meta_write_arb_io_in_1_bits_data_coh_state = T_2730_io_meta_write_bits_data_coh_state;
+ assign meta_write_arb_io_out_ready = io_meta_write_ready;
+ assign mem_req_arb_clk = clk;
+ assign mem_req_arb_reset = reset;
+ assign mem_req_arb_io_in_0_valid = T_2714_io_mem_req_valid;
+ assign mem_req_arb_io_in_0_bits_addr_block = T_2714_io_mem_req_bits_addr_block;
+ assign mem_req_arb_io_in_0_bits_client_xact_id = T_2714_io_mem_req_bits_client_xact_id;
+ assign mem_req_arb_io_in_0_bits_addr_beat = T_2714_io_mem_req_bits_addr_beat;
+ assign mem_req_arb_io_in_0_bits_is_builtin_type = T_2714_io_mem_req_bits_is_builtin_type;
+ assign mem_req_arb_io_in_0_bits_a_type = T_2714_io_mem_req_bits_a_type;
+ assign mem_req_arb_io_in_0_bits_union = T_2714_io_mem_req_bits_union;
+ assign mem_req_arb_io_in_0_bits_data = T_2714_io_mem_req_bits_data;
+ assign mem_req_arb_io_in_1_valid = T_2730_io_mem_req_valid;
+ assign mem_req_arb_io_in_1_bits_addr_block = T_2730_io_mem_req_bits_addr_block;
+ assign mem_req_arb_io_in_1_bits_client_xact_id = T_2730_io_mem_req_bits_client_xact_id;
+ assign mem_req_arb_io_in_1_bits_addr_beat = T_2730_io_mem_req_bits_addr_beat;
+ assign mem_req_arb_io_in_1_bits_is_builtin_type = T_2730_io_mem_req_bits_is_builtin_type;
+ assign mem_req_arb_io_in_1_bits_a_type = T_2730_io_mem_req_bits_a_type;
+ assign mem_req_arb_io_in_1_bits_union = T_2730_io_mem_req_bits_union;
+ assign mem_req_arb_io_in_1_bits_data = T_2730_io_mem_req_bits_data;
+ assign mem_req_arb_io_in_2_valid = T_2812_io_acquire_valid;
+ assign mem_req_arb_io_in_2_bits_addr_block = T_2812_io_acquire_bits_addr_block;
+ assign mem_req_arb_io_in_2_bits_client_xact_id = T_2812_io_acquire_bits_client_xact_id;
+ assign mem_req_arb_io_in_2_bits_addr_beat = T_2812_io_acquire_bits_addr_beat;
+ assign mem_req_arb_io_in_2_bits_is_builtin_type = T_2812_io_acquire_bits_is_builtin_type;
+ assign mem_req_arb_io_in_2_bits_a_type = T_2812_io_acquire_bits_a_type;
+ assign mem_req_arb_io_in_2_bits_union = T_2812_io_acquire_bits_union;
+ assign mem_req_arb_io_in_2_bits_data = T_2812_io_acquire_bits_data;
+ assign mem_req_arb_io_out_ready = io_mem_req_ready;
+ assign wb_req_arb_clk = clk;
+ assign wb_req_arb_reset = reset;
+ assign wb_req_arb_io_in_0_valid = T_2714_io_wb_req_valid;
+ assign wb_req_arb_io_in_0_bits_addr_beat = T_2714_io_wb_req_bits_addr_beat;
+ assign wb_req_arb_io_in_0_bits_addr_block = T_2714_io_wb_req_bits_addr_block;
+ assign wb_req_arb_io_in_0_bits_client_xact_id = T_2714_io_wb_req_bits_client_xact_id;
+ assign wb_req_arb_io_in_0_bits_voluntary = T_2714_io_wb_req_bits_voluntary;
+ assign wb_req_arb_io_in_0_bits_r_type = T_2714_io_wb_req_bits_r_type;
+ assign wb_req_arb_io_in_0_bits_data = T_2714_io_wb_req_bits_data;
+ assign wb_req_arb_io_in_0_bits_way_en = T_2714_io_wb_req_bits_way_en;
+ assign wb_req_arb_io_in_1_valid = T_2730_io_wb_req_valid;
+ assign wb_req_arb_io_in_1_bits_addr_beat = T_2730_io_wb_req_bits_addr_beat;
+ assign wb_req_arb_io_in_1_bits_addr_block = T_2730_io_wb_req_bits_addr_block;
+ assign wb_req_arb_io_in_1_bits_client_xact_id = T_2730_io_wb_req_bits_client_xact_id;
+ assign wb_req_arb_io_in_1_bits_voluntary = T_2730_io_wb_req_bits_voluntary;
+ assign wb_req_arb_io_in_1_bits_r_type = T_2730_io_wb_req_bits_r_type;
+ assign wb_req_arb_io_in_1_bits_data = T_2730_io_wb_req_bits_data;
+ assign wb_req_arb_io_in_1_bits_way_en = T_2730_io_wb_req_bits_way_en;
+ assign wb_req_arb_io_out_ready = io_wb_req_ready;
+ assign replay_arb_clk = clk;
+ assign replay_arb_reset = reset;
+ assign replay_arb_io_in_0_valid = T_2714_io_replay_valid;
+ assign replay_arb_io_in_0_bits_addr = T_2714_io_replay_bits_addr;
+ assign replay_arb_io_in_0_bits_tag = T_2714_io_replay_bits_tag;
+ assign replay_arb_io_in_0_bits_cmd = T_2714_io_replay_bits_cmd;
+ assign replay_arb_io_in_0_bits_typ = T_2714_io_replay_bits_typ;
+ assign replay_arb_io_in_0_bits_kill = T_2714_io_replay_bits_kill;
+ assign replay_arb_io_in_0_bits_phys = T_2714_io_replay_bits_phys;
+ assign replay_arb_io_in_0_bits_sdq_id = T_2714_io_replay_bits_sdq_id;
+ assign replay_arb_io_in_1_valid = T_2730_io_replay_valid;
+ assign replay_arb_io_in_1_bits_addr = T_2730_io_replay_bits_addr;
+ assign replay_arb_io_in_1_bits_tag = T_2730_io_replay_bits_tag;
+ assign replay_arb_io_in_1_bits_cmd = T_2730_io_replay_bits_cmd;
+ assign replay_arb_io_in_1_bits_typ = T_2730_io_replay_bits_typ;
+ assign replay_arb_io_in_1_bits_kill = T_2730_io_replay_bits_kill;
+ assign replay_arb_io_in_1_bits_phys = T_2730_io_replay_bits_phys;
+ assign replay_arb_io_in_1_bits_sdq_id = T_2730_io_replay_bits_sdq_id;
+ assign replay_arb_io_out_ready = io_replay_ready;
+ assign alloc_arb_clk = clk;
+ assign alloc_arb_reset = reset;
+ assign alloc_arb_io_in_0_valid = T_2714_io_req_pri_rdy;
+ assign alloc_arb_io_in_0_bits = GEN_4;
+ assign alloc_arb_io_in_1_valid = T_2730_io_req_pri_rdy;
+ assign alloc_arb_io_in_1_bits = GEN_5;
+ assign alloc_arb_io_out_ready = T_2750;
+ assign T_2714_clk = clk;
+ assign T_2714_reset = reset;
+ assign T_2714_io_req_pri_val = alloc_arb_io_in_0_ready;
+ assign T_2714_io_req_sec_val = T_2717;
+ assign T_2714_io_req_bits_addr = io_req_bits_addr;
+ assign T_2714_io_req_bits_tag = io_req_bits_tag;
+ assign T_2714_io_req_bits_cmd = io_req_bits_cmd;
+ assign T_2714_io_req_bits_typ = io_req_bits_typ;
+ assign T_2714_io_req_bits_kill = io_req_bits_kill;
+ assign T_2714_io_req_bits_phys = io_req_bits_phys;
+ assign T_2714_io_req_bits_sdq_id = sdq_alloc_id;
+ assign T_2714_io_req_bits_tag_match = io_req_bits_tag_match;
+ assign T_2714_io_req_bits_old_meta_tag = io_req_bits_old_meta_tag;
+ assign T_2714_io_req_bits_old_meta_coh_state = io_req_bits_old_meta_coh_state;
+ assign T_2714_io_req_bits_way_en = io_req_bits_way_en;
+ assign T_2714_io_mem_req_ready = mem_req_arb_io_in_0_ready;
+ assign T_2714_io_meta_read_ready = meta_read_arb_io_in_0_ready;
+ assign T_2714_io_meta_write_ready = meta_write_arb_io_in_0_ready;
+ assign T_2714_io_replay_ready = replay_arb_io_in_0_ready;
+ assign T_2714_io_mem_grant_valid = T_2720;
+ assign T_2714_io_mem_grant_bits_addr_beat = io_mem_grant_bits_addr_beat;
+ assign T_2714_io_mem_grant_bits_client_xact_id = io_mem_grant_bits_client_xact_id;
+ assign T_2714_io_mem_grant_bits_manager_xact_id = io_mem_grant_bits_manager_xact_id;
+ assign T_2714_io_mem_grant_bits_is_builtin_type = io_mem_grant_bits_is_builtin_type;
+ assign T_2714_io_mem_grant_bits_g_type = io_mem_grant_bits_g_type;
+ assign T_2714_io_mem_grant_bits_data = io_mem_grant_bits_data;
+ assign T_2714_io_wb_req_ready = wb_req_arb_io_in_0_ready;
+ assign T_2715 = T_2714_io_wb_req_bits_addr_block[25:6];
+ assign T_2716 = io_req_valid & sdq_rdy;
+ assign T_2717 = T_2716 & tag_match;
+ assign T_2719 = io_mem_grant_bits_client_xact_id == 1'h0;
+ assign T_2720 = io_mem_grant_valid & T_2719;
+ assign T_2721 = 1'h0 | T_2714_io_req_pri_rdy;
+ assign T_2722 = 1'h0 | T_2714_io_req_sec_rdy;
+ assign T_2723 = 1'h0 | T_2714_io_idx_match;
+ assign T_2725 = T_2714_io_req_pri_rdy == 1'h0;
+ assign T_2728 = T_2714_io_probe_rdy == 1'h0;
+ assign T_2730_clk = clk;
+ assign T_2730_reset = reset;
+ assign T_2730_io_req_pri_val = alloc_arb_io_in_1_ready;
+ assign T_2730_io_req_sec_val = T_2733;
+ assign T_2730_io_req_bits_addr = io_req_bits_addr;
+ assign T_2730_io_req_bits_tag = io_req_bits_tag;
+ assign T_2730_io_req_bits_cmd = io_req_bits_cmd;
+ assign T_2730_io_req_bits_typ = io_req_bits_typ;
+ assign T_2730_io_req_bits_kill = io_req_bits_kill;
+ assign T_2730_io_req_bits_phys = io_req_bits_phys;
+ assign T_2730_io_req_bits_sdq_id = sdq_alloc_id;
+ assign T_2730_io_req_bits_tag_match = io_req_bits_tag_match;
+ assign T_2730_io_req_bits_old_meta_tag = io_req_bits_old_meta_tag;
+ assign T_2730_io_req_bits_old_meta_coh_state = io_req_bits_old_meta_coh_state;
+ assign T_2730_io_req_bits_way_en = io_req_bits_way_en;
+ assign T_2730_io_mem_req_ready = mem_req_arb_io_in_1_ready;
+ assign T_2730_io_meta_read_ready = meta_read_arb_io_in_1_ready;
+ assign T_2730_io_meta_write_ready = meta_write_arb_io_in_1_ready;
+ assign T_2730_io_replay_ready = replay_arb_io_in_1_ready;
+ assign T_2730_io_mem_grant_valid = T_2736;
+ assign T_2730_io_mem_grant_bits_addr_beat = io_mem_grant_bits_addr_beat;
+ assign T_2730_io_mem_grant_bits_client_xact_id = io_mem_grant_bits_client_xact_id;
+ assign T_2730_io_mem_grant_bits_manager_xact_id = io_mem_grant_bits_manager_xact_id;
+ assign T_2730_io_mem_grant_bits_is_builtin_type = io_mem_grant_bits_is_builtin_type;
+ assign T_2730_io_mem_grant_bits_g_type = io_mem_grant_bits_g_type;
+ assign T_2730_io_mem_grant_bits_data = io_mem_grant_bits_data;
+ assign T_2730_io_wb_req_ready = wb_req_arb_io_in_1_ready;
+ assign T_2731 = T_2730_io_wb_req_bits_addr_block[25:6];
+ assign T_2732 = io_req_valid & sdq_rdy;
+ assign T_2733 = T_2732 & tag_match;
+ assign T_2735 = io_mem_grant_bits_client_xact_id == 1'h1;
+ assign T_2736 = io_mem_grant_valid & T_2735;
+ assign pri_rdy = T_2721 | T_2730_io_req_pri_rdy;
+ assign sec_rdy = T_2722 | T_2730_io_req_sec_rdy;
+ assign idx_match = T_2723 | T_2730_io_idx_match;
+ assign T_2741 = T_2730_io_req_pri_rdy == 1'h0;
+ assign T_2744 = T_2730_io_probe_rdy == 1'h0;
+ assign T_2746 = io_req_valid & sdq_rdy;
+ assign T_2747 = T_2746 & cacheable;
+ assign T_2749 = idx_match == 1'h0;
+ assign T_2750 = T_2747 & T_2749;
+ assign mmio_alloc_arb_clk = clk;
+ assign mmio_alloc_arb_reset = reset;
+ assign mmio_alloc_arb_io_in_0_valid = T_2812_io_req_ready;
+ assign mmio_alloc_arb_io_in_0_bits = GEN_6;
+ assign mmio_alloc_arb_io_out_ready = T_2822;
+ assign resp_arb_clk = clk;
+ assign resp_arb_reset = reset;
+ assign resp_arb_io_in_0_valid = T_2812_io_resp_valid;
+ assign resp_arb_io_in_0_bits_addr = T_2812_io_resp_bits_addr;
+ assign resp_arb_io_in_0_bits_tag = T_2812_io_resp_bits_tag;
+ assign resp_arb_io_in_0_bits_cmd = T_2812_io_resp_bits_cmd;
+ assign resp_arb_io_in_0_bits_typ = T_2812_io_resp_bits_typ;
+ assign resp_arb_io_in_0_bits_data = T_2812_io_resp_bits_data;
+ assign resp_arb_io_in_0_bits_nack = T_2812_io_resp_bits_nack;
+ assign resp_arb_io_in_0_bits_replay = T_2812_io_resp_bits_replay;
+ assign resp_arb_io_in_0_bits_has_data = T_2812_io_resp_bits_has_data;
+ assign resp_arb_io_in_0_bits_data_word_bypass = T_2812_io_resp_bits_data_word_bypass;
+ assign resp_arb_io_in_0_bits_store_data = T_2812_io_resp_bits_store_data;
+ assign resp_arb_io_out_ready = io_resp_ready;
+ assign T_2812_clk = clk;
+ assign T_2812_reset = reset;
+ assign T_2812_io_req_valid = mmio_alloc_arb_io_in_0_ready;
+ assign T_2812_io_req_bits_addr = io_req_bits_addr;
+ assign T_2812_io_req_bits_tag = io_req_bits_tag;
+ assign T_2812_io_req_bits_cmd = io_req_bits_cmd;
+ assign T_2812_io_req_bits_typ = io_req_bits_typ;
+ assign T_2812_io_req_bits_kill = io_req_bits_kill;
+ assign T_2812_io_req_bits_phys = io_req_bits_phys;
+ assign T_2812_io_req_bits_data = io_req_bits_data;
+ assign T_2812_io_acquire_ready = mem_req_arb_io_in_2_ready;
+ assign T_2812_io_grant_valid = T_2816;
+ assign T_2812_io_grant_bits_addr_beat = io_mem_grant_bits_addr_beat;
+ assign T_2812_io_grant_bits_client_xact_id = io_mem_grant_bits_client_xact_id;
+ assign T_2812_io_grant_bits_manager_xact_id = io_mem_grant_bits_manager_xact_id;
+ assign T_2812_io_grant_bits_is_builtin_type = io_mem_grant_bits_is_builtin_type;
+ assign T_2812_io_grant_bits_g_type = io_mem_grant_bits_g_type;
+ assign T_2812_io_grant_bits_data = io_mem_grant_bits_data;
+ assign T_2812_io_resp_ready = resp_arb_io_in_0_ready;
+ assign mmio_rdy = 1'h0 | T_2812_io_req_ready;
+ assign T_2815 = io_mem_grant_bits_client_xact_id == 2'h2;
+ assign T_2816 = io_mem_grant_valid & T_2815;
+ assign T_2818 = T_2812_io_req_ready == 1'h0;
+ assign T_2821 = cacheable == 1'h0;
+ assign T_2822 = io_req_valid & T_2821;
+ assign T_2824 = cacheable == 1'h0;
+ assign T_2825 = tag_match & sec_rdy;
+ assign T_2826 = idx_match ? T_2825 : pri_rdy;
+ assign T_2827 = T_2826 & sdq_rdy;
+ assign T_2828 = T_2824 ? mmio_rdy : T_2827;
+ assign GEN_0 = GEN_2 ? refillMux_1_way_en : refillMux_0_way_en;
+ assign GEN_1 = GEN_3 ? refillMux_1_addr : refillMux_0_addr;
+ assign T_2878 = io_replay_ready & io_replay_valid;
+ assign T_2879 = io_replay_bits_cmd == 5'h1;
+ assign T_2880 = io_replay_bits_cmd == 5'h7;
+ assign T_2881 = T_2879 | T_2880;
+ assign T_2882 = io_replay_bits_cmd[3];
+ assign T_2883 = io_replay_bits_cmd == 5'h4;
+ assign T_2884 = T_2882 | T_2883;
+ assign T_2885 = T_2881 | T_2884;
+ assign free_sdq = T_2878 & T_2885;
+ assign T_2889 = io_replay_valid | sdq_enq;
+ assign T_2891 = 1'h1 << replay_arb_io_out_bits_sdq_id;
+ assign T_2893 = 17'h0 - free_sdq;
+ assign T_2894 = T_2893[16:0];
+ assign T_2895 = T_2891 & T_2894;
+ assign T_2896 = ~ T_2895;
+ assign T_2897 = sdq_val & T_2896;
+ assign T_2898 = sdq_val;
+ assign T_2899 = ~ T_2898;
+ assign T_2900 = T_2899[0];
+ assign T_2901 = T_2899[1];
+ assign T_2902 = T_2899[2];
+ assign T_2903 = T_2899[3];
+ assign T_2904 = T_2899[4];
+ assign T_2905 = T_2899[5];
+ assign T_2906 = T_2899[6];
+ assign T_2907 = T_2899[7];
+ assign T_2908 = T_2899[8];
+ assign T_2909 = T_2899[9];
+ assign T_2910 = T_2899[10];
+ assign T_2911 = T_2899[11];
+ assign T_2912 = T_2899[12];
+ assign T_2913 = T_2899[13];
+ assign T_2914 = T_2899[14];
+ assign T_2915 = T_2899[15];
+ assign T_2916 = T_2899[16];
+ assign T_2935_0 = 17'h1;
+ assign T_2935_1 = 17'h2;
+ assign T_2935_2 = 17'h4;
+ assign T_2935_3 = 17'h8;
+ assign T_2935_4 = 17'h10;
+ assign T_2935_5 = 17'h20;
+ assign T_2935_6 = 17'h40;
+ assign T_2935_7 = 17'h80;
+ assign T_2935_8 = 17'h100;
+ assign T_2935_9 = 17'h200;
+ assign T_2935_10 = 17'h400;
+ assign T_2935_11 = 17'h800;
+ assign T_2935_12 = 17'h1000;
+ assign T_2935_13 = 17'h2000;
+ assign T_2935_14 = 17'h4000;
+ assign T_2935_15 = 17'h8000;
+ assign T_2935_16 = 17'h10000;
+ assign T_2956 = T_2916 ? T_2935_16 : 17'h0;
+ assign T_2957 = T_2915 ? T_2935_15 : T_2956;
+ assign T_2958 = T_2914 ? T_2935_14 : T_2957;
+ assign T_2959 = T_2913 ? T_2935_13 : T_2958;
+ assign T_2960 = T_2912 ? T_2935_12 : T_2959;
+ assign T_2961 = T_2911 ? T_2935_11 : T_2960;
+ assign T_2962 = T_2910 ? T_2935_10 : T_2961;
+ assign T_2963 = T_2909 ? T_2935_9 : T_2962;
+ assign T_2964 = T_2908 ? T_2935_8 : T_2963;
+ assign T_2965 = T_2907 ? T_2935_7 : T_2964;
+ assign T_2966 = T_2906 ? T_2935_6 : T_2965;
+ assign T_2967 = T_2905 ? T_2935_5 : T_2966;
+ assign T_2968 = T_2904 ? T_2935_4 : T_2967;
+ assign T_2969 = T_2903 ? T_2935_3 : T_2968;
+ assign T_2970 = T_2902 ? T_2935_2 : T_2969;
+ assign T_2971 = T_2901 ? T_2935_1 : T_2970;
+ assign T_2972 = T_2900 ? T_2935_0 : T_2971;
+ assign T_2974 = 17'h0 - sdq_enq;
+ assign T_2975 = T_2974[16:0];
+ assign T_2976 = T_2972 & T_2975;
+ assign T_2977 = T_2897 | T_2976;
+ assign GEN_2 = 1'h1 == io_mem_grant_bits_client_xact_id;
+ assign GEN_3 = 1'h1 == io_mem_grant_bits_client_xact_id;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ sdq_val = {1{$random}};
+ for (initvar = 0; initvar < 17; initvar = initvar+1)
+ sdq[initvar] = {2{$random}};
+ T_2887 = {1{$random}};
+ GEN_4 = {1{$random}};
+ GEN_5 = {1{$random}};
+ GEN_6 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ sdq_val <= 17'h0;
+ end else begin
+ if(T_2889) begin
+ sdq_val <= T_2977;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(free_sdq) begin
+ T_2887 <= replay_arb_io_out_bits_sdq_id;
+ end else begin
+ ;
+ end
+ end
+ end
+ always @(posedge sdq_T_1896_clk) begin
+ if(sdq_T_1896_en & sdq_T_1896_mask) begin
+ sdq[sdq_T_1896_addr] <= sdq_T_1896_data;
+ end
+ end
+endmodule
+module MetadataArray(
+ input clk,
+ input reset,
+ output io_read_ready,
+ input io_read_valid,
+ input [5:0] io_read_bits_idx,
+ output io_write_ready,
+ input io_write_valid,
+ input [5:0] io_write_bits_idx,
+ input [3:0] io_write_bits_way_en,
+ input [19:0] io_write_bits_data_tag,
+ input [1:0] io_write_bits_data_coh_state,
+ output [19:0] io_resp_0_tag,
+ output [1:0] io_resp_0_coh_state,
+ output [19:0] io_resp_1_tag,
+ output [1:0] io_resp_1_coh_state,
+ output [19:0] io_resp_2_tag,
+ output [1:0] io_resp_2_coh_state,
+ output [19:0] io_resp_3_tag,
+ output [1:0] io_resp_3_coh_state
+);
+ wire [1:0] T_30_state;
+ wire [19:0] rstVal_tag;
+ wire [1:0] rstVal_coh_state;
+ reg [6:0] rst_cnt;
+ wire rst;
+ wire [6:0] waddr;
+ wire [19:0] T_1633_tag;
+ wire [1:0] T_1633_coh_state;
+ wire [21:0] wdata;
+ wire [3:0] T_1708;
+ wire GEN_0;
+ wire [3:0] T_1709;
+ wire T_1710;
+ wire T_1711;
+ wire T_1712;
+ wire T_1713;
+ wire wmask_0;
+ wire wmask_1;
+ wire wmask_2;
+ wire wmask_3;
+ wire [7:0] T_1722;
+ wire [6:0] T_1723;
+ reg [21:0] tag_arr_0 [0:63];
+ wire [21:0] tag_arr_0_T_1761_data;
+ wire [5:0] tag_arr_0_T_1761_addr;
+ wire tag_arr_0_T_1761_en;
+ wire tag_arr_0_T_1761_clk;
+ reg [5:0] GEN_1;
+ reg GEN_2;
+ wire [21:0] tag_arr_0_T_1751_data;
+ wire [5:0] tag_arr_0_T_1751_addr;
+ wire tag_arr_0_T_1751_mask;
+ wire tag_arr_0_T_1751_en;
+ wire tag_arr_0_T_1751_clk;
+ reg [21:0] tag_arr_1 [0:63];
+ wire [21:0] tag_arr_1_T_1761_data;
+ wire [5:0] tag_arr_1_T_1761_addr;
+ wire tag_arr_1_T_1761_en;
+ wire tag_arr_1_T_1761_clk;
+ reg [5:0] GEN_3;
+ reg GEN_4;
+ wire [21:0] tag_arr_1_T_1751_data;
+ wire [5:0] tag_arr_1_T_1751_addr;
+ wire tag_arr_1_T_1751_mask;
+ wire tag_arr_1_T_1751_en;
+ wire tag_arr_1_T_1751_clk;
+ reg [21:0] tag_arr_2 [0:63];
+ wire [21:0] tag_arr_2_T_1761_data;
+ wire [5:0] tag_arr_2_T_1761_addr;
+ wire tag_arr_2_T_1761_en;
+ wire tag_arr_2_T_1761_clk;
+ reg [5:0] GEN_5;
+ reg GEN_6;
+ wire [21:0] tag_arr_2_T_1751_data;
+ wire [5:0] tag_arr_2_T_1751_addr;
+ wire tag_arr_2_T_1751_mask;
+ wire tag_arr_2_T_1751_en;
+ wire tag_arr_2_T_1751_clk;
+ reg [21:0] tag_arr_3 [0:63];
+ wire [21:0] tag_arr_3_T_1761_data;
+ wire [5:0] tag_arr_3_T_1761_addr;
+ wire tag_arr_3_T_1761_en;
+ wire tag_arr_3_T_1761_clk;
+ reg [5:0] GEN_7;
+ reg GEN_8;
+ wire [21:0] tag_arr_3_T_1751_data;
+ wire [5:0] tag_arr_3_T_1751_addr;
+ wire tag_arr_3_T_1751_mask;
+ wire tag_arr_3_T_1751_en;
+ wire tag_arr_3_T_1751_clk;
+ wire T_1741;
+ wire [21:0] T_1743_0;
+ wire [21:0] T_1743_1;
+ wire [21:0] T_1743_2;
+ wire [21:0] T_1743_3;
+ wire [5:0] T_1758;
+ wire [43:0] T_1767;
+ wire [43:0] T_1768;
+ wire [87:0] tags;
+ wire [19:0] T_2428_0_tag;
+ wire [1:0] T_2428_0_coh_state;
+ wire [19:0] T_2428_1_tag;
+ wire [1:0] T_2428_1_coh_state;
+ wire [19:0] T_2428_2_tag;
+ wire [1:0] T_2428_2_coh_state;
+ wire [19:0] T_2428_3_tag;
+ wire [1:0] T_2428_3_coh_state;
+ wire [1:0] T_2794;
+ wire [19:0] T_2795;
+ wire [1:0] T_2796;
+ wire [19:0] T_2797;
+ wire [1:0] T_2798;
+ wire [19:0] T_2799;
+ wire [1:0] T_2800;
+ wire [19:0] T_2801;
+ wire T_2803;
+ wire T_2805;
+ wire T_2806;
+ wire T_2808;
+ assign io_read_ready = T_2806;
+ assign io_write_ready = T_2808;
+ assign io_resp_0_tag = T_2428_0_tag;
+ assign io_resp_0_coh_state = T_2428_0_coh_state;
+ assign io_resp_1_tag = T_2428_1_tag;
+ assign io_resp_1_coh_state = T_2428_1_coh_state;
+ assign io_resp_2_tag = T_2428_2_tag;
+ assign io_resp_2_coh_state = T_2428_2_coh_state;
+ assign io_resp_3_tag = T_2428_3_tag;
+ assign io_resp_3_coh_state = T_2428_3_coh_state;
+ assign T_30_state = 1'h0;
+ assign rstVal_tag = 1'h0;
+ assign rstVal_coh_state = T_30_state;
+ assign rst = rst_cnt < 7'h40;
+ assign waddr = rst ? rst_cnt : io_write_bits_idx;
+ assign T_1633_tag = rst ? rstVal_tag : io_write_bits_data_tag;
+ assign T_1633_coh_state = rst ? rstVal_coh_state : io_write_bits_data_coh_state;
+ assign wdata = {T_1633_tag,T_1633_coh_state};
+ assign T_1708 = $signed(io_write_bits_way_en);
+ assign GEN_0 = $signed(1'h1);
+ assign T_1709 = rst ? $signed(GEN_0) : $signed(T_1708);
+ assign T_1710 = T_1709[0];
+ assign T_1711 = T_1709[1];
+ assign T_1712 = T_1709[2];
+ assign T_1713 = T_1709[3];
+ assign wmask_0 = T_1710;
+ assign wmask_1 = T_1711;
+ assign wmask_2 = T_1712;
+ assign wmask_3 = T_1713;
+ assign T_1722 = rst_cnt + 1'h1;
+ assign T_1723 = T_1722[6:0];
+ assign tag_arr_0_T_1761_addr = T_1758;
+ assign tag_arr_0_T_1761_en = 1'h1;
+ assign tag_arr_0_T_1761_clk = clk;
+ assign tag_arr_0_T_1761_data = tag_arr_0[GEN_1];
+ assign tag_arr_0_T_1751_data = T_1743_0;
+ assign tag_arr_0_T_1751_addr = waddr;
+ assign tag_arr_0_T_1751_mask = T_1741 ? wmask_0 ? 1'h1 : 1'h0 : 1'h0;
+ assign tag_arr_0_T_1751_en = T_1741 ? 1'h1 : 1'h0;
+ assign tag_arr_0_T_1751_clk = clk;
+ assign tag_arr_1_T_1761_addr = T_1758;
+ assign tag_arr_1_T_1761_en = 1'h1;
+ assign tag_arr_1_T_1761_clk = clk;
+ assign tag_arr_1_T_1761_data = tag_arr_1[GEN_3];
+ assign tag_arr_1_T_1751_data = T_1743_1;
+ assign tag_arr_1_T_1751_addr = waddr;
+ assign tag_arr_1_T_1751_mask = T_1741 ? wmask_1 ? 1'h1 : 1'h0 : 1'h0;
+ assign tag_arr_1_T_1751_en = T_1741 ? 1'h1 : 1'h0;
+ assign tag_arr_1_T_1751_clk = clk;
+ assign tag_arr_2_T_1761_addr = T_1758;
+ assign tag_arr_2_T_1761_en = 1'h1;
+ assign tag_arr_2_T_1761_clk = clk;
+ assign tag_arr_2_T_1761_data = tag_arr_2[GEN_5];
+ assign tag_arr_2_T_1751_data = T_1743_2;
+ assign tag_arr_2_T_1751_addr = waddr;
+ assign tag_arr_2_T_1751_mask = T_1741 ? wmask_2 ? 1'h1 : 1'h0 : 1'h0;
+ assign tag_arr_2_T_1751_en = T_1741 ? 1'h1 : 1'h0;
+ assign tag_arr_2_T_1751_clk = clk;
+ assign tag_arr_3_T_1761_addr = T_1758;
+ assign tag_arr_3_T_1761_en = 1'h1;
+ assign tag_arr_3_T_1761_clk = clk;
+ assign tag_arr_3_T_1761_data = tag_arr_3[GEN_7];
+ assign tag_arr_3_T_1751_data = T_1743_3;
+ assign tag_arr_3_T_1751_addr = waddr;
+ assign tag_arr_3_T_1751_mask = T_1741 ? wmask_3 ? 1'h1 : 1'h0 : 1'h0;
+ assign tag_arr_3_T_1751_en = T_1741 ? 1'h1 : 1'h0;
+ assign tag_arr_3_T_1751_clk = clk;
+ assign T_1741 = rst | io_write_valid;
+ assign T_1743_0 = wdata;
+ assign T_1743_1 = wdata;
+ assign T_1743_2 = wdata;
+ assign T_1743_3 = wdata;
+ assign T_1758 = io_read_bits_idx;
+ assign T_1767 = {tag_arr_3_T_1761_data,tag_arr_2_T_1761_data};
+ assign T_1768 = {tag_arr_1_T_1761_data,tag_arr_0_T_1761_data};
+ assign tags = {T_1767,T_1768};
+ assign T_2428_0_tag = T_2795;
+ assign T_2428_0_coh_state = T_2794;
+ assign T_2428_1_tag = T_2797;
+ assign T_2428_1_coh_state = T_2796;
+ assign T_2428_2_tag = T_2799;
+ assign T_2428_2_coh_state = T_2798;
+ assign T_2428_3_tag = T_2801;
+ assign T_2428_3_coh_state = T_2800;
+ assign T_2794 = tags[1:0];
+ assign T_2795 = tags[21:2];
+ assign T_2796 = tags[23:22];
+ assign T_2797 = tags[43:24];
+ assign T_2798 = tags[45:44];
+ assign T_2799 = tags[65:46];
+ assign T_2800 = tags[67:66];
+ assign T_2801 = tags[87:68];
+ assign T_2803 = rst == 1'h0;
+ assign T_2805 = io_write_valid == 1'h0;
+ assign T_2806 = T_2803 & T_2805;
+ assign T_2808 = rst == 1'h0;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ rst_cnt = {1{$random}};
+ for (initvar = 0; initvar < 64; initvar = initvar+1)
+ tag_arr_0[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 64; initvar = initvar+1)
+ tag_arr_1[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 64; initvar = initvar+1)
+ tag_arr_2[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 64; initvar = initvar+1)
+ tag_arr_3[initvar] = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ rst_cnt <= 7'h0;
+ end else begin
+ if(rst) begin
+ rst_cnt <= T_1723;
+ end else begin
+ ;
+ end
+ end
+ end
+ always @(posedge tag_arr_0_T_1761_clk) begin
+ GEN_1 <= tag_arr_0_T_1761_addr;
+ GEN_2 <= tag_arr_0_T_1761_en;
+ end
+ always @(posedge tag_arr_0_T_1751_clk) begin
+ if(tag_arr_0_T_1751_en & tag_arr_0_T_1751_mask) begin
+ tag_arr_0[tag_arr_0_T_1751_addr] <= tag_arr_0_T_1751_data;
+ end
+ end
+ always @(posedge tag_arr_1_T_1761_clk) begin
+ GEN_3 <= tag_arr_1_T_1761_addr;
+ GEN_4 <= tag_arr_1_T_1761_en;
+ end
+ always @(posedge tag_arr_1_T_1751_clk) begin
+ if(tag_arr_1_T_1751_en & tag_arr_1_T_1751_mask) begin
+ tag_arr_1[tag_arr_1_T_1751_addr] <= tag_arr_1_T_1751_data;
+ end
+ end
+ always @(posedge tag_arr_2_T_1761_clk) begin
+ GEN_5 <= tag_arr_2_T_1761_addr;
+ GEN_6 <= tag_arr_2_T_1761_en;
+ end
+ always @(posedge tag_arr_2_T_1751_clk) begin
+ if(tag_arr_2_T_1751_en & tag_arr_2_T_1751_mask) begin
+ tag_arr_2[tag_arr_2_T_1751_addr] <= tag_arr_2_T_1751_data;
+ end
+ end
+ always @(posedge tag_arr_3_T_1761_clk) begin
+ GEN_7 <= tag_arr_3_T_1761_addr;
+ GEN_8 <= tag_arr_3_T_1761_en;
+ end
+ always @(posedge tag_arr_3_T_1751_clk) begin
+ if(tag_arr_3_T_1751_en & tag_arr_3_T_1751_mask) begin
+ tag_arr_3[tag_arr_3_T_1751_addr] <= tag_arr_3_T_1751_data;
+ end
+ end
+endmodule
+module Arbiter_105(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input [5:0] io_in_0_bits_idx,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input [5:0] io_in_1_bits_idx,
+ output io_in_2_ready,
+ input io_in_2_valid,
+ input [5:0] io_in_2_bits_idx,
+ output io_in_3_ready,
+ input io_in_3_valid,
+ input [5:0] io_in_3_bits_idx,
+ output io_in_4_ready,
+ input io_in_4_valid,
+ input [5:0] io_in_4_bits_idx,
+ input io_out_ready,
+ output io_out_valid,
+ output [5:0] io_out_bits_idx,
+ output [2:0] io_chosen
+);
+ wire [2:0] T_128;
+ wire GEN_0;
+ wire [5:0] GEN_1;
+ wire GEN_2;
+ wire T_153;
+ wire T_155;
+ wire T_157;
+ wire T_158;
+ wire T_160;
+ wire T_162;
+ wire T_163;
+ wire T_164;
+ wire T_166;
+ wire T_168;
+ wire T_169;
+ wire T_170;
+ wire T_171;
+ wire T_173;
+ wire T_175;
+ wire T_176;
+ wire T_177;
+ wire T_179;
+ wire T_180;
+ wire T_181;
+ wire T_183;
+ wire T_184;
+ wire T_185;
+ wire T_187;
+ wire T_188;
+ wire T_189;
+ wire T_191;
+ wire T_192;
+ wire T_193;
+ wire [2:0] T_196;
+ wire [2:0] T_198;
+ wire [2:0] T_200;
+ wire [2:0] T_202;
+ wire [2:0] T_203;
+ wire GEN_3;
+ wire GEN_4;
+ wire GEN_5;
+ wire GEN_6;
+ wire GEN_7;
+ wire GEN_8;
+ wire GEN_9;
+ wire GEN_10;
+ assign io_in_0_ready = T_177;
+ assign io_in_1_ready = T_181;
+ assign io_in_2_ready = T_185;
+ assign io_in_3_ready = T_189;
+ assign io_in_4_ready = T_193;
+ assign io_out_valid = GEN_0;
+ assign io_out_bits_idx = GEN_1;
+ assign io_chosen = T_128;
+ assign T_128 = T_203;
+ assign GEN_0 = GEN_3 ? io_in_4_valid : GEN_4 ? io_in_3_valid : GEN_5 ? io_in_2_valid : GEN_6 ? io_in_1_valid : io_in_0_valid;
+ assign GEN_1 = GEN_7 ? io_in_4_bits_idx : GEN_8 ? io_in_3_bits_idx : GEN_9 ? io_in_2_bits_idx : GEN_10 ? io_in_1_bits_idx : io_in_0_bits_idx;
+ assign GEN_2 = 1'h0;
+ assign T_153 = 1'h0 | io_in_0_valid;
+ assign T_155 = T_153 == 1'h0;
+ assign T_157 = 1'h0 | io_in_0_valid;
+ assign T_158 = T_157 | io_in_1_valid;
+ assign T_160 = T_158 == 1'h0;
+ assign T_162 = 1'h0 | io_in_0_valid;
+ assign T_163 = T_162 | io_in_1_valid;
+ assign T_164 = T_163 | io_in_2_valid;
+ assign T_166 = T_164 == 1'h0;
+ assign T_168 = 1'h0 | io_in_0_valid;
+ assign T_169 = T_168 | io_in_1_valid;
+ assign T_170 = T_169 | io_in_2_valid;
+ assign T_171 = T_170 | io_in_3_valid;
+ assign T_173 = T_171 == 1'h0;
+ assign T_175 = 3'h4 == 1'h0;
+ assign T_176 = 1'h0 ? T_175 : 1'h1;
+ assign T_177 = T_176 & io_out_ready;
+ assign T_179 = 3'h4 == 1'h1;
+ assign T_180 = 1'h0 ? T_179 : T_155;
+ assign T_181 = T_180 & io_out_ready;
+ assign T_183 = 3'h4 == 2'h2;
+ assign T_184 = 1'h0 ? T_183 : T_160;
+ assign T_185 = T_184 & io_out_ready;
+ assign T_187 = 3'h4 == 2'h3;
+ assign T_188 = 1'h0 ? T_187 : T_166;
+ assign T_189 = T_188 & io_out_ready;
+ assign T_191 = 3'h4 == 3'h4;
+ assign T_192 = 1'h0 ? T_191 : T_173;
+ assign T_193 = T_192 & io_out_ready;
+ assign T_196 = io_in_3_valid ? 2'h3 : 3'h4;
+ assign T_198 = io_in_2_valid ? 2'h2 : T_196;
+ assign T_200 = io_in_1_valid ? 1'h1 : T_198;
+ assign T_202 = io_in_0_valid ? 1'h0 : T_200;
+ assign T_203 = 1'h0 ? 3'h4 : T_202;
+ assign GEN_3 = 3'h4 == T_128;
+ assign GEN_4 = 2'h3 == T_128;
+ assign GEN_5 = 2'h2 == T_128;
+ assign GEN_6 = 1'h1 == T_128;
+ assign GEN_7 = 3'h4 == T_128;
+ assign GEN_8 = 2'h3 == T_128;
+ assign GEN_9 = 2'h2 == T_128;
+ assign GEN_10 = 1'h1 == T_128;
+endmodule
+module DataArray(
+ input clk,
+ input reset,
+ output io_read_ready,
+ input io_read_valid,
+ input [3:0] io_read_bits_way_en,
+ input [11:0] io_read_bits_addr,
+ output io_write_ready,
+ input io_write_valid,
+ input [3:0] io_write_bits_way_en,
+ input [11:0] io_write_bits_addr,
+ input [1:0] io_write_bits_wmask,
+ input [127:0] io_write_bits_data,
+ output [127:0] io_resp_0,
+ output [127:0] io_resp_1,
+ output [127:0] io_resp_2,
+ output [127:0] io_resp_3
+);
+ wire [7:0] waddr;
+ wire [7:0] raddr;
+ wire [1:0] T_572;
+ wire [1:0] T_573;
+ wire [127:0] T_582_0;
+ wire [127:0] T_582_1;
+ reg [11:0] T_586;
+ reg [63:0] T_599_0 [0:255];
+ wire [63:0] T_599_0_T_632_data;
+ wire [7:0] T_599_0_T_632_addr;
+ wire T_599_0_T_632_en;
+ wire T_599_0_T_632_clk;
+ reg [7:0] GEN_8;
+ reg GEN_9;
+ wire [63:0] T_599_0_T_621_data;
+ wire [7:0] T_599_0_T_621_addr;
+ wire T_599_0_T_621_mask;
+ wire T_599_0_T_621_en;
+ wire T_599_0_T_621_clk;
+ reg [63:0] T_599_1 [0:255];
+ wire [63:0] T_599_1_T_632_data;
+ wire [7:0] T_599_1_T_632_addr;
+ wire T_599_1_T_632_en;
+ wire T_599_1_T_632_clk;
+ reg [7:0] GEN_10;
+ reg GEN_11;
+ wire [63:0] T_599_1_T_621_data;
+ wire [7:0] T_599_1_T_621_addr;
+ wire T_599_1_T_621_mask;
+ wire T_599_1_T_621_en;
+ wire T_599_1_T_621_clk;
+ wire T_601;
+ wire T_602;
+ wire T_603;
+ wire T_604;
+ wire [63:0] T_605;
+ wire [63:0] T_606;
+ wire [63:0] T_608_0;
+ wire [63:0] T_608_1;
+ wire T_612;
+ wire T_613;
+ wire T_615_0;
+ wire T_615_1;
+ wire T_626;
+ wire T_627;
+ wire [7:0] T_629;
+ wire [127:0] T_636;
+ reg [63:0] T_649_0 [0:255];
+ wire [63:0] T_649_0_T_682_data;
+ wire [7:0] T_649_0_T_682_addr;
+ wire T_649_0_T_682_en;
+ wire T_649_0_T_682_clk;
+ reg [7:0] GEN_12;
+ reg GEN_13;
+ wire [63:0] T_649_0_T_671_data;
+ wire [7:0] T_649_0_T_671_addr;
+ wire T_649_0_T_671_mask;
+ wire T_649_0_T_671_en;
+ wire T_649_0_T_671_clk;
+ reg [63:0] T_649_1 [0:255];
+ wire [63:0] T_649_1_T_682_data;
+ wire [7:0] T_649_1_T_682_addr;
+ wire T_649_1_T_682_en;
+ wire T_649_1_T_682_clk;
+ reg [7:0] GEN_14;
+ reg GEN_15;
+ wire [63:0] T_649_1_T_671_data;
+ wire [7:0] T_649_1_T_671_addr;
+ wire T_649_1_T_671_mask;
+ wire T_649_1_T_671_en;
+ wire T_649_1_T_671_clk;
+ wire T_651;
+ wire T_652;
+ wire T_653;
+ wire T_654;
+ wire [63:0] T_655;
+ wire [63:0] T_656;
+ wire [63:0] T_658_0;
+ wire [63:0] T_658_1;
+ wire T_662;
+ wire T_663;
+ wire T_665_0;
+ wire T_665_1;
+ wire T_676;
+ wire T_677;
+ wire [7:0] T_679;
+ wire [127:0] T_686;
+ wire [63:0] T_687;
+ wire [63:0] T_688;
+ wire [63:0] T_690_0;
+ wire [63:0] T_690_1;
+ wire T_694;
+ wire [63:0] T_697_0;
+ wire [63:0] T_697_1;
+ wire [63:0] GEN_0;
+ wire [127:0] T_701;
+ wire [63:0] T_702;
+ wire [63:0] T_703;
+ wire [63:0] T_705_0;
+ wire [63:0] T_705_1;
+ wire T_709;
+ wire [63:0] T_712_0;
+ wire [63:0] T_712_1;
+ wire [63:0] GEN_1;
+ wire [127:0] T_716;
+ wire [1:0] T_717;
+ wire [1:0] T_718;
+ wire [127:0] T_727_0;
+ wire [127:0] T_727_1;
+ reg [11:0] T_731;
+ reg [63:0] T_744_0 [0:255];
+ wire [63:0] T_744_0_T_777_data;
+ wire [7:0] T_744_0_T_777_addr;
+ wire T_744_0_T_777_en;
+ wire T_744_0_T_777_clk;
+ reg [7:0] GEN_16;
+ reg GEN_17;
+ wire [63:0] T_744_0_T_766_data;
+ wire [7:0] T_744_0_T_766_addr;
+ wire T_744_0_T_766_mask;
+ wire T_744_0_T_766_en;
+ wire T_744_0_T_766_clk;
+ reg [63:0] T_744_1 [0:255];
+ wire [63:0] T_744_1_T_777_data;
+ wire [7:0] T_744_1_T_777_addr;
+ wire T_744_1_T_777_en;
+ wire T_744_1_T_777_clk;
+ reg [7:0] GEN_18;
+ reg GEN_19;
+ wire [63:0] T_744_1_T_766_data;
+ wire [7:0] T_744_1_T_766_addr;
+ wire T_744_1_T_766_mask;
+ wire T_744_1_T_766_en;
+ wire T_744_1_T_766_clk;
+ wire T_746;
+ wire T_747;
+ wire T_748;
+ wire T_749;
+ wire [63:0] T_750;
+ wire [63:0] T_751;
+ wire [63:0] T_753_0;
+ wire [63:0] T_753_1;
+ wire T_757;
+ wire T_758;
+ wire T_760_0;
+ wire T_760_1;
+ wire T_771;
+ wire T_772;
+ wire [7:0] T_774;
+ wire [127:0] T_781;
+ reg [63:0] T_794_0 [0:255];
+ wire [63:0] T_794_0_T_827_data;
+ wire [7:0] T_794_0_T_827_addr;
+ wire T_794_0_T_827_en;
+ wire T_794_0_T_827_clk;
+ reg [7:0] GEN_20;
+ reg GEN_21;
+ wire [63:0] T_794_0_T_816_data;
+ wire [7:0] T_794_0_T_816_addr;
+ wire T_794_0_T_816_mask;
+ wire T_794_0_T_816_en;
+ wire T_794_0_T_816_clk;
+ reg [63:0] T_794_1 [0:255];
+ wire [63:0] T_794_1_T_827_data;
+ wire [7:0] T_794_1_T_827_addr;
+ wire T_794_1_T_827_en;
+ wire T_794_1_T_827_clk;
+ reg [7:0] GEN_22;
+ reg GEN_23;
+ wire [63:0] T_794_1_T_816_data;
+ wire [7:0] T_794_1_T_816_addr;
+ wire T_794_1_T_816_mask;
+ wire T_794_1_T_816_en;
+ wire T_794_1_T_816_clk;
+ wire T_796;
+ wire T_797;
+ wire T_798;
+ wire T_799;
+ wire [63:0] T_800;
+ wire [63:0] T_801;
+ wire [63:0] T_803_0;
+ wire [63:0] T_803_1;
+ wire T_807;
+ wire T_808;
+ wire T_810_0;
+ wire T_810_1;
+ wire T_821;
+ wire T_822;
+ wire [7:0] T_824;
+ wire [127:0] T_831;
+ wire [63:0] T_832;
+ wire [63:0] T_833;
+ wire [63:0] T_835_0;
+ wire [63:0] T_835_1;
+ wire T_839;
+ wire [63:0] T_842_0;
+ wire [63:0] T_842_1;
+ wire [63:0] GEN_2;
+ wire [127:0] T_846;
+ wire [63:0] T_847;
+ wire [63:0] T_848;
+ wire [63:0] T_850_0;
+ wire [63:0] T_850_1;
+ wire T_854;
+ wire [63:0] T_857_0;
+ wire [63:0] T_857_1;
+ wire [63:0] GEN_3;
+ wire [127:0] T_861;
+ wire GEN_4;
+ wire GEN_5;
+ wire GEN_6;
+ wire GEN_7;
+ assign io_read_ready = 1'h1;
+ assign io_write_ready = 1'h1;
+ assign io_resp_0 = T_701;
+ assign io_resp_1 = T_716;
+ assign io_resp_2 = T_846;
+ assign io_resp_3 = T_861;
+ assign waddr = io_write_bits_addr[11:4];
+ assign raddr = io_read_bits_addr[11:4];
+ assign T_572 = io_write_bits_way_en[1:0];
+ assign T_573 = io_read_bits_way_en[1:0];
+ assign T_582_0 = T_636;
+ assign T_582_1 = T_686;
+ assign T_599_0_T_632_addr = T_629;
+ assign T_599_0_T_632_en = 1'h1;
+ assign T_599_0_T_632_clk = clk;
+ assign T_599_0_T_632_data = T_599_0[GEN_8];
+ assign T_599_0_T_621_data = T_608_0;
+ assign T_599_0_T_621_addr = waddr;
+ assign T_599_0_T_621_mask = T_604 ? T_615_0 ? 1'h1 : 1'h0 : 1'h0;
+ assign T_599_0_T_621_en = T_604 ? 1'h1 : 1'h0;
+ assign T_599_0_T_621_clk = clk;
+ assign T_599_1_T_632_addr = T_629;
+ assign T_599_1_T_632_en = 1'h1;
+ assign T_599_1_T_632_clk = clk;
+ assign T_599_1_T_632_data = T_599_1[GEN_10];
+ assign T_599_1_T_621_data = T_608_1;
+ assign T_599_1_T_621_addr = waddr;
+ assign T_599_1_T_621_mask = T_604 ? T_615_1 ? 1'h1 : 1'h0 : 1'h0;
+ assign T_599_1_T_621_en = T_604 ? 1'h1 : 1'h0;
+ assign T_599_1_T_621_clk = clk;
+ assign T_601 = T_572 != 1'h0;
+ assign T_602 = T_601 & io_write_valid;
+ assign T_603 = io_write_bits_wmask[0];
+ assign T_604 = T_602 & T_603;
+ assign T_605 = io_write_bits_data[63:0];
+ assign T_606 = io_write_bits_data[63:0];
+ assign T_608_0 = T_605;
+ assign T_608_1 = T_606;
+ assign T_612 = T_572[0];
+ assign T_613 = T_572[1];
+ assign T_615_0 = T_612;
+ assign T_615_1 = T_613;
+ assign T_626 = T_573 != 1'h0;
+ assign T_627 = T_626 & io_read_valid;
+ assign T_629 = raddr;
+ assign T_636 = {T_599_1_T_632_data,T_599_0_T_632_data};
+ assign T_649_0_T_682_addr = T_679;
+ assign T_649_0_T_682_en = 1'h1;
+ assign T_649_0_T_682_clk = clk;
+ assign T_649_0_T_682_data = T_649_0[GEN_12];
+ assign T_649_0_T_671_data = T_658_0;
+ assign T_649_0_T_671_addr = waddr;
+ assign T_649_0_T_671_mask = T_654 ? T_665_0 ? 1'h1 : 1'h0 : 1'h0;
+ assign T_649_0_T_671_en = T_654 ? 1'h1 : 1'h0;
+ assign T_649_0_T_671_clk = clk;
+ assign T_649_1_T_682_addr = T_679;
+ assign T_649_1_T_682_en = 1'h1;
+ assign T_649_1_T_682_clk = clk;
+ assign T_649_1_T_682_data = T_649_1[GEN_14];
+ assign T_649_1_T_671_data = T_658_1;
+ assign T_649_1_T_671_addr = waddr;
+ assign T_649_1_T_671_mask = T_654 ? T_665_1 ? 1'h1 : 1'h0 : 1'h0;
+ assign T_649_1_T_671_en = T_654 ? 1'h1 : 1'h0;
+ assign T_649_1_T_671_clk = clk;
+ assign T_651 = T_572 != 1'h0;
+ assign T_652 = T_651 & io_write_valid;
+ assign T_653 = io_write_bits_wmask[1];
+ assign T_654 = T_652 & T_653;
+ assign T_655 = io_write_bits_data[127:64];
+ assign T_656 = io_write_bits_data[127:64];
+ assign T_658_0 = T_655;
+ assign T_658_1 = T_656;
+ assign T_662 = T_572[0];
+ assign T_663 = T_572[1];
+ assign T_665_0 = T_662;
+ assign T_665_1 = T_663;
+ assign T_676 = T_573 != 1'h0;
+ assign T_677 = T_676 & io_read_valid;
+ assign T_679 = raddr;
+ assign T_686 = {T_649_1_T_682_data,T_649_0_T_682_data};
+ assign T_687 = T_582_0[63:0];
+ assign T_688 = T_582_1[63:0];
+ assign T_690_0 = T_687;
+ assign T_690_1 = T_688;
+ assign T_694 = T_586[3];
+ assign T_697_0 = GEN_0;
+ assign T_697_1 = T_690_1;
+ assign GEN_0 = GEN_4 ? T_690_1 : T_690_0;
+ assign T_701 = {T_697_1,T_697_0};
+ assign T_702 = T_582_0[127:64];
+ assign T_703 = T_582_1[127:64];
+ assign T_705_0 = T_702;
+ assign T_705_1 = T_703;
+ assign T_709 = T_586[3];
+ assign T_712_0 = GEN_1;
+ assign T_712_1 = T_705_1;
+ assign GEN_1 = GEN_5 ? T_705_1 : T_705_0;
+ assign T_716 = {T_712_1,T_712_0};
+ assign T_717 = io_write_bits_way_en[3:2];
+ assign T_718 = io_read_bits_way_en[3:2];
+ assign T_727_0 = T_781;
+ assign T_727_1 = T_831;
+ assign T_744_0_T_777_addr = T_774;
+ assign T_744_0_T_777_en = 1'h1;
+ assign T_744_0_T_777_clk = clk;
+ assign T_744_0_T_777_data = T_744_0[GEN_16];
+ assign T_744_0_T_766_data = T_753_0;
+ assign T_744_0_T_766_addr = waddr;
+ assign T_744_0_T_766_mask = T_749 ? T_760_0 ? 1'h1 : 1'h0 : 1'h0;
+ assign T_744_0_T_766_en = T_749 ? 1'h1 : 1'h0;
+ assign T_744_0_T_766_clk = clk;
+ assign T_744_1_T_777_addr = T_774;
+ assign T_744_1_T_777_en = 1'h1;
+ assign T_744_1_T_777_clk = clk;
+ assign T_744_1_T_777_data = T_744_1[GEN_18];
+ assign T_744_1_T_766_data = T_753_1;
+ assign T_744_1_T_766_addr = waddr;
+ assign T_744_1_T_766_mask = T_749 ? T_760_1 ? 1'h1 : 1'h0 : 1'h0;
+ assign T_744_1_T_766_en = T_749 ? 1'h1 : 1'h0;
+ assign T_744_1_T_766_clk = clk;
+ assign T_746 = T_717 != 1'h0;
+ assign T_747 = T_746 & io_write_valid;
+ assign T_748 = io_write_bits_wmask[0];
+ assign T_749 = T_747 & T_748;
+ assign T_750 = io_write_bits_data[63:0];
+ assign T_751 = io_write_bits_data[63:0];
+ assign T_753_0 = T_750;
+ assign T_753_1 = T_751;
+ assign T_757 = T_717[0];
+ assign T_758 = T_717[1];
+ assign T_760_0 = T_757;
+ assign T_760_1 = T_758;
+ assign T_771 = T_718 != 1'h0;
+ assign T_772 = T_771 & io_read_valid;
+ assign T_774 = raddr;
+ assign T_781 = {T_744_1_T_777_data,T_744_0_T_777_data};
+ assign T_794_0_T_827_addr = T_824;
+ assign T_794_0_T_827_en = 1'h1;
+ assign T_794_0_T_827_clk = clk;
+ assign T_794_0_T_827_data = T_794_0[GEN_20];
+ assign T_794_0_T_816_data = T_803_0;
+ assign T_794_0_T_816_addr = waddr;
+ assign T_794_0_T_816_mask = T_799 ? T_810_0 ? 1'h1 : 1'h0 : 1'h0;
+ assign T_794_0_T_816_en = T_799 ? 1'h1 : 1'h0;
+ assign T_794_0_T_816_clk = clk;
+ assign T_794_1_T_827_addr = T_824;
+ assign T_794_1_T_827_en = 1'h1;
+ assign T_794_1_T_827_clk = clk;
+ assign T_794_1_T_827_data = T_794_1[GEN_22];
+ assign T_794_1_T_816_data = T_803_1;
+ assign T_794_1_T_816_addr = waddr;
+ assign T_794_1_T_816_mask = T_799 ? T_810_1 ? 1'h1 : 1'h0 : 1'h0;
+ assign T_794_1_T_816_en = T_799 ? 1'h1 : 1'h0;
+ assign T_794_1_T_816_clk = clk;
+ assign T_796 = T_717 != 1'h0;
+ assign T_797 = T_796 & io_write_valid;
+ assign T_798 = io_write_bits_wmask[1];
+ assign T_799 = T_797 & T_798;
+ assign T_800 = io_write_bits_data[127:64];
+ assign T_801 = io_write_bits_data[127:64];
+ assign T_803_0 = T_800;
+ assign T_803_1 = T_801;
+ assign T_807 = T_717[0];
+ assign T_808 = T_717[1];
+ assign T_810_0 = T_807;
+ assign T_810_1 = T_808;
+ assign T_821 = T_718 != 1'h0;
+ assign T_822 = T_821 & io_read_valid;
+ assign T_824 = raddr;
+ assign T_831 = {T_794_1_T_827_data,T_794_0_T_827_data};
+ assign T_832 = T_727_0[63:0];
+ assign T_833 = T_727_1[63:0];
+ assign T_835_0 = T_832;
+ assign T_835_1 = T_833;
+ assign T_839 = T_731[3];
+ assign T_842_0 = GEN_2;
+ assign T_842_1 = T_835_1;
+ assign GEN_2 = GEN_6 ? T_835_1 : T_835_0;
+ assign T_846 = {T_842_1,T_842_0};
+ assign T_847 = T_727_0[127:64];
+ assign T_848 = T_727_1[127:64];
+ assign T_850_0 = T_847;
+ assign T_850_1 = T_848;
+ assign T_854 = T_731[3];
+ assign T_857_0 = GEN_3;
+ assign T_857_1 = T_850_1;
+ assign GEN_3 = GEN_7 ? T_850_1 : T_850_0;
+ assign T_861 = {T_857_1,T_857_0};
+ assign GEN_4 = 1'h1 == T_694;
+ assign GEN_5 = 1'h1 == T_709;
+ assign GEN_6 = 1'h1 == T_839;
+ assign GEN_7 = 1'h1 == T_854;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_586 = {1{$random}};
+ for (initvar = 0; initvar < 256; initvar = initvar+1)
+ T_599_0[initvar] = {2{$random}};
+ for (initvar = 0; initvar < 256; initvar = initvar+1)
+ T_599_1[initvar] = {2{$random}};
+ for (initvar = 0; initvar < 256; initvar = initvar+1)
+ T_649_0[initvar] = {2{$random}};
+ for (initvar = 0; initvar < 256; initvar = initvar+1)
+ T_649_1[initvar] = {2{$random}};
+ T_731 = {1{$random}};
+ for (initvar = 0; initvar < 256; initvar = initvar+1)
+ T_744_0[initvar] = {2{$random}};
+ for (initvar = 0; initvar < 256; initvar = initvar+1)
+ T_744_1[initvar] = {2{$random}};
+ for (initvar = 0; initvar < 256; initvar = initvar+1)
+ T_794_0[initvar] = {2{$random}};
+ for (initvar = 0; initvar < 256; initvar = initvar+1)
+ T_794_1[initvar] = {2{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_read_valid) begin
+ T_586 <= io_read_bits_addr;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_read_valid) begin
+ T_731 <= io_read_bits_addr;
+ end else begin
+ ;
+ end
+ end
+ end
+ always @(posedge T_599_0_T_632_clk) begin
+ GEN_8 <= T_599_0_T_632_addr;
+ GEN_9 <= T_599_0_T_632_en;
+ end
+ always @(posedge T_599_0_T_621_clk) begin
+ if(T_599_0_T_621_en & T_599_0_T_621_mask) begin
+ T_599_0[T_599_0_T_621_addr] <= T_599_0_T_621_data;
+ end
+ end
+ always @(posedge T_599_1_T_632_clk) begin
+ GEN_10 <= T_599_1_T_632_addr;
+ GEN_11 <= T_599_1_T_632_en;
+ end
+ always @(posedge T_599_1_T_621_clk) begin
+ if(T_599_1_T_621_en & T_599_1_T_621_mask) begin
+ T_599_1[T_599_1_T_621_addr] <= T_599_1_T_621_data;
+ end
+ end
+ always @(posedge T_649_0_T_682_clk) begin
+ GEN_12 <= T_649_0_T_682_addr;
+ GEN_13 <= T_649_0_T_682_en;
+ end
+ always @(posedge T_649_0_T_671_clk) begin
+ if(T_649_0_T_671_en & T_649_0_T_671_mask) begin
+ T_649_0[T_649_0_T_671_addr] <= T_649_0_T_671_data;
+ end
+ end
+ always @(posedge T_649_1_T_682_clk) begin
+ GEN_14 <= T_649_1_T_682_addr;
+ GEN_15 <= T_649_1_T_682_en;
+ end
+ always @(posedge T_649_1_T_671_clk) begin
+ if(T_649_1_T_671_en & T_649_1_T_671_mask) begin
+ T_649_1[T_649_1_T_671_addr] <= T_649_1_T_671_data;
+ end
+ end
+ always @(posedge T_744_0_T_777_clk) begin
+ GEN_16 <= T_744_0_T_777_addr;
+ GEN_17 <= T_744_0_T_777_en;
+ end
+ always @(posedge T_744_0_T_766_clk) begin
+ if(T_744_0_T_766_en & T_744_0_T_766_mask) begin
+ T_744_0[T_744_0_T_766_addr] <= T_744_0_T_766_data;
+ end
+ end
+ always @(posedge T_744_1_T_777_clk) begin
+ GEN_18 <= T_744_1_T_777_addr;
+ GEN_19 <= T_744_1_T_777_en;
+ end
+ always @(posedge T_744_1_T_766_clk) begin
+ if(T_744_1_T_766_en & T_744_1_T_766_mask) begin
+ T_744_1[T_744_1_T_766_addr] <= T_744_1_T_766_data;
+ end
+ end
+ always @(posedge T_794_0_T_827_clk) begin
+ GEN_20 <= T_794_0_T_827_addr;
+ GEN_21 <= T_794_0_T_827_en;
+ end
+ always @(posedge T_794_0_T_816_clk) begin
+ if(T_794_0_T_816_en & T_794_0_T_816_mask) begin
+ T_794_0[T_794_0_T_816_addr] <= T_794_0_T_816_data;
+ end
+ end
+ always @(posedge T_794_1_T_827_clk) begin
+ GEN_22 <= T_794_1_T_827_addr;
+ GEN_23 <= T_794_1_T_827_en;
+ end
+ always @(posedge T_794_1_T_816_clk) begin
+ if(T_794_1_T_816_en & T_794_1_T_816_mask) begin
+ T_794_1[T_794_1_T_816_addr] <= T_794_1_T_816_data;
+ end
+ end
+endmodule
+module Arbiter_107(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input [3:0] io_in_0_bits_way_en,
+ input [11:0] io_in_0_bits_addr,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input [3:0] io_in_1_bits_way_en,
+ input [11:0] io_in_1_bits_addr,
+ output io_in_2_ready,
+ input io_in_2_valid,
+ input [3:0] io_in_2_bits_way_en,
+ input [11:0] io_in_2_bits_addr,
+ output io_in_3_ready,
+ input io_in_3_valid,
+ input [3:0] io_in_3_bits_way_en,
+ input [11:0] io_in_3_bits_addr,
+ input io_out_ready,
+ output io_out_valid,
+ output [3:0] io_out_bits_way_en,
+ output [11:0] io_out_bits_addr,
+ output [1:0] io_chosen
+);
+ wire [1:0] T_1524;
+ wire GEN_0;
+ wire [3:0] GEN_1;
+ wire [11:0] GEN_2;
+ wire GEN_3;
+ wire T_1831;
+ wire T_1833;
+ wire T_1835;
+ wire T_1836;
+ wire T_1838;
+ wire T_1840;
+ wire T_1841;
+ wire T_1842;
+ wire T_1844;
+ wire T_1846;
+ wire T_1847;
+ wire T_1848;
+ wire T_1850;
+ wire T_1851;
+ wire T_1852;
+ wire T_1854;
+ wire T_1855;
+ wire T_1856;
+ wire T_1858;
+ wire T_1859;
+ wire T_1860;
+ wire [1:0] T_1863;
+ wire [1:0] T_1865;
+ wire [1:0] T_1867;
+ wire [1:0] T_1868;
+ wire GEN_4;
+ wire GEN_5;
+ wire GEN_6;
+ wire GEN_7;
+ wire GEN_8;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ assign io_in_0_ready = T_1848;
+ assign io_in_1_ready = T_1852;
+ assign io_in_2_ready = T_1856;
+ assign io_in_3_ready = T_1860;
+ assign io_out_valid = GEN_0;
+ assign io_out_bits_way_en = GEN_1;
+ assign io_out_bits_addr = GEN_2;
+ assign io_chosen = T_1524;
+ assign T_1524 = T_1868;
+ assign GEN_0 = GEN_4 ? io_in_3_valid : GEN_5 ? io_in_2_valid : GEN_6 ? io_in_1_valid : io_in_0_valid;
+ assign GEN_1 = GEN_7 ? io_in_3_bits_way_en : GEN_8 ? io_in_2_bits_way_en : GEN_9 ? io_in_1_bits_way_en : io_in_0_bits_way_en;
+ assign GEN_2 = GEN_10 ? io_in_3_bits_addr : GEN_11 ? io_in_2_bits_addr : GEN_12 ? io_in_1_bits_addr : io_in_0_bits_addr;
+ assign GEN_3 = 1'h0;
+ assign T_1831 = 1'h0 | io_in_0_valid;
+ assign T_1833 = T_1831 == 1'h0;
+ assign T_1835 = 1'h0 | io_in_0_valid;
+ assign T_1836 = T_1835 | io_in_1_valid;
+ assign T_1838 = T_1836 == 1'h0;
+ assign T_1840 = 1'h0 | io_in_0_valid;
+ assign T_1841 = T_1840 | io_in_1_valid;
+ assign T_1842 = T_1841 | io_in_2_valid;
+ assign T_1844 = T_1842 == 1'h0;
+ assign T_1846 = 2'h3 == 1'h0;
+ assign T_1847 = 1'h0 ? T_1846 : 1'h1;
+ assign T_1848 = T_1847 & io_out_ready;
+ assign T_1850 = 2'h3 == 1'h1;
+ assign T_1851 = 1'h0 ? T_1850 : T_1833;
+ assign T_1852 = T_1851 & io_out_ready;
+ assign T_1854 = 2'h3 == 2'h2;
+ assign T_1855 = 1'h0 ? T_1854 : T_1838;
+ assign T_1856 = T_1855 & io_out_ready;
+ assign T_1858 = 2'h3 == 2'h3;
+ assign T_1859 = 1'h0 ? T_1858 : T_1844;
+ assign T_1860 = T_1859 & io_out_ready;
+ assign T_1863 = io_in_2_valid ? 2'h2 : 2'h3;
+ assign T_1865 = io_in_1_valid ? 1'h1 : T_1863;
+ assign T_1867 = io_in_0_valid ? 1'h0 : T_1865;
+ assign T_1868 = 1'h0 ? 2'h3 : T_1867;
+ assign GEN_4 = 2'h3 == T_1524;
+ assign GEN_5 = 2'h2 == T_1524;
+ assign GEN_6 = 1'h1 == T_1524;
+ assign GEN_7 = 2'h3 == T_1524;
+ assign GEN_8 = 2'h2 == T_1524;
+ assign GEN_9 = 1'h1 == T_1524;
+ assign GEN_10 = 2'h3 == T_1524;
+ assign GEN_11 = 2'h2 == T_1524;
+ assign GEN_12 = 1'h1 == T_1524;
+endmodule
+module Arbiter_108(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input [3:0] io_in_0_bits_way_en,
+ input [11:0] io_in_0_bits_addr,
+ input [1:0] io_in_0_bits_wmask,
+ input [127:0] io_in_0_bits_data,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input [3:0] io_in_1_bits_way_en,
+ input [11:0] io_in_1_bits_addr,
+ input [1:0] io_in_1_bits_wmask,
+ input [127:0] io_in_1_bits_data,
+ input io_out_ready,
+ output io_out_valid,
+ output [3:0] io_out_bits_way_en,
+ output [11:0] io_out_bits_addr,
+ output [1:0] io_out_bits_wmask,
+ output [127:0] io_out_bits_data,
+ output io_chosen
+);
+ wire T_1164;
+ wire GEN_0;
+ wire [3:0] GEN_1;
+ wire [11:0] GEN_2;
+ wire [1:0] GEN_3;
+ wire [127:0] GEN_4;
+ wire GEN_5;
+ wire T_1483;
+ wire T_1485;
+ wire T_1487;
+ wire T_1488;
+ wire T_1489;
+ wire T_1491;
+ wire T_1492;
+ wire T_1493;
+ wire T_1496;
+ wire T_1497;
+ wire GEN_6;
+ wire GEN_7;
+ wire GEN_8;
+ wire GEN_9;
+ wire GEN_10;
+ assign io_in_0_ready = T_1489;
+ assign io_in_1_ready = T_1493;
+ assign io_out_valid = GEN_0;
+ assign io_out_bits_way_en = GEN_1;
+ assign io_out_bits_addr = GEN_2;
+ assign io_out_bits_wmask = GEN_3;
+ assign io_out_bits_data = GEN_4;
+ assign io_chosen = T_1164;
+ assign T_1164 = T_1497;
+ assign GEN_0 = GEN_6 ? io_in_1_valid : io_in_0_valid;
+ assign GEN_1 = GEN_7 ? io_in_1_bits_way_en : io_in_0_bits_way_en;
+ assign GEN_2 = GEN_8 ? io_in_1_bits_addr : io_in_0_bits_addr;
+ assign GEN_3 = GEN_9 ? io_in_1_bits_wmask : io_in_0_bits_wmask;
+ assign GEN_4 = GEN_10 ? io_in_1_bits_data : io_in_0_bits_data;
+ assign GEN_5 = 1'h0;
+ assign T_1483 = 1'h0 | io_in_0_valid;
+ assign T_1485 = T_1483 == 1'h0;
+ assign T_1487 = 1'h1 == 1'h0;
+ assign T_1488 = 1'h0 ? T_1487 : 1'h1;
+ assign T_1489 = T_1488 & io_out_ready;
+ assign T_1491 = 1'h1 == 1'h1;
+ assign T_1492 = 1'h0 ? T_1491 : T_1485;
+ assign T_1493 = T_1492 & io_out_ready;
+ assign T_1496 = io_in_0_valid ? 1'h0 : 1'h1;
+ assign T_1497 = 1'h0 ? 1'h1 : T_1496;
+ assign GEN_6 = 1'h1 == T_1164;
+ assign GEN_7 = 1'h1 == T_1164;
+ assign GEN_8 = 1'h1 == T_1164;
+ assign GEN_9 = 1'h1 == T_1164;
+ assign GEN_10 = 1'h1 == T_1164;
+endmodule
+module AMOALU(
+ input clk,
+ input reset,
+ input [5:0] io_addr,
+ input [4:0] io_cmd,
+ input [2:0] io_typ,
+ input [63:0] io_lhs,
+ input [63:0] io_rhs,
+ output [63:0] io_out
+);
+ wire [1:0] T_10;
+ wire T_12;
+ wire [31:0] T_13;
+ wire [63:0] T_14;
+ wire [63:0] rhs;
+ wire T_16;
+ wire T_17;
+ wire sgned;
+ wire T_19;
+ wire T_20;
+ wire max;
+ wire T_22;
+ wire T_23;
+ wire min;
+ wire T_25;
+ wire T_26;
+ wire T_27;
+ wire T_28;
+ wire T_29;
+ wire T_30;
+ wire word;
+ wire [63:0] T_33;
+ wire T_34;
+ wire [31:0] T_35;
+ wire [63:0] mask;
+ wire [63:0] T_37;
+ wire [63:0] T_38;
+ wire [64:0] T_39;
+ wire [63:0] adder_out;
+ wire T_41;
+ wire T_43;
+ wire T_44;
+ wire T_45;
+ wire T_46;
+ wire cmp_lhs;
+ wire T_48;
+ wire T_50;
+ wire T_51;
+ wire T_52;
+ wire T_53;
+ wire cmp_rhs;
+ wire [31:0] T_55;
+ wire [31:0] T_56;
+ wire lt_lo;
+ wire [31:0] T_58;
+ wire [31:0] T_59;
+ wire lt_hi;
+ wire [31:0] T_61;
+ wire [31:0] T_62;
+ wire eq_hi;
+ wire T_64;
+ wire T_65;
+ wire T_66;
+ wire T_67;
+ wire lt;
+ wire T_69;
+ wire T_70;
+ wire less;
+ wire T_72;
+ wire T_73;
+ wire [63:0] T_74;
+ wire T_75;
+ wire [63:0] T_76;
+ wire T_77;
+ wire [63:0] T_78;
+ wire T_79;
+ wire T_81;
+ wire [7:0] T_82;
+ wire [15:0] T_83;
+ wire [31:0] T_84;
+ wire [63:0] T_85;
+ wire T_87;
+ wire [15:0] T_88;
+ wire [31:0] T_89;
+ wire [63:0] T_90;
+ wire T_92;
+ wire [31:0] T_93;
+ wire [63:0] T_94;
+ wire [63:0] T_95;
+ wire [63:0] T_96;
+ wire [63:0] T_97;
+ wire [63:0] T_98;
+ wire [63:0] T_99;
+ wire [63:0] T_100;
+ wire [63:0] T_101;
+ wire [63:0] out;
+ wire T_104;
+ wire T_106;
+ wire T_108;
+ wire T_111;
+ wire T_112;
+ wire T_113;
+ wire T_115;
+ wire [1:0] T_116;
+ wire T_117;
+ wire [1:0] T_119;
+ wire T_121;
+ wire [1:0] T_124;
+ wire [1:0] T_125;
+ wire T_126;
+ wire [1:0] T_128;
+ wire [3:0] T_129;
+ wire T_130;
+ wire [3:0] T_132;
+ wire T_134;
+ wire [3:0] T_137;
+ wire [3:0] T_138;
+ wire T_139;
+ wire [3:0] T_141;
+ wire [7:0] T_142;
+ wire T_143;
+ wire T_144;
+ wire T_145;
+ wire T_146;
+ wire T_147;
+ wire T_148;
+ wire T_149;
+ wire T_150;
+ wire T_152_0;
+ wire T_152_1;
+ wire T_152_2;
+ wire T_152_3;
+ wire T_152_4;
+ wire T_152_5;
+ wire T_152_6;
+ wire T_152_7;
+ wire [8:0] T_163;
+ wire [7:0] T_164;
+ wire [8:0] T_166;
+ wire [7:0] T_167;
+ wire [8:0] T_169;
+ wire [7:0] T_170;
+ wire [8:0] T_172;
+ wire [7:0] T_173;
+ wire [8:0] T_175;
+ wire [7:0] T_176;
+ wire [8:0] T_178;
+ wire [7:0] T_179;
+ wire [8:0] T_181;
+ wire [7:0] T_182;
+ wire [8:0] T_184;
+ wire [7:0] T_185;
+ wire [7:0] T_187_0;
+ wire [7:0] T_187_1;
+ wire [7:0] T_187_2;
+ wire [7:0] T_187_3;
+ wire [7:0] T_187_4;
+ wire [7:0] T_187_5;
+ wire [7:0] T_187_6;
+ wire [7:0] T_187_7;
+ wire [15:0] T_197;
+ wire [15:0] T_198;
+ wire [31:0] T_199;
+ wire [15:0] T_200;
+ wire [15:0] T_201;
+ wire [31:0] T_202;
+ wire [63:0] wmask;
+ wire [63:0] T_204;
+ wire [63:0] T_205;
+ wire [63:0] T_206;
+ wire [63:0] T_207;
+ assign io_out = T_207;
+ assign T_10 = io_typ[1:0];
+ assign T_12 = T_10 == 2'h2;
+ assign T_13 = io_rhs[31:0];
+ assign T_14 = {T_13,T_13};
+ assign rhs = T_12 ? T_14 : io_rhs;
+ assign T_16 = io_cmd == 5'hc;
+ assign T_17 = io_cmd == 5'hd;
+ assign sgned = T_16 | T_17;
+ assign T_19 = io_cmd == 5'hd;
+ assign T_20 = io_cmd == 5'hf;
+ assign max = T_19 | T_20;
+ assign T_22 = io_cmd == 5'hc;
+ assign T_23 = io_cmd == 5'he;
+ assign min = T_22 | T_23;
+ assign T_25 = io_typ == 3'h2;
+ assign T_26 = io_typ == 3'h6;
+ assign T_27 = T_25 | T_26;
+ assign T_28 = io_typ == 3'h0;
+ assign T_29 = T_27 | T_28;
+ assign T_30 = io_typ == 3'h4;
+ assign word = T_29 | T_30;
+ assign T_33 = ~ 64'h0;
+ assign T_34 = io_addr[2];
+ assign T_35 = T_34 << 31;
+ assign mask = T_33 ^ T_35;
+ assign T_37 = io_lhs & mask;
+ assign T_38 = rhs & mask;
+ assign T_39 = T_37 + T_38;
+ assign adder_out = T_39[63:0];
+ assign T_41 = io_addr[2];
+ assign T_43 = T_41 == 1'h0;
+ assign T_44 = word & T_43;
+ assign T_45 = io_lhs[31];
+ assign T_46 = io_lhs[63];
+ assign cmp_lhs = T_44 ? T_45 : T_46;
+ assign T_48 = io_addr[2];
+ assign T_50 = T_48 == 1'h0;
+ assign T_51 = word & T_50;
+ assign T_52 = rhs[31];
+ assign T_53 = rhs[63];
+ assign cmp_rhs = T_51 ? T_52 : T_53;
+ assign T_55 = io_lhs[31:0];
+ assign T_56 = rhs[31:0];
+ assign lt_lo = T_55 < T_56;
+ assign T_58 = io_lhs[63:32];
+ assign T_59 = rhs[63:32];
+ assign lt_hi = T_58 < T_59;
+ assign T_61 = io_lhs[63:32];
+ assign T_62 = rhs[63:32];
+ assign eq_hi = T_61 == T_62;
+ assign T_64 = io_addr[2];
+ assign T_65 = T_64 ? lt_hi : lt_lo;
+ assign T_66 = eq_hi & lt_lo;
+ assign T_67 = lt_hi | T_66;
+ assign lt = word ? T_65 : T_67;
+ assign T_69 = cmp_lhs == cmp_rhs;
+ assign T_70 = sgned ? cmp_lhs : cmp_rhs;
+ assign less = T_69 ? lt : T_70;
+ assign T_72 = io_cmd == 5'h8;
+ assign T_73 = io_cmd == 5'hb;
+ assign T_74 = io_lhs & rhs;
+ assign T_75 = io_cmd == 5'ha;
+ assign T_76 = io_lhs | rhs;
+ assign T_77 = io_cmd == 5'h9;
+ assign T_78 = io_lhs ^ rhs;
+ assign T_79 = less ? min : max;
+ assign T_81 = T_10 == 1'h0;
+ assign T_82 = io_rhs[7:0];
+ assign T_83 = {T_82,T_82};
+ assign T_84 = {T_83,T_83};
+ assign T_85 = {T_84,T_84};
+ assign T_87 = T_10 == 1'h1;
+ assign T_88 = io_rhs[15:0];
+ assign T_89 = {T_88,T_88};
+ assign T_90 = {T_89,T_89};
+ assign T_92 = T_10 == 2'h2;
+ assign T_93 = io_rhs[31:0];
+ assign T_94 = {T_93,T_93};
+ assign T_95 = T_92 ? T_94 : io_rhs;
+ assign T_96 = T_87 ? T_90 : T_95;
+ assign T_97 = T_81 ? T_85 : T_96;
+ assign T_98 = T_79 ? io_lhs : T_97;
+ assign T_99 = T_77 ? T_78 : T_98;
+ assign T_100 = T_75 ? T_76 : T_99;
+ assign T_101 = T_73 ? T_74 : T_100;
+ assign out = T_72 ? adder_out : T_101;
+ assign T_104 = io_addr[0];
+ assign T_106 = T_104 ? 1'h1 : 1'h0;
+ assign T_108 = T_10 >= 1'h1;
+ assign T_111 = T_108 ? 1'h1 : 1'h0;
+ assign T_112 = T_106 | T_111;
+ assign T_113 = io_addr[0];
+ assign T_115 = T_113 ? 1'h0 : 1'h1;
+ assign T_116 = {T_112,T_115};
+ assign T_117 = io_addr[1];
+ assign T_119 = T_117 ? T_116 : 1'h0;
+ assign T_121 = T_10 >= 2'h2;
+ assign T_124 = T_121 ? 2'h3 : 1'h0;
+ assign T_125 = T_119 | T_124;
+ assign T_126 = io_addr[1];
+ assign T_128 = T_126 ? 1'h0 : T_116;
+ assign T_129 = {T_125,T_128};
+ assign T_130 = io_addr[2];
+ assign T_132 = T_130 ? T_129 : 1'h0;
+ assign T_134 = T_10 >= 2'h3;
+ assign T_137 = T_134 ? 4'hf : 1'h0;
+ assign T_138 = T_132 | T_137;
+ assign T_139 = io_addr[2];
+ assign T_141 = T_139 ? 1'h0 : T_129;
+ assign T_142 = {T_138,T_141};
+ assign T_143 = T_142[0];
+ assign T_144 = T_142[1];
+ assign T_145 = T_142[2];
+ assign T_146 = T_142[3];
+ assign T_147 = T_142[4];
+ assign T_148 = T_142[5];
+ assign T_149 = T_142[6];
+ assign T_150 = T_142[7];
+ assign T_152_0 = T_143;
+ assign T_152_1 = T_144;
+ assign T_152_2 = T_145;
+ assign T_152_3 = T_146;
+ assign T_152_4 = T_147;
+ assign T_152_5 = T_148;
+ assign T_152_6 = T_149;
+ assign T_152_7 = T_150;
+ assign T_163 = 8'h0 - T_152_0;
+ assign T_164 = T_163[7:0];
+ assign T_166 = 8'h0 - T_152_1;
+ assign T_167 = T_166[7:0];
+ assign T_169 = 8'h0 - T_152_2;
+ assign T_170 = T_169[7:0];
+ assign T_172 = 8'h0 - T_152_3;
+ assign T_173 = T_172[7:0];
+ assign T_175 = 8'h0 - T_152_4;
+ assign T_176 = T_175[7:0];
+ assign T_178 = 8'h0 - T_152_5;
+ assign T_179 = T_178[7:0];
+ assign T_181 = 8'h0 - T_152_6;
+ assign T_182 = T_181[7:0];
+ assign T_184 = 8'h0 - T_152_7;
+ assign T_185 = T_184[7:0];
+ assign T_187_0 = T_164;
+ assign T_187_1 = T_167;
+ assign T_187_2 = T_170;
+ assign T_187_3 = T_173;
+ assign T_187_4 = T_176;
+ assign T_187_5 = T_179;
+ assign T_187_6 = T_182;
+ assign T_187_7 = T_185;
+ assign T_197 = {T_187_7,T_187_6};
+ assign T_198 = {T_187_5,T_187_4};
+ assign T_199 = {T_197,T_198};
+ assign T_200 = {T_187_3,T_187_2};
+ assign T_201 = {T_187_1,T_187_0};
+ assign T_202 = {T_200,T_201};
+ assign wmask = {T_199,T_202};
+ assign T_204 = wmask & out;
+ assign T_205 = ~ wmask;
+ assign T_206 = T_205 & io_lhs;
+ assign T_207 = T_204 | T_206;
+endmodule
+module LockingArbiter_109(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input [1:0] io_in_0_bits_addr_beat,
+ input [25:0] io_in_0_bits_addr_block,
+ input [1:0] io_in_0_bits_client_xact_id,
+ input io_in_0_bits_voluntary,
+ input [2:0] io_in_0_bits_r_type,
+ input [127:0] io_in_0_bits_data,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input [1:0] io_in_1_bits_addr_beat,
+ input [25:0] io_in_1_bits_addr_block,
+ input [1:0] io_in_1_bits_client_xact_id,
+ input io_in_1_bits_voluntary,
+ input [2:0] io_in_1_bits_r_type,
+ input [127:0] io_in_1_bits_data,
+ input io_out_ready,
+ output io_out_valid,
+ output [1:0] io_out_bits_addr_beat,
+ output [25:0] io_out_bits_addr_block,
+ output [1:0] io_out_bits_client_xact_id,
+ output io_out_bits_voluntary,
+ output [2:0] io_out_bits_r_type,
+ output [127:0] io_out_bits_data,
+ output io_chosen
+);
+ reg T_700;
+ reg T_702;
+ wire T_704;
+ wire GEN_0;
+ wire [1:0] GEN_1;
+ wire [25:0] GEN_2;
+ wire [1:0] GEN_3;
+ wire GEN_4;
+ wire [2:0] GEN_5;
+ wire [127:0] GEN_6;
+ wire GEN_7;
+ wire T_897;
+ wire T_899;
+ wire T_901;
+ wire T_902;
+ wire T_903;
+ wire T_905;
+ wire T_906;
+ wire T_907;
+ reg [1:0] T_909;
+ wire [2:0] T_911;
+ wire [1:0] T_912;
+ wire T_913;
+ wire [1:0] T_916_0;
+ wire [1:0] T_916_1;
+ wire [1:0] T_916_2;
+ wire T_921;
+ wire T_922;
+ wire T_923;
+ wire T_925;
+ wire T_926;
+ wire T_927;
+ wire T_928;
+ wire T_930;
+ wire T_932;
+ wire T_933;
+ wire T_935_0;
+ wire T_935_1;
+ wire T_941;
+ wire T_943;
+ wire choose;
+ wire T_948;
+ wire GEN_8;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ wire GEN_13;
+ wire GEN_14;
+ assign io_in_0_ready = T_903;
+ assign io_in_1_ready = T_907;
+ assign io_out_valid = GEN_0;
+ assign io_out_bits_addr_beat = GEN_1;
+ assign io_out_bits_addr_block = GEN_2;
+ assign io_out_bits_client_xact_id = GEN_3;
+ assign io_out_bits_voluntary = GEN_4;
+ assign io_out_bits_r_type = GEN_5;
+ assign io_out_bits_data = GEN_6;
+ assign io_chosen = T_704;
+ assign T_704 = T_948;
+ assign GEN_0 = GEN_8 ? io_in_1_valid : io_in_0_valid;
+ assign GEN_1 = GEN_9 ? io_in_1_bits_addr_beat : io_in_0_bits_addr_beat;
+ assign GEN_2 = GEN_10 ? io_in_1_bits_addr_block : io_in_0_bits_addr_block;
+ assign GEN_3 = GEN_11 ? io_in_1_bits_client_xact_id : io_in_0_bits_client_xact_id;
+ assign GEN_4 = GEN_12 ? io_in_1_bits_voluntary : io_in_0_bits_voluntary;
+ assign GEN_5 = GEN_13 ? io_in_1_bits_r_type : io_in_0_bits_r_type;
+ assign GEN_6 = GEN_14 ? io_in_1_bits_data : io_in_0_bits_data;
+ assign GEN_7 = 1'h0;
+ assign T_897 = 1'h0 | io_in_0_valid;
+ assign T_899 = T_897 == 1'h0;
+ assign T_901 = T_702 == 1'h0;
+ assign T_902 = T_700 ? T_901 : 1'h1;
+ assign T_903 = T_902 & io_out_ready;
+ assign T_905 = T_702 == 1'h1;
+ assign T_906 = T_700 ? T_905 : T_899;
+ assign T_907 = T_906 & io_out_ready;
+ assign T_911 = T_909 + 1'h1;
+ assign T_912 = T_911[1:0];
+ assign T_913 = io_out_ready & io_out_valid;
+ assign T_916_0 = 1'h0;
+ assign T_916_1 = 1'h1;
+ assign T_916_2 = 2'h2;
+ assign T_921 = T_916_0 == io_out_bits_r_type;
+ assign T_922 = T_916_1 == io_out_bits_r_type;
+ assign T_923 = T_916_2 == io_out_bits_r_type;
+ assign T_925 = 1'h0 | T_921;
+ assign T_926 = T_925 | T_922;
+ assign T_927 = T_926 | T_923;
+ assign T_928 = 1'h1 & T_927;
+ assign T_930 = T_700 == 1'h0;
+ assign T_932 = io_in_0_ready & io_in_0_valid;
+ assign T_933 = io_in_1_ready & io_in_1_valid;
+ assign T_935_0 = T_932;
+ assign T_935_1 = T_933;
+ assign T_941 = T_935_0 ? 1'h0 : 1'h1;
+ assign T_943 = T_912 == 1'h0;
+ assign choose = io_in_0_valid ? 1'h0 : 1'h1;
+ assign T_948 = T_700 ? T_702 : choose;
+ assign GEN_8 = 1'h1 == T_704;
+ assign GEN_9 = 1'h1 == T_704;
+ assign GEN_10 = 1'h1 == T_704;
+ assign GEN_11 = 1'h1 == T_704;
+ assign GEN_12 = 1'h1 == T_704;
+ assign GEN_13 = 1'h1 == T_704;
+ assign GEN_14 = 1'h1 == T_704;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_700 = {1{$random}};
+ T_702 = {1{$random}};
+ T_909 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ T_700 <= 1'h0;
+ end else begin
+ if(T_913) begin
+ if(T_943) begin
+ T_700 <= 1'h0;
+ end else begin
+ if(T_928) begin
+ if(T_930) begin
+ T_700 <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_702 <= 1'h1;
+ end else begin
+ if(T_913) begin
+ if(T_928) begin
+ if(T_930) begin
+ T_702 <= T_941;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_909 <= 2'h0;
+ end else begin
+ if(T_913) begin
+ if(T_928) begin
+ T_909 <= T_912;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module HellaCache(
+ input clk,
+ input reset,
+ output io_cpu_req_ready,
+ input io_cpu_req_valid,
+ input [39:0] io_cpu_req_bits_addr,
+ input [8:0] io_cpu_req_bits_tag,
+ input [4:0] io_cpu_req_bits_cmd,
+ input [2:0] io_cpu_req_bits_typ,
+ input io_cpu_req_bits_kill,
+ input io_cpu_req_bits_phys,
+ input [63:0] io_cpu_req_bits_data,
+ output io_cpu_resp_valid,
+ output [39:0] io_cpu_resp_bits_addr,
+ output [8:0] io_cpu_resp_bits_tag,
+ output [4:0] io_cpu_resp_bits_cmd,
+ output [2:0] io_cpu_resp_bits_typ,
+ output [63:0] io_cpu_resp_bits_data,
+ output io_cpu_resp_bits_nack,
+ output io_cpu_resp_bits_replay,
+ output io_cpu_resp_bits_has_data,
+ output [63:0] io_cpu_resp_bits_data_word_bypass,
+ output [63:0] io_cpu_resp_bits_store_data,
+ output io_cpu_replay_next_valid,
+ output [8:0] io_cpu_replay_next_bits,
+ output io_cpu_xcpt_ma_ld,
+ output io_cpu_xcpt_ma_st,
+ output io_cpu_xcpt_pf_ld,
+ output io_cpu_xcpt_pf_st,
+ input io_cpu_invalidate_lr,
+ output io_cpu_ordered,
+ input io_ptw_req_ready,
+ output io_ptw_req_valid,
+ output [26:0] io_ptw_req_bits_addr,
+ output [1:0] io_ptw_req_bits_prv,
+ output io_ptw_req_bits_store,
+ output io_ptw_req_bits_fetch,
+ input io_ptw_resp_valid,
+ input io_ptw_resp_bits_error,
+ input [19:0] io_ptw_resp_bits_pte_ppn,
+ input [2:0] io_ptw_resp_bits_pte_reserved_for_software,
+ input io_ptw_resp_bits_pte_d,
+ input io_ptw_resp_bits_pte_r,
+ input [3:0] io_ptw_resp_bits_pte_typ,
+ input io_ptw_resp_bits_pte_v,
+ input io_ptw_status_sd,
+ input [30:0] io_ptw_status_zero2,
+ input io_ptw_status_sd_rv32,
+ input [8:0] io_ptw_status_zero1,
+ input [4:0] io_ptw_status_vm,
+ input io_ptw_status_mprv,
+ input [1:0] io_ptw_status_xs,
+ input [1:0] io_ptw_status_fs,
+ input [1:0] io_ptw_status_prv3,
+ input io_ptw_status_ie3,
+ input [1:0] io_ptw_status_prv2,
+ input io_ptw_status_ie2,
+ input [1:0] io_ptw_status_prv1,
+ input io_ptw_status_ie1,
+ input [1:0] io_ptw_status_prv,
+ input io_ptw_status_ie,
+ input io_ptw_invalidate,
+ input io_mem_acquire_ready,
+ output io_mem_acquire_valid,
+ output [25:0] io_mem_acquire_bits_addr_block,
+ output [1:0] io_mem_acquire_bits_client_xact_id,
+ output [1:0] io_mem_acquire_bits_addr_beat,
+ output io_mem_acquire_bits_is_builtin_type,
+ output [2:0] io_mem_acquire_bits_a_type,
+ output [16:0] io_mem_acquire_bits_union,
+ output [127:0] io_mem_acquire_bits_data,
+ output io_mem_grant_ready,
+ input io_mem_grant_valid,
+ input [1:0] io_mem_grant_bits_addr_beat,
+ input [1:0] io_mem_grant_bits_client_xact_id,
+ input [3:0] io_mem_grant_bits_manager_xact_id,
+ input io_mem_grant_bits_is_builtin_type,
+ input [3:0] io_mem_grant_bits_g_type,
+ input [127:0] io_mem_grant_bits_data,
+ output io_mem_probe_ready,
+ input io_mem_probe_valid,
+ input [25:0] io_mem_probe_bits_addr_block,
+ input [1:0] io_mem_probe_bits_p_type,
+ input io_mem_release_ready,
+ output io_mem_release_valid,
+ output [1:0] io_mem_release_bits_addr_beat,
+ output [25:0] io_mem_release_bits_addr_block,
+ output [1:0] io_mem_release_bits_client_xact_id,
+ output io_mem_release_bits_voluntary,
+ output [2:0] io_mem_release_bits_r_type,
+ output [127:0] io_mem_release_bits_data
+);
+ wire wb_clk;
+ wire wb_reset;
+ wire wb_io_req_ready;
+ wire wb_io_req_valid;
+ wire [1:0] wb_io_req_bits_addr_beat;
+ wire [25:0] wb_io_req_bits_addr_block;
+ wire [1:0] wb_io_req_bits_client_xact_id;
+ wire wb_io_req_bits_voluntary;
+ wire [2:0] wb_io_req_bits_r_type;
+ wire [127:0] wb_io_req_bits_data;
+ wire [3:0] wb_io_req_bits_way_en;
+ wire wb_io_meta_read_ready;
+ wire wb_io_meta_read_valid;
+ wire [5:0] wb_io_meta_read_bits_idx;
+ wire [19:0] wb_io_meta_read_bits_tag;
+ wire wb_io_data_req_ready;
+ wire wb_io_data_req_valid;
+ wire [3:0] wb_io_data_req_bits_way_en;
+ wire [11:0] wb_io_data_req_bits_addr;
+ wire [127:0] wb_io_data_resp;
+ wire wb_io_release_ready;
+ wire wb_io_release_valid;
+ wire [1:0] wb_io_release_bits_addr_beat;
+ wire [25:0] wb_io_release_bits_addr_block;
+ wire [1:0] wb_io_release_bits_client_xact_id;
+ wire wb_io_release_bits_voluntary;
+ wire [2:0] wb_io_release_bits_r_type;
+ wire [127:0] wb_io_release_bits_data;
+ wire prober_clk;
+ wire prober_reset;
+ wire prober_io_req_ready;
+ wire prober_io_req_valid;
+ wire [25:0] prober_io_req_bits_addr_block;
+ wire [1:0] prober_io_req_bits_p_type;
+ wire [1:0] prober_io_req_bits_client_xact_id;
+ wire prober_io_rep_ready;
+ wire prober_io_rep_valid;
+ wire [1:0] prober_io_rep_bits_addr_beat;
+ wire [25:0] prober_io_rep_bits_addr_block;
+ wire [1:0] prober_io_rep_bits_client_xact_id;
+ wire prober_io_rep_bits_voluntary;
+ wire [2:0] prober_io_rep_bits_r_type;
+ wire [127:0] prober_io_rep_bits_data;
+ wire prober_io_meta_read_ready;
+ wire prober_io_meta_read_valid;
+ wire [5:0] prober_io_meta_read_bits_idx;
+ wire [19:0] prober_io_meta_read_bits_tag;
+ wire prober_io_meta_write_ready;
+ wire prober_io_meta_write_valid;
+ wire [5:0] prober_io_meta_write_bits_idx;
+ wire [3:0] prober_io_meta_write_bits_way_en;
+ wire [19:0] prober_io_meta_write_bits_data_tag;
+ wire [1:0] prober_io_meta_write_bits_data_coh_state;
+ wire prober_io_wb_req_ready;
+ wire prober_io_wb_req_valid;
+ wire [1:0] prober_io_wb_req_bits_addr_beat;
+ wire [25:0] prober_io_wb_req_bits_addr_block;
+ wire [1:0] prober_io_wb_req_bits_client_xact_id;
+ wire prober_io_wb_req_bits_voluntary;
+ wire [2:0] prober_io_wb_req_bits_r_type;
+ wire [127:0] prober_io_wb_req_bits_data;
+ wire [3:0] prober_io_wb_req_bits_way_en;
+ wire [3:0] prober_io_way_en;
+ wire prober_io_mshr_rdy;
+ wire [1:0] prober_io_block_state_state;
+ wire mshrs_clk;
+ wire mshrs_reset;
+ wire mshrs_io_req_ready;
+ wire mshrs_io_req_valid;
+ wire [39:0] mshrs_io_req_bits_addr;
+ wire [8:0] mshrs_io_req_bits_tag;
+ wire [4:0] mshrs_io_req_bits_cmd;
+ wire [2:0] mshrs_io_req_bits_typ;
+ wire mshrs_io_req_bits_kill;
+ wire mshrs_io_req_bits_phys;
+ wire [63:0] mshrs_io_req_bits_data;
+ wire mshrs_io_req_bits_tag_match;
+ wire [19:0] mshrs_io_req_bits_old_meta_tag;
+ wire [1:0] mshrs_io_req_bits_old_meta_coh_state;
+ wire [3:0] mshrs_io_req_bits_way_en;
+ wire mshrs_io_resp_ready;
+ wire mshrs_io_resp_valid;
+ wire [39:0] mshrs_io_resp_bits_addr;
+ wire [8:0] mshrs_io_resp_bits_tag;
+ wire [4:0] mshrs_io_resp_bits_cmd;
+ wire [2:0] mshrs_io_resp_bits_typ;
+ wire [63:0] mshrs_io_resp_bits_data;
+ wire mshrs_io_resp_bits_nack;
+ wire mshrs_io_resp_bits_replay;
+ wire mshrs_io_resp_bits_has_data;
+ wire [63:0] mshrs_io_resp_bits_data_word_bypass;
+ wire [63:0] mshrs_io_resp_bits_store_data;
+ wire mshrs_io_secondary_miss;
+ wire mshrs_io_mem_req_ready;
+ wire mshrs_io_mem_req_valid;
+ wire [25:0] mshrs_io_mem_req_bits_addr_block;
+ wire [1:0] mshrs_io_mem_req_bits_client_xact_id;
+ wire [1:0] mshrs_io_mem_req_bits_addr_beat;
+ wire mshrs_io_mem_req_bits_is_builtin_type;
+ wire [2:0] mshrs_io_mem_req_bits_a_type;
+ wire [16:0] mshrs_io_mem_req_bits_union;
+ wire [127:0] mshrs_io_mem_req_bits_data;
+ wire [3:0] mshrs_io_refill_way_en;
+ wire [11:0] mshrs_io_refill_addr;
+ wire mshrs_io_meta_read_ready;
+ wire mshrs_io_meta_read_valid;
+ wire [5:0] mshrs_io_meta_read_bits_idx;
+ wire [19:0] mshrs_io_meta_read_bits_tag;
+ wire mshrs_io_meta_write_ready;
+ wire mshrs_io_meta_write_valid;
+ wire [5:0] mshrs_io_meta_write_bits_idx;
+ wire [3:0] mshrs_io_meta_write_bits_way_en;
+ wire [19:0] mshrs_io_meta_write_bits_data_tag;
+ wire [1:0] mshrs_io_meta_write_bits_data_coh_state;
+ wire mshrs_io_replay_ready;
+ wire mshrs_io_replay_valid;
+ wire [39:0] mshrs_io_replay_bits_addr;
+ wire [8:0] mshrs_io_replay_bits_tag;
+ wire [4:0] mshrs_io_replay_bits_cmd;
+ wire [2:0] mshrs_io_replay_bits_typ;
+ wire mshrs_io_replay_bits_kill;
+ wire mshrs_io_replay_bits_phys;
+ wire [63:0] mshrs_io_replay_bits_data;
+ wire mshrs_io_mem_grant_valid;
+ wire [1:0] mshrs_io_mem_grant_bits_addr_beat;
+ wire [1:0] mshrs_io_mem_grant_bits_client_xact_id;
+ wire [3:0] mshrs_io_mem_grant_bits_manager_xact_id;
+ wire mshrs_io_mem_grant_bits_is_builtin_type;
+ wire [3:0] mshrs_io_mem_grant_bits_g_type;
+ wire [127:0] mshrs_io_mem_grant_bits_data;
+ wire mshrs_io_wb_req_ready;
+ wire mshrs_io_wb_req_valid;
+ wire [1:0] mshrs_io_wb_req_bits_addr_beat;
+ wire [25:0] mshrs_io_wb_req_bits_addr_block;
+ wire [1:0] mshrs_io_wb_req_bits_client_xact_id;
+ wire mshrs_io_wb_req_bits_voluntary;
+ wire [2:0] mshrs_io_wb_req_bits_r_type;
+ wire [127:0] mshrs_io_wb_req_bits_data;
+ wire [3:0] mshrs_io_wb_req_bits_way_en;
+ wire mshrs_io_probe_rdy;
+ wire mshrs_io_fence_rdy;
+ wire T_1622;
+ reg s1_valid;
+ reg [39:0] s1_req_addr;
+ reg [8:0] s1_req_tag;
+ reg [4:0] s1_req_cmd;
+ reg [2:0] s1_req_typ;
+ reg s1_req_kill;
+ reg s1_req_phys;
+ reg [63:0] s1_req_data;
+ wire T_1680;
+ wire s1_valid_masked;
+ reg s1_replay;
+ reg s1_clk_en;
+ reg s2_valid;
+ wire T_1688;
+ reg s2_killed;
+ reg [39:0] s2_req_addr;
+ reg [8:0] s2_req_tag;
+ reg [4:0] s2_req_cmd;
+ reg [2:0] s2_req_typ;
+ reg s2_req_kill;
+ reg s2_req_phys;
+ reg [63:0] s2_req_data;
+ reg T_1745;
+ wire T_1746;
+ wire s2_replay;
+ wire s2_recycle;
+ wire s2_valid_masked;
+ reg s3_valid;
+ reg [39:0] s3_req_addr;
+ reg [8:0] s3_req_tag;
+ reg [4:0] s3_req_cmd;
+ reg [2:0] s3_req_typ;
+ reg s3_req_kill;
+ reg s3_req_phys;
+ reg [63:0] s3_req_data;
+ reg [3:0] s3_way;
+ reg s1_recycled;
+ wire T_1812;
+ wire T_1813;
+ wire T_1814;
+ wire T_1815;
+ wire T_1816;
+ wire T_1817;
+ wire T_1818;
+ wire T_1819;
+ wire s1_read;
+ wire T_1821;
+ wire T_1822;
+ wire T_1823;
+ wire T_1824;
+ wire T_1825;
+ wire T_1826;
+ wire s1_write;
+ wire T_1828;
+ wire T_1829;
+ wire T_1830;
+ wire T_1831;
+ wire s1_readwrite;
+ wire dtlb_clk;
+ wire dtlb_reset;
+ wire dtlb_io_req_ready;
+ wire dtlb_io_req_valid;
+ wire [6:0] dtlb_io_req_bits_asid;
+ wire [27:0] dtlb_io_req_bits_vpn;
+ wire dtlb_io_req_bits_passthrough;
+ wire dtlb_io_req_bits_instruction;
+ wire dtlb_io_req_bits_store;
+ wire dtlb_io_resp_miss;
+ wire [19:0] dtlb_io_resp_ppn;
+ wire dtlb_io_resp_xcpt_ld;
+ wire dtlb_io_resp_xcpt_st;
+ wire dtlb_io_resp_xcpt_if;
+ wire [7:0] dtlb_io_resp_hit_idx;
+ wire dtlb_io_ptw_req_ready;
+ wire dtlb_io_ptw_req_valid;
+ wire [26:0] dtlb_io_ptw_req_bits_addr;
+ wire [1:0] dtlb_io_ptw_req_bits_prv;
+ wire dtlb_io_ptw_req_bits_store;
+ wire dtlb_io_ptw_req_bits_fetch;
+ wire dtlb_io_ptw_resp_valid;
+ wire dtlb_io_ptw_resp_bits_error;
+ wire [19:0] dtlb_io_ptw_resp_bits_pte_ppn;
+ wire [2:0] dtlb_io_ptw_resp_bits_pte_reserved_for_software;
+ wire dtlb_io_ptw_resp_bits_pte_d;
+ wire dtlb_io_ptw_resp_bits_pte_r;
+ wire [3:0] dtlb_io_ptw_resp_bits_pte_typ;
+ wire dtlb_io_ptw_resp_bits_pte_v;
+ wire dtlb_io_ptw_status_sd;
+ wire [30:0] dtlb_io_ptw_status_zero2;
+ wire dtlb_io_ptw_status_sd_rv32;
+ wire [8:0] dtlb_io_ptw_status_zero1;
+ wire [4:0] dtlb_io_ptw_status_vm;
+ wire dtlb_io_ptw_status_mprv;
+ wire [1:0] dtlb_io_ptw_status_xs;
+ wire [1:0] dtlb_io_ptw_status_fs;
+ wire [1:0] dtlb_io_ptw_status_prv3;
+ wire dtlb_io_ptw_status_ie3;
+ wire [1:0] dtlb_io_ptw_status_prv2;
+ wire dtlb_io_ptw_status_ie2;
+ wire [1:0] dtlb_io_ptw_status_prv1;
+ wire dtlb_io_ptw_status_ie1;
+ wire [1:0] dtlb_io_ptw_status_prv;
+ wire dtlb_io_ptw_status_ie;
+ wire dtlb_io_ptw_invalidate;
+ wire T_1834;
+ wire T_1836;
+ wire T_1837;
+ wire [27:0] T_1839;
+ wire T_1842;
+ wire T_1844;
+ wire T_1845;
+ wire [25:0] T_1847;
+ wire [31:0] T_1848;
+ wire [25:0] T_1850;
+ wire [31:0] T_1851;
+ wire [11:0] T_1853;
+ wire [31:0] s1_addr;
+ wire [63:0] T_1855;
+ wire [1:0] T_1857;
+ wire [3:0] T_1859;
+ wire [4:0] T_1861;
+ wire [3:0] T_1862;
+ wire [2:0] T_1863;
+ wire [39:0] T_1864;
+ wire misaligned;
+ wire T_1867;
+ wire T_1868;
+ wire T_1869;
+ wire T_1870;
+ wire T_1871;
+ wire T_1872;
+ wire T_1873;
+ reg T_1874;
+ wire T_1875;
+ wire T_1877;
+ wire T_1879;
+ wire T_1881;
+ wire T_1883;
+ wire meta_clk;
+ wire meta_reset;
+ wire meta_io_read_ready;
+ wire meta_io_read_valid;
+ wire [5:0] meta_io_read_bits_idx;
+ wire meta_io_write_ready;
+ wire meta_io_write_valid;
+ wire [5:0] meta_io_write_bits_idx;
+ wire [3:0] meta_io_write_bits_way_en;
+ wire [19:0] meta_io_write_bits_data_tag;
+ wire [1:0] meta_io_write_bits_data_coh_state;
+ wire [19:0] meta_io_resp_0_tag;
+ wire [1:0] meta_io_resp_0_coh_state;
+ wire [19:0] meta_io_resp_1_tag;
+ wire [1:0] meta_io_resp_1_coh_state;
+ wire [19:0] meta_io_resp_2_tag;
+ wire [1:0] meta_io_resp_2_coh_state;
+ wire [19:0] meta_io_resp_3_tag;
+ wire [1:0] meta_io_resp_3_coh_state;
+ wire metaReadArb_clk;
+ wire metaReadArb_reset;
+ wire metaReadArb_io_in_0_ready;
+ wire metaReadArb_io_in_0_valid;
+ wire [5:0] metaReadArb_io_in_0_bits_idx;
+ wire metaReadArb_io_in_1_ready;
+ wire metaReadArb_io_in_1_valid;
+ wire [5:0] metaReadArb_io_in_1_bits_idx;
+ wire metaReadArb_io_in_2_ready;
+ wire metaReadArb_io_in_2_valid;
+ wire [5:0] metaReadArb_io_in_2_bits_idx;
+ wire metaReadArb_io_in_3_ready;
+ wire metaReadArb_io_in_3_valid;
+ wire [5:0] metaReadArb_io_in_3_bits_idx;
+ wire metaReadArb_io_in_4_ready;
+ wire metaReadArb_io_in_4_valid;
+ wire [5:0] metaReadArb_io_in_4_bits_idx;
+ wire metaReadArb_io_out_ready;
+ wire metaReadArb_io_out_valid;
+ wire [5:0] metaReadArb_io_out_bits_idx;
+ wire [2:0] metaReadArb_io_chosen;
+ wire metaWriteArb_clk;
+ wire metaWriteArb_reset;
+ wire metaWriteArb_io_in_0_ready;
+ wire metaWriteArb_io_in_0_valid;
+ wire [5:0] metaWriteArb_io_in_0_bits_idx;
+ wire [3:0] metaWriteArb_io_in_0_bits_way_en;
+ wire [19:0] metaWriteArb_io_in_0_bits_data_tag;
+ wire [1:0] metaWriteArb_io_in_0_bits_data_coh_state;
+ wire metaWriteArb_io_in_1_ready;
+ wire metaWriteArb_io_in_1_valid;
+ wire [5:0] metaWriteArb_io_in_1_bits_idx;
+ wire [3:0] metaWriteArb_io_in_1_bits_way_en;
+ wire [19:0] metaWriteArb_io_in_1_bits_data_tag;
+ wire [1:0] metaWriteArb_io_in_1_bits_data_coh_state;
+ wire metaWriteArb_io_out_ready;
+ wire metaWriteArb_io_out_valid;
+ wire [5:0] metaWriteArb_io_out_bits_idx;
+ wire [3:0] metaWriteArb_io_out_bits_way_en;
+ wire [19:0] metaWriteArb_io_out_bits_data_tag;
+ wire [1:0] metaWriteArb_io_out_bits_data_coh_state;
+ wire metaWriteArb_io_chosen;
+ wire data_clk;
+ wire data_reset;
+ wire data_io_read_ready;
+ wire data_io_read_valid;
+ wire [3:0] data_io_read_bits_way_en;
+ wire [11:0] data_io_read_bits_addr;
+ wire data_io_write_ready;
+ wire data_io_write_valid;
+ wire [3:0] data_io_write_bits_way_en;
+ wire [11:0] data_io_write_bits_addr;
+ wire [1:0] data_io_write_bits_wmask;
+ wire [127:0] data_io_write_bits_data;
+ wire [127:0] data_io_resp_0;
+ wire [127:0] data_io_resp_1;
+ wire [127:0] data_io_resp_2;
+ wire [127:0] data_io_resp_3;
+ wire readArb_clk;
+ wire readArb_reset;
+ wire readArb_io_in_0_ready;
+ wire readArb_io_in_0_valid;
+ wire [3:0] readArb_io_in_0_bits_way_en;
+ wire [11:0] readArb_io_in_0_bits_addr;
+ wire readArb_io_in_1_ready;
+ wire readArb_io_in_1_valid;
+ wire [3:0] readArb_io_in_1_bits_way_en;
+ wire [11:0] readArb_io_in_1_bits_addr;
+ wire readArb_io_in_2_ready;
+ wire readArb_io_in_2_valid;
+ wire [3:0] readArb_io_in_2_bits_way_en;
+ wire [11:0] readArb_io_in_2_bits_addr;
+ wire readArb_io_in_3_ready;
+ wire readArb_io_in_3_valid;
+ wire [3:0] readArb_io_in_3_bits_way_en;
+ wire [11:0] readArb_io_in_3_bits_addr;
+ wire readArb_io_out_ready;
+ wire readArb_io_out_valid;
+ wire [3:0] readArb_io_out_bits_way_en;
+ wire [11:0] readArb_io_out_bits_addr;
+ wire [1:0] readArb_io_chosen;
+ wire writeArb_clk;
+ wire writeArb_reset;
+ wire writeArb_io_in_0_ready;
+ wire writeArb_io_in_0_valid;
+ wire [3:0] writeArb_io_in_0_bits_way_en;
+ wire [11:0] writeArb_io_in_0_bits_addr;
+ wire [1:0] writeArb_io_in_0_bits_wmask;
+ wire [127:0] writeArb_io_in_0_bits_data;
+ wire writeArb_io_in_1_ready;
+ wire writeArb_io_in_1_valid;
+ wire [3:0] writeArb_io_in_1_bits_way_en;
+ wire [11:0] writeArb_io_in_1_bits_addr;
+ wire [1:0] writeArb_io_in_1_bits_wmask;
+ wire [127:0] writeArb_io_in_1_bits_data;
+ wire writeArb_io_out_ready;
+ wire writeArb_io_out_valid;
+ wire [3:0] writeArb_io_out_bits_way_en;
+ wire [11:0] writeArb_io_out_bits_addr;
+ wire [1:0] writeArb_io_out_bits_wmask;
+ wire [127:0] writeArb_io_out_bits_data;
+ wire writeArb_io_chosen;
+ wire [63:0] T_2141;
+ wire [63:0] T_2142;
+ wire [63:0] T_2144_0;
+ wire [63:0] T_2144_1;
+ wire [127:0] T_2148;
+ wire [33:0] T_2149;
+ wire T_2151;
+ wire [3:0] T_2154;
+ wire T_2156;
+ wire [33:0] T_2158;
+ wire [3:0] T_2160;
+ wire [19:0] T_2161;
+ wire T_2162;
+ wire [19:0] T_2163;
+ wire T_2164;
+ wire [19:0] T_2165;
+ wire T_2166;
+ wire [19:0] T_2167;
+ wire T_2168;
+ wire T_2170_0;
+ wire T_2170_1;
+ wire T_2170_2;
+ wire T_2170_3;
+ wire [1:0] T_2176;
+ wire [1:0] T_2177;
+ wire [3:0] s1_tag_eq_way;
+ wire T_2179;
+ wire T_2180;
+ wire T_2181;
+ wire T_2182;
+ wire T_2183;
+ wire T_2184;
+ wire T_2185;
+ wire T_2186;
+ wire T_2187;
+ wire T_2188;
+ wire T_2189;
+ wire T_2190;
+ wire T_2192_0;
+ wire T_2192_1;
+ wire T_2192_2;
+ wire T_2192_3;
+ wire [1:0] T_2198;
+ wire [1:0] T_2199;
+ wire [3:0] s1_tag_match_way;
+ wire T_2202;
+ wire T_2203;
+ wire T_2205;
+ wire s1_writeback;
+ reg [3:0] s2_tag_match_way;
+ wire s2_tag_match;
+ reg [1:0] T_2210_state;
+ reg [1:0] T_2235_state;
+ reg [1:0] T_2260_state;
+ reg [1:0] T_2285_state;
+ wire [1:0] T_2335_0_state;
+ wire [1:0] T_2335_1_state;
+ wire [1:0] T_2335_2_state;
+ wire [1:0] T_2335_3_state;
+ wire T_2461;
+ wire T_2462;
+ wire T_2463;
+ wire T_2464;
+ wire [1:0] T_2466;
+ wire [1:0] T_2468;
+ wire [1:0] T_2470;
+ wire [1:0] T_2472;
+ wire [1:0] T_2498;
+ wire [1:0] T_2499;
+ wire [1:0] T_2500;
+ wire [1:0] s2_hit_state_state;
+ wire [1:0] T_2551;
+ wire T_2552;
+ wire T_2553;
+ wire T_2554;
+ wire T_2555;
+ wire T_2556;
+ wire T_2557;
+ wire T_2558;
+ wire T_2559;
+ wire T_2560;
+ wire T_2561;
+ wire T_2562;
+ wire [1:0] T_2564_0;
+ wire [1:0] T_2564_1;
+ wire T_2568;
+ wire T_2569;
+ wire T_2571;
+ wire T_2572;
+ wire [1:0] T_2574_0;
+ wire [1:0] T_2574_1;
+ wire [1:0] T_2574_2;
+ wire T_2579;
+ wire T_2580;
+ wire T_2581;
+ wire T_2583;
+ wire T_2584;
+ wire T_2585;
+ wire T_2586;
+ wire T_2587;
+ wire T_2588;
+ wire T_2589;
+ wire T_2590;
+ wire T_2591;
+ wire T_2592;
+ wire T_2593;
+ wire T_2594;
+ wire [1:0] T_2595;
+ wire [1:0] T_2621_state;
+ wire T_2646;
+ wire s2_hit;
+ reg [4:0] lrsc_count;
+ wire lrsc_valid;
+ reg [33:0] lrsc_addr;
+ wire s2_lr;
+ wire s2_sc;
+ wire [33:0] T_2656;
+ wire T_2657;
+ wire s2_lrsc_addr_match;
+ wire T_2660;
+ wire s2_sc_fail;
+ wire [5:0] T_2663;
+ wire [4:0] T_2664;
+ wire T_2665;
+ wire T_2666;
+ wire T_2668;
+ wire [33:0] T_2670;
+ wire [127:0] s2_data_0;
+ wire [127:0] s2_data_1;
+ wire [127:0] s2_data_2;
+ wire [127:0] s2_data_3;
+ reg [63:0] T_2697_0;
+ reg [63:0] T_2697_1;
+ wire T_2701;
+ wire T_2702;
+ wire T_2706;
+ wire T_2707;
+ wire T_2708;
+ wire T_2709;
+ wire [127:0] T_2710;
+ wire T_2714;
+ wire T_2715;
+ wire T_2716;
+ wire T_2717;
+ wire [63:0] T_2718;
+ wire [127:0] T_2719;
+ reg [63:0] T_2728_0;
+ reg [63:0] T_2728_1;
+ wire T_2732;
+ wire T_2733;
+ wire T_2737;
+ wire T_2738;
+ wire T_2739;
+ wire T_2740;
+ wire [127:0] T_2741;
+ wire T_2745;
+ wire T_2746;
+ wire T_2747;
+ wire T_2748;
+ wire [63:0] T_2749;
+ wire [127:0] T_2750;
+ reg [63:0] T_2759_0;
+ reg [63:0] T_2759_1;
+ wire T_2763;
+ wire T_2764;
+ wire T_2768;
+ wire T_2769;
+ wire T_2770;
+ wire T_2771;
+ wire [127:0] T_2772;
+ wire T_2776;
+ wire T_2777;
+ wire T_2778;
+ wire T_2779;
+ wire [63:0] T_2780;
+ wire [127:0] T_2781;
+ reg [63:0] T_2790_0;
+ reg [63:0] T_2790_1;
+ wire T_2794;
+ wire T_2795;
+ wire T_2799;
+ wire T_2800;
+ wire T_2801;
+ wire T_2802;
+ wire [127:0] T_2803;
+ wire T_2807;
+ wire T_2808;
+ wire T_2809;
+ wire T_2810;
+ wire [63:0] T_2811;
+ wire [127:0] T_2812;
+ wire T_2813;
+ wire T_2814;
+ wire T_2815;
+ wire T_2816;
+ wire [127:0] T_2818;
+ wire [127:0] T_2820;
+ wire [127:0] T_2822;
+ wire [127:0] T_2824;
+ wire [127:0] T_2826;
+ wire [127:0] T_2827;
+ wire [127:0] T_2828;
+ wire [127:0] s2_data_muxed;
+ wire [63:0] T_2830;
+ wire [63:0] T_2831;
+ wire [63:0] T_2833_0;
+ wire [63:0] T_2833_1;
+ wire [127:0] s2_data_corrected;
+ wire [63:0] T_2839_0;
+ wire [63:0] T_2839_1;
+ wire [127:0] s2_data_uncorrected;
+ wire T_2848_0;
+ wire T_2848_1;
+ wire [1:0] T_2852;
+ wire [1:0] T_2853;
+ wire s2_data_correctable;
+ wire T_2855;
+ wire T_2856;
+ wire T_2858;
+ wire T_2859;
+ wire T_2860;
+ wire T_2861;
+ wire T_2862;
+ wire T_2863;
+ wire T_2864;
+ wire T_2865;
+ wire T_2866;
+ wire T_2867;
+ wire amoalu_clk;
+ wire amoalu_reset;
+ wire [5:0] amoalu_io_addr;
+ wire [4:0] amoalu_io_cmd;
+ wire [2:0] amoalu_io_typ;
+ wire [63:0] amoalu_io_lhs;
+ wire [63:0] amoalu_io_rhs;
+ wire [63:0] amoalu_io_out;
+ wire T_2869;
+ wire T_2870;
+ wire T_2871;
+ wire T_2872;
+ wire T_2873;
+ wire T_2874;
+ wire T_2875;
+ wire T_2876;
+ wire T_2877;
+ wire T_2878;
+ wire [127:0] T_2879;
+ wire rowIdx;
+ wire [1:0] rowWMask;
+ wire [127:0] T_2883;
+ wire T_2885;
+ reg [15:0] T_2888;
+ wire T_2889;
+ wire T_2890;
+ wire T_2891;
+ wire T_2892;
+ wire T_2893;
+ wire T_2894;
+ wire T_2895;
+ wire [14:0] T_2896;
+ wire [15:0] T_2897;
+ wire [1:0] T_2898;
+ wire [3:0] s1_replaced_way_en;
+ wire [1:0] T_2901;
+ reg [1:0] T_2902;
+ wire [3:0] s2_replaced_way_en;
+ wire T_2905;
+ wire T_2906;
+ reg [19:0] T_2907_tag;
+ reg [1:0] T_2907_coh_state;
+ wire T_2980;
+ wire T_2981;
+ reg [19:0] T_2982_tag;
+ reg [1:0] T_2982_coh_state;
+ wire T_3055;
+ wire T_3056;
+ reg [19:0] T_3057_tag;
+ reg [1:0] T_3057_coh_state;
+ wire T_3130;
+ wire T_3131;
+ reg [19:0] T_3132_tag;
+ reg [1:0] T_3132_coh_state;
+ wire [19:0] T_3278_0_tag;
+ wire [1:0] T_3278_0_coh_state;
+ wire [19:0] T_3278_1_tag;
+ wire [1:0] T_3278_1_coh_state;
+ wire [19:0] T_3278_2_tag;
+ wire [1:0] T_3278_2_coh_state;
+ wire [19:0] T_3278_3_tag;
+ wire [1:0] T_3278_3_coh_state;
+ wire T_3644;
+ wire T_3645;
+ wire T_3646;
+ wire T_3647;
+ wire [21:0] T_3648;
+ wire [21:0] T_3650;
+ wire [21:0] T_3651;
+ wire [21:0] T_3653;
+ wire [21:0] T_3654;
+ wire [21:0] T_3656;
+ wire [21:0] T_3657;
+ wire [21:0] T_3659;
+ wire [21:0] T_3733;
+ wire [21:0] T_3734;
+ wire [21:0] T_3735;
+ wire [19:0] s2_repl_meta_tag;
+ wire [1:0] s2_repl_meta_coh_state;
+ wire [1:0] T_3882;
+ wire [19:0] T_3883;
+ wire T_3885;
+ wire T_3886;
+ wire T_3887;
+ wire T_3888;
+ wire T_3889;
+ wire T_3890;
+ wire T_3891;
+ wire T_3892;
+ wire T_3893;
+ wire T_3894;
+ wire T_3895;
+ wire T_3896;
+ wire T_3897;
+ wire T_3898;
+ wire T_3899;
+ wire T_3900;
+ wire T_3901;
+ wire T_3902;
+ wire T_3903;
+ wire T_3904;
+ wire T_3905;
+ wire T_3906;
+ wire T_3907;
+ wire T_3908;
+ wire [19:0] T_3982_tag;
+ wire [1:0] T_3982_coh_state;
+ wire [19:0] T_4055_tag;
+ wire [1:0] T_4055_coh_state;
+ wire [3:0] T_4128;
+ wire T_4129;
+ wire [3:0] T_4132;
+ wire T_4133;
+ wire releaseArb_clk;
+ wire releaseArb_reset;
+ wire releaseArb_io_in_0_ready;
+ wire releaseArb_io_in_0_valid;
+ wire [1:0] releaseArb_io_in_0_bits_addr_beat;
+ wire [25:0] releaseArb_io_in_0_bits_addr_block;
+ wire [1:0] releaseArb_io_in_0_bits_client_xact_id;
+ wire releaseArb_io_in_0_bits_voluntary;
+ wire [2:0] releaseArb_io_in_0_bits_r_type;
+ wire [127:0] releaseArb_io_in_0_bits_data;
+ wire releaseArb_io_in_1_ready;
+ wire releaseArb_io_in_1_valid;
+ wire [1:0] releaseArb_io_in_1_bits_addr_beat;
+ wire [25:0] releaseArb_io_in_1_bits_addr_block;
+ wire [1:0] releaseArb_io_in_1_bits_client_xact_id;
+ wire releaseArb_io_in_1_bits_voluntary;
+ wire [2:0] releaseArb_io_in_1_bits_r_type;
+ wire [127:0] releaseArb_io_in_1_bits_data;
+ wire releaseArb_io_out_ready;
+ wire releaseArb_io_out_valid;
+ wire [1:0] releaseArb_io_out_bits_addr_beat;
+ wire [25:0] releaseArb_io_out_bits_addr_block;
+ wire [1:0] releaseArb_io_out_bits_client_xact_id;
+ wire releaseArb_io_out_bits_voluntary;
+ wire [2:0] releaseArb_io_out_bits_r_type;
+ wire [127:0] releaseArb_io_out_bits_data;
+ wire releaseArb_io_chosen;
+ wire T_4166;
+ wire T_4167;
+ wire T_4169;
+ wire T_4170;
+ wire T_4171_clk;
+ wire T_4171_reset;
+ wire T_4171_io_in_ready;
+ wire T_4171_io_in_valid;
+ wire [1:0] T_4171_io_in_bits_addr_beat;
+ wire [1:0] T_4171_io_in_bits_client_xact_id;
+ wire [3:0] T_4171_io_in_bits_manager_xact_id;
+ wire T_4171_io_in_bits_is_builtin_type;
+ wire [3:0] T_4171_io_in_bits_g_type;
+ wire [127:0] T_4171_io_in_bits_data;
+ wire T_4171_io_out_ready;
+ wire T_4171_io_out_valid;
+ wire [1:0] T_4171_io_out_bits_addr_beat;
+ wire [1:0] T_4171_io_out_bits_client_xact_id;
+ wire [3:0] T_4171_io_out_bits_manager_xact_id;
+ wire T_4171_io_out_bits_is_builtin_type;
+ wire [3:0] T_4171_io_out_bits_g_type;
+ wire [127:0] T_4171_io_out_bits_data;
+ wire T_4171_io_cnt;
+ wire T_4171_io_done;
+ wire T_4172;
+ wire [2:0] T_4176_0;
+ wire [2:0] T_4176_1;
+ wire T_4180;
+ wire T_4181;
+ wire T_4183;
+ wire T_4184;
+ wire T_4186_0;
+ wire T_4186_1;
+ wire T_4190;
+ wire T_4191;
+ wire T_4193;
+ wire T_4194;
+ wire T_4195;
+ wire T_4197;
+ wire T_4198;
+ wire [2:0] T_4202_0;
+ wire [2:0] T_4202_1;
+ wire T_4206;
+ wire T_4207;
+ wire T_4209;
+ wire T_4210;
+ wire T_4212_0;
+ wire T_4212_1;
+ wire T_4216;
+ wire T_4217;
+ wire T_4219;
+ wire T_4220;
+ wire T_4221;
+ wire T_4222;
+ wire T_4224;
+ wire T_4225;
+ wire [1:0] T_4227;
+ wire [127:0] T_4228;
+ wire T_4230;
+ wire T_4231;
+ wire wbArb_clk;
+ wire wbArb_reset;
+ wire wbArb_io_in_0_ready;
+ wire wbArb_io_in_0_valid;
+ wire [1:0] wbArb_io_in_0_bits_addr_beat;
+ wire [25:0] wbArb_io_in_0_bits_addr_block;
+ wire [1:0] wbArb_io_in_0_bits_client_xact_id;
+ wire wbArb_io_in_0_bits_voluntary;
+ wire [2:0] wbArb_io_in_0_bits_r_type;
+ wire [127:0] wbArb_io_in_0_bits_data;
+ wire [3:0] wbArb_io_in_0_bits_way_en;
+ wire wbArb_io_in_1_ready;
+ wire wbArb_io_in_1_valid;
+ wire [1:0] wbArb_io_in_1_bits_addr_beat;
+ wire [25:0] wbArb_io_in_1_bits_addr_block;
+ wire [1:0] wbArb_io_in_1_bits_client_xact_id;
+ wire wbArb_io_in_1_bits_voluntary;
+ wire [2:0] wbArb_io_in_1_bits_r_type;
+ wire [127:0] wbArb_io_in_1_bits_data;
+ wire [3:0] wbArb_io_in_1_bits_way_en;
+ wire wbArb_io_out_ready;
+ wire wbArb_io_out_valid;
+ wire [1:0] wbArb_io_out_bits_addr_beat;
+ wire [25:0] wbArb_io_out_bits_addr_block;
+ wire [1:0] wbArb_io_out_bits_client_xact_id;
+ wire wbArb_io_out_bits_voluntary;
+ wire [2:0] wbArb_io_out_bits_r_type;
+ wire [127:0] wbArb_io_out_bits_data;
+ wire [3:0] wbArb_io_out_bits_way_en;
+ wire wbArb_io_chosen;
+ reg s4_valid;
+ wire T_4266;
+ reg [39:0] s4_req_addr;
+ reg [8:0] s4_req_tag;
+ reg [4:0] s4_req_cmd;
+ reg [2:0] s4_req_typ;
+ reg s4_req_kill;
+ reg s4_req_phys;
+ reg [63:0] s4_req_data;
+ wire T_4321;
+ wire T_4323;
+ wire T_4324;
+ wire [28:0] T_4325;
+ wire [36:0] T_4326;
+ wire T_4327;
+ wire T_4328;
+ wire T_4329;
+ wire T_4330;
+ wire T_4331;
+ wire T_4332;
+ wire T_4333;
+ wire T_4334;
+ wire T_4335;
+ wire T_4336;
+ wire [28:0] T_4337;
+ wire [36:0] T_4338;
+ wire T_4339;
+ wire T_4340;
+ wire T_4341;
+ wire T_4342;
+ wire T_4343;
+ wire T_4344;
+ wire T_4345;
+ wire T_4346;
+ wire T_4347;
+ wire T_4348;
+ wire [28:0] T_4349;
+ wire [36:0] T_4350;
+ wire T_4351;
+ wire T_4352;
+ wire T_4353;
+ wire T_4354;
+ wire T_4355;
+ wire T_4356;
+ wire T_4357;
+ wire T_4358;
+ wire T_4359;
+ wire T_4360;
+ reg [63:0] s2_store_bypass_data;
+ reg s2_store_bypass;
+ wire T_4366;
+ wire T_4367;
+ wire [63:0] T_4368;
+ wire [63:0] T_4369;
+ wire [6:0] T_4372;
+ wire [127:0] s2_data_word_prebypass;
+ wire [127:0] s2_data_word;
+ wire [1:0] T_4375;
+ wire [2:0] T_4376;
+ wire GEN_0;
+ wire T_4378;
+ wire T_4379;
+ wire [5:0] T_4380;
+ wire T_4381;
+ wire T_4383;
+ wire T_4384;
+ wire s1_nack;
+ wire T_4386;
+ reg s2_nack_hit;
+ wire s2_nack_victim;
+ wire T_4391;
+ wire T_4393;
+ wire s2_nack_miss;
+ wire T_4395;
+ wire s2_nack;
+ wire T_4398;
+ wire T_4399;
+ wire T_4400;
+ wire T_4401;
+ wire s2_recycle_ecc;
+ reg s2_recycle_next;
+ wire T_4405;
+ wire T_4406;
+ reg block_miss;
+ wire T_4409;
+ wire T_4410;
+ wire cache_resp_valid;
+ wire [39:0] cache_resp_bits_addr;
+ wire [8:0] cache_resp_bits_tag;
+ wire [4:0] cache_resp_bits_cmd;
+ wire [2:0] cache_resp_bits_typ;
+ wire [63:0] cache_resp_bits_data;
+ wire cache_resp_bits_nack;
+ wire cache_resp_bits_replay;
+ wire cache_resp_bits_has_data;
+ wire [63:0] cache_resp_bits_data_word_bypass;
+ wire [63:0] cache_resp_bits_store_data;
+ wire T_4701;
+ wire T_4702;
+ wire T_4704;
+ wire T_4705;
+ wire T_4706;
+ wire T_4707;
+ wire T_4708;
+ wire T_4709;
+ wire T_4710;
+ wire T_4711;
+ wire T_4712;
+ wire T_4713;
+ wire T_4714;
+ wire T_4715;
+ wire [31:0] T_4716;
+ wire [31:0] T_4717;
+ wire [31:0] T_4718;
+ wire T_4720;
+ wire [31:0] T_4722;
+ wire T_4724;
+ wire T_4725;
+ wire T_4726;
+ wire T_4727;
+ wire [32:0] T_4729;
+ wire [31:0] T_4730;
+ wire [31:0] T_4731;
+ wire [31:0] T_4732;
+ wire [63:0] T_4733;
+ wire T_4734;
+ wire [15:0] T_4735;
+ wire [15:0] T_4736;
+ wire [15:0] T_4737;
+ wire T_4739;
+ wire [15:0] T_4741;
+ wire T_4743;
+ wire T_4744;
+ wire T_4745;
+ wire T_4746;
+ wire [48:0] T_4748;
+ wire [47:0] T_4749;
+ wire [47:0] T_4750;
+ wire [47:0] T_4751;
+ wire [63:0] T_4752;
+ wire T_4753;
+ wire [7:0] T_4754;
+ wire [7:0] T_4755;
+ wire [7:0] T_4756;
+ wire T_4758;
+ wire [7:0] T_4760;
+ wire T_4762;
+ wire T_4763;
+ wire T_4764;
+ wire T_4765;
+ wire [56:0] T_4767;
+ wire [55:0] T_4768;
+ wire [55:0] T_4769;
+ wire [55:0] T_4770;
+ wire [63:0] T_4771;
+ wire [63:0] T_4772;
+ wire T_4773;
+ wire uncache_resp_valid;
+ wire [39:0] uncache_resp_bits_addr;
+ wire [8:0] uncache_resp_bits_tag;
+ wire [4:0] uncache_resp_bits_cmd;
+ wire [2:0] uncache_resp_bits_typ;
+ wire [63:0] uncache_resp_bits_data;
+ wire uncache_resp_bits_nack;
+ wire uncache_resp_bits_replay;
+ wire uncache_resp_bits_has_data;
+ wire [63:0] uncache_resp_bits_data_word_bypass;
+ wire [63:0] uncache_resp_bits_store_data;
+ wire T_5063;
+ wire cache_pass;
+ wire T_5066;
+ wire T_5067_valid;
+ wire [39:0] T_5067_bits_addr;
+ wire [8:0] T_5067_bits_tag;
+ wire [4:0] T_5067_bits_cmd;
+ wire [2:0] T_5067_bits_typ;
+ wire [63:0] T_5067_bits_data;
+ wire T_5067_bits_nack;
+ wire T_5067_bits_replay;
+ wire T_5067_bits_has_data;
+ wire [63:0] T_5067_bits_data_word_bypass;
+ wire [63:0] T_5067_bits_store_data;
+ wire T_5183;
+ wire [31:0] T_5184;
+ wire [31:0] T_5185;
+ wire [31:0] T_5186;
+ wire T_5188;
+ wire [31:0] T_5190;
+ wire T_5192;
+ wire T_5193;
+ wire T_5194;
+ wire T_5195;
+ wire [32:0] T_5197;
+ wire [31:0] T_5198;
+ wire [31:0] T_5199;
+ wire [31:0] T_5200;
+ wire [63:0] T_5201;
+ wire T_5203;
+ wire T_5204;
+ wire T_5206;
+ wire T_5207;
+ wire T_5208;
+ wire GEN_1;
+ reg [1:0] GEN_2;
+ reg [63:0] GEN_3;
+ WritebackUnit wb (
+ .clk(wb_clk),
+ .reset(wb_reset),
+ .io_req_ready(wb_io_req_ready),
+ .io_req_valid(wb_io_req_valid),
+ .io_req_bits_addr_beat(wb_io_req_bits_addr_beat),
+ .io_req_bits_addr_block(wb_io_req_bits_addr_block),
+ .io_req_bits_client_xact_id(wb_io_req_bits_client_xact_id),
+ .io_req_bits_voluntary(wb_io_req_bits_voluntary),
+ .io_req_bits_r_type(wb_io_req_bits_r_type),
+ .io_req_bits_data(wb_io_req_bits_data),
+ .io_req_bits_way_en(wb_io_req_bits_way_en),
+ .io_meta_read_ready(wb_io_meta_read_ready),
+ .io_meta_read_valid(wb_io_meta_read_valid),
+ .io_meta_read_bits_idx(wb_io_meta_read_bits_idx),
+ .io_meta_read_bits_tag(wb_io_meta_read_bits_tag),
+ .io_data_req_ready(wb_io_data_req_ready),
+ .io_data_req_valid(wb_io_data_req_valid),
+ .io_data_req_bits_way_en(wb_io_data_req_bits_way_en),
+ .io_data_req_bits_addr(wb_io_data_req_bits_addr),
+ .io_data_resp(wb_io_data_resp),
+ .io_release_ready(wb_io_release_ready),
+ .io_release_valid(wb_io_release_valid),
+ .io_release_bits_addr_beat(wb_io_release_bits_addr_beat),
+ .io_release_bits_addr_block(wb_io_release_bits_addr_block),
+ .io_release_bits_client_xact_id(wb_io_release_bits_client_xact_id),
+ .io_release_bits_voluntary(wb_io_release_bits_voluntary),
+ .io_release_bits_r_type(wb_io_release_bits_r_type),
+ .io_release_bits_data(wb_io_release_bits_data)
+ );
+ ProbeUnit prober (
+ .clk(prober_clk),
+ .reset(prober_reset),
+ .io_req_ready(prober_io_req_ready),
+ .io_req_valid(prober_io_req_valid),
+ .io_req_bits_addr_block(prober_io_req_bits_addr_block),
+ .io_req_bits_p_type(prober_io_req_bits_p_type),
+ .io_req_bits_client_xact_id(prober_io_req_bits_client_xact_id),
+ .io_rep_ready(prober_io_rep_ready),
+ .io_rep_valid(prober_io_rep_valid),
+ .io_rep_bits_addr_beat(prober_io_rep_bits_addr_beat),
+ .io_rep_bits_addr_block(prober_io_rep_bits_addr_block),
+ .io_rep_bits_client_xact_id(prober_io_rep_bits_client_xact_id),
+ .io_rep_bits_voluntary(prober_io_rep_bits_voluntary),
+ .io_rep_bits_r_type(prober_io_rep_bits_r_type),
+ .io_rep_bits_data(prober_io_rep_bits_data),
+ .io_meta_read_ready(prober_io_meta_read_ready),
+ .io_meta_read_valid(prober_io_meta_read_valid),
+ .io_meta_read_bits_idx(prober_io_meta_read_bits_idx),
+ .io_meta_read_bits_tag(prober_io_meta_read_bits_tag),
+ .io_meta_write_ready(prober_io_meta_write_ready),
+ .io_meta_write_valid(prober_io_meta_write_valid),
+ .io_meta_write_bits_idx(prober_io_meta_write_bits_idx),
+ .io_meta_write_bits_way_en(prober_io_meta_write_bits_way_en),
+ .io_meta_write_bits_data_tag(prober_io_meta_write_bits_data_tag),
+ .io_meta_write_bits_data_coh_state(prober_io_meta_write_bits_data_coh_state),
+ .io_wb_req_ready(prober_io_wb_req_ready),
+ .io_wb_req_valid(prober_io_wb_req_valid),
+ .io_wb_req_bits_addr_beat(prober_io_wb_req_bits_addr_beat),
+ .io_wb_req_bits_addr_block(prober_io_wb_req_bits_addr_block),
+ .io_wb_req_bits_client_xact_id(prober_io_wb_req_bits_client_xact_id),
+ .io_wb_req_bits_voluntary(prober_io_wb_req_bits_voluntary),
+ .io_wb_req_bits_r_type(prober_io_wb_req_bits_r_type),
+ .io_wb_req_bits_data(prober_io_wb_req_bits_data),
+ .io_wb_req_bits_way_en(prober_io_wb_req_bits_way_en),
+ .io_way_en(prober_io_way_en),
+ .io_mshr_rdy(prober_io_mshr_rdy),
+ .io_block_state_state(prober_io_block_state_state)
+ );
+ MSHRFile mshrs (
+ .clk(mshrs_clk),
+ .reset(mshrs_reset),
+ .io_req_ready(mshrs_io_req_ready),
+ .io_req_valid(mshrs_io_req_valid),
+ .io_req_bits_addr(mshrs_io_req_bits_addr),
+ .io_req_bits_tag(mshrs_io_req_bits_tag),
+ .io_req_bits_cmd(mshrs_io_req_bits_cmd),
+ .io_req_bits_typ(mshrs_io_req_bits_typ),
+ .io_req_bits_kill(mshrs_io_req_bits_kill),
+ .io_req_bits_phys(mshrs_io_req_bits_phys),
+ .io_req_bits_data(mshrs_io_req_bits_data),
+ .io_req_bits_tag_match(mshrs_io_req_bits_tag_match),
+ .io_req_bits_old_meta_tag(mshrs_io_req_bits_old_meta_tag),
+ .io_req_bits_old_meta_coh_state(mshrs_io_req_bits_old_meta_coh_state),
+ .io_req_bits_way_en(mshrs_io_req_bits_way_en),
+ .io_resp_ready(mshrs_io_resp_ready),
+ .io_resp_valid(mshrs_io_resp_valid),
+ .io_resp_bits_addr(mshrs_io_resp_bits_addr),
+ .io_resp_bits_tag(mshrs_io_resp_bits_tag),
+ .io_resp_bits_cmd(mshrs_io_resp_bits_cmd),
+ .io_resp_bits_typ(mshrs_io_resp_bits_typ),
+ .io_resp_bits_data(mshrs_io_resp_bits_data),
+ .io_resp_bits_nack(mshrs_io_resp_bits_nack),
+ .io_resp_bits_replay(mshrs_io_resp_bits_replay),
+ .io_resp_bits_has_data(mshrs_io_resp_bits_has_data),
+ .io_resp_bits_data_word_bypass(mshrs_io_resp_bits_data_word_bypass),
+ .io_resp_bits_store_data(mshrs_io_resp_bits_store_data),
+ .io_secondary_miss(mshrs_io_secondary_miss),
+ .io_mem_req_ready(mshrs_io_mem_req_ready),
+ .io_mem_req_valid(mshrs_io_mem_req_valid),
+ .io_mem_req_bits_addr_block(mshrs_io_mem_req_bits_addr_block),
+ .io_mem_req_bits_client_xact_id(mshrs_io_mem_req_bits_client_xact_id),
+ .io_mem_req_bits_addr_beat(mshrs_io_mem_req_bits_addr_beat),
+ .io_mem_req_bits_is_builtin_type(mshrs_io_mem_req_bits_is_builtin_type),
+ .io_mem_req_bits_a_type(mshrs_io_mem_req_bits_a_type),
+ .io_mem_req_bits_union(mshrs_io_mem_req_bits_union),
+ .io_mem_req_bits_data(mshrs_io_mem_req_bits_data),
+ .io_refill_way_en(mshrs_io_refill_way_en),
+ .io_refill_addr(mshrs_io_refill_addr),
+ .io_meta_read_ready(mshrs_io_meta_read_ready),
+ .io_meta_read_valid(mshrs_io_meta_read_valid),
+ .io_meta_read_bits_idx(mshrs_io_meta_read_bits_idx),
+ .io_meta_read_bits_tag(mshrs_io_meta_read_bits_tag),
+ .io_meta_write_ready(mshrs_io_meta_write_ready),
+ .io_meta_write_valid(mshrs_io_meta_write_valid),
+ .io_meta_write_bits_idx(mshrs_io_meta_write_bits_idx),
+ .io_meta_write_bits_way_en(mshrs_io_meta_write_bits_way_en),
+ .io_meta_write_bits_data_tag(mshrs_io_meta_write_bits_data_tag),
+ .io_meta_write_bits_data_coh_state(mshrs_io_meta_write_bits_data_coh_state),
+ .io_replay_ready(mshrs_io_replay_ready),
+ .io_replay_valid(mshrs_io_replay_valid),
+ .io_replay_bits_addr(mshrs_io_replay_bits_addr),
+ .io_replay_bits_tag(mshrs_io_replay_bits_tag),
+ .io_replay_bits_cmd(mshrs_io_replay_bits_cmd),
+ .io_replay_bits_typ(mshrs_io_replay_bits_typ),
+ .io_replay_bits_kill(mshrs_io_replay_bits_kill),
+ .io_replay_bits_phys(mshrs_io_replay_bits_phys),
+ .io_replay_bits_data(mshrs_io_replay_bits_data),
+ .io_mem_grant_valid(mshrs_io_mem_grant_valid),
+ .io_mem_grant_bits_addr_beat(mshrs_io_mem_grant_bits_addr_beat),
+ .io_mem_grant_bits_client_xact_id(mshrs_io_mem_grant_bits_client_xact_id),
+ .io_mem_grant_bits_manager_xact_id(mshrs_io_mem_grant_bits_manager_xact_id),
+ .io_mem_grant_bits_is_builtin_type(mshrs_io_mem_grant_bits_is_builtin_type),
+ .io_mem_grant_bits_g_type(mshrs_io_mem_grant_bits_g_type),
+ .io_mem_grant_bits_data(mshrs_io_mem_grant_bits_data),
+ .io_wb_req_ready(mshrs_io_wb_req_ready),
+ .io_wb_req_valid(mshrs_io_wb_req_valid),
+ .io_wb_req_bits_addr_beat(mshrs_io_wb_req_bits_addr_beat),
+ .io_wb_req_bits_addr_block(mshrs_io_wb_req_bits_addr_block),
+ .io_wb_req_bits_client_xact_id(mshrs_io_wb_req_bits_client_xact_id),
+ .io_wb_req_bits_voluntary(mshrs_io_wb_req_bits_voluntary),
+ .io_wb_req_bits_r_type(mshrs_io_wb_req_bits_r_type),
+ .io_wb_req_bits_data(mshrs_io_wb_req_bits_data),
+ .io_wb_req_bits_way_en(mshrs_io_wb_req_bits_way_en),
+ .io_probe_rdy(mshrs_io_probe_rdy),
+ .io_fence_rdy(mshrs_io_fence_rdy)
+ );
+ TLB dtlb (
+ .clk(dtlb_clk),
+ .reset(dtlb_reset),
+ .io_req_ready(dtlb_io_req_ready),
+ .io_req_valid(dtlb_io_req_valid),
+ .io_req_bits_asid(dtlb_io_req_bits_asid),
+ .io_req_bits_vpn(dtlb_io_req_bits_vpn),
+ .io_req_bits_passthrough(dtlb_io_req_bits_passthrough),
+ .io_req_bits_instruction(dtlb_io_req_bits_instruction),
+ .io_req_bits_store(dtlb_io_req_bits_store),
+ .io_resp_miss(dtlb_io_resp_miss),
+ .io_resp_ppn(dtlb_io_resp_ppn),
+ .io_resp_xcpt_ld(dtlb_io_resp_xcpt_ld),
+ .io_resp_xcpt_st(dtlb_io_resp_xcpt_st),
+ .io_resp_xcpt_if(dtlb_io_resp_xcpt_if),
+ .io_resp_hit_idx(dtlb_io_resp_hit_idx),
+ .io_ptw_req_ready(dtlb_io_ptw_req_ready),
+ .io_ptw_req_valid(dtlb_io_ptw_req_valid),
+ .io_ptw_req_bits_addr(dtlb_io_ptw_req_bits_addr),
+ .io_ptw_req_bits_prv(dtlb_io_ptw_req_bits_prv),
+ .io_ptw_req_bits_store(dtlb_io_ptw_req_bits_store),
+ .io_ptw_req_bits_fetch(dtlb_io_ptw_req_bits_fetch),
+ .io_ptw_resp_valid(dtlb_io_ptw_resp_valid),
+ .io_ptw_resp_bits_error(dtlb_io_ptw_resp_bits_error),
+ .io_ptw_resp_bits_pte_ppn(dtlb_io_ptw_resp_bits_pte_ppn),
+ .io_ptw_resp_bits_pte_reserved_for_software(dtlb_io_ptw_resp_bits_pte_reserved_for_software),
+ .io_ptw_resp_bits_pte_d(dtlb_io_ptw_resp_bits_pte_d),
+ .io_ptw_resp_bits_pte_r(dtlb_io_ptw_resp_bits_pte_r),
+ .io_ptw_resp_bits_pte_typ(dtlb_io_ptw_resp_bits_pte_typ),
+ .io_ptw_resp_bits_pte_v(dtlb_io_ptw_resp_bits_pte_v),
+ .io_ptw_status_sd(dtlb_io_ptw_status_sd),
+ .io_ptw_status_zero2(dtlb_io_ptw_status_zero2),
+ .io_ptw_status_sd_rv32(dtlb_io_ptw_status_sd_rv32),
+ .io_ptw_status_zero1(dtlb_io_ptw_status_zero1),
+ .io_ptw_status_vm(dtlb_io_ptw_status_vm),
+ .io_ptw_status_mprv(dtlb_io_ptw_status_mprv),
+ .io_ptw_status_xs(dtlb_io_ptw_status_xs),
+ .io_ptw_status_fs(dtlb_io_ptw_status_fs),
+ .io_ptw_status_prv3(dtlb_io_ptw_status_prv3),
+ .io_ptw_status_ie3(dtlb_io_ptw_status_ie3),
+ .io_ptw_status_prv2(dtlb_io_ptw_status_prv2),
+ .io_ptw_status_ie2(dtlb_io_ptw_status_ie2),
+ .io_ptw_status_prv1(dtlb_io_ptw_status_prv1),
+ .io_ptw_status_ie1(dtlb_io_ptw_status_ie1),
+ .io_ptw_status_prv(dtlb_io_ptw_status_prv),
+ .io_ptw_status_ie(dtlb_io_ptw_status_ie),
+ .io_ptw_invalidate(dtlb_io_ptw_invalidate)
+ );
+ MetadataArray meta (
+ .clk(meta_clk),
+ .reset(meta_reset),
+ .io_read_ready(meta_io_read_ready),
+ .io_read_valid(meta_io_read_valid),
+ .io_read_bits_idx(meta_io_read_bits_idx),
+ .io_write_ready(meta_io_write_ready),
+ .io_write_valid(meta_io_write_valid),
+ .io_write_bits_idx(meta_io_write_bits_idx),
+ .io_write_bits_way_en(meta_io_write_bits_way_en),
+ .io_write_bits_data_tag(meta_io_write_bits_data_tag),
+ .io_write_bits_data_coh_state(meta_io_write_bits_data_coh_state),
+ .io_resp_0_tag(meta_io_resp_0_tag),
+ .io_resp_0_coh_state(meta_io_resp_0_coh_state),
+ .io_resp_1_tag(meta_io_resp_1_tag),
+ .io_resp_1_coh_state(meta_io_resp_1_coh_state),
+ .io_resp_2_tag(meta_io_resp_2_tag),
+ .io_resp_2_coh_state(meta_io_resp_2_coh_state),
+ .io_resp_3_tag(meta_io_resp_3_tag),
+ .io_resp_3_coh_state(meta_io_resp_3_coh_state)
+ );
+ Arbiter_105 metaReadArb (
+ .clk(metaReadArb_clk),
+ .reset(metaReadArb_reset),
+ .io_in_0_ready(metaReadArb_io_in_0_ready),
+ .io_in_0_valid(metaReadArb_io_in_0_valid),
+ .io_in_0_bits_idx(metaReadArb_io_in_0_bits_idx),
+ .io_in_1_ready(metaReadArb_io_in_1_ready),
+ .io_in_1_valid(metaReadArb_io_in_1_valid),
+ .io_in_1_bits_idx(metaReadArb_io_in_1_bits_idx),
+ .io_in_2_ready(metaReadArb_io_in_2_ready),
+ .io_in_2_valid(metaReadArb_io_in_2_valid),
+ .io_in_2_bits_idx(metaReadArb_io_in_2_bits_idx),
+ .io_in_3_ready(metaReadArb_io_in_3_ready),
+ .io_in_3_valid(metaReadArb_io_in_3_valid),
+ .io_in_3_bits_idx(metaReadArb_io_in_3_bits_idx),
+ .io_in_4_ready(metaReadArb_io_in_4_ready),
+ .io_in_4_valid(metaReadArb_io_in_4_valid),
+ .io_in_4_bits_idx(metaReadArb_io_in_4_bits_idx),
+ .io_out_ready(metaReadArb_io_out_ready),
+ .io_out_valid(metaReadArb_io_out_valid),
+ .io_out_bits_idx(metaReadArb_io_out_bits_idx),
+ .io_chosen(metaReadArb_io_chosen)
+ );
+ Arbiter_94 metaWriteArb (
+ .clk(metaWriteArb_clk),
+ .reset(metaWriteArb_reset),
+ .io_in_0_ready(metaWriteArb_io_in_0_ready),
+ .io_in_0_valid(metaWriteArb_io_in_0_valid),
+ .io_in_0_bits_idx(metaWriteArb_io_in_0_bits_idx),
+ .io_in_0_bits_way_en(metaWriteArb_io_in_0_bits_way_en),
+ .io_in_0_bits_data_tag(metaWriteArb_io_in_0_bits_data_tag),
+ .io_in_0_bits_data_coh_state(metaWriteArb_io_in_0_bits_data_coh_state),
+ .io_in_1_ready(metaWriteArb_io_in_1_ready),
+ .io_in_1_valid(metaWriteArb_io_in_1_valid),
+ .io_in_1_bits_idx(metaWriteArb_io_in_1_bits_idx),
+ .io_in_1_bits_way_en(metaWriteArb_io_in_1_bits_way_en),
+ .io_in_1_bits_data_tag(metaWriteArb_io_in_1_bits_data_tag),
+ .io_in_1_bits_data_coh_state(metaWriteArb_io_in_1_bits_data_coh_state),
+ .io_out_ready(metaWriteArb_io_out_ready),
+ .io_out_valid(metaWriteArb_io_out_valid),
+ .io_out_bits_idx(metaWriteArb_io_out_bits_idx),
+ .io_out_bits_way_en(metaWriteArb_io_out_bits_way_en),
+ .io_out_bits_data_tag(metaWriteArb_io_out_bits_data_tag),
+ .io_out_bits_data_coh_state(metaWriteArb_io_out_bits_data_coh_state),
+ .io_chosen(metaWriteArb_io_chosen)
+ );
+ DataArray data (
+ .clk(data_clk),
+ .reset(data_reset),
+ .io_read_ready(data_io_read_ready),
+ .io_read_valid(data_io_read_valid),
+ .io_read_bits_way_en(data_io_read_bits_way_en),
+ .io_read_bits_addr(data_io_read_bits_addr),
+ .io_write_ready(data_io_write_ready),
+ .io_write_valid(data_io_write_valid),
+ .io_write_bits_way_en(data_io_write_bits_way_en),
+ .io_write_bits_addr(data_io_write_bits_addr),
+ .io_write_bits_wmask(data_io_write_bits_wmask),
+ .io_write_bits_data(data_io_write_bits_data),
+ .io_resp_0(data_io_resp_0),
+ .io_resp_1(data_io_resp_1),
+ .io_resp_2(data_io_resp_2),
+ .io_resp_3(data_io_resp_3)
+ );
+ Arbiter_107 readArb (
+ .clk(readArb_clk),
+ .reset(readArb_reset),
+ .io_in_0_ready(readArb_io_in_0_ready),
+ .io_in_0_valid(readArb_io_in_0_valid),
+ .io_in_0_bits_way_en(readArb_io_in_0_bits_way_en),
+ .io_in_0_bits_addr(readArb_io_in_0_bits_addr),
+ .io_in_1_ready(readArb_io_in_1_ready),
+ .io_in_1_valid(readArb_io_in_1_valid),
+ .io_in_1_bits_way_en(readArb_io_in_1_bits_way_en),
+ .io_in_1_bits_addr(readArb_io_in_1_bits_addr),
+ .io_in_2_ready(readArb_io_in_2_ready),
+ .io_in_2_valid(readArb_io_in_2_valid),
+ .io_in_2_bits_way_en(readArb_io_in_2_bits_way_en),
+ .io_in_2_bits_addr(readArb_io_in_2_bits_addr),
+ .io_in_3_ready(readArb_io_in_3_ready),
+ .io_in_3_valid(readArb_io_in_3_valid),
+ .io_in_3_bits_way_en(readArb_io_in_3_bits_way_en),
+ .io_in_3_bits_addr(readArb_io_in_3_bits_addr),
+ .io_out_ready(readArb_io_out_ready),
+ .io_out_valid(readArb_io_out_valid),
+ .io_out_bits_way_en(readArb_io_out_bits_way_en),
+ .io_out_bits_addr(readArb_io_out_bits_addr),
+ .io_chosen(readArb_io_chosen)
+ );
+ Arbiter_108 writeArb (
+ .clk(writeArb_clk),
+ .reset(writeArb_reset),
+ .io_in_0_ready(writeArb_io_in_0_ready),
+ .io_in_0_valid(writeArb_io_in_0_valid),
+ .io_in_0_bits_way_en(writeArb_io_in_0_bits_way_en),
+ .io_in_0_bits_addr(writeArb_io_in_0_bits_addr),
+ .io_in_0_bits_wmask(writeArb_io_in_0_bits_wmask),
+ .io_in_0_bits_data(writeArb_io_in_0_bits_data),
+ .io_in_1_ready(writeArb_io_in_1_ready),
+ .io_in_1_valid(writeArb_io_in_1_valid),
+ .io_in_1_bits_way_en(writeArb_io_in_1_bits_way_en),
+ .io_in_1_bits_addr(writeArb_io_in_1_bits_addr),
+ .io_in_1_bits_wmask(writeArb_io_in_1_bits_wmask),
+ .io_in_1_bits_data(writeArb_io_in_1_bits_data),
+ .io_out_ready(writeArb_io_out_ready),
+ .io_out_valid(writeArb_io_out_valid),
+ .io_out_bits_way_en(writeArb_io_out_bits_way_en),
+ .io_out_bits_addr(writeArb_io_out_bits_addr),
+ .io_out_bits_wmask(writeArb_io_out_bits_wmask),
+ .io_out_bits_data(writeArb_io_out_bits_data),
+ .io_chosen(writeArb_io_chosen)
+ );
+ AMOALU amoalu (
+ .clk(amoalu_clk),
+ .reset(amoalu_reset),
+ .io_addr(amoalu_io_addr),
+ .io_cmd(amoalu_io_cmd),
+ .io_typ(amoalu_io_typ),
+ .io_lhs(amoalu_io_lhs),
+ .io_rhs(amoalu_io_rhs),
+ .io_out(amoalu_io_out)
+ );
+ LockingArbiter_109 releaseArb (
+ .clk(releaseArb_clk),
+ .reset(releaseArb_reset),
+ .io_in_0_ready(releaseArb_io_in_0_ready),
+ .io_in_0_valid(releaseArb_io_in_0_valid),
+ .io_in_0_bits_addr_beat(releaseArb_io_in_0_bits_addr_beat),
+ .io_in_0_bits_addr_block(releaseArb_io_in_0_bits_addr_block),
+ .io_in_0_bits_client_xact_id(releaseArb_io_in_0_bits_client_xact_id),
+ .io_in_0_bits_voluntary(releaseArb_io_in_0_bits_voluntary),
+ .io_in_0_bits_r_type(releaseArb_io_in_0_bits_r_type),
+ .io_in_0_bits_data(releaseArb_io_in_0_bits_data),
+ .io_in_1_ready(releaseArb_io_in_1_ready),
+ .io_in_1_valid(releaseArb_io_in_1_valid),
+ .io_in_1_bits_addr_beat(releaseArb_io_in_1_bits_addr_beat),
+ .io_in_1_bits_addr_block(releaseArb_io_in_1_bits_addr_block),
+ .io_in_1_bits_client_xact_id(releaseArb_io_in_1_bits_client_xact_id),
+ .io_in_1_bits_voluntary(releaseArb_io_in_1_bits_voluntary),
+ .io_in_1_bits_r_type(releaseArb_io_in_1_bits_r_type),
+ .io_in_1_bits_data(releaseArb_io_in_1_bits_data),
+ .io_out_ready(releaseArb_io_out_ready),
+ .io_out_valid(releaseArb_io_out_valid),
+ .io_out_bits_addr_beat(releaseArb_io_out_bits_addr_beat),
+ .io_out_bits_addr_block(releaseArb_io_out_bits_addr_block),
+ .io_out_bits_client_xact_id(releaseArb_io_out_bits_client_xact_id),
+ .io_out_bits_voluntary(releaseArb_io_out_bits_voluntary),
+ .io_out_bits_r_type(releaseArb_io_out_bits_r_type),
+ .io_out_bits_data(releaseArb_io_out_bits_data),
+ .io_chosen(releaseArb_io_chosen)
+ );
+ FlowThroughSerializer T_4171 (
+ .clk(T_4171_clk),
+ .reset(T_4171_reset),
+ .io_in_ready(T_4171_io_in_ready),
+ .io_in_valid(T_4171_io_in_valid),
+ .io_in_bits_addr_beat(T_4171_io_in_bits_addr_beat),
+ .io_in_bits_client_xact_id(T_4171_io_in_bits_client_xact_id),
+ .io_in_bits_manager_xact_id(T_4171_io_in_bits_manager_xact_id),
+ .io_in_bits_is_builtin_type(T_4171_io_in_bits_is_builtin_type),
+ .io_in_bits_g_type(T_4171_io_in_bits_g_type),
+ .io_in_bits_data(T_4171_io_in_bits_data),
+ .io_out_ready(T_4171_io_out_ready),
+ .io_out_valid(T_4171_io_out_valid),
+ .io_out_bits_addr_beat(T_4171_io_out_bits_addr_beat),
+ .io_out_bits_client_xact_id(T_4171_io_out_bits_client_xact_id),
+ .io_out_bits_manager_xact_id(T_4171_io_out_bits_manager_xact_id),
+ .io_out_bits_is_builtin_type(T_4171_io_out_bits_is_builtin_type),
+ .io_out_bits_g_type(T_4171_io_out_bits_g_type),
+ .io_out_bits_data(T_4171_io_out_bits_data),
+ .io_cnt(T_4171_io_cnt),
+ .io_done(T_4171_io_done)
+ );
+ Arbiter_95 wbArb (
+ .clk(wbArb_clk),
+ .reset(wbArb_reset),
+ .io_in_0_ready(wbArb_io_in_0_ready),
+ .io_in_0_valid(wbArb_io_in_0_valid),
+ .io_in_0_bits_addr_beat(wbArb_io_in_0_bits_addr_beat),
+ .io_in_0_bits_addr_block(wbArb_io_in_0_bits_addr_block),
+ .io_in_0_bits_client_xact_id(wbArb_io_in_0_bits_client_xact_id),
+ .io_in_0_bits_voluntary(wbArb_io_in_0_bits_voluntary),
+ .io_in_0_bits_r_type(wbArb_io_in_0_bits_r_type),
+ .io_in_0_bits_data(wbArb_io_in_0_bits_data),
+ .io_in_0_bits_way_en(wbArb_io_in_0_bits_way_en),
+ .io_in_1_ready(wbArb_io_in_1_ready),
+ .io_in_1_valid(wbArb_io_in_1_valid),
+ .io_in_1_bits_addr_beat(wbArb_io_in_1_bits_addr_beat),
+ .io_in_1_bits_addr_block(wbArb_io_in_1_bits_addr_block),
+ .io_in_1_bits_client_xact_id(wbArb_io_in_1_bits_client_xact_id),
+ .io_in_1_bits_voluntary(wbArb_io_in_1_bits_voluntary),
+ .io_in_1_bits_r_type(wbArb_io_in_1_bits_r_type),
+ .io_in_1_bits_data(wbArb_io_in_1_bits_data),
+ .io_in_1_bits_way_en(wbArb_io_in_1_bits_way_en),
+ .io_out_ready(wbArb_io_out_ready),
+ .io_out_valid(wbArb_io_out_valid),
+ .io_out_bits_addr_beat(wbArb_io_out_bits_addr_beat),
+ .io_out_bits_addr_block(wbArb_io_out_bits_addr_block),
+ .io_out_bits_client_xact_id(wbArb_io_out_bits_client_xact_id),
+ .io_out_bits_voluntary(wbArb_io_out_bits_voluntary),
+ .io_out_bits_r_type(wbArb_io_out_bits_r_type),
+ .io_out_bits_data(wbArb_io_out_bits_data),
+ .io_out_bits_way_en(wbArb_io_out_bits_way_en),
+ .io_chosen(wbArb_io_chosen)
+ );
+ assign io_cpu_req_ready = block_miss ? 1'h0 : T_2156 ? 1'h0 : T_2151 ? 1'h0 : T_1845 ? 1'h0 : 1'h1;
+ assign io_cpu_resp_valid = T_5067_valid;
+ assign io_cpu_resp_bits_addr = T_5067_bits_addr;
+ assign io_cpu_resp_bits_tag = T_5067_bits_tag;
+ assign io_cpu_resp_bits_cmd = T_5067_bits_cmd;
+ assign io_cpu_resp_bits_typ = T_5067_bits_typ;
+ assign io_cpu_resp_bits_data = T_5067_bits_data;
+ assign io_cpu_resp_bits_nack = T_5067_bits_nack;
+ assign io_cpu_resp_bits_replay = T_5067_bits_replay;
+ assign io_cpu_resp_bits_has_data = T_5067_bits_has_data;
+ assign io_cpu_resp_bits_data_word_bypass = T_5201;
+ assign io_cpu_resp_bits_store_data = T_5067_bits_store_data;
+ assign io_cpu_replay_next_valid = T_5208;
+ assign io_cpu_replay_next_bits = s1_req_tag;
+ assign io_cpu_xcpt_ma_ld = T_1867;
+ assign io_cpu_xcpt_ma_st = T_1868;
+ assign io_cpu_xcpt_pf_ld = T_1869;
+ assign io_cpu_xcpt_pf_st = T_1870;
+ assign io_cpu_ordered = T_5207;
+ assign io_ptw_req_valid = dtlb_io_ptw_req_valid;
+ assign io_ptw_req_bits_addr = dtlb_io_ptw_req_bits_addr;
+ assign io_ptw_req_bits_prv = dtlb_io_ptw_req_bits_prv;
+ assign io_ptw_req_bits_store = dtlb_io_ptw_req_bits_store;
+ assign io_ptw_req_bits_fetch = dtlb_io_ptw_req_bits_fetch;
+ assign io_mem_acquire_valid = mshrs_io_mem_req_valid;
+ assign io_mem_acquire_bits_addr_block = mshrs_io_mem_req_bits_addr_block;
+ assign io_mem_acquire_bits_client_xact_id = mshrs_io_mem_req_bits_client_xact_id;
+ assign io_mem_acquire_bits_addr_beat = mshrs_io_mem_req_bits_addr_beat;
+ assign io_mem_acquire_bits_is_builtin_type = mshrs_io_mem_req_bits_is_builtin_type;
+ assign io_mem_acquire_bits_a_type = mshrs_io_mem_req_bits_a_type;
+ assign io_mem_acquire_bits_union = mshrs_io_mem_req_bits_union;
+ assign io_mem_acquire_bits_data = mshrs_io_mem_req_bits_data;
+ assign io_mem_grant_ready = T_4171_io_in_ready;
+ assign io_mem_probe_ready = T_4170;
+ assign io_mem_release_valid = releaseArb_io_out_valid;
+ assign io_mem_release_bits_addr_beat = releaseArb_io_out_bits_addr_beat;
+ assign io_mem_release_bits_addr_block = releaseArb_io_out_bits_addr_block;
+ assign io_mem_release_bits_client_xact_id = releaseArb_io_out_bits_client_xact_id;
+ assign io_mem_release_bits_voluntary = releaseArb_io_out_bits_voluntary;
+ assign io_mem_release_bits_r_type = releaseArb_io_out_bits_r_type;
+ assign io_mem_release_bits_data = releaseArb_io_out_bits_data;
+ assign wb_clk = clk;
+ assign wb_reset = reset;
+ assign wb_io_req_valid = wbArb_io_out_valid;
+ assign wb_io_req_bits_addr_beat = wbArb_io_out_bits_addr_beat;
+ assign wb_io_req_bits_addr_block = wbArb_io_out_bits_addr_block;
+ assign wb_io_req_bits_client_xact_id = wbArb_io_out_bits_client_xact_id;
+ assign wb_io_req_bits_voluntary = wbArb_io_out_bits_voluntary;
+ assign wb_io_req_bits_r_type = wbArb_io_out_bits_r_type;
+ assign wb_io_req_bits_data = wbArb_io_out_bits_data;
+ assign wb_io_req_bits_way_en = wbArb_io_out_bits_way_en;
+ assign wb_io_meta_read_ready = metaReadArb_io_in_3_ready;
+ assign wb_io_data_req_ready = readArb_io_in_2_ready;
+ assign wb_io_data_resp = s2_data_corrected;
+ assign wb_io_release_ready = releaseArb_io_in_0_ready;
+ assign prober_clk = clk;
+ assign prober_reset = reset;
+ assign prober_io_req_valid = T_4167;
+ assign prober_io_req_bits_addr_block = io_mem_probe_bits_addr_block;
+ assign prober_io_req_bits_p_type = io_mem_probe_bits_p_type;
+ assign prober_io_req_bits_client_xact_id = GEN_2;
+ assign prober_io_rep_ready = releaseArb_io_in_1_ready;
+ assign prober_io_meta_read_ready = metaReadArb_io_in_2_ready;
+ assign prober_io_meta_write_ready = metaWriteArb_io_in_1_ready;
+ assign prober_io_wb_req_ready = wbArb_io_in_0_ready;
+ assign prober_io_way_en = s2_tag_match_way;
+ assign prober_io_mshr_rdy = mshrs_io_probe_rdy;
+ assign prober_io_block_state_state = s2_hit_state_state;
+ assign mshrs_clk = clk;
+ assign mshrs_reset = reset;
+ assign mshrs_io_req_valid = s2_nack_hit ? 1'h0 : T_3908;
+ assign mshrs_io_req_bits_addr = s2_req_addr;
+ assign mshrs_io_req_bits_tag = s2_req_tag;
+ assign mshrs_io_req_bits_cmd = s2_req_cmd;
+ assign mshrs_io_req_bits_typ = s2_req_typ;
+ assign mshrs_io_req_bits_kill = s2_req_kill;
+ assign mshrs_io_req_bits_phys = s2_req_phys;
+ assign mshrs_io_req_bits_data = s2_req_data;
+ assign mshrs_io_req_bits_tag_match = s2_tag_match;
+ assign mshrs_io_req_bits_old_meta_tag = T_4055_tag;
+ assign mshrs_io_req_bits_old_meta_coh_state = T_4055_coh_state;
+ assign mshrs_io_req_bits_way_en = T_4128;
+ assign mshrs_io_resp_ready = T_5066;
+ assign mshrs_io_mem_req_ready = io_mem_acquire_ready;
+ assign mshrs_io_meta_read_ready = metaReadArb_io_in_1_ready;
+ assign mshrs_io_meta_write_ready = metaWriteArb_io_in_0_ready;
+ assign mshrs_io_replay_ready = readArb_io_in_1_ready;
+ assign mshrs_io_mem_grant_valid = T_4172;
+ assign mshrs_io_mem_grant_bits_addr_beat = T_4171_io_out_bits_addr_beat;
+ assign mshrs_io_mem_grant_bits_client_xact_id = T_4171_io_out_bits_client_xact_id;
+ assign mshrs_io_mem_grant_bits_manager_xact_id = T_4171_io_out_bits_manager_xact_id;
+ assign mshrs_io_mem_grant_bits_is_builtin_type = T_4171_io_out_bits_is_builtin_type;
+ assign mshrs_io_mem_grant_bits_g_type = T_4171_io_out_bits_g_type;
+ assign mshrs_io_mem_grant_bits_data = T_4171_io_out_bits_data;
+ assign mshrs_io_wb_req_ready = wbArb_io_in_1_ready;
+ assign T_1622 = io_cpu_req_ready & io_cpu_req_valid;
+ assign T_1680 = io_cpu_req_bits_kill == 1'h0;
+ assign s1_valid_masked = s1_valid & T_1680;
+ assign T_1688 = s1_valid & io_cpu_req_bits_kill;
+ assign T_1746 = s2_req_cmd != 5'h5;
+ assign s2_replay = T_1745 & T_1746;
+ assign s2_recycle = T_4406;
+ assign s2_valid_masked = T_4399;
+ assign T_1812 = s1_req_cmd == 5'h0;
+ assign T_1813 = s1_req_cmd == 5'h6;
+ assign T_1814 = T_1812 | T_1813;
+ assign T_1815 = s1_req_cmd == 5'h7;
+ assign T_1816 = T_1814 | T_1815;
+ assign T_1817 = s1_req_cmd[3];
+ assign T_1818 = s1_req_cmd == 5'h4;
+ assign T_1819 = T_1817 | T_1818;
+ assign s1_read = T_1816 | T_1819;
+ assign T_1821 = s1_req_cmd == 5'h1;
+ assign T_1822 = s1_req_cmd == 5'h7;
+ assign T_1823 = T_1821 | T_1822;
+ assign T_1824 = s1_req_cmd[3];
+ assign T_1825 = s1_req_cmd == 5'h4;
+ assign T_1826 = T_1824 | T_1825;
+ assign s1_write = T_1823 | T_1826;
+ assign T_1828 = s1_read | s1_write;
+ assign T_1829 = s1_req_cmd == 5'h2;
+ assign T_1830 = s1_req_cmd == 5'h3;
+ assign T_1831 = T_1829 | T_1830;
+ assign s1_readwrite = T_1828 | T_1831;
+ assign dtlb_clk = clk;
+ assign dtlb_reset = reset;
+ assign dtlb_io_req_valid = T_1837;
+ assign dtlb_io_req_bits_asid = 1'h0;
+ assign dtlb_io_req_bits_vpn = T_1839;
+ assign dtlb_io_req_bits_passthrough = s1_req_phys;
+ assign dtlb_io_req_bits_instruction = 1'h0;
+ assign dtlb_io_req_bits_store = s1_write;
+ assign dtlb_io_ptw_req_ready = io_ptw_req_ready;
+ assign dtlb_io_ptw_resp_valid = io_ptw_resp_valid;
+ assign dtlb_io_ptw_resp_bits_error = io_ptw_resp_bits_error;
+ assign dtlb_io_ptw_resp_bits_pte_ppn = io_ptw_resp_bits_pte_ppn;
+ assign dtlb_io_ptw_resp_bits_pte_reserved_for_software = io_ptw_resp_bits_pte_reserved_for_software;
+ assign dtlb_io_ptw_resp_bits_pte_d = io_ptw_resp_bits_pte_d;
+ assign dtlb_io_ptw_resp_bits_pte_r = io_ptw_resp_bits_pte_r;
+ assign dtlb_io_ptw_resp_bits_pte_typ = io_ptw_resp_bits_pte_typ;
+ assign dtlb_io_ptw_resp_bits_pte_v = io_ptw_resp_bits_pte_v;
+ assign dtlb_io_ptw_status_sd = io_ptw_status_sd;
+ assign dtlb_io_ptw_status_zero2 = io_ptw_status_zero2;
+ assign dtlb_io_ptw_status_sd_rv32 = io_ptw_status_sd_rv32;
+ assign dtlb_io_ptw_status_zero1 = io_ptw_status_zero1;
+ assign dtlb_io_ptw_status_vm = io_ptw_status_vm;
+ assign dtlb_io_ptw_status_mprv = io_ptw_status_mprv;
+ assign dtlb_io_ptw_status_xs = io_ptw_status_xs;
+ assign dtlb_io_ptw_status_fs = io_ptw_status_fs;
+ assign dtlb_io_ptw_status_prv3 = io_ptw_status_prv3;
+ assign dtlb_io_ptw_status_ie3 = io_ptw_status_ie3;
+ assign dtlb_io_ptw_status_prv2 = io_ptw_status_prv2;
+ assign dtlb_io_ptw_status_ie2 = io_ptw_status_ie2;
+ assign dtlb_io_ptw_status_prv1 = io_ptw_status_prv1;
+ assign dtlb_io_ptw_status_ie1 = io_ptw_status_ie1;
+ assign dtlb_io_ptw_status_prv = io_ptw_status_prv;
+ assign dtlb_io_ptw_status_ie = io_ptw_status_ie;
+ assign dtlb_io_ptw_invalidate = io_ptw_invalidate;
+ assign T_1834 = s1_valid_masked & s1_readwrite;
+ assign T_1836 = s1_req_phys == 1'h0;
+ assign T_1837 = T_1834 & T_1836;
+ assign T_1839 = s1_req_addr[39:12];
+ assign T_1842 = dtlb_io_req_ready == 1'h0;
+ assign T_1844 = io_cpu_req_bits_phys == 1'h0;
+ assign T_1845 = T_1842 & T_1844;
+ assign T_1847 = {wb_io_meta_read_bits_tag,wb_io_meta_read_bits_idx};
+ assign T_1848 = T_1847 << 6;
+ assign T_1850 = {prober_io_meta_read_bits_tag,prober_io_meta_read_bits_idx};
+ assign T_1851 = T_1850 << 6;
+ assign T_1853 = s1_req_addr[11:0];
+ assign s1_addr = {dtlb_io_resp_ppn,T_1853};
+ assign T_1855 = s1_replay ? mshrs_io_replay_bits_data : io_cpu_req_bits_data;
+ assign T_1857 = s1_req_typ[1:0];
+ assign T_1859 = 1'h1 << T_1857;
+ assign T_1861 = T_1859 - 1'h1;
+ assign T_1862 = T_1861[3:0];
+ assign T_1863 = T_1862[2:0];
+ assign T_1864 = s1_req_addr & T_1863;
+ assign misaligned = T_1864 != 1'h0;
+ assign T_1867 = s1_read & misaligned;
+ assign T_1868 = s1_write & misaligned;
+ assign T_1869 = s1_read & dtlb_io_resp_xcpt_ld;
+ assign T_1870 = s1_write & dtlb_io_resp_xcpt_st;
+ assign T_1871 = io_cpu_xcpt_ma_ld | io_cpu_xcpt_ma_st;
+ assign T_1872 = T_1871 | io_cpu_xcpt_pf_ld;
+ assign T_1873 = T_1872 | io_cpu_xcpt_pf_st;
+ assign T_1875 = T_1874 & io_cpu_resp_valid;
+ assign T_1877 = T_1875 == 1'h0;
+ assign T_1879 = reset == 1'h0;
+ assign T_1881 = T_1877 == 1'h0;
+ assign T_1883 = reset == 1'h0;
+ assign meta_clk = clk;
+ assign meta_reset = reset;
+ assign meta_io_read_valid = metaReadArb_io_out_valid;
+ assign meta_io_read_bits_idx = metaReadArb_io_out_bits_idx;
+ assign meta_io_write_valid = metaWriteArb_io_out_valid;
+ assign meta_io_write_bits_idx = metaWriteArb_io_out_bits_idx;
+ assign meta_io_write_bits_way_en = metaWriteArb_io_out_bits_way_en;
+ assign meta_io_write_bits_data_tag = metaWriteArb_io_out_bits_data_tag;
+ assign meta_io_write_bits_data_coh_state = metaWriteArb_io_out_bits_data_coh_state;
+ assign metaReadArb_clk = clk;
+ assign metaReadArb_reset = reset;
+ assign metaReadArb_io_in_0_valid = s2_recycle;
+ assign metaReadArb_io_in_0_bits_idx = T_2158;
+ assign metaReadArb_io_in_1_valid = mshrs_io_meta_read_valid;
+ assign metaReadArb_io_in_1_bits_idx = mshrs_io_meta_read_bits_idx;
+ assign metaReadArb_io_in_2_valid = prober_io_meta_read_valid;
+ assign metaReadArb_io_in_2_bits_idx = prober_io_meta_read_bits_idx;
+ assign metaReadArb_io_in_3_valid = wb_io_meta_read_valid;
+ assign metaReadArb_io_in_3_bits_idx = wb_io_meta_read_bits_idx;
+ assign metaReadArb_io_in_4_valid = io_cpu_req_valid;
+ assign metaReadArb_io_in_4_bits_idx = T_2149;
+ assign metaReadArb_io_out_ready = meta_io_read_ready;
+ assign metaWriteArb_clk = clk;
+ assign metaWriteArb_reset = reset;
+ assign metaWriteArb_io_in_0_valid = mshrs_io_meta_write_valid;
+ assign metaWriteArb_io_in_0_bits_idx = mshrs_io_meta_write_bits_idx;
+ assign metaWriteArb_io_in_0_bits_way_en = mshrs_io_meta_write_bits_way_en;
+ assign metaWriteArb_io_in_0_bits_data_tag = mshrs_io_meta_write_bits_data_tag;
+ assign metaWriteArb_io_in_0_bits_data_coh_state = mshrs_io_meta_write_bits_data_coh_state;
+ assign metaWriteArb_io_in_1_valid = prober_io_meta_write_valid;
+ assign metaWriteArb_io_in_1_bits_idx = prober_io_meta_write_bits_idx;
+ assign metaWriteArb_io_in_1_bits_way_en = prober_io_meta_write_bits_way_en;
+ assign metaWriteArb_io_in_1_bits_data_tag = prober_io_meta_write_bits_data_tag;
+ assign metaWriteArb_io_in_1_bits_data_coh_state = prober_io_meta_write_bits_data_coh_state;
+ assign metaWriteArb_io_out_ready = meta_io_write_ready;
+ assign data_clk = clk;
+ assign data_reset = reset;
+ assign data_io_read_valid = readArb_io_out_valid;
+ assign data_io_read_bits_way_en = readArb_io_out_bits_way_en;
+ assign data_io_read_bits_addr = readArb_io_out_bits_addr;
+ assign data_io_write_valid = writeArb_io_out_valid;
+ assign data_io_write_bits_way_en = writeArb_io_out_bits_way_en;
+ assign data_io_write_bits_addr = writeArb_io_out_bits_addr;
+ assign data_io_write_bits_wmask = writeArb_io_out_bits_wmask;
+ assign data_io_write_bits_data = T_2148;
+ assign readArb_clk = clk;
+ assign readArb_reset = reset;
+ assign readArb_io_in_0_valid = s2_recycle;
+ assign readArb_io_in_0_bits_way_en = T_2160;
+ assign readArb_io_in_0_bits_addr = s2_req_addr;
+ assign readArb_io_in_1_valid = mshrs_io_replay_valid;
+ assign readArb_io_in_1_bits_way_en = T_4132;
+ assign readArb_io_in_1_bits_addr = mshrs_io_replay_bits_addr;
+ assign readArb_io_in_2_valid = wb_io_data_req_valid;
+ assign readArb_io_in_2_bits_way_en = wb_io_data_req_bits_way_en;
+ assign readArb_io_in_2_bits_addr = wb_io_data_req_bits_addr;
+ assign readArb_io_in_3_valid = io_cpu_req_valid;
+ assign readArb_io_in_3_bits_way_en = T_2154;
+ assign readArb_io_in_3_bits_addr = io_cpu_req_bits_addr;
+ assign readArb_io_out_ready = T_4231;
+ assign writeArb_clk = clk;
+ assign writeArb_reset = reset;
+ assign writeArb_io_in_0_valid = s3_valid;
+ assign writeArb_io_in_0_bits_way_en = s3_way;
+ assign writeArb_io_in_0_bits_addr = s3_req_addr;
+ assign writeArb_io_in_0_bits_wmask = rowWMask;
+ assign writeArb_io_in_0_bits_data = T_2883;
+ assign writeArb_io_in_1_valid = T_4225;
+ assign writeArb_io_in_1_bits_way_en = mshrs_io_refill_way_en;
+ assign writeArb_io_in_1_bits_addr = mshrs_io_refill_addr;
+ assign writeArb_io_in_1_bits_wmask = T_4227;
+ assign writeArb_io_in_1_bits_data = T_4228;
+ assign writeArb_io_out_ready = data_io_write_ready;
+ assign T_2141 = writeArb_io_out_bits_data[63:0];
+ assign T_2142 = writeArb_io_out_bits_data[127:64];
+ assign T_2144_0 = T_2141;
+ assign T_2144_1 = T_2142;
+ assign T_2148 = {T_2144_1,T_2144_0};
+ assign T_2149 = io_cpu_req_bits_addr[39:6];
+ assign T_2151 = metaReadArb_io_in_4_ready == 1'h0;
+ assign T_2154 = ~ 4'h0;
+ assign T_2156 = readArb_io_in_3_ready == 1'h0;
+ assign T_2158 = s2_req_addr[39:6];
+ assign T_2160 = ~ 4'h0;
+ assign T_2161 = s1_addr[31:12];
+ assign T_2162 = meta_io_resp_0_tag == T_2161;
+ assign T_2163 = s1_addr[31:12];
+ assign T_2164 = meta_io_resp_1_tag == T_2163;
+ assign T_2165 = s1_addr[31:12];
+ assign T_2166 = meta_io_resp_2_tag == T_2165;
+ assign T_2167 = s1_addr[31:12];
+ assign T_2168 = meta_io_resp_3_tag == T_2167;
+ assign T_2170_0 = T_2162;
+ assign T_2170_1 = T_2164;
+ assign T_2170_2 = T_2166;
+ assign T_2170_3 = T_2168;
+ assign T_2176 = {T_2170_3,T_2170_2};
+ assign T_2177 = {T_2170_1,T_2170_0};
+ assign s1_tag_eq_way = {T_2176,T_2177};
+ assign T_2179 = s1_tag_eq_way[0];
+ assign T_2180 = meta_io_resp_0_coh_state != 1'h0;
+ assign T_2181 = T_2179 & T_2180;
+ assign T_2182 = s1_tag_eq_way[1];
+ assign T_2183 = meta_io_resp_1_coh_state != 1'h0;
+ assign T_2184 = T_2182 & T_2183;
+ assign T_2185 = s1_tag_eq_way[2];
+ assign T_2186 = meta_io_resp_2_coh_state != 1'h0;
+ assign T_2187 = T_2185 & T_2186;
+ assign T_2188 = s1_tag_eq_way[3];
+ assign T_2189 = meta_io_resp_3_coh_state != 1'h0;
+ assign T_2190 = T_2188 & T_2189;
+ assign T_2192_0 = T_2181;
+ assign T_2192_1 = T_2184;
+ assign T_2192_2 = T_2187;
+ assign T_2192_3 = T_2190;
+ assign T_2198 = {T_2192_3,T_2192_2};
+ assign T_2199 = {T_2192_1,T_2192_0};
+ assign s1_tag_match_way = {T_2198,T_2199};
+ assign T_2202 = s1_valid == 1'h0;
+ assign T_2203 = s1_clk_en & T_2202;
+ assign T_2205 = s1_replay == 1'h0;
+ assign s1_writeback = T_2203 & T_2205;
+ assign s2_tag_match = s2_tag_match_way != 1'h0;
+ assign T_2335_0_state = T_2210_state;
+ assign T_2335_1_state = T_2235_state;
+ assign T_2335_2_state = T_2260_state;
+ assign T_2335_3_state = T_2285_state;
+ assign T_2461 = s2_tag_match_way[0];
+ assign T_2462 = s2_tag_match_way[1];
+ assign T_2463 = s2_tag_match_way[2];
+ assign T_2464 = s2_tag_match_way[3];
+ assign T_2466 = T_2461 ? T_2335_0_state : 1'h0;
+ assign T_2468 = T_2462 ? T_2335_1_state : 1'h0;
+ assign T_2470 = T_2463 ? T_2335_2_state : 1'h0;
+ assign T_2472 = T_2464 ? T_2335_3_state : 1'h0;
+ assign T_2498 = T_2466 | T_2468;
+ assign T_2499 = T_2498 | T_2470;
+ assign T_2500 = T_2499 | T_2472;
+ assign s2_hit_state_state = T_2551;
+ assign T_2551 = T_2500;
+ assign T_2552 = s2_req_cmd == 5'h1;
+ assign T_2553 = s2_req_cmd == 5'h7;
+ assign T_2554 = T_2552 | T_2553;
+ assign T_2555 = s2_req_cmd[3];
+ assign T_2556 = s2_req_cmd == 5'h4;
+ assign T_2557 = T_2555 | T_2556;
+ assign T_2558 = T_2554 | T_2557;
+ assign T_2559 = s2_req_cmd == 5'h3;
+ assign T_2560 = T_2558 | T_2559;
+ assign T_2561 = s2_req_cmd == 5'h6;
+ assign T_2562 = T_2560 | T_2561;
+ assign T_2564_0 = 2'h2;
+ assign T_2564_1 = 2'h3;
+ assign T_2568 = T_2564_0 == s2_hit_state_state;
+ assign T_2569 = T_2564_1 == s2_hit_state_state;
+ assign T_2571 = 1'h0 | T_2568;
+ assign T_2572 = T_2571 | T_2569;
+ assign T_2574_0 = 1'h1;
+ assign T_2574_1 = 2'h2;
+ assign T_2574_2 = 2'h3;
+ assign T_2579 = T_2574_0 == s2_hit_state_state;
+ assign T_2580 = T_2574_1 == s2_hit_state_state;
+ assign T_2581 = T_2574_2 == s2_hit_state_state;
+ assign T_2583 = 1'h0 | T_2579;
+ assign T_2584 = T_2583 | T_2580;
+ assign T_2585 = T_2584 | T_2581;
+ assign T_2586 = T_2562 ? T_2572 : T_2585;
+ assign T_2587 = s2_tag_match & T_2586;
+ assign T_2588 = s2_req_cmd == 5'h1;
+ assign T_2589 = s2_req_cmd == 5'h7;
+ assign T_2590 = T_2588 | T_2589;
+ assign T_2591 = s2_req_cmd[3];
+ assign T_2592 = s2_req_cmd == 5'h4;
+ assign T_2593 = T_2591 | T_2592;
+ assign T_2594 = T_2590 | T_2593;
+ assign T_2595 = T_2594 ? 2'h3 : s2_hit_state_state;
+ assign T_2621_state = T_2595;
+ assign T_2646 = s2_hit_state_state == T_2621_state;
+ assign s2_hit = T_2587 & T_2646;
+ assign lrsc_valid = lrsc_count != 1'h0;
+ assign s2_lr = s2_req_cmd == 5'h6;
+ assign s2_sc = s2_req_cmd == 5'h7;
+ assign T_2656 = s2_req_addr[39:6];
+ assign T_2657 = lrsc_addr == T_2656;
+ assign s2_lrsc_addr_match = lrsc_valid & T_2657;
+ assign T_2660 = s2_lrsc_addr_match == 1'h0;
+ assign s2_sc_fail = s2_sc & T_2660;
+ assign T_2663 = lrsc_count - 1'h1;
+ assign T_2664 = T_2663[4:0];
+ assign T_2665 = s2_valid_masked & s2_hit;
+ assign T_2666 = T_2665 | s2_replay;
+ assign T_2668 = lrsc_valid == 1'h0;
+ assign T_2670 = s2_req_addr[39:6];
+ assign s2_data_0 = T_2719;
+ assign s2_data_1 = T_2750;
+ assign s2_data_2 = T_2781;
+ assign s2_data_3 = T_2812;
+ assign T_2701 = s1_tag_eq_way[0];
+ assign T_2702 = s1_clk_en & T_2701;
+ assign T_2706 = 1'h1 == 1'h0;
+ assign T_2707 = 1'h1 | T_2706;
+ assign T_2708 = T_2707 | s1_writeback;
+ assign T_2709 = T_2702 & T_2708;
+ assign T_2710 = data_io_resp_0[127:0];
+ assign T_2714 = 1'h1 == 1'h0;
+ assign T_2715 = 1'h0 | T_2714;
+ assign T_2716 = T_2715 | s1_writeback;
+ assign T_2717 = T_2702 & T_2716;
+ assign T_2718 = data_io_resp_0[127:64];
+ assign T_2719 = {T_2697_1,T_2697_0};
+ assign T_2732 = s1_tag_eq_way[1];
+ assign T_2733 = s1_clk_en & T_2732;
+ assign T_2737 = 1'h1 == 1'h0;
+ assign T_2738 = 1'h1 | T_2737;
+ assign T_2739 = T_2738 | s1_writeback;
+ assign T_2740 = T_2733 & T_2739;
+ assign T_2741 = data_io_resp_1[127:0];
+ assign T_2745 = 1'h1 == 1'h0;
+ assign T_2746 = 1'h0 | T_2745;
+ assign T_2747 = T_2746 | s1_writeback;
+ assign T_2748 = T_2733 & T_2747;
+ assign T_2749 = data_io_resp_1[127:64];
+ assign T_2750 = {T_2728_1,T_2728_0};
+ assign T_2763 = s1_tag_eq_way[2];
+ assign T_2764 = s1_clk_en & T_2763;
+ assign T_2768 = 1'h1 == 1'h0;
+ assign T_2769 = 1'h1 | T_2768;
+ assign T_2770 = T_2769 | s1_writeback;
+ assign T_2771 = T_2764 & T_2770;
+ assign T_2772 = data_io_resp_2[127:0];
+ assign T_2776 = 1'h1 == 1'h0;
+ assign T_2777 = 1'h0 | T_2776;
+ assign T_2778 = T_2777 | s1_writeback;
+ assign T_2779 = T_2764 & T_2778;
+ assign T_2780 = data_io_resp_2[127:64];
+ assign T_2781 = {T_2759_1,T_2759_0};
+ assign T_2794 = s1_tag_eq_way[3];
+ assign T_2795 = s1_clk_en & T_2794;
+ assign T_2799 = 1'h1 == 1'h0;
+ assign T_2800 = 1'h1 | T_2799;
+ assign T_2801 = T_2800 | s1_writeback;
+ assign T_2802 = T_2795 & T_2801;
+ assign T_2803 = data_io_resp_3[127:0];
+ assign T_2807 = 1'h1 == 1'h0;
+ assign T_2808 = 1'h0 | T_2807;
+ assign T_2809 = T_2808 | s1_writeback;
+ assign T_2810 = T_2795 & T_2809;
+ assign T_2811 = data_io_resp_3[127:64];
+ assign T_2812 = {T_2790_1,T_2790_0};
+ assign T_2813 = s2_tag_match_way[0];
+ assign T_2814 = s2_tag_match_way[1];
+ assign T_2815 = s2_tag_match_way[2];
+ assign T_2816 = s2_tag_match_way[3];
+ assign T_2818 = T_2813 ? s2_data_0 : 1'h0;
+ assign T_2820 = T_2814 ? s2_data_1 : 1'h0;
+ assign T_2822 = T_2815 ? s2_data_2 : 1'h0;
+ assign T_2824 = T_2816 ? s2_data_3 : 1'h0;
+ assign T_2826 = T_2818 | T_2820;
+ assign T_2827 = T_2826 | T_2822;
+ assign T_2828 = T_2827 | T_2824;
+ assign s2_data_muxed = T_2828;
+ assign T_2830 = s2_data_muxed[63:0];
+ assign T_2831 = s2_data_muxed[127:64];
+ assign T_2833_0 = T_2830;
+ assign T_2833_1 = T_2831;
+ assign s2_data_corrected = {T_2833_1,T_2833_0};
+ assign T_2839_0 = T_2830;
+ assign T_2839_1 = T_2831;
+ assign s2_data_uncorrected = {T_2839_1,T_2839_0};
+ assign T_2848_0 = 1'h0;
+ assign T_2848_1 = 1'h0;
+ assign T_2852 = {T_2848_1,T_2848_0};
+ assign T_2853 = T_2852 >> 1'h0;
+ assign s2_data_correctable = T_2853[0];
+ assign T_2855 = s2_valid_masked & s2_hit;
+ assign T_2856 = T_2855 | s2_replay;
+ assign T_2858 = s2_sc_fail == 1'h0;
+ assign T_2859 = T_2856 & T_2858;
+ assign T_2860 = s2_req_cmd == 5'h1;
+ assign T_2861 = s2_req_cmd == 5'h7;
+ assign T_2862 = T_2860 | T_2861;
+ assign T_2863 = s2_req_cmd[3];
+ assign T_2864 = s2_req_cmd == 5'h4;
+ assign T_2865 = T_2863 | T_2864;
+ assign T_2866 = T_2862 | T_2865;
+ assign T_2867 = T_2859 & T_2866;
+ assign amoalu_clk = clk;
+ assign amoalu_reset = reset;
+ assign amoalu_io_addr = s2_req_addr;
+ assign amoalu_io_cmd = s2_req_cmd;
+ assign amoalu_io_typ = s2_req_typ;
+ assign amoalu_io_lhs = s2_data_word;
+ assign amoalu_io_rhs = s2_req_data;
+ assign T_2869 = s2_valid | s2_replay;
+ assign T_2870 = s2_req_cmd == 5'h1;
+ assign T_2871 = s2_req_cmd == 5'h7;
+ assign T_2872 = T_2870 | T_2871;
+ assign T_2873 = s2_req_cmd[3];
+ assign T_2874 = s2_req_cmd == 5'h4;
+ assign T_2875 = T_2873 | T_2874;
+ assign T_2876 = T_2872 | T_2875;
+ assign T_2877 = T_2876 | s2_data_correctable;
+ assign T_2878 = T_2869 & T_2877;
+ assign T_2879 = s2_data_correctable ? s2_data_corrected : amoalu_io_out;
+ assign rowIdx = s3_req_addr[3];
+ assign rowWMask = 1'h1 << rowIdx;
+ assign T_2883 = {s3_req_data,s3_req_data};
+ assign T_2885 = T_4129 ? 1'h1 : 1'h0;
+ assign T_2889 = T_2888[0];
+ assign T_2890 = T_2888[2];
+ assign T_2891 = T_2889 ^ T_2890;
+ assign T_2892 = T_2888[3];
+ assign T_2893 = T_2891 ^ T_2892;
+ assign T_2894 = T_2888[5];
+ assign T_2895 = T_2893 ^ T_2894;
+ assign T_2896 = T_2888[15:1];
+ assign T_2897 = {T_2895,T_2896};
+ assign T_2898 = T_2888[1:0];
+ assign s1_replaced_way_en = 1'h1 << T_2898;
+ assign T_2901 = T_2888[1:0];
+ assign s2_replaced_way_en = 1'h1 << T_2902;
+ assign T_2905 = s1_replaced_way_en[0];
+ assign T_2906 = s1_clk_en & T_2905;
+ assign T_2980 = s1_replaced_way_en[1];
+ assign T_2981 = s1_clk_en & T_2980;
+ assign T_3055 = s1_replaced_way_en[2];
+ assign T_3056 = s1_clk_en & T_3055;
+ assign T_3130 = s1_replaced_way_en[3];
+ assign T_3131 = s1_clk_en & T_3130;
+ assign T_3278_0_tag = T_2907_tag;
+ assign T_3278_0_coh_state = T_2907_coh_state;
+ assign T_3278_1_tag = T_2982_tag;
+ assign T_3278_1_coh_state = T_2982_coh_state;
+ assign T_3278_2_tag = T_3057_tag;
+ assign T_3278_2_coh_state = T_3057_coh_state;
+ assign T_3278_3_tag = T_3132_tag;
+ assign T_3278_3_coh_state = T_3132_coh_state;
+ assign T_3644 = s2_replaced_way_en[0];
+ assign T_3645 = s2_replaced_way_en[1];
+ assign T_3646 = s2_replaced_way_en[2];
+ assign T_3647 = s2_replaced_way_en[3];
+ assign T_3648 = {T_3278_0_tag,T_3278_0_coh_state};
+ assign T_3650 = T_3644 ? T_3648 : 1'h0;
+ assign T_3651 = {T_3278_1_tag,T_3278_1_coh_state};
+ assign T_3653 = T_3645 ? T_3651 : 1'h0;
+ assign T_3654 = {T_3278_2_tag,T_3278_2_coh_state};
+ assign T_3656 = T_3646 ? T_3654 : 1'h0;
+ assign T_3657 = {T_3278_3_tag,T_3278_3_coh_state};
+ assign T_3659 = T_3647 ? T_3657 : 1'h0;
+ assign T_3733 = T_3650 | T_3653;
+ assign T_3734 = T_3733 | T_3656;
+ assign T_3735 = T_3734 | T_3659;
+ assign s2_repl_meta_tag = T_3883;
+ assign s2_repl_meta_coh_state = T_3882;
+ assign T_3882 = T_3735[1:0];
+ assign T_3883 = T_3735[21:2];
+ assign T_3885 = s2_hit == 1'h0;
+ assign T_3886 = s2_valid_masked & T_3885;
+ assign T_3887 = s2_req_cmd == 5'h2;
+ assign T_3888 = s2_req_cmd == 5'h3;
+ assign T_3889 = T_3887 | T_3888;
+ assign T_3890 = s2_req_cmd == 5'h0;
+ assign T_3891 = s2_req_cmd == 5'h6;
+ assign T_3892 = T_3890 | T_3891;
+ assign T_3893 = s2_req_cmd == 5'h7;
+ assign T_3894 = T_3892 | T_3893;
+ assign T_3895 = s2_req_cmd[3];
+ assign T_3896 = s2_req_cmd == 5'h4;
+ assign T_3897 = T_3895 | T_3896;
+ assign T_3898 = T_3894 | T_3897;
+ assign T_3899 = T_3889 | T_3898;
+ assign T_3900 = s2_req_cmd == 5'h1;
+ assign T_3901 = s2_req_cmd == 5'h7;
+ assign T_3902 = T_3900 | T_3901;
+ assign T_3903 = s2_req_cmd[3];
+ assign T_3904 = s2_req_cmd == 5'h4;
+ assign T_3905 = T_3903 | T_3904;
+ assign T_3906 = T_3902 | T_3905;
+ assign T_3907 = T_3899 | T_3906;
+ assign T_3908 = T_3886 & T_3907;
+ assign T_3982_tag = s2_repl_meta_tag;
+ assign T_3982_coh_state = s2_hit_state_state;
+ assign T_4055_tag = s2_tag_match ? T_3982_tag : s2_repl_meta_tag;
+ assign T_4055_coh_state = s2_tag_match ? T_3982_coh_state : s2_repl_meta_coh_state;
+ assign T_4128 = s2_tag_match ? s2_tag_match_way : s2_replaced_way_en;
+ assign T_4129 = mshrs_io_req_ready & mshrs_io_req_valid;
+ assign T_4132 = ~ 4'h0;
+ assign T_4133 = mshrs_io_replay_valid & readArb_io_in_1_ready;
+ assign releaseArb_clk = clk;
+ assign releaseArb_reset = reset;
+ assign releaseArb_io_in_0_valid = wb_io_release_valid;
+ assign releaseArb_io_in_0_bits_addr_beat = wb_io_release_bits_addr_beat;
+ assign releaseArb_io_in_0_bits_addr_block = wb_io_release_bits_addr_block;
+ assign releaseArb_io_in_0_bits_client_xact_id = wb_io_release_bits_client_xact_id;
+ assign releaseArb_io_in_0_bits_voluntary = wb_io_release_bits_voluntary;
+ assign releaseArb_io_in_0_bits_r_type = wb_io_release_bits_r_type;
+ assign releaseArb_io_in_0_bits_data = wb_io_release_bits_data;
+ assign releaseArb_io_in_1_valid = prober_io_rep_valid;
+ assign releaseArb_io_in_1_bits_addr_beat = prober_io_rep_bits_addr_beat;
+ assign releaseArb_io_in_1_bits_addr_block = prober_io_rep_bits_addr_block;
+ assign releaseArb_io_in_1_bits_client_xact_id = prober_io_rep_bits_client_xact_id;
+ assign releaseArb_io_in_1_bits_voluntary = prober_io_rep_bits_voluntary;
+ assign releaseArb_io_in_1_bits_r_type = prober_io_rep_bits_r_type;
+ assign releaseArb_io_in_1_bits_data = prober_io_rep_bits_data;
+ assign releaseArb_io_out_ready = io_mem_release_ready;
+ assign T_4166 = lrsc_valid == 1'h0;
+ assign T_4167 = io_mem_probe_valid & T_4166;
+ assign T_4169 = lrsc_valid == 1'h0;
+ assign T_4170 = prober_io_req_ready & T_4169;
+ assign T_4171_clk = clk;
+ assign T_4171_reset = reset;
+ assign T_4171_io_in_valid = io_mem_grant_valid;
+ assign T_4171_io_in_bits_addr_beat = io_mem_grant_bits_addr_beat;
+ assign T_4171_io_in_bits_client_xact_id = io_mem_grant_bits_client_xact_id;
+ assign T_4171_io_in_bits_manager_xact_id = io_mem_grant_bits_manager_xact_id;
+ assign T_4171_io_in_bits_is_builtin_type = io_mem_grant_bits_is_builtin_type;
+ assign T_4171_io_in_bits_g_type = io_mem_grant_bits_g_type;
+ assign T_4171_io_in_bits_data = io_mem_grant_bits_data;
+ assign T_4171_io_out_ready = T_4198;
+ assign T_4172 = T_4171_io_out_ready & T_4171_io_out_valid;
+ assign T_4176_0 = 3'h5;
+ assign T_4176_1 = 3'h4;
+ assign T_4180 = T_4176_0 == T_4171_io_out_bits_g_type;
+ assign T_4181 = T_4176_1 == T_4171_io_out_bits_g_type;
+ assign T_4183 = 1'h0 | T_4180;
+ assign T_4184 = T_4183 | T_4181;
+ assign T_4186_0 = 1'h0;
+ assign T_4186_1 = 1'h1;
+ assign T_4190 = T_4186_0 == T_4171_io_out_bits_g_type;
+ assign T_4191 = T_4186_1 == T_4171_io_out_bits_g_type;
+ assign T_4193 = 1'h0 | T_4190;
+ assign T_4194 = T_4193 | T_4191;
+ assign T_4195 = T_4171_io_out_bits_is_builtin_type ? T_4184 : T_4194;
+ assign T_4197 = T_4195 == 1'h0;
+ assign T_4198 = writeArb_io_in_1_ready | T_4197;
+ assign T_4202_0 = 3'h5;
+ assign T_4202_1 = 3'h4;
+ assign T_4206 = T_4202_0 == T_4171_io_out_bits_g_type;
+ assign T_4207 = T_4202_1 == T_4171_io_out_bits_g_type;
+ assign T_4209 = 1'h0 | T_4206;
+ assign T_4210 = T_4209 | T_4207;
+ assign T_4212_0 = 1'h0;
+ assign T_4212_1 = 1'h1;
+ assign T_4216 = T_4212_0 == T_4171_io_out_bits_g_type;
+ assign T_4217 = T_4212_1 == T_4171_io_out_bits_g_type;
+ assign T_4219 = 1'h0 | T_4216;
+ assign T_4220 = T_4219 | T_4217;
+ assign T_4221 = T_4171_io_out_bits_is_builtin_type ? T_4210 : T_4220;
+ assign T_4222 = T_4171_io_out_valid & T_4221;
+ assign T_4224 = T_4171_io_out_bits_client_xact_id < 2'h2;
+ assign T_4225 = T_4222 & T_4224;
+ assign T_4227 = ~ 2'h0;
+ assign T_4228 = T_4171_io_out_bits_data;
+ assign T_4230 = T_4171_io_out_valid == 1'h0;
+ assign T_4231 = T_4230 | T_4171_io_out_ready;
+ assign wbArb_clk = clk;
+ assign wbArb_reset = reset;
+ assign wbArb_io_in_0_valid = prober_io_wb_req_valid;
+ assign wbArb_io_in_0_bits_addr_beat = prober_io_wb_req_bits_addr_beat;
+ assign wbArb_io_in_0_bits_addr_block = prober_io_wb_req_bits_addr_block;
+ assign wbArb_io_in_0_bits_client_xact_id = prober_io_wb_req_bits_client_xact_id;
+ assign wbArb_io_in_0_bits_voluntary = prober_io_wb_req_bits_voluntary;
+ assign wbArb_io_in_0_bits_r_type = prober_io_wb_req_bits_r_type;
+ assign wbArb_io_in_0_bits_data = prober_io_wb_req_bits_data;
+ assign wbArb_io_in_0_bits_way_en = prober_io_wb_req_bits_way_en;
+ assign wbArb_io_in_1_valid = mshrs_io_wb_req_valid;
+ assign wbArb_io_in_1_bits_addr_beat = mshrs_io_wb_req_bits_addr_beat;
+ assign wbArb_io_in_1_bits_addr_block = mshrs_io_wb_req_bits_addr_block;
+ assign wbArb_io_in_1_bits_client_xact_id = mshrs_io_wb_req_bits_client_xact_id;
+ assign wbArb_io_in_1_bits_voluntary = mshrs_io_wb_req_bits_voluntary;
+ assign wbArb_io_in_1_bits_r_type = mshrs_io_wb_req_bits_r_type;
+ assign wbArb_io_in_1_bits_data = mshrs_io_wb_req_bits_data;
+ assign wbArb_io_in_1_bits_way_en = mshrs_io_wb_req_bits_way_en;
+ assign wbArb_io_out_ready = wb_io_req_ready;
+ assign T_4266 = s3_valid & metaReadArb_io_out_valid;
+ assign T_4321 = s2_valid_masked | s2_replay;
+ assign T_4323 = s2_sc_fail == 1'h0;
+ assign T_4324 = T_4321 & T_4323;
+ assign T_4325 = s1_addr[31:3];
+ assign T_4326 = s2_req_addr[39:3];
+ assign T_4327 = T_4325 == T_4326;
+ assign T_4328 = T_4324 & T_4327;
+ assign T_4329 = s2_req_cmd == 5'h1;
+ assign T_4330 = s2_req_cmd == 5'h7;
+ assign T_4331 = T_4329 | T_4330;
+ assign T_4332 = s2_req_cmd[3];
+ assign T_4333 = s2_req_cmd == 5'h4;
+ assign T_4334 = T_4332 | T_4333;
+ assign T_4335 = T_4331 | T_4334;
+ assign T_4336 = T_4328 & T_4335;
+ assign T_4337 = s1_addr[31:3];
+ assign T_4338 = s3_req_addr[39:3];
+ assign T_4339 = T_4337 == T_4338;
+ assign T_4340 = s3_valid & T_4339;
+ assign T_4341 = s3_req_cmd == 5'h1;
+ assign T_4342 = s3_req_cmd == 5'h7;
+ assign T_4343 = T_4341 | T_4342;
+ assign T_4344 = s3_req_cmd[3];
+ assign T_4345 = s3_req_cmd == 5'h4;
+ assign T_4346 = T_4344 | T_4345;
+ assign T_4347 = T_4343 | T_4346;
+ assign T_4348 = T_4340 & T_4347;
+ assign T_4349 = s1_addr[31:3];
+ assign T_4350 = s4_req_addr[39:3];
+ assign T_4351 = T_4349 == T_4350;
+ assign T_4352 = s4_valid & T_4351;
+ assign T_4353 = s4_req_cmd == 5'h1;
+ assign T_4354 = s4_req_cmd == 5'h7;
+ assign T_4355 = T_4353 | T_4354;
+ assign T_4356 = s4_req_cmd[3];
+ assign T_4357 = s4_req_cmd == 5'h4;
+ assign T_4358 = T_4356 | T_4357;
+ assign T_4359 = T_4355 | T_4358;
+ assign T_4360 = T_4352 & T_4359;
+ assign T_4366 = T_4336 | T_4348;
+ assign T_4367 = T_4366 | T_4360;
+ assign T_4368 = T_4348 ? s3_req_data : s4_req_data;
+ assign T_4369 = T_4336 ? amoalu_io_out : T_4368;
+ assign T_4372 = {1'h0,6'h0};
+ assign s2_data_word_prebypass = s2_data_uncorrected >> T_4372;
+ assign s2_data_word = s2_store_bypass ? s2_store_bypass_data : s2_data_word_prebypass;
+ assign T_4375 = s2_req_typ[1:0];
+ assign T_4376 = $signed(s2_req_typ);
+ assign GEN_0 = $signed(1'h0);
+ assign T_4378 = $signed(T_4376) >= $signed(GEN_0);
+ assign T_4379 = dtlb_io_req_valid & dtlb_io_resp_miss;
+ assign T_4380 = s1_req_addr[11:6];
+ assign T_4381 = T_4380 == prober_io_meta_write_bits_idx;
+ assign T_4383 = prober_io_req_ready == 1'h0;
+ assign T_4384 = T_4381 & T_4383;
+ assign s1_nack = T_4379 | T_4384;
+ assign T_4386 = s1_valid | s1_replay;
+ assign s2_nack_victim = s2_hit & mshrs_io_secondary_miss;
+ assign T_4391 = s2_hit == 1'h0;
+ assign T_4393 = mshrs_io_req_ready == 1'h0;
+ assign s2_nack_miss = T_4391 & T_4393;
+ assign T_4395 = s2_nack_hit | s2_nack_victim;
+ assign s2_nack = T_4395 | s2_nack_miss;
+ assign T_4398 = s2_nack == 1'h0;
+ assign T_4399 = s2_valid & T_4398;
+ assign T_4400 = s2_valid | s2_replay;
+ assign T_4401 = T_4400 & s2_hit;
+ assign s2_recycle_ecc = T_4401 & s2_data_correctable;
+ assign T_4405 = s1_valid | s1_replay;
+ assign T_4406 = s2_recycle_ecc | s2_recycle_next;
+ assign T_4409 = s2_valid | block_miss;
+ assign T_4410 = T_4409 & s2_nack_miss;
+ assign cache_resp_valid = T_4705;
+ assign cache_resp_bits_addr = s2_req_addr;
+ assign cache_resp_bits_tag = s2_req_tag;
+ assign cache_resp_bits_cmd = s2_req_cmd;
+ assign cache_resp_bits_typ = s2_req_typ;
+ assign cache_resp_bits_data = T_4772;
+ assign cache_resp_bits_nack = T_4773;
+ assign cache_resp_bits_replay = s2_replay;
+ assign cache_resp_bits_has_data = T_4714;
+ assign cache_resp_bits_data_word_bypass = GEN_3;
+ assign cache_resp_bits_store_data = s2_req_data;
+ assign T_4701 = s2_valid_masked & s2_hit;
+ assign T_4702 = s2_replay | T_4701;
+ assign T_4704 = s2_data_correctable == 1'h0;
+ assign T_4705 = T_4702 & T_4704;
+ assign T_4706 = s2_req_cmd == 5'h0;
+ assign T_4707 = s2_req_cmd == 5'h6;
+ assign T_4708 = T_4706 | T_4707;
+ assign T_4709 = s2_req_cmd == 5'h7;
+ assign T_4710 = T_4708 | T_4709;
+ assign T_4711 = s2_req_cmd[3];
+ assign T_4712 = s2_req_cmd == 5'h4;
+ assign T_4713 = T_4711 | T_4712;
+ assign T_4714 = T_4710 | T_4713;
+ assign T_4715 = s2_req_addr[2];
+ assign T_4716 = s2_data_word[63:32];
+ assign T_4717 = s2_data_word[31:0];
+ assign T_4718 = T_4715 ? T_4716 : T_4717;
+ assign T_4720 = 1'h0 & s2_sc;
+ assign T_4722 = T_4720 ? 1'h0 : T_4718;
+ assign T_4724 = T_4375 == 2'h2;
+ assign T_4725 = T_4724 | T_4720;
+ assign T_4726 = T_4722[31];
+ assign T_4727 = T_4378 & T_4726;
+ assign T_4729 = 32'h0 - T_4727;
+ assign T_4730 = T_4729[31:0];
+ assign T_4731 = s2_data_word[63:32];
+ assign T_4732 = T_4725 ? T_4730 : T_4731;
+ assign T_4733 = {T_4732,T_4722};
+ assign T_4734 = s2_req_addr[1];
+ assign T_4735 = T_4733[31:16];
+ assign T_4736 = T_4733[15:0];
+ assign T_4737 = T_4734 ? T_4735 : T_4736;
+ assign T_4739 = 1'h0 & s2_sc;
+ assign T_4741 = T_4739 ? 1'h0 : T_4737;
+ assign T_4743 = T_4375 == 1'h1;
+ assign T_4744 = T_4743 | T_4739;
+ assign T_4745 = T_4741[15];
+ assign T_4746 = T_4378 & T_4745;
+ assign T_4748 = 48'h0 - T_4746;
+ assign T_4749 = T_4748[47:0];
+ assign T_4750 = T_4733[63:16];
+ assign T_4751 = T_4744 ? T_4749 : T_4750;
+ assign T_4752 = {T_4751,T_4741};
+ assign T_4753 = s2_req_addr[0];
+ assign T_4754 = T_4752[15:8];
+ assign T_4755 = T_4752[7:0];
+ assign T_4756 = T_4753 ? T_4754 : T_4755;
+ assign T_4758 = 1'h1 & s2_sc;
+ assign T_4760 = T_4758 ? 1'h0 : T_4756;
+ assign T_4762 = T_4375 == 1'h0;
+ assign T_4763 = T_4762 | T_4758;
+ assign T_4764 = T_4760[7];
+ assign T_4765 = T_4378 & T_4764;
+ assign T_4767 = 56'h0 - T_4765;
+ assign T_4768 = T_4767[55:0];
+ assign T_4769 = T_4752[63:8];
+ assign T_4770 = T_4763 ? T_4768 : T_4769;
+ assign T_4771 = {T_4770,T_4760};
+ assign T_4772 = T_4771 | s2_sc_fail;
+ assign T_4773 = s2_valid & s2_nack;
+ assign uncache_resp_valid = mshrs_io_resp_valid;
+ assign uncache_resp_bits_addr = mshrs_io_resp_bits_addr;
+ assign uncache_resp_bits_tag = mshrs_io_resp_bits_tag;
+ assign uncache_resp_bits_cmd = mshrs_io_resp_bits_cmd;
+ assign uncache_resp_bits_typ = mshrs_io_resp_bits_typ;
+ assign uncache_resp_bits_data = mshrs_io_resp_bits_data;
+ assign uncache_resp_bits_nack = mshrs_io_resp_bits_nack;
+ assign uncache_resp_bits_replay = mshrs_io_resp_bits_replay;
+ assign uncache_resp_bits_has_data = mshrs_io_resp_bits_has_data;
+ assign uncache_resp_bits_data_word_bypass = mshrs_io_resp_bits_data_word_bypass;
+ assign uncache_resp_bits_store_data = mshrs_io_resp_bits_store_data;
+ assign T_5063 = s2_valid | s2_killed;
+ assign cache_pass = T_5063 | s2_replay;
+ assign T_5066 = cache_pass == 1'h0;
+ assign T_5067_valid = cache_pass ? cache_resp_valid : uncache_resp_valid;
+ assign T_5067_bits_addr = cache_pass ? cache_resp_bits_addr : uncache_resp_bits_addr;
+ assign T_5067_bits_tag = cache_pass ? cache_resp_bits_tag : uncache_resp_bits_tag;
+ assign T_5067_bits_cmd = cache_pass ? cache_resp_bits_cmd : uncache_resp_bits_cmd;
+ assign T_5067_bits_typ = cache_pass ? cache_resp_bits_typ : uncache_resp_bits_typ;
+ assign T_5067_bits_data = cache_pass ? cache_resp_bits_data : uncache_resp_bits_data;
+ assign T_5067_bits_nack = cache_pass ? cache_resp_bits_nack : uncache_resp_bits_nack;
+ assign T_5067_bits_replay = cache_pass ? cache_resp_bits_replay : uncache_resp_bits_replay;
+ assign T_5067_bits_has_data = cache_pass ? cache_resp_bits_has_data : uncache_resp_bits_has_data;
+ assign T_5067_bits_data_word_bypass = cache_pass ? cache_resp_bits_data_word_bypass : uncache_resp_bits_data_word_bypass;
+ assign T_5067_bits_store_data = cache_pass ? cache_resp_bits_store_data : uncache_resp_bits_store_data;
+ assign T_5183 = s2_req_addr[2];
+ assign T_5184 = s2_data_word[63:32];
+ assign T_5185 = s2_data_word[31:0];
+ assign T_5186 = T_5183 ? T_5184 : T_5185;
+ assign T_5188 = 1'h0 & s2_sc;
+ assign T_5190 = T_5188 ? 1'h0 : T_5186;
+ assign T_5192 = T_4375 == 2'h2;
+ assign T_5193 = T_5192 | T_5188;
+ assign T_5194 = T_5190[31];
+ assign T_5195 = T_4378 & T_5194;
+ assign T_5197 = 32'h0 - T_5195;
+ assign T_5198 = T_5197[31:0];
+ assign T_5199 = s2_data_word[63:32];
+ assign T_5200 = T_5193 ? T_5198 : T_5199;
+ assign T_5201 = {T_5200,T_5190};
+ assign T_5203 = s1_valid == 1'h0;
+ assign T_5204 = mshrs_io_fence_rdy & T_5203;
+ assign T_5206 = s2_valid == 1'h0;
+ assign T_5207 = T_5204 & T_5206;
+ assign T_5208 = s1_replay & s1_read;
+ assign GEN_1 = T_1879 & T_1881;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ s1_valid = {1{$random}};
+ s1_req_addr = {2{$random}};
+ s1_req_tag = {1{$random}};
+ s1_req_cmd = {1{$random}};
+ s1_req_typ = {1{$random}};
+ s1_req_kill = {1{$random}};
+ s1_req_phys = {1{$random}};
+ s1_req_data = {2{$random}};
+ s1_replay = {1{$random}};
+ s1_clk_en = {1{$random}};
+ s2_valid = {1{$random}};
+ s2_killed = {1{$random}};
+ s2_req_addr = {2{$random}};
+ s2_req_tag = {1{$random}};
+ s2_req_cmd = {1{$random}};
+ s2_req_typ = {1{$random}};
+ s2_req_kill = {1{$random}};
+ s2_req_phys = {1{$random}};
+ s2_req_data = {2{$random}};
+ T_1745 = {1{$random}};
+ s3_valid = {1{$random}};
+ s3_req_addr = {2{$random}};
+ s3_req_tag = {1{$random}};
+ s3_req_cmd = {1{$random}};
+ s3_req_typ = {1{$random}};
+ s3_req_kill = {1{$random}};
+ s3_req_phys = {1{$random}};
+ s3_req_data = {2{$random}};
+ s3_way = {1{$random}};
+ s1_recycled = {1{$random}};
+ T_1874 = {1{$random}};
+ s2_tag_match_way = {1{$random}};
+ T_2210_state = {1{$random}};
+ T_2235_state = {1{$random}};
+ T_2260_state = {1{$random}};
+ T_2285_state = {1{$random}};
+ lrsc_count = {1{$random}};
+ lrsc_addr = {2{$random}};
+ T_2697_0 = {2{$random}};
+ T_2697_1 = {2{$random}};
+ T_2728_0 = {2{$random}};
+ T_2728_1 = {2{$random}};
+ T_2759_0 = {2{$random}};
+ T_2759_1 = {2{$random}};
+ T_2790_0 = {2{$random}};
+ T_2790_1 = {2{$random}};
+ T_2888 = {1{$random}};
+ T_2902 = {1{$random}};
+ T_2907_tag = {1{$random}};
+ T_2907_coh_state = {1{$random}};
+ T_2982_tag = {1{$random}};
+ T_2982_coh_state = {1{$random}};
+ T_3057_tag = {1{$random}};
+ T_3057_coh_state = {1{$random}};
+ T_3132_tag = {1{$random}};
+ T_3132_coh_state = {1{$random}};
+ s4_valid = {1{$random}};
+ s4_req_addr = {2{$random}};
+ s4_req_tag = {1{$random}};
+ s4_req_cmd = {1{$random}};
+ s4_req_typ = {1{$random}};
+ s4_req_kill = {1{$random}};
+ s4_req_phys = {1{$random}};
+ s4_req_data = {2{$random}};
+ s2_store_bypass_data = {2{$random}};
+ s2_store_bypass = {1{$random}};
+ s2_nack_hit = {1{$random}};
+ s2_recycle_next = {1{$random}};
+ block_miss = {1{$random}};
+ GEN_2 = {1{$random}};
+ GEN_3 = {2{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ s1_valid <= 1'h0;
+ end else begin
+ s1_valid <= T_1622;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(s2_recycle) begin
+ s1_req_addr <= s2_req_addr;
+ end else begin
+ if(mshrs_io_replay_valid) begin
+ s1_req_addr <= mshrs_io_replay_bits_addr;
+ end else begin
+ if(prober_io_meta_read_valid) begin
+ s1_req_addr <= T_1851;
+ end else begin
+ if(wb_io_meta_read_valid) begin
+ s1_req_addr <= T_1848;
+ end else begin
+ if(io_cpu_req_valid) begin
+ s1_req_addr <= io_cpu_req_bits_addr;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(s2_recycle) begin
+ s1_req_tag <= s2_req_tag;
+ end else begin
+ if(mshrs_io_replay_valid) begin
+ s1_req_tag <= mshrs_io_replay_bits_tag;
+ end else begin
+ if(io_cpu_req_valid) begin
+ s1_req_tag <= io_cpu_req_bits_tag;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(s2_recycle) begin
+ s1_req_cmd <= s2_req_cmd;
+ end else begin
+ if(mshrs_io_replay_valid) begin
+ s1_req_cmd <= mshrs_io_replay_bits_cmd;
+ end else begin
+ if(io_cpu_req_valid) begin
+ s1_req_cmd <= io_cpu_req_bits_cmd;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(s2_recycle) begin
+ s1_req_typ <= s2_req_typ;
+ end else begin
+ if(mshrs_io_replay_valid) begin
+ s1_req_typ <= mshrs_io_replay_bits_typ;
+ end else begin
+ if(io_cpu_req_valid) begin
+ s1_req_typ <= io_cpu_req_bits_typ;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(s2_recycle) begin
+ s1_req_kill <= s2_req_kill;
+ end else begin
+ if(mshrs_io_replay_valid) begin
+ s1_req_kill <= mshrs_io_replay_bits_kill;
+ end else begin
+ if(io_cpu_req_valid) begin
+ s1_req_kill <= io_cpu_req_bits_kill;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(s2_recycle) begin
+ s1_req_phys <= s2_req_phys;
+ end else begin
+ if(mshrs_io_replay_valid) begin
+ s1_req_phys <= mshrs_io_replay_bits_phys;
+ end else begin
+ if(prober_io_meta_read_valid) begin
+ s1_req_phys <= 1'h1;
+ end else begin
+ if(wb_io_meta_read_valid) begin
+ s1_req_phys <= 1'h1;
+ end else begin
+ if(io_cpu_req_valid) begin
+ s1_req_phys <= io_cpu_req_bits_phys;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(s2_recycle) begin
+ s1_req_data <= s2_req_data;
+ end else begin
+ if(mshrs_io_replay_valid) begin
+ s1_req_data <= mshrs_io_replay_bits_data;
+ end else begin
+ if(io_cpu_req_valid) begin
+ s1_req_data <= io_cpu_req_bits_data;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ if(reset) begin
+ s1_replay <= 1'h0;
+ end else begin
+ s1_replay <= T_4133;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ s1_clk_en <= metaReadArb_io_out_valid;
+ end
+ if(reset) begin
+ s2_valid <= 1'h0;
+ end else begin
+ s2_valid <= s1_valid_masked;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ s2_killed <= T_1688;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(s1_clk_en) begin
+ s2_req_addr <= s1_addr;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(s1_clk_en) begin
+ s2_req_tag <= s1_req_tag;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(s1_clk_en) begin
+ s2_req_cmd <= s1_req_cmd;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(s1_clk_en) begin
+ s2_req_typ <= s1_req_typ;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(s1_clk_en) begin
+ s2_req_kill <= s1_req_kill;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(s1_clk_en) begin
+ s2_req_phys <= s1_req_phys;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(s1_clk_en) begin
+ if(s1_recycled) begin
+ s2_req_data <= s1_req_data;
+ end else begin
+ if(s1_write) begin
+ s2_req_data <= T_1855;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_1745 <= 1'h0;
+ end else begin
+ T_1745 <= s1_replay;
+ end
+ if(reset) begin
+ s3_valid <= 1'h0;
+ end else begin
+ s3_valid <= T_2867;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_2878) begin
+ s3_req_addr <= s2_req_addr;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_2878) begin
+ s3_req_tag <= s2_req_tag;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_2878) begin
+ s3_req_cmd <= s2_req_cmd;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_2878) begin
+ s3_req_typ <= s2_req_typ;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_2878) begin
+ s3_req_kill <= s2_req_kill;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_2878) begin
+ s3_req_phys <= s2_req_phys;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_2878) begin
+ s3_req_data <= T_2879;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_2878) begin
+ s3_way <= s2_tag_match_way;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ s1_recycled <= 1'h0;
+ end else begin
+ if(s1_clk_en) begin
+ s1_recycled <= s2_recycle;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ T_1874 <= T_1873;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(s1_clk_en) begin
+ s2_tag_match_way <= s1_tag_match_way;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(s1_clk_en) begin
+ T_2210_state <= meta_io_resp_0_coh_state;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(s1_clk_en) begin
+ T_2235_state <= meta_io_resp_1_coh_state;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(s1_clk_en) begin
+ T_2260_state <= meta_io_resp_2_coh_state;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(s1_clk_en) begin
+ T_2285_state <= meta_io_resp_3_coh_state;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ lrsc_count <= 1'h0;
+ end else begin
+ if(io_cpu_invalidate_lr) begin
+ lrsc_count <= 1'h0;
+ end else begin
+ if(T_2666) begin
+ if(s2_sc) begin
+ lrsc_count <= 1'h0;
+ end else begin
+ if(s2_lr) begin
+ if(T_2668) begin
+ lrsc_count <= 5'h1f;
+ end else begin
+ if(lrsc_valid) begin
+ lrsc_count <= T_2664;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(lrsc_valid) begin
+ lrsc_count <= T_2664;
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(lrsc_valid) begin
+ lrsc_count <= T_2664;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_2666) begin
+ if(s2_lr) begin
+ lrsc_addr <= T_2670;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_2709) begin
+ T_2697_0 <= T_2710;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_2717) begin
+ T_2697_1 <= T_2718;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_2740) begin
+ T_2728_0 <= T_2741;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_2748) begin
+ T_2728_1 <= T_2749;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_2771) begin
+ T_2759_0 <= T_2772;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_2779) begin
+ T_2759_1 <= T_2780;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_2802) begin
+ T_2790_0 <= T_2803;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_2810) begin
+ T_2790_1 <= T_2811;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_2888 <= 16'h1;
+ end else begin
+ if(T_2885) begin
+ T_2888 <= T_2897;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(s1_clk_en) begin
+ T_2902 <= T_2901;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_2906) begin
+ T_2907_tag <= meta_io_resp_0_tag;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_2906) begin
+ T_2907_coh_state <= meta_io_resp_0_coh_state;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_2981) begin
+ T_2982_tag <= meta_io_resp_1_tag;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_2981) begin
+ T_2982_coh_state <= meta_io_resp_1_coh_state;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_3056) begin
+ T_3057_tag <= meta_io_resp_2_tag;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_3056) begin
+ T_3057_coh_state <= meta_io_resp_2_coh_state;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_3131) begin
+ T_3132_tag <= meta_io_resp_3_tag;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_3131) begin
+ T_3132_coh_state <= meta_io_resp_3_coh_state;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ s4_valid <= 1'h0;
+ end else begin
+ s4_valid <= s3_valid;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_4266) begin
+ s4_req_addr <= s3_req_addr;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_4266) begin
+ s4_req_tag <= s3_req_tag;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_4266) begin
+ s4_req_cmd <= s3_req_cmd;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_4266) begin
+ s4_req_typ <= s3_req_typ;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_4266) begin
+ s4_req_kill <= s3_req_kill;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_4266) begin
+ s4_req_phys <= s3_req_phys;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_4266) begin
+ s4_req_data <= s3_req_data;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(s1_clk_en) begin
+ if(T_4367) begin
+ s2_store_bypass_data <= T_4369;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(s1_clk_en) begin
+ if(T_4367) begin
+ s2_store_bypass <= 1'h1;
+ end else begin
+ s2_store_bypass <= 1'h0;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_4386) begin
+ s2_nack_hit <= s1_nack;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ s2_recycle_next <= 1'h0;
+ end else begin
+ if(T_4405) begin
+ s2_recycle_next <= s2_recycle_ecc;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ block_miss <= 1'h0;
+ end else begin
+ block_miss <= T_4410;
+ end
+ `ifndef SYNTHESIS
+ if(GEN_1 & T_1883) begin
+ $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): DCache exception occurred - cache response not killed.");
+ end
+ `endif
+ `ifndef SYNTHESIS
+ if(T_1879 & T_1881) begin
+ $fdisplay(32'h80000002,"1");$finish;
+ end
+ `endif
+ end
+endmodule
+module RRArbiter_112(
+ input clk,
+ input reset,
+ output io_in_0_ready,
+ input io_in_0_valid,
+ input [26:0] io_in_0_bits_addr,
+ input [1:0] io_in_0_bits_prv,
+ input io_in_0_bits_store,
+ input io_in_0_bits_fetch,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input [26:0] io_in_1_bits_addr,
+ input [1:0] io_in_1_bits_prv,
+ input io_in_1_bits_store,
+ input io_in_1_bits_fetch,
+ input io_out_ready,
+ output io_out_valid,
+ output [26:0] io_out_bits_addr,
+ output [1:0] io_out_bits_prv,
+ output io_out_bits_store,
+ output io_out_bits_fetch,
+ output io_chosen
+);
+ wire T_152;
+ wire GEN_0;
+ wire [26:0] GEN_1;
+ wire [1:0] GEN_2;
+ wire GEN_3;
+ wire GEN_4;
+ wire GEN_5;
+ reg T_195;
+ wire T_196;
+ wire T_197;
+ wire T_199;
+ wire T_200;
+ wire T_203;
+ wire T_205;
+ wire T_207;
+ wire T_208;
+ wire T_210;
+ wire T_212;
+ wire T_213;
+ wire T_214;
+ wire T_216;
+ wire T_218;
+ wire T_219;
+ wire T_220;
+ wire T_222;
+ wire T_223;
+ wire T_224;
+ wire T_226;
+ wire T_227;
+ wire T_228;
+ wire T_230;
+ wire T_231;
+ wire T_232;
+ wire T_235;
+ wire T_237;
+ wire T_238;
+ wire T_240;
+ wire T_241;
+ wire T_242;
+ wire GEN_6;
+ wire GEN_7;
+ wire GEN_8;
+ wire GEN_9;
+ wire GEN_10;
+ assign io_in_0_ready = T_228;
+ assign io_in_1_ready = T_232;
+ assign io_out_valid = GEN_0;
+ assign io_out_bits_addr = GEN_1;
+ assign io_out_bits_prv = GEN_2;
+ assign io_out_bits_store = GEN_3;
+ assign io_out_bits_fetch = GEN_4;
+ assign io_chosen = T_152;
+ assign T_152 = T_241;
+ assign GEN_0 = GEN_6 ? io_in_1_valid : io_in_0_valid;
+ assign GEN_1 = GEN_7 ? io_in_1_bits_addr : io_in_0_bits_addr;
+ assign GEN_2 = GEN_8 ? io_in_1_bits_prv : io_in_0_bits_prv;
+ assign GEN_3 = GEN_9 ? io_in_1_bits_store : io_in_0_bits_store;
+ assign GEN_4 = GEN_10 ? io_in_1_bits_fetch : io_in_0_bits_fetch;
+ assign GEN_5 = 1'h0;
+ assign T_196 = 1'h0 > T_195;
+ assign T_197 = io_in_0_valid & T_196;
+ assign T_199 = 1'h1 > T_195;
+ assign T_200 = io_in_1_valid & T_199;
+ assign T_203 = 1'h0 | T_197;
+ assign T_205 = T_203 == 1'h0;
+ assign T_207 = 1'h0 | T_197;
+ assign T_208 = T_207 | T_200;
+ assign T_210 = T_208 == 1'h0;
+ assign T_212 = 1'h0 | T_197;
+ assign T_213 = T_212 | T_200;
+ assign T_214 = T_213 | io_in_0_valid;
+ assign T_216 = T_214 == 1'h0;
+ assign T_218 = 1'h0 > T_195;
+ assign T_219 = 1'h1 & T_218;
+ assign T_220 = T_219 | T_210;
+ assign T_222 = 1'h1 > T_195;
+ assign T_223 = T_205 & T_222;
+ assign T_224 = T_223 | T_216;
+ assign T_226 = 1'h1 == 1'h0;
+ assign T_227 = 1'h0 ? T_226 : T_220;
+ assign T_228 = T_227 & io_out_ready;
+ assign T_230 = 1'h1 == 1'h1;
+ assign T_231 = 1'h0 ? T_230 : T_224;
+ assign T_232 = T_231 & io_out_ready;
+ assign T_235 = io_in_0_valid ? 1'h0 : 1'h1;
+ assign T_237 = 1'h1 > T_195;
+ assign T_238 = io_in_1_valid & T_237;
+ assign T_240 = T_238 ? 1'h1 : T_235;
+ assign T_241 = 1'h0 ? 1'h1 : T_240;
+ assign T_242 = io_out_ready & io_out_valid;
+ assign GEN_6 = 1'h1 == T_152;
+ assign GEN_7 = 1'h1 == T_152;
+ assign GEN_8 = 1'h1 == T_152;
+ assign GEN_9 = 1'h1 == T_152;
+ assign GEN_10 = 1'h1 == T_152;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_195 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ T_195 <= 1'h0;
+ end else begin
+ if(T_242) begin
+ T_195 <= T_152;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module PTW(
+ input clk,
+ input reset,
+ output io_requestor_0_req_ready,
+ input io_requestor_0_req_valid,
+ input [26:0] io_requestor_0_req_bits_addr,
+ input [1:0] io_requestor_0_req_bits_prv,
+ input io_requestor_0_req_bits_store,
+ input io_requestor_0_req_bits_fetch,
+ output io_requestor_0_resp_valid,
+ output io_requestor_0_resp_bits_error,
+ output [19:0] io_requestor_0_resp_bits_pte_ppn,
+ output [2:0] io_requestor_0_resp_bits_pte_reserved_for_software,
+ output io_requestor_0_resp_bits_pte_d,
+ output io_requestor_0_resp_bits_pte_r,
+ output [3:0] io_requestor_0_resp_bits_pte_typ,
+ output io_requestor_0_resp_bits_pte_v,
+ output io_requestor_0_status_sd,
+ output [30:0] io_requestor_0_status_zero2,
+ output io_requestor_0_status_sd_rv32,
+ output [8:0] io_requestor_0_status_zero1,
+ output [4:0] io_requestor_0_status_vm,
+ output io_requestor_0_status_mprv,
+ output [1:0] io_requestor_0_status_xs,
+ output [1:0] io_requestor_0_status_fs,
+ output [1:0] io_requestor_0_status_prv3,
+ output io_requestor_0_status_ie3,
+ output [1:0] io_requestor_0_status_prv2,
+ output io_requestor_0_status_ie2,
+ output [1:0] io_requestor_0_status_prv1,
+ output io_requestor_0_status_ie1,
+ output [1:0] io_requestor_0_status_prv,
+ output io_requestor_0_status_ie,
+ output io_requestor_0_invalidate,
+ output io_requestor_1_req_ready,
+ input io_requestor_1_req_valid,
+ input [26:0] io_requestor_1_req_bits_addr,
+ input [1:0] io_requestor_1_req_bits_prv,
+ input io_requestor_1_req_bits_store,
+ input io_requestor_1_req_bits_fetch,
+ output io_requestor_1_resp_valid,
+ output io_requestor_1_resp_bits_error,
+ output [19:0] io_requestor_1_resp_bits_pte_ppn,
+ output [2:0] io_requestor_1_resp_bits_pte_reserved_for_software,
+ output io_requestor_1_resp_bits_pte_d,
+ output io_requestor_1_resp_bits_pte_r,
+ output [3:0] io_requestor_1_resp_bits_pte_typ,
+ output io_requestor_1_resp_bits_pte_v,
+ output io_requestor_1_status_sd,
+ output [30:0] io_requestor_1_status_zero2,
+ output io_requestor_1_status_sd_rv32,
+ output [8:0] io_requestor_1_status_zero1,
+ output [4:0] io_requestor_1_status_vm,
+ output io_requestor_1_status_mprv,
+ output [1:0] io_requestor_1_status_xs,
+ output [1:0] io_requestor_1_status_fs,
+ output [1:0] io_requestor_1_status_prv3,
+ output io_requestor_1_status_ie3,
+ output [1:0] io_requestor_1_status_prv2,
+ output io_requestor_1_status_ie2,
+ output [1:0] io_requestor_1_status_prv1,
+ output io_requestor_1_status_ie1,
+ output [1:0] io_requestor_1_status_prv,
+ output io_requestor_1_status_ie,
+ output io_requestor_1_invalidate,
+ input io_mem_req_ready,
+ output io_mem_req_valid,
+ output [39:0] io_mem_req_bits_addr,
+ output [8:0] io_mem_req_bits_tag,
+ output [4:0] io_mem_req_bits_cmd,
+ output [2:0] io_mem_req_bits_typ,
+ output io_mem_req_bits_kill,
+ output io_mem_req_bits_phys,
+ output [63:0] io_mem_req_bits_data,
+ input io_mem_resp_valid,
+ input [39:0] io_mem_resp_bits_addr,
+ input [8:0] io_mem_resp_bits_tag,
+ input [4:0] io_mem_resp_bits_cmd,
+ input [2:0] io_mem_resp_bits_typ,
+ input [63:0] io_mem_resp_bits_data,
+ input io_mem_resp_bits_nack,
+ input io_mem_resp_bits_replay,
+ input io_mem_resp_bits_has_data,
+ input [63:0] io_mem_resp_bits_data_word_bypass,
+ input [63:0] io_mem_resp_bits_store_data,
+ input io_mem_replay_next_valid,
+ input [8:0] io_mem_replay_next_bits,
+ input io_mem_xcpt_ma_ld,
+ input io_mem_xcpt_ma_st,
+ input io_mem_xcpt_pf_ld,
+ input io_mem_xcpt_pf_st,
+ output io_mem_invalidate_lr,
+ input io_mem_ordered,
+ input [31:0] io_dpath_ptbr,
+ input io_dpath_invalidate,
+ input io_dpath_status_sd,
+ input [30:0] io_dpath_status_zero2,
+ input io_dpath_status_sd_rv32,
+ input [8:0] io_dpath_status_zero1,
+ input [4:0] io_dpath_status_vm,
+ input io_dpath_status_mprv,
+ input [1:0] io_dpath_status_xs,
+ input [1:0] io_dpath_status_fs,
+ input [1:0] io_dpath_status_prv3,
+ input io_dpath_status_ie3,
+ input [1:0] io_dpath_status_prv2,
+ input io_dpath_status_ie2,
+ input [1:0] io_dpath_status_prv1,
+ input io_dpath_status_ie1,
+ input [1:0] io_dpath_status_prv,
+ input io_dpath_status_ie
+);
+ reg [2:0] state;
+ reg [1:0] count;
+ reg [26:0] r_req_addr;
+ reg [1:0] r_req_prv;
+ reg r_req_store;
+ reg r_req_fetch;
+ reg r_req_dest;
+ reg [19:0] r_pte_ppn;
+ reg [2:0] r_pte_reserved_for_software;
+ reg r_pte_d;
+ reg r_pte_r;
+ reg [3:0] r_pte_typ;
+ reg r_pte_v;
+ wire [8:0] T_1590;
+ wire [8:0] T_1591;
+ wire [17:0] T_1592;
+ wire [8:0] T_1593;
+ wire [26:0] T_1594;
+ wire [8:0] T_1595;
+ wire [8:0] T_1597_0;
+ wire [8:0] T_1597_1;
+ wire [8:0] T_1597_2;
+ wire arb_clk;
+ wire arb_reset;
+ wire arb_io_in_0_ready;
+ wire arb_io_in_0_valid;
+ wire [26:0] arb_io_in_0_bits_addr;
+ wire [1:0] arb_io_in_0_bits_prv;
+ wire arb_io_in_0_bits_store;
+ wire arb_io_in_0_bits_fetch;
+ wire arb_io_in_1_ready;
+ wire arb_io_in_1_valid;
+ wire [26:0] arb_io_in_1_bits_addr;
+ wire [1:0] arb_io_in_1_bits_prv;
+ wire arb_io_in_1_bits_store;
+ wire arb_io_in_1_bits_fetch;
+ wire arb_io_out_ready;
+ wire arb_io_out_valid;
+ wire [26:0] arb_io_out_bits_addr;
+ wire [1:0] arb_io_out_bits_prv;
+ wire arb_io_out_bits_store;
+ wire arb_io_out_bits_fetch;
+ wire arb_io_chosen;
+ wire T_1609;
+ wire [19:0] pte_ppn;
+ wire [2:0] pte_reserved_for_software;
+ wire pte_d;
+ wire pte_r;
+ wire [3:0] pte_typ;
+ wire pte_v;
+ wire T_1631;
+ wire [3:0] T_1632;
+ wire T_1633;
+ wire T_1634;
+ wire [2:0] T_1635;
+ wire [19:0] T_1636;
+ wire [8:0] GEN_0;
+ wire [28:0] T_1637;
+ wire [31:0] pte_addr;
+ wire T_1639;
+ wire [19:0] T_1640;
+ reg [2:0] T_1642;
+ reg T_1652_0;
+ reg T_1652_1;
+ reg T_1652_2;
+ wire [1:0] T_1657;
+ wire [2:0] T_1658;
+ reg [31:0] T_1661 [0:2];
+ wire [31:0] T_1661_T_1666_data;
+ wire [1:0] T_1661_T_1666_addr;
+ wire T_1661_T_1666_en;
+ wire T_1661_T_1666_clk;
+ wire [31:0] T_1661_T_1669_data;
+ wire [1:0] T_1661_T_1669_addr;
+ wire T_1661_T_1669_en;
+ wire T_1661_T_1669_clk;
+ wire [31:0] T_1661_T_1672_data;
+ wire [1:0] T_1661_T_1672_addr;
+ wire T_1661_T_1672_en;
+ wire T_1661_T_1672_clk;
+ wire [31:0] T_1661_T_1721_data;
+ wire [1:0] T_1661_T_1721_addr;
+ wire T_1661_T_1721_mask;
+ wire T_1661_T_1721_en;
+ wire T_1661_T_1721_clk;
+ reg [19:0] T_1664 [0:2];
+ wire [19:0] T_1664_T_1761_data;
+ wire [1:0] T_1664_T_1761_addr;
+ wire T_1664_T_1761_en;
+ wire T_1664_T_1761_clk;
+ wire [19:0] T_1664_T_1763_data;
+ wire [1:0] T_1664_T_1763_addr;
+ wire T_1664_T_1763_en;
+ wire T_1664_T_1763_clk;
+ wire [19:0] T_1664_T_1765_data;
+ wire [1:0] T_1664_T_1765_addr;
+ wire T_1664_T_1765_en;
+ wire T_1664_T_1765_clk;
+ wire [19:0] T_1664_T_1722_data;
+ wire [1:0] T_1664_T_1722_addr;
+ wire T_1664_T_1722_mask;
+ wire T_1664_T_1722_en;
+ wire T_1664_T_1722_clk;
+ wire T_1667;
+ wire T_1670;
+ wire T_1673;
+ wire T_1675_0;
+ wire T_1675_1;
+ wire T_1675_2;
+ wire [1:0] T_1680;
+ wire [2:0] T_1681;
+ wire [2:0] T_1682;
+ wire pte_cache_hit;
+ wire T_1686;
+ wire T_1687;
+ wire T_1688;
+ wire T_1690;
+ wire T_1691;
+ wire [2:0] T_1692;
+ wire T_1694;
+ wire [2:0] T_1696;
+ wire T_1697;
+ wire [1:0] T_1698;
+ wire [2:0] T_1699;
+ wire T_1700;
+ wire [2:0] T_1701;
+ wire [1:0] T_1702;
+ wire [2:0] T_1703;
+ wire T_1704;
+ wire T_1705;
+ wire T_1706;
+ wire T_1708_0;
+ wire T_1708_1;
+ wire T_1708_2;
+ wire [1:0] T_1716;
+ wire [1:0] T_1717;
+ wire [1:0] T_1718;
+ wire GEN_1;
+ wire T_1723;
+ wire T_1724;
+ wire T_1725;
+ wire [1:0] T_1726;
+ wire T_1728;
+ wire [1:0] T_1729;
+ wire T_1730;
+ wire [1:0] T_1731;
+ wire T_1733;
+ wire [3:0] T_1735;
+ wire [2:0] T_1736;
+ wire [2:0] T_1737;
+ wire [2:0] T_1738;
+ wire [2:0] T_1740;
+ wire [2:0] T_1741;
+ wire [1:0] T_1742;
+ wire T_1743;
+ wire [5:0] T_1745;
+ wire [2:0] T_1746;
+ wire [2:0] T_1747;
+ wire [2:0] T_1748;
+ wire [2:0] T_1750;
+ wire [2:0] T_1751;
+ wire [2:0] T_1752;
+ wire T_1753;
+ wire T_1757;
+ wire T_1758;
+ wire T_1759;
+ wire [19:0] T_1767;
+ wire [19:0] T_1769;
+ wire [19:0] T_1771;
+ wire [19:0] T_1773;
+ wire [19:0] T_1774;
+ wire [19:0] pte_cache_data;
+ wire T_1776;
+ wire T_1778;
+ wire T_1779;
+ wire T_1780;
+ wire T_1781;
+ wire T_1783;
+ wire T_1784;
+ wire T_1785;
+ wire T_1786;
+ wire T_1788;
+ wire T_1789;
+ wire T_1790;
+ wire T_1791;
+ wire T_1793;
+ wire T_1794;
+ wire T_1796;
+ wire T_1797;
+ wire T_1798;
+ wire T_1799;
+ wire T_1801;
+ wire T_1802;
+ wire T_1804;
+ wire T_1805;
+ wire T_1806;
+ wire T_1807;
+ wire T_1809;
+ wire T_1810;
+ wire T_1812;
+ wire T_1813;
+ wire T_1814;
+ wire T_1815;
+ wire perm_ok;
+ wire T_1818;
+ wire T_1820;
+ wire T_1821;
+ wire T_1822;
+ wire set_dirty_bit;
+ wire T_1824;
+ wire T_1825;
+ wire T_1827;
+ wire T_1828;
+ wire [19:0] T_1844_ppn;
+ wire [2:0] T_1844_reserved_for_software;
+ wire T_1844_d;
+ wire T_1844_r;
+ wire [3:0] T_1844_typ;
+ wire T_1844_v;
+ wire [19:0] pte_wdata_ppn;
+ wire [2:0] pte_wdata_reserved_for_software;
+ wire pte_wdata_d;
+ wire pte_wdata_r;
+ wire [3:0] pte_wdata_typ;
+ wire pte_wdata_v;
+ wire T_1865;
+ wire T_1866;
+ wire T_1867;
+ wire T_1869;
+ wire [4:0] T_1870;
+ wire [3:0] T_1872;
+ wire [23:0] T_1873;
+ wire [4:0] T_1874;
+ wire [5:0] T_1875;
+ wire [29:0] T_1876;
+ wire resp_err;
+ wire T_1878;
+ wire resp_val;
+ wire [27:0] r_resp_ppn;
+ wire [9:0] T_1881;
+ wire [17:0] T_1882;
+ wire [27:0] T_1883;
+ wire [18:0] T_1884;
+ wire [8:0] T_1885;
+ wire [27:0] T_1886;
+ wire [27:0] T_1888_0;
+ wire [27:0] T_1888_1;
+ wire [27:0] T_1888_2;
+ wire T_1895;
+ wire T_1896;
+ wire [27:0] GEN_2;
+ wire T_1898;
+ wire T_1899;
+ wire [27:0] GEN_3;
+ wire T_1900;
+ wire T_1902;
+ wire T_1904;
+ wire T_1905;
+ wire [2:0] T_1908;
+ wire [1:0] T_1909;
+ wire T_1911;
+ wire T_1912;
+ wire T_1913;
+ wire T_1915;
+ wire T_1916;
+ wire T_1918;
+ wire T_1919;
+ wire [2:0] T_1921;
+ wire [1:0] T_1922;
+ wire T_1924;
+ wire T_1925;
+ wire [2:0] T_1926;
+ wire T_1927;
+ wire T_1928;
+ wire T_1929;
+ wire T_1930;
+ wire GEN_4;
+ wire GEN_5;
+ wire GEN_6;
+ wire GEN_7;
+ wire GEN_8;
+ wire GEN_9;
+ wire GEN_10;
+ wire GEN_11;
+ wire GEN_12;
+ reg [8:0] GEN_13;
+ reg GEN_14;
+ RRArbiter_112 arb (
+ .clk(arb_clk),
+ .reset(arb_reset),
+ .io_in_0_ready(arb_io_in_0_ready),
+ .io_in_0_valid(arb_io_in_0_valid),
+ .io_in_0_bits_addr(arb_io_in_0_bits_addr),
+ .io_in_0_bits_prv(arb_io_in_0_bits_prv),
+ .io_in_0_bits_store(arb_io_in_0_bits_store),
+ .io_in_0_bits_fetch(arb_io_in_0_bits_fetch),
+ .io_in_1_ready(arb_io_in_1_ready),
+ .io_in_1_valid(arb_io_in_1_valid),
+ .io_in_1_bits_addr(arb_io_in_1_bits_addr),
+ .io_in_1_bits_prv(arb_io_in_1_bits_prv),
+ .io_in_1_bits_store(arb_io_in_1_bits_store),
+ .io_in_1_bits_fetch(arb_io_in_1_bits_fetch),
+ .io_out_ready(arb_io_out_ready),
+ .io_out_valid(arb_io_out_valid),
+ .io_out_bits_addr(arb_io_out_bits_addr),
+ .io_out_bits_prv(arb_io_out_bits_prv),
+ .io_out_bits_store(arb_io_out_bits_store),
+ .io_out_bits_fetch(arb_io_out_bits_fetch),
+ .io_chosen(arb_io_chosen)
+ );
+ assign io_requestor_0_req_ready = arb_io_in_0_ready;
+ assign io_requestor_0_resp_valid = T_1896;
+ assign io_requestor_0_resp_bits_error = resp_err;
+ assign io_requestor_0_resp_bits_pte_ppn = GEN_2;
+ assign io_requestor_0_resp_bits_pte_reserved_for_software = r_pte_reserved_for_software;
+ assign io_requestor_0_resp_bits_pte_d = r_pte_d;
+ assign io_requestor_0_resp_bits_pte_r = r_pte_r;
+ assign io_requestor_0_resp_bits_pte_typ = r_pte_typ;
+ assign io_requestor_0_resp_bits_pte_v = r_pte_v;
+ assign io_requestor_0_status_sd = io_dpath_status_sd;
+ assign io_requestor_0_status_zero2 = io_dpath_status_zero2;
+ assign io_requestor_0_status_sd_rv32 = io_dpath_status_sd_rv32;
+ assign io_requestor_0_status_zero1 = io_dpath_status_zero1;
+ assign io_requestor_0_status_vm = io_dpath_status_vm;
+ assign io_requestor_0_status_mprv = io_dpath_status_mprv;
+ assign io_requestor_0_status_xs = io_dpath_status_xs;
+ assign io_requestor_0_status_fs = io_dpath_status_fs;
+ assign io_requestor_0_status_prv3 = io_dpath_status_prv3;
+ assign io_requestor_0_status_ie3 = io_dpath_status_ie3;
+ assign io_requestor_0_status_prv2 = io_dpath_status_prv2;
+ assign io_requestor_0_status_ie2 = io_dpath_status_ie2;
+ assign io_requestor_0_status_prv1 = io_dpath_status_prv1;
+ assign io_requestor_0_status_ie1 = io_dpath_status_ie1;
+ assign io_requestor_0_status_prv = io_dpath_status_prv;
+ assign io_requestor_0_status_ie = io_dpath_status_ie;
+ assign io_requestor_0_invalidate = io_dpath_invalidate;
+ assign io_requestor_1_req_ready = arb_io_in_1_ready;
+ assign io_requestor_1_resp_valid = T_1899;
+ assign io_requestor_1_resp_bits_error = resp_err;
+ assign io_requestor_1_resp_bits_pte_ppn = GEN_3;
+ assign io_requestor_1_resp_bits_pte_reserved_for_software = r_pte_reserved_for_software;
+ assign io_requestor_1_resp_bits_pte_d = r_pte_d;
+ assign io_requestor_1_resp_bits_pte_r = r_pte_r;
+ assign io_requestor_1_resp_bits_pte_typ = r_pte_typ;
+ assign io_requestor_1_resp_bits_pte_v = r_pte_v;
+ assign io_requestor_1_status_sd = io_dpath_status_sd;
+ assign io_requestor_1_status_zero2 = io_dpath_status_zero2;
+ assign io_requestor_1_status_sd_rv32 = io_dpath_status_sd_rv32;
+ assign io_requestor_1_status_zero1 = io_dpath_status_zero1;
+ assign io_requestor_1_status_vm = io_dpath_status_vm;
+ assign io_requestor_1_status_mprv = io_dpath_status_mprv;
+ assign io_requestor_1_status_xs = io_dpath_status_xs;
+ assign io_requestor_1_status_fs = io_dpath_status_fs;
+ assign io_requestor_1_status_prv3 = io_dpath_status_prv3;
+ assign io_requestor_1_status_ie3 = io_dpath_status_ie3;
+ assign io_requestor_1_status_prv2 = io_dpath_status_prv2;
+ assign io_requestor_1_status_ie2 = io_dpath_status_ie2;
+ assign io_requestor_1_status_prv1 = io_dpath_status_prv1;
+ assign io_requestor_1_status_ie1 = io_dpath_status_ie1;
+ assign io_requestor_1_status_prv = io_dpath_status_prv;
+ assign io_requestor_1_status_ie = io_dpath_status_ie;
+ assign io_requestor_1_invalidate = io_dpath_invalidate;
+ assign io_mem_req_valid = T_1902 ? T_1905 ? 1'h0 : T_1867 : T_1867;
+ assign io_mem_req_bits_addr = pte_addr;
+ assign io_mem_req_bits_tag = GEN_13;
+ assign io_mem_req_bits_cmd = T_1870;
+ assign io_mem_req_bits_typ = 3'h3;
+ assign io_mem_req_bits_kill = 1'h0;
+ assign io_mem_req_bits_phys = 1'h1;
+ assign io_mem_req_bits_data = T_1876;
+ assign io_mem_invalidate_lr = GEN_14;
+ assign T_1590 = r_req_addr[26:18];
+ assign T_1591 = T_1590;
+ assign T_1592 = r_req_addr[26:9];
+ assign T_1593 = T_1592[8:0];
+ assign T_1594 = r_req_addr[26:0];
+ assign T_1595 = T_1594[8:0];
+ assign T_1597_0 = T_1591;
+ assign T_1597_1 = T_1593;
+ assign T_1597_2 = T_1595;
+ assign arb_clk = clk;
+ assign arb_reset = reset;
+ assign arb_io_in_0_valid = io_requestor_0_req_valid;
+ assign arb_io_in_0_bits_addr = io_requestor_0_req_bits_addr;
+ assign arb_io_in_0_bits_prv = io_requestor_0_req_bits_prv;
+ assign arb_io_in_0_bits_store = io_requestor_0_req_bits_store;
+ assign arb_io_in_0_bits_fetch = io_requestor_0_req_bits_fetch;
+ assign arb_io_in_1_valid = io_requestor_1_req_valid;
+ assign arb_io_in_1_bits_addr = io_requestor_1_req_bits_addr;
+ assign arb_io_in_1_bits_prv = io_requestor_1_req_bits_prv;
+ assign arb_io_in_1_bits_store = io_requestor_1_req_bits_store;
+ assign arb_io_in_1_bits_fetch = io_requestor_1_req_bits_fetch;
+ assign arb_io_out_ready = T_1609;
+ assign T_1609 = state == 1'h0;
+ assign pte_ppn = T_1636;
+ assign pte_reserved_for_software = T_1635;
+ assign pte_d = T_1634;
+ assign pte_r = T_1633;
+ assign pte_typ = T_1632;
+ assign pte_v = T_1631;
+ assign T_1631 = io_mem_resp_bits_data[0];
+ assign T_1632 = io_mem_resp_bits_data[4:1];
+ assign T_1633 = io_mem_resp_bits_data[5];
+ assign T_1634 = io_mem_resp_bits_data[6];
+ assign T_1635 = io_mem_resp_bits_data[9:7];
+ assign T_1636 = io_mem_resp_bits_data[29:10];
+ assign GEN_0 = GEN_4 ? T_1597_2 : GEN_5 ? T_1597_1 : T_1597_0;
+ assign T_1637 = {r_pte_ppn,GEN_0};
+ assign pte_addr = T_1637 << 3;
+ assign T_1639 = arb_io_out_ready & arb_io_out_valid;
+ assign T_1640 = io_dpath_ptbr[31:12];
+ assign T_1657 = {T_1652_1,T_1652_0};
+ assign T_1658 = {T_1652_2,T_1657};
+ assign T_1661_T_1666_addr = 1'h0;
+ assign T_1661_T_1666_en = 1'h1;
+ assign T_1661_T_1666_clk = clk;
+ assign T_1661_T_1666_data = T_1661[T_1661_T_1666_addr];
+ assign T_1661_T_1669_addr = 1'h1;
+ assign T_1661_T_1669_en = 1'h1;
+ assign T_1661_T_1669_clk = clk;
+ assign T_1661_T_1669_data = T_1661[T_1661_T_1669_addr];
+ assign T_1661_T_1672_addr = 2'h2;
+ assign T_1661_T_1672_en = 1'h1;
+ assign T_1661_T_1672_clk = clk;
+ assign T_1661_T_1672_data = T_1661[T_1661_T_1672_addr];
+ assign T_1661_T_1721_data = pte_addr;
+ assign T_1661_T_1721_addr = T_1718;
+ assign T_1661_T_1721_mask = T_1691 ? 1'h1 : 1'h0;
+ assign T_1661_T_1721_en = T_1691 ? 1'h1 : 1'h0;
+ assign T_1661_T_1721_clk = clk;
+ assign T_1664_T_1761_addr = 1'h0;
+ assign T_1664_T_1761_en = 1'h1;
+ assign T_1664_T_1761_clk = clk;
+ assign T_1664_T_1761_data = T_1664[T_1664_T_1761_addr];
+ assign T_1664_T_1763_addr = 1'h1;
+ assign T_1664_T_1763_en = 1'h1;
+ assign T_1664_T_1763_clk = clk;
+ assign T_1664_T_1763_data = T_1664[T_1664_T_1763_addr];
+ assign T_1664_T_1765_addr = 2'h2;
+ assign T_1664_T_1765_en = 1'h1;
+ assign T_1664_T_1765_clk = clk;
+ assign T_1664_T_1765_data = T_1664[T_1664_T_1765_addr];
+ assign T_1664_T_1722_data = pte_ppn;
+ assign T_1664_T_1722_addr = T_1718;
+ assign T_1664_T_1722_mask = T_1691 ? 1'h1 : 1'h0;
+ assign T_1664_T_1722_en = T_1691 ? 1'h1 : 1'h0;
+ assign T_1664_T_1722_clk = clk;
+ assign T_1667 = T_1661_T_1666_data == pte_addr;
+ assign T_1670 = T_1661_T_1669_data == pte_addr;
+ assign T_1673 = T_1661_T_1672_data == pte_addr;
+ assign T_1675_0 = T_1667;
+ assign T_1675_1 = T_1670;
+ assign T_1675_2 = T_1673;
+ assign T_1680 = {T_1675_1,T_1675_0};
+ assign T_1681 = {T_1675_2,T_1680};
+ assign T_1682 = T_1681 & T_1658;
+ assign pte_cache_hit = T_1682 != 1'h0;
+ assign T_1686 = pte_typ < 2'h2;
+ assign T_1687 = pte_v & T_1686;
+ assign T_1688 = io_mem_resp_valid & T_1687;
+ assign T_1690 = pte_cache_hit == 1'h0;
+ assign T_1691 = T_1688 & T_1690;
+ assign T_1692 = ~ T_1658;
+ assign T_1694 = T_1692 == 1'h0;
+ assign T_1696 = T_1642 >> 1'h1;
+ assign T_1697 = T_1696[0];
+ assign T_1698 = {1'h1,T_1697};
+ assign T_1699 = T_1642 >> T_1698;
+ assign T_1700 = T_1699[0];
+ assign T_1701 = {T_1698,T_1700};
+ assign T_1702 = T_1701[1:0];
+ assign T_1703 = ~ T_1658;
+ assign T_1704 = T_1703[0];
+ assign T_1705 = T_1703[1];
+ assign T_1706 = T_1703[2];
+ assign T_1708_0 = T_1704;
+ assign T_1708_1 = T_1705;
+ assign T_1708_2 = T_1706;
+ assign T_1716 = T_1708_1 ? 1'h1 : 2'h2;
+ assign T_1717 = T_1708_0 ? 1'h0 : T_1716;
+ assign T_1718 = T_1694 ? T_1702 : T_1717;
+ assign GEN_1 = 1'h1;
+ assign T_1723 = state == 1'h1;
+ assign T_1724 = pte_cache_hit & T_1723;
+ assign T_1725 = T_1682[2];
+ assign T_1726 = T_1682[1:0];
+ assign T_1728 = T_1725 != 1'h0;
+ assign T_1729 = T_1725 | T_1726;
+ assign T_1730 = T_1729[1];
+ assign T_1731 = {T_1728,T_1730};
+ assign T_1733 = T_1731[1];
+ assign T_1735 = 3'h1 << 1'h1;
+ assign T_1736 = T_1735[2:0];
+ assign T_1737 = ~ T_1736;
+ assign T_1738 = T_1642 & T_1737;
+ assign T_1740 = T_1733 ? 1'h0 : T_1736;
+ assign T_1741 = T_1738 | T_1740;
+ assign T_1742 = {1'h1,T_1733};
+ assign T_1743 = T_1731[0];
+ assign T_1745 = 3'h1 << T_1742;
+ assign T_1746 = T_1745[2:0];
+ assign T_1747 = ~ T_1746;
+ assign T_1748 = T_1741 & T_1747;
+ assign T_1750 = T_1743 ? 1'h0 : T_1746;
+ assign T_1751 = T_1748 | T_1750;
+ assign T_1752 = {T_1742,T_1743};
+ assign T_1753 = reset | io_dpath_invalidate;
+ assign T_1757 = T_1682[0];
+ assign T_1758 = T_1682[1];
+ assign T_1759 = T_1682[2];
+ assign T_1767 = T_1757 ? T_1664_T_1761_data : 1'h0;
+ assign T_1769 = T_1758 ? T_1664_T_1763_data : 1'h0;
+ assign T_1771 = T_1759 ? T_1664_T_1765_data : 1'h0;
+ assign T_1773 = T_1767 | T_1769;
+ assign T_1774 = T_1773 | T_1771;
+ assign pte_cache_data = T_1774;
+ assign T_1776 = r_req_prv[0];
+ assign T_1778 = pte_typ >= 3'h4;
+ assign T_1779 = pte_v & T_1778;
+ assign T_1780 = pte_typ[1];
+ assign T_1781 = T_1779 & T_1780;
+ assign T_1783 = pte_typ >= 2'h2;
+ assign T_1784 = pte_v & T_1783;
+ assign T_1785 = pte_typ[0];
+ assign T_1786 = T_1784 & T_1785;
+ assign T_1788 = pte_typ >= 2'h2;
+ assign T_1789 = pte_v & T_1788;
+ assign T_1790 = r_req_store ? T_1786 : T_1789;
+ assign T_1791 = r_req_fetch ? T_1781 : T_1790;
+ assign T_1793 = pte_typ >= 2'h2;
+ assign T_1794 = pte_v & T_1793;
+ assign T_1796 = pte_typ < 4'h8;
+ assign T_1797 = T_1794 & T_1796;
+ assign T_1798 = pte_typ[1];
+ assign T_1799 = T_1797 & T_1798;
+ assign T_1801 = pte_typ >= 2'h2;
+ assign T_1802 = pte_v & T_1801;
+ assign T_1804 = pte_typ < 4'h8;
+ assign T_1805 = T_1802 & T_1804;
+ assign T_1806 = pte_typ[0];
+ assign T_1807 = T_1805 & T_1806;
+ assign T_1809 = pte_typ >= 2'h2;
+ assign T_1810 = pte_v & T_1809;
+ assign T_1812 = pte_typ < 4'h8;
+ assign T_1813 = T_1810 & T_1812;
+ assign T_1814 = r_req_store ? T_1807 : T_1813;
+ assign T_1815 = r_req_fetch ? T_1799 : T_1814;
+ assign perm_ok = T_1776 ? T_1791 : T_1815;
+ assign T_1818 = pte_r == 1'h0;
+ assign T_1820 = pte_d == 1'h0;
+ assign T_1821 = r_req_store & T_1820;
+ assign T_1822 = T_1818 | T_1821;
+ assign set_dirty_bit = perm_ok & T_1822;
+ assign T_1824 = state == 2'h2;
+ assign T_1825 = io_mem_resp_valid & T_1824;
+ assign T_1827 = set_dirty_bit == 1'h0;
+ assign T_1828 = T_1825 & T_1827;
+ assign T_1844_ppn = 20'h0;
+ assign T_1844_reserved_for_software = 3'h0;
+ assign T_1844_d = 1'h0;
+ assign T_1844_r = 1'h0;
+ assign T_1844_typ = 4'h0;
+ assign T_1844_v = 1'h0;
+ assign pte_wdata_ppn = T_1844_ppn;
+ assign pte_wdata_reserved_for_software = T_1844_reserved_for_software;
+ assign pte_wdata_d = r_req_store;
+ assign pte_wdata_r = 1'h1;
+ assign pte_wdata_typ = T_1844_typ;
+ assign pte_wdata_v = T_1844_v;
+ assign T_1865 = state == 1'h1;
+ assign T_1866 = state == 2'h3;
+ assign T_1867 = T_1865 | T_1866;
+ assign T_1869 = state == 2'h3;
+ assign T_1870 = T_1869 ? 5'ha : 5'h0;
+ assign T_1872 = {pte_wdata_reserved_for_software,pte_wdata_d};
+ assign T_1873 = {pte_wdata_ppn,T_1872};
+ assign T_1874 = {pte_wdata_typ,pte_wdata_v};
+ assign T_1875 = {pte_wdata_r,T_1874};
+ assign T_1876 = {T_1873,T_1875};
+ assign resp_err = state == 3'h6;
+ assign T_1878 = state == 3'h5;
+ assign resp_val = T_1878 | resp_err;
+ assign r_resp_ppn = io_mem_req_bits_addr[39:12];
+ assign T_1881 = r_resp_ppn[27:18];
+ assign T_1882 = r_req_addr[17:0];
+ assign T_1883 = {T_1881,T_1882};
+ assign T_1884 = r_resp_ppn[27:9];
+ assign T_1885 = r_req_addr[8:0];
+ assign T_1886 = {T_1884,T_1885};
+ assign T_1888_0 = T_1883;
+ assign T_1888_1 = T_1886;
+ assign T_1888_2 = r_resp_ppn;
+ assign T_1895 = r_req_dest == 1'h0;
+ assign T_1896 = resp_val & T_1895;
+ assign GEN_2 = GEN_9 ? T_1888_2 : GEN_10 ? T_1888_1 : T_1888_0;
+ assign T_1898 = r_req_dest == 1'h1;
+ assign T_1899 = resp_val & T_1898;
+ assign GEN_3 = GEN_11 ? T_1888_2 : GEN_12 ? T_1888_1 : T_1888_0;
+ assign T_1900 = 1'h0 == state;
+ assign T_1902 = 1'h1 == state;
+ assign T_1904 = count < 2'h2;
+ assign T_1905 = pte_cache_hit & T_1904;
+ assign T_1908 = count + 1'h1;
+ assign T_1909 = T_1908[1:0];
+ assign T_1911 = T_1905 == 1'h0;
+ assign T_1912 = T_1911 & io_mem_req_ready;
+ assign T_1913 = 2'h2 == state;
+ assign T_1915 = pte_typ < 2'h2;
+ assign T_1916 = pte_v & T_1915;
+ assign T_1918 = count < 2'h2;
+ assign T_1919 = T_1916 & T_1918;
+ assign T_1921 = count + 1'h1;
+ assign T_1922 = T_1921[1:0];
+ assign T_1924 = pte_typ >= 2'h2;
+ assign T_1925 = pte_v & T_1924;
+ assign T_1926 = set_dirty_bit ? 2'h3 : 3'h5;
+ assign T_1927 = 2'h3 == state;
+ assign T_1928 = 3'h4 == state;
+ assign T_1929 = 3'h5 == state;
+ assign T_1930 = 3'h6 == state;
+ assign GEN_4 = 2'h2 == count;
+ assign GEN_5 = 1'h1 == count;
+ assign GEN_6 = 1'h0 == T_1718;
+ assign GEN_7 = 1'h1 == T_1718;
+ assign GEN_8 = 2'h2 == T_1718;
+ assign GEN_9 = 2'h2 == count;
+ assign GEN_10 = 1'h1 == count;
+ assign GEN_11 = 2'h2 == count;
+ assign GEN_12 = 1'h1 == count;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ state = {1{$random}};
+ count = {1{$random}};
+ r_req_addr = {1{$random}};
+ r_req_prv = {1{$random}};
+ r_req_store = {1{$random}};
+ r_req_fetch = {1{$random}};
+ r_req_dest = {1{$random}};
+ r_pte_ppn = {1{$random}};
+ r_pte_reserved_for_software = {1{$random}};
+ r_pte_d = {1{$random}};
+ r_pte_r = {1{$random}};
+ r_pte_typ = {1{$random}};
+ r_pte_v = {1{$random}};
+ T_1642 = {1{$random}};
+ T_1652_0 = {1{$random}};
+ T_1652_1 = {1{$random}};
+ T_1652_2 = {1{$random}};
+ for (initvar = 0; initvar < 3; initvar = initvar+1)
+ T_1661[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 3; initvar = initvar+1)
+ T_1664[initvar] = {1{$random}};
+ GEN_13 = {1{$random}};
+ GEN_14 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1930) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1929) begin
+ state <= 1'h0;
+ end else begin
+ if(T_1928) begin
+ if(io_mem_resp_valid) begin
+ state <= 1'h1;
+ end else begin
+ if(io_mem_resp_bits_nack) begin
+ state <= 2'h3;
+ end else begin
+ if(T_1927) begin
+ if(io_mem_req_ready) begin
+ state <= 3'h4;
+ end else begin
+ if(T_1913) begin
+ if(io_mem_resp_valid) begin
+ if(T_1925) begin
+ state <= T_1926;
+ end else begin
+ if(T_1919) begin
+ state <= 1'h1;
+ end else begin
+ state <= 3'h6;
+ end
+ end
+ end else begin
+ if(io_mem_resp_bits_nack) begin
+ state <= 1'h1;
+ end else begin
+ if(T_1902) begin
+ if(T_1912) begin
+ state <= 2'h2;
+ end else begin
+ if(T_1905) begin
+ state <= 1'h1;
+ end else begin
+ if(T_1900) begin
+ if(arb_io_out_valid) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1900) begin
+ if(arb_io_out_valid) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1902) begin
+ if(T_1912) begin
+ state <= 2'h2;
+ end else begin
+ if(T_1905) begin
+ state <= 1'h1;
+ end else begin
+ if(T_1900) begin
+ if(arb_io_out_valid) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1900) begin
+ if(arb_io_out_valid) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1913) begin
+ if(io_mem_resp_valid) begin
+ if(T_1925) begin
+ state <= T_1926;
+ end else begin
+ if(T_1919) begin
+ state <= 1'h1;
+ end else begin
+ state <= 3'h6;
+ end
+ end
+ end else begin
+ if(io_mem_resp_bits_nack) begin
+ state <= 1'h1;
+ end else begin
+ if(T_1902) begin
+ if(T_1912) begin
+ state <= 2'h2;
+ end else begin
+ if(T_1905) begin
+ state <= 1'h1;
+ end else begin
+ if(T_1900) begin
+ if(arb_io_out_valid) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1900) begin
+ if(arb_io_out_valid) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1902) begin
+ if(T_1912) begin
+ state <= 2'h2;
+ end else begin
+ if(T_1905) begin
+ state <= 1'h1;
+ end else begin
+ if(T_1900) begin
+ if(arb_io_out_valid) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1900) begin
+ if(arb_io_out_valid) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1927) begin
+ if(io_mem_req_ready) begin
+ state <= 3'h4;
+ end else begin
+ if(T_1913) begin
+ if(io_mem_resp_valid) begin
+ if(T_1925) begin
+ state <= T_1926;
+ end else begin
+ if(T_1919) begin
+ state <= 1'h1;
+ end else begin
+ state <= 3'h6;
+ end
+ end
+ end else begin
+ if(io_mem_resp_bits_nack) begin
+ state <= 1'h1;
+ end else begin
+ if(T_1902) begin
+ if(T_1912) begin
+ state <= 2'h2;
+ end else begin
+ if(T_1905) begin
+ state <= 1'h1;
+ end else begin
+ if(T_1900) begin
+ if(arb_io_out_valid) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1900) begin
+ if(arb_io_out_valid) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1902) begin
+ if(T_1912) begin
+ state <= 2'h2;
+ end else begin
+ if(T_1905) begin
+ state <= 1'h1;
+ end else begin
+ if(T_1900) begin
+ if(arb_io_out_valid) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1900) begin
+ if(arb_io_out_valid) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1913) begin
+ if(io_mem_resp_valid) begin
+ if(T_1925) begin
+ state <= T_1926;
+ end else begin
+ if(T_1919) begin
+ state <= 1'h1;
+ end else begin
+ state <= 3'h6;
+ end
+ end
+ end else begin
+ if(io_mem_resp_bits_nack) begin
+ state <= 1'h1;
+ end else begin
+ if(T_1902) begin
+ if(T_1912) begin
+ state <= 2'h2;
+ end else begin
+ if(T_1905) begin
+ state <= 1'h1;
+ end else begin
+ if(T_1900) begin
+ if(arb_io_out_valid) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1900) begin
+ if(arb_io_out_valid) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end else begin
+ if(T_1902) begin
+ if(T_1912) begin
+ state <= 2'h2;
+ end else begin
+ if(T_1905) begin
+ state <= 1'h1;
+ end else begin
+ if(T_1900) begin
+ if(arb_io_out_valid) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1900) begin
+ if(arb_io_out_valid) begin
+ state <= 1'h1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1913) begin
+ if(io_mem_resp_valid) begin
+ if(T_1919) begin
+ count <= T_1922;
+ end else begin
+ if(T_1902) begin
+ if(T_1905) begin
+ count <= T_1909;
+ end else begin
+ if(T_1900) begin
+ count <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1900) begin
+ count <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1902) begin
+ if(T_1905) begin
+ count <= T_1909;
+ end else begin
+ if(T_1900) begin
+ count <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1900) begin
+ count <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1902) begin
+ if(T_1905) begin
+ count <= T_1909;
+ end else begin
+ if(T_1900) begin
+ count <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_1900) begin
+ count <= 1'h0;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1639) begin
+ r_req_addr <= arb_io_out_bits_addr;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1639) begin
+ r_req_prv <= arb_io_out_bits_prv;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1639) begin
+ r_req_store <= arb_io_out_bits_store;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1639) begin
+ r_req_fetch <= arb_io_out_bits_fetch;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1639) begin
+ r_req_dest <= arb_io_chosen;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1902) begin
+ if(T_1905) begin
+ r_pte_ppn <= pte_cache_data;
+ end else begin
+ if(T_1828) begin
+ r_pte_ppn <= pte_ppn;
+ end else begin
+ if(T_1639) begin
+ r_pte_ppn <= T_1640;
+ end else begin
+ ;
+ end
+ end
+ end
+ end else begin
+ if(T_1828) begin
+ r_pte_ppn <= pte_ppn;
+ end else begin
+ if(T_1639) begin
+ r_pte_ppn <= T_1640;
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1828) begin
+ r_pte_reserved_for_software <= pte_reserved_for_software;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1828) begin
+ r_pte_d <= pte_d;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1828) begin
+ r_pte_r <= pte_r;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1828) begin
+ r_pte_typ <= pte_typ;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1828) begin
+ r_pte_v <= pte_v;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1724) begin
+ T_1642 <= T_1751;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1753) begin
+ T_1652_0 <= 1'h0;
+ end else begin
+ if(T_1691) begin
+ if(GEN_6) begin
+ T_1652_0 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1753) begin
+ T_1652_1 <= 1'h0;
+ end else begin
+ if(T_1691) begin
+ if(GEN_7) begin
+ T_1652_1 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1753) begin
+ T_1652_2 <= 1'h0;
+ end else begin
+ if(T_1691) begin
+ if(GEN_8) begin
+ T_1652_2 <= GEN_1;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end
+ end
+ always @(posedge T_1661_T_1721_clk) begin
+ if(T_1661_T_1721_en & T_1661_T_1721_mask) begin
+ T_1661[T_1661_T_1721_addr] <= T_1661_T_1721_data;
+ end
+ end
+ always @(posedge T_1664_T_1722_clk) begin
+ if(T_1664_T_1722_en & T_1664_T_1722_mask) begin
+ T_1664[T_1664_T_1722_addr] <= T_1664_T_1722_data;
+ end
+ end
+endmodule
+module HellaCacheArbiter(
+ input clk,
+ input reset,
+ output io_requestor_0_req_ready,
+ input io_requestor_0_req_valid,
+ input [39:0] io_requestor_0_req_bits_addr,
+ input [8:0] io_requestor_0_req_bits_tag,
+ input [4:0] io_requestor_0_req_bits_cmd,
+ input [2:0] io_requestor_0_req_bits_typ,
+ input io_requestor_0_req_bits_kill,
+ input io_requestor_0_req_bits_phys,
+ input [63:0] io_requestor_0_req_bits_data,
+ output io_requestor_0_resp_valid,
+ output [39:0] io_requestor_0_resp_bits_addr,
+ output [8:0] io_requestor_0_resp_bits_tag,
+ output [4:0] io_requestor_0_resp_bits_cmd,
+ output [2:0] io_requestor_0_resp_bits_typ,
+ output [63:0] io_requestor_0_resp_bits_data,
+ output io_requestor_0_resp_bits_nack,
+ output io_requestor_0_resp_bits_replay,
+ output io_requestor_0_resp_bits_has_data,
+ output [63:0] io_requestor_0_resp_bits_data_word_bypass,
+ output [63:0] io_requestor_0_resp_bits_store_data,
+ output io_requestor_0_replay_next_valid,
+ output [8:0] io_requestor_0_replay_next_bits,
+ output io_requestor_0_xcpt_ma_ld,
+ output io_requestor_0_xcpt_ma_st,
+ output io_requestor_0_xcpt_pf_ld,
+ output io_requestor_0_xcpt_pf_st,
+ input io_requestor_0_invalidate_lr,
+ output io_requestor_0_ordered,
+ output io_requestor_1_req_ready,
+ input io_requestor_1_req_valid,
+ input [39:0] io_requestor_1_req_bits_addr,
+ input [8:0] io_requestor_1_req_bits_tag,
+ input [4:0] io_requestor_1_req_bits_cmd,
+ input [2:0] io_requestor_1_req_bits_typ,
+ input io_requestor_1_req_bits_kill,
+ input io_requestor_1_req_bits_phys,
+ input [63:0] io_requestor_1_req_bits_data,
+ output io_requestor_1_resp_valid,
+ output [39:0] io_requestor_1_resp_bits_addr,
+ output [8:0] io_requestor_1_resp_bits_tag,
+ output [4:0] io_requestor_1_resp_bits_cmd,
+ output [2:0] io_requestor_1_resp_bits_typ,
+ output [63:0] io_requestor_1_resp_bits_data,
+ output io_requestor_1_resp_bits_nack,
+ output io_requestor_1_resp_bits_replay,
+ output io_requestor_1_resp_bits_has_data,
+ output [63:0] io_requestor_1_resp_bits_data_word_bypass,
+ output [63:0] io_requestor_1_resp_bits_store_data,
+ output io_requestor_1_replay_next_valid,
+ output [8:0] io_requestor_1_replay_next_bits,
+ output io_requestor_1_xcpt_ma_ld,
+ output io_requestor_1_xcpt_ma_st,
+ output io_requestor_1_xcpt_pf_ld,
+ output io_requestor_1_xcpt_pf_st,
+ input io_requestor_1_invalidate_lr,
+ output io_requestor_1_ordered,
+ input io_mem_req_ready,
+ output io_mem_req_valid,
+ output [39:0] io_mem_req_bits_addr,
+ output [8:0] io_mem_req_bits_tag,
+ output [4:0] io_mem_req_bits_cmd,
+ output [2:0] io_mem_req_bits_typ,
+ output io_mem_req_bits_kill,
+ output io_mem_req_bits_phys,
+ output [63:0] io_mem_req_bits_data,
+ input io_mem_resp_valid,
+ input [39:0] io_mem_resp_bits_addr,
+ input [8:0] io_mem_resp_bits_tag,
+ input [4:0] io_mem_resp_bits_cmd,
+ input [2:0] io_mem_resp_bits_typ,
+ input [63:0] io_mem_resp_bits_data,
+ input io_mem_resp_bits_nack,
+ input io_mem_resp_bits_replay,
+ input io_mem_resp_bits_has_data,
+ input [63:0] io_mem_resp_bits_data_word_bypass,
+ input [63:0] io_mem_resp_bits_store_data,
+ input io_mem_replay_next_valid,
+ input [8:0] io_mem_replay_next_bits,
+ input io_mem_xcpt_ma_ld,
+ input io_mem_xcpt_ma_st,
+ input io_mem_xcpt_pf_ld,
+ input io_mem_xcpt_pf_st,
+ output io_mem_invalidate_lr,
+ input io_mem_ordered
+);
+ reg T_5286;
+ reg T_5287;
+ wire T_5288;
+ wire T_5290;
+ wire T_5291;
+ wire [9:0] T_5293;
+ wire [9:0] T_5295;
+ wire T_5296;
+ wire T_5298;
+ wire T_5299;
+ wire [7:0] T_5300;
+ wire T_5301;
+ wire T_5302;
+ wire T_5303;
+ wire T_5305;
+ wire T_5306;
+ wire [7:0] T_5307;
+ wire T_5308;
+ wire T_5310;
+ wire T_5311;
+ wire [7:0] T_5312;
+ wire T_5313;
+ wire T_5314;
+ wire T_5315;
+ wire T_5317;
+ wire T_5318;
+ wire [7:0] T_5319;
+ reg GEN_0;
+ assign io_requestor_0_req_ready = io_mem_req_ready;
+ assign io_requestor_0_resp_valid = T_5299;
+ assign io_requestor_0_resp_bits_addr = io_mem_resp_bits_addr;
+ assign io_requestor_0_resp_bits_tag = T_5300;
+ assign io_requestor_0_resp_bits_cmd = io_mem_resp_bits_cmd;
+ assign io_requestor_0_resp_bits_typ = io_mem_resp_bits_typ;
+ assign io_requestor_0_resp_bits_data = io_mem_resp_bits_data;
+ assign io_requestor_0_resp_bits_nack = T_5301;
+ assign io_requestor_0_resp_bits_replay = T_5302;
+ assign io_requestor_0_resp_bits_has_data = io_mem_resp_bits_has_data;
+ assign io_requestor_0_resp_bits_data_word_bypass = io_mem_resp_bits_data_word_bypass;
+ assign io_requestor_0_resp_bits_store_data = io_mem_resp_bits_store_data;
+ assign io_requestor_0_replay_next_valid = T_5306;
+ assign io_requestor_0_replay_next_bits = T_5307;
+ assign io_requestor_0_xcpt_ma_ld = io_mem_xcpt_ma_ld;
+ assign io_requestor_0_xcpt_ma_st = io_mem_xcpt_ma_st;
+ assign io_requestor_0_xcpt_pf_ld = io_mem_xcpt_pf_ld;
+ assign io_requestor_0_xcpt_pf_st = io_mem_xcpt_pf_st;
+ assign io_requestor_0_ordered = io_mem_ordered;
+ assign io_requestor_1_req_ready = T_5291;
+ assign io_requestor_1_resp_valid = T_5311;
+ assign io_requestor_1_resp_bits_addr = io_mem_resp_bits_addr;
+ assign io_requestor_1_resp_bits_tag = T_5312;
+ assign io_requestor_1_resp_bits_cmd = io_mem_resp_bits_cmd;
+ assign io_requestor_1_resp_bits_typ = io_mem_resp_bits_typ;
+ assign io_requestor_1_resp_bits_data = io_mem_resp_bits_data;
+ assign io_requestor_1_resp_bits_nack = T_5313;
+ assign io_requestor_1_resp_bits_replay = T_5314;
+ assign io_requestor_1_resp_bits_has_data = io_mem_resp_bits_has_data;
+ assign io_requestor_1_resp_bits_data_word_bypass = io_mem_resp_bits_data_word_bypass;
+ assign io_requestor_1_resp_bits_store_data = io_mem_resp_bits_store_data;
+ assign io_requestor_1_replay_next_valid = T_5318;
+ assign io_requestor_1_replay_next_bits = T_5319;
+ assign io_requestor_1_xcpt_ma_ld = io_mem_xcpt_ma_ld;
+ assign io_requestor_1_xcpt_ma_st = io_mem_xcpt_ma_st;
+ assign io_requestor_1_xcpt_pf_ld = io_mem_xcpt_pf_ld;
+ assign io_requestor_1_xcpt_pf_st = io_mem_xcpt_pf_st;
+ assign io_requestor_1_ordered = io_mem_ordered;
+ assign io_mem_req_valid = T_5288;
+ assign io_mem_req_bits_addr = io_requestor_0_req_valid ? io_requestor_0_req_bits_addr : io_requestor_1_req_bits_addr;
+ assign io_mem_req_bits_tag = io_requestor_0_req_valid ? T_5295 : T_5293;
+ assign io_mem_req_bits_cmd = io_requestor_0_req_valid ? io_requestor_0_req_bits_cmd : io_requestor_1_req_bits_cmd;
+ assign io_mem_req_bits_typ = io_requestor_0_req_valid ? io_requestor_0_req_bits_typ : io_requestor_1_req_bits_typ;
+ assign io_mem_req_bits_kill = T_5286 ? io_requestor_0_req_bits_kill : io_requestor_1_req_bits_kill;
+ assign io_mem_req_bits_phys = io_requestor_0_req_valid ? io_requestor_0_req_bits_phys : io_requestor_1_req_bits_phys;
+ assign io_mem_req_bits_data = T_5286 ? io_requestor_0_req_bits_data : io_requestor_1_req_bits_data;
+ assign io_mem_invalidate_lr = GEN_0;
+ assign T_5288 = io_requestor_0_req_valid | io_requestor_1_req_valid;
+ assign T_5290 = io_requestor_0_req_valid == 1'h0;
+ assign T_5291 = io_requestor_0_req_ready & T_5290;
+ assign T_5293 = {io_requestor_1_req_bits_tag,1'h1};
+ assign T_5295 = {io_requestor_0_req_bits_tag,1'h0};
+ assign T_5296 = io_mem_resp_bits_tag[0];
+ assign T_5298 = T_5296 == 1'h0;
+ assign T_5299 = io_mem_resp_valid & T_5298;
+ assign T_5300 = io_mem_resp_bits_tag[8:1];
+ assign T_5301 = io_mem_resp_bits_nack & T_5298;
+ assign T_5302 = io_mem_resp_bits_replay & T_5298;
+ assign T_5303 = io_mem_replay_next_bits[0];
+ assign T_5305 = T_5303 == 1'h0;
+ assign T_5306 = io_mem_replay_next_valid & T_5305;
+ assign T_5307 = io_mem_replay_next_bits[8:1];
+ assign T_5308 = io_mem_resp_bits_tag[0];
+ assign T_5310 = T_5308 == 1'h1;
+ assign T_5311 = io_mem_resp_valid & T_5310;
+ assign T_5312 = io_mem_resp_bits_tag[8:1];
+ assign T_5313 = io_mem_resp_bits_nack & T_5310;
+ assign T_5314 = io_mem_resp_bits_replay & T_5310;
+ assign T_5315 = io_mem_replay_next_bits[0];
+ assign T_5317 = T_5315 == 1'h1;
+ assign T_5318 = io_mem_replay_next_valid & T_5317;
+ assign T_5319 = io_mem_replay_next_bits[8:1];
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_5286 = {1{$random}};
+ T_5287 = {1{$random}};
+ GEN_0 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(1'h0) begin
+ ;
+ end else begin
+ T_5286 <= io_requestor_0_req_valid;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ T_5287 <= io_requestor_1_req_valid;
+ end
+ end
+endmodule
+module FPUDecoder(
+ input clk,
+ input reset,
+ input [31:0] io_inst,
+ output [4:0] io_sigs_cmd,
+ output io_sigs_ldst,
+ output io_sigs_wen,
+ output io_sigs_ren1,
+ output io_sigs_ren2,
+ output io_sigs_ren3,
+ output io_sigs_swap12,
+ output io_sigs_swap23,
+ output io_sigs_single,
+ output io_sigs_fromint,
+ output io_sigs_toint,
+ output io_sigs_fastpipe,
+ output io_sigs_fma,
+ output io_sigs_div,
+ output io_sigs_sqrt,
+ output io_sigs_round,
+ output io_sigs_wflags
+);
+ wire [31:0] T_42;
+ wire T_44;
+ wire [31:0] T_46;
+ wire T_48;
+ wire T_50;
+ wire T_51;
+ wire [31:0] T_53;
+ wire T_55;
+ wire [31:0] T_57;
+ wire T_59;
+ wire T_61;
+ wire T_62;
+ wire [31:0] T_64;
+ wire T_66;
+ wire [31:0] T_68;
+ wire T_70;
+ wire T_72;
+ wire T_73;
+ wire [31:0] T_75;
+ wire T_77;
+ wire T_79;
+ wire T_80;
+ wire [31:0] T_82;
+ wire T_84;
+ wire T_86;
+ wire [1:0] T_87;
+ wire [2:0] T_88;
+ wire [3:0] T_89;
+ wire [4:0] T_90;
+ wire T_92;
+ wire [31:0] T_94;
+ wire T_96;
+ wire [31:0] T_98;
+ wire T_100;
+ wire [31:0] T_102;
+ wire T_104;
+ wire T_106;
+ wire T_107;
+ wire T_108;
+ wire [31:0] T_110;
+ wire T_112;
+ wire [31:0] T_114;
+ wire T_116;
+ wire [31:0] T_118;
+ wire T_120;
+ wire T_122;
+ wire T_123;
+ wire T_124;
+ wire [31:0] T_126;
+ wire T_128;
+ wire [31:0] T_130;
+ wire T_132;
+ wire T_134;
+ wire T_135;
+ wire T_136;
+ wire T_138;
+ wire [31:0] T_140;
+ wire T_142;
+ wire T_144;
+ wire T_145;
+ wire [31:0] T_147;
+ wire T_149;
+ wire T_151;
+ wire [31:0] T_153;
+ wire T_155;
+ wire [31:0] T_157;
+ wire T_159;
+ wire T_161;
+ wire T_162;
+ wire [31:0] T_164;
+ wire T_166;
+ wire T_168;
+ wire [31:0] T_170;
+ wire T_172;
+ wire T_174;
+ wire T_175;
+ wire [31:0] T_177;
+ wire T_179;
+ wire [31:0] T_181;
+ wire T_183;
+ wire T_185;
+ wire T_186;
+ wire [31:0] T_188;
+ wire T_190;
+ wire [31:0] T_192;
+ wire T_194;
+ wire T_196;
+ wire T_197;
+ wire T_198;
+ wire [31:0] T_200;
+ wire T_202;
+ wire T_204;
+ wire [31:0] T_206;
+ wire T_208;
+ wire T_210;
+ wire [31:0] T_212;
+ wire T_214;
+ wire [31:0] T_216;
+ wire T_218;
+ wire T_220;
+ wire T_221;
+ wire T_222;
+ wire [31:0] T_224;
+ wire T_226;
+ wire [31:0] T_228;
+ wire T_230;
+ wire T_232;
+ wire T_233;
+ wire T_234;
+ wire T_235;
+ assign io_sigs_cmd = T_90;
+ assign io_sigs_ldst = T_92;
+ assign io_sigs_wen = T_108;
+ assign io_sigs_ren1 = T_124;
+ assign io_sigs_ren2 = T_136;
+ assign io_sigs_ren3 = T_138;
+ assign io_sigs_swap12 = T_145;
+ assign io_sigs_swap23 = T_151;
+ assign io_sigs_single = T_162;
+ assign io_sigs_fromint = T_168;
+ assign io_sigs_toint = T_175;
+ assign io_sigs_fastpipe = T_186;
+ assign io_sigs_fma = T_198;
+ assign io_sigs_div = T_204;
+ assign io_sigs_sqrt = T_210;
+ assign io_sigs_round = T_222;
+ assign io_sigs_wflags = T_235;
+ assign T_42 = io_inst & 32'h4;
+ assign T_44 = T_42 == 32'h4;
+ assign T_46 = io_inst & 32'h8000010;
+ assign T_48 = T_46 == 32'h8000010;
+ assign T_50 = 1'h0 | T_44;
+ assign T_51 = T_50 | T_48;
+ assign T_53 = io_inst & 32'h8;
+ assign T_55 = T_53 == 32'h8;
+ assign T_57 = io_inst & 32'h10000010;
+ assign T_59 = T_57 == 32'h10000010;
+ assign T_61 = 1'h0 | T_55;
+ assign T_62 = T_61 | T_59;
+ assign T_64 = io_inst & 32'h40;
+ assign T_66 = T_64 == 32'h0;
+ assign T_68 = io_inst & 32'h20000000;
+ assign T_70 = T_68 == 32'h20000000;
+ assign T_72 = 1'h0 | T_66;
+ assign T_73 = T_72 | T_70;
+ assign T_75 = io_inst & 32'h40000000;
+ assign T_77 = T_75 == 32'h40000000;
+ assign T_79 = 1'h0 | T_66;
+ assign T_80 = T_79 | T_77;
+ assign T_82 = io_inst & 32'h10;
+ assign T_84 = T_82 == 32'h0;
+ assign T_86 = 1'h0 | T_84;
+ assign T_87 = {T_62,T_51};
+ assign T_88 = {T_73,T_87};
+ assign T_89 = {T_80,T_88};
+ assign T_90 = {T_86,T_89};
+ assign T_92 = 1'h0 | T_66;
+ assign T_94 = io_inst & 32'h80000020;
+ assign T_96 = T_94 == 32'h0;
+ assign T_98 = io_inst & 32'h30;
+ assign T_100 = T_98 == 32'h0;
+ assign T_102 = io_inst & 32'h10000020;
+ assign T_104 = T_102 == 32'h10000000;
+ assign T_106 = 1'h0 | T_96;
+ assign T_107 = T_106 | T_100;
+ assign T_108 = T_107 | T_104;
+ assign T_110 = io_inst & 32'h80000004;
+ assign T_112 = T_110 == 32'h0;
+ assign T_114 = io_inst & 32'h10000004;
+ assign T_116 = T_114 == 32'h0;
+ assign T_118 = io_inst & 32'h50;
+ assign T_120 = T_118 == 32'h40;
+ assign T_122 = 1'h0 | T_112;
+ assign T_123 = T_122 | T_116;
+ assign T_124 = T_123 | T_120;
+ assign T_126 = io_inst & 32'h40000004;
+ assign T_128 = T_126 == 32'h0;
+ assign T_130 = io_inst & 32'h20;
+ assign T_132 = T_130 == 32'h20;
+ assign T_134 = 1'h0 | T_128;
+ assign T_135 = T_134 | T_132;
+ assign T_136 = T_135 | T_120;
+ assign T_138 = 1'h0 | T_120;
+ assign T_140 = io_inst & 32'h50000010;
+ assign T_142 = T_140 == 32'h50000010;
+ assign T_144 = 1'h0 | T_66;
+ assign T_145 = T_144 | T_142;
+ assign T_147 = io_inst & 32'h30000010;
+ assign T_149 = T_147 == 32'h10;
+ assign T_151 = 1'h0 | T_149;
+ assign T_153 = io_inst & 32'h1040;
+ assign T_155 = T_153 == 32'h0;
+ assign T_157 = io_inst & 32'h2000040;
+ assign T_159 = T_157 == 32'h40;
+ assign T_161 = 1'h0 | T_155;
+ assign T_162 = T_161 | T_159;
+ assign T_164 = io_inst & 32'h90000010;
+ assign T_166 = T_164 == 32'h90000010;
+ assign T_168 = 1'h0 | T_166;
+ assign T_170 = io_inst & 32'h90000010;
+ assign T_172 = T_170 == 32'h80000010;
+ assign T_174 = 1'h0 | T_132;
+ assign T_175 = T_174 | T_172;
+ assign T_177 = io_inst & 32'ha0000010;
+ assign T_179 = T_177 == 32'h20000010;
+ assign T_181 = io_inst & 32'hd0000010;
+ assign T_183 = T_181 == 32'h40000010;
+ assign T_185 = 1'h0 | T_179;
+ assign T_186 = T_185 | T_183;
+ assign T_188 = io_inst & 32'h70000004;
+ assign T_190 = T_188 == 32'h0;
+ assign T_192 = io_inst & 32'h68000004;
+ assign T_194 = T_192 == 32'h0;
+ assign T_196 = 1'h0 | T_190;
+ assign T_197 = T_196 | T_194;
+ assign T_198 = T_197 | T_120;
+ assign T_200 = io_inst & 32'h58000010;
+ assign T_202 = T_200 == 32'h18000010;
+ assign T_204 = 1'h0 | T_202;
+ assign T_206 = io_inst & 32'hd0000010;
+ assign T_208 = T_206 == 32'h50000010;
+ assign T_210 = 1'h0 | T_208;
+ assign T_212 = io_inst & 32'h20000004;
+ assign T_214 = T_212 == 32'h0;
+ assign T_216 = io_inst & 32'h40002000;
+ assign T_218 = T_216 == 32'h40000000;
+ assign T_220 = 1'h0 | T_214;
+ assign T_221 = T_220 | T_120;
+ assign T_222 = T_221 | T_218;
+ assign T_224 = io_inst & 32'h8002000;
+ assign T_226 = T_224 == 32'h8000000;
+ assign T_228 = io_inst & 32'hc0000004;
+ assign T_230 = T_228 == 32'h80000000;
+ assign T_232 = 1'h0 | T_214;
+ assign T_233 = T_232 | T_120;
+ assign T_234 = T_233 | T_226;
+ assign T_235 = T_234 | T_230;
+endmodule
+module MulAddRecFN_preMul(
+ input clk,
+ input reset,
+ input [1:0] io_op,
+ input [32:0] io_a,
+ input [32:0] io_b,
+ input [32:0] io_c,
+ input [1:0] io_roundingMode,
+ output [23:0] io_mulAddA,
+ output [23:0] io_mulAddB,
+ output [47:0] io_mulAddC,
+ output [2:0] io_toPostMul_highExpA,
+ output io_toPostMul_isNaN_isQuietNaNA,
+ output [2:0] io_toPostMul_highExpB,
+ output io_toPostMul_isNaN_isQuietNaNB,
+ output io_toPostMul_signProd,
+ output io_toPostMul_isZeroProd,
+ output io_toPostMul_opSignC,
+ output [2:0] io_toPostMul_highExpC,
+ output io_toPostMul_isNaN_isQuietNaNC,
+ output io_toPostMul_isCDominant,
+ output io_toPostMul_CAlignDist_0,
+ output [6:0] io_toPostMul_CAlignDist,
+ output io_toPostMul_bit0AlignedNegSigC,
+ output [25:0] io_toPostMul_highAlignedNegSigC,
+ output [10:0] io_toPostMul_sExpSum,
+ output [1:0] io_toPostMul_roundingMode
+);
+ wire signA;
+ wire [8:0] expA;
+ wire [22:0] fractA;
+ wire [2:0] T_50;
+ wire isZeroA;
+ wire T_54;
+ wire [23:0] sigA;
+ wire signB;
+ wire [8:0] expB;
+ wire [22:0] fractB;
+ wire [2:0] T_59;
+ wire isZeroB;
+ wire T_63;
+ wire [23:0] sigB;
+ wire T_65;
+ wire T_66;
+ wire opSignC;
+ wire [8:0] expC;
+ wire [22:0] fractC;
+ wire [2:0] T_70;
+ wire isZeroC;
+ wire T_74;
+ wire [23:0] sigC;
+ wire T_76;
+ wire T_77;
+ wire signProd;
+ wire isZeroProd;
+ wire T_80;
+ wire T_82;
+ wire [3:0] T_84;
+ wire [2:0] T_85;
+ wire [7:0] T_86;
+ wire [10:0] T_87;
+ wire [11:0] T_88;
+ wire [10:0] T_89;
+ wire [11:0] T_91;
+ wire [10:0] sExpAlignedProd;
+ wire doSubMags;
+ wire [11:0] T_94;
+ wire [10:0] sNatCAlignDist;
+ wire T_96;
+ wire CAlignDist_floor;
+ wire [9:0] T_98;
+ wire T_100;
+ wire CAlignDist_0;
+ wire T_103;
+ wire [9:0] T_104;
+ wire T_106;
+ wire T_107;
+ wire isCDominant;
+ wire [9:0] T_110;
+ wire T_112;
+ wire [6:0] T_113;
+ wire [6:0] T_115;
+ wire [6:0] CAlignDist;
+ wire [10:0] sExpSum;
+ wire [128:0] GEN_0;
+ wire [128:0] T_119;
+ wire [23:0] T_120;
+ wire [15:0] T_121;
+ wire [15:0] T_124;
+ wire [15:0] T_125;
+ wire [7:0] T_126;
+ wire [15:0] T_127;
+ wire [7:0] T_128;
+ wire [15:0] T_129;
+ wire [15:0] T_130;
+ wire [15:0] T_131;
+ wire [15:0] T_132;
+ wire [11:0] T_133;
+ wire [15:0] T_134;
+ wire [15:0] T_135;
+ wire [11:0] T_136;
+ wire [15:0] T_137;
+ wire [11:0] T_138;
+ wire [15:0] T_139;
+ wire [15:0] T_140;
+ wire [15:0] T_141;
+ wire [15:0] T_142;
+ wire [13:0] T_143;
+ wire [15:0] T_144;
+ wire [15:0] T_145;
+ wire [13:0] T_146;
+ wire [15:0] T_147;
+ wire [13:0] T_148;
+ wire [15:0] T_149;
+ wire [15:0] T_150;
+ wire [15:0] T_151;
+ wire [15:0] T_152;
+ wire [14:0] T_153;
+ wire [15:0] T_154;
+ wire [15:0] T_155;
+ wire [14:0] T_156;
+ wire [15:0] T_157;
+ wire [14:0] T_158;
+ wire [15:0] T_159;
+ wire [15:0] T_160;
+ wire [15:0] T_161;
+ wire [15:0] T_162;
+ wire [7:0] T_163;
+ wire [7:0] T_166;
+ wire [7:0] T_167;
+ wire [3:0] T_168;
+ wire [7:0] T_169;
+ wire [3:0] T_170;
+ wire [7:0] T_171;
+ wire [7:0] T_172;
+ wire [7:0] T_173;
+ wire [7:0] T_174;
+ wire [5:0] T_175;
+ wire [7:0] T_176;
+ wire [7:0] T_177;
+ wire [5:0] T_178;
+ wire [7:0] T_179;
+ wire [5:0] T_180;
+ wire [7:0] T_181;
+ wire [7:0] T_182;
+ wire [7:0] T_183;
+ wire [7:0] T_184;
+ wire [6:0] T_185;
+ wire [7:0] T_186;
+ wire [7:0] T_187;
+ wire [6:0] T_188;
+ wire [7:0] T_189;
+ wire [6:0] T_190;
+ wire [7:0] T_191;
+ wire [7:0] T_192;
+ wire [7:0] T_193;
+ wire [7:0] T_194;
+ wire [23:0] CExtraMask;
+ wire [23:0] T_196;
+ wire [23:0] negSigC;
+ wire [50:0] T_199;
+ wire [49:0] T_200;
+ wire [73:0] T_201;
+ wire [74:0] T_202;
+ wire [74:0] T_203;
+ wire [74:0] T_204;
+ wire [23:0] T_205;
+ wire T_207;
+ wire T_208;
+ wire [74:0] T_209;
+ wire [75:0] T_210;
+ wire [74:0] alignedNegSigC;
+ wire [47:0] T_212;
+ wire [2:0] T_213;
+ wire T_214;
+ wire [2:0] T_215;
+ wire T_216;
+ wire [2:0] T_217;
+ wire T_218;
+ wire T_219;
+ wire [25:0] T_220;
+ assign io_mulAddA = sigA;
+ assign io_mulAddB = sigB;
+ assign io_mulAddC = T_212;
+ assign io_toPostMul_highExpA = T_213;
+ assign io_toPostMul_isNaN_isQuietNaNA = T_214;
+ assign io_toPostMul_highExpB = T_215;
+ assign io_toPostMul_isNaN_isQuietNaNB = T_216;
+ assign io_toPostMul_signProd = signProd;
+ assign io_toPostMul_isZeroProd = isZeroProd;
+ assign io_toPostMul_opSignC = opSignC;
+ assign io_toPostMul_highExpC = T_217;
+ assign io_toPostMul_isNaN_isQuietNaNC = T_218;
+ assign io_toPostMul_isCDominant = isCDominant;
+ assign io_toPostMul_CAlignDist_0 = CAlignDist_0;
+ assign io_toPostMul_CAlignDist = CAlignDist;
+ assign io_toPostMul_bit0AlignedNegSigC = T_219;
+ assign io_toPostMul_highAlignedNegSigC = T_220;
+ assign io_toPostMul_sExpSum = sExpSum;
+ assign io_toPostMul_roundingMode = io_roundingMode;
+ assign signA = io_a[32];
+ assign expA = io_a[31:23];
+ assign fractA = io_a[22:0];
+ assign T_50 = expA[8:6];
+ assign isZeroA = T_50 == 1'h0;
+ assign T_54 = isZeroA == 1'h0;
+ assign sigA = {T_54,fractA};
+ assign signB = io_b[32];
+ assign expB = io_b[31:23];
+ assign fractB = io_b[22:0];
+ assign T_59 = expB[8:6];
+ assign isZeroB = T_59 == 1'h0;
+ assign T_63 = isZeroB == 1'h0;
+ assign sigB = {T_63,fractB};
+ assign T_65 = io_c[32];
+ assign T_66 = io_op[0];
+ assign opSignC = T_65 ^ T_66;
+ assign expC = io_c[31:23];
+ assign fractC = io_c[22:0];
+ assign T_70 = expC[8:6];
+ assign isZeroC = T_70 == 1'h0;
+ assign T_74 = isZeroC == 1'h0;
+ assign sigC = {T_74,fractC};
+ assign T_76 = signA ^ signB;
+ assign T_77 = io_op[1];
+ assign signProd = T_76 ^ T_77;
+ assign isZeroProd = isZeroA | isZeroB;
+ assign T_80 = expB[8];
+ assign T_82 = T_80 == 1'h0;
+ assign T_84 = 3'h0 - T_82;
+ assign T_85 = T_84[2:0];
+ assign T_86 = expB[7:0];
+ assign T_87 = {T_85,T_86};
+ assign T_88 = expA + T_87;
+ assign T_89 = T_88[10:0];
+ assign T_91 = T_89 + 5'h1b;
+ assign sExpAlignedProd = T_91[10:0];
+ assign doSubMags = signProd ^ opSignC;
+ assign T_94 = sExpAlignedProd - expC;
+ assign sNatCAlignDist = T_94[10:0];
+ assign T_96 = sNatCAlignDist[10];
+ assign CAlignDist_floor = isZeroProd | T_96;
+ assign T_98 = sNatCAlignDist[9:0];
+ assign T_100 = T_98 == 1'h0;
+ assign CAlignDist_0 = CAlignDist_floor | T_100;
+ assign T_103 = isZeroC == 1'h0;
+ assign T_104 = sNatCAlignDist[9:0];
+ assign T_106 = T_104 < 5'h19;
+ assign T_107 = CAlignDist_floor | T_106;
+ assign isCDominant = T_103 & T_107;
+ assign T_110 = sNatCAlignDist[9:0];
+ assign T_112 = T_110 < 7'h4a;
+ assign T_113 = sNatCAlignDist[6:0];
+ assign T_115 = T_112 ? T_113 : 7'h4a;
+ assign CAlignDist = CAlignDist_floor ? 1'h0 : T_115;
+ assign sExpSum = CAlignDist_floor ? expC : sExpAlignedProd;
+ assign GEN_0 = $signed(129'h100000000000000000000000000000000);
+ assign T_119 = $signed(GEN_0) >>> CAlignDist;
+ assign T_120 = T_119[77:54];
+ assign T_121 = T_120[15:0];
+ assign T_124 = 8'hff << 8;
+ assign T_125 = 16'hffff ^ T_124;
+ assign T_126 = T_121[15:8];
+ assign T_127 = T_126 & T_125;
+ assign T_128 = T_121[7:0];
+ assign T_129 = T_128 << 8;
+ assign T_130 = ~ T_125;
+ assign T_131 = T_129 & T_130;
+ assign T_132 = T_127 | T_131;
+ assign T_133 = T_125[11:0];
+ assign T_134 = T_133 << 4;
+ assign T_135 = T_125 ^ T_134;
+ assign T_136 = T_132[15:4];
+ assign T_137 = T_136 & T_135;
+ assign T_138 = T_132[11:0];
+ assign T_139 = T_138 << 4;
+ assign T_140 = ~ T_135;
+ assign T_141 = T_139 & T_140;
+ assign T_142 = T_137 | T_141;
+ assign T_143 = T_135[13:0];
+ assign T_144 = T_143 << 2;
+ assign T_145 = T_135 ^ T_144;
+ assign T_146 = T_142[15:2];
+ assign T_147 = T_146 & T_145;
+ assign T_148 = T_142[13:0];
+ assign T_149 = T_148 << 2;
+ assign T_150 = ~ T_145;
+ assign T_151 = T_149 & T_150;
+ assign T_152 = T_147 | T_151;
+ assign T_153 = T_145[14:0];
+ assign T_154 = T_153 << 1;
+ assign T_155 = T_145 ^ T_154;
+ assign T_156 = T_152[15:1];
+ assign T_157 = T_156 & T_155;
+ assign T_158 = T_152[14:0];
+ assign T_159 = T_158 << 1;
+ assign T_160 = ~ T_155;
+ assign T_161 = T_159 & T_160;
+ assign T_162 = T_157 | T_161;
+ assign T_163 = T_120[23:16];
+ assign T_166 = 4'hf << 4;
+ assign T_167 = 8'hff ^ T_166;
+ assign T_168 = T_163[7:4];
+ assign T_169 = T_168 & T_167;
+ assign T_170 = T_163[3:0];
+ assign T_171 = T_170 << 4;
+ assign T_172 = ~ T_167;
+ assign T_173 = T_171 & T_172;
+ assign T_174 = T_169 | T_173;
+ assign T_175 = T_167[5:0];
+ assign T_176 = T_175 << 2;
+ assign T_177 = T_167 ^ T_176;
+ assign T_178 = T_174[7:2];
+ assign T_179 = T_178 & T_177;
+ assign T_180 = T_174[5:0];
+ assign T_181 = T_180 << 2;
+ assign T_182 = ~ T_177;
+ assign T_183 = T_181 & T_182;
+ assign T_184 = T_179 | T_183;
+ assign T_185 = T_177[6:0];
+ assign T_186 = T_185 << 1;
+ assign T_187 = T_177 ^ T_186;
+ assign T_188 = T_184[7:1];
+ assign T_189 = T_188 & T_187;
+ assign T_190 = T_184[6:0];
+ assign T_191 = T_190 << 1;
+ assign T_192 = ~ T_187;
+ assign T_193 = T_191 & T_192;
+ assign T_194 = T_189 | T_193;
+ assign CExtraMask = {T_162,T_194};
+ assign T_196 = ~ sigC;
+ assign negSigC = doSubMags ? T_196 : sigC;
+ assign T_199 = 50'h0 - doSubMags;
+ assign T_200 = T_199[49:0];
+ assign T_201 = {negSigC,T_200};
+ assign T_202 = {doSubMags,T_201};
+ assign T_203 = $signed(T_202);
+ assign T_204 = $signed(T_203) >>> CAlignDist;
+ assign T_205 = sigC & CExtraMask;
+ assign T_207 = T_205 != 1'h0;
+ assign T_208 = T_207 ^ doSubMags;
+ assign T_209 = $unsigned(T_204);
+ assign T_210 = {T_209,T_208};
+ assign alignedNegSigC = T_210[74:0];
+ assign T_212 = alignedNegSigC[48:1];
+ assign T_213 = expA[8:6];
+ assign T_214 = fractA[22];
+ assign T_215 = expB[8:6];
+ assign T_216 = fractB[22];
+ assign T_217 = expC[8:6];
+ assign T_218 = fractC[22];
+ assign T_219 = alignedNegSigC[0];
+ assign T_220 = alignedNegSigC[74:49];
+endmodule
+module MulAddRecFN_postMul(
+ input clk,
+ input reset,
+ input [2:0] io_fromPreMul_highExpA,
+ input io_fromPreMul_isNaN_isQuietNaNA,
+ input [2:0] io_fromPreMul_highExpB,
+ input io_fromPreMul_isNaN_isQuietNaNB,
+ input io_fromPreMul_signProd,
+ input io_fromPreMul_isZeroProd,
+ input io_fromPreMul_opSignC,
+ input [2:0] io_fromPreMul_highExpC,
+ input io_fromPreMul_isNaN_isQuietNaNC,
+ input io_fromPreMul_isCDominant,
+ input io_fromPreMul_CAlignDist_0,
+ input [6:0] io_fromPreMul_CAlignDist,
+ input io_fromPreMul_bit0AlignedNegSigC,
+ input [25:0] io_fromPreMul_highAlignedNegSigC,
+ input [10:0] io_fromPreMul_sExpSum,
+ input [1:0] io_fromPreMul_roundingMode,
+ input [48:0] io_mulAddResult,
+ output [32:0] io_out,
+ output [4:0] io_exceptionFlags
+);
+ wire isZeroA;
+ wire [1:0] T_44;
+ wire isSpecialA;
+ wire T_47;
+ wire T_49;
+ wire isInfA;
+ wire T_51;
+ wire isNaNA;
+ wire T_54;
+ wire isSigNaNA;
+ wire isZeroB;
+ wire [1:0] T_58;
+ wire isSpecialB;
+ wire T_61;
+ wire T_63;
+ wire isInfB;
+ wire T_65;
+ wire isNaNB;
+ wire T_68;
+ wire isSigNaNB;
+ wire isZeroC;
+ wire [1:0] T_72;
+ wire isSpecialC;
+ wire T_75;
+ wire T_77;
+ wire isInfC;
+ wire T_79;
+ wire isNaNC;
+ wire T_82;
+ wire isSigNaNC;
+ wire roundingMode_nearest_even;
+ wire roundingMode_minMag;
+ wire roundingMode_min;
+ wire roundingMode_max;
+ wire signZeroNotEqOpSigns;
+ wire doSubMags;
+ wire T_96;
+ wire [26:0] T_98;
+ wire [25:0] T_99;
+ wire [25:0] T_100;
+ wire [47:0] T_101;
+ wire [48:0] T_102;
+ wire [74:0] sigSum;
+ wire [49:0] T_105;
+ wire [49:0] T_106;
+ wire [49:0] T_107;
+ wire [50:0] T_108;
+ wire [50:0] T_109;
+ wire [49:0] T_111;
+ wire T_112;
+ wire T_114;
+ wire T_116;
+ wire T_118;
+ wire T_120;
+ wire T_122;
+ wire T_124;
+ wire T_126;
+ wire T_128;
+ wire T_130;
+ wire T_132;
+ wire T_134;
+ wire T_136;
+ wire T_138;
+ wire T_140;
+ wire T_142;
+ wire T_144;
+ wire T_146;
+ wire T_148;
+ wire T_150;
+ wire T_152;
+ wire T_154;
+ wire T_156;
+ wire T_158;
+ wire T_160;
+ wire T_162;
+ wire T_164;
+ wire T_166;
+ wire T_168;
+ wire T_170;
+ wire T_172;
+ wire T_174;
+ wire T_176;
+ wire T_178;
+ wire T_180;
+ wire T_182;
+ wire T_184;
+ wire T_186;
+ wire T_188;
+ wire T_190;
+ wire T_192;
+ wire T_194;
+ wire T_196;
+ wire T_198;
+ wire T_200;
+ wire T_202;
+ wire T_204;
+ wire T_206;
+ wire T_208;
+ wire T_209;
+ wire [1:0] T_210;
+ wire [1:0] T_211;
+ wire [2:0] T_212;
+ wire [2:0] T_213;
+ wire [2:0] T_214;
+ wire [2:0] T_215;
+ wire [3:0] T_216;
+ wire [3:0] T_217;
+ wire [3:0] T_218;
+ wire [3:0] T_219;
+ wire [3:0] T_220;
+ wire [3:0] T_221;
+ wire [3:0] T_222;
+ wire [3:0] T_223;
+ wire [4:0] T_224;
+ wire [4:0] T_225;
+ wire [4:0] T_226;
+ wire [4:0] T_227;
+ wire [4:0] T_228;
+ wire [4:0] T_229;
+ wire [4:0] T_230;
+ wire [4:0] T_231;
+ wire [4:0] T_232;
+ wire [4:0] T_233;
+ wire [4:0] T_234;
+ wire [4:0] T_235;
+ wire [4:0] T_236;
+ wire [4:0] T_237;
+ wire [4:0] T_238;
+ wire [4:0] T_239;
+ wire [5:0] T_240;
+ wire [5:0] T_241;
+ wire [5:0] T_242;
+ wire [5:0] T_243;
+ wire [5:0] T_244;
+ wire [5:0] T_245;
+ wire [5:0] T_246;
+ wire [5:0] T_247;
+ wire [5:0] T_248;
+ wire [5:0] T_249;
+ wire [5:0] T_250;
+ wire [5:0] T_251;
+ wire [5:0] T_252;
+ wire [5:0] T_253;
+ wire [5:0] T_254;
+ wire [5:0] T_255;
+ wire [5:0] T_256;
+ wire [5:0] T_257;
+ wire [7:0] T_258;
+ wire [6:0] estNormPos_dist;
+ wire [15:0] T_260;
+ wire T_262;
+ wire [17:0] T_263;
+ wire T_265;
+ wire [1:0] firstReduceSigSum;
+ wire [74:0] notSigSum;
+ wire [15:0] T_268;
+ wire T_270;
+ wire [17:0] T_271;
+ wire T_273;
+ wire [1:0] firstReduceNotSigSum;
+ wire T_275;
+ wire [7:0] T_277;
+ wire [6:0] T_278;
+ wire [4:0] T_279;
+ wire [6:0] CDom_estNormDist;
+ wire T_281;
+ wire T_282;
+ wire T_283;
+ wire T_284;
+ wire T_285;
+ wire [40:0] T_286;
+ wire T_288;
+ wire [41:0] T_289;
+ wire [41:0] T_290;
+ wire [41:0] T_291;
+ wire [41:0] T_292;
+ wire T_293;
+ wire T_294;
+ wire T_295;
+ wire T_296;
+ wire [40:0] T_297;
+ wire T_298;
+ wire [41:0] T_299;
+ wire [41:0] T_300;
+ wire [41:0] T_301;
+ wire [41:0] T_302;
+ wire [41:0] T_303;
+ wire [41:0] T_304;
+ wire T_305;
+ wire T_306;
+ wire T_307;
+ wire T_308;
+ wire [40:0] T_309;
+ wire T_311;
+ wire [41:0] T_312;
+ wire [41:0] T_313;
+ wire [41:0] T_314;
+ wire [41:0] T_315;
+ wire [41:0] T_316;
+ wire [41:0] T_317;
+ wire T_318;
+ wire T_319;
+ wire T_320;
+ wire [40:0] T_321;
+ wire T_322;
+ wire [41:0] T_323;
+ wire [41:0] T_324;
+ wire [41:0] T_325;
+ wire [41:0] T_326;
+ wire [41:0] T_327;
+ wire [41:0] T_328;
+ wire [41:0] CDom_firstNormAbsSigSum;
+ wire [32:0] T_330;
+ wire T_331;
+ wire T_332;
+ wire T_333;
+ wire T_334;
+ wire [33:0] T_335;
+ wire [41:0] T_336;
+ wire T_337;
+ wire T_338;
+ wire [25:0] T_339;
+ wire [16:0] T_341;
+ wire [15:0] T_342;
+ wire [41:0] T_343;
+ wire [41:0] T_344;
+ wire T_345;
+ wire [9:0] T_346;
+ wire [32:0] T_348;
+ wire [31:0] T_349;
+ wire [41:0] T_350;
+ wire [41:0] T_351;
+ wire [41:0] notCDom_pos_firstNormAbsSigSum;
+ wire [31:0] T_353;
+ wire T_354;
+ wire [32:0] T_355;
+ wire [41:0] T_356;
+ wire T_357;
+ wire T_358;
+ wire [26:0] T_359;
+ wire [57:0] T_361;
+ wire [57:0] T_362;
+ wire T_363;
+ wire [10:0] T_364;
+ wire [73:0] T_366;
+ wire [73:0] T_367;
+ wire [73:0] notCDom_neg_cFirstNormAbsSigSum;
+ wire notCDom_signSigSum;
+ wire T_370;
+ wire T_371;
+ wire doNegSignSum;
+ wire [6:0] T_373;
+ wire [6:0] estNormDist;
+ wire [73:0] T_375;
+ wire [41:0] T_376;
+ wire [73:0] cFirstNormAbsSigSum;
+ wire T_378;
+ wire T_379;
+ wire T_380;
+ wire doIncrSig;
+ wire [3:0] estNormDist_5;
+ wire [3:0] normTo2ShiftDist;
+ wire [16:0] GEN_0;
+ wire [16:0] T_385;
+ wire [14:0] T_386;
+ wire [7:0] T_387;
+ wire [7:0] T_390;
+ wire [7:0] T_391;
+ wire [3:0] T_392;
+ wire [7:0] T_393;
+ wire [3:0] T_394;
+ wire [7:0] T_395;
+ wire [7:0] T_396;
+ wire [7:0] T_397;
+ wire [7:0] T_398;
+ wire [5:0] T_399;
+ wire [7:0] T_400;
+ wire [7:0] T_401;
+ wire [5:0] T_402;
+ wire [7:0] T_403;
+ wire [5:0] T_404;
+ wire [7:0] T_405;
+ wire [7:0] T_406;
+ wire [7:0] T_407;
+ wire [7:0] T_408;
+ wire [6:0] T_409;
+ wire [7:0] T_410;
+ wire [7:0] T_411;
+ wire [6:0] T_412;
+ wire [7:0] T_413;
+ wire [6:0] T_414;
+ wire [7:0] T_415;
+ wire [7:0] T_416;
+ wire [7:0] T_417;
+ wire [7:0] T_418;
+ wire [6:0] T_419;
+ wire [3:0] T_420;
+ wire [1:0] T_421;
+ wire T_422;
+ wire T_423;
+ wire [1:0] T_424;
+ wire [1:0] T_425;
+ wire T_426;
+ wire T_427;
+ wire [1:0] T_428;
+ wire [3:0] T_429;
+ wire [2:0] T_430;
+ wire [1:0] T_431;
+ wire T_432;
+ wire T_433;
+ wire [1:0] T_434;
+ wire T_435;
+ wire [2:0] T_436;
+ wire [6:0] T_437;
+ wire [14:0] T_438;
+ wire [15:0] absSigSumExtraMask;
+ wire [41:0] T_441;
+ wire [41:0] T_442;
+ wire [15:0] T_443;
+ wire [15:0] T_444;
+ wire [15:0] T_445;
+ wire T_447;
+ wire [15:0] T_448;
+ wire [15:0] T_449;
+ wire T_451;
+ wire T_452;
+ wire [42:0] T_453;
+ wire [27:0] sigX3;
+ wire [1:0] T_455;
+ wire sigX3Shift1;
+ wire [11:0] T_458;
+ wire [10:0] sExpX3;
+ wire [2:0] T_460;
+ wire isZeroY;
+ wire T_463;
+ wire signY;
+ wire [9:0] sExpX3_13;
+ wire T_466;
+ wire [27:0] T_468;
+ wire [26:0] T_469;
+ wire [9:0] T_470;
+ wire [1024:0] GEN_1;
+ wire [1024:0] T_472;
+ wire [24:0] T_473;
+ wire [15:0] T_474;
+ wire [15:0] T_477;
+ wire [15:0] T_478;
+ wire [7:0] T_479;
+ wire [15:0] T_480;
+ wire [7:0] T_481;
+ wire [15:0] T_482;
+ wire [15:0] T_483;
+ wire [15:0] T_484;
+ wire [15:0] T_485;
+ wire [11:0] T_486;
+ wire [15:0] T_487;
+ wire [15:0] T_488;
+ wire [11:0] T_489;
+ wire [15:0] T_490;
+ wire [11:0] T_491;
+ wire [15:0] T_492;
+ wire [15:0] T_493;
+ wire [15:0] T_494;
+ wire [15:0] T_495;
+ wire [13:0] T_496;
+ wire [15:0] T_497;
+ wire [15:0] T_498;
+ wire [13:0] T_499;
+ wire [15:0] T_500;
+ wire [13:0] T_501;
+ wire [15:0] T_502;
+ wire [15:0] T_503;
+ wire [15:0] T_504;
+ wire [15:0] T_505;
+ wire [14:0] T_506;
+ wire [15:0] T_507;
+ wire [15:0] T_508;
+ wire [14:0] T_509;
+ wire [15:0] T_510;
+ wire [14:0] T_511;
+ wire [15:0] T_512;
+ wire [15:0] T_513;
+ wire [15:0] T_514;
+ wire [15:0] T_515;
+ wire [8:0] T_516;
+ wire [7:0] T_517;
+ wire [7:0] T_520;
+ wire [7:0] T_521;
+ wire [3:0] T_522;
+ wire [7:0] T_523;
+ wire [3:0] T_524;
+ wire [7:0] T_525;
+ wire [7:0] T_526;
+ wire [7:0] T_527;
+ wire [7:0] T_528;
+ wire [5:0] T_529;
+ wire [7:0] T_530;
+ wire [7:0] T_531;
+ wire [5:0] T_532;
+ wire [7:0] T_533;
+ wire [5:0] T_534;
+ wire [7:0] T_535;
+ wire [7:0] T_536;
+ wire [7:0] T_537;
+ wire [7:0] T_538;
+ wire [6:0] T_539;
+ wire [7:0] T_540;
+ wire [7:0] T_541;
+ wire [6:0] T_542;
+ wire [7:0] T_543;
+ wire [6:0] T_544;
+ wire [7:0] T_545;
+ wire [7:0] T_546;
+ wire [7:0] T_547;
+ wire [7:0] T_548;
+ wire T_549;
+ wire [8:0] T_550;
+ wire [24:0] T_551;
+ wire T_552;
+ wire [24:0] T_553;
+ wire [26:0] T_555;
+ wire [26:0] roundMask;
+ wire [25:0] T_557;
+ wire [25:0] T_558;
+ wire [26:0] roundPosMask;
+ wire [27:0] T_560;
+ wire roundPosBit;
+ wire [25:0] T_563;
+ wire [27:0] T_564;
+ wire anyRoundExtra;
+ wire [27:0] T_567;
+ wire [25:0] T_568;
+ wire [27:0] T_569;
+ wire allRoundExtra;
+ wire anyRound;
+ wire allRound;
+ wire roundDirectUp;
+ wire T_575;
+ wire T_576;
+ wire T_577;
+ wire T_578;
+ wire T_579;
+ wire T_580;
+ wire T_581;
+ wire T_582;
+ wire T_583;
+ wire T_584;
+ wire T_585;
+ wire T_586;
+ wire T_587;
+ wire T_588;
+ wire T_590;
+ wire roundUp;
+ wire T_592;
+ wire T_593;
+ wire T_594;
+ wire T_595;
+ wire T_596;
+ wire T_597;
+ wire roundEven;
+ wire T_599;
+ wire roundInexact;
+ wire [27:0] T_601;
+ wire [25:0] T_602;
+ wire [26:0] T_604;
+ wire [25:0] T_605;
+ wire [25:0] roundUp_sigY3;
+ wire T_607;
+ wire T_608;
+ wire T_609;
+ wire T_610;
+ wire [26:0] T_611;
+ wire [27:0] T_612;
+ wire [25:0] T_613;
+ wire [25:0] T_615;
+ wire T_616;
+ wire [25:0] T_618;
+ wire [25:0] T_619;
+ wire [25:0] T_620;
+ wire [25:0] T_621;
+ wire [25:0] T_622;
+ wire [25:0] T_624;
+ wire [25:0] sigY3;
+ wire T_626;
+ wire [11:0] T_628;
+ wire [10:0] T_629;
+ wire [10:0] T_631;
+ wire T_632;
+ wire [10:0] T_634;
+ wire [10:0] T_635;
+ wire [1:0] T_636;
+ wire T_638;
+ wire [11:0] T_640;
+ wire [10:0] T_641;
+ wire [10:0] T_643;
+ wire [10:0] sExpY;
+ wire [8:0] expY;
+ wire [22:0] T_646;
+ wire [22:0] T_647;
+ wire [22:0] fractY;
+ wire [2:0] T_649;
+ wire overflowY;
+ wire T_652;
+ wire T_653;
+ wire [8:0] T_654;
+ wire T_656;
+ wire T_657;
+ wire totalUnderflowY;
+ wire T_659;
+ wire [7:0] T_662;
+ wire T_663;
+ wire T_664;
+ wire underflowY;
+ wire T_666;
+ wire T_667;
+ wire T_668;
+ wire roundMagUp;
+ wire overflowY_roundMagUp;
+ wire mulSpecial;
+ wire addSpecial;
+ wire notSpecial_addZeros;
+ wire T_674;
+ wire T_675;
+ wire commonCase;
+ wire T_677;
+ wire T_678;
+ wire T_679;
+ wire T_680;
+ wire T_681;
+ wire T_682;
+ wire T_683;
+ wire T_684;
+ wire T_685;
+ wire T_686;
+ wire notSigNaN_invalid;
+ wire T_688;
+ wire T_689;
+ wire invalid;
+ wire overflow;
+ wire underflow;
+ wire T_693;
+ wire inexact;
+ wire T_695;
+ wire notSpecial_isZeroOut;
+ wire T_697;
+ wire pegMinFiniteMagOut;
+ wire T_699;
+ wire pegMaxFiniteMagOut;
+ wire T_701;
+ wire T_702;
+ wire T_703;
+ wire notNaN_isInfOut;
+ wire T_705;
+ wire T_706;
+ wire isNaNOut;
+ wire T_709;
+ wire T_710;
+ wire T_712;
+ wire T_713;
+ wire T_714;
+ wire T_715;
+ wire T_717;
+ wire T_718;
+ wire T_719;
+ wire T_720;
+ wire T_722;
+ wire T_723;
+ wire T_724;
+ wire T_725;
+ wire uncommonCaseSignOut;
+ wire T_728;
+ wire T_729;
+ wire T_730;
+ wire signOut;
+ wire [8:0] T_734;
+ wire [8:0] T_735;
+ wire [8:0] T_736;
+ wire [8:0] T_738;
+ wire [8:0] T_740;
+ wire [8:0] T_741;
+ wire [8:0] T_742;
+ wire [8:0] T_745;
+ wire [8:0] T_746;
+ wire [8:0] T_747;
+ wire [8:0] T_750;
+ wire [8:0] T_751;
+ wire [8:0] T_752;
+ wire [8:0] T_755;
+ wire [8:0] T_756;
+ wire [8:0] T_759;
+ wire [8:0] T_760;
+ wire [8:0] T_763;
+ wire [8:0] T_764;
+ wire [8:0] T_767;
+ wire [8:0] expOut;
+ wire T_769;
+ wire T_770;
+ wire [22:0] T_772;
+ wire [22:0] T_773;
+ wire [22:0] T_774;
+ wire [23:0] T_776;
+ wire [22:0] T_777;
+ wire [22:0] fractOut;
+ wire [31:0] T_779;
+ wire [32:0] T_780;
+ wire [1:0] T_782;
+ wire [1:0] T_783;
+ wire [2:0] T_784;
+ wire [4:0] T_785;
+ assign io_out = T_780;
+ assign io_exceptionFlags = T_785;
+ assign isZeroA = io_fromPreMul_highExpA == 1'h0;
+ assign T_44 = io_fromPreMul_highExpA[2:1];
+ assign isSpecialA = T_44 == 2'h3;
+ assign T_47 = io_fromPreMul_highExpA[0];
+ assign T_49 = T_47 == 1'h0;
+ assign isInfA = isSpecialA & T_49;
+ assign T_51 = io_fromPreMul_highExpA[0];
+ assign isNaNA = isSpecialA & T_51;
+ assign T_54 = io_fromPreMul_isNaN_isQuietNaNA == 1'h0;
+ assign isSigNaNA = isNaNA & T_54;
+ assign isZeroB = io_fromPreMul_highExpB == 1'h0;
+ assign T_58 = io_fromPreMul_highExpB[2:1];
+ assign isSpecialB = T_58 == 2'h3;
+ assign T_61 = io_fromPreMul_highExpB[0];
+ assign T_63 = T_61 == 1'h0;
+ assign isInfB = isSpecialB & T_63;
+ assign T_65 = io_fromPreMul_highExpB[0];
+ assign isNaNB = isSpecialB & T_65;
+ assign T_68 = io_fromPreMul_isNaN_isQuietNaNB == 1'h0;
+ assign isSigNaNB = isNaNB & T_68;
+ assign isZeroC = io_fromPreMul_highExpC == 1'h0;
+ assign T_72 = io_fromPreMul_highExpC[2:1];
+ assign isSpecialC = T_72 == 2'h3;
+ assign T_75 = io_fromPreMul_highExpC[0];
+ assign T_77 = T_75 == 1'h0;
+ assign isInfC = isSpecialC & T_77;
+ assign T_79 = io_fromPreMul_highExpC[0];
+ assign isNaNC = isSpecialC & T_79;
+ assign T_82 = io_fromPreMul_isNaN_isQuietNaNC == 1'h0;
+ assign isSigNaNC = isNaNC & T_82;
+ assign roundingMode_nearest_even = io_fromPreMul_roundingMode == 2'h0;
+ assign roundingMode_minMag = io_fromPreMul_roundingMode == 2'h1;
+ assign roundingMode_min = io_fromPreMul_roundingMode == 2'h2;
+ assign roundingMode_max = io_fromPreMul_roundingMode == 2'h3;
+ assign signZeroNotEqOpSigns = roundingMode_min ? 1'h1 : 1'h0;
+ assign doSubMags = io_fromPreMul_signProd ^ io_fromPreMul_opSignC;
+ assign T_96 = io_mulAddResult[48];
+ assign T_98 = io_fromPreMul_highAlignedNegSigC + 1'h1;
+ assign T_99 = T_98[25:0];
+ assign T_100 = T_96 ? T_99 : io_fromPreMul_highAlignedNegSigC;
+ assign T_101 = io_mulAddResult[47:0];
+ assign T_102 = {T_101,io_fromPreMul_bit0AlignedNegSigC};
+ assign sigSum = {T_100,T_102};
+ assign T_105 = sigSum[50:1];
+ assign T_106 = 50'h0 ^ T_105;
+ assign T_107 = 50'h0 | T_105;
+ assign T_108 = T_107 << 1;
+ assign T_109 = T_106 ^ T_108;
+ assign T_111 = T_109[49:0];
+ assign T_112 = T_111[49];
+ assign T_114 = T_111[48];
+ assign T_116 = T_111[47];
+ assign T_118 = T_111[46];
+ assign T_120 = T_111[45];
+ assign T_122 = T_111[44];
+ assign T_124 = T_111[43];
+ assign T_126 = T_111[42];
+ assign T_128 = T_111[41];
+ assign T_130 = T_111[40];
+ assign T_132 = T_111[39];
+ assign T_134 = T_111[38];
+ assign T_136 = T_111[37];
+ assign T_138 = T_111[36];
+ assign T_140 = T_111[35];
+ assign T_142 = T_111[34];
+ assign T_144 = T_111[33];
+ assign T_146 = T_111[32];
+ assign T_148 = T_111[31];
+ assign T_150 = T_111[30];
+ assign T_152 = T_111[29];
+ assign T_154 = T_111[28];
+ assign T_156 = T_111[27];
+ assign T_158 = T_111[26];
+ assign T_160 = T_111[25];
+ assign T_162 = T_111[24];
+ assign T_164 = T_111[23];
+ assign T_166 = T_111[22];
+ assign T_168 = T_111[21];
+ assign T_170 = T_111[20];
+ assign T_172 = T_111[19];
+ assign T_174 = T_111[18];
+ assign T_176 = T_111[17];
+ assign T_178 = T_111[16];
+ assign T_180 = T_111[15];
+ assign T_182 = T_111[14];
+ assign T_184 = T_111[13];
+ assign T_186 = T_111[12];
+ assign T_188 = T_111[11];
+ assign T_190 = T_111[10];
+ assign T_192 = T_111[9];
+ assign T_194 = T_111[8];
+ assign T_196 = T_111[7];
+ assign T_198 = T_111[6];
+ assign T_200 = T_111[5];
+ assign T_202 = T_111[4];
+ assign T_204 = T_111[3];
+ assign T_206 = T_111[2];
+ assign T_208 = T_111[1];
+ assign T_209 = T_208 << 0;
+ assign T_210 = T_206 ? 2'h2 : T_209;
+ assign T_211 = T_204 ? 2'h3 : T_210;
+ assign T_212 = T_202 ? 3'h4 : T_211;
+ assign T_213 = T_200 ? 3'h5 : T_212;
+ assign T_214 = T_198 ? 3'h6 : T_213;
+ assign T_215 = T_196 ? 3'h7 : T_214;
+ assign T_216 = T_194 ? 4'h8 : T_215;
+ assign T_217 = T_192 ? 4'h9 : T_216;
+ assign T_218 = T_190 ? 4'ha : T_217;
+ assign T_219 = T_188 ? 4'hb : T_218;
+ assign T_220 = T_186 ? 4'hc : T_219;
+ assign T_221 = T_184 ? 4'hd : T_220;
+ assign T_222 = T_182 ? 4'he : T_221;
+ assign T_223 = T_180 ? 4'hf : T_222;
+ assign T_224 = T_178 ? 5'h10 : T_223;
+ assign T_225 = T_176 ? 5'h11 : T_224;
+ assign T_226 = T_174 ? 5'h12 : T_225;
+ assign T_227 = T_172 ? 5'h13 : T_226;
+ assign T_228 = T_170 ? 5'h14 : T_227;
+ assign T_229 = T_168 ? 5'h15 : T_228;
+ assign T_230 = T_166 ? 5'h16 : T_229;
+ assign T_231 = T_164 ? 5'h17 : T_230;
+ assign T_232 = T_162 ? 5'h18 : T_231;
+ assign T_233 = T_160 ? 5'h19 : T_232;
+ assign T_234 = T_158 ? 5'h1a : T_233;
+ assign T_235 = T_156 ? 5'h1b : T_234;
+ assign T_236 = T_154 ? 5'h1c : T_235;
+ assign T_237 = T_152 ? 5'h1d : T_236;
+ assign T_238 = T_150 ? 5'h1e : T_237;
+ assign T_239 = T_148 ? 5'h1f : T_238;
+ assign T_240 = T_146 ? 6'h20 : T_239;
+ assign T_241 = T_144 ? 6'h21 : T_240;
+ assign T_242 = T_142 ? 6'h22 : T_241;
+ assign T_243 = T_140 ? 6'h23 : T_242;
+ assign T_244 = T_138 ? 6'h24 : T_243;
+ assign T_245 = T_136 ? 6'h25 : T_244;
+ assign T_246 = T_134 ? 6'h26 : T_245;
+ assign T_247 = T_132 ? 6'h27 : T_246;
+ assign T_248 = T_130 ? 6'h28 : T_247;
+ assign T_249 = T_128 ? 6'h29 : T_248;
+ assign T_250 = T_126 ? 6'h2a : T_249;
+ assign T_251 = T_124 ? 6'h2b : T_250;
+ assign T_252 = T_122 ? 6'h2c : T_251;
+ assign T_253 = T_120 ? 6'h2d : T_252;
+ assign T_254 = T_118 ? 6'h2e : T_253;
+ assign T_255 = T_116 ? 6'h2f : T_254;
+ assign T_256 = T_114 ? 6'h30 : T_255;
+ assign T_257 = T_112 ? 6'h31 : T_256;
+ assign T_258 = 7'h49 - T_257;
+ assign estNormPos_dist = T_258[6:0];
+ assign T_260 = sigSum[33:18];
+ assign T_262 = T_260 != 1'h0;
+ assign T_263 = sigSum[17:0];
+ assign T_265 = T_263 != 1'h0;
+ assign firstReduceSigSum = {T_262,T_265};
+ assign notSigSum = ~ sigSum;
+ assign T_268 = notSigSum[33:18];
+ assign T_270 = T_268 != 1'h0;
+ assign T_271 = notSigSum[17:0];
+ assign T_273 = T_271 != 1'h0;
+ assign firstReduceNotSigSum = {T_270,T_273};
+ assign T_275 = io_fromPreMul_CAlignDist_0 | doSubMags;
+ assign T_277 = io_fromPreMul_CAlignDist - 1'h1;
+ assign T_278 = T_277[6:0];
+ assign T_279 = T_278[4:0];
+ assign CDom_estNormDist = T_275 ? io_fromPreMul_CAlignDist : T_279;
+ assign T_281 = ~ doSubMags;
+ assign T_282 = CDom_estNormDist[4];
+ assign T_283 = ~ T_282;
+ assign T_284 = T_281 & T_283;
+ assign T_285 = $signed(T_284);
+ assign T_286 = sigSum[74:34];
+ assign T_288 = firstReduceSigSum != 1'h0;
+ assign T_289 = {T_286,T_288};
+ assign T_290 = $signed(T_289);
+ assign T_291 = $signed(T_285) & $signed(T_290);
+ assign T_292 = $signed(T_291);
+ assign T_293 = ~ doSubMags;
+ assign T_294 = CDom_estNormDist[4];
+ assign T_295 = T_293 & T_294;
+ assign T_296 = $signed(T_295);
+ assign T_297 = sigSum[58:18];
+ assign T_298 = firstReduceSigSum[0];
+ assign T_299 = {T_297,T_298};
+ assign T_300 = $signed(T_299);
+ assign T_301 = $signed(T_296) & $signed(T_300);
+ assign T_302 = $signed(T_301);
+ assign T_303 = $signed(T_292) | $signed(T_302);
+ assign T_304 = $signed(T_303);
+ assign T_305 = CDom_estNormDist[4];
+ assign T_306 = ~ T_305;
+ assign T_307 = doSubMags & T_306;
+ assign T_308 = $signed(T_307);
+ assign T_309 = notSigSum[74:34];
+ assign T_311 = firstReduceNotSigSum != 1'h0;
+ assign T_312 = {T_309,T_311};
+ assign T_313 = $signed(T_312);
+ assign T_314 = $signed(T_308) & $signed(T_313);
+ assign T_315 = $signed(T_314);
+ assign T_316 = $signed(T_304) | $signed(T_315);
+ assign T_317 = $signed(T_316);
+ assign T_318 = CDom_estNormDist[4];
+ assign T_319 = doSubMags & T_318;
+ assign T_320 = $signed(T_319);
+ assign T_321 = notSigSum[58:18];
+ assign T_322 = firstReduceNotSigSum[0];
+ assign T_323 = {T_321,T_322};
+ assign T_324 = $signed(T_323);
+ assign T_325 = $signed(T_320) & $signed(T_324);
+ assign T_326 = $signed(T_325);
+ assign T_327 = $signed(T_317) | $signed(T_326);
+ assign T_328 = $signed(T_327);
+ assign CDom_firstNormAbsSigSum = $unsigned(T_328);
+ assign T_330 = sigSum[50:18];
+ assign T_331 = firstReduceNotSigSum[0];
+ assign T_332 = ~ T_331;
+ assign T_333 = firstReduceSigSum[0];
+ assign T_334 = doSubMags ? T_332 : T_333;
+ assign T_335 = {T_330,T_334};
+ assign T_336 = sigSum[42:1];
+ assign T_337 = estNormPos_dist[5];
+ assign T_338 = estNormPos_dist[4];
+ assign T_339 = sigSum[26:1];
+ assign T_341 = 16'h0 - doSubMags;
+ assign T_342 = T_341[15:0];
+ assign T_343 = {T_339,T_342};
+ assign T_344 = T_338 ? T_343 : T_336;
+ assign T_345 = estNormPos_dist[4];
+ assign T_346 = sigSum[10:1];
+ assign T_348 = 32'h0 - doSubMags;
+ assign T_349 = T_348[31:0];
+ assign T_350 = {T_346,T_349};
+ assign T_351 = T_345 ? T_335 : T_350;
+ assign notCDom_pos_firstNormAbsSigSum = T_337 ? T_344 : T_351;
+ assign T_353 = notSigSum[49:18];
+ assign T_354 = firstReduceNotSigSum[0];
+ assign T_355 = {T_353,T_354};
+ assign T_356 = notSigSum[42:1];
+ assign T_357 = estNormPos_dist[5];
+ assign T_358 = estNormPos_dist[4];
+ assign T_359 = notSigSum[27:1];
+ assign T_361 = T_359 << 5'h10;
+ assign T_362 = T_358 ? T_361 : T_356;
+ assign T_363 = estNormPos_dist[4];
+ assign T_364 = notSigSum[11:1];
+ assign T_366 = T_364 << 6'h20;
+ assign T_367 = T_363 ? T_355 : T_366;
+ assign notCDom_neg_cFirstNormAbsSigSum = T_357 ? T_362 : T_367;
+ assign notCDom_signSigSum = sigSum[51];
+ assign T_370 = ~ isZeroC;
+ assign T_371 = doSubMags & T_370;
+ assign doNegSignSum = io_fromPreMul_isCDominant ? T_371 : notCDom_signSigSum;
+ assign T_373 = notCDom_signSigSum ? estNormPos_dist : estNormPos_dist;
+ assign estNormDist = io_fromPreMul_isCDominant ? CDom_estNormDist : T_373;
+ assign T_375 = io_fromPreMul_isCDominant ? CDom_firstNormAbsSigSum : notCDom_neg_cFirstNormAbsSigSum;
+ assign T_376 = io_fromPreMul_isCDominant ? CDom_firstNormAbsSigSum : notCDom_pos_firstNormAbsSigSum;
+ assign cFirstNormAbsSigSum = notCDom_signSigSum ? T_375 : T_376;
+ assign T_378 = ~ io_fromPreMul_isCDominant;
+ assign T_379 = ~ notCDom_signSigSum;
+ assign T_380 = T_378 & T_379;
+ assign doIncrSig = T_380 & doSubMags;
+ assign estNormDist_5 = estNormDist[3:0];
+ assign normTo2ShiftDist = ~ estNormDist_5;
+ assign GEN_0 = $signed(17'h10000);
+ assign T_385 = $signed(GEN_0) >>> normTo2ShiftDist;
+ assign T_386 = T_385[15:1];
+ assign T_387 = T_386[7:0];
+ assign T_390 = 4'hf << 4;
+ assign T_391 = 8'hff ^ T_390;
+ assign T_392 = T_387[7:4];
+ assign T_393 = T_392 & T_391;
+ assign T_394 = T_387[3:0];
+ assign T_395 = T_394 << 4;
+ assign T_396 = ~ T_391;
+ assign T_397 = T_395 & T_396;
+ assign T_398 = T_393 | T_397;
+ assign T_399 = T_391[5:0];
+ assign T_400 = T_399 << 2;
+ assign T_401 = T_391 ^ T_400;
+ assign T_402 = T_398[7:2];
+ assign T_403 = T_402 & T_401;
+ assign T_404 = T_398[5:0];
+ assign T_405 = T_404 << 2;
+ assign T_406 = ~ T_401;
+ assign T_407 = T_405 & T_406;
+ assign T_408 = T_403 | T_407;
+ assign T_409 = T_401[6:0];
+ assign T_410 = T_409 << 1;
+ assign T_411 = T_401 ^ T_410;
+ assign T_412 = T_408[7:1];
+ assign T_413 = T_412 & T_411;
+ assign T_414 = T_408[6:0];
+ assign T_415 = T_414 << 1;
+ assign T_416 = ~ T_411;
+ assign T_417 = T_415 & T_416;
+ assign T_418 = T_413 | T_417;
+ assign T_419 = T_386[14:8];
+ assign T_420 = T_419[3:0];
+ assign T_421 = T_420[1:0];
+ assign T_422 = T_421[0];
+ assign T_423 = T_421[1];
+ assign T_424 = {T_422,T_423};
+ assign T_425 = T_420[3:2];
+ assign T_426 = T_425[0];
+ assign T_427 = T_425[1];
+ assign T_428 = {T_426,T_427};
+ assign T_429 = {T_424,T_428};
+ assign T_430 = T_419[6:4];
+ assign T_431 = T_430[1:0];
+ assign T_432 = T_431[0];
+ assign T_433 = T_431[1];
+ assign T_434 = {T_432,T_433};
+ assign T_435 = T_430[2];
+ assign T_436 = {T_434,T_435};
+ assign T_437 = {T_429,T_436};
+ assign T_438 = {T_418,T_437};
+ assign absSigSumExtraMask = {T_438,1'h1};
+ assign T_441 = cFirstNormAbsSigSum[42:1];
+ assign T_442 = T_441 >> normTo2ShiftDist;
+ assign T_443 = cFirstNormAbsSigSum[15:0];
+ assign T_444 = ~ T_443;
+ assign T_445 = T_444 & absSigSumExtraMask;
+ assign T_447 = T_445 == 1'h0;
+ assign T_448 = cFirstNormAbsSigSum[15:0];
+ assign T_449 = T_448 & absSigSumExtraMask;
+ assign T_451 = T_449 != 1'h0;
+ assign T_452 = doIncrSig ? T_447 : T_451;
+ assign T_453 = {T_442,T_452};
+ assign sigX3 = T_453[27:0];
+ assign T_455 = sigX3[27:26];
+ assign sigX3Shift1 = T_455 == 1'h0;
+ assign T_458 = io_fromPreMul_sExpSum - estNormDist;
+ assign sExpX3 = T_458[10:0];
+ assign T_460 = sigX3[27:25];
+ assign isZeroY = T_460 == 1'h0;
+ assign T_463 = io_fromPreMul_signProd ^ doNegSignSum;
+ assign signY = isZeroY ? signZeroNotEqOpSigns : T_463;
+ assign sExpX3_13 = sExpX3[9:0];
+ assign T_466 = sExpX3[10];
+ assign T_468 = 27'h0 - T_466;
+ assign T_469 = T_468[26:0];
+ assign T_470 = ~ sExpX3_13;
+ assign GEN_1 = $signed(1025'h10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000);
+ assign T_472 = $signed(GEN_1) >>> T_470;
+ assign T_473 = T_472[131:107];
+ assign T_474 = T_473[15:0];
+ assign T_477 = 8'hff << 8;
+ assign T_478 = 16'hffff ^ T_477;
+ assign T_479 = T_474[15:8];
+ assign T_480 = T_479 & T_478;
+ assign T_481 = T_474[7:0];
+ assign T_482 = T_481 << 8;
+ assign T_483 = ~ T_478;
+ assign T_484 = T_482 & T_483;
+ assign T_485 = T_480 | T_484;
+ assign T_486 = T_478[11:0];
+ assign T_487 = T_486 << 4;
+ assign T_488 = T_478 ^ T_487;
+ assign T_489 = T_485[15:4];
+ assign T_490 = T_489 & T_488;
+ assign T_491 = T_485[11:0];
+ assign T_492 = T_491 << 4;
+ assign T_493 = ~ T_488;
+ assign T_494 = T_492 & T_493;
+ assign T_495 = T_490 | T_494;
+ assign T_496 = T_488[13:0];
+ assign T_497 = T_496 << 2;
+ assign T_498 = T_488 ^ T_497;
+ assign T_499 = T_495[15:2];
+ assign T_500 = T_499 & T_498;
+ assign T_501 = T_495[13:0];
+ assign T_502 = T_501 << 2;
+ assign T_503 = ~ T_498;
+ assign T_504 = T_502 & T_503;
+ assign T_505 = T_500 | T_504;
+ assign T_506 = T_498[14:0];
+ assign T_507 = T_506 << 1;
+ assign T_508 = T_498 ^ T_507;
+ assign T_509 = T_505[15:1];
+ assign T_510 = T_509 & T_508;
+ assign T_511 = T_505[14:0];
+ assign T_512 = T_511 << 1;
+ assign T_513 = ~ T_508;
+ assign T_514 = T_512 & T_513;
+ assign T_515 = T_510 | T_514;
+ assign T_516 = T_473[24:16];
+ assign T_517 = T_516[7:0];
+ assign T_520 = 4'hf << 4;
+ assign T_521 = 8'hff ^ T_520;
+ assign T_522 = T_517[7:4];
+ assign T_523 = T_522 & T_521;
+ assign T_524 = T_517[3:0];
+ assign T_525 = T_524 << 4;
+ assign T_526 = ~ T_521;
+ assign T_527 = T_525 & T_526;
+ assign T_528 = T_523 | T_527;
+ assign T_529 = T_521[5:0];
+ assign T_530 = T_529 << 2;
+ assign T_531 = T_521 ^ T_530;
+ assign T_532 = T_528[7:2];
+ assign T_533 = T_532 & T_531;
+ assign T_534 = T_528[5:0];
+ assign T_535 = T_534 << 2;
+ assign T_536 = ~ T_531;
+ assign T_537 = T_535 & T_536;
+ assign T_538 = T_533 | T_537;
+ assign T_539 = T_531[6:0];
+ assign T_540 = T_539 << 1;
+ assign T_541 = T_531 ^ T_540;
+ assign T_542 = T_538[7:1];
+ assign T_543 = T_542 & T_541;
+ assign T_544 = T_538[6:0];
+ assign T_545 = T_544 << 1;
+ assign T_546 = ~ T_541;
+ assign T_547 = T_545 & T_546;
+ assign T_548 = T_543 | T_547;
+ assign T_549 = T_516[8];
+ assign T_550 = {T_548,T_549};
+ assign T_551 = {T_515,T_550};
+ assign T_552 = sigX3[26];
+ assign T_553 = T_551 | T_552;
+ assign T_555 = {T_553,2'h3};
+ assign roundMask = T_469 | T_555;
+ assign T_557 = roundMask[26:1];
+ assign T_558 = ~ T_557;
+ assign roundPosMask = T_558 & roundMask;
+ assign T_560 = sigX3 & roundPosMask;
+ assign roundPosBit = T_560 != 1'h0;
+ assign T_563 = roundMask[26:1];
+ assign T_564 = sigX3 & T_563;
+ assign anyRoundExtra = T_564 != 1'h0;
+ assign T_567 = ~ sigX3;
+ assign T_568 = roundMask[26:1];
+ assign T_569 = T_567 & T_568;
+ assign allRoundExtra = T_569 == 1'h0;
+ assign anyRound = roundPosBit | anyRoundExtra;
+ assign allRound = roundPosBit & allRoundExtra;
+ assign roundDirectUp = signY ? roundingMode_min : roundingMode_max;
+ assign T_575 = ~ doIncrSig;
+ assign T_576 = T_575 & roundingMode_nearest_even;
+ assign T_577 = T_576 & roundPosBit;
+ assign T_578 = T_577 & anyRoundExtra;
+ assign T_579 = ~ doIncrSig;
+ assign T_580 = T_579 & roundDirectUp;
+ assign T_581 = T_580 & anyRound;
+ assign T_582 = T_578 | T_581;
+ assign T_583 = doIncrSig & allRound;
+ assign T_584 = T_582 | T_583;
+ assign T_585 = doIncrSig & roundingMode_nearest_even;
+ assign T_586 = T_585 & roundPosBit;
+ assign T_587 = T_584 | T_586;
+ assign T_588 = doIncrSig & roundDirectUp;
+ assign T_590 = T_588 & 1'h1;
+ assign roundUp = T_587 | T_590;
+ assign T_592 = ~ roundPosBit;
+ assign T_593 = roundingMode_nearest_even & T_592;
+ assign T_594 = T_593 & allRoundExtra;
+ assign T_595 = roundingMode_nearest_even & roundPosBit;
+ assign T_596 = ~ anyRoundExtra;
+ assign T_597 = T_595 & T_596;
+ assign roundEven = doIncrSig ? T_594 : T_597;
+ assign T_599 = ~ allRound;
+ assign roundInexact = doIncrSig ? T_599 : anyRound;
+ assign T_601 = sigX3 | roundMask;
+ assign T_602 = T_601[27:2];
+ assign T_604 = T_602 + 1'h1;
+ assign T_605 = T_604[25:0];
+ assign roundUp_sigY3 = T_605;
+ assign T_607 = ~ roundUp;
+ assign T_608 = ~ roundEven;
+ assign T_609 = T_607 & T_608;
+ assign T_610 = T_609;
+ assign T_611 = ~ roundMask;
+ assign T_612 = sigX3 & T_611;
+ assign T_613 = T_612[27:2];
+ assign T_615 = T_610 ? T_613 : 1'h0;
+ assign T_616 = roundUp;
+ assign T_618 = T_616 ? roundUp_sigY3 : 1'h0;
+ assign T_619 = T_615 | T_618;
+ assign T_620 = roundMask[26:1];
+ assign T_621 = ~ T_620;
+ assign T_622 = roundUp_sigY3 & T_621;
+ assign T_624 = roundEven ? T_622 : 1'h0;
+ assign sigY3 = T_619 | T_624;
+ assign T_626 = sigY3[25];
+ assign T_628 = sExpX3 + 1'h1;
+ assign T_629 = T_628[10:0];
+ assign T_631 = T_626 ? T_629 : 1'h0;
+ assign T_632 = sigY3[24];
+ assign T_634 = T_632 ? sExpX3 : 1'h0;
+ assign T_635 = T_631 | T_634;
+ assign T_636 = sigY3[25:24];
+ assign T_638 = T_636 == 1'h0;
+ assign T_640 = sExpX3 - 1'h1;
+ assign T_641 = T_640[10:0];
+ assign T_643 = T_638 ? T_641 : 1'h0;
+ assign sExpY = T_635 | T_643;
+ assign expY = sExpY[8:0];
+ assign T_646 = sigY3[22:0];
+ assign T_647 = sigY3[23:1];
+ assign fractY = sigX3Shift1 ? T_646 : T_647;
+ assign T_649 = sExpY[9:7];
+ assign overflowY = T_649 == 2'h3;
+ assign T_652 = ~ isZeroY;
+ assign T_653 = sExpY[9];
+ assign T_654 = sExpY[8:0];
+ assign T_656 = T_654 < 7'h6b;
+ assign T_657 = T_653 | T_656;
+ assign totalUnderflowY = T_652 & T_657;
+ assign T_659 = sExpX3[10];
+ assign T_662 = sigX3Shift1 ? 8'h82 : 8'h81;
+ assign T_663 = sExpX3_13 <= T_662;
+ assign T_664 = T_659 | T_663;
+ assign underflowY = roundInexact & T_664;
+ assign T_666 = roundingMode_min & signY;
+ assign T_667 = ~ signY;
+ assign T_668 = roundingMode_max & T_667;
+ assign roundMagUp = T_666 | T_668;
+ assign overflowY_roundMagUp = roundingMode_nearest_even | roundMagUp;
+ assign mulSpecial = isSpecialA | isSpecialB;
+ assign addSpecial = mulSpecial | isSpecialC;
+ assign notSpecial_addZeros = io_fromPreMul_isZeroProd & isZeroC;
+ assign T_674 = ~ addSpecial;
+ assign T_675 = ~ notSpecial_addZeros;
+ assign commonCase = T_674 & T_675;
+ assign T_677 = isInfA & isZeroB;
+ assign T_678 = isZeroA & isInfB;
+ assign T_679 = T_677 | T_678;
+ assign T_680 = ~ isNaNA;
+ assign T_681 = ~ isNaNB;
+ assign T_682 = T_680 & T_681;
+ assign T_683 = isInfA | isInfB;
+ assign T_684 = T_682 & T_683;
+ assign T_685 = T_684 & isInfC;
+ assign T_686 = T_685 & doSubMags;
+ assign notSigNaN_invalid = T_679 | T_686;
+ assign T_688 = isSigNaNA | isSigNaNB;
+ assign T_689 = T_688 | isSigNaNC;
+ assign invalid = T_689 | notSigNaN_invalid;
+ assign overflow = commonCase & overflowY;
+ assign underflow = commonCase & underflowY;
+ assign T_693 = commonCase & roundInexact;
+ assign inexact = overflow | T_693;
+ assign T_695 = notSpecial_addZeros | isZeroY;
+ assign notSpecial_isZeroOut = T_695 | totalUnderflowY;
+ assign T_697 = commonCase & totalUnderflowY;
+ assign pegMinFiniteMagOut = T_697 & roundMagUp;
+ assign T_699 = ~ overflowY_roundMagUp;
+ assign pegMaxFiniteMagOut = overflow & T_699;
+ assign T_701 = isInfA | isInfB;
+ assign T_702 = T_701 | isInfC;
+ assign T_703 = overflow & overflowY_roundMagUp;
+ assign notNaN_isInfOut = T_702 | T_703;
+ assign T_705 = isNaNA | isNaNB;
+ assign T_706 = T_705 | isNaNC;
+ assign isNaNOut = T_706 | notSigNaN_invalid;
+ assign T_709 = doSubMags == 1'h0;
+ assign T_710 = T_709 & io_fromPreMul_opSignC;
+ assign T_712 = isSpecialC == 1'h0;
+ assign T_713 = mulSpecial & T_712;
+ assign T_714 = T_713 & io_fromPreMul_signProd;
+ assign T_715 = T_710 | T_714;
+ assign T_717 = mulSpecial == 1'h0;
+ assign T_718 = T_717 & isSpecialC;
+ assign T_719 = T_718 & io_fromPreMul_opSignC;
+ assign T_720 = T_715 | T_719;
+ assign T_722 = mulSpecial == 1'h0;
+ assign T_723 = T_722 & notSpecial_addZeros;
+ assign T_724 = T_723 & doSubMags;
+ assign T_725 = T_724 & signZeroNotEqOpSigns;
+ assign uncommonCaseSignOut = T_720 | T_725;
+ assign T_728 = isNaNOut == 1'h0;
+ assign T_729 = T_728 & uncommonCaseSignOut;
+ assign T_730 = commonCase & signY;
+ assign signOut = T_729 | T_730;
+ assign T_734 = notSpecial_isZeroOut ? 9'h1c0 : 9'h0;
+ assign T_735 = ~ T_734;
+ assign T_736 = expY & T_735;
+ assign T_738 = ~ 9'h6b;
+ assign T_740 = pegMinFiniteMagOut ? T_738 : 9'h0;
+ assign T_741 = ~ T_740;
+ assign T_742 = T_736 & T_741;
+ assign T_745 = pegMaxFiniteMagOut ? 9'h80 : 9'h0;
+ assign T_746 = ~ T_745;
+ assign T_747 = T_742 & T_746;
+ assign T_750 = notNaN_isInfOut ? 7'h40 : 9'h0;
+ assign T_751 = ~ T_750;
+ assign T_752 = T_747 & T_751;
+ assign T_755 = pegMinFiniteMagOut ? 7'h6b : 9'h0;
+ assign T_756 = T_752 | T_755;
+ assign T_759 = pegMaxFiniteMagOut ? 9'h17f : 9'h0;
+ assign T_760 = T_756 | T_759;
+ assign T_763 = notNaN_isInfOut ? 9'h180 : 9'h0;
+ assign T_764 = T_760 | T_763;
+ assign T_767 = isNaNOut ? 9'h1c0 : 9'h0;
+ assign expOut = T_764 | T_767;
+ assign T_769 = totalUnderflowY & roundMagUp;
+ assign T_770 = T_769 | isNaNOut;
+ assign T_772 = T_770 ? 1'h0 : fractY;
+ assign T_773 = isNaNOut << 22;
+ assign T_774 = T_772 | T_773;
+ assign T_776 = 23'h0 - pegMaxFiniteMagOut;
+ assign T_777 = T_776[22:0];
+ assign fractOut = T_774 | T_777;
+ assign T_779 = {expOut,fractOut};
+ assign T_780 = {signOut,T_779};
+ assign T_782 = {invalid,1'h0};
+ assign T_783 = {underflow,inexact};
+ assign T_784 = {overflow,T_783};
+ assign T_785 = {T_782,T_784};
+endmodule
+module MulAddRecFN(
+ input clk,
+ input reset,
+ input [1:0] io_op,
+ input [32:0] io_a,
+ input [32:0] io_b,
+ input [32:0] io_c,
+ input [1:0] io_roundingMode,
+ output [32:0] io_out,
+ output [4:0] io_exceptionFlags
+);
+ wire mulAddRecFN_preMul_clk;
+ wire mulAddRecFN_preMul_reset;
+ wire [1:0] mulAddRecFN_preMul_io_op;
+ wire [32:0] mulAddRecFN_preMul_io_a;
+ wire [32:0] mulAddRecFN_preMul_io_b;
+ wire [32:0] mulAddRecFN_preMul_io_c;
+ wire [1:0] mulAddRecFN_preMul_io_roundingMode;
+ wire [23:0] mulAddRecFN_preMul_io_mulAddA;
+ wire [23:0] mulAddRecFN_preMul_io_mulAddB;
+ wire [47:0] mulAddRecFN_preMul_io_mulAddC;
+ wire [2:0] mulAddRecFN_preMul_io_toPostMul_highExpA;
+ wire mulAddRecFN_preMul_io_toPostMul_isNaN_isQuietNaNA;
+ wire [2:0] mulAddRecFN_preMul_io_toPostMul_highExpB;
+ wire mulAddRecFN_preMul_io_toPostMul_isNaN_isQuietNaNB;
+ wire mulAddRecFN_preMul_io_toPostMul_signProd;
+ wire mulAddRecFN_preMul_io_toPostMul_isZeroProd;
+ wire mulAddRecFN_preMul_io_toPostMul_opSignC;
+ wire [2:0] mulAddRecFN_preMul_io_toPostMul_highExpC;
+ wire mulAddRecFN_preMul_io_toPostMul_isNaN_isQuietNaNC;
+ wire mulAddRecFN_preMul_io_toPostMul_isCDominant;
+ wire mulAddRecFN_preMul_io_toPostMul_CAlignDist_0;
+ wire [6:0] mulAddRecFN_preMul_io_toPostMul_CAlignDist;
+ wire mulAddRecFN_preMul_io_toPostMul_bit0AlignedNegSigC;
+ wire [25:0] mulAddRecFN_preMul_io_toPostMul_highAlignedNegSigC;
+ wire [10:0] mulAddRecFN_preMul_io_toPostMul_sExpSum;
+ wire [1:0] mulAddRecFN_preMul_io_toPostMul_roundingMode;
+ wire mulAddRecFN_postMul_clk;
+ wire mulAddRecFN_postMul_reset;
+ wire [2:0] mulAddRecFN_postMul_io_fromPreMul_highExpA;
+ wire mulAddRecFN_postMul_io_fromPreMul_isNaN_isQuietNaNA;
+ wire [2:0] mulAddRecFN_postMul_io_fromPreMul_highExpB;
+ wire mulAddRecFN_postMul_io_fromPreMul_isNaN_isQuietNaNB;
+ wire mulAddRecFN_postMul_io_fromPreMul_signProd;
+ wire mulAddRecFN_postMul_io_fromPreMul_isZeroProd;
+ wire mulAddRecFN_postMul_io_fromPreMul_opSignC;
+ wire [2:0] mulAddRecFN_postMul_io_fromPreMul_highExpC;
+ wire mulAddRecFN_postMul_io_fromPreMul_isNaN_isQuietNaNC;
+ wire mulAddRecFN_postMul_io_fromPreMul_isCDominant;
+ wire mulAddRecFN_postMul_io_fromPreMul_CAlignDist_0;
+ wire [6:0] mulAddRecFN_postMul_io_fromPreMul_CAlignDist;
+ wire mulAddRecFN_postMul_io_fromPreMul_bit0AlignedNegSigC;
+ wire [25:0] mulAddRecFN_postMul_io_fromPreMul_highAlignedNegSigC;
+ wire [10:0] mulAddRecFN_postMul_io_fromPreMul_sExpSum;
+ wire [1:0] mulAddRecFN_postMul_io_fromPreMul_roundingMode;
+ wire [48:0] mulAddRecFN_postMul_io_mulAddResult;
+ wire [32:0] mulAddRecFN_postMul_io_out;
+ wire [4:0] mulAddRecFN_postMul_io_exceptionFlags;
+ wire [47:0] T_14;
+ wire [48:0] T_16;
+ wire [49:0] T_17;
+ wire [48:0] T_18;
+ MulAddRecFN_preMul mulAddRecFN_preMul (
+ .clk(mulAddRecFN_preMul_clk),
+ .reset(mulAddRecFN_preMul_reset),
+ .io_op(mulAddRecFN_preMul_io_op),
+ .io_a(mulAddRecFN_preMul_io_a),
+ .io_b(mulAddRecFN_preMul_io_b),
+ .io_c(mulAddRecFN_preMul_io_c),
+ .io_roundingMode(mulAddRecFN_preMul_io_roundingMode),
+ .io_mulAddA(mulAddRecFN_preMul_io_mulAddA),
+ .io_mulAddB(mulAddRecFN_preMul_io_mulAddB),
+ .io_mulAddC(mulAddRecFN_preMul_io_mulAddC),
+ .io_toPostMul_highExpA(mulAddRecFN_preMul_io_toPostMul_highExpA),
+ .io_toPostMul_isNaN_isQuietNaNA(mulAddRecFN_preMul_io_toPostMul_isNaN_isQuietNaNA),
+ .io_toPostMul_highExpB(mulAddRecFN_preMul_io_toPostMul_highExpB),
+ .io_toPostMul_isNaN_isQuietNaNB(mulAddRecFN_preMul_io_toPostMul_isNaN_isQuietNaNB),
+ .io_toPostMul_signProd(mulAddRecFN_preMul_io_toPostMul_signProd),
+ .io_toPostMul_isZeroProd(mulAddRecFN_preMul_io_toPostMul_isZeroProd),
+ .io_toPostMul_opSignC(mulAddRecFN_preMul_io_toPostMul_opSignC),
+ .io_toPostMul_highExpC(mulAddRecFN_preMul_io_toPostMul_highExpC),
+ .io_toPostMul_isNaN_isQuietNaNC(mulAddRecFN_preMul_io_toPostMul_isNaN_isQuietNaNC),
+ .io_toPostMul_isCDominant(mulAddRecFN_preMul_io_toPostMul_isCDominant),
+ .io_toPostMul_CAlignDist_0(mulAddRecFN_preMul_io_toPostMul_CAlignDist_0),
+ .io_toPostMul_CAlignDist(mulAddRecFN_preMul_io_toPostMul_CAlignDist),
+ .io_toPostMul_bit0AlignedNegSigC(mulAddRecFN_preMul_io_toPostMul_bit0AlignedNegSigC),
+ .io_toPostMul_highAlignedNegSigC(mulAddRecFN_preMul_io_toPostMul_highAlignedNegSigC),
+ .io_toPostMul_sExpSum(mulAddRecFN_preMul_io_toPostMul_sExpSum),
+ .io_toPostMul_roundingMode(mulAddRecFN_preMul_io_toPostMul_roundingMode)
+ );
+ MulAddRecFN_postMul mulAddRecFN_postMul (
+ .clk(mulAddRecFN_postMul_clk),
+ .reset(mulAddRecFN_postMul_reset),
+ .io_fromPreMul_highExpA(mulAddRecFN_postMul_io_fromPreMul_highExpA),
+ .io_fromPreMul_isNaN_isQuietNaNA(mulAddRecFN_postMul_io_fromPreMul_isNaN_isQuietNaNA),
+ .io_fromPreMul_highExpB(mulAddRecFN_postMul_io_fromPreMul_highExpB),
+ .io_fromPreMul_isNaN_isQuietNaNB(mulAddRecFN_postMul_io_fromPreMul_isNaN_isQuietNaNB),
+ .io_fromPreMul_signProd(mulAddRecFN_postMul_io_fromPreMul_signProd),
+ .io_fromPreMul_isZeroProd(mulAddRecFN_postMul_io_fromPreMul_isZeroProd),
+ .io_fromPreMul_opSignC(mulAddRecFN_postMul_io_fromPreMul_opSignC),
+ .io_fromPreMul_highExpC(mulAddRecFN_postMul_io_fromPreMul_highExpC),
+ .io_fromPreMul_isNaN_isQuietNaNC(mulAddRecFN_postMul_io_fromPreMul_isNaN_isQuietNaNC),
+ .io_fromPreMul_isCDominant(mulAddRecFN_postMul_io_fromPreMul_isCDominant),
+ .io_fromPreMul_CAlignDist_0(mulAddRecFN_postMul_io_fromPreMul_CAlignDist_0),
+ .io_fromPreMul_CAlignDist(mulAddRecFN_postMul_io_fromPreMul_CAlignDist),
+ .io_fromPreMul_bit0AlignedNegSigC(mulAddRecFN_postMul_io_fromPreMul_bit0AlignedNegSigC),
+ .io_fromPreMul_highAlignedNegSigC(mulAddRecFN_postMul_io_fromPreMul_highAlignedNegSigC),
+ .io_fromPreMul_sExpSum(mulAddRecFN_postMul_io_fromPreMul_sExpSum),
+ .io_fromPreMul_roundingMode(mulAddRecFN_postMul_io_fromPreMul_roundingMode),
+ .io_mulAddResult(mulAddRecFN_postMul_io_mulAddResult),
+ .io_out(mulAddRecFN_postMul_io_out),
+ .io_exceptionFlags(mulAddRecFN_postMul_io_exceptionFlags)
+ );
+ assign io_out = mulAddRecFN_postMul_io_out;
+ assign io_exceptionFlags = mulAddRecFN_postMul_io_exceptionFlags;
+ assign mulAddRecFN_preMul_clk = clk;
+ assign mulAddRecFN_preMul_reset = reset;
+ assign mulAddRecFN_preMul_io_op = io_op;
+ assign mulAddRecFN_preMul_io_a = io_a;
+ assign mulAddRecFN_preMul_io_b = io_b;
+ assign mulAddRecFN_preMul_io_c = io_c;
+ assign mulAddRecFN_preMul_io_roundingMode = io_roundingMode;
+ assign mulAddRecFN_postMul_clk = clk;
+ assign mulAddRecFN_postMul_reset = reset;
+ assign mulAddRecFN_postMul_io_fromPreMul_highExpA = mulAddRecFN_preMul_io_toPostMul_highExpA;
+ assign mulAddRecFN_postMul_io_fromPreMul_isNaN_isQuietNaNA = mulAddRecFN_preMul_io_toPostMul_isNaN_isQuietNaNA;
+ assign mulAddRecFN_postMul_io_fromPreMul_highExpB = mulAddRecFN_preMul_io_toPostMul_highExpB;
+ assign mulAddRecFN_postMul_io_fromPreMul_isNaN_isQuietNaNB = mulAddRecFN_preMul_io_toPostMul_isNaN_isQuietNaNB;
+ assign mulAddRecFN_postMul_io_fromPreMul_signProd = mulAddRecFN_preMul_io_toPostMul_signProd;
+ assign mulAddRecFN_postMul_io_fromPreMul_isZeroProd = mulAddRecFN_preMul_io_toPostMul_isZeroProd;
+ assign mulAddRecFN_postMul_io_fromPreMul_opSignC = mulAddRecFN_preMul_io_toPostMul_opSignC;
+ assign mulAddRecFN_postMul_io_fromPreMul_highExpC = mulAddRecFN_preMul_io_toPostMul_highExpC;
+ assign mulAddRecFN_postMul_io_fromPreMul_isNaN_isQuietNaNC = mulAddRecFN_preMul_io_toPostMul_isNaN_isQuietNaNC;
+ assign mulAddRecFN_postMul_io_fromPreMul_isCDominant = mulAddRecFN_preMul_io_toPostMul_isCDominant;
+ assign mulAddRecFN_postMul_io_fromPreMul_CAlignDist_0 = mulAddRecFN_preMul_io_toPostMul_CAlignDist_0;
+ assign mulAddRecFN_postMul_io_fromPreMul_CAlignDist = mulAddRecFN_preMul_io_toPostMul_CAlignDist;
+ assign mulAddRecFN_postMul_io_fromPreMul_bit0AlignedNegSigC = mulAddRecFN_preMul_io_toPostMul_bit0AlignedNegSigC;
+ assign mulAddRecFN_postMul_io_fromPreMul_highAlignedNegSigC = mulAddRecFN_preMul_io_toPostMul_highAlignedNegSigC;
+ assign mulAddRecFN_postMul_io_fromPreMul_sExpSum = mulAddRecFN_preMul_io_toPostMul_sExpSum;
+ assign mulAddRecFN_postMul_io_fromPreMul_roundingMode = mulAddRecFN_preMul_io_toPostMul_roundingMode;
+ assign mulAddRecFN_postMul_io_mulAddResult = T_18;
+ assign T_14 = mulAddRecFN_preMul_io_mulAddA * mulAddRecFN_preMul_io_mulAddB;
+ assign T_16 = {1'h0,mulAddRecFN_preMul_io_mulAddC};
+ assign T_17 = T_14 + T_16;
+ assign T_18 = T_17[48:0];
+endmodule
+module FPUFMAPipe(
+ input clk,
+ input reset,
+ input io_in_valid,
+ input [4:0] io_in_bits_cmd,
+ input io_in_bits_ldst,
+ input io_in_bits_wen,
+ input io_in_bits_ren1,
+ input io_in_bits_ren2,
+ input io_in_bits_ren3,
+ input io_in_bits_swap12,
+ input io_in_bits_swap23,
+ input io_in_bits_single,
+ input io_in_bits_fromint,
+ input io_in_bits_toint,
+ input io_in_bits_fastpipe,
+ input io_in_bits_fma,
+ input io_in_bits_div,
+ input io_in_bits_sqrt,
+ input io_in_bits_round,
+ input io_in_bits_wflags,
+ input [2:0] io_in_bits_rm,
+ input [1:0] io_in_bits_typ,
+ input [64:0] io_in_bits_in1,
+ input [64:0] io_in_bits_in2,
+ input [64:0] io_in_bits_in3,
+ output io_out_valid,
+ output [64:0] io_out_bits_data,
+ output [4:0] io_out_bits_exc
+);
+ wire [31:0] one;
+ wire T_136;
+ wire T_137;
+ wire T_138;
+ wire [32:0] zero;
+ reg valid;
+ reg [4:0] in_cmd;
+ reg in_ldst;
+ reg in_wen;
+ reg in_ren1;
+ reg in_ren2;
+ reg in_ren3;
+ reg in_swap12;
+ reg in_swap23;
+ reg in_single;
+ reg in_fromint;
+ reg in_toint;
+ reg in_fastpipe;
+ reg in_fma;
+ reg in_div;
+ reg in_sqrt;
+ reg in_round;
+ reg in_wflags;
+ reg [2:0] in_rm;
+ reg [1:0] in_typ;
+ reg [64:0] in_in1;
+ reg [64:0] in_in2;
+ reg [64:0] in_in3;
+ wire T_187;
+ wire T_188;
+ wire T_189;
+ wire T_190;
+ wire [1:0] T_191;
+ wire T_192;
+ wire T_194;
+ wire fma_clk;
+ wire fma_reset;
+ wire [1:0] fma_io_op;
+ wire [32:0] fma_io_a;
+ wire [32:0] fma_io_b;
+ wire [32:0] fma_io_c;
+ wire [1:0] fma_io_roundingMode;
+ wire [32:0] fma_io_out;
+ wire [4:0] fma_io_exceptionFlags;
+ wire [64:0] res_data;
+ wire [4:0] res_exc;
+ wire [31:0] GEN_0;
+ wire [31:0] T_203;
+ wire [64:0] T_204;
+ reg T_207;
+ reg [64:0] T_208_data;
+ reg [4:0] T_208_exc;
+ wire T_219_valid;
+ wire [64:0] T_219_bits_data;
+ wire [4:0] T_219_bits_exc;
+ MulAddRecFN fma (
+ .clk(fma_clk),
+ .reset(fma_reset),
+ .io_op(fma_io_op),
+ .io_a(fma_io_a),
+ .io_b(fma_io_b),
+ .io_c(fma_io_c),
+ .io_roundingMode(fma_io_roundingMode),
+ .io_out(fma_io_out),
+ .io_exceptionFlags(fma_io_exceptionFlags)
+ );
+ assign io_out_valid = T_219_valid;
+ assign io_out_bits_data = T_219_bits_data;
+ assign io_out_bits_exc = T_219_bits_exc;
+ assign one = 1'h1 << 31;
+ assign T_136 = io_in_bits_in1[32];
+ assign T_137 = io_in_bits_in2[32];
+ assign T_138 = T_136 ^ T_137;
+ assign zero = T_138 << 32;
+ assign T_187 = io_in_bits_cmd[1];
+ assign T_188 = io_in_bits_ren3 | io_in_bits_swap23;
+ assign T_189 = T_187 & T_188;
+ assign T_190 = io_in_bits_cmd[0];
+ assign T_191 = {T_189,T_190};
+ assign T_192 = io_in_bits_ren3 | io_in_bits_swap23;
+ assign T_194 = T_192 == 1'h0;
+ assign fma_clk = clk;
+ assign fma_reset = reset;
+ assign fma_io_op = in_cmd;
+ assign fma_io_a = in_in1;
+ assign fma_io_b = in_in2;
+ assign fma_io_c = in_in3;
+ assign fma_io_roundingMode = in_rm;
+ assign res_data = T_204;
+ assign res_exc = fma_io_exceptionFlags;
+ assign GEN_0 = $signed(32'hffffffff);
+ assign T_203 = $unsigned(GEN_0);
+ assign T_204 = {T_203,fma_io_out};
+ assign T_219_valid = T_207;
+ assign T_219_bits_data = T_208_data;
+ assign T_219_bits_exc = T_208_exc;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ valid = {1{$random}};
+ in_cmd = {1{$random}};
+ in_ldst = {1{$random}};
+ in_wen = {1{$random}};
+ in_ren1 = {1{$random}};
+ in_ren2 = {1{$random}};
+ in_ren3 = {1{$random}};
+ in_swap12 = {1{$random}};
+ in_swap23 = {1{$random}};
+ in_single = {1{$random}};
+ in_fromint = {1{$random}};
+ in_toint = {1{$random}};
+ in_fastpipe = {1{$random}};
+ in_fma = {1{$random}};
+ in_div = {1{$random}};
+ in_sqrt = {1{$random}};
+ in_round = {1{$random}};
+ in_wflags = {1{$random}};
+ in_rm = {1{$random}};
+ in_typ = {1{$random}};
+ in_in1 = {3{$random}};
+ in_in2 = {3{$random}};
+ in_in3 = {3{$random}};
+ T_207 = {1{$random}};
+ T_208_data = {3{$random}};
+ T_208_exc = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(1'h0) begin
+ ;
+ end else begin
+ valid <= io_in_valid;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_cmd <= T_191;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_ldst <= io_in_bits_ldst;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_wen <= io_in_bits_wen;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_ren1 <= io_in_bits_ren1;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_ren2 <= io_in_bits_ren2;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_ren3 <= io_in_bits_ren3;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_swap12 <= io_in_bits_swap12;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_swap23 <= io_in_bits_swap23;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_single <= io_in_bits_single;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_fromint <= io_in_bits_fromint;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_toint <= io_in_bits_toint;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_fastpipe <= io_in_bits_fastpipe;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_fma <= io_in_bits_fma;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_div <= io_in_bits_div;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_sqrt <= io_in_bits_sqrt;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_round <= io_in_bits_round;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_wflags <= io_in_bits_wflags;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_rm <= io_in_bits_rm;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_typ <= io_in_bits_typ;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_in1 <= io_in_bits_in1;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ if(io_in_bits_swap23) begin
+ in_in2 <= one;
+ end else begin
+ in_in2 <= io_in_bits_in2;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ if(T_194) begin
+ in_in3 <= zero;
+ end else begin
+ in_in3 <= io_in_bits_in3;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_207 <= 1'h0;
+ end else begin
+ T_207 <= valid;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(valid) begin
+ T_208_data <= res_data;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(valid) begin
+ T_208_exc <= res_exc;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module MulAddRecFN_preMul_115(
+ input clk,
+ input reset,
+ input [1:0] io_op,
+ input [64:0] io_a,
+ input [64:0] io_b,
+ input [64:0] io_c,
+ input [1:0] io_roundingMode,
+ output [52:0] io_mulAddA,
+ output [52:0] io_mulAddB,
+ output [105:0] io_mulAddC,
+ output [2:0] io_toPostMul_highExpA,
+ output io_toPostMul_isNaN_isQuietNaNA,
+ output [2:0] io_toPostMul_highExpB,
+ output io_toPostMul_isNaN_isQuietNaNB,
+ output io_toPostMul_signProd,
+ output io_toPostMul_isZeroProd,
+ output io_toPostMul_opSignC,
+ output [2:0] io_toPostMul_highExpC,
+ output io_toPostMul_isNaN_isQuietNaNC,
+ output io_toPostMul_isCDominant,
+ output io_toPostMul_CAlignDist_0,
+ output [7:0] io_toPostMul_CAlignDist,
+ output io_toPostMul_bit0AlignedNegSigC,
+ output [54:0] io_toPostMul_highAlignedNegSigC,
+ output [13:0] io_toPostMul_sExpSum,
+ output [1:0] io_toPostMul_roundingMode
+);
+ wire signA;
+ wire [11:0] expA;
+ wire [51:0] fractA;
+ wire [2:0] T_50;
+ wire isZeroA;
+ wire T_54;
+ wire [52:0] sigA;
+ wire signB;
+ wire [11:0] expB;
+ wire [51:0] fractB;
+ wire [2:0] T_59;
+ wire isZeroB;
+ wire T_63;
+ wire [52:0] sigB;
+ wire T_65;
+ wire T_66;
+ wire opSignC;
+ wire [11:0] expC;
+ wire [51:0] fractC;
+ wire [2:0] T_70;
+ wire isZeroC;
+ wire T_74;
+ wire [52:0] sigC;
+ wire T_76;
+ wire T_77;
+ wire signProd;
+ wire isZeroProd;
+ wire T_80;
+ wire T_82;
+ wire [3:0] T_84;
+ wire [2:0] T_85;
+ wire [10:0] T_86;
+ wire [13:0] T_87;
+ wire [14:0] T_88;
+ wire [13:0] T_89;
+ wire [14:0] T_91;
+ wire [13:0] sExpAlignedProd;
+ wire doSubMags;
+ wire [14:0] T_94;
+ wire [13:0] sNatCAlignDist;
+ wire T_96;
+ wire CAlignDist_floor;
+ wire [12:0] T_98;
+ wire T_100;
+ wire CAlignDist_0;
+ wire T_103;
+ wire [12:0] T_104;
+ wire T_106;
+ wire T_107;
+ wire isCDominant;
+ wire [12:0] T_110;
+ wire T_112;
+ wire [7:0] T_113;
+ wire [7:0] T_115;
+ wire [7:0] CAlignDist;
+ wire [13:0] sExpSum;
+ wire [256:0] GEN_0;
+ wire [256:0] T_119;
+ wire [52:0] T_120;
+ wire [31:0] T_121;
+ wire [31:0] T_124;
+ wire [31:0] T_125;
+ wire [15:0] T_126;
+ wire [31:0] T_127;
+ wire [15:0] T_128;
+ wire [31:0] T_129;
+ wire [31:0] T_130;
+ wire [31:0] T_131;
+ wire [31:0] T_132;
+ wire [23:0] T_133;
+ wire [31:0] T_134;
+ wire [31:0] T_135;
+ wire [23:0] T_136;
+ wire [31:0] T_137;
+ wire [23:0] T_138;
+ wire [31:0] T_139;
+ wire [31:0] T_140;
+ wire [31:0] T_141;
+ wire [31:0] T_142;
+ wire [27:0] T_143;
+ wire [31:0] T_144;
+ wire [31:0] T_145;
+ wire [27:0] T_146;
+ wire [31:0] T_147;
+ wire [27:0] T_148;
+ wire [31:0] T_149;
+ wire [31:0] T_150;
+ wire [31:0] T_151;
+ wire [31:0] T_152;
+ wire [29:0] T_153;
+ wire [31:0] T_154;
+ wire [31:0] T_155;
+ wire [29:0] T_156;
+ wire [31:0] T_157;
+ wire [29:0] T_158;
+ wire [31:0] T_159;
+ wire [31:0] T_160;
+ wire [31:0] T_161;
+ wire [31:0] T_162;
+ wire [30:0] T_163;
+ wire [31:0] T_164;
+ wire [31:0] T_165;
+ wire [30:0] T_166;
+ wire [31:0] T_167;
+ wire [30:0] T_168;
+ wire [31:0] T_169;
+ wire [31:0] T_170;
+ wire [31:0] T_171;
+ wire [31:0] T_172;
+ wire [20:0] T_173;
+ wire [15:0] T_174;
+ wire [15:0] T_177;
+ wire [15:0] T_178;
+ wire [7:0] T_179;
+ wire [15:0] T_180;
+ wire [7:0] T_181;
+ wire [15:0] T_182;
+ wire [15:0] T_183;
+ wire [15:0] T_184;
+ wire [15:0] T_185;
+ wire [11:0] T_186;
+ wire [15:0] T_187;
+ wire [15:0] T_188;
+ wire [11:0] T_189;
+ wire [15:0] T_190;
+ wire [11:0] T_191;
+ wire [15:0] T_192;
+ wire [15:0] T_193;
+ wire [15:0] T_194;
+ wire [15:0] T_195;
+ wire [13:0] T_196;
+ wire [15:0] T_197;
+ wire [15:0] T_198;
+ wire [13:0] T_199;
+ wire [15:0] T_200;
+ wire [13:0] T_201;
+ wire [15:0] T_202;
+ wire [15:0] T_203;
+ wire [15:0] T_204;
+ wire [15:0] T_205;
+ wire [14:0] T_206;
+ wire [15:0] T_207;
+ wire [15:0] T_208;
+ wire [14:0] T_209;
+ wire [15:0] T_210;
+ wire [14:0] T_211;
+ wire [15:0] T_212;
+ wire [15:0] T_213;
+ wire [15:0] T_214;
+ wire [15:0] T_215;
+ wire [4:0] T_216;
+ wire [3:0] T_217;
+ wire [1:0] T_218;
+ wire T_219;
+ wire T_220;
+ wire [1:0] T_221;
+ wire [1:0] T_222;
+ wire T_223;
+ wire T_224;
+ wire [1:0] T_225;
+ wire [3:0] T_226;
+ wire T_227;
+ wire [4:0] T_228;
+ wire [20:0] T_229;
+ wire [52:0] CExtraMask;
+ wire [52:0] T_231;
+ wire [52:0] negSigC;
+ wire [108:0] T_234;
+ wire [107:0] T_235;
+ wire [160:0] T_236;
+ wire [161:0] T_237;
+ wire [161:0] T_238;
+ wire [161:0] T_239;
+ wire [52:0] T_240;
+ wire T_242;
+ wire T_243;
+ wire [161:0] T_244;
+ wire [162:0] T_245;
+ wire [161:0] alignedNegSigC;
+ wire [105:0] T_247;
+ wire [2:0] T_248;
+ wire T_249;
+ wire [2:0] T_250;
+ wire T_251;
+ wire [2:0] T_252;
+ wire T_253;
+ wire T_254;
+ wire [54:0] T_255;
+ assign io_mulAddA = sigA;
+ assign io_mulAddB = sigB;
+ assign io_mulAddC = T_247;
+ assign io_toPostMul_highExpA = T_248;
+ assign io_toPostMul_isNaN_isQuietNaNA = T_249;
+ assign io_toPostMul_highExpB = T_250;
+ assign io_toPostMul_isNaN_isQuietNaNB = T_251;
+ assign io_toPostMul_signProd = signProd;
+ assign io_toPostMul_isZeroProd = isZeroProd;
+ assign io_toPostMul_opSignC = opSignC;
+ assign io_toPostMul_highExpC = T_252;
+ assign io_toPostMul_isNaN_isQuietNaNC = T_253;
+ assign io_toPostMul_isCDominant = isCDominant;
+ assign io_toPostMul_CAlignDist_0 = CAlignDist_0;
+ assign io_toPostMul_CAlignDist = CAlignDist;
+ assign io_toPostMul_bit0AlignedNegSigC = T_254;
+ assign io_toPostMul_highAlignedNegSigC = T_255;
+ assign io_toPostMul_sExpSum = sExpSum;
+ assign io_toPostMul_roundingMode = io_roundingMode;
+ assign signA = io_a[64];
+ assign expA = io_a[63:52];
+ assign fractA = io_a[51:0];
+ assign T_50 = expA[11:9];
+ assign isZeroA = T_50 == 1'h0;
+ assign T_54 = isZeroA == 1'h0;
+ assign sigA = {T_54,fractA};
+ assign signB = io_b[64];
+ assign expB = io_b[63:52];
+ assign fractB = io_b[51:0];
+ assign T_59 = expB[11:9];
+ assign isZeroB = T_59 == 1'h0;
+ assign T_63 = isZeroB == 1'h0;
+ assign sigB = {T_63,fractB};
+ assign T_65 = io_c[64];
+ assign T_66 = io_op[0];
+ assign opSignC = T_65 ^ T_66;
+ assign expC = io_c[63:52];
+ assign fractC = io_c[51:0];
+ assign T_70 = expC[11:9];
+ assign isZeroC = T_70 == 1'h0;
+ assign T_74 = isZeroC == 1'h0;
+ assign sigC = {T_74,fractC};
+ assign T_76 = signA ^ signB;
+ assign T_77 = io_op[1];
+ assign signProd = T_76 ^ T_77;
+ assign isZeroProd = isZeroA | isZeroB;
+ assign T_80 = expB[11];
+ assign T_82 = T_80 == 1'h0;
+ assign T_84 = 3'h0 - T_82;
+ assign T_85 = T_84[2:0];
+ assign T_86 = expB[10:0];
+ assign T_87 = {T_85,T_86};
+ assign T_88 = expA + T_87;
+ assign T_89 = T_88[13:0];
+ assign T_91 = T_89 + 6'h38;
+ assign sExpAlignedProd = T_91[13:0];
+ assign doSubMags = signProd ^ opSignC;
+ assign T_94 = sExpAlignedProd - expC;
+ assign sNatCAlignDist = T_94[13:0];
+ assign T_96 = sNatCAlignDist[13];
+ assign CAlignDist_floor = isZeroProd | T_96;
+ assign T_98 = sNatCAlignDist[12:0];
+ assign T_100 = T_98 == 1'h0;
+ assign CAlignDist_0 = CAlignDist_floor | T_100;
+ assign T_103 = isZeroC == 1'h0;
+ assign T_104 = sNatCAlignDist[12:0];
+ assign T_106 = T_104 < 6'h36;
+ assign T_107 = CAlignDist_floor | T_106;
+ assign isCDominant = T_103 & T_107;
+ assign T_110 = sNatCAlignDist[12:0];
+ assign T_112 = T_110 < 8'ha1;
+ assign T_113 = sNatCAlignDist[7:0];
+ assign T_115 = T_112 ? T_113 : 8'ha1;
+ assign CAlignDist = CAlignDist_floor ? 1'h0 : T_115;
+ assign sExpSum = CAlignDist_floor ? expC : sExpAlignedProd;
+ assign GEN_0 = $signed(257'h10000000000000000000000000000000000000000000000000000000000000000);
+ assign T_119 = $signed(GEN_0) >>> CAlignDist;
+ assign T_120 = T_119[147:95];
+ assign T_121 = T_120[31:0];
+ assign T_124 = 16'hffff << 16;
+ assign T_125 = 32'hffffffff ^ T_124;
+ assign T_126 = T_121[31:16];
+ assign T_127 = T_126 & T_125;
+ assign T_128 = T_121[15:0];
+ assign T_129 = T_128 << 16;
+ assign T_130 = ~ T_125;
+ assign T_131 = T_129 & T_130;
+ assign T_132 = T_127 | T_131;
+ assign T_133 = T_125[23:0];
+ assign T_134 = T_133 << 8;
+ assign T_135 = T_125 ^ T_134;
+ assign T_136 = T_132[31:8];
+ assign T_137 = T_136 & T_135;
+ assign T_138 = T_132[23:0];
+ assign T_139 = T_138 << 8;
+ assign T_140 = ~ T_135;
+ assign T_141 = T_139 & T_140;
+ assign T_142 = T_137 | T_141;
+ assign T_143 = T_135[27:0];
+ assign T_144 = T_143 << 4;
+ assign T_145 = T_135 ^ T_144;
+ assign T_146 = T_142[31:4];
+ assign T_147 = T_146 & T_145;
+ assign T_148 = T_142[27:0];
+ assign T_149 = T_148 << 4;
+ assign T_150 = ~ T_145;
+ assign T_151 = T_149 & T_150;
+ assign T_152 = T_147 | T_151;
+ assign T_153 = T_145[29:0];
+ assign T_154 = T_153 << 2;
+ assign T_155 = T_145 ^ T_154;
+ assign T_156 = T_152[31:2];
+ assign T_157 = T_156 & T_155;
+ assign T_158 = T_152[29:0];
+ assign T_159 = T_158 << 2;
+ assign T_160 = ~ T_155;
+ assign T_161 = T_159 & T_160;
+ assign T_162 = T_157 | T_161;
+ assign T_163 = T_155[30:0];
+ assign T_164 = T_163 << 1;
+ assign T_165 = T_155 ^ T_164;
+ assign T_166 = T_162[31:1];
+ assign T_167 = T_166 & T_165;
+ assign T_168 = T_162[30:0];
+ assign T_169 = T_168 << 1;
+ assign T_170 = ~ T_165;
+ assign T_171 = T_169 & T_170;
+ assign T_172 = T_167 | T_171;
+ assign T_173 = T_120[52:32];
+ assign T_174 = T_173[15:0];
+ assign T_177 = 8'hff << 8;
+ assign T_178 = 16'hffff ^ T_177;
+ assign T_179 = T_174[15:8];
+ assign T_180 = T_179 & T_178;
+ assign T_181 = T_174[7:0];
+ assign T_182 = T_181 << 8;
+ assign T_183 = ~ T_178;
+ assign T_184 = T_182 & T_183;
+ assign T_185 = T_180 | T_184;
+ assign T_186 = T_178[11:0];
+ assign T_187 = T_186 << 4;
+ assign T_188 = T_178 ^ T_187;
+ assign T_189 = T_185[15:4];
+ assign T_190 = T_189 & T_188;
+ assign T_191 = T_185[11:0];
+ assign T_192 = T_191 << 4;
+ assign T_193 = ~ T_188;
+ assign T_194 = T_192 & T_193;
+ assign T_195 = T_190 | T_194;
+ assign T_196 = T_188[13:0];
+ assign T_197 = T_196 << 2;
+ assign T_198 = T_188 ^ T_197;
+ assign T_199 = T_195[15:2];
+ assign T_200 = T_199 & T_198;
+ assign T_201 = T_195[13:0];
+ assign T_202 = T_201 << 2;
+ assign T_203 = ~ T_198;
+ assign T_204 = T_202 & T_203;
+ assign T_205 = T_200 | T_204;
+ assign T_206 = T_198[14:0];
+ assign T_207 = T_206 << 1;
+ assign T_208 = T_198 ^ T_207;
+ assign T_209 = T_205[15:1];
+ assign T_210 = T_209 & T_208;
+ assign T_211 = T_205[14:0];
+ assign T_212 = T_211 << 1;
+ assign T_213 = ~ T_208;
+ assign T_214 = T_212 & T_213;
+ assign T_215 = T_210 | T_214;
+ assign T_216 = T_173[20:16];
+ assign T_217 = T_216[3:0];
+ assign T_218 = T_217[1:0];
+ assign T_219 = T_218[0];
+ assign T_220 = T_218[1];
+ assign T_221 = {T_219,T_220};
+ assign T_222 = T_217[3:2];
+ assign T_223 = T_222[0];
+ assign T_224 = T_222[1];
+ assign T_225 = {T_223,T_224};
+ assign T_226 = {T_221,T_225};
+ assign T_227 = T_216[4];
+ assign T_228 = {T_226,T_227};
+ assign T_229 = {T_215,T_228};
+ assign CExtraMask = {T_172,T_229};
+ assign T_231 = ~ sigC;
+ assign negSigC = doSubMags ? T_231 : sigC;
+ assign T_234 = 108'h0 - doSubMags;
+ assign T_235 = T_234[107:0];
+ assign T_236 = {negSigC,T_235};
+ assign T_237 = {doSubMags,T_236};
+ assign T_238 = $signed(T_237);
+ assign T_239 = $signed(T_238) >>> CAlignDist;
+ assign T_240 = sigC & CExtraMask;
+ assign T_242 = T_240 != 1'h0;
+ assign T_243 = T_242 ^ doSubMags;
+ assign T_244 = $unsigned(T_239);
+ assign T_245 = {T_244,T_243};
+ assign alignedNegSigC = T_245[161:0];
+ assign T_247 = alignedNegSigC[106:1];
+ assign T_248 = expA[11:9];
+ assign T_249 = fractA[51];
+ assign T_250 = expB[11:9];
+ assign T_251 = fractB[51];
+ assign T_252 = expC[11:9];
+ assign T_253 = fractC[51];
+ assign T_254 = alignedNegSigC[0];
+ assign T_255 = alignedNegSigC[161:107];
+endmodule
+module MulAddRecFN_postMul_116(
+ input clk,
+ input reset,
+ input [2:0] io_fromPreMul_highExpA,
+ input io_fromPreMul_isNaN_isQuietNaNA,
+ input [2:0] io_fromPreMul_highExpB,
+ input io_fromPreMul_isNaN_isQuietNaNB,
+ input io_fromPreMul_signProd,
+ input io_fromPreMul_isZeroProd,
+ input io_fromPreMul_opSignC,
+ input [2:0] io_fromPreMul_highExpC,
+ input io_fromPreMul_isNaN_isQuietNaNC,
+ input io_fromPreMul_isCDominant,
+ input io_fromPreMul_CAlignDist_0,
+ input [7:0] io_fromPreMul_CAlignDist,
+ input io_fromPreMul_bit0AlignedNegSigC,
+ input [54:0] io_fromPreMul_highAlignedNegSigC,
+ input [13:0] io_fromPreMul_sExpSum,
+ input [1:0] io_fromPreMul_roundingMode,
+ input [106:0] io_mulAddResult,
+ output [64:0] io_out,
+ output [4:0] io_exceptionFlags
+);
+ wire isZeroA;
+ wire [1:0] T_44;
+ wire isSpecialA;
+ wire T_47;
+ wire T_49;
+ wire isInfA;
+ wire T_51;
+ wire isNaNA;
+ wire T_54;
+ wire isSigNaNA;
+ wire isZeroB;
+ wire [1:0] T_58;
+ wire isSpecialB;
+ wire T_61;
+ wire T_63;
+ wire isInfB;
+ wire T_65;
+ wire isNaNB;
+ wire T_68;
+ wire isSigNaNB;
+ wire isZeroC;
+ wire [1:0] T_72;
+ wire isSpecialC;
+ wire T_75;
+ wire T_77;
+ wire isInfC;
+ wire T_79;
+ wire isNaNC;
+ wire T_82;
+ wire isSigNaNC;
+ wire roundingMode_nearest_even;
+ wire roundingMode_minMag;
+ wire roundingMode_min;
+ wire roundingMode_max;
+ wire signZeroNotEqOpSigns;
+ wire doSubMags;
+ wire T_92;
+ wire [55:0] T_94;
+ wire [54:0] T_95;
+ wire [54:0] T_96;
+ wire [105:0] T_97;
+ wire [106:0] T_98;
+ wire [161:0] sigSum;
+ wire [107:0] T_101;
+ wire [107:0] T_102;
+ wire [107:0] T_103;
+ wire [108:0] T_104;
+ wire [108:0] T_105;
+ wire [107:0] T_107;
+ wire T_108;
+ wire T_110;
+ wire T_112;
+ wire T_114;
+ wire T_116;
+ wire T_118;
+ wire T_120;
+ wire T_122;
+ wire T_124;
+ wire T_126;
+ wire T_128;
+ wire T_130;
+ wire T_132;
+ wire T_134;
+ wire T_136;
+ wire T_138;
+ wire T_140;
+ wire T_142;
+ wire T_144;
+ wire T_146;
+ wire T_148;
+ wire T_150;
+ wire T_152;
+ wire T_154;
+ wire T_156;
+ wire T_158;
+ wire T_160;
+ wire T_162;
+ wire T_164;
+ wire T_166;
+ wire T_168;
+ wire T_170;
+ wire T_172;
+ wire T_174;
+ wire T_176;
+ wire T_178;
+ wire T_180;
+ wire T_182;
+ wire T_184;
+ wire T_186;
+ wire T_188;
+ wire T_190;
+ wire T_192;
+ wire T_194;
+ wire T_196;
+ wire T_198;
+ wire T_200;
+ wire T_202;
+ wire T_204;
+ wire T_206;
+ wire T_208;
+ wire T_210;
+ wire T_212;
+ wire T_214;
+ wire T_216;
+ wire T_218;
+ wire T_220;
+ wire T_222;
+ wire T_224;
+ wire T_226;
+ wire T_228;
+ wire T_230;
+ wire T_232;
+ wire T_234;
+ wire T_236;
+ wire T_238;
+ wire T_240;
+ wire T_242;
+ wire T_244;
+ wire T_246;
+ wire T_248;
+ wire T_250;
+ wire T_252;
+ wire T_254;
+ wire T_256;
+ wire T_258;
+ wire T_260;
+ wire T_262;
+ wire T_264;
+ wire T_266;
+ wire T_268;
+ wire T_270;
+ wire T_272;
+ wire T_274;
+ wire T_276;
+ wire T_278;
+ wire T_280;
+ wire T_282;
+ wire T_284;
+ wire T_286;
+ wire T_288;
+ wire T_290;
+ wire T_292;
+ wire T_294;
+ wire T_296;
+ wire T_298;
+ wire T_300;
+ wire T_302;
+ wire T_304;
+ wire T_306;
+ wire T_308;
+ wire T_310;
+ wire T_312;
+ wire T_314;
+ wire T_316;
+ wire T_318;
+ wire T_320;
+ wire T_321;
+ wire [1:0] T_322;
+ wire [1:0] T_323;
+ wire [2:0] T_324;
+ wire [2:0] T_325;
+ wire [2:0] T_326;
+ wire [2:0] T_327;
+ wire [3:0] T_328;
+ wire [3:0] T_329;
+ wire [3:0] T_330;
+ wire [3:0] T_331;
+ wire [3:0] T_332;
+ wire [3:0] T_333;
+ wire [3:0] T_334;
+ wire [3:0] T_335;
+ wire [4:0] T_336;
+ wire [4:0] T_337;
+ wire [4:0] T_338;
+ wire [4:0] T_339;
+ wire [4:0] T_340;
+ wire [4:0] T_341;
+ wire [4:0] T_342;
+ wire [4:0] T_343;
+ wire [4:0] T_344;
+ wire [4:0] T_345;
+ wire [4:0] T_346;
+ wire [4:0] T_347;
+ wire [4:0] T_348;
+ wire [4:0] T_349;
+ wire [4:0] T_350;
+ wire [4:0] T_351;
+ wire [5:0] T_352;
+ wire [5:0] T_353;
+ wire [5:0] T_354;
+ wire [5:0] T_355;
+ wire [5:0] T_356;
+ wire [5:0] T_357;
+ wire [5:0] T_358;
+ wire [5:0] T_359;
+ wire [5:0] T_360;
+ wire [5:0] T_361;
+ wire [5:0] T_362;
+ wire [5:0] T_363;
+ wire [5:0] T_364;
+ wire [5:0] T_365;
+ wire [5:0] T_366;
+ wire [5:0] T_367;
+ wire [5:0] T_368;
+ wire [5:0] T_369;
+ wire [5:0] T_370;
+ wire [5:0] T_371;
+ wire [5:0] T_372;
+ wire [5:0] T_373;
+ wire [5:0] T_374;
+ wire [5:0] T_375;
+ wire [5:0] T_376;
+ wire [5:0] T_377;
+ wire [5:0] T_378;
+ wire [5:0] T_379;
+ wire [5:0] T_380;
+ wire [5:0] T_381;
+ wire [5:0] T_382;
+ wire [5:0] T_383;
+ wire [6:0] T_384;
+ wire [6:0] T_385;
+ wire [6:0] T_386;
+ wire [6:0] T_387;
+ wire [6:0] T_388;
+ wire [6:0] T_389;
+ wire [6:0] T_390;
+ wire [6:0] T_391;
+ wire [6:0] T_392;
+ wire [6:0] T_393;
+ wire [6:0] T_394;
+ wire [6:0] T_395;
+ wire [6:0] T_396;
+ wire [6:0] T_397;
+ wire [6:0] T_398;
+ wire [6:0] T_399;
+ wire [6:0] T_400;
+ wire [6:0] T_401;
+ wire [6:0] T_402;
+ wire [6:0] T_403;
+ wire [6:0] T_404;
+ wire [6:0] T_405;
+ wire [6:0] T_406;
+ wire [6:0] T_407;
+ wire [6:0] T_408;
+ wire [6:0] T_409;
+ wire [6:0] T_410;
+ wire [6:0] T_411;
+ wire [6:0] T_412;
+ wire [6:0] T_413;
+ wire [6:0] T_414;
+ wire [6:0] T_415;
+ wire [6:0] T_416;
+ wire [6:0] T_417;
+ wire [6:0] T_418;
+ wire [6:0] T_419;
+ wire [6:0] T_420;
+ wire [6:0] T_421;
+ wire [6:0] T_422;
+ wire [6:0] T_423;
+ wire [6:0] T_424;
+ wire [6:0] T_425;
+ wire [6:0] T_426;
+ wire [6:0] T_427;
+ wire [8:0] T_428;
+ wire [7:0] estNormPos_dist;
+ wire [31:0] T_430;
+ wire T_432;
+ wire [43:0] T_433;
+ wire T_435;
+ wire [1:0] firstReduceSigSum;
+ wire [161:0] notSigSum;
+ wire [31:0] T_438;
+ wire T_440;
+ wire [43:0] T_441;
+ wire T_443;
+ wire [1:0] firstReduceNotSigSum;
+ wire T_445;
+ wire [8:0] T_447;
+ wire [7:0] T_448;
+ wire [5:0] T_449;
+ wire [7:0] CDom_estNormDist;
+ wire T_451;
+ wire T_452;
+ wire T_453;
+ wire T_454;
+ wire T_455;
+ wire [85:0] T_456;
+ wire T_458;
+ wire [86:0] T_459;
+ wire [86:0] T_460;
+ wire [86:0] T_461;
+ wire [86:0] T_462;
+ wire T_463;
+ wire T_464;
+ wire T_465;
+ wire T_466;
+ wire [85:0] T_467;
+ wire T_468;
+ wire [86:0] T_469;
+ wire [86:0] T_470;
+ wire [86:0] T_471;
+ wire [86:0] T_472;
+ wire [86:0] T_473;
+ wire [86:0] T_474;
+ wire T_475;
+ wire T_476;
+ wire T_477;
+ wire T_478;
+ wire [85:0] T_479;
+ wire T_481;
+ wire [86:0] T_482;
+ wire [86:0] T_483;
+ wire [86:0] T_484;
+ wire [86:0] T_485;
+ wire [86:0] T_486;
+ wire [86:0] T_487;
+ wire T_488;
+ wire T_489;
+ wire T_490;
+ wire [85:0] T_491;
+ wire T_492;
+ wire [86:0] T_493;
+ wire [86:0] T_494;
+ wire [86:0] T_495;
+ wire [86:0] T_496;
+ wire [86:0] T_497;
+ wire [86:0] T_498;
+ wire [86:0] CDom_firstNormAbsSigSum;
+ wire [64:0] T_500;
+ wire T_501;
+ wire T_502;
+ wire T_503;
+ wire T_504;
+ wire [65:0] T_505;
+ wire [96:0] T_506;
+ wire T_507;
+ wire T_508;
+ wire [86:0] T_510;
+ wire [85:0] T_511;
+ wire [86:0] T_512;
+ wire [86:0] T_513;
+ wire [85:0] T_514;
+ wire [10:0] T_515;
+ wire T_517;
+ wire [10:0] T_518;
+ wire T_520;
+ wire T_521;
+ wire [86:0] T_522;
+ wire T_523;
+ wire T_524;
+ wire [64:0] T_525;
+ wire [22:0] T_527;
+ wire [21:0] T_528;
+ wire [86:0] T_529;
+ wire [86:0] T_530;
+ wire T_531;
+ wire [32:0] T_532;
+ wire [54:0] T_534;
+ wire [53:0] T_535;
+ wire [86:0] T_536;
+ wire [86:0] T_537;
+ wire [86:0] notCDom_pos_firstNormAbsSigSum;
+ wire [63:0] T_539;
+ wire T_540;
+ wire [64:0] T_541;
+ wire [96:0] T_542;
+ wire T_543;
+ wire [1:0] T_544;
+ wire [128:0] T_546;
+ wire [128:0] T_547;
+ wire [86:0] T_548;
+ wire [10:0] T_549;
+ wire T_551;
+ wire [87:0] T_552;
+ wire T_553;
+ wire T_554;
+ wire [65:0] T_555;
+ wire [96:0] T_557;
+ wire [96:0] T_558;
+ wire T_559;
+ wire [33:0] T_560;
+ wire [96:0] T_562;
+ wire [128:0] T_563;
+ wire [128:0] notCDom_neg_cFirstNormAbsSigSum;
+ wire notCDom_signSigSum;
+ wire T_566;
+ wire T_567;
+ wire doNegSignSum;
+ wire [7:0] T_569;
+ wire [7:0] estNormDist;
+ wire [128:0] T_571;
+ wire [86:0] T_572;
+ wire [128:0] cFirstNormAbsSigSum;
+ wire T_574;
+ wire T_575;
+ wire T_576;
+ wire doIncrSig;
+ wire [4:0] estNormDist_5;
+ wire [4:0] normTo2ShiftDist;
+ wire [32:0] GEN_0;
+ wire [32:0] T_581;
+ wire [30:0] T_582;
+ wire [15:0] T_583;
+ wire [15:0] T_586;
+ wire [15:0] T_587;
+ wire [7:0] T_588;
+ wire [15:0] T_589;
+ wire [7:0] T_590;
+ wire [15:0] T_591;
+ wire [15:0] T_592;
+ wire [15:0] T_593;
+ wire [15:0] T_594;
+ wire [11:0] T_595;
+ wire [15:0] T_596;
+ wire [15:0] T_597;
+ wire [11:0] T_598;
+ wire [15:0] T_599;
+ wire [11:0] T_600;
+ wire [15:0] T_601;
+ wire [15:0] T_602;
+ wire [15:0] T_603;
+ wire [15:0] T_604;
+ wire [13:0] T_605;
+ wire [15:0] T_606;
+ wire [15:0] T_607;
+ wire [13:0] T_608;
+ wire [15:0] T_609;
+ wire [13:0] T_610;
+ wire [15:0] T_611;
+ wire [15:0] T_612;
+ wire [15:0] T_613;
+ wire [15:0] T_614;
+ wire [14:0] T_615;
+ wire [15:0] T_616;
+ wire [15:0] T_617;
+ wire [14:0] T_618;
+ wire [15:0] T_619;
+ wire [14:0] T_620;
+ wire [15:0] T_621;
+ wire [15:0] T_622;
+ wire [15:0] T_623;
+ wire [15:0] T_624;
+ wire [14:0] T_625;
+ wire [7:0] T_626;
+ wire [7:0] T_629;
+ wire [7:0] T_630;
+ wire [3:0] T_631;
+ wire [7:0] T_632;
+ wire [3:0] T_633;
+ wire [7:0] T_634;
+ wire [7:0] T_635;
+ wire [7:0] T_636;
+ wire [7:0] T_637;
+ wire [5:0] T_638;
+ wire [7:0] T_639;
+ wire [7:0] T_640;
+ wire [5:0] T_641;
+ wire [7:0] T_642;
+ wire [5:0] T_643;
+ wire [7:0] T_644;
+ wire [7:0] T_645;
+ wire [7:0] T_646;
+ wire [7:0] T_647;
+ wire [6:0] T_648;
+ wire [7:0] T_649;
+ wire [7:0] T_650;
+ wire [6:0] T_651;
+ wire [7:0] T_652;
+ wire [6:0] T_653;
+ wire [7:0] T_654;
+ wire [7:0] T_655;
+ wire [7:0] T_656;
+ wire [7:0] T_657;
+ wire [6:0] T_658;
+ wire [3:0] T_659;
+ wire [1:0] T_660;
+ wire T_661;
+ wire T_662;
+ wire [1:0] T_663;
+ wire [1:0] T_664;
+ wire T_665;
+ wire T_666;
+ wire [1:0] T_667;
+ wire [3:0] T_668;
+ wire [2:0] T_669;
+ wire [1:0] T_670;
+ wire T_671;
+ wire T_672;
+ wire [1:0] T_673;
+ wire T_674;
+ wire [2:0] T_675;
+ wire [6:0] T_676;
+ wire [14:0] T_677;
+ wire [30:0] T_678;
+ wire [31:0] absSigSumExtraMask;
+ wire [86:0] T_681;
+ wire [86:0] T_682;
+ wire [31:0] T_683;
+ wire [31:0] T_684;
+ wire [31:0] T_685;
+ wire T_687;
+ wire [31:0] T_688;
+ wire [31:0] T_689;
+ wire T_691;
+ wire T_692;
+ wire [87:0] T_693;
+ wire [56:0] sigX3;
+ wire [1:0] T_695;
+ wire sigX3Shift1;
+ wire [14:0] T_698;
+ wire [13:0] sExpX3;
+ wire [2:0] T_700;
+ wire isZeroY;
+ wire T_703;
+ wire signY;
+ wire [12:0] sExpX3_13;
+ wire T_706;
+ wire [56:0] T_708;
+ wire [55:0] T_709;
+ wire [12:0] T_710;
+ wire [8192:0] GEN_1;
+ wire [8192:0] T_712;
+ wire [53:0] T_713;
+ wire [31:0] T_714;
+ wire [31:0] T_717;
+ wire [31:0] T_718;
+ wire [15:0] T_719;
+ wire [31:0] T_720;
+ wire [15:0] T_721;
+ wire [31:0] T_722;
+ wire [31:0] T_723;
+ wire [31:0] T_724;
+ wire [31:0] T_725;
+ wire [23:0] T_726;
+ wire [31:0] T_727;
+ wire [31:0] T_728;
+ wire [23:0] T_729;
+ wire [31:0] T_730;
+ wire [23:0] T_731;
+ wire [31:0] T_732;
+ wire [31:0] T_733;
+ wire [31:0] T_734;
+ wire [31:0] T_735;
+ wire [27:0] T_736;
+ wire [31:0] T_737;
+ wire [31:0] T_738;
+ wire [27:0] T_739;
+ wire [31:0] T_740;
+ wire [27:0] T_741;
+ wire [31:0] T_742;
+ wire [31:0] T_743;
+ wire [31:0] T_744;
+ wire [31:0] T_745;
+ wire [29:0] T_746;
+ wire [31:0] T_747;
+ wire [31:0] T_748;
+ wire [29:0] T_749;
+ wire [31:0] T_750;
+ wire [29:0] T_751;
+ wire [31:0] T_752;
+ wire [31:0] T_753;
+ wire [31:0] T_754;
+ wire [31:0] T_755;
+ wire [30:0] T_756;
+ wire [31:0] T_757;
+ wire [31:0] T_758;
+ wire [30:0] T_759;
+ wire [31:0] T_760;
+ wire [30:0] T_761;
+ wire [31:0] T_762;
+ wire [31:0] T_763;
+ wire [31:0] T_764;
+ wire [31:0] T_765;
+ wire [21:0] T_766;
+ wire [15:0] T_767;
+ wire [15:0] T_770;
+ wire [15:0] T_771;
+ wire [7:0] T_772;
+ wire [15:0] T_773;
+ wire [7:0] T_774;
+ wire [15:0] T_775;
+ wire [15:0] T_776;
+ wire [15:0] T_777;
+ wire [15:0] T_778;
+ wire [11:0] T_779;
+ wire [15:0] T_780;
+ wire [15:0] T_781;
+ wire [11:0] T_782;
+ wire [15:0] T_783;
+ wire [11:0] T_784;
+ wire [15:0] T_785;
+ wire [15:0] T_786;
+ wire [15:0] T_787;
+ wire [15:0] T_788;
+ wire [13:0] T_789;
+ wire [15:0] T_790;
+ wire [15:0] T_791;
+ wire [13:0] T_792;
+ wire [15:0] T_793;
+ wire [13:0] T_794;
+ wire [15:0] T_795;
+ wire [15:0] T_796;
+ wire [15:0] T_797;
+ wire [15:0] T_798;
+ wire [14:0] T_799;
+ wire [15:0] T_800;
+ wire [15:0] T_801;
+ wire [14:0] T_802;
+ wire [15:0] T_803;
+ wire [14:0] T_804;
+ wire [15:0] T_805;
+ wire [15:0] T_806;
+ wire [15:0] T_807;
+ wire [15:0] T_808;
+ wire [5:0] T_809;
+ wire [3:0] T_810;
+ wire [1:0] T_811;
+ wire T_812;
+ wire T_813;
+ wire [1:0] T_814;
+ wire [1:0] T_815;
+ wire T_816;
+ wire T_817;
+ wire [1:0] T_818;
+ wire [3:0] T_819;
+ wire [1:0] T_820;
+ wire T_821;
+ wire T_822;
+ wire [1:0] T_823;
+ wire [5:0] T_824;
+ wire [21:0] T_825;
+ wire [53:0] T_826;
+ wire T_827;
+ wire [53:0] T_828;
+ wire [55:0] T_830;
+ wire [55:0] roundMask;
+ wire [54:0] T_832;
+ wire [54:0] T_833;
+ wire [55:0] roundPosMask;
+ wire [56:0] T_835;
+ wire roundPosBit;
+ wire [54:0] T_838;
+ wire [56:0] T_839;
+ wire anyRoundExtra;
+ wire [56:0] T_842;
+ wire [54:0] T_843;
+ wire [56:0] T_844;
+ wire allRoundExtra;
+ wire anyRound;
+ wire allRound;
+ wire roundDirectUp;
+ wire T_850;
+ wire T_851;
+ wire T_852;
+ wire T_853;
+ wire T_854;
+ wire T_855;
+ wire T_856;
+ wire T_857;
+ wire T_858;
+ wire T_859;
+ wire T_860;
+ wire T_861;
+ wire T_862;
+ wire T_863;
+ wire T_865;
+ wire roundUp;
+ wire T_867;
+ wire T_868;
+ wire T_869;
+ wire T_870;
+ wire T_871;
+ wire T_872;
+ wire roundEven;
+ wire T_874;
+ wire roundInexact;
+ wire [56:0] T_876;
+ wire [54:0] T_877;
+ wire [55:0] T_879;
+ wire [54:0] T_880;
+ wire [54:0] roundUp_sigY3;
+ wire T_882;
+ wire T_883;
+ wire T_884;
+ wire T_885;
+ wire [55:0] T_886;
+ wire [56:0] T_887;
+ wire [54:0] T_888;
+ wire [54:0] T_890;
+ wire T_891;
+ wire [54:0] T_893;
+ wire [54:0] T_894;
+ wire [54:0] T_895;
+ wire [54:0] T_896;
+ wire [54:0] T_897;
+ wire [54:0] T_899;
+ wire [54:0] sigY3;
+ wire T_901;
+ wire [14:0] T_903;
+ wire [13:0] T_904;
+ wire [13:0] T_906;
+ wire T_907;
+ wire [13:0] T_909;
+ wire [13:0] T_910;
+ wire [1:0] T_911;
+ wire T_913;
+ wire [14:0] T_915;
+ wire [13:0] T_916;
+ wire [13:0] T_918;
+ wire [13:0] sExpY;
+ wire [11:0] expY;
+ wire [51:0] T_921;
+ wire [51:0] T_922;
+ wire [51:0] fractY;
+ wire [2:0] T_924;
+ wire overflowY;
+ wire T_927;
+ wire T_928;
+ wire [11:0] T_929;
+ wire T_931;
+ wire T_932;
+ wire totalUnderflowY;
+ wire T_934;
+ wire [10:0] T_937;
+ wire T_938;
+ wire T_939;
+ wire underflowY;
+ wire T_941;
+ wire T_942;
+ wire T_943;
+ wire roundMagUp;
+ wire overflowY_roundMagUp;
+ wire mulSpecial;
+ wire addSpecial;
+ wire notSpecial_addZeros;
+ wire T_949;
+ wire T_950;
+ wire commonCase;
+ wire T_952;
+ wire T_953;
+ wire T_954;
+ wire T_955;
+ wire T_956;
+ wire T_957;
+ wire T_958;
+ wire T_959;
+ wire T_960;
+ wire T_961;
+ wire notSigNaN_invalid;
+ wire T_963;
+ wire T_964;
+ wire invalid;
+ wire overflow;
+ wire underflow;
+ wire T_968;
+ wire inexact;
+ wire T_970;
+ wire notSpecial_isZeroOut;
+ wire T_972;
+ wire pegMinFiniteMagOut;
+ wire T_974;
+ wire pegMaxFiniteMagOut;
+ wire T_976;
+ wire T_977;
+ wire T_978;
+ wire notNaN_isInfOut;
+ wire T_980;
+ wire T_981;
+ wire isNaNOut;
+ wire T_984;
+ wire T_985;
+ wire T_987;
+ wire T_988;
+ wire T_989;
+ wire T_990;
+ wire T_992;
+ wire T_993;
+ wire T_994;
+ wire T_995;
+ wire T_997;
+ wire T_998;
+ wire T_999;
+ wire T_1000;
+ wire uncommonCaseSignOut;
+ wire T_1003;
+ wire T_1004;
+ wire T_1005;
+ wire signOut;
+ wire [11:0] T_1009;
+ wire [11:0] T_1010;
+ wire [11:0] T_1011;
+ wire [11:0] T_1013;
+ wire [11:0] T_1015;
+ wire [11:0] T_1016;
+ wire [11:0] T_1017;
+ wire [11:0] T_1020;
+ wire [11:0] T_1021;
+ wire [11:0] T_1022;
+ wire [11:0] T_1025;
+ wire [11:0] T_1026;
+ wire [11:0] T_1027;
+ wire [11:0] T_1030;
+ wire [11:0] T_1031;
+ wire [11:0] T_1034;
+ wire [11:0] T_1035;
+ wire [11:0] T_1038;
+ wire [11:0] T_1039;
+ wire [11:0] T_1042;
+ wire [11:0] expOut;
+ wire T_1044;
+ wire T_1045;
+ wire [51:0] T_1047;
+ wire [51:0] T_1048;
+ wire [51:0] T_1049;
+ wire [52:0] T_1051;
+ wire [51:0] T_1052;
+ wire [51:0] fractOut;
+ wire [63:0] T_1054;
+ wire [64:0] T_1055;
+ wire [1:0] T_1057;
+ wire [1:0] T_1058;
+ wire [2:0] T_1059;
+ wire [4:0] T_1060;
+ assign io_out = T_1055;
+ assign io_exceptionFlags = T_1060;
+ assign isZeroA = io_fromPreMul_highExpA == 1'h0;
+ assign T_44 = io_fromPreMul_highExpA[2:1];
+ assign isSpecialA = T_44 == 2'h3;
+ assign T_47 = io_fromPreMul_highExpA[0];
+ assign T_49 = T_47 == 1'h0;
+ assign isInfA = isSpecialA & T_49;
+ assign T_51 = io_fromPreMul_highExpA[0];
+ assign isNaNA = isSpecialA & T_51;
+ assign T_54 = io_fromPreMul_isNaN_isQuietNaNA == 1'h0;
+ assign isSigNaNA = isNaNA & T_54;
+ assign isZeroB = io_fromPreMul_highExpB == 1'h0;
+ assign T_58 = io_fromPreMul_highExpB[2:1];
+ assign isSpecialB = T_58 == 2'h3;
+ assign T_61 = io_fromPreMul_highExpB[0];
+ assign T_63 = T_61 == 1'h0;
+ assign isInfB = isSpecialB & T_63;
+ assign T_65 = io_fromPreMul_highExpB[0];
+ assign isNaNB = isSpecialB & T_65;
+ assign T_68 = io_fromPreMul_isNaN_isQuietNaNB == 1'h0;
+ assign isSigNaNB = isNaNB & T_68;
+ assign isZeroC = io_fromPreMul_highExpC == 1'h0;
+ assign T_72 = io_fromPreMul_highExpC[2:1];
+ assign isSpecialC = T_72 == 2'h3;
+ assign T_75 = io_fromPreMul_highExpC[0];
+ assign T_77 = T_75 == 1'h0;
+ assign isInfC = isSpecialC & T_77;
+ assign T_79 = io_fromPreMul_highExpC[0];
+ assign isNaNC = isSpecialC & T_79;
+ assign T_82 = io_fromPreMul_isNaN_isQuietNaNC == 1'h0;
+ assign isSigNaNC = isNaNC & T_82;
+ assign roundingMode_nearest_even = io_fromPreMul_roundingMode == 2'h0;
+ assign roundingMode_minMag = io_fromPreMul_roundingMode == 2'h1;
+ assign roundingMode_min = io_fromPreMul_roundingMode == 2'h2;
+ assign roundingMode_max = io_fromPreMul_roundingMode == 2'h3;
+ assign signZeroNotEqOpSigns = roundingMode_min ? 1'h1 : 1'h0;
+ assign doSubMags = io_fromPreMul_signProd ^ io_fromPreMul_opSignC;
+ assign T_92 = io_mulAddResult[106];
+ assign T_94 = io_fromPreMul_highAlignedNegSigC + 1'h1;
+ assign T_95 = T_94[54:0];
+ assign T_96 = T_92 ? T_95 : io_fromPreMul_highAlignedNegSigC;
+ assign T_97 = io_mulAddResult[105:0];
+ assign T_98 = {T_97,io_fromPreMul_bit0AlignedNegSigC};
+ assign sigSum = {T_96,T_98};
+ assign T_101 = sigSum[108:1];
+ assign T_102 = 108'h0 ^ T_101;
+ assign T_103 = 108'h0 | T_101;
+ assign T_104 = T_103 << 1;
+ assign T_105 = T_102 ^ T_104;
+ assign T_107 = T_105[107:0];
+ assign T_108 = T_107[107];
+ assign T_110 = T_107[106];
+ assign T_112 = T_107[105];
+ assign T_114 = T_107[104];
+ assign T_116 = T_107[103];
+ assign T_118 = T_107[102];
+ assign T_120 = T_107[101];
+ assign T_122 = T_107[100];
+ assign T_124 = T_107[99];
+ assign T_126 = T_107[98];
+ assign T_128 = T_107[97];
+ assign T_130 = T_107[96];
+ assign T_132 = T_107[95];
+ assign T_134 = T_107[94];
+ assign T_136 = T_107[93];
+ assign T_138 = T_107[92];
+ assign T_140 = T_107[91];
+ assign T_142 = T_107[90];
+ assign T_144 = T_107[89];
+ assign T_146 = T_107[88];
+ assign T_148 = T_107[87];
+ assign T_150 = T_107[86];
+ assign T_152 = T_107[85];
+ assign T_154 = T_107[84];
+ assign T_156 = T_107[83];
+ assign T_158 = T_107[82];
+ assign T_160 = T_107[81];
+ assign T_162 = T_107[80];
+ assign T_164 = T_107[79];
+ assign T_166 = T_107[78];
+ assign T_168 = T_107[77];
+ assign T_170 = T_107[76];
+ assign T_172 = T_107[75];
+ assign T_174 = T_107[74];
+ assign T_176 = T_107[73];
+ assign T_178 = T_107[72];
+ assign T_180 = T_107[71];
+ assign T_182 = T_107[70];
+ assign T_184 = T_107[69];
+ assign T_186 = T_107[68];
+ assign T_188 = T_107[67];
+ assign T_190 = T_107[66];
+ assign T_192 = T_107[65];
+ assign T_194 = T_107[64];
+ assign T_196 = T_107[63];
+ assign T_198 = T_107[62];
+ assign T_200 = T_107[61];
+ assign T_202 = T_107[60];
+ assign T_204 = T_107[59];
+ assign T_206 = T_107[58];
+ assign T_208 = T_107[57];
+ assign T_210 = T_107[56];
+ assign T_212 = T_107[55];
+ assign T_214 = T_107[54];
+ assign T_216 = T_107[53];
+ assign T_218 = T_107[52];
+ assign T_220 = T_107[51];
+ assign T_222 = T_107[50];
+ assign T_224 = T_107[49];
+ assign T_226 = T_107[48];
+ assign T_228 = T_107[47];
+ assign T_230 = T_107[46];
+ assign T_232 = T_107[45];
+ assign T_234 = T_107[44];
+ assign T_236 = T_107[43];
+ assign T_238 = T_107[42];
+ assign T_240 = T_107[41];
+ assign T_242 = T_107[40];
+ assign T_244 = T_107[39];
+ assign T_246 = T_107[38];
+ assign T_248 = T_107[37];
+ assign T_250 = T_107[36];
+ assign T_252 = T_107[35];
+ assign T_254 = T_107[34];
+ assign T_256 = T_107[33];
+ assign T_258 = T_107[32];
+ assign T_260 = T_107[31];
+ assign T_262 = T_107[30];
+ assign T_264 = T_107[29];
+ assign T_266 = T_107[28];
+ assign T_268 = T_107[27];
+ assign T_270 = T_107[26];
+ assign T_272 = T_107[25];
+ assign T_274 = T_107[24];
+ assign T_276 = T_107[23];
+ assign T_278 = T_107[22];
+ assign T_280 = T_107[21];
+ assign T_282 = T_107[20];
+ assign T_284 = T_107[19];
+ assign T_286 = T_107[18];
+ assign T_288 = T_107[17];
+ assign T_290 = T_107[16];
+ assign T_292 = T_107[15];
+ assign T_294 = T_107[14];
+ assign T_296 = T_107[13];
+ assign T_298 = T_107[12];
+ assign T_300 = T_107[11];
+ assign T_302 = T_107[10];
+ assign T_304 = T_107[9];
+ assign T_306 = T_107[8];
+ assign T_308 = T_107[7];
+ assign T_310 = T_107[6];
+ assign T_312 = T_107[5];
+ assign T_314 = T_107[4];
+ assign T_316 = T_107[3];
+ assign T_318 = T_107[2];
+ assign T_320 = T_107[1];
+ assign T_321 = T_320 << 0;
+ assign T_322 = T_318 ? 2'h2 : T_321;
+ assign T_323 = T_316 ? 2'h3 : T_322;
+ assign T_324 = T_314 ? 3'h4 : T_323;
+ assign T_325 = T_312 ? 3'h5 : T_324;
+ assign T_326 = T_310 ? 3'h6 : T_325;
+ assign T_327 = T_308 ? 3'h7 : T_326;
+ assign T_328 = T_306 ? 4'h8 : T_327;
+ assign T_329 = T_304 ? 4'h9 : T_328;
+ assign T_330 = T_302 ? 4'ha : T_329;
+ assign T_331 = T_300 ? 4'hb : T_330;
+ assign T_332 = T_298 ? 4'hc : T_331;
+ assign T_333 = T_296 ? 4'hd : T_332;
+ assign T_334 = T_294 ? 4'he : T_333;
+ assign T_335 = T_292 ? 4'hf : T_334;
+ assign T_336 = T_290 ? 5'h10 : T_335;
+ assign T_337 = T_288 ? 5'h11 : T_336;
+ assign T_338 = T_286 ? 5'h12 : T_337;
+ assign T_339 = T_284 ? 5'h13 : T_338;
+ assign T_340 = T_282 ? 5'h14 : T_339;
+ assign T_341 = T_280 ? 5'h15 : T_340;
+ assign T_342 = T_278 ? 5'h16 : T_341;
+ assign T_343 = T_276 ? 5'h17 : T_342;
+ assign T_344 = T_274 ? 5'h18 : T_343;
+ assign T_345 = T_272 ? 5'h19 : T_344;
+ assign T_346 = T_270 ? 5'h1a : T_345;
+ assign T_347 = T_268 ? 5'h1b : T_346;
+ assign T_348 = T_266 ? 5'h1c : T_347;
+ assign T_349 = T_264 ? 5'h1d : T_348;
+ assign T_350 = T_262 ? 5'h1e : T_349;
+ assign T_351 = T_260 ? 5'h1f : T_350;
+ assign T_352 = T_258 ? 6'h20 : T_351;
+ assign T_353 = T_256 ? 6'h21 : T_352;
+ assign T_354 = T_254 ? 6'h22 : T_353;
+ assign T_355 = T_252 ? 6'h23 : T_354;
+ assign T_356 = T_250 ? 6'h24 : T_355;
+ assign T_357 = T_248 ? 6'h25 : T_356;
+ assign T_358 = T_246 ? 6'h26 : T_357;
+ assign T_359 = T_244 ? 6'h27 : T_358;
+ assign T_360 = T_242 ? 6'h28 : T_359;
+ assign T_361 = T_240 ? 6'h29 : T_360;
+ assign T_362 = T_238 ? 6'h2a : T_361;
+ assign T_363 = T_236 ? 6'h2b : T_362;
+ assign T_364 = T_234 ? 6'h2c : T_363;
+ assign T_365 = T_232 ? 6'h2d : T_364;
+ assign T_366 = T_230 ? 6'h2e : T_365;
+ assign T_367 = T_228 ? 6'h2f : T_366;
+ assign T_368 = T_226 ? 6'h30 : T_367;
+ assign T_369 = T_224 ? 6'h31 : T_368;
+ assign T_370 = T_222 ? 6'h32 : T_369;
+ assign T_371 = T_220 ? 6'h33 : T_370;
+ assign T_372 = T_218 ? 6'h34 : T_371;
+ assign T_373 = T_216 ? 6'h35 : T_372;
+ assign T_374 = T_214 ? 6'h36 : T_373;
+ assign T_375 = T_212 ? 6'h37 : T_374;
+ assign T_376 = T_210 ? 6'h38 : T_375;
+ assign T_377 = T_208 ? 6'h39 : T_376;
+ assign T_378 = T_206 ? 6'h3a : T_377;
+ assign T_379 = T_204 ? 6'h3b : T_378;
+ assign T_380 = T_202 ? 6'h3c : T_379;
+ assign T_381 = T_200 ? 6'h3d : T_380;
+ assign T_382 = T_198 ? 6'h3e : T_381;
+ assign T_383 = T_196 ? 6'h3f : T_382;
+ assign T_384 = T_194 ? 7'h40 : T_383;
+ assign T_385 = T_192 ? 7'h41 : T_384;
+ assign T_386 = T_190 ? 7'h42 : T_385;
+ assign T_387 = T_188 ? 7'h43 : T_386;
+ assign T_388 = T_186 ? 7'h44 : T_387;
+ assign T_389 = T_184 ? 7'h45 : T_388;
+ assign T_390 = T_182 ? 7'h46 : T_389;
+ assign T_391 = T_180 ? 7'h47 : T_390;
+ assign T_392 = T_178 ? 7'h48 : T_391;
+ assign T_393 = T_176 ? 7'h49 : T_392;
+ assign T_394 = T_174 ? 7'h4a : T_393;
+ assign T_395 = T_172 ? 7'h4b : T_394;
+ assign T_396 = T_170 ? 7'h4c : T_395;
+ assign T_397 = T_168 ? 7'h4d : T_396;
+ assign T_398 = T_166 ? 7'h4e : T_397;
+ assign T_399 = T_164 ? 7'h4f : T_398;
+ assign T_400 = T_162 ? 7'h50 : T_399;
+ assign T_401 = T_160 ? 7'h51 : T_400;
+ assign T_402 = T_158 ? 7'h52 : T_401;
+ assign T_403 = T_156 ? 7'h53 : T_402;
+ assign T_404 = T_154 ? 7'h54 : T_403;
+ assign T_405 = T_152 ? 7'h55 : T_404;
+ assign T_406 = T_150 ? 7'h56 : T_405;
+ assign T_407 = T_148 ? 7'h57 : T_406;
+ assign T_408 = T_146 ? 7'h58 : T_407;
+ assign T_409 = T_144 ? 7'h59 : T_408;
+ assign T_410 = T_142 ? 7'h5a : T_409;
+ assign T_411 = T_140 ? 7'h5b : T_410;
+ assign T_412 = T_138 ? 7'h5c : T_411;
+ assign T_413 = T_136 ? 7'h5d : T_412;
+ assign T_414 = T_134 ? 7'h5e : T_413;
+ assign T_415 = T_132 ? 7'h5f : T_414;
+ assign T_416 = T_130 ? 7'h60 : T_415;
+ assign T_417 = T_128 ? 7'h61 : T_416;
+ assign T_418 = T_126 ? 7'h62 : T_417;
+ assign T_419 = T_124 ? 7'h63 : T_418;
+ assign T_420 = T_122 ? 7'h64 : T_419;
+ assign T_421 = T_120 ? 7'h65 : T_420;
+ assign T_422 = T_118 ? 7'h66 : T_421;
+ assign T_423 = T_116 ? 7'h67 : T_422;
+ assign T_424 = T_114 ? 7'h68 : T_423;
+ assign T_425 = T_112 ? 7'h69 : T_424;
+ assign T_426 = T_110 ? 7'h6a : T_425;
+ assign T_427 = T_108 ? 7'h6b : T_426;
+ assign T_428 = 8'ha0 - T_427;
+ assign estNormPos_dist = T_428[7:0];
+ assign T_430 = sigSum[75:44];
+ assign T_432 = T_430 != 1'h0;
+ assign T_433 = sigSum[43:0];
+ assign T_435 = T_433 != 1'h0;
+ assign firstReduceSigSum = {T_432,T_435};
+ assign notSigSum = ~ sigSum;
+ assign T_438 = notSigSum[75:44];
+ assign T_440 = T_438 != 1'h0;
+ assign T_441 = notSigSum[43:0];
+ assign T_443 = T_441 != 1'h0;
+ assign firstReduceNotSigSum = {T_440,T_443};
+ assign T_445 = io_fromPreMul_CAlignDist_0 | doSubMags;
+ assign T_447 = io_fromPreMul_CAlignDist - 1'h1;
+ assign T_448 = T_447[7:0];
+ assign T_449 = T_448[5:0];
+ assign CDom_estNormDist = T_445 ? io_fromPreMul_CAlignDist : T_449;
+ assign T_451 = ~ doSubMags;
+ assign T_452 = CDom_estNormDist[5];
+ assign T_453 = ~ T_452;
+ assign T_454 = T_451 & T_453;
+ assign T_455 = $signed(T_454);
+ assign T_456 = sigSum[161:76];
+ assign T_458 = firstReduceSigSum != 1'h0;
+ assign T_459 = {T_456,T_458};
+ assign T_460 = $signed(T_459);
+ assign T_461 = $signed(T_455) & $signed(T_460);
+ assign T_462 = $signed(T_461);
+ assign T_463 = ~ doSubMags;
+ assign T_464 = CDom_estNormDist[5];
+ assign T_465 = T_463 & T_464;
+ assign T_466 = $signed(T_465);
+ assign T_467 = sigSum[129:44];
+ assign T_468 = firstReduceSigSum[0];
+ assign T_469 = {T_467,T_468};
+ assign T_470 = $signed(T_469);
+ assign T_471 = $signed(T_466) & $signed(T_470);
+ assign T_472 = $signed(T_471);
+ assign T_473 = $signed(T_462) | $signed(T_472);
+ assign T_474 = $signed(T_473);
+ assign T_475 = CDom_estNormDist[5];
+ assign T_476 = ~ T_475;
+ assign T_477 = doSubMags & T_476;
+ assign T_478 = $signed(T_477);
+ assign T_479 = notSigSum[161:76];
+ assign T_481 = firstReduceNotSigSum != 1'h0;
+ assign T_482 = {T_479,T_481};
+ assign T_483 = $signed(T_482);
+ assign T_484 = $signed(T_478) & $signed(T_483);
+ assign T_485 = $signed(T_484);
+ assign T_486 = $signed(T_474) | $signed(T_485);
+ assign T_487 = $signed(T_486);
+ assign T_488 = CDom_estNormDist[5];
+ assign T_489 = doSubMags & T_488;
+ assign T_490 = $signed(T_489);
+ assign T_491 = notSigSum[129:44];
+ assign T_492 = firstReduceNotSigSum[0];
+ assign T_493 = {T_491,T_492};
+ assign T_494 = $signed(T_493);
+ assign T_495 = $signed(T_490) & $signed(T_494);
+ assign T_496 = $signed(T_495);
+ assign T_497 = $signed(T_487) | $signed(T_496);
+ assign T_498 = $signed(T_497);
+ assign CDom_firstNormAbsSigSum = $unsigned(T_498);
+ assign T_500 = sigSum[108:44];
+ assign T_501 = firstReduceNotSigSum[0];
+ assign T_502 = ~ T_501;
+ assign T_503 = firstReduceSigSum[0];
+ assign T_504 = doSubMags ? T_502 : T_503;
+ assign T_505 = {T_500,T_504};
+ assign T_506 = sigSum[97:1];
+ assign T_507 = estNormPos_dist[4];
+ assign T_508 = sigSum[1];
+ assign T_510 = 86'h0 - doSubMags;
+ assign T_511 = T_510[85:0];
+ assign T_512 = {T_508,T_511};
+ assign T_513 = T_507 ? T_505 : T_512;
+ assign T_514 = sigSum[97:12];
+ assign T_515 = notSigSum[11:1];
+ assign T_517 = T_515 == 1'h0;
+ assign T_518 = sigSum[11:1];
+ assign T_520 = T_518 != 1'h0;
+ assign T_521 = doSubMags ? T_517 : T_520;
+ assign T_522 = {T_514,T_521};
+ assign T_523 = estNormPos_dist[6];
+ assign T_524 = estNormPos_dist[5];
+ assign T_525 = sigSum[65:1];
+ assign T_527 = 22'h0 - doSubMags;
+ assign T_528 = T_527[21:0];
+ assign T_529 = {T_525,T_528};
+ assign T_530 = T_524 ? T_529 : T_522;
+ assign T_531 = estNormPos_dist[5];
+ assign T_532 = sigSum[33:1];
+ assign T_534 = 54'h0 - doSubMags;
+ assign T_535 = T_534[53:0];
+ assign T_536 = {T_532,T_535};
+ assign T_537 = T_531 ? T_513 : T_536;
+ assign notCDom_pos_firstNormAbsSigSum = T_523 ? T_530 : T_537;
+ assign T_539 = notSigSum[107:44];
+ assign T_540 = firstReduceNotSigSum[0];
+ assign T_541 = {T_539,T_540};
+ assign T_542 = notSigSum[97:1];
+ assign T_543 = estNormPos_dist[4];
+ assign T_544 = notSigSum[2:1];
+ assign T_546 = T_544 << 7'h56;
+ assign T_547 = T_543 ? T_541 : T_546;
+ assign T_548 = notSigSum[98:12];
+ assign T_549 = notSigSum[11:1];
+ assign T_551 = T_549 != 1'h0;
+ assign T_552 = {T_548,T_551};
+ assign T_553 = estNormPos_dist[6];
+ assign T_554 = estNormPos_dist[5];
+ assign T_555 = notSigSum[66:1];
+ assign T_557 = T_555 << 5'h16;
+ assign T_558 = T_554 ? T_557 : T_552;
+ assign T_559 = estNormPos_dist[5];
+ assign T_560 = notSigSum[34:1];
+ assign T_562 = T_560 << 6'h36;
+ assign T_563 = T_559 ? T_547 : T_562;
+ assign notCDom_neg_cFirstNormAbsSigSum = T_553 ? T_558 : T_563;
+ assign notCDom_signSigSum = sigSum[109];
+ assign T_566 = ~ isZeroC;
+ assign T_567 = doSubMags & T_566;
+ assign doNegSignSum = io_fromPreMul_isCDominant ? T_567 : notCDom_signSigSum;
+ assign T_569 = notCDom_signSigSum ? estNormPos_dist : estNormPos_dist;
+ assign estNormDist = io_fromPreMul_isCDominant ? CDom_estNormDist : T_569;
+ assign T_571 = io_fromPreMul_isCDominant ? CDom_firstNormAbsSigSum : notCDom_neg_cFirstNormAbsSigSum;
+ assign T_572 = io_fromPreMul_isCDominant ? CDom_firstNormAbsSigSum : notCDom_pos_firstNormAbsSigSum;
+ assign cFirstNormAbsSigSum = notCDom_signSigSum ? T_571 : T_572;
+ assign T_574 = ~ io_fromPreMul_isCDominant;
+ assign T_575 = ~ notCDom_signSigSum;
+ assign T_576 = T_574 & T_575;
+ assign doIncrSig = T_576 & doSubMags;
+ assign estNormDist_5 = estNormDist[4:0];
+ assign normTo2ShiftDist = ~ estNormDist_5;
+ assign GEN_0 = $signed(33'h100000000);
+ assign T_581 = $signed(GEN_0) >>> normTo2ShiftDist;
+ assign T_582 = T_581[31:1];
+ assign T_583 = T_582[15:0];
+ assign T_586 = 8'hff << 8;
+ assign T_587 = 16'hffff ^ T_586;
+ assign T_588 = T_583[15:8];
+ assign T_589 = T_588 & T_587;
+ assign T_590 = T_583[7:0];
+ assign T_591 = T_590 << 8;
+ assign T_592 = ~ T_587;
+ assign T_593 = T_591 & T_592;
+ assign T_594 = T_589 | T_593;
+ assign T_595 = T_587[11:0];
+ assign T_596 = T_595 << 4;
+ assign T_597 = T_587 ^ T_596;
+ assign T_598 = T_594[15:4];
+ assign T_599 = T_598 & T_597;
+ assign T_600 = T_594[11:0];
+ assign T_601 = T_600 << 4;
+ assign T_602 = ~ T_597;
+ assign T_603 = T_601 & T_602;
+ assign T_604 = T_599 | T_603;
+ assign T_605 = T_597[13:0];
+ assign T_606 = T_605 << 2;
+ assign T_607 = T_597 ^ T_606;
+ assign T_608 = T_604[15:2];
+ assign T_609 = T_608 & T_607;
+ assign T_610 = T_604[13:0];
+ assign T_611 = T_610 << 2;
+ assign T_612 = ~ T_607;
+ assign T_613 = T_611 & T_612;
+ assign T_614 = T_609 | T_613;
+ assign T_615 = T_607[14:0];
+ assign T_616 = T_615 << 1;
+ assign T_617 = T_607 ^ T_616;
+ assign T_618 = T_614[15:1];
+ assign T_619 = T_618 & T_617;
+ assign T_620 = T_614[14:0];
+ assign T_621 = T_620 << 1;
+ assign T_622 = ~ T_617;
+ assign T_623 = T_621 & T_622;
+ assign T_624 = T_619 | T_623;
+ assign T_625 = T_582[30:16];
+ assign T_626 = T_625[7:0];
+ assign T_629 = 4'hf << 4;
+ assign T_630 = 8'hff ^ T_629;
+ assign T_631 = T_626[7:4];
+ assign T_632 = T_631 & T_630;
+ assign T_633 = T_626[3:0];
+ assign T_634 = T_633 << 4;
+ assign T_635 = ~ T_630;
+ assign T_636 = T_634 & T_635;
+ assign T_637 = T_632 | T_636;
+ assign T_638 = T_630[5:0];
+ assign T_639 = T_638 << 2;
+ assign T_640 = T_630 ^ T_639;
+ assign T_641 = T_637[7:2];
+ assign T_642 = T_641 & T_640;
+ assign T_643 = T_637[5:0];
+ assign T_644 = T_643 << 2;
+ assign T_645 = ~ T_640;
+ assign T_646 = T_644 & T_645;
+ assign T_647 = T_642 | T_646;
+ assign T_648 = T_640[6:0];
+ assign T_649 = T_648 << 1;
+ assign T_650 = T_640 ^ T_649;
+ assign T_651 = T_647[7:1];
+ assign T_652 = T_651 & T_650;
+ assign T_653 = T_647[6:0];
+ assign T_654 = T_653 << 1;
+ assign T_655 = ~ T_650;
+ assign T_656 = T_654 & T_655;
+ assign T_657 = T_652 | T_656;
+ assign T_658 = T_625[14:8];
+ assign T_659 = T_658[3:0];
+ assign T_660 = T_659[1:0];
+ assign T_661 = T_660[0];
+ assign T_662 = T_660[1];
+ assign T_663 = {T_661,T_662};
+ assign T_664 = T_659[3:2];
+ assign T_665 = T_664[0];
+ assign T_666 = T_664[1];
+ assign T_667 = {T_665,T_666};
+ assign T_668 = {T_663,T_667};
+ assign T_669 = T_658[6:4];
+ assign T_670 = T_669[1:0];
+ assign T_671 = T_670[0];
+ assign T_672 = T_670[1];
+ assign T_673 = {T_671,T_672};
+ assign T_674 = T_669[2];
+ assign T_675 = {T_673,T_674};
+ assign T_676 = {T_668,T_675};
+ assign T_677 = {T_657,T_676};
+ assign T_678 = {T_624,T_677};
+ assign absSigSumExtraMask = {T_678,1'h1};
+ assign T_681 = cFirstNormAbsSigSum[87:1];
+ assign T_682 = T_681 >> normTo2ShiftDist;
+ assign T_683 = cFirstNormAbsSigSum[31:0];
+ assign T_684 = ~ T_683;
+ assign T_685 = T_684 & absSigSumExtraMask;
+ assign T_687 = T_685 == 1'h0;
+ assign T_688 = cFirstNormAbsSigSum[31:0];
+ assign T_689 = T_688 & absSigSumExtraMask;
+ assign T_691 = T_689 != 1'h0;
+ assign T_692 = doIncrSig ? T_687 : T_691;
+ assign T_693 = {T_682,T_692};
+ assign sigX3 = T_693[56:0];
+ assign T_695 = sigX3[56:55];
+ assign sigX3Shift1 = T_695 == 1'h0;
+ assign T_698 = io_fromPreMul_sExpSum - estNormDist;
+ assign sExpX3 = T_698[13:0];
+ assign T_700 = sigX3[56:54];
+ assign isZeroY = T_700 == 1'h0;
+ assign T_703 = io_fromPreMul_signProd ^ doNegSignSum;
+ assign signY = isZeroY ? signZeroNotEqOpSigns : T_703;
+ assign sExpX3_13 = sExpX3[12:0];
+ assign T_706 = sExpX3[13];
+ assign T_708 = 56'h0 - T_706;
+ assign T_709 = T_708[55:0];
+ assign T_710 = ~ sExpX3_13;
+ assign GEN_1 = $signed(8193'h100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000);
+ assign T_712 = $signed(GEN_1) >>> T_710;
+ assign T_713 = T_712[1027:974];
+ assign T_714 = T_713[31:0];
+ assign T_717 = 16'hffff << 16;
+ assign T_718 = 32'hffffffff ^ T_717;
+ assign T_719 = T_714[31:16];
+ assign T_720 = T_719 & T_718;
+ assign T_721 = T_714[15:0];
+ assign T_722 = T_721 << 16;
+ assign T_723 = ~ T_718;
+ assign T_724 = T_722 & T_723;
+ assign T_725 = T_720 | T_724;
+ assign T_726 = T_718[23:0];
+ assign T_727 = T_726 << 8;
+ assign T_728 = T_718 ^ T_727;
+ assign T_729 = T_725[31:8];
+ assign T_730 = T_729 & T_728;
+ assign T_731 = T_725[23:0];
+ assign T_732 = T_731 << 8;
+ assign T_733 = ~ T_728;
+ assign T_734 = T_732 & T_733;
+ assign T_735 = T_730 | T_734;
+ assign T_736 = T_728[27:0];
+ assign T_737 = T_736 << 4;
+ assign T_738 = T_728 ^ T_737;
+ assign T_739 = T_735[31:4];
+ assign T_740 = T_739 & T_738;
+ assign T_741 = T_735[27:0];
+ assign T_742 = T_741 << 4;
+ assign T_743 = ~ T_738;
+ assign T_744 = T_742 & T_743;
+ assign T_745 = T_740 | T_744;
+ assign T_746 = T_738[29:0];
+ assign T_747 = T_746 << 2;
+ assign T_748 = T_738 ^ T_747;
+ assign T_749 = T_745[31:2];
+ assign T_750 = T_749 & T_748;
+ assign T_751 = T_745[29:0];
+ assign T_752 = T_751 << 2;
+ assign T_753 = ~ T_748;
+ assign T_754 = T_752 & T_753;
+ assign T_755 = T_750 | T_754;
+ assign T_756 = T_748[30:0];
+ assign T_757 = T_756 << 1;
+ assign T_758 = T_748 ^ T_757;
+ assign T_759 = T_755[31:1];
+ assign T_760 = T_759 & T_758;
+ assign T_761 = T_755[30:0];
+ assign T_762 = T_761 << 1;
+ assign T_763 = ~ T_758;
+ assign T_764 = T_762 & T_763;
+ assign T_765 = T_760 | T_764;
+ assign T_766 = T_713[53:32];
+ assign T_767 = T_766[15:0];
+ assign T_770 = 8'hff << 8;
+ assign T_771 = 16'hffff ^ T_770;
+ assign T_772 = T_767[15:8];
+ assign T_773 = T_772 & T_771;
+ assign T_774 = T_767[7:0];
+ assign T_775 = T_774 << 8;
+ assign T_776 = ~ T_771;
+ assign T_777 = T_775 & T_776;
+ assign T_778 = T_773 | T_777;
+ assign T_779 = T_771[11:0];
+ assign T_780 = T_779 << 4;
+ assign T_781 = T_771 ^ T_780;
+ assign T_782 = T_778[15:4];
+ assign T_783 = T_782 & T_781;
+ assign T_784 = T_778[11:0];
+ assign T_785 = T_784 << 4;
+ assign T_786 = ~ T_781;
+ assign T_787 = T_785 & T_786;
+ assign T_788 = T_783 | T_787;
+ assign T_789 = T_781[13:0];
+ assign T_790 = T_789 << 2;
+ assign T_791 = T_781 ^ T_790;
+ assign T_792 = T_788[15:2];
+ assign T_793 = T_792 & T_791;
+ assign T_794 = T_788[13:0];
+ assign T_795 = T_794 << 2;
+ assign T_796 = ~ T_791;
+ assign T_797 = T_795 & T_796;
+ assign T_798 = T_793 | T_797;
+ assign T_799 = T_791[14:0];
+ assign T_800 = T_799 << 1;
+ assign T_801 = T_791 ^ T_800;
+ assign T_802 = T_798[15:1];
+ assign T_803 = T_802 & T_801;
+ assign T_804 = T_798[14:0];
+ assign T_805 = T_804 << 1;
+ assign T_806 = ~ T_801;
+ assign T_807 = T_805 & T_806;
+ assign T_808 = T_803 | T_807;
+ assign T_809 = T_766[21:16];
+ assign T_810 = T_809[3:0];
+ assign T_811 = T_810[1:0];
+ assign T_812 = T_811[0];
+ assign T_813 = T_811[1];
+ assign T_814 = {T_812,T_813};
+ assign T_815 = T_810[3:2];
+ assign T_816 = T_815[0];
+ assign T_817 = T_815[1];
+ assign T_818 = {T_816,T_817};
+ assign T_819 = {T_814,T_818};
+ assign T_820 = T_809[5:4];
+ assign T_821 = T_820[0];
+ assign T_822 = T_820[1];
+ assign T_823 = {T_821,T_822};
+ assign T_824 = {T_819,T_823};
+ assign T_825 = {T_808,T_824};
+ assign T_826 = {T_765,T_825};
+ assign T_827 = sigX3[55];
+ assign T_828 = T_826 | T_827;
+ assign T_830 = {T_828,2'h3};
+ assign roundMask = T_709 | T_830;
+ assign T_832 = roundMask[55:1];
+ assign T_833 = ~ T_832;
+ assign roundPosMask = T_833 & roundMask;
+ assign T_835 = sigX3 & roundPosMask;
+ assign roundPosBit = T_835 != 1'h0;
+ assign T_838 = roundMask[55:1];
+ assign T_839 = sigX3 & T_838;
+ assign anyRoundExtra = T_839 != 1'h0;
+ assign T_842 = ~ sigX3;
+ assign T_843 = roundMask[55:1];
+ assign T_844 = T_842 & T_843;
+ assign allRoundExtra = T_844 == 1'h0;
+ assign anyRound = roundPosBit | anyRoundExtra;
+ assign allRound = roundPosBit & allRoundExtra;
+ assign roundDirectUp = signY ? roundingMode_min : roundingMode_max;
+ assign T_850 = ~ doIncrSig;
+ assign T_851 = T_850 & roundingMode_nearest_even;
+ assign T_852 = T_851 & roundPosBit;
+ assign T_853 = T_852 & anyRoundExtra;
+ assign T_854 = ~ doIncrSig;
+ assign T_855 = T_854 & roundDirectUp;
+ assign T_856 = T_855 & anyRound;
+ assign T_857 = T_853 | T_856;
+ assign T_858 = doIncrSig & allRound;
+ assign T_859 = T_857 | T_858;
+ assign T_860 = doIncrSig & roundingMode_nearest_even;
+ assign T_861 = T_860 & roundPosBit;
+ assign T_862 = T_859 | T_861;
+ assign T_863 = doIncrSig & roundDirectUp;
+ assign T_865 = T_863 & 1'h1;
+ assign roundUp = T_862 | T_865;
+ assign T_867 = ~ roundPosBit;
+ assign T_868 = roundingMode_nearest_even & T_867;
+ assign T_869 = T_868 & allRoundExtra;
+ assign T_870 = roundingMode_nearest_even & roundPosBit;
+ assign T_871 = ~ anyRoundExtra;
+ assign T_872 = T_870 & T_871;
+ assign roundEven = doIncrSig ? T_869 : T_872;
+ assign T_874 = ~ allRound;
+ assign roundInexact = doIncrSig ? T_874 : anyRound;
+ assign T_876 = sigX3 | roundMask;
+ assign T_877 = T_876[56:2];
+ assign T_879 = T_877 + 1'h1;
+ assign T_880 = T_879[54:0];
+ assign roundUp_sigY3 = T_880;
+ assign T_882 = ~ roundUp;
+ assign T_883 = ~ roundEven;
+ assign T_884 = T_882 & T_883;
+ assign T_885 = T_884;
+ assign T_886 = ~ roundMask;
+ assign T_887 = sigX3 & T_886;
+ assign T_888 = T_887[56:2];
+ assign T_890 = T_885 ? T_888 : 1'h0;
+ assign T_891 = roundUp;
+ assign T_893 = T_891 ? roundUp_sigY3 : 1'h0;
+ assign T_894 = T_890 | T_893;
+ assign T_895 = roundMask[55:1];
+ assign T_896 = ~ T_895;
+ assign T_897 = roundUp_sigY3 & T_896;
+ assign T_899 = roundEven ? T_897 : 1'h0;
+ assign sigY3 = T_894 | T_899;
+ assign T_901 = sigY3[54];
+ assign T_903 = sExpX3 + 1'h1;
+ assign T_904 = T_903[13:0];
+ assign T_906 = T_901 ? T_904 : 1'h0;
+ assign T_907 = sigY3[53];
+ assign T_909 = T_907 ? sExpX3 : 1'h0;
+ assign T_910 = T_906 | T_909;
+ assign T_911 = sigY3[54:53];
+ assign T_913 = T_911 == 1'h0;
+ assign T_915 = sExpX3 - 1'h1;
+ assign T_916 = T_915[13:0];
+ assign T_918 = T_913 ? T_916 : 1'h0;
+ assign sExpY = T_910 | T_918;
+ assign expY = sExpY[11:0];
+ assign T_921 = sigY3[51:0];
+ assign T_922 = sigY3[52:1];
+ assign fractY = sigX3Shift1 ? T_921 : T_922;
+ assign T_924 = sExpY[12:10];
+ assign overflowY = T_924 == 2'h3;
+ assign T_927 = ~ isZeroY;
+ assign T_928 = sExpY[12];
+ assign T_929 = sExpY[11:0];
+ assign T_931 = T_929 < 10'h3ce;
+ assign T_932 = T_928 | T_931;
+ assign totalUnderflowY = T_927 & T_932;
+ assign T_934 = sExpX3[13];
+ assign T_937 = sigX3Shift1 ? 11'h402 : 11'h401;
+ assign T_938 = sExpX3_13 <= T_937;
+ assign T_939 = T_934 | T_938;
+ assign underflowY = roundInexact & T_939;
+ assign T_941 = roundingMode_min & signY;
+ assign T_942 = ~ signY;
+ assign T_943 = roundingMode_max & T_942;
+ assign roundMagUp = T_941 | T_943;
+ assign overflowY_roundMagUp = roundingMode_nearest_even | roundMagUp;
+ assign mulSpecial = isSpecialA | isSpecialB;
+ assign addSpecial = mulSpecial | isSpecialC;
+ assign notSpecial_addZeros = io_fromPreMul_isZeroProd & isZeroC;
+ assign T_949 = ~ addSpecial;
+ assign T_950 = ~ notSpecial_addZeros;
+ assign commonCase = T_949 & T_950;
+ assign T_952 = isInfA & isZeroB;
+ assign T_953 = isZeroA & isInfB;
+ assign T_954 = T_952 | T_953;
+ assign T_955 = ~ isNaNA;
+ assign T_956 = ~ isNaNB;
+ assign T_957 = T_955 & T_956;
+ assign T_958 = isInfA | isInfB;
+ assign T_959 = T_957 & T_958;
+ assign T_960 = T_959 & isInfC;
+ assign T_961 = T_960 & doSubMags;
+ assign notSigNaN_invalid = T_954 | T_961;
+ assign T_963 = isSigNaNA | isSigNaNB;
+ assign T_964 = T_963 | isSigNaNC;
+ assign invalid = T_964 | notSigNaN_invalid;
+ assign overflow = commonCase & overflowY;
+ assign underflow = commonCase & underflowY;
+ assign T_968 = commonCase & roundInexact;
+ assign inexact = overflow | T_968;
+ assign T_970 = notSpecial_addZeros | isZeroY;
+ assign notSpecial_isZeroOut = T_970 | totalUnderflowY;
+ assign T_972 = commonCase & totalUnderflowY;
+ assign pegMinFiniteMagOut = T_972 & roundMagUp;
+ assign T_974 = ~ overflowY_roundMagUp;
+ assign pegMaxFiniteMagOut = overflow & T_974;
+ assign T_976 = isInfA | isInfB;
+ assign T_977 = T_976 | isInfC;
+ assign T_978 = overflow & overflowY_roundMagUp;
+ assign notNaN_isInfOut = T_977 | T_978;
+ assign T_980 = isNaNA | isNaNB;
+ assign T_981 = T_980 | isNaNC;
+ assign isNaNOut = T_981 | notSigNaN_invalid;
+ assign T_984 = doSubMags == 1'h0;
+ assign T_985 = T_984 & io_fromPreMul_opSignC;
+ assign T_987 = isSpecialC == 1'h0;
+ assign T_988 = mulSpecial & T_987;
+ assign T_989 = T_988 & io_fromPreMul_signProd;
+ assign T_990 = T_985 | T_989;
+ assign T_992 = mulSpecial == 1'h0;
+ assign T_993 = T_992 & isSpecialC;
+ assign T_994 = T_993 & io_fromPreMul_opSignC;
+ assign T_995 = T_990 | T_994;
+ assign T_997 = mulSpecial == 1'h0;
+ assign T_998 = T_997 & notSpecial_addZeros;
+ assign T_999 = T_998 & doSubMags;
+ assign T_1000 = T_999 & signZeroNotEqOpSigns;
+ assign uncommonCaseSignOut = T_995 | T_1000;
+ assign T_1003 = isNaNOut == 1'h0;
+ assign T_1004 = T_1003 & uncommonCaseSignOut;
+ assign T_1005 = commonCase & signY;
+ assign signOut = T_1004 | T_1005;
+ assign T_1009 = notSpecial_isZeroOut ? 12'he00 : 12'h0;
+ assign T_1010 = ~ T_1009;
+ assign T_1011 = expY & T_1010;
+ assign T_1013 = ~ 12'h3ce;
+ assign T_1015 = pegMinFiniteMagOut ? T_1013 : 12'h0;
+ assign T_1016 = ~ T_1015;
+ assign T_1017 = T_1011 & T_1016;
+ assign T_1020 = pegMaxFiniteMagOut ? 12'h400 : 12'h0;
+ assign T_1021 = ~ T_1020;
+ assign T_1022 = T_1017 & T_1021;
+ assign T_1025 = notNaN_isInfOut ? 10'h200 : 12'h0;
+ assign T_1026 = ~ T_1025;
+ assign T_1027 = T_1022 & T_1026;
+ assign T_1030 = pegMinFiniteMagOut ? 10'h3ce : 12'h0;
+ assign T_1031 = T_1027 | T_1030;
+ assign T_1034 = pegMaxFiniteMagOut ? 12'hbff : 12'h0;
+ assign T_1035 = T_1031 | T_1034;
+ assign T_1038 = notNaN_isInfOut ? 12'hc00 : 12'h0;
+ assign T_1039 = T_1035 | T_1038;
+ assign T_1042 = isNaNOut ? 12'he00 : 12'h0;
+ assign expOut = T_1039 | T_1042;
+ assign T_1044 = totalUnderflowY & roundMagUp;
+ assign T_1045 = T_1044 | isNaNOut;
+ assign T_1047 = T_1045 ? 1'h0 : fractY;
+ assign T_1048 = isNaNOut << 51;
+ assign T_1049 = T_1047 | T_1048;
+ assign T_1051 = 52'h0 - pegMaxFiniteMagOut;
+ assign T_1052 = T_1051[51:0];
+ assign fractOut = T_1049 | T_1052;
+ assign T_1054 = {expOut,fractOut};
+ assign T_1055 = {signOut,T_1054};
+ assign T_1057 = {invalid,1'h0};
+ assign T_1058 = {underflow,inexact};
+ assign T_1059 = {overflow,T_1058};
+ assign T_1060 = {T_1057,T_1059};
+endmodule
+module MulAddRecFN_114(
+ input clk,
+ input reset,
+ input [1:0] io_op,
+ input [64:0] io_a,
+ input [64:0] io_b,
+ input [64:0] io_c,
+ input [1:0] io_roundingMode,
+ output [64:0] io_out,
+ output [4:0] io_exceptionFlags
+);
+ wire mulAddRecFN_preMul_clk;
+ wire mulAddRecFN_preMul_reset;
+ wire [1:0] mulAddRecFN_preMul_io_op;
+ wire [64:0] mulAddRecFN_preMul_io_a;
+ wire [64:0] mulAddRecFN_preMul_io_b;
+ wire [64:0] mulAddRecFN_preMul_io_c;
+ wire [1:0] mulAddRecFN_preMul_io_roundingMode;
+ wire [52:0] mulAddRecFN_preMul_io_mulAddA;
+ wire [52:0] mulAddRecFN_preMul_io_mulAddB;
+ wire [105:0] mulAddRecFN_preMul_io_mulAddC;
+ wire [2:0] mulAddRecFN_preMul_io_toPostMul_highExpA;
+ wire mulAddRecFN_preMul_io_toPostMul_isNaN_isQuietNaNA;
+ wire [2:0] mulAddRecFN_preMul_io_toPostMul_highExpB;
+ wire mulAddRecFN_preMul_io_toPostMul_isNaN_isQuietNaNB;
+ wire mulAddRecFN_preMul_io_toPostMul_signProd;
+ wire mulAddRecFN_preMul_io_toPostMul_isZeroProd;
+ wire mulAddRecFN_preMul_io_toPostMul_opSignC;
+ wire [2:0] mulAddRecFN_preMul_io_toPostMul_highExpC;
+ wire mulAddRecFN_preMul_io_toPostMul_isNaN_isQuietNaNC;
+ wire mulAddRecFN_preMul_io_toPostMul_isCDominant;
+ wire mulAddRecFN_preMul_io_toPostMul_CAlignDist_0;
+ wire [7:0] mulAddRecFN_preMul_io_toPostMul_CAlignDist;
+ wire mulAddRecFN_preMul_io_toPostMul_bit0AlignedNegSigC;
+ wire [54:0] mulAddRecFN_preMul_io_toPostMul_highAlignedNegSigC;
+ wire [13:0] mulAddRecFN_preMul_io_toPostMul_sExpSum;
+ wire [1:0] mulAddRecFN_preMul_io_toPostMul_roundingMode;
+ wire mulAddRecFN_postMul_clk;
+ wire mulAddRecFN_postMul_reset;
+ wire [2:0] mulAddRecFN_postMul_io_fromPreMul_highExpA;
+ wire mulAddRecFN_postMul_io_fromPreMul_isNaN_isQuietNaNA;
+ wire [2:0] mulAddRecFN_postMul_io_fromPreMul_highExpB;
+ wire mulAddRecFN_postMul_io_fromPreMul_isNaN_isQuietNaNB;
+ wire mulAddRecFN_postMul_io_fromPreMul_signProd;
+ wire mulAddRecFN_postMul_io_fromPreMul_isZeroProd;
+ wire mulAddRecFN_postMul_io_fromPreMul_opSignC;
+ wire [2:0] mulAddRecFN_postMul_io_fromPreMul_highExpC;
+ wire mulAddRecFN_postMul_io_fromPreMul_isNaN_isQuietNaNC;
+ wire mulAddRecFN_postMul_io_fromPreMul_isCDominant;
+ wire mulAddRecFN_postMul_io_fromPreMul_CAlignDist_0;
+ wire [7:0] mulAddRecFN_postMul_io_fromPreMul_CAlignDist;
+ wire mulAddRecFN_postMul_io_fromPreMul_bit0AlignedNegSigC;
+ wire [54:0] mulAddRecFN_postMul_io_fromPreMul_highAlignedNegSigC;
+ wire [13:0] mulAddRecFN_postMul_io_fromPreMul_sExpSum;
+ wire [1:0] mulAddRecFN_postMul_io_fromPreMul_roundingMode;
+ wire [106:0] mulAddRecFN_postMul_io_mulAddResult;
+ wire [64:0] mulAddRecFN_postMul_io_out;
+ wire [4:0] mulAddRecFN_postMul_io_exceptionFlags;
+ wire [105:0] T_14;
+ wire [106:0] T_16;
+ wire [107:0] T_17;
+ wire [106:0] T_18;
+ MulAddRecFN_preMul_115 mulAddRecFN_preMul (
+ .clk(mulAddRecFN_preMul_clk),
+ .reset(mulAddRecFN_preMul_reset),
+ .io_op(mulAddRecFN_preMul_io_op),
+ .io_a(mulAddRecFN_preMul_io_a),
+ .io_b(mulAddRecFN_preMul_io_b),
+ .io_c(mulAddRecFN_preMul_io_c),
+ .io_roundingMode(mulAddRecFN_preMul_io_roundingMode),
+ .io_mulAddA(mulAddRecFN_preMul_io_mulAddA),
+ .io_mulAddB(mulAddRecFN_preMul_io_mulAddB),
+ .io_mulAddC(mulAddRecFN_preMul_io_mulAddC),
+ .io_toPostMul_highExpA(mulAddRecFN_preMul_io_toPostMul_highExpA),
+ .io_toPostMul_isNaN_isQuietNaNA(mulAddRecFN_preMul_io_toPostMul_isNaN_isQuietNaNA),
+ .io_toPostMul_highExpB(mulAddRecFN_preMul_io_toPostMul_highExpB),
+ .io_toPostMul_isNaN_isQuietNaNB(mulAddRecFN_preMul_io_toPostMul_isNaN_isQuietNaNB),
+ .io_toPostMul_signProd(mulAddRecFN_preMul_io_toPostMul_signProd),
+ .io_toPostMul_isZeroProd(mulAddRecFN_preMul_io_toPostMul_isZeroProd),
+ .io_toPostMul_opSignC(mulAddRecFN_preMul_io_toPostMul_opSignC),
+ .io_toPostMul_highExpC(mulAddRecFN_preMul_io_toPostMul_highExpC),
+ .io_toPostMul_isNaN_isQuietNaNC(mulAddRecFN_preMul_io_toPostMul_isNaN_isQuietNaNC),
+ .io_toPostMul_isCDominant(mulAddRecFN_preMul_io_toPostMul_isCDominant),
+ .io_toPostMul_CAlignDist_0(mulAddRecFN_preMul_io_toPostMul_CAlignDist_0),
+ .io_toPostMul_CAlignDist(mulAddRecFN_preMul_io_toPostMul_CAlignDist),
+ .io_toPostMul_bit0AlignedNegSigC(mulAddRecFN_preMul_io_toPostMul_bit0AlignedNegSigC),
+ .io_toPostMul_highAlignedNegSigC(mulAddRecFN_preMul_io_toPostMul_highAlignedNegSigC),
+ .io_toPostMul_sExpSum(mulAddRecFN_preMul_io_toPostMul_sExpSum),
+ .io_toPostMul_roundingMode(mulAddRecFN_preMul_io_toPostMul_roundingMode)
+ );
+ MulAddRecFN_postMul_116 mulAddRecFN_postMul (
+ .clk(mulAddRecFN_postMul_clk),
+ .reset(mulAddRecFN_postMul_reset),
+ .io_fromPreMul_highExpA(mulAddRecFN_postMul_io_fromPreMul_highExpA),
+ .io_fromPreMul_isNaN_isQuietNaNA(mulAddRecFN_postMul_io_fromPreMul_isNaN_isQuietNaNA),
+ .io_fromPreMul_highExpB(mulAddRecFN_postMul_io_fromPreMul_highExpB),
+ .io_fromPreMul_isNaN_isQuietNaNB(mulAddRecFN_postMul_io_fromPreMul_isNaN_isQuietNaNB),
+ .io_fromPreMul_signProd(mulAddRecFN_postMul_io_fromPreMul_signProd),
+ .io_fromPreMul_isZeroProd(mulAddRecFN_postMul_io_fromPreMul_isZeroProd),
+ .io_fromPreMul_opSignC(mulAddRecFN_postMul_io_fromPreMul_opSignC),
+ .io_fromPreMul_highExpC(mulAddRecFN_postMul_io_fromPreMul_highExpC),
+ .io_fromPreMul_isNaN_isQuietNaNC(mulAddRecFN_postMul_io_fromPreMul_isNaN_isQuietNaNC),
+ .io_fromPreMul_isCDominant(mulAddRecFN_postMul_io_fromPreMul_isCDominant),
+ .io_fromPreMul_CAlignDist_0(mulAddRecFN_postMul_io_fromPreMul_CAlignDist_0),
+ .io_fromPreMul_CAlignDist(mulAddRecFN_postMul_io_fromPreMul_CAlignDist),
+ .io_fromPreMul_bit0AlignedNegSigC(mulAddRecFN_postMul_io_fromPreMul_bit0AlignedNegSigC),
+ .io_fromPreMul_highAlignedNegSigC(mulAddRecFN_postMul_io_fromPreMul_highAlignedNegSigC),
+ .io_fromPreMul_sExpSum(mulAddRecFN_postMul_io_fromPreMul_sExpSum),
+ .io_fromPreMul_roundingMode(mulAddRecFN_postMul_io_fromPreMul_roundingMode),
+ .io_mulAddResult(mulAddRecFN_postMul_io_mulAddResult),
+ .io_out(mulAddRecFN_postMul_io_out),
+ .io_exceptionFlags(mulAddRecFN_postMul_io_exceptionFlags)
+ );
+ assign io_out = mulAddRecFN_postMul_io_out;
+ assign io_exceptionFlags = mulAddRecFN_postMul_io_exceptionFlags;
+ assign mulAddRecFN_preMul_clk = clk;
+ assign mulAddRecFN_preMul_reset = reset;
+ assign mulAddRecFN_preMul_io_op = io_op;
+ assign mulAddRecFN_preMul_io_a = io_a;
+ assign mulAddRecFN_preMul_io_b = io_b;
+ assign mulAddRecFN_preMul_io_c = io_c;
+ assign mulAddRecFN_preMul_io_roundingMode = io_roundingMode;
+ assign mulAddRecFN_postMul_clk = clk;
+ assign mulAddRecFN_postMul_reset = reset;
+ assign mulAddRecFN_postMul_io_fromPreMul_highExpA = mulAddRecFN_preMul_io_toPostMul_highExpA;
+ assign mulAddRecFN_postMul_io_fromPreMul_isNaN_isQuietNaNA = mulAddRecFN_preMul_io_toPostMul_isNaN_isQuietNaNA;
+ assign mulAddRecFN_postMul_io_fromPreMul_highExpB = mulAddRecFN_preMul_io_toPostMul_highExpB;
+ assign mulAddRecFN_postMul_io_fromPreMul_isNaN_isQuietNaNB = mulAddRecFN_preMul_io_toPostMul_isNaN_isQuietNaNB;
+ assign mulAddRecFN_postMul_io_fromPreMul_signProd = mulAddRecFN_preMul_io_toPostMul_signProd;
+ assign mulAddRecFN_postMul_io_fromPreMul_isZeroProd = mulAddRecFN_preMul_io_toPostMul_isZeroProd;
+ assign mulAddRecFN_postMul_io_fromPreMul_opSignC = mulAddRecFN_preMul_io_toPostMul_opSignC;
+ assign mulAddRecFN_postMul_io_fromPreMul_highExpC = mulAddRecFN_preMul_io_toPostMul_highExpC;
+ assign mulAddRecFN_postMul_io_fromPreMul_isNaN_isQuietNaNC = mulAddRecFN_preMul_io_toPostMul_isNaN_isQuietNaNC;
+ assign mulAddRecFN_postMul_io_fromPreMul_isCDominant = mulAddRecFN_preMul_io_toPostMul_isCDominant;
+ assign mulAddRecFN_postMul_io_fromPreMul_CAlignDist_0 = mulAddRecFN_preMul_io_toPostMul_CAlignDist_0;
+ assign mulAddRecFN_postMul_io_fromPreMul_CAlignDist = mulAddRecFN_preMul_io_toPostMul_CAlignDist;
+ assign mulAddRecFN_postMul_io_fromPreMul_bit0AlignedNegSigC = mulAddRecFN_preMul_io_toPostMul_bit0AlignedNegSigC;
+ assign mulAddRecFN_postMul_io_fromPreMul_highAlignedNegSigC = mulAddRecFN_preMul_io_toPostMul_highAlignedNegSigC;
+ assign mulAddRecFN_postMul_io_fromPreMul_sExpSum = mulAddRecFN_preMul_io_toPostMul_sExpSum;
+ assign mulAddRecFN_postMul_io_fromPreMul_roundingMode = mulAddRecFN_preMul_io_toPostMul_roundingMode;
+ assign mulAddRecFN_postMul_io_mulAddResult = T_18;
+ assign T_14 = mulAddRecFN_preMul_io_mulAddA * mulAddRecFN_preMul_io_mulAddB;
+ assign T_16 = {1'h0,mulAddRecFN_preMul_io_mulAddC};
+ assign T_17 = T_14 + T_16;
+ assign T_18 = T_17[106:0];
+endmodule
+module FPUFMAPipe_113(
+ input clk,
+ input reset,
+ input io_in_valid,
+ input [4:0] io_in_bits_cmd,
+ input io_in_bits_ldst,
+ input io_in_bits_wen,
+ input io_in_bits_ren1,
+ input io_in_bits_ren2,
+ input io_in_bits_ren3,
+ input io_in_bits_swap12,
+ input io_in_bits_swap23,
+ input io_in_bits_single,
+ input io_in_bits_fromint,
+ input io_in_bits_toint,
+ input io_in_bits_fastpipe,
+ input io_in_bits_fma,
+ input io_in_bits_div,
+ input io_in_bits_sqrt,
+ input io_in_bits_round,
+ input io_in_bits_wflags,
+ input [2:0] io_in_bits_rm,
+ input [1:0] io_in_bits_typ,
+ input [64:0] io_in_bits_in1,
+ input [64:0] io_in_bits_in2,
+ input [64:0] io_in_bits_in3,
+ output io_out_valid,
+ output [64:0] io_out_bits_data,
+ output [4:0] io_out_bits_exc
+);
+ wire [63:0] one;
+ wire T_136;
+ wire T_137;
+ wire T_138;
+ wire [64:0] zero;
+ reg valid;
+ reg [4:0] in_cmd;
+ reg in_ldst;
+ reg in_wen;
+ reg in_ren1;
+ reg in_ren2;
+ reg in_ren3;
+ reg in_swap12;
+ reg in_swap23;
+ reg in_single;
+ reg in_fromint;
+ reg in_toint;
+ reg in_fastpipe;
+ reg in_fma;
+ reg in_div;
+ reg in_sqrt;
+ reg in_round;
+ reg in_wflags;
+ reg [2:0] in_rm;
+ reg [1:0] in_typ;
+ reg [64:0] in_in1;
+ reg [64:0] in_in2;
+ reg [64:0] in_in3;
+ wire T_187;
+ wire T_188;
+ wire T_189;
+ wire T_190;
+ wire [1:0] T_191;
+ wire T_192;
+ wire T_194;
+ wire fma_clk;
+ wire fma_reset;
+ wire [1:0] fma_io_op;
+ wire [64:0] fma_io_a;
+ wire [64:0] fma_io_b;
+ wire [64:0] fma_io_c;
+ wire [1:0] fma_io_roundingMode;
+ wire [64:0] fma_io_out;
+ wire [4:0] fma_io_exceptionFlags;
+ wire [64:0] res_data;
+ wire [4:0] res_exc;
+ wire [31:0] GEN_0;
+ wire [31:0] T_203;
+ wire [96:0] T_204;
+ reg T_207;
+ reg [64:0] T_208_data;
+ reg [4:0] T_208_exc;
+ reg T_213;
+ reg [64:0] T_214_data;
+ reg [4:0] T_214_exc;
+ wire T_225_valid;
+ wire [64:0] T_225_bits_data;
+ wire [4:0] T_225_bits_exc;
+ MulAddRecFN_114 fma (
+ .clk(fma_clk),
+ .reset(fma_reset),
+ .io_op(fma_io_op),
+ .io_a(fma_io_a),
+ .io_b(fma_io_b),
+ .io_c(fma_io_c),
+ .io_roundingMode(fma_io_roundingMode),
+ .io_out(fma_io_out),
+ .io_exceptionFlags(fma_io_exceptionFlags)
+ );
+ assign io_out_valid = T_225_valid;
+ assign io_out_bits_data = T_225_bits_data;
+ assign io_out_bits_exc = T_225_bits_exc;
+ assign one = 1'h1 << 63;
+ assign T_136 = io_in_bits_in1[64];
+ assign T_137 = io_in_bits_in2[64];
+ assign T_138 = T_136 ^ T_137;
+ assign zero = T_138 << 64;
+ assign T_187 = io_in_bits_cmd[1];
+ assign T_188 = io_in_bits_ren3 | io_in_bits_swap23;
+ assign T_189 = T_187 & T_188;
+ assign T_190 = io_in_bits_cmd[0];
+ assign T_191 = {T_189,T_190};
+ assign T_192 = io_in_bits_ren3 | io_in_bits_swap23;
+ assign T_194 = T_192 == 1'h0;
+ assign fma_clk = clk;
+ assign fma_reset = reset;
+ assign fma_io_op = in_cmd;
+ assign fma_io_a = in_in1;
+ assign fma_io_b = in_in2;
+ assign fma_io_c = in_in3;
+ assign fma_io_roundingMode = in_rm;
+ assign res_data = T_204;
+ assign res_exc = fma_io_exceptionFlags;
+ assign GEN_0 = $signed(32'hffffffff);
+ assign T_203 = $unsigned(GEN_0);
+ assign T_204 = {T_203,fma_io_out};
+ assign T_225_valid = T_213;
+ assign T_225_bits_data = T_214_data;
+ assign T_225_bits_exc = T_214_exc;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ valid = {1{$random}};
+ in_cmd = {1{$random}};
+ in_ldst = {1{$random}};
+ in_wen = {1{$random}};
+ in_ren1 = {1{$random}};
+ in_ren2 = {1{$random}};
+ in_ren3 = {1{$random}};
+ in_swap12 = {1{$random}};
+ in_swap23 = {1{$random}};
+ in_single = {1{$random}};
+ in_fromint = {1{$random}};
+ in_toint = {1{$random}};
+ in_fastpipe = {1{$random}};
+ in_fma = {1{$random}};
+ in_div = {1{$random}};
+ in_sqrt = {1{$random}};
+ in_round = {1{$random}};
+ in_wflags = {1{$random}};
+ in_rm = {1{$random}};
+ in_typ = {1{$random}};
+ in_in1 = {3{$random}};
+ in_in2 = {3{$random}};
+ in_in3 = {3{$random}};
+ T_207 = {1{$random}};
+ T_208_data = {3{$random}};
+ T_208_exc = {1{$random}};
+ T_213 = {1{$random}};
+ T_214_data = {3{$random}};
+ T_214_exc = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(1'h0) begin
+ ;
+ end else begin
+ valid <= io_in_valid;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_cmd <= T_191;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_ldst <= io_in_bits_ldst;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_wen <= io_in_bits_wen;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_ren1 <= io_in_bits_ren1;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_ren2 <= io_in_bits_ren2;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_ren3 <= io_in_bits_ren3;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_swap12 <= io_in_bits_swap12;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_swap23 <= io_in_bits_swap23;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_single <= io_in_bits_single;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_fromint <= io_in_bits_fromint;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_toint <= io_in_bits_toint;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_fastpipe <= io_in_bits_fastpipe;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_fma <= io_in_bits_fma;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_div <= io_in_bits_div;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_sqrt <= io_in_bits_sqrt;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_round <= io_in_bits_round;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_wflags <= io_in_bits_wflags;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_rm <= io_in_bits_rm;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_typ <= io_in_bits_typ;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_in1 <= io_in_bits_in1;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ if(io_in_bits_swap23) begin
+ in_in2 <= one;
+ end else begin
+ in_in2 <= io_in_bits_in2;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ if(T_194) begin
+ in_in3 <= zero;
+ end else begin
+ in_in3 <= io_in_bits_in3;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_207 <= 1'h0;
+ end else begin
+ T_207 <= valid;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(valid) begin
+ T_208_data <= res_data;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(valid) begin
+ T_208_exc <= res_exc;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_213 <= 1'h0;
+ end else begin
+ T_213 <= T_207;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_207) begin
+ T_214_data <= T_208_data;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_207) begin
+ T_214_exc <= T_208_exc;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module RecFNToRecFN(
+ input clk,
+ input reset,
+ input [32:0] io_in,
+ input [1:0] io_roundingMode,
+ output [64:0] io_out,
+ output [4:0] io_exceptionFlags
+);
+ wire [8:0] T_8;
+ wire [1:0] T_9;
+ wire T_11;
+ wire T_19_sign;
+ wire T_19_isNaN;
+ wire T_19_isInf;
+ wire T_19_isZero;
+ wire [9:0] T_19_sExp;
+ wire [26:0] T_19_sig;
+ wire T_26;
+ wire T_27;
+ wire T_28;
+ wire T_29;
+ wire T_31;
+ wire T_32;
+ wire [2:0] T_33;
+ wire T_35;
+ wire [9:0] T_36;
+ wire [22:0] T_38;
+ wire [24:0] T_40;
+ wire [26:0] T_41;
+ wire [11:0] GEN_0;
+ wire [12:0] T_43;
+ wire [11:0] T_44;
+ wire [11:0] T_45;
+ wire outRawFloat_sign;
+ wire outRawFloat_isNaN;
+ wire outRawFloat_isInf;
+ wire outRawFloat_isZero;
+ wire [12:0] outRawFloat_sExp;
+ wire [55:0] outRawFloat_sig;
+ wire [55:0] T_60;
+ wire T_61;
+ wire T_63;
+ wire invalidExc;
+ wire T_65;
+ wire T_66;
+ wire [11:0] T_67;
+ wire [11:0] T_70;
+ wire [11:0] T_71;
+ wire [11:0] T_72;
+ wire T_73;
+ wire [11:0] T_76;
+ wire [11:0] T_77;
+ wire [11:0] T_78;
+ wire [11:0] T_81;
+ wire [11:0] T_82;
+ wire [11:0] T_85;
+ wire [11:0] T_86;
+ wire [51:0] T_88;
+ wire [51:0] T_89;
+ wire [63:0] T_90;
+ wire [64:0] T_91;
+ wire [4:0] T_93;
+ assign io_out = T_91;
+ assign io_exceptionFlags = T_93;
+ assign T_8 = io_in[31:23];
+ assign T_9 = T_8[8:7];
+ assign T_11 = T_9 == 2'h3;
+ assign T_19_sign = T_26;
+ assign T_19_isNaN = T_28;
+ assign T_19_isInf = T_32;
+ assign T_19_isZero = T_35;
+ assign T_19_sExp = T_36;
+ assign T_19_sig = T_41;
+ assign T_26 = io_in[32];
+ assign T_27 = T_8[6];
+ assign T_28 = T_11 & T_27;
+ assign T_29 = T_8[6];
+ assign T_31 = T_29 == 1'h0;
+ assign T_32 = T_11 & T_31;
+ assign T_33 = T_8[8:6];
+ assign T_35 = T_33 == 1'h0;
+ assign T_36 = {1'b0,$signed(T_8)};
+ assign T_38 = io_in[22:0];
+ assign T_40 = {T_38,2'h0};
+ assign T_41 = {2'h1,T_40};
+ assign GEN_0 = $signed(12'h700);
+ assign T_43 = $signed(T_19_sExp) + $signed(GEN_0);
+ assign T_44 = T_43[11:0];
+ assign T_45 = $signed(T_44);
+ assign outRawFloat_sign = T_19_sign;
+ assign outRawFloat_isNaN = T_19_isNaN;
+ assign outRawFloat_isInf = T_19_isInf;
+ assign outRawFloat_isZero = T_19_isZero;
+ assign outRawFloat_sExp = T_45;
+ assign outRawFloat_sig = T_60;
+ assign T_60 = T_19_sig << 29;
+ assign T_61 = outRawFloat_sig[53];
+ assign T_63 = T_61 == 1'h0;
+ assign invalidExc = outRawFloat_isNaN & T_63;
+ assign T_65 = ~ outRawFloat_isNaN;
+ assign T_66 = outRawFloat_sign & T_65;
+ assign T_67 = outRawFloat_sExp[11:0];
+ assign T_70 = outRawFloat_isZero ? 12'hc00 : 1'h0;
+ assign T_71 = ~ T_70;
+ assign T_72 = T_67 & T_71;
+ assign T_73 = outRawFloat_isZero | outRawFloat_isInf;
+ assign T_76 = T_73 ? 12'h200 : 1'h0;
+ assign T_77 = ~ T_76;
+ assign T_78 = T_72 & T_77;
+ assign T_81 = outRawFloat_isInf ? 12'hc00 : 1'h0;
+ assign T_82 = T_78 | T_81;
+ assign T_85 = outRawFloat_isNaN ? 12'he00 : 1'h0;
+ assign T_86 = T_82 | T_85;
+ assign T_88 = outRawFloat_sig[53:2];
+ assign T_89 = outRawFloat_isNaN ? 52'h8000000000000 : T_88;
+ assign T_90 = {T_86,T_89};
+ assign T_91 = {T_66,T_90};
+ assign T_93 = {invalidExc,4'h0};
+endmodule
+module CompareRecFN(
+ input clk,
+ input reset,
+ input [64:0] io_a,
+ input [64:0] io_b,
+ input io_signaling,
+ output io_lt,
+ output io_eq,
+ output io_gt,
+ output [4:0] io_exceptionFlags
+);
+ wire [11:0] T_11;
+ wire [1:0] T_12;
+ wire T_14;
+ wire rawA_sign;
+ wire rawA_isNaN;
+ wire rawA_isInf;
+ wire rawA_isZero;
+ wire [12:0] rawA_sExp;
+ wire [55:0] rawA_sig;
+ wire T_29;
+ wire T_30;
+ wire T_31;
+ wire T_32;
+ wire T_34;
+ wire T_35;
+ wire [2:0] T_36;
+ wire T_38;
+ wire [12:0] T_39;
+ wire [51:0] T_41;
+ wire [53:0] T_43;
+ wire [55:0] T_44;
+ wire [11:0] T_45;
+ wire [1:0] T_46;
+ wire T_48;
+ wire rawB_sign;
+ wire rawB_isNaN;
+ wire rawB_isInf;
+ wire rawB_isZero;
+ wire [12:0] rawB_sExp;
+ wire [55:0] rawB_sig;
+ wire T_63;
+ wire T_64;
+ wire T_65;
+ wire T_66;
+ wire T_68;
+ wire T_69;
+ wire [2:0] T_70;
+ wire T_72;
+ wire [12:0] T_73;
+ wire [51:0] T_75;
+ wire [53:0] T_77;
+ wire [55:0] T_78;
+ wire T_79;
+ wire T_80;
+ wire ordered;
+ wire bothInfs;
+ wire bothZeros;
+ wire eqExps;
+ wire T_85;
+ wire T_86;
+ wire T_87;
+ wire common_ltMags;
+ wire T_89;
+ wire common_eqMags;
+ wire T_91;
+ wire T_92;
+ wire T_93;
+ wire T_94;
+ wire T_95;
+ wire T_96;
+ wire T_97;
+ wire T_98;
+ wire T_99;
+ wire T_100;
+ wire T_101;
+ wire T_102;
+ wire T_103;
+ wire ordered_lt;
+ wire T_105;
+ wire T_106;
+ wire T_107;
+ wire ordered_eq;
+ wire T_109;
+ wire T_111;
+ wire T_112;
+ wire T_113;
+ wire T_115;
+ wire T_116;
+ wire T_117;
+ wire T_118;
+ wire T_119;
+ wire invalid;
+ wire T_121;
+ wire T_122;
+ wire T_123;
+ wire T_124;
+ wire T_125;
+ wire T_126;
+ wire [4:0] T_128;
+ assign io_lt = T_121;
+ assign io_eq = T_122;
+ assign io_gt = T_126;
+ assign io_exceptionFlags = T_128;
+ assign T_11 = io_a[63:52];
+ assign T_12 = T_11[11:10];
+ assign T_14 = T_12 == 2'h3;
+ assign rawA_sign = T_29;
+ assign rawA_isNaN = T_31;
+ assign rawA_isInf = T_35;
+ assign rawA_isZero = T_38;
+ assign rawA_sExp = T_39;
+ assign rawA_sig = T_44;
+ assign T_29 = io_a[64];
+ assign T_30 = T_11[9];
+ assign T_31 = T_14 & T_30;
+ assign T_32 = T_11[9];
+ assign T_34 = T_32 == 1'h0;
+ assign T_35 = T_14 & T_34;
+ assign T_36 = T_11[11:9];
+ assign T_38 = T_36 == 1'h0;
+ assign T_39 = {1'b0,$signed(T_11)};
+ assign T_41 = io_a[51:0];
+ assign T_43 = {T_41,2'h0};
+ assign T_44 = {2'h1,T_43};
+ assign T_45 = io_b[63:52];
+ assign T_46 = T_45[11:10];
+ assign T_48 = T_46 == 2'h3;
+ assign rawB_sign = T_63;
+ assign rawB_isNaN = T_65;
+ assign rawB_isInf = T_69;
+ assign rawB_isZero = T_72;
+ assign rawB_sExp = T_73;
+ assign rawB_sig = T_78;
+ assign T_63 = io_b[64];
+ assign T_64 = T_45[9];
+ assign T_65 = T_48 & T_64;
+ assign T_66 = T_45[9];
+ assign T_68 = T_66 == 1'h0;
+ assign T_69 = T_48 & T_68;
+ assign T_70 = T_45[11:9];
+ assign T_72 = T_70 == 1'h0;
+ assign T_73 = {1'b0,$signed(T_45)};
+ assign T_75 = io_b[51:0];
+ assign T_77 = {T_75,2'h0};
+ assign T_78 = {2'h1,T_77};
+ assign T_79 = ~ rawA_isNaN;
+ assign T_80 = ~ rawB_isNaN;
+ assign ordered = T_79 & T_80;
+ assign bothInfs = rawA_isInf & rawB_isInf;
+ assign bothZeros = rawA_isZero & rawB_isZero;
+ assign eqExps = $signed(rawA_sExp) == $signed(rawB_sExp);
+ assign T_85 = $signed(rawA_sExp) < $signed(rawB_sExp);
+ assign T_86 = rawA_sig < rawB_sig;
+ assign T_87 = eqExps & T_86;
+ assign common_ltMags = T_85 | T_87;
+ assign T_89 = rawA_sig == rawB_sig;
+ assign common_eqMags = eqExps & T_89;
+ assign T_91 = ~ bothZeros;
+ assign T_92 = ~ rawB_sign;
+ assign T_93 = rawA_sign & T_92;
+ assign T_94 = ~ bothInfs;
+ assign T_95 = ~ common_ltMags;
+ assign T_96 = rawA_sign & T_95;
+ assign T_97 = ~ common_eqMags;
+ assign T_98 = T_96 & T_97;
+ assign T_99 = ~ rawB_sign;
+ assign T_100 = T_99 & common_ltMags;
+ assign T_101 = T_98 | T_100;
+ assign T_102 = T_94 & T_101;
+ assign T_103 = T_93 | T_102;
+ assign ordered_lt = T_91 & T_103;
+ assign T_105 = rawA_sign == rawB_sign;
+ assign T_106 = bothInfs | common_eqMags;
+ assign T_107 = T_105 & T_106;
+ assign ordered_eq = bothZeros | T_107;
+ assign T_109 = rawA_sig[53];
+ assign T_111 = T_109 == 1'h0;
+ assign T_112 = rawA_isNaN & T_111;
+ assign T_113 = rawB_sig[53];
+ assign T_115 = T_113 == 1'h0;
+ assign T_116 = rawB_isNaN & T_115;
+ assign T_117 = T_112 | T_116;
+ assign T_118 = ~ ordered;
+ assign T_119 = io_signaling & T_118;
+ assign invalid = T_117 | T_119;
+ assign T_121 = ordered & ordered_lt;
+ assign T_122 = ordered & ordered_eq;
+ assign T_123 = ~ ordered_lt;
+ assign T_124 = ordered & T_123;
+ assign T_125 = ~ ordered_eq;
+ assign T_126 = T_124 & T_125;
+ assign T_128 = {invalid,4'h0};
+endmodule
+module RecFNToIN(
+ input clk,
+ input reset,
+ input [64:0] io_in,
+ input [1:0] io_roundingMode,
+ input io_signedOut,
+ output [63:0] io_out,
+ output [2:0] io_intExceptionFlags
+);
+ wire sign;
+ wire [11:0] exp;
+ wire [51:0] fract;
+ wire [2:0] T_12;
+ wire isZero;
+ wire [1:0] T_15;
+ wire [1:0] T_16;
+ wire isSpecial;
+ wire T_19;
+ wire isNaN;
+ wire notSpecial_magGeOne;
+ wire [52:0] T_22;
+ wire [5:0] T_23;
+ wire [5:0] T_25;
+ wire [115:0] shiftedSig;
+ wire [63:0] unroundedInt;
+ wire [1:0] T_28;
+ wire [50:0] T_29;
+ wire T_31;
+ wire [2:0] roundBits;
+ wire [1:0] T_33;
+ wire T_35;
+ wire T_37;
+ wire roundInexact;
+ wire [1:0] T_39;
+ wire [1:0] T_40;
+ wire T_42;
+ wire [1:0] T_43;
+ wire [1:0] T_44;
+ wire T_46;
+ wire T_47;
+ wire [10:0] T_48;
+ wire [10:0] T_49;
+ wire T_51;
+ wire [1:0] T_52;
+ wire T_54;
+ wire T_56;
+ wire roundIncr_nearestEven;
+ wire T_58;
+ wire T_59;
+ wire T_60;
+ wire T_61;
+ wire T_62;
+ wire T_63;
+ wire T_64;
+ wire T_66;
+ wire T_67;
+ wire T_68;
+ wire roundIncr;
+ wire [63:0] T_70;
+ wire [63:0] onesCompUnroundedInt;
+ wire T_72;
+ wire [64:0] T_74;
+ wire [63:0] T_75;
+ wire [63:0] roundedInt;
+ wire [61:0] T_77;
+ wire [61:0] T_78;
+ wire T_80;
+ wire roundCarryBut2;
+ wire [10:0] posExp;
+ wire T_84;
+ wire T_86;
+ wire T_88;
+ wire [62:0] T_89;
+ wire T_91;
+ wire T_92;
+ wire T_93;
+ wire T_94;
+ wire T_95;
+ wire T_97;
+ wire T_99;
+ wire T_100;
+ wire T_101;
+ wire T_102;
+ wire overflow_signed;
+ wire T_106;
+ wire T_107;
+ wire T_109;
+ wire T_110;
+ wire T_111;
+ wire T_112;
+ wire T_113;
+ wire T_114;
+ wire overflow_unsigned;
+ wire overflow;
+ wire T_118;
+ wire excSign;
+ wire T_120;
+ wire [63:0] T_123;
+ wire T_125;
+ wire T_126;
+ wire [62:0] T_129;
+ wire [63:0] T_130;
+ wire T_132;
+ wire [63:0] T_135;
+ wire [63:0] excValue;
+ wire T_138;
+ wire T_139;
+ wire T_141;
+ wire inexact;
+ wire T_143;
+ wire [63:0] T_144;
+ wire [1:0] T_145;
+ wire [2:0] T_146;
+ assign io_out = T_144;
+ assign io_intExceptionFlags = T_146;
+ assign sign = io_in[64];
+ assign exp = io_in[63:52];
+ assign fract = io_in[51:0];
+ assign T_12 = exp[11:9];
+ assign isZero = T_12 == 1'h0;
+ assign T_15 = exp[11:10];
+ assign T_16 = ~ T_15;
+ assign isSpecial = T_16 == 1'h0;
+ assign T_19 = exp[9];
+ assign isNaN = isSpecial & T_19;
+ assign notSpecial_magGeOne = exp[11];
+ assign T_22 = {notSpecial_magGeOne,fract};
+ assign T_23 = exp[5:0];
+ assign T_25 = notSpecial_magGeOne ? T_23 : 1'h0;
+ assign shiftedSig = T_22 << T_25;
+ assign unroundedInt = shiftedSig[115:52];
+ assign T_28 = shiftedSig[52:51];
+ assign T_29 = shiftedSig[50:0];
+ assign T_31 = T_29 != 1'h0;
+ assign roundBits = {T_28,T_31};
+ assign T_33 = roundBits[1:0];
+ assign T_35 = T_33 != 1'h0;
+ assign T_37 = isZero == 1'h0;
+ assign roundInexact = notSpecial_magGeOne ? T_35 : T_37;
+ assign T_39 = roundBits[2:1];
+ assign T_40 = ~ T_39;
+ assign T_42 = T_40 == 1'h0;
+ assign T_43 = roundBits[1:0];
+ assign T_44 = ~ T_43;
+ assign T_46 = T_44 == 1'h0;
+ assign T_47 = T_42 | T_46;
+ assign T_48 = exp[10:0];
+ assign T_49 = ~ T_48;
+ assign T_51 = T_49 == 1'h0;
+ assign T_52 = roundBits[1:0];
+ assign T_54 = T_52 != 1'h0;
+ assign T_56 = T_51 ? T_54 : 1'h0;
+ assign roundIncr_nearestEven = notSpecial_magGeOne ? T_47 : T_56;
+ assign T_58 = io_roundingMode == 2'h0;
+ assign T_59 = T_58 & roundIncr_nearestEven;
+ assign T_60 = io_roundingMode == 2'h2;
+ assign T_61 = sign & roundInexact;
+ assign T_62 = T_60 & T_61;
+ assign T_63 = T_59 | T_62;
+ assign T_64 = io_roundingMode == 2'h3;
+ assign T_66 = sign == 1'h0;
+ assign T_67 = T_66 & roundInexact;
+ assign T_68 = T_64 & T_67;
+ assign roundIncr = T_63 | T_68;
+ assign T_70 = ~ unroundedInt;
+ assign onesCompUnroundedInt = sign ? T_70 : unroundedInt;
+ assign T_72 = roundIncr ^ sign;
+ assign T_74 = onesCompUnroundedInt + 1'h1;
+ assign T_75 = T_74[63:0];
+ assign roundedInt = T_72 ? T_75 : onesCompUnroundedInt;
+ assign T_77 = unroundedInt[61:0];
+ assign T_78 = ~ T_77;
+ assign T_80 = T_78 == 1'h0;
+ assign roundCarryBut2 = T_80 & roundIncr;
+ assign posExp = exp[10:0];
+ assign T_84 = posExp >= 7'h40;
+ assign T_86 = posExp == 6'h3f;
+ assign T_88 = sign == 1'h0;
+ assign T_89 = unroundedInt[62:0];
+ assign T_91 = T_89 != 1'h0;
+ assign T_92 = T_88 | T_91;
+ assign T_93 = T_92 | roundIncr;
+ assign T_94 = T_86 & T_93;
+ assign T_95 = T_84 | T_94;
+ assign T_97 = sign == 1'h0;
+ assign T_99 = posExp == 6'h3e;
+ assign T_100 = T_97 & T_99;
+ assign T_101 = T_100 & roundCarryBut2;
+ assign T_102 = T_95 | T_101;
+ assign overflow_signed = notSpecial_magGeOne ? T_102 : 1'h0;
+ assign T_106 = posExp >= 7'h40;
+ assign T_107 = sign | T_106;
+ assign T_109 = posExp == 6'h3f;
+ assign T_110 = unroundedInt[62];
+ assign T_111 = T_109 & T_110;
+ assign T_112 = T_111 & roundCarryBut2;
+ assign T_113 = T_107 | T_112;
+ assign T_114 = sign & roundIncr;
+ assign overflow_unsigned = notSpecial_magGeOne ? T_113 : T_114;
+ assign overflow = io_signedOut ? overflow_signed : overflow_unsigned;
+ assign T_118 = isNaN == 1'h0;
+ assign excSign = sign & T_118;
+ assign T_120 = io_signedOut & excSign;
+ assign T_123 = T_120 ? 64'h8000000000000000 : 1'h0;
+ assign T_125 = excSign == 1'h0;
+ assign T_126 = io_signedOut & T_125;
+ assign T_129 = T_126 ? 63'h7fffffffffffffff : 1'h0;
+ assign T_130 = T_123 | T_129;
+ assign T_132 = io_signedOut == 1'h0;
+ assign T_135 = T_132 ? 64'hffffffffffffffff : 1'h0;
+ assign excValue = T_130 | T_135;
+ assign T_138 = isSpecial == 1'h0;
+ assign T_139 = roundInexact & T_138;
+ assign T_141 = overflow == 1'h0;
+ assign inexact = T_139 & T_141;
+ assign T_143 = isSpecial | overflow;
+ assign T_144 = T_143 ? excValue : roundedInt;
+ assign T_145 = {overflow,inexact};
+ assign T_146 = {isSpecial,T_145};
+endmodule
+module RecFNToIN_118(
+ input clk,
+ input reset,
+ input [64:0] io_in,
+ input [1:0] io_roundingMode,
+ input io_signedOut,
+ output [31:0] io_out,
+ output [2:0] io_intExceptionFlags
+);
+ wire sign;
+ wire [11:0] exp;
+ wire [51:0] fract;
+ wire [2:0] T_12;
+ wire isZero;
+ wire [1:0] T_15;
+ wire [1:0] T_16;
+ wire isSpecial;
+ wire T_19;
+ wire isNaN;
+ wire notSpecial_magGeOne;
+ wire [52:0] T_22;
+ wire [4:0] T_23;
+ wire [4:0] T_25;
+ wire [83:0] shiftedSig;
+ wire [31:0] unroundedInt;
+ wire [1:0] T_28;
+ wire [50:0] T_29;
+ wire T_31;
+ wire [2:0] roundBits;
+ wire [1:0] T_33;
+ wire T_35;
+ wire T_37;
+ wire roundInexact;
+ wire [1:0] T_39;
+ wire [1:0] T_40;
+ wire T_42;
+ wire [1:0] T_43;
+ wire [1:0] T_44;
+ wire T_46;
+ wire T_47;
+ wire [10:0] T_48;
+ wire [10:0] T_49;
+ wire T_51;
+ wire [1:0] T_52;
+ wire T_54;
+ wire T_56;
+ wire roundIncr_nearestEven;
+ wire T_58;
+ wire T_59;
+ wire T_60;
+ wire T_61;
+ wire T_62;
+ wire T_63;
+ wire T_64;
+ wire T_66;
+ wire T_67;
+ wire T_68;
+ wire roundIncr;
+ wire [31:0] T_70;
+ wire [31:0] onesCompUnroundedInt;
+ wire T_72;
+ wire [32:0] T_74;
+ wire [31:0] T_75;
+ wire [31:0] roundedInt;
+ wire [29:0] T_77;
+ wire [29:0] T_78;
+ wire T_80;
+ wire roundCarryBut2;
+ wire [10:0] posExp;
+ wire T_84;
+ wire T_86;
+ wire T_88;
+ wire [30:0] T_89;
+ wire T_91;
+ wire T_92;
+ wire T_93;
+ wire T_94;
+ wire T_95;
+ wire T_97;
+ wire T_99;
+ wire T_100;
+ wire T_101;
+ wire T_102;
+ wire overflow_signed;
+ wire T_106;
+ wire T_107;
+ wire T_109;
+ wire T_110;
+ wire T_111;
+ wire T_112;
+ wire T_113;
+ wire T_114;
+ wire overflow_unsigned;
+ wire overflow;
+ wire T_118;
+ wire excSign;
+ wire T_120;
+ wire [31:0] T_123;
+ wire T_125;
+ wire T_126;
+ wire [30:0] T_129;
+ wire [31:0] T_130;
+ wire T_132;
+ wire [31:0] T_135;
+ wire [31:0] excValue;
+ wire T_138;
+ wire T_139;
+ wire T_141;
+ wire inexact;
+ wire T_143;
+ wire [31:0] T_144;
+ wire [1:0] T_145;
+ wire [2:0] T_146;
+ assign io_out = T_144;
+ assign io_intExceptionFlags = T_146;
+ assign sign = io_in[64];
+ assign exp = io_in[63:52];
+ assign fract = io_in[51:0];
+ assign T_12 = exp[11:9];
+ assign isZero = T_12 == 1'h0;
+ assign T_15 = exp[11:10];
+ assign T_16 = ~ T_15;
+ assign isSpecial = T_16 == 1'h0;
+ assign T_19 = exp[9];
+ assign isNaN = isSpecial & T_19;
+ assign notSpecial_magGeOne = exp[11];
+ assign T_22 = {notSpecial_magGeOne,fract};
+ assign T_23 = exp[4:0];
+ assign T_25 = notSpecial_magGeOne ? T_23 : 1'h0;
+ assign shiftedSig = T_22 << T_25;
+ assign unroundedInt = shiftedSig[83:52];
+ assign T_28 = shiftedSig[52:51];
+ assign T_29 = shiftedSig[50:0];
+ assign T_31 = T_29 != 1'h0;
+ assign roundBits = {T_28,T_31};
+ assign T_33 = roundBits[1:0];
+ assign T_35 = T_33 != 1'h0;
+ assign T_37 = isZero == 1'h0;
+ assign roundInexact = notSpecial_magGeOne ? T_35 : T_37;
+ assign T_39 = roundBits[2:1];
+ assign T_40 = ~ T_39;
+ assign T_42 = T_40 == 1'h0;
+ assign T_43 = roundBits[1:0];
+ assign T_44 = ~ T_43;
+ assign T_46 = T_44 == 1'h0;
+ assign T_47 = T_42 | T_46;
+ assign T_48 = exp[10:0];
+ assign T_49 = ~ T_48;
+ assign T_51 = T_49 == 1'h0;
+ assign T_52 = roundBits[1:0];
+ assign T_54 = T_52 != 1'h0;
+ assign T_56 = T_51 ? T_54 : 1'h0;
+ assign roundIncr_nearestEven = notSpecial_magGeOne ? T_47 : T_56;
+ assign T_58 = io_roundingMode == 2'h0;
+ assign T_59 = T_58 & roundIncr_nearestEven;
+ assign T_60 = io_roundingMode == 2'h2;
+ assign T_61 = sign & roundInexact;
+ assign T_62 = T_60 & T_61;
+ assign T_63 = T_59 | T_62;
+ assign T_64 = io_roundingMode == 2'h3;
+ assign T_66 = sign == 1'h0;
+ assign T_67 = T_66 & roundInexact;
+ assign T_68 = T_64 & T_67;
+ assign roundIncr = T_63 | T_68;
+ assign T_70 = ~ unroundedInt;
+ assign onesCompUnroundedInt = sign ? T_70 : unroundedInt;
+ assign T_72 = roundIncr ^ sign;
+ assign T_74 = onesCompUnroundedInt + 1'h1;
+ assign T_75 = T_74[31:0];
+ assign roundedInt = T_72 ? T_75 : onesCompUnroundedInt;
+ assign T_77 = unroundedInt[29:0];
+ assign T_78 = ~ T_77;
+ assign T_80 = T_78 == 1'h0;
+ assign roundCarryBut2 = T_80 & roundIncr;
+ assign posExp = exp[10:0];
+ assign T_84 = posExp >= 6'h20;
+ assign T_86 = posExp == 5'h1f;
+ assign T_88 = sign == 1'h0;
+ assign T_89 = unroundedInt[30:0];
+ assign T_91 = T_89 != 1'h0;
+ assign T_92 = T_88 | T_91;
+ assign T_93 = T_92 | roundIncr;
+ assign T_94 = T_86 & T_93;
+ assign T_95 = T_84 | T_94;
+ assign T_97 = sign == 1'h0;
+ assign T_99 = posExp == 5'h1e;
+ assign T_100 = T_97 & T_99;
+ assign T_101 = T_100 & roundCarryBut2;
+ assign T_102 = T_95 | T_101;
+ assign overflow_signed = notSpecial_magGeOne ? T_102 : 1'h0;
+ assign T_106 = posExp >= 6'h20;
+ assign T_107 = sign | T_106;
+ assign T_109 = posExp == 5'h1f;
+ assign T_110 = unroundedInt[30];
+ assign T_111 = T_109 & T_110;
+ assign T_112 = T_111 & roundCarryBut2;
+ assign T_113 = T_107 | T_112;
+ assign T_114 = sign & roundIncr;
+ assign overflow_unsigned = notSpecial_magGeOne ? T_113 : T_114;
+ assign overflow = io_signedOut ? overflow_signed : overflow_unsigned;
+ assign T_118 = isNaN == 1'h0;
+ assign excSign = sign & T_118;
+ assign T_120 = io_signedOut & excSign;
+ assign T_123 = T_120 ? 32'h80000000 : 1'h0;
+ assign T_125 = excSign == 1'h0;
+ assign T_126 = io_signedOut & T_125;
+ assign T_129 = T_126 ? 31'h7fffffff : 1'h0;
+ assign T_130 = T_123 | T_129;
+ assign T_132 = io_signedOut == 1'h0;
+ assign T_135 = T_132 ? 32'hffffffff : 1'h0;
+ assign excValue = T_130 | T_135;
+ assign T_138 = isSpecial == 1'h0;
+ assign T_139 = roundInexact & T_138;
+ assign T_141 = overflow == 1'h0;
+ assign inexact = T_139 & T_141;
+ assign T_143 = isSpecial | overflow;
+ assign T_144 = T_143 ? excValue : roundedInt;
+ assign T_145 = {overflow,inexact};
+ assign T_146 = {isSpecial,T_145};
+endmodule
+module FPToInt(
+ input clk,
+ input reset,
+ input io_in_valid,
+ input [4:0] io_in_bits_cmd,
+ input io_in_bits_ldst,
+ input io_in_bits_wen,
+ input io_in_bits_ren1,
+ input io_in_bits_ren2,
+ input io_in_bits_ren3,
+ input io_in_bits_swap12,
+ input io_in_bits_swap23,
+ input io_in_bits_single,
+ input io_in_bits_fromint,
+ input io_in_bits_toint,
+ input io_in_bits_fastpipe,
+ input io_in_bits_fma,
+ input io_in_bits_div,
+ input io_in_bits_sqrt,
+ input io_in_bits_round,
+ input io_in_bits_wflags,
+ input [2:0] io_in_bits_rm,
+ input [1:0] io_in_bits_typ,
+ input [64:0] io_in_bits_in1,
+ input [64:0] io_in_bits_in2,
+ input [64:0] io_in_bits_in3,
+ output [4:0] io_as_double_cmd,
+ output io_as_double_ldst,
+ output io_as_double_wen,
+ output io_as_double_ren1,
+ output io_as_double_ren2,
+ output io_as_double_ren3,
+ output io_as_double_swap12,
+ output io_as_double_swap23,
+ output io_as_double_single,
+ output io_as_double_fromint,
+ output io_as_double_toint,
+ output io_as_double_fastpipe,
+ output io_as_double_fma,
+ output io_as_double_div,
+ output io_as_double_sqrt,
+ output io_as_double_round,
+ output io_as_double_wflags,
+ output [2:0] io_as_double_rm,
+ output [1:0] io_as_double_typ,
+ output [64:0] io_as_double_in1,
+ output [64:0] io_as_double_in2,
+ output [64:0] io_as_double_in3,
+ output io_out_valid,
+ output io_out_bits_lt,
+ output [63:0] io_out_bits_store,
+ output [63:0] io_out_bits_toint,
+ output [4:0] io_out_bits_exc
+);
+ reg [4:0] in_cmd;
+ reg in_ldst;
+ reg in_wen;
+ reg in_ren1;
+ reg in_ren2;
+ reg in_ren3;
+ reg in_swap12;
+ reg in_swap23;
+ reg in_single;
+ reg in_fromint;
+ reg in_toint;
+ reg in_fastpipe;
+ reg in_fma;
+ reg in_div;
+ reg in_sqrt;
+ reg in_round;
+ reg in_wflags;
+ reg [2:0] in_rm;
+ reg [1:0] in_typ;
+ reg [64:0] in_in1;
+ reg [64:0] in_in2;
+ reg [64:0] in_in3;
+ reg valid;
+ wire T_233_clk;
+ wire T_233_reset;
+ wire [32:0] T_233_io_in;
+ wire [1:0] T_233_io_roundingMode;
+ wire [64:0] T_233_io_out;
+ wire [4:0] T_233_io_exceptionFlags;
+ wire T_235_clk;
+ wire T_235_reset;
+ wire [32:0] T_235_io_in;
+ wire [1:0] T_235_io_roundingMode;
+ wire [64:0] T_235_io_out;
+ wire [4:0] T_235_io_exceptionFlags;
+ wire T_238;
+ wire T_239;
+ wire [4:0] T_242;
+ wire T_243;
+ wire T_245;
+ wire T_246;
+ wire T_247;
+ wire [8:0] T_248;
+ wire [22:0] T_249;
+ wire [6:0] T_250;
+ wire T_252;
+ wire [2:0] T_253;
+ wire T_255;
+ wire [1:0] T_256;
+ wire T_258;
+ wire T_259;
+ wire T_260;
+ wire [1:0] T_261;
+ wire T_263;
+ wire T_265;
+ wire T_266;
+ wire [1:0] T_267;
+ wire T_269;
+ wire T_270;
+ wire [1:0] T_271;
+ wire T_273;
+ wire T_274;
+ wire T_275;
+ wire [4:0] T_277;
+ wire [5:0] T_278;
+ wire [4:0] T_279;
+ wire [23:0] T_281;
+ wire [23:0] T_282;
+ wire [22:0] T_283;
+ wire [7:0] T_284;
+ wire [8:0] T_286;
+ wire [7:0] T_287;
+ wire [8:0] T_289;
+ wire [7:0] T_290;
+ wire [7:0] T_291;
+ wire T_292;
+ wire [22:0] T_294;
+ wire [22:0] T_295;
+ wire [30:0] T_296;
+ wire [31:0] unrec_s;
+ wire T_298;
+ wire [11:0] T_299;
+ wire [51:0] T_300;
+ wire [9:0] T_301;
+ wire T_303;
+ wire [2:0] T_304;
+ wire T_306;
+ wire [1:0] T_307;
+ wire T_309;
+ wire T_310;
+ wire T_311;
+ wire [1:0] T_312;
+ wire T_314;
+ wire T_316;
+ wire T_317;
+ wire [1:0] T_318;
+ wire T_320;
+ wire T_321;
+ wire [1:0] T_322;
+ wire T_324;
+ wire T_325;
+ wire T_326;
+ wire [5:0] T_328;
+ wire [6:0] T_329;
+ wire [5:0] T_330;
+ wire [52:0] T_332;
+ wire [52:0] T_333;
+ wire [51:0] T_334;
+ wire [10:0] T_335;
+ wire [11:0] T_337;
+ wire [10:0] T_338;
+ wire [11:0] T_340;
+ wire [10:0] T_341;
+ wire [10:0] T_342;
+ wire T_343;
+ wire [51:0] T_345;
+ wire [51:0] T_346;
+ wire [62:0] T_347;
+ wire [63:0] unrec_d;
+ wire T_349;
+ wire [32:0] T_351;
+ wire [31:0] T_352;
+ wire [63:0] T_353;
+ wire [63:0] unrec_out;
+ wire T_355;
+ wire [8:0] T_356;
+ wire [22:0] T_357;
+ wire [2:0] T_358;
+ wire [1:0] T_359;
+ wire T_361;
+ wire [6:0] T_362;
+ wire T_364;
+ wire T_366;
+ wire T_368;
+ wire T_369;
+ wire T_370;
+ wire T_372;
+ wire T_374;
+ wire T_375;
+ wire T_377;
+ wire T_378;
+ wire T_380;
+ wire T_381;
+ wire T_383;
+ wire T_384;
+ wire [2:0] T_385;
+ wire T_387;
+ wire T_388;
+ wire T_390;
+ wire T_391;
+ wire T_392;
+ wire T_393;
+ wire T_395;
+ wire T_396;
+ wire T_398;
+ wire T_399;
+ wire T_401;
+ wire T_402;
+ wire T_404;
+ wire T_405;
+ wire T_406;
+ wire T_407;
+ wire T_408;
+ wire T_409;
+ wire [1:0] T_410;
+ wire [1:0] T_411;
+ wire [2:0] T_412;
+ wire [4:0] T_413;
+ wire [1:0] T_414;
+ wire [1:0] T_415;
+ wire [2:0] T_416;
+ wire [4:0] T_417;
+ wire [9:0] classify_s;
+ wire T_419;
+ wire [11:0] T_420;
+ wire [51:0] T_421;
+ wire [2:0] T_422;
+ wire [1:0] T_423;
+ wire T_425;
+ wire [9:0] T_426;
+ wire T_428;
+ wire T_430;
+ wire T_432;
+ wire T_433;
+ wire T_434;
+ wire T_436;
+ wire T_438;
+ wire T_439;
+ wire T_441;
+ wire T_442;
+ wire T_444;
+ wire T_445;
+ wire T_447;
+ wire T_448;
+ wire [2:0] T_449;
+ wire T_451;
+ wire T_452;
+ wire T_454;
+ wire T_455;
+ wire T_456;
+ wire T_457;
+ wire T_459;
+ wire T_460;
+ wire T_462;
+ wire T_463;
+ wire T_465;
+ wire T_466;
+ wire T_468;
+ wire T_469;
+ wire T_470;
+ wire T_471;
+ wire T_472;
+ wire T_473;
+ wire [1:0] T_474;
+ wire [1:0] T_475;
+ wire [2:0] T_476;
+ wire [4:0] T_477;
+ wire [1:0] T_478;
+ wire [1:0] T_479;
+ wire [2:0] T_480;
+ wire [4:0] T_481;
+ wire [9:0] classify_d;
+ wire [9:0] classify_out;
+ wire dcmp_clk;
+ wire dcmp_reset;
+ wire [64:0] dcmp_io_a;
+ wire [64:0] dcmp_io_b;
+ wire dcmp_io_signaling;
+ wire dcmp_io_lt;
+ wire dcmp_io_eq;
+ wire dcmp_io_gt;
+ wire [4:0] dcmp_io_exceptionFlags;
+ wire [2:0] T_486;
+ wire [1:0] T_487;
+ wire [2:0] T_488;
+ wire dcmp_out;
+ wire d2l_clk;
+ wire d2l_reset;
+ wire [64:0] d2l_io_in;
+ wire [1:0] d2l_io_roundingMode;
+ wire d2l_io_signedOut;
+ wire [63:0] d2l_io_out;
+ wire [2:0] d2l_io_intExceptionFlags;
+ wire d2w_clk;
+ wire d2w_reset;
+ wire [64:0] d2w_io_in;
+ wire [1:0] d2w_io_roundingMode;
+ wire d2w_io_signedOut;
+ wire [31:0] d2w_io_out;
+ wire [2:0] d2w_io_intExceptionFlags;
+ wire T_493;
+ wire T_494;
+ wire T_495;
+ wire T_496;
+ wire T_497;
+ wire [63:0] T_498;
+ wire [4:0] T_502;
+ wire T_503;
+ wire [4:0] T_506;
+ wire T_507;
+ wire T_508;
+ wire [63:0] T_509;
+ wire [31:0] T_510;
+ wire [63:0] T_511;
+ wire [63:0] T_512;
+ wire T_513;
+ wire [2:0] T_514;
+ wire [1:0] T_515;
+ wire T_517;
+ wire T_519;
+ wire [3:0] T_520;
+ wire [4:0] T_521;
+ RecFNToRecFN T_233 (
+ .clk(T_233_clk),
+ .reset(T_233_reset),
+ .io_in(T_233_io_in),
+ .io_roundingMode(T_233_io_roundingMode),
+ .io_out(T_233_io_out),
+ .io_exceptionFlags(T_233_io_exceptionFlags)
+ );
+ RecFNToRecFN T_235 (
+ .clk(T_235_clk),
+ .reset(T_235_reset),
+ .io_in(T_235_io_in),
+ .io_roundingMode(T_235_io_roundingMode),
+ .io_out(T_235_io_out),
+ .io_exceptionFlags(T_235_io_exceptionFlags)
+ );
+ CompareRecFN dcmp (
+ .clk(dcmp_clk),
+ .reset(dcmp_reset),
+ .io_a(dcmp_io_a),
+ .io_b(dcmp_io_b),
+ .io_signaling(dcmp_io_signaling),
+ .io_lt(dcmp_io_lt),
+ .io_eq(dcmp_io_eq),
+ .io_gt(dcmp_io_gt),
+ .io_exceptionFlags(dcmp_io_exceptionFlags)
+ );
+ RecFNToIN d2l (
+ .clk(d2l_clk),
+ .reset(d2l_reset),
+ .io_in(d2l_io_in),
+ .io_roundingMode(d2l_io_roundingMode),
+ .io_signedOut(d2l_io_signedOut),
+ .io_out(d2l_io_out),
+ .io_intExceptionFlags(d2l_io_intExceptionFlags)
+ );
+ RecFNToIN_118 d2w (
+ .clk(d2w_clk),
+ .reset(d2w_reset),
+ .io_in(d2w_io_in),
+ .io_roundingMode(d2w_io_roundingMode),
+ .io_signedOut(d2w_io_signedOut),
+ .io_out(d2w_io_out),
+ .io_intExceptionFlags(d2w_io_intExceptionFlags)
+ );
+ assign io_as_double_cmd = in_cmd;
+ assign io_as_double_ldst = in_ldst;
+ assign io_as_double_wen = in_wen;
+ assign io_as_double_ren1 = in_ren1;
+ assign io_as_double_ren2 = in_ren2;
+ assign io_as_double_ren3 = in_ren3;
+ assign io_as_double_swap12 = in_swap12;
+ assign io_as_double_swap23 = in_swap23;
+ assign io_as_double_single = in_single;
+ assign io_as_double_fromint = in_fromint;
+ assign io_as_double_toint = in_toint;
+ assign io_as_double_fastpipe = in_fastpipe;
+ assign io_as_double_fma = in_fma;
+ assign io_as_double_div = in_div;
+ assign io_as_double_sqrt = in_sqrt;
+ assign io_as_double_round = in_round;
+ assign io_as_double_wflags = in_wflags;
+ assign io_as_double_rm = in_rm;
+ assign io_as_double_typ = in_typ;
+ assign io_as_double_in1 = in_in1;
+ assign io_as_double_in2 = in_in2;
+ assign io_as_double_in3 = in_in3;
+ assign io_out_valid = valid;
+ assign io_out_bits_lt = dcmp_io_lt;
+ assign io_out_bits_store = unrec_out;
+ assign io_out_bits_toint = T_507 ? T_512 : T_503 ? dcmp_out : T_498;
+ assign io_out_bits_exc = T_507 ? T_521 : T_503 ? dcmp_io_exceptionFlags : 1'h0;
+ assign T_233_clk = clk;
+ assign T_233_reset = reset;
+ assign T_233_io_in = io_in_bits_in1;
+ assign T_233_io_roundingMode = 1'h0;
+ assign T_235_clk = clk;
+ assign T_235_reset = reset;
+ assign T_235_io_in = io_in_bits_in2;
+ assign T_235_io_roundingMode = 1'h0;
+ assign T_238 = io_in_bits_ldst == 1'h0;
+ assign T_239 = io_in_bits_single & T_238;
+ assign T_242 = io_in_bits_cmd & 4'hc;
+ assign T_243 = 4'hc == T_242;
+ assign T_245 = T_243 == 1'h0;
+ assign T_246 = T_239 & T_245;
+ assign T_247 = in_in1[32];
+ assign T_248 = in_in1[31:23];
+ assign T_249 = in_in1[22:0];
+ assign T_250 = T_248[6:0];
+ assign T_252 = T_250 < 2'h2;
+ assign T_253 = T_248[8:6];
+ assign T_255 = T_253 == 1'h1;
+ assign T_256 = T_248[8:7];
+ assign T_258 = T_256 == 1'h1;
+ assign T_259 = T_258 & T_252;
+ assign T_260 = T_255 | T_259;
+ assign T_261 = T_248[8:7];
+ assign T_263 = T_261 == 1'h1;
+ assign T_265 = T_252 == 1'h0;
+ assign T_266 = T_263 & T_265;
+ assign T_267 = T_248[8:7];
+ assign T_269 = T_267 == 2'h2;
+ assign T_270 = T_266 | T_269;
+ assign T_271 = T_248[8:7];
+ assign T_273 = T_271 == 2'h3;
+ assign T_274 = T_248[6];
+ assign T_275 = T_273 & T_274;
+ assign T_277 = T_248[4:0];
+ assign T_278 = 2'h2 - T_277;
+ assign T_279 = T_278[4:0];
+ assign T_281 = {1'h1,T_249};
+ assign T_282 = T_281 >> T_279;
+ assign T_283 = T_282[22:0];
+ assign T_284 = T_248[7:0];
+ assign T_286 = T_284 - 8'h81;
+ assign T_287 = T_286[7:0];
+ assign T_289 = 8'h0 - T_273;
+ assign T_290 = T_289[7:0];
+ assign T_291 = T_270 ? T_287 : T_290;
+ assign T_292 = T_270 | T_275;
+ assign T_294 = T_260 ? T_283 : 1'h0;
+ assign T_295 = T_292 ? T_249 : T_294;
+ assign T_296 = {T_291,T_295};
+ assign unrec_s = {T_247,T_296};
+ assign T_298 = in_in1[64];
+ assign T_299 = in_in1[63:52];
+ assign T_300 = in_in1[51:0];
+ assign T_301 = T_299[9:0];
+ assign T_303 = T_301 < 2'h2;
+ assign T_304 = T_299[11:9];
+ assign T_306 = T_304 == 1'h1;
+ assign T_307 = T_299[11:10];
+ assign T_309 = T_307 == 1'h1;
+ assign T_310 = T_309 & T_303;
+ assign T_311 = T_306 | T_310;
+ assign T_312 = T_299[11:10];
+ assign T_314 = T_312 == 1'h1;
+ assign T_316 = T_303 == 1'h0;
+ assign T_317 = T_314 & T_316;
+ assign T_318 = T_299[11:10];
+ assign T_320 = T_318 == 2'h2;
+ assign T_321 = T_317 | T_320;
+ assign T_322 = T_299[11:10];
+ assign T_324 = T_322 == 2'h3;
+ assign T_325 = T_299[9];
+ assign T_326 = T_324 & T_325;
+ assign T_328 = T_299[5:0];
+ assign T_329 = 2'h2 - T_328;
+ assign T_330 = T_329[5:0];
+ assign T_332 = {1'h1,T_300};
+ assign T_333 = T_332 >> T_330;
+ assign T_334 = T_333[51:0];
+ assign T_335 = T_299[10:0];
+ assign T_337 = T_335 - 11'h401;
+ assign T_338 = T_337[10:0];
+ assign T_340 = 11'h0 - T_324;
+ assign T_341 = T_340[10:0];
+ assign T_342 = T_321 ? T_338 : T_341;
+ assign T_343 = T_321 | T_326;
+ assign T_345 = T_311 ? T_334 : 1'h0;
+ assign T_346 = T_343 ? T_300 : T_345;
+ assign T_347 = {T_342,T_346};
+ assign unrec_d = {T_298,T_347};
+ assign T_349 = unrec_s[31];
+ assign T_351 = 32'h0 - T_349;
+ assign T_352 = T_351[31:0];
+ assign T_353 = {T_352,unrec_s};
+ assign unrec_out = in_single ? T_353 : unrec_d;
+ assign T_355 = in_in1[32];
+ assign T_356 = in_in1[31:23];
+ assign T_357 = in_in1[22:0];
+ assign T_358 = T_356[8:6];
+ assign T_359 = T_358[2:1];
+ assign T_361 = T_359 == 2'h3;
+ assign T_362 = T_356[6:0];
+ assign T_364 = T_362 < 2'h2;
+ assign T_366 = T_358 == 1'h1;
+ assign T_368 = T_359 == 1'h1;
+ assign T_369 = T_368 & T_364;
+ assign T_370 = T_366 | T_369;
+ assign T_372 = T_359 == 1'h1;
+ assign T_374 = T_364 == 1'h0;
+ assign T_375 = T_372 & T_374;
+ assign T_377 = T_359 == 2'h2;
+ assign T_378 = T_375 | T_377;
+ assign T_380 = T_358 == 1'h0;
+ assign T_381 = T_356[6];
+ assign T_383 = T_381 == 1'h0;
+ assign T_384 = T_361 & T_383;
+ assign T_385 = ~ T_358;
+ assign T_387 = T_385 == 1'h0;
+ assign T_388 = T_357[22];
+ assign T_390 = T_388 == 1'h0;
+ assign T_391 = T_387 & T_390;
+ assign T_392 = T_357[22];
+ assign T_393 = T_387 & T_392;
+ assign T_395 = T_355 == 1'h0;
+ assign T_396 = T_384 & T_395;
+ assign T_398 = T_355 == 1'h0;
+ assign T_399 = T_378 & T_398;
+ assign T_401 = T_355 == 1'h0;
+ assign T_402 = T_370 & T_401;
+ assign T_404 = T_355 == 1'h0;
+ assign T_405 = T_380 & T_404;
+ assign T_406 = T_380 & T_355;
+ assign T_407 = T_370 & T_355;
+ assign T_408 = T_378 & T_355;
+ assign T_409 = T_384 & T_355;
+ assign T_410 = {T_393,T_391};
+ assign T_411 = {T_399,T_402};
+ assign T_412 = {T_396,T_411};
+ assign T_413 = {T_410,T_412};
+ assign T_414 = {T_405,T_406};
+ assign T_415 = {T_408,T_409};
+ assign T_416 = {T_407,T_415};
+ assign T_417 = {T_414,T_416};
+ assign classify_s = {T_413,T_417};
+ assign T_419 = in_in1[64];
+ assign T_420 = in_in1[63:52];
+ assign T_421 = in_in1[51:0];
+ assign T_422 = T_420[11:9];
+ assign T_423 = T_422[2:1];
+ assign T_425 = T_423 == 2'h3;
+ assign T_426 = T_420[9:0];
+ assign T_428 = T_426 < 2'h2;
+ assign T_430 = T_422 == 1'h1;
+ assign T_432 = T_423 == 1'h1;
+ assign T_433 = T_432 & T_428;
+ assign T_434 = T_430 | T_433;
+ assign T_436 = T_423 == 1'h1;
+ assign T_438 = T_428 == 1'h0;
+ assign T_439 = T_436 & T_438;
+ assign T_441 = T_423 == 2'h2;
+ assign T_442 = T_439 | T_441;
+ assign T_444 = T_422 == 1'h0;
+ assign T_445 = T_420[9];
+ assign T_447 = T_445 == 1'h0;
+ assign T_448 = T_425 & T_447;
+ assign T_449 = ~ T_422;
+ assign T_451 = T_449 == 1'h0;
+ assign T_452 = T_421[51];
+ assign T_454 = T_452 == 1'h0;
+ assign T_455 = T_451 & T_454;
+ assign T_456 = T_421[51];
+ assign T_457 = T_451 & T_456;
+ assign T_459 = T_419 == 1'h0;
+ assign T_460 = T_448 & T_459;
+ assign T_462 = T_419 == 1'h0;
+ assign T_463 = T_442 & T_462;
+ assign T_465 = T_419 == 1'h0;
+ assign T_466 = T_434 & T_465;
+ assign T_468 = T_419 == 1'h0;
+ assign T_469 = T_444 & T_468;
+ assign T_470 = T_444 & T_419;
+ assign T_471 = T_434 & T_419;
+ assign T_472 = T_442 & T_419;
+ assign T_473 = T_448 & T_419;
+ assign T_474 = {T_457,T_455};
+ assign T_475 = {T_463,T_466};
+ assign T_476 = {T_460,T_475};
+ assign T_477 = {T_474,T_476};
+ assign T_478 = {T_469,T_470};
+ assign T_479 = {T_472,T_473};
+ assign T_480 = {T_471,T_479};
+ assign T_481 = {T_478,T_480};
+ assign classify_d = {T_477,T_481};
+ assign classify_out = in_single ? classify_s : classify_d;
+ assign dcmp_clk = clk;
+ assign dcmp_reset = reset;
+ assign dcmp_io_a = in_in1;
+ assign dcmp_io_b = in_in2;
+ assign dcmp_io_signaling = 1'h1;
+ assign T_486 = ~ in_rm;
+ assign T_487 = {dcmp_io_lt,dcmp_io_eq};
+ assign T_488 = T_486 & T_487;
+ assign dcmp_out = T_488 != 1'h0;
+ assign d2l_clk = clk;
+ assign d2l_reset = reset;
+ assign d2l_io_in = in_in1;
+ assign d2l_io_roundingMode = in_rm;
+ assign d2l_io_signedOut = T_494;
+ assign d2w_clk = clk;
+ assign d2w_reset = reset;
+ assign d2w_io_in = in_in1;
+ assign d2w_io_roundingMode = in_rm;
+ assign d2w_io_signedOut = T_496;
+ assign T_493 = in_typ[0];
+ assign T_494 = ~ T_493;
+ assign T_495 = in_typ[0];
+ assign T_496 = ~ T_495;
+ assign T_497 = in_rm[0];
+ assign T_498 = T_497 ? classify_out : unrec_out;
+ assign T_502 = in_cmd & 4'hc;
+ assign T_503 = 3'h4 == T_502;
+ assign T_506 = in_cmd & 4'hc;
+ assign T_507 = 4'h8 == T_506;
+ assign T_508 = in_typ[1];
+ assign T_509 = $signed(d2l_io_out);
+ assign T_510 = $signed(d2w_io_out);
+ assign T_511 = T_508 ? $signed(T_509) : $signed(T_510);
+ assign T_512 = $unsigned(T_511);
+ assign T_513 = in_typ[1];
+ assign T_514 = T_513 ? d2l_io_intExceptionFlags : d2w_io_intExceptionFlags;
+ assign T_515 = T_514[2:1];
+ assign T_517 = T_515 != 1'h0;
+ assign T_519 = T_514[0];
+ assign T_520 = {3'h0,T_519};
+ assign T_521 = {T_517,T_520};
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ in_cmd = {1{$random}};
+ in_ldst = {1{$random}};
+ in_wen = {1{$random}};
+ in_ren1 = {1{$random}};
+ in_ren2 = {1{$random}};
+ in_ren3 = {1{$random}};
+ in_swap12 = {1{$random}};
+ in_swap23 = {1{$random}};
+ in_single = {1{$random}};
+ in_fromint = {1{$random}};
+ in_toint = {1{$random}};
+ in_fastpipe = {1{$random}};
+ in_fma = {1{$random}};
+ in_div = {1{$random}};
+ in_sqrt = {1{$random}};
+ in_round = {1{$random}};
+ in_wflags = {1{$random}};
+ in_rm = {1{$random}};
+ in_typ = {1{$random}};
+ in_in1 = {3{$random}};
+ in_in2 = {3{$random}};
+ in_in3 = {3{$random}};
+ valid = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_cmd <= io_in_bits_cmd;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_ldst <= io_in_bits_ldst;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_wen <= io_in_bits_wen;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_ren1 <= io_in_bits_ren1;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_ren2 <= io_in_bits_ren2;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_ren3 <= io_in_bits_ren3;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_swap12 <= io_in_bits_swap12;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_swap23 <= io_in_bits_swap23;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_single <= io_in_bits_single;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_fromint <= io_in_bits_fromint;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_toint <= io_in_bits_toint;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_fastpipe <= io_in_bits_fastpipe;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_fma <= io_in_bits_fma;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_div <= io_in_bits_div;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_sqrt <= io_in_bits_sqrt;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_round <= io_in_bits_round;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_wflags <= io_in_bits_wflags;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_rm <= io_in_bits_rm;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_typ <= io_in_bits_typ;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ if(T_246) begin
+ in_in1 <= T_233_io_out;
+ end else begin
+ in_in1 <= io_in_bits_in1;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ if(T_246) begin
+ in_in2 <= T_235_io_out;
+ end else begin
+ in_in2 <= io_in_bits_in2;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ in_in3 <= io_in_bits_in3;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ valid <= io_in_valid;
+ end
+ end
+endmodule
+module INToRecFN(
+ input clk,
+ input reset,
+ input io_signedIn,
+ input [63:0] io_in,
+ input [1:0] io_roundingMode,
+ output [32:0] io_out,
+ output [4:0] io_exceptionFlags
+);
+ wire T_9;
+ wire sign;
+ wire [64:0] T_12;
+ wire [63:0] T_13;
+ wire [63:0] absIn;
+ wire [63:0] T_15;
+ wire T_16;
+ wire T_18;
+ wire T_20;
+ wire T_22;
+ wire T_24;
+ wire T_26;
+ wire T_28;
+ wire T_30;
+ wire T_32;
+ wire T_34;
+ wire T_36;
+ wire T_38;
+ wire T_40;
+ wire T_42;
+ wire T_44;
+ wire T_46;
+ wire T_48;
+ wire T_50;
+ wire T_52;
+ wire T_54;
+ wire T_56;
+ wire T_58;
+ wire T_60;
+ wire T_62;
+ wire T_64;
+ wire T_66;
+ wire T_68;
+ wire T_70;
+ wire T_72;
+ wire T_74;
+ wire T_76;
+ wire T_78;
+ wire T_80;
+ wire T_82;
+ wire T_84;
+ wire T_86;
+ wire T_88;
+ wire T_90;
+ wire T_92;
+ wire T_94;
+ wire T_96;
+ wire T_98;
+ wire T_100;
+ wire T_102;
+ wire T_104;
+ wire T_106;
+ wire T_108;
+ wire T_110;
+ wire T_112;
+ wire T_114;
+ wire T_116;
+ wire T_118;
+ wire T_120;
+ wire T_122;
+ wire T_124;
+ wire T_126;
+ wire T_128;
+ wire T_130;
+ wire T_132;
+ wire T_134;
+ wire T_136;
+ wire T_138;
+ wire T_140;
+ wire T_141;
+ wire [1:0] T_142;
+ wire [1:0] T_143;
+ wire [2:0] T_144;
+ wire [2:0] T_145;
+ wire [2:0] T_146;
+ wire [2:0] T_147;
+ wire [3:0] T_148;
+ wire [3:0] T_149;
+ wire [3:0] T_150;
+ wire [3:0] T_151;
+ wire [3:0] T_152;
+ wire [3:0] T_153;
+ wire [3:0] T_154;
+ wire [3:0] T_155;
+ wire [4:0] T_156;
+ wire [4:0] T_157;
+ wire [4:0] T_158;
+ wire [4:0] T_159;
+ wire [4:0] T_160;
+ wire [4:0] T_161;
+ wire [4:0] T_162;
+ wire [4:0] T_163;
+ wire [4:0] T_164;
+ wire [4:0] T_165;
+ wire [4:0] T_166;
+ wire [4:0] T_167;
+ wire [4:0] T_168;
+ wire [4:0] T_169;
+ wire [4:0] T_170;
+ wire [4:0] T_171;
+ wire [5:0] T_172;
+ wire [5:0] T_173;
+ wire [5:0] T_174;
+ wire [5:0] T_175;
+ wire [5:0] T_176;
+ wire [5:0] T_177;
+ wire [5:0] T_178;
+ wire [5:0] T_179;
+ wire [5:0] T_180;
+ wire [5:0] T_181;
+ wire [5:0] T_182;
+ wire [5:0] T_183;
+ wire [5:0] T_184;
+ wire [5:0] T_185;
+ wire [5:0] T_186;
+ wire [5:0] T_187;
+ wire [5:0] T_188;
+ wire [5:0] T_189;
+ wire [5:0] T_190;
+ wire [5:0] T_191;
+ wire [5:0] T_192;
+ wire [5:0] T_193;
+ wire [5:0] T_194;
+ wire [5:0] T_195;
+ wire [5:0] T_196;
+ wire [5:0] T_197;
+ wire [5:0] T_198;
+ wire [5:0] T_199;
+ wire [5:0] T_200;
+ wire [5:0] T_201;
+ wire [5:0] T_202;
+ wire [5:0] T_203;
+ wire [5:0] normCount;
+ wire [126:0] T_205;
+ wire [63:0] normAbsIn;
+ wire [1:0] T_208;
+ wire [38:0] T_209;
+ wire T_211;
+ wire [2:0] roundBits;
+ wire [1:0] T_213;
+ wire roundInexact;
+ wire T_216;
+ wire [1:0] T_217;
+ wire [1:0] T_218;
+ wire T_220;
+ wire [1:0] T_221;
+ wire [1:0] T_222;
+ wire T_224;
+ wire T_225;
+ wire T_227;
+ wire T_228;
+ wire T_229;
+ wire T_231;
+ wire T_232;
+ wire T_233;
+ wire T_235;
+ wire T_236;
+ wire T_238;
+ wire round;
+ wire [23:0] T_241;
+ wire [24:0] unroundedNorm;
+ wire [25:0] T_245;
+ wire [24:0] T_246;
+ wire [24:0] roundedNorm;
+ wire [5:0] T_249;
+ wire [6:0] unroundedExp;
+ wire [7:0] T_253;
+ wire T_254;
+ wire [8:0] T_255;
+ wire [7:0] roundedExp;
+ wire T_258;
+ wire [7:0] T_260;
+ wire [7:0] T_261;
+ wire [8:0] expOut;
+ wire overflow;
+ wire inexact;
+ wire [22:0] T_265;
+ wire [31:0] T_266;
+ wire [32:0] T_267;
+ wire [2:0] T_270;
+ wire [1:0] T_271;
+ wire [4:0] T_272;
+ assign io_out = T_267;
+ assign io_exceptionFlags = T_272;
+ assign T_9 = io_in[63];
+ assign sign = io_signedIn & T_9;
+ assign T_12 = 1'h0 - io_in;
+ assign T_13 = T_12[63:0];
+ assign absIn = sign ? T_13 : io_in;
+ assign T_15 = absIn << 0;
+ assign T_16 = T_15[63];
+ assign T_18 = T_15[62];
+ assign T_20 = T_15[61];
+ assign T_22 = T_15[60];
+ assign T_24 = T_15[59];
+ assign T_26 = T_15[58];
+ assign T_28 = T_15[57];
+ assign T_30 = T_15[56];
+ assign T_32 = T_15[55];
+ assign T_34 = T_15[54];
+ assign T_36 = T_15[53];
+ assign T_38 = T_15[52];
+ assign T_40 = T_15[51];
+ assign T_42 = T_15[50];
+ assign T_44 = T_15[49];
+ assign T_46 = T_15[48];
+ assign T_48 = T_15[47];
+ assign T_50 = T_15[46];
+ assign T_52 = T_15[45];
+ assign T_54 = T_15[44];
+ assign T_56 = T_15[43];
+ assign T_58 = T_15[42];
+ assign T_60 = T_15[41];
+ assign T_62 = T_15[40];
+ assign T_64 = T_15[39];
+ assign T_66 = T_15[38];
+ assign T_68 = T_15[37];
+ assign T_70 = T_15[36];
+ assign T_72 = T_15[35];
+ assign T_74 = T_15[34];
+ assign T_76 = T_15[33];
+ assign T_78 = T_15[32];
+ assign T_80 = T_15[31];
+ assign T_82 = T_15[30];
+ assign T_84 = T_15[29];
+ assign T_86 = T_15[28];
+ assign T_88 = T_15[27];
+ assign T_90 = T_15[26];
+ assign T_92 = T_15[25];
+ assign T_94 = T_15[24];
+ assign T_96 = T_15[23];
+ assign T_98 = T_15[22];
+ assign T_100 = T_15[21];
+ assign T_102 = T_15[20];
+ assign T_104 = T_15[19];
+ assign T_106 = T_15[18];
+ assign T_108 = T_15[17];
+ assign T_110 = T_15[16];
+ assign T_112 = T_15[15];
+ assign T_114 = T_15[14];
+ assign T_116 = T_15[13];
+ assign T_118 = T_15[12];
+ assign T_120 = T_15[11];
+ assign T_122 = T_15[10];
+ assign T_124 = T_15[9];
+ assign T_126 = T_15[8];
+ assign T_128 = T_15[7];
+ assign T_130 = T_15[6];
+ assign T_132 = T_15[5];
+ assign T_134 = T_15[4];
+ assign T_136 = T_15[3];
+ assign T_138 = T_15[2];
+ assign T_140 = T_15[1];
+ assign T_141 = T_140 << 0;
+ assign T_142 = T_138 ? 2'h2 : T_141;
+ assign T_143 = T_136 ? 2'h3 : T_142;
+ assign T_144 = T_134 ? 3'h4 : T_143;
+ assign T_145 = T_132 ? 3'h5 : T_144;
+ assign T_146 = T_130 ? 3'h6 : T_145;
+ assign T_147 = T_128 ? 3'h7 : T_146;
+ assign T_148 = T_126 ? 4'h8 : T_147;
+ assign T_149 = T_124 ? 4'h9 : T_148;
+ assign T_150 = T_122 ? 4'ha : T_149;
+ assign T_151 = T_120 ? 4'hb : T_150;
+ assign T_152 = T_118 ? 4'hc : T_151;
+ assign T_153 = T_116 ? 4'hd : T_152;
+ assign T_154 = T_114 ? 4'he : T_153;
+ assign T_155 = T_112 ? 4'hf : T_154;
+ assign T_156 = T_110 ? 5'h10 : T_155;
+ assign T_157 = T_108 ? 5'h11 : T_156;
+ assign T_158 = T_106 ? 5'h12 : T_157;
+ assign T_159 = T_104 ? 5'h13 : T_158;
+ assign T_160 = T_102 ? 5'h14 : T_159;
+ assign T_161 = T_100 ? 5'h15 : T_160;
+ assign T_162 = T_98 ? 5'h16 : T_161;
+ assign T_163 = T_96 ? 5'h17 : T_162;
+ assign T_164 = T_94 ? 5'h18 : T_163;
+ assign T_165 = T_92 ? 5'h19 : T_164;
+ assign T_166 = T_90 ? 5'h1a : T_165;
+ assign T_167 = T_88 ? 5'h1b : T_166;
+ assign T_168 = T_86 ? 5'h1c : T_167;
+ assign T_169 = T_84 ? 5'h1d : T_168;
+ assign T_170 = T_82 ? 5'h1e : T_169;
+ assign T_171 = T_80 ? 5'h1f : T_170;
+ assign T_172 = T_78 ? 6'h20 : T_171;
+ assign T_173 = T_76 ? 6'h21 : T_172;
+ assign T_174 = T_74 ? 6'h22 : T_173;
+ assign T_175 = T_72 ? 6'h23 : T_174;
+ assign T_176 = T_70 ? 6'h24 : T_175;
+ assign T_177 = T_68 ? 6'h25 : T_176;
+ assign T_178 = T_66 ? 6'h26 : T_177;
+ assign T_179 = T_64 ? 6'h27 : T_178;
+ assign T_180 = T_62 ? 6'h28 : T_179;
+ assign T_181 = T_60 ? 6'h29 : T_180;
+ assign T_182 = T_58 ? 6'h2a : T_181;
+ assign T_183 = T_56 ? 6'h2b : T_182;
+ assign T_184 = T_54 ? 6'h2c : T_183;
+ assign T_185 = T_52 ? 6'h2d : T_184;
+ assign T_186 = T_50 ? 6'h2e : T_185;
+ assign T_187 = T_48 ? 6'h2f : T_186;
+ assign T_188 = T_46 ? 6'h30 : T_187;
+ assign T_189 = T_44 ? 6'h31 : T_188;
+ assign T_190 = T_42 ? 6'h32 : T_189;
+ assign T_191 = T_40 ? 6'h33 : T_190;
+ assign T_192 = T_38 ? 6'h34 : T_191;
+ assign T_193 = T_36 ? 6'h35 : T_192;
+ assign T_194 = T_34 ? 6'h36 : T_193;
+ assign T_195 = T_32 ? 6'h37 : T_194;
+ assign T_196 = T_30 ? 6'h38 : T_195;
+ assign T_197 = T_28 ? 6'h39 : T_196;
+ assign T_198 = T_26 ? 6'h3a : T_197;
+ assign T_199 = T_24 ? 6'h3b : T_198;
+ assign T_200 = T_22 ? 6'h3c : T_199;
+ assign T_201 = T_20 ? 6'h3d : T_200;
+ assign T_202 = T_18 ? 6'h3e : T_201;
+ assign T_203 = T_16 ? 6'h3f : T_202;
+ assign normCount = ~ T_203;
+ assign T_205 = absIn << normCount;
+ assign normAbsIn = T_205[63:0];
+ assign T_208 = normAbsIn[40:39];
+ assign T_209 = normAbsIn[38:0];
+ assign T_211 = T_209 != 1'h0;
+ assign roundBits = {T_208,T_211};
+ assign T_213 = roundBits[1:0];
+ assign roundInexact = T_213 != 1'h0;
+ assign T_216 = io_roundingMode == 2'h0;
+ assign T_217 = roundBits[2:1];
+ assign T_218 = ~ T_217;
+ assign T_220 = T_218 == 1'h0;
+ assign T_221 = roundBits[1:0];
+ assign T_222 = ~ T_221;
+ assign T_224 = T_222 == 1'h0;
+ assign T_225 = T_220 | T_224;
+ assign T_227 = T_216 ? T_225 : 1'h0;
+ assign T_228 = io_roundingMode == 2'h2;
+ assign T_229 = sign & roundInexact;
+ assign T_231 = T_228 ? T_229 : 1'h0;
+ assign T_232 = T_227 | T_231;
+ assign T_233 = io_roundingMode == 2'h3;
+ assign T_235 = sign == 1'h0;
+ assign T_236 = T_235 & roundInexact;
+ assign T_238 = T_233 ? T_236 : 1'h0;
+ assign round = T_232 | T_238;
+ assign T_241 = normAbsIn[63:40];
+ assign unroundedNorm = {1'h0,T_241};
+ assign T_245 = unroundedNorm + 1'h1;
+ assign T_246 = T_245[24:0];
+ assign roundedNorm = round ? T_246 : unroundedNorm;
+ assign T_249 = ~ normCount;
+ assign unroundedExp = {1'h0,T_249};
+ assign T_253 = {1'h0,unroundedExp};
+ assign T_254 = roundedNorm[24];
+ assign T_255 = T_253 + T_254;
+ assign roundedExp = T_255[7:0];
+ assign T_258 = normAbsIn[63];
+ assign T_260 = roundedExp;
+ assign T_261 = 1'h0 ? 8'h80 : T_260;
+ assign expOut = {T_258,T_261};
+ assign overflow = 1'h0 | 1'h0;
+ assign inexact = roundInexact | overflow;
+ assign T_265 = roundedNorm[22:0];
+ assign T_266 = {expOut,T_265};
+ assign T_267 = {sign,T_266};
+ assign T_270 = {2'h0,overflow};
+ assign T_271 = {1'h0,inexact};
+ assign T_272 = {T_270,T_271};
+endmodule
+module INToRecFN_119(
+ input clk,
+ input reset,
+ input io_signedIn,
+ input [63:0] io_in,
+ input [1:0] io_roundingMode,
+ output [64:0] io_out,
+ output [4:0] io_exceptionFlags
+);
+ wire T_9;
+ wire sign;
+ wire [64:0] T_12;
+ wire [63:0] T_13;
+ wire [63:0] absIn;
+ wire [63:0] T_15;
+ wire T_16;
+ wire T_18;
+ wire T_20;
+ wire T_22;
+ wire T_24;
+ wire T_26;
+ wire T_28;
+ wire T_30;
+ wire T_32;
+ wire T_34;
+ wire T_36;
+ wire T_38;
+ wire T_40;
+ wire T_42;
+ wire T_44;
+ wire T_46;
+ wire T_48;
+ wire T_50;
+ wire T_52;
+ wire T_54;
+ wire T_56;
+ wire T_58;
+ wire T_60;
+ wire T_62;
+ wire T_64;
+ wire T_66;
+ wire T_68;
+ wire T_70;
+ wire T_72;
+ wire T_74;
+ wire T_76;
+ wire T_78;
+ wire T_80;
+ wire T_82;
+ wire T_84;
+ wire T_86;
+ wire T_88;
+ wire T_90;
+ wire T_92;
+ wire T_94;
+ wire T_96;
+ wire T_98;
+ wire T_100;
+ wire T_102;
+ wire T_104;
+ wire T_106;
+ wire T_108;
+ wire T_110;
+ wire T_112;
+ wire T_114;
+ wire T_116;
+ wire T_118;
+ wire T_120;
+ wire T_122;
+ wire T_124;
+ wire T_126;
+ wire T_128;
+ wire T_130;
+ wire T_132;
+ wire T_134;
+ wire T_136;
+ wire T_138;
+ wire T_140;
+ wire T_141;
+ wire [1:0] T_142;
+ wire [1:0] T_143;
+ wire [2:0] T_144;
+ wire [2:0] T_145;
+ wire [2:0] T_146;
+ wire [2:0] T_147;
+ wire [3:0] T_148;
+ wire [3:0] T_149;
+ wire [3:0] T_150;
+ wire [3:0] T_151;
+ wire [3:0] T_152;
+ wire [3:0] T_153;
+ wire [3:0] T_154;
+ wire [3:0] T_155;
+ wire [4:0] T_156;
+ wire [4:0] T_157;
+ wire [4:0] T_158;
+ wire [4:0] T_159;
+ wire [4:0] T_160;
+ wire [4:0] T_161;
+ wire [4:0] T_162;
+ wire [4:0] T_163;
+ wire [4:0] T_164;
+ wire [4:0] T_165;
+ wire [4:0] T_166;
+ wire [4:0] T_167;
+ wire [4:0] T_168;
+ wire [4:0] T_169;
+ wire [4:0] T_170;
+ wire [4:0] T_171;
+ wire [5:0] T_172;
+ wire [5:0] T_173;
+ wire [5:0] T_174;
+ wire [5:0] T_175;
+ wire [5:0] T_176;
+ wire [5:0] T_177;
+ wire [5:0] T_178;
+ wire [5:0] T_179;
+ wire [5:0] T_180;
+ wire [5:0] T_181;
+ wire [5:0] T_182;
+ wire [5:0] T_183;
+ wire [5:0] T_184;
+ wire [5:0] T_185;
+ wire [5:0] T_186;
+ wire [5:0] T_187;
+ wire [5:0] T_188;
+ wire [5:0] T_189;
+ wire [5:0] T_190;
+ wire [5:0] T_191;
+ wire [5:0] T_192;
+ wire [5:0] T_193;
+ wire [5:0] T_194;
+ wire [5:0] T_195;
+ wire [5:0] T_196;
+ wire [5:0] T_197;
+ wire [5:0] T_198;
+ wire [5:0] T_199;
+ wire [5:0] T_200;
+ wire [5:0] T_201;
+ wire [5:0] T_202;
+ wire [5:0] T_203;
+ wire [5:0] normCount;
+ wire [126:0] T_205;
+ wire [63:0] normAbsIn;
+ wire [1:0] T_208;
+ wire [9:0] T_209;
+ wire T_211;
+ wire [2:0] roundBits;
+ wire [1:0] T_213;
+ wire roundInexact;
+ wire T_216;
+ wire [1:0] T_217;
+ wire [1:0] T_218;
+ wire T_220;
+ wire [1:0] T_221;
+ wire [1:0] T_222;
+ wire T_224;
+ wire T_225;
+ wire T_227;
+ wire T_228;
+ wire T_229;
+ wire T_231;
+ wire T_232;
+ wire T_233;
+ wire T_235;
+ wire T_236;
+ wire T_238;
+ wire round;
+ wire [52:0] T_241;
+ wire [53:0] unroundedNorm;
+ wire [54:0] T_245;
+ wire [53:0] T_246;
+ wire [53:0] roundedNorm;
+ wire [5:0] T_249;
+ wire [9:0] unroundedExp;
+ wire [10:0] T_253;
+ wire T_254;
+ wire [11:0] T_255;
+ wire [10:0] roundedExp;
+ wire T_258;
+ wire [10:0] T_260;
+ wire [10:0] T_261;
+ wire [11:0] expOut;
+ wire overflow;
+ wire inexact;
+ wire [51:0] T_265;
+ wire [63:0] T_266;
+ wire [64:0] T_267;
+ wire [2:0] T_270;
+ wire [1:0] T_271;
+ wire [4:0] T_272;
+ assign io_out = T_267;
+ assign io_exceptionFlags = T_272;
+ assign T_9 = io_in[63];
+ assign sign = io_signedIn & T_9;
+ assign T_12 = 1'h0 - io_in;
+ assign T_13 = T_12[63:0];
+ assign absIn = sign ? T_13 : io_in;
+ assign T_15 = absIn << 0;
+ assign T_16 = T_15[63];
+ assign T_18 = T_15[62];
+ assign T_20 = T_15[61];
+ assign T_22 = T_15[60];
+ assign T_24 = T_15[59];
+ assign T_26 = T_15[58];
+ assign T_28 = T_15[57];
+ assign T_30 = T_15[56];
+ assign T_32 = T_15[55];
+ assign T_34 = T_15[54];
+ assign T_36 = T_15[53];
+ assign T_38 = T_15[52];
+ assign T_40 = T_15[51];
+ assign T_42 = T_15[50];
+ assign T_44 = T_15[49];
+ assign T_46 = T_15[48];
+ assign T_48 = T_15[47];
+ assign T_50 = T_15[46];
+ assign T_52 = T_15[45];
+ assign T_54 = T_15[44];
+ assign T_56 = T_15[43];
+ assign T_58 = T_15[42];
+ assign T_60 = T_15[41];
+ assign T_62 = T_15[40];
+ assign T_64 = T_15[39];
+ assign T_66 = T_15[38];
+ assign T_68 = T_15[37];
+ assign T_70 = T_15[36];
+ assign T_72 = T_15[35];
+ assign T_74 = T_15[34];
+ assign T_76 = T_15[33];
+ assign T_78 = T_15[32];
+ assign T_80 = T_15[31];
+ assign T_82 = T_15[30];
+ assign T_84 = T_15[29];
+ assign T_86 = T_15[28];
+ assign T_88 = T_15[27];
+ assign T_90 = T_15[26];
+ assign T_92 = T_15[25];
+ assign T_94 = T_15[24];
+ assign T_96 = T_15[23];
+ assign T_98 = T_15[22];
+ assign T_100 = T_15[21];
+ assign T_102 = T_15[20];
+ assign T_104 = T_15[19];
+ assign T_106 = T_15[18];
+ assign T_108 = T_15[17];
+ assign T_110 = T_15[16];
+ assign T_112 = T_15[15];
+ assign T_114 = T_15[14];
+ assign T_116 = T_15[13];
+ assign T_118 = T_15[12];
+ assign T_120 = T_15[11];
+ assign T_122 = T_15[10];
+ assign T_124 = T_15[9];
+ assign T_126 = T_15[8];
+ assign T_128 = T_15[7];
+ assign T_130 = T_15[6];
+ assign T_132 = T_15[5];
+ assign T_134 = T_15[4];
+ assign T_136 = T_15[3];
+ assign T_138 = T_15[2];
+ assign T_140 = T_15[1];
+ assign T_141 = T_140 << 0;
+ assign T_142 = T_138 ? 2'h2 : T_141;
+ assign T_143 = T_136 ? 2'h3 : T_142;
+ assign T_144 = T_134 ? 3'h4 : T_143;
+ assign T_145 = T_132 ? 3'h5 : T_144;
+ assign T_146 = T_130 ? 3'h6 : T_145;
+ assign T_147 = T_128 ? 3'h7 : T_146;
+ assign T_148 = T_126 ? 4'h8 : T_147;
+ assign T_149 = T_124 ? 4'h9 : T_148;
+ assign T_150 = T_122 ? 4'ha : T_149;
+ assign T_151 = T_120 ? 4'hb : T_150;
+ assign T_152 = T_118 ? 4'hc : T_151;
+ assign T_153 = T_116 ? 4'hd : T_152;
+ assign T_154 = T_114 ? 4'he : T_153;
+ assign T_155 = T_112 ? 4'hf : T_154;
+ assign T_156 = T_110 ? 5'h10 : T_155;
+ assign T_157 = T_108 ? 5'h11 : T_156;
+ assign T_158 = T_106 ? 5'h12 : T_157;
+ assign T_159 = T_104 ? 5'h13 : T_158;
+ assign T_160 = T_102 ? 5'h14 : T_159;
+ assign T_161 = T_100 ? 5'h15 : T_160;
+ assign T_162 = T_98 ? 5'h16 : T_161;
+ assign T_163 = T_96 ? 5'h17 : T_162;
+ assign T_164 = T_94 ? 5'h18 : T_163;
+ assign T_165 = T_92 ? 5'h19 : T_164;
+ assign T_166 = T_90 ? 5'h1a : T_165;
+ assign T_167 = T_88 ? 5'h1b : T_166;
+ assign T_168 = T_86 ? 5'h1c : T_167;
+ assign T_169 = T_84 ? 5'h1d : T_168;
+ assign T_170 = T_82 ? 5'h1e : T_169;
+ assign T_171 = T_80 ? 5'h1f : T_170;
+ assign T_172 = T_78 ? 6'h20 : T_171;
+ assign T_173 = T_76 ? 6'h21 : T_172;
+ assign T_174 = T_74 ? 6'h22 : T_173;
+ assign T_175 = T_72 ? 6'h23 : T_174;
+ assign T_176 = T_70 ? 6'h24 : T_175;
+ assign T_177 = T_68 ? 6'h25 : T_176;
+ assign T_178 = T_66 ? 6'h26 : T_177;
+ assign T_179 = T_64 ? 6'h27 : T_178;
+ assign T_180 = T_62 ? 6'h28 : T_179;
+ assign T_181 = T_60 ? 6'h29 : T_180;
+ assign T_182 = T_58 ? 6'h2a : T_181;
+ assign T_183 = T_56 ? 6'h2b : T_182;
+ assign T_184 = T_54 ? 6'h2c : T_183;
+ assign T_185 = T_52 ? 6'h2d : T_184;
+ assign T_186 = T_50 ? 6'h2e : T_185;
+ assign T_187 = T_48 ? 6'h2f : T_186;
+ assign T_188 = T_46 ? 6'h30 : T_187;
+ assign T_189 = T_44 ? 6'h31 : T_188;
+ assign T_190 = T_42 ? 6'h32 : T_189;
+ assign T_191 = T_40 ? 6'h33 : T_190;
+ assign T_192 = T_38 ? 6'h34 : T_191;
+ assign T_193 = T_36 ? 6'h35 : T_192;
+ assign T_194 = T_34 ? 6'h36 : T_193;
+ assign T_195 = T_32 ? 6'h37 : T_194;
+ assign T_196 = T_30 ? 6'h38 : T_195;
+ assign T_197 = T_28 ? 6'h39 : T_196;
+ assign T_198 = T_26 ? 6'h3a : T_197;
+ assign T_199 = T_24 ? 6'h3b : T_198;
+ assign T_200 = T_22 ? 6'h3c : T_199;
+ assign T_201 = T_20 ? 6'h3d : T_200;
+ assign T_202 = T_18 ? 6'h3e : T_201;
+ assign T_203 = T_16 ? 6'h3f : T_202;
+ assign normCount = ~ T_203;
+ assign T_205 = absIn << normCount;
+ assign normAbsIn = T_205[63:0];
+ assign T_208 = normAbsIn[11:10];
+ assign T_209 = normAbsIn[9:0];
+ assign T_211 = T_209 != 1'h0;
+ assign roundBits = {T_208,T_211};
+ assign T_213 = roundBits[1:0];
+ assign roundInexact = T_213 != 1'h0;
+ assign T_216 = io_roundingMode == 2'h0;
+ assign T_217 = roundBits[2:1];
+ assign T_218 = ~ T_217;
+ assign T_220 = T_218 == 1'h0;
+ assign T_221 = roundBits[1:0];
+ assign T_222 = ~ T_221;
+ assign T_224 = T_222 == 1'h0;
+ assign T_225 = T_220 | T_224;
+ assign T_227 = T_216 ? T_225 : 1'h0;
+ assign T_228 = io_roundingMode == 2'h2;
+ assign T_229 = sign & roundInexact;
+ assign T_231 = T_228 ? T_229 : 1'h0;
+ assign T_232 = T_227 | T_231;
+ assign T_233 = io_roundingMode == 2'h3;
+ assign T_235 = sign == 1'h0;
+ assign T_236 = T_235 & roundInexact;
+ assign T_238 = T_233 ? T_236 : 1'h0;
+ assign round = T_232 | T_238;
+ assign T_241 = normAbsIn[63:11];
+ assign unroundedNorm = {1'h0,T_241};
+ assign T_245 = unroundedNorm + 1'h1;
+ assign T_246 = T_245[53:0];
+ assign roundedNorm = round ? T_246 : unroundedNorm;
+ assign T_249 = ~ normCount;
+ assign unroundedExp = {4'h0,T_249};
+ assign T_253 = {1'h0,unroundedExp};
+ assign T_254 = roundedNorm[53];
+ assign T_255 = T_253 + T_254;
+ assign roundedExp = T_255[10:0];
+ assign T_258 = normAbsIn[63];
+ assign T_260 = roundedExp;
+ assign T_261 = 1'h0 ? 11'h400 : T_260;
+ assign expOut = {T_258,T_261};
+ assign overflow = 1'h0 | 1'h0;
+ assign inexact = roundInexact | overflow;
+ assign T_265 = roundedNorm[51:0];
+ assign T_266 = {expOut,T_265};
+ assign T_267 = {sign,T_266};
+ assign T_270 = {2'h0,overflow};
+ assign T_271 = {1'h0,inexact};
+ assign T_272 = {T_270,T_271};
+endmodule
+module IntToFP(
+ input clk,
+ input reset,
+ input io_in_valid,
+ input [4:0] io_in_bits_cmd,
+ input io_in_bits_ldst,
+ input io_in_bits_wen,
+ input io_in_bits_ren1,
+ input io_in_bits_ren2,
+ input io_in_bits_ren3,
+ input io_in_bits_swap12,
+ input io_in_bits_swap23,
+ input io_in_bits_single,
+ input io_in_bits_fromint,
+ input io_in_bits_toint,
+ input io_in_bits_fastpipe,
+ input io_in_bits_fma,
+ input io_in_bits_div,
+ input io_in_bits_sqrt,
+ input io_in_bits_round,
+ input io_in_bits_wflags,
+ input [2:0] io_in_bits_rm,
+ input [1:0] io_in_bits_typ,
+ input [64:0] io_in_bits_in1,
+ input [64:0] io_in_bits_in2,
+ input [64:0] io_in_bits_in3,
+ output io_out_valid,
+ output [64:0] io_out_bits_data,
+ output [4:0] io_out_bits_exc
+);
+ reg T_136;
+ reg [4:0] T_137_cmd;
+ reg T_137_ldst;
+ reg T_137_wen;
+ reg T_137_ren1;
+ reg T_137_ren2;
+ reg T_137_ren3;
+ reg T_137_swap12;
+ reg T_137_swap23;
+ reg T_137_single;
+ reg T_137_fromint;
+ reg T_137_toint;
+ reg T_137_fastpipe;
+ reg T_137_fma;
+ reg T_137_div;
+ reg T_137_sqrt;
+ reg T_137_round;
+ reg T_137_wflags;
+ reg [2:0] T_137_rm;
+ reg [1:0] T_137_typ;
+ reg [64:0] T_137_in1;
+ reg [64:0] T_137_in2;
+ reg [64:0] T_137_in3;
+ wire in_valid;
+ wire [4:0] in_bits_cmd;
+ wire in_bits_ldst;
+ wire in_bits_wen;
+ wire in_bits_ren1;
+ wire in_bits_ren2;
+ wire in_bits_ren3;
+ wire in_bits_swap12;
+ wire in_bits_swap23;
+ wire in_bits_single;
+ wire in_bits_fromint;
+ wire in_bits_toint;
+ wire in_bits_fastpipe;
+ wire in_bits_fma;
+ wire in_bits_div;
+ wire in_bits_sqrt;
+ wire in_bits_round;
+ wire in_bits_wflags;
+ wire [2:0] in_bits_rm;
+ wire [1:0] in_bits_typ;
+ wire [64:0] in_bits_in1;
+ wire [64:0] in_bits_in2;
+ wire [64:0] in_bits_in3;
+ wire [64:0] mux_data;
+ wire [4:0] mux_exc;
+ wire T_263;
+ wire [10:0] T_264;
+ wire [51:0] T_265;
+ wire T_267;
+ wire T_269;
+ wire T_270;
+ wire [63:0] T_271;
+ wire T_272;
+ wire T_274;
+ wire T_276;
+ wire T_278;
+ wire T_280;
+ wire T_282;
+ wire T_284;
+ wire T_286;
+ wire T_288;
+ wire T_290;
+ wire T_292;
+ wire T_294;
+ wire T_296;
+ wire T_298;
+ wire T_300;
+ wire T_302;
+ wire T_304;
+ wire T_306;
+ wire T_308;
+ wire T_310;
+ wire T_312;
+ wire T_314;
+ wire T_316;
+ wire T_318;
+ wire T_320;
+ wire T_322;
+ wire T_324;
+ wire T_326;
+ wire T_328;
+ wire T_330;
+ wire T_332;
+ wire T_334;
+ wire T_336;
+ wire T_338;
+ wire T_340;
+ wire T_342;
+ wire T_344;
+ wire T_346;
+ wire T_348;
+ wire T_350;
+ wire T_352;
+ wire T_354;
+ wire T_356;
+ wire T_358;
+ wire T_360;
+ wire T_362;
+ wire T_364;
+ wire T_366;
+ wire T_368;
+ wire T_370;
+ wire T_372;
+ wire T_374;
+ wire T_376;
+ wire T_378;
+ wire T_380;
+ wire T_382;
+ wire T_384;
+ wire T_386;
+ wire T_388;
+ wire T_390;
+ wire T_392;
+ wire T_394;
+ wire T_396;
+ wire T_397;
+ wire [1:0] T_398;
+ wire [1:0] T_399;
+ wire [2:0] T_400;
+ wire [2:0] T_401;
+ wire [2:0] T_402;
+ wire [2:0] T_403;
+ wire [3:0] T_404;
+ wire [3:0] T_405;
+ wire [3:0] T_406;
+ wire [3:0] T_407;
+ wire [3:0] T_408;
+ wire [3:0] T_409;
+ wire [3:0] T_410;
+ wire [3:0] T_411;
+ wire [4:0] T_412;
+ wire [4:0] T_413;
+ wire [4:0] T_414;
+ wire [4:0] T_415;
+ wire [4:0] T_416;
+ wire [4:0] T_417;
+ wire [4:0] T_418;
+ wire [4:0] T_419;
+ wire [4:0] T_420;
+ wire [4:0] T_421;
+ wire [4:0] T_422;
+ wire [4:0] T_423;
+ wire [4:0] T_424;
+ wire [4:0] T_425;
+ wire [4:0] T_426;
+ wire [4:0] T_427;
+ wire [5:0] T_428;
+ wire [5:0] T_429;
+ wire [5:0] T_430;
+ wire [5:0] T_431;
+ wire [5:0] T_432;
+ wire [5:0] T_433;
+ wire [5:0] T_434;
+ wire [5:0] T_435;
+ wire [5:0] T_436;
+ wire [5:0] T_437;
+ wire [5:0] T_438;
+ wire [5:0] T_439;
+ wire [5:0] T_440;
+ wire [5:0] T_441;
+ wire [5:0] T_442;
+ wire [5:0] T_443;
+ wire [5:0] T_444;
+ wire [5:0] T_445;
+ wire [5:0] T_446;
+ wire [5:0] T_447;
+ wire [5:0] T_448;
+ wire [5:0] T_449;
+ wire [5:0] T_450;
+ wire [5:0] T_451;
+ wire [5:0] T_452;
+ wire [5:0] T_453;
+ wire [5:0] T_454;
+ wire [5:0] T_455;
+ wire [5:0] T_456;
+ wire [5:0] T_457;
+ wire [5:0] T_458;
+ wire [5:0] T_459;
+ wire [5:0] T_460;
+ wire [114:0] T_461;
+ wire [50:0] T_462;
+ wire [51:0] T_464;
+ wire [12:0] T_467;
+ wire [11:0] T_468;
+ wire [11:0] T_469;
+ wire [11:0] T_470;
+ wire [1:0] T_474;
+ wire [10:0] T_475;
+ wire [12:0] T_476;
+ wire [11:0] T_477;
+ wire [1:0] T_478;
+ wire T_480;
+ wire T_482;
+ wire T_483;
+ wire [3:0] T_485;
+ wire [2:0] T_486;
+ wire [11:0] T_487;
+ wire [11:0] T_488;
+ wire [11:0] T_489;
+ wire [9:0] T_490;
+ wire [11:0] T_491;
+ wire [51:0] T_492;
+ wire [63:0] T_493;
+ wire [64:0] T_494;
+ wire T_496;
+ wire [7:0] T_497;
+ wire [22:0] T_498;
+ wire T_500;
+ wire T_502;
+ wire T_503;
+ wire [31:0] T_504;
+ wire T_505;
+ wire T_507;
+ wire T_509;
+ wire T_511;
+ wire T_513;
+ wire T_515;
+ wire T_517;
+ wire T_519;
+ wire T_521;
+ wire T_523;
+ wire T_525;
+ wire T_527;
+ wire T_529;
+ wire T_531;
+ wire T_533;
+ wire T_535;
+ wire T_537;
+ wire T_539;
+ wire T_541;
+ wire T_543;
+ wire T_545;
+ wire T_547;
+ wire T_549;
+ wire T_551;
+ wire T_553;
+ wire T_555;
+ wire T_557;
+ wire T_559;
+ wire T_561;
+ wire T_563;
+ wire T_565;
+ wire T_566;
+ wire [1:0] T_567;
+ wire [1:0] T_568;
+ wire [2:0] T_569;
+ wire [2:0] T_570;
+ wire [2:0] T_571;
+ wire [2:0] T_572;
+ wire [3:0] T_573;
+ wire [3:0] T_574;
+ wire [3:0] T_575;
+ wire [3:0] T_576;
+ wire [3:0] T_577;
+ wire [3:0] T_578;
+ wire [3:0] T_579;
+ wire [3:0] T_580;
+ wire [4:0] T_581;
+ wire [4:0] T_582;
+ wire [4:0] T_583;
+ wire [4:0] T_584;
+ wire [4:0] T_585;
+ wire [4:0] T_586;
+ wire [4:0] T_587;
+ wire [4:0] T_588;
+ wire [4:0] T_589;
+ wire [4:0] T_590;
+ wire [4:0] T_591;
+ wire [4:0] T_592;
+ wire [4:0] T_593;
+ wire [4:0] T_594;
+ wire [4:0] T_595;
+ wire [4:0] T_596;
+ wire [4:0] T_597;
+ wire [53:0] T_598;
+ wire [21:0] T_599;
+ wire [22:0] T_601;
+ wire [9:0] T_604;
+ wire [8:0] T_605;
+ wire [8:0] T_606;
+ wire [8:0] T_607;
+ wire [1:0] T_611;
+ wire [7:0] T_612;
+ wire [9:0] T_613;
+ wire [8:0] T_614;
+ wire [1:0] T_615;
+ wire T_617;
+ wire T_619;
+ wire T_620;
+ wire [3:0] T_622;
+ wire [2:0] T_623;
+ wire [8:0] T_624;
+ wire [8:0] T_625;
+ wire [8:0] T_626;
+ wire [6:0] T_627;
+ wire [8:0] T_628;
+ wire [22:0] T_629;
+ wire [31:0] T_630;
+ wire [32:0] T_631;
+ wire [31:0] GEN_0;
+ wire [31:0] T_632;
+ wire [64:0] T_633;
+ wire T_634;
+ wire [64:0] T_635;
+ wire T_636;
+ wire [31:0] T_637;
+ wire [32:0] T_638;
+ wire [31:0] T_639;
+ wire [31:0] T_640;
+ wire [32:0] T_641;
+ wire [64:0] longValue;
+ wire l2s_clk;
+ wire l2s_reset;
+ wire l2s_io_signedIn;
+ wire [63:0] l2s_io_in;
+ wire [1:0] l2s_io_roundingMode;
+ wire [32:0] l2s_io_out;
+ wire [4:0] l2s_io_exceptionFlags;
+ wire T_644;
+ wire T_645;
+ wire [64:0] T_646;
+ wire l2d_clk;
+ wire l2d_reset;
+ wire l2d_io_signedIn;
+ wire [63:0] l2d_io_in;
+ wire [1:0] l2d_io_roundingMode;
+ wire [64:0] l2d_io_out;
+ wire [4:0] l2d_io_exceptionFlags;
+ wire T_648;
+ wire T_649;
+ wire [64:0] T_650;
+ wire [4:0] T_653;
+ wire T_654;
+ wire [31:0] GEN_1;
+ wire [31:0] T_656;
+ wire [64:0] T_657;
+ wire T_659;
+ reg T_662;
+ reg [64:0] T_663_data;
+ reg [4:0] T_663_exc;
+ reg T_668;
+ reg [64:0] T_669_data;
+ reg [4:0] T_669_exc;
+ wire T_680_valid;
+ wire [64:0] T_680_bits_data;
+ wire [4:0] T_680_bits_exc;
+ INToRecFN l2s (
+ .clk(l2s_clk),
+ .reset(l2s_reset),
+ .io_signedIn(l2s_io_signedIn),
+ .io_in(l2s_io_in),
+ .io_roundingMode(l2s_io_roundingMode),
+ .io_out(l2s_io_out),
+ .io_exceptionFlags(l2s_io_exceptionFlags)
+ );
+ INToRecFN_119 l2d (
+ .clk(l2d_clk),
+ .reset(l2d_reset),
+ .io_signedIn(l2d_io_signedIn),
+ .io_in(l2d_io_in),
+ .io_roundingMode(l2d_io_roundingMode),
+ .io_out(l2d_io_out),
+ .io_exceptionFlags(l2d_io_exceptionFlags)
+ );
+ assign io_out_valid = T_680_valid;
+ assign io_out_bits_data = T_680_bits_data;
+ assign io_out_bits_exc = T_680_bits_exc;
+ assign in_valid = T_136;
+ assign in_bits_cmd = T_137_cmd;
+ assign in_bits_ldst = T_137_ldst;
+ assign in_bits_wen = T_137_wen;
+ assign in_bits_ren1 = T_137_ren1;
+ assign in_bits_ren2 = T_137_ren2;
+ assign in_bits_ren3 = T_137_ren3;
+ assign in_bits_swap12 = T_137_swap12;
+ assign in_bits_swap23 = T_137_swap23;
+ assign in_bits_single = T_137_single;
+ assign in_bits_fromint = T_137_fromint;
+ assign in_bits_toint = T_137_toint;
+ assign in_bits_fastpipe = T_137_fastpipe;
+ assign in_bits_fma = T_137_fma;
+ assign in_bits_div = T_137_div;
+ assign in_bits_sqrt = T_137_sqrt;
+ assign in_bits_round = T_137_round;
+ assign in_bits_wflags = T_137_wflags;
+ assign in_bits_rm = T_137_rm;
+ assign in_bits_typ = T_137_typ;
+ assign in_bits_in1 = T_137_in1;
+ assign in_bits_in2 = T_137_in2;
+ assign in_bits_in3 = T_137_in3;
+ assign mux_data = T_654 ? T_659 ? l2d_io_out : in_bits_single ? T_657 : in_bits_single ? T_633 : T_494 : in_bits_single ? T_633 : T_494;
+ assign mux_exc = T_654 ? T_659 ? l2d_io_exceptionFlags : in_bits_single ? l2s_io_exceptionFlags : 1'h0 : 1'h0;
+ assign T_263 = in_bits_in1[63];
+ assign T_264 = in_bits_in1[62:52];
+ assign T_265 = in_bits_in1[51:0];
+ assign T_267 = T_264 == 1'h0;
+ assign T_269 = T_265 == 1'h0;
+ assign T_270 = T_267 & T_269;
+ assign T_271 = T_265 << 12;
+ assign T_272 = T_271[63];
+ assign T_274 = T_271[62];
+ assign T_276 = T_271[61];
+ assign T_278 = T_271[60];
+ assign T_280 = T_271[59];
+ assign T_282 = T_271[58];
+ assign T_284 = T_271[57];
+ assign T_286 = T_271[56];
+ assign T_288 = T_271[55];
+ assign T_290 = T_271[54];
+ assign T_292 = T_271[53];
+ assign T_294 = T_271[52];
+ assign T_296 = T_271[51];
+ assign T_298 = T_271[50];
+ assign T_300 = T_271[49];
+ assign T_302 = T_271[48];
+ assign T_304 = T_271[47];
+ assign T_306 = T_271[46];
+ assign T_308 = T_271[45];
+ assign T_310 = T_271[44];
+ assign T_312 = T_271[43];
+ assign T_314 = T_271[42];
+ assign T_316 = T_271[41];
+ assign T_318 = T_271[40];
+ assign T_320 = T_271[39];
+ assign T_322 = T_271[38];
+ assign T_324 = T_271[37];
+ assign T_326 = T_271[36];
+ assign T_328 = T_271[35];
+ assign T_330 = T_271[34];
+ assign T_332 = T_271[33];
+ assign T_334 = T_271[32];
+ assign T_336 = T_271[31];
+ assign T_338 = T_271[30];
+ assign T_340 = T_271[29];
+ assign T_342 = T_271[28];
+ assign T_344 = T_271[27];
+ assign T_346 = T_271[26];
+ assign T_348 = T_271[25];
+ assign T_350 = T_271[24];
+ assign T_352 = T_271[23];
+ assign T_354 = T_271[22];
+ assign T_356 = T_271[21];
+ assign T_358 = T_271[20];
+ assign T_360 = T_271[19];
+ assign T_362 = T_271[18];
+ assign T_364 = T_271[17];
+ assign T_366 = T_271[16];
+ assign T_368 = T_271[15];
+ assign T_370 = T_271[14];
+ assign T_372 = T_271[13];
+ assign T_374 = T_271[12];
+ assign T_376 = T_271[11];
+ assign T_378 = T_271[10];
+ assign T_380 = T_271[9];
+ assign T_382 = T_271[8];
+ assign T_384 = T_271[7];
+ assign T_386 = T_271[6];
+ assign T_388 = T_271[5];
+ assign T_390 = T_271[4];
+ assign T_392 = T_271[3];
+ assign T_394 = T_271[2];
+ assign T_396 = T_271[1];
+ assign T_397 = T_396 << 0;
+ assign T_398 = T_394 ? 2'h2 : T_397;
+ assign T_399 = T_392 ? 2'h3 : T_398;
+ assign T_400 = T_390 ? 3'h4 : T_399;
+ assign T_401 = T_388 ? 3'h5 : T_400;
+ assign T_402 = T_386 ? 3'h6 : T_401;
+ assign T_403 = T_384 ? 3'h7 : T_402;
+ assign T_404 = T_382 ? 4'h8 : T_403;
+ assign T_405 = T_380 ? 4'h9 : T_404;
+ assign T_406 = T_378 ? 4'ha : T_405;
+ assign T_407 = T_376 ? 4'hb : T_406;
+ assign T_408 = T_374 ? 4'hc : T_407;
+ assign T_409 = T_372 ? 4'hd : T_408;
+ assign T_410 = T_370 ? 4'he : T_409;
+ assign T_411 = T_368 ? 4'hf : T_410;
+ assign T_412 = T_366 ? 5'h10 : T_411;
+ assign T_413 = T_364 ? 5'h11 : T_412;
+ assign T_414 = T_362 ? 5'h12 : T_413;
+ assign T_415 = T_360 ? 5'h13 : T_414;
+ assign T_416 = T_358 ? 5'h14 : T_415;
+ assign T_417 = T_356 ? 5'h15 : T_416;
+ assign T_418 = T_354 ? 5'h16 : T_417;
+ assign T_419 = T_352 ? 5'h17 : T_418;
+ assign T_420 = T_350 ? 5'h18 : T_419;
+ assign T_421 = T_348 ? 5'h19 : T_420;
+ assign T_422 = T_346 ? 5'h1a : T_421;
+ assign T_423 = T_344 ? 5'h1b : T_422;
+ assign T_424 = T_342 ? 5'h1c : T_423;
+ assign T_425 = T_340 ? 5'h1d : T_424;
+ assign T_426 = T_338 ? 5'h1e : T_425;
+ assign T_427 = T_336 ? 5'h1f : T_426;
+ assign T_428 = T_334 ? 6'h20 : T_427;
+ assign T_429 = T_332 ? 6'h21 : T_428;
+ assign T_430 = T_330 ? 6'h22 : T_429;
+ assign T_431 = T_328 ? 6'h23 : T_430;
+ assign T_432 = T_326 ? 6'h24 : T_431;
+ assign T_433 = T_324 ? 6'h25 : T_432;
+ assign T_434 = T_322 ? 6'h26 : T_433;
+ assign T_435 = T_320 ? 6'h27 : T_434;
+ assign T_436 = T_318 ? 6'h28 : T_435;
+ assign T_437 = T_316 ? 6'h29 : T_436;
+ assign T_438 = T_314 ? 6'h2a : T_437;
+ assign T_439 = T_312 ? 6'h2b : T_438;
+ assign T_440 = T_310 ? 6'h2c : T_439;
+ assign T_441 = T_308 ? 6'h2d : T_440;
+ assign T_442 = T_306 ? 6'h2e : T_441;
+ assign T_443 = T_304 ? 6'h2f : T_442;
+ assign T_444 = T_302 ? 6'h30 : T_443;
+ assign T_445 = T_300 ? 6'h31 : T_444;
+ assign T_446 = T_298 ? 6'h32 : T_445;
+ assign T_447 = T_296 ? 6'h33 : T_446;
+ assign T_448 = T_294 ? 6'h34 : T_447;
+ assign T_449 = T_292 ? 6'h35 : T_448;
+ assign T_450 = T_290 ? 6'h36 : T_449;
+ assign T_451 = T_288 ? 6'h37 : T_450;
+ assign T_452 = T_286 ? 6'h38 : T_451;
+ assign T_453 = T_284 ? 6'h39 : T_452;
+ assign T_454 = T_282 ? 6'h3a : T_453;
+ assign T_455 = T_280 ? 6'h3b : T_454;
+ assign T_456 = T_278 ? 6'h3c : T_455;
+ assign T_457 = T_276 ? 6'h3d : T_456;
+ assign T_458 = T_274 ? 6'h3e : T_457;
+ assign T_459 = T_272 ? 6'h3f : T_458;
+ assign T_460 = ~ T_459;
+ assign T_461 = T_265 << T_460;
+ assign T_462 = T_461[50:0];
+ assign T_464 = {T_462,1'h0};
+ assign T_467 = 12'h0 - 1'h1;
+ assign T_468 = T_467[11:0];
+ assign T_469 = T_460 ^ T_468;
+ assign T_470 = T_267 ? T_469 : T_264;
+ assign T_474 = T_267 ? 2'h2 : 1'h1;
+ assign T_475 = 11'h400 | T_474;
+ assign T_476 = T_470 + T_475;
+ assign T_477 = T_476[11:0];
+ assign T_478 = T_477[11:10];
+ assign T_480 = T_478 == 2'h3;
+ assign T_482 = T_269 == 1'h0;
+ assign T_483 = T_480 & T_482;
+ assign T_485 = 3'h0 - T_270;
+ assign T_486 = T_485[2:0];
+ assign T_487 = T_486 << 9;
+ assign T_488 = ~ T_487;
+ assign T_489 = T_477 & T_488;
+ assign T_490 = T_483 << 9;
+ assign T_491 = T_489 | T_490;
+ assign T_492 = T_267 ? T_464 : T_265;
+ assign T_493 = {T_491,T_492};
+ assign T_494 = {T_263,T_493};
+ assign T_496 = in_bits_in1[31];
+ assign T_497 = in_bits_in1[30:23];
+ assign T_498 = in_bits_in1[22:0];
+ assign T_500 = T_497 == 1'h0;
+ assign T_502 = T_498 == 1'h0;
+ assign T_503 = T_500 & T_502;
+ assign T_504 = T_498 << 9;
+ assign T_505 = T_504[31];
+ assign T_507 = T_504[30];
+ assign T_509 = T_504[29];
+ assign T_511 = T_504[28];
+ assign T_513 = T_504[27];
+ assign T_515 = T_504[26];
+ assign T_517 = T_504[25];
+ assign T_519 = T_504[24];
+ assign T_521 = T_504[23];
+ assign T_523 = T_504[22];
+ assign T_525 = T_504[21];
+ assign T_527 = T_504[20];
+ assign T_529 = T_504[19];
+ assign T_531 = T_504[18];
+ assign T_533 = T_504[17];
+ assign T_535 = T_504[16];
+ assign T_537 = T_504[15];
+ assign T_539 = T_504[14];
+ assign T_541 = T_504[13];
+ assign T_543 = T_504[12];
+ assign T_545 = T_504[11];
+ assign T_547 = T_504[10];
+ assign T_549 = T_504[9];
+ assign T_551 = T_504[8];
+ assign T_553 = T_504[7];
+ assign T_555 = T_504[6];
+ assign T_557 = T_504[5];
+ assign T_559 = T_504[4];
+ assign T_561 = T_504[3];
+ assign T_563 = T_504[2];
+ assign T_565 = T_504[1];
+ assign T_566 = T_565 << 0;
+ assign T_567 = T_563 ? 2'h2 : T_566;
+ assign T_568 = T_561 ? 2'h3 : T_567;
+ assign T_569 = T_559 ? 3'h4 : T_568;
+ assign T_570 = T_557 ? 3'h5 : T_569;
+ assign T_571 = T_555 ? 3'h6 : T_570;
+ assign T_572 = T_553 ? 3'h7 : T_571;
+ assign T_573 = T_551 ? 4'h8 : T_572;
+ assign T_574 = T_549 ? 4'h9 : T_573;
+ assign T_575 = T_547 ? 4'ha : T_574;
+ assign T_576 = T_545 ? 4'hb : T_575;
+ assign T_577 = T_543 ? 4'hc : T_576;
+ assign T_578 = T_541 ? 4'hd : T_577;
+ assign T_579 = T_539 ? 4'he : T_578;
+ assign T_580 = T_537 ? 4'hf : T_579;
+ assign T_581 = T_535 ? 5'h10 : T_580;
+ assign T_582 = T_533 ? 5'h11 : T_581;
+ assign T_583 = T_531 ? 5'h12 : T_582;
+ assign T_584 = T_529 ? 5'h13 : T_583;
+ assign T_585 = T_527 ? 5'h14 : T_584;
+ assign T_586 = T_525 ? 5'h15 : T_585;
+ assign T_587 = T_523 ? 5'h16 : T_586;
+ assign T_588 = T_521 ? 5'h17 : T_587;
+ assign T_589 = T_519 ? 5'h18 : T_588;
+ assign T_590 = T_517 ? 5'h19 : T_589;
+ assign T_591 = T_515 ? 5'h1a : T_590;
+ assign T_592 = T_513 ? 5'h1b : T_591;
+ assign T_593 = T_511 ? 5'h1c : T_592;
+ assign T_594 = T_509 ? 5'h1d : T_593;
+ assign T_595 = T_507 ? 5'h1e : T_594;
+ assign T_596 = T_505 ? 5'h1f : T_595;
+ assign T_597 = ~ T_596;
+ assign T_598 = T_498 << T_597;
+ assign T_599 = T_598[21:0];
+ assign T_601 = {T_599,1'h0};
+ assign T_604 = 9'h0 - 1'h1;
+ assign T_605 = T_604[8:0];
+ assign T_606 = T_597 ^ T_605;
+ assign T_607 = T_500 ? T_606 : T_497;
+ assign T_611 = T_500 ? 2'h2 : 1'h1;
+ assign T_612 = 8'h80 | T_611;
+ assign T_613 = T_607 + T_612;
+ assign T_614 = T_613[8:0];
+ assign T_615 = T_614[8:7];
+ assign T_617 = T_615 == 2'h3;
+ assign T_619 = T_502 == 1'h0;
+ assign T_620 = T_617 & T_619;
+ assign T_622 = 3'h0 - T_503;
+ assign T_623 = T_622[2:0];
+ assign T_624 = T_623 << 6;
+ assign T_625 = ~ T_624;
+ assign T_626 = T_614 & T_625;
+ assign T_627 = T_620 << 6;
+ assign T_628 = T_626 | T_627;
+ assign T_629 = T_500 ? T_601 : T_498;
+ assign T_630 = {T_628,T_629};
+ assign T_631 = {T_496,T_630};
+ assign GEN_0 = $signed(32'hffffffff);
+ assign T_632 = $unsigned(GEN_0);
+ assign T_633 = {T_632,T_631};
+ assign T_634 = in_bits_typ[1];
+ assign T_635 = $signed(in_bits_in1);
+ assign T_636 = in_bits_typ[0];
+ assign T_637 = in_bits_in1[31:0];
+ assign T_638 = {1'b0,$signed(T_637)};
+ assign T_639 = in_bits_in1[31:0];
+ assign T_640 = $signed(T_639);
+ assign T_641 = T_636 ? $signed(T_638) : $signed(T_640);
+ assign longValue = T_634 ? $signed(T_635) : $signed(T_641);
+ assign l2s_clk = clk;
+ assign l2s_reset = reset;
+ assign l2s_io_signedIn = T_645;
+ assign l2s_io_in = T_646;
+ assign l2s_io_roundingMode = in_bits_rm;
+ assign T_644 = in_bits_typ[0];
+ assign T_645 = ~ T_644;
+ assign T_646 = $unsigned(longValue);
+ assign l2d_clk = clk;
+ assign l2d_reset = reset;
+ assign l2d_io_signedIn = T_649;
+ assign l2d_io_in = T_650;
+ assign l2d_io_roundingMode = in_bits_rm;
+ assign T_648 = in_bits_typ[0];
+ assign T_649 = ~ T_648;
+ assign T_650 = $unsigned(longValue);
+ assign T_653 = in_bits_cmd & 3'h4;
+ assign T_654 = 1'h0 == T_653;
+ assign GEN_1 = $signed(32'hffffffff);
+ assign T_656 = $unsigned(GEN_1);
+ assign T_657 = {T_656,l2s_io_out};
+ assign T_659 = in_bits_single == 1'h0;
+ assign T_680_valid = T_668;
+ assign T_680_bits_data = T_669_data;
+ assign T_680_bits_exc = T_669_exc;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_136 = {1{$random}};
+ T_137_cmd = {1{$random}};
+ T_137_ldst = {1{$random}};
+ T_137_wen = {1{$random}};
+ T_137_ren1 = {1{$random}};
+ T_137_ren2 = {1{$random}};
+ T_137_ren3 = {1{$random}};
+ T_137_swap12 = {1{$random}};
+ T_137_swap23 = {1{$random}};
+ T_137_single = {1{$random}};
+ T_137_fromint = {1{$random}};
+ T_137_toint = {1{$random}};
+ T_137_fastpipe = {1{$random}};
+ T_137_fma = {1{$random}};
+ T_137_div = {1{$random}};
+ T_137_sqrt = {1{$random}};
+ T_137_round = {1{$random}};
+ T_137_wflags = {1{$random}};
+ T_137_rm = {1{$random}};
+ T_137_typ = {1{$random}};
+ T_137_in1 = {3{$random}};
+ T_137_in2 = {3{$random}};
+ T_137_in3 = {3{$random}};
+ T_662 = {1{$random}};
+ T_663_data = {3{$random}};
+ T_663_exc = {1{$random}};
+ T_668 = {1{$random}};
+ T_669_data = {3{$random}};
+ T_669_exc = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ T_136 <= 1'h0;
+ end else begin
+ T_136 <= io_in_valid;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_137_cmd <= io_in_bits_cmd;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_137_ldst <= io_in_bits_ldst;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_137_wen <= io_in_bits_wen;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_137_ren1 <= io_in_bits_ren1;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_137_ren2 <= io_in_bits_ren2;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_137_ren3 <= io_in_bits_ren3;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_137_swap12 <= io_in_bits_swap12;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_137_swap23 <= io_in_bits_swap23;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_137_single <= io_in_bits_single;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_137_fromint <= io_in_bits_fromint;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_137_toint <= io_in_bits_toint;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_137_fastpipe <= io_in_bits_fastpipe;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_137_fma <= io_in_bits_fma;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_137_div <= io_in_bits_div;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_137_sqrt <= io_in_bits_sqrt;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_137_round <= io_in_bits_round;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_137_wflags <= io_in_bits_wflags;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_137_rm <= io_in_bits_rm;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_137_typ <= io_in_bits_typ;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_137_in1 <= io_in_bits_in1;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_137_in2 <= io_in_bits_in2;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_137_in3 <= io_in_bits_in3;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_662 <= 1'h0;
+ end else begin
+ T_662 <= in_valid;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(in_valid) begin
+ T_663_data <= mux_data;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(in_valid) begin
+ T_663_exc <= mux_exc;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_668 <= 1'h0;
+ end else begin
+ T_668 <= T_662;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_662) begin
+ T_669_data <= T_663_data;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_662) begin
+ T_669_exc <= T_663_exc;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module RoundRawFNToRecFN(
+ input clk,
+ input reset,
+ input io_invalidExc,
+ input io_infiniteExc,
+ input io_in_sign,
+ input io_in_isNaN,
+ input io_in_isInf,
+ input io_in_isZero,
+ input [9:0] io_in_sExp,
+ input [26:0] io_in_sig,
+ input [1:0] io_roundingMode,
+ output [32:0] io_out,
+ output [4:0] io_exceptionFlags
+);
+ wire roundingMode_nearest_even;
+ wire roundingMode_minMag;
+ wire roundingMode_min;
+ wire roundingMode_max;
+ wire T_27;
+ wire T_28;
+ wire T_29;
+ wire roundMagUp;
+ wire doShiftSigDown1;
+ wire GEN_0;
+ wire T_33;
+ wire [25:0] T_35;
+ wire [24:0] T_36;
+ wire [8:0] T_37;
+ wire [8:0] T_38;
+ wire [512:0] GEN_1;
+ wire [512:0] T_40;
+ wire [24:0] T_41;
+ wire [15:0] T_42;
+ wire [15:0] T_45;
+ wire [15:0] T_46;
+ wire [7:0] T_47;
+ wire [15:0] T_48;
+ wire [7:0] T_49;
+ wire [15:0] T_50;
+ wire [15:0] T_51;
+ wire [15:0] T_52;
+ wire [15:0] T_53;
+ wire [11:0] T_54;
+ wire [15:0] T_55;
+ wire [15:0] T_56;
+ wire [11:0] T_57;
+ wire [15:0] T_58;
+ wire [11:0] T_59;
+ wire [15:0] T_60;
+ wire [15:0] T_61;
+ wire [15:0] T_62;
+ wire [15:0] T_63;
+ wire [13:0] T_64;
+ wire [15:0] T_65;
+ wire [15:0] T_66;
+ wire [13:0] T_67;
+ wire [15:0] T_68;
+ wire [13:0] T_69;
+ wire [15:0] T_70;
+ wire [15:0] T_71;
+ wire [15:0] T_72;
+ wire [15:0] T_73;
+ wire [14:0] T_74;
+ wire [15:0] T_75;
+ wire [15:0] T_76;
+ wire [14:0] T_77;
+ wire [15:0] T_78;
+ wire [14:0] T_79;
+ wire [15:0] T_80;
+ wire [15:0] T_81;
+ wire [15:0] T_82;
+ wire [15:0] T_83;
+ wire [8:0] T_84;
+ wire [7:0] T_85;
+ wire [7:0] T_88;
+ wire [7:0] T_89;
+ wire [3:0] T_90;
+ wire [7:0] T_91;
+ wire [3:0] T_92;
+ wire [7:0] T_93;
+ wire [7:0] T_94;
+ wire [7:0] T_95;
+ wire [7:0] T_96;
+ wire [5:0] T_97;
+ wire [7:0] T_98;
+ wire [7:0] T_99;
+ wire [5:0] T_100;
+ wire [7:0] T_101;
+ wire [5:0] T_102;
+ wire [7:0] T_103;
+ wire [7:0] T_104;
+ wire [7:0] T_105;
+ wire [7:0] T_106;
+ wire [6:0] T_107;
+ wire [7:0] T_108;
+ wire [7:0] T_109;
+ wire [6:0] T_110;
+ wire [7:0] T_111;
+ wire [6:0] T_112;
+ wire [7:0] T_113;
+ wire [7:0] T_114;
+ wire [7:0] T_115;
+ wire [7:0] T_116;
+ wire T_117;
+ wire [8:0] T_118;
+ wire [24:0] T_119;
+ wire [24:0] T_120;
+ wire [24:0] T_121;
+ wire [26:0] roundMask;
+ wire [25:0] T_124;
+ wire [25:0] T_125;
+ wire [26:0] roundPosMask;
+ wire [26:0] T_127;
+ wire roundPosBit;
+ wire [25:0] T_130;
+ wire [26:0] T_131;
+ wire anyRoundExtra;
+ wire common_inexact;
+ wire T_135;
+ wire T_136;
+ wire T_137;
+ wire [26:0] T_138;
+ wire [24:0] T_139;
+ wire [25:0] T_141;
+ wire [24:0] T_142;
+ wire T_143;
+ wire T_144;
+ wire T_145;
+ wire [25:0] T_146;
+ wire [25:0] T_148;
+ wire [25:0] T_149;
+ wire [25:0] T_150;
+ wire [26:0] T_151;
+ wire [26:0] T_152;
+ wire [24:0] T_153;
+ wire [25:0] roundedSig;
+ wire [1:0] T_155;
+ wire [2:0] T_156;
+ wire [10:0] T_157;
+ wire [9:0] T_158;
+ wire [9:0] sRoundedExp;
+ wire [8:0] common_expOut;
+ wire [22:0] T_161;
+ wire [22:0] T_162;
+ wire [22:0] common_fractOut;
+ wire [2:0] T_164;
+ wire [2:0] GEN_2;
+ wire common_overflow;
+ wire [7:0] GEN_3;
+ wire common_totalUnderflow;
+ wire [8:0] GEN_4;
+ wire [8:0] GEN_5;
+ wire [8:0] T_171;
+ wire T_172;
+ wire common_underflow;
+ wire isNaNOut;
+ wire notNaN_isSpecialInfOut;
+ wire T_176;
+ wire T_177;
+ wire T_178;
+ wire T_179;
+ wire commonCase;
+ wire overflow;
+ wire underflow;
+ wire T_183;
+ wire inexact;
+ wire overflow_roundMagUp;
+ wire T_186;
+ wire pegMinNonzeroMagOut;
+ wire T_188;
+ wire T_189;
+ wire pegMaxFiniteMagOut;
+ wire T_191;
+ wire notNaN_isInfOut;
+ wire signOut;
+ wire T_195;
+ wire [8:0] T_198;
+ wire [8:0] T_199;
+ wire [8:0] T_200;
+ wire [8:0] T_202;
+ wire [8:0] T_204;
+ wire [8:0] T_205;
+ wire [8:0] T_206;
+ wire [8:0] T_209;
+ wire [8:0] T_210;
+ wire [8:0] T_211;
+ wire [8:0] T_214;
+ wire [8:0] T_215;
+ wire [8:0] T_216;
+ wire [8:0] T_219;
+ wire [8:0] T_220;
+ wire [8:0] T_223;
+ wire [8:0] T_224;
+ wire [8:0] T_227;
+ wire [8:0] T_228;
+ wire [8:0] T_231;
+ wire [8:0] expOut;
+ wire T_233;
+ wire T_234;
+ wire [22:0] T_236;
+ wire [23:0] T_238;
+ wire [22:0] T_239;
+ wire [22:0] T_240;
+ wire [22:0] T_241;
+ wire [22:0] fractOut;
+ wire [31:0] T_243;
+ wire [32:0] T_244;
+ wire [1:0] T_245;
+ wire [1:0] T_246;
+ wire [2:0] T_247;
+ wire [4:0] T_248;
+ assign io_out = T_244;
+ assign io_exceptionFlags = T_248;
+ assign roundingMode_nearest_even = io_roundingMode == 2'h0;
+ assign roundingMode_minMag = io_roundingMode == 2'h1;
+ assign roundingMode_min = io_roundingMode == 2'h2;
+ assign roundingMode_max = io_roundingMode == 2'h3;
+ assign T_27 = roundingMode_min & io_in_sign;
+ assign T_28 = ~ io_in_sign;
+ assign T_29 = roundingMode_max & T_28;
+ assign roundMagUp = T_27 | T_29;
+ assign doShiftSigDown1 = io_in_sig[26];
+ assign GEN_0 = $signed(1'h0);
+ assign T_33 = $signed(io_in_sExp) < $signed(GEN_0);
+ assign T_35 = 25'h0 - T_33;
+ assign T_36 = T_35[24:0];
+ assign T_37 = io_in_sExp[8:0];
+ assign T_38 = ~ T_37;
+ assign GEN_1 = $signed(513'h100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000);
+ assign T_40 = $signed(GEN_1) >>> T_38;
+ assign T_41 = T_40[130:106];
+ assign T_42 = T_41[15:0];
+ assign T_45 = 8'hff << 8;
+ assign T_46 = 16'hffff ^ T_45;
+ assign T_47 = T_42[15:8];
+ assign T_48 = T_47 & T_46;
+ assign T_49 = T_42[7:0];
+ assign T_50 = T_49 << 8;
+ assign T_51 = ~ T_46;
+ assign T_52 = T_50 & T_51;
+ assign T_53 = T_48 | T_52;
+ assign T_54 = T_46[11:0];
+ assign T_55 = T_54 << 4;
+ assign T_56 = T_46 ^ T_55;
+ assign T_57 = T_53[15:4];
+ assign T_58 = T_57 & T_56;
+ assign T_59 = T_53[11:0];
+ assign T_60 = T_59 << 4;
+ assign T_61 = ~ T_56;
+ assign T_62 = T_60 & T_61;
+ assign T_63 = T_58 | T_62;
+ assign T_64 = T_56[13:0];
+ assign T_65 = T_64 << 2;
+ assign T_66 = T_56 ^ T_65;
+ assign T_67 = T_63[15:2];
+ assign T_68 = T_67 & T_66;
+ assign T_69 = T_63[13:0];
+ assign T_70 = T_69 << 2;
+ assign T_71 = ~ T_66;
+ assign T_72 = T_70 & T_71;
+ assign T_73 = T_68 | T_72;
+ assign T_74 = T_66[14:0];
+ assign T_75 = T_74 << 1;
+ assign T_76 = T_66 ^ T_75;
+ assign T_77 = T_73[15:1];
+ assign T_78 = T_77 & T_76;
+ assign T_79 = T_73[14:0];
+ assign T_80 = T_79 << 1;
+ assign T_81 = ~ T_76;
+ assign T_82 = T_80 & T_81;
+ assign T_83 = T_78 | T_82;
+ assign T_84 = T_41[24:16];
+ assign T_85 = T_84[7:0];
+ assign T_88 = 4'hf << 4;
+ assign T_89 = 8'hff ^ T_88;
+ assign T_90 = T_85[7:4];
+ assign T_91 = T_90 & T_89;
+ assign T_92 = T_85[3:0];
+ assign T_93 = T_92 << 4;
+ assign T_94 = ~ T_89;
+ assign T_95 = T_93 & T_94;
+ assign T_96 = T_91 | T_95;
+ assign T_97 = T_89[5:0];
+ assign T_98 = T_97 << 2;
+ assign T_99 = T_89 ^ T_98;
+ assign T_100 = T_96[7:2];
+ assign T_101 = T_100 & T_99;
+ assign T_102 = T_96[5:0];
+ assign T_103 = T_102 << 2;
+ assign T_104 = ~ T_99;
+ assign T_105 = T_103 & T_104;
+ assign T_106 = T_101 | T_105;
+ assign T_107 = T_99[6:0];
+ assign T_108 = T_107 << 1;
+ assign T_109 = T_99 ^ T_108;
+ assign T_110 = T_106[7:1];
+ assign T_111 = T_110 & T_109;
+ assign T_112 = T_106[6:0];
+ assign T_113 = T_112 << 1;
+ assign T_114 = ~ T_109;
+ assign T_115 = T_113 & T_114;
+ assign T_116 = T_111 | T_115;
+ assign T_117 = T_84[8];
+ assign T_118 = {T_116,T_117};
+ assign T_119 = {T_83,T_118};
+ assign T_120 = T_36 | T_119;
+ assign T_121 = T_120 | doShiftSigDown1;
+ assign roundMask = {T_121,2'h3};
+ assign T_124 = roundMask[26:1];
+ assign T_125 = ~ T_124;
+ assign roundPosMask = T_125 & roundMask;
+ assign T_127 = io_in_sig & roundPosMask;
+ assign roundPosBit = T_127 != 1'h0;
+ assign T_130 = roundMask[26:1];
+ assign T_131 = io_in_sig & T_130;
+ assign anyRoundExtra = T_131 != 1'h0;
+ assign common_inexact = roundPosBit | anyRoundExtra;
+ assign T_135 = roundingMode_nearest_even & roundPosBit;
+ assign T_136 = roundMagUp & common_inexact;
+ assign T_137 = T_135 | T_136;
+ assign T_138 = io_in_sig | roundMask;
+ assign T_139 = T_138[26:2];
+ assign T_141 = T_139 + 1'h1;
+ assign T_142 = T_141[24:0];
+ assign T_143 = roundingMode_nearest_even & roundPosBit;
+ assign T_144 = ~ anyRoundExtra;
+ assign T_145 = T_143 & T_144;
+ assign T_146 = roundMask[26:1];
+ assign T_148 = T_145 ? T_146 : 26'h0;
+ assign T_149 = ~ T_148;
+ assign T_150 = T_142 & T_149;
+ assign T_151 = ~ roundMask;
+ assign T_152 = io_in_sig & T_151;
+ assign T_153 = T_152[26:2];
+ assign roundedSig = T_137 ? T_150 : T_153;
+ assign T_155 = roundedSig[25:24];
+ assign T_156 = {1'b0,$signed(T_155)};
+ assign T_157 = $signed(io_in_sExp) + $signed(T_156);
+ assign T_158 = T_157[9:0];
+ assign sRoundedExp = $signed(T_158);
+ assign common_expOut = sRoundedExp[8:0];
+ assign T_161 = roundedSig[23:1];
+ assign T_162 = roundedSig[22:0];
+ assign common_fractOut = doShiftSigDown1 ? T_161 : T_162;
+ assign T_164 = sRoundedExp[9:7];
+ assign GEN_2 = $signed(3'h3);
+ assign common_overflow = $signed(T_164) >= $signed(GEN_2);
+ assign GEN_3 = $signed(8'h6b);
+ assign common_totalUnderflow = $signed(sRoundedExp) < $signed(GEN_3);
+ assign GEN_4 = $signed(9'h81);
+ assign GEN_5 = $signed(9'h82);
+ assign T_171 = doShiftSigDown1 ? $signed(GEN_4) : $signed(GEN_5);
+ assign T_172 = $signed(io_in_sExp) < $signed(T_171);
+ assign common_underflow = common_inexact & T_172;
+ assign isNaNOut = io_invalidExc | io_in_isNaN;
+ assign notNaN_isSpecialInfOut = io_infiniteExc | io_in_isInf;
+ assign T_176 = ~ isNaNOut;
+ assign T_177 = ~ notNaN_isSpecialInfOut;
+ assign T_178 = T_176 & T_177;
+ assign T_179 = ~ io_in_isZero;
+ assign commonCase = T_178 & T_179;
+ assign overflow = commonCase & common_overflow;
+ assign underflow = commonCase & common_underflow;
+ assign T_183 = commonCase & common_inexact;
+ assign inexact = overflow | T_183;
+ assign overflow_roundMagUp = roundingMode_nearest_even | roundMagUp;
+ assign T_186 = commonCase & common_totalUnderflow;
+ assign pegMinNonzeroMagOut = T_186 & roundMagUp;
+ assign T_188 = commonCase & overflow;
+ assign T_189 = ~ overflow_roundMagUp;
+ assign pegMaxFiniteMagOut = T_188 & T_189;
+ assign T_191 = overflow & overflow_roundMagUp;
+ assign notNaN_isInfOut = notNaN_isSpecialInfOut | T_191;
+ assign signOut = isNaNOut ? 1'h0 : io_in_sign;
+ assign T_195 = io_in_isZero | common_totalUnderflow;
+ assign T_198 = T_195 ? 9'h1c0 : 1'h0;
+ assign T_199 = ~ T_198;
+ assign T_200 = common_expOut & T_199;
+ assign T_202 = ~ 9'h6b;
+ assign T_204 = pegMinNonzeroMagOut ? T_202 : 1'h0;
+ assign T_205 = ~ T_204;
+ assign T_206 = T_200 & T_205;
+ assign T_209 = pegMaxFiniteMagOut ? 9'h80 : 1'h0;
+ assign T_210 = ~ T_209;
+ assign T_211 = T_206 & T_210;
+ assign T_214 = notNaN_isInfOut ? 9'h40 : 1'h0;
+ assign T_215 = ~ T_214;
+ assign T_216 = T_211 & T_215;
+ assign T_219 = pegMinNonzeroMagOut ? 9'h6b : 1'h0;
+ assign T_220 = T_216 | T_219;
+ assign T_223 = pegMaxFiniteMagOut ? 9'h17f : 1'h0;
+ assign T_224 = T_220 | T_223;
+ assign T_227 = notNaN_isInfOut ? 9'h180 : 1'h0;
+ assign T_228 = T_224 | T_227;
+ assign T_231 = isNaNOut ? 9'h1c0 : 1'h0;
+ assign expOut = T_228 | T_231;
+ assign T_233 = common_totalUnderflow & roundMagUp;
+ assign T_234 = T_233 | isNaNOut;
+ assign T_236 = T_234 ? 1'h0 : common_fractOut;
+ assign T_238 = 23'h0 - pegMaxFiniteMagOut;
+ assign T_239 = T_238[22:0];
+ assign T_240 = T_236 | T_239;
+ assign T_241 = isNaNOut << 22;
+ assign fractOut = T_240 | T_241;
+ assign T_243 = {expOut,fractOut};
+ assign T_244 = {signOut,T_243};
+ assign T_245 = {io_invalidExc,io_infiniteExc};
+ assign T_246 = {underflow,inexact};
+ assign T_247 = {overflow,T_246};
+ assign T_248 = {T_245,T_247};
+endmodule
+module RecFNToRecFN_121(
+ input clk,
+ input reset,
+ input [64:0] io_in,
+ input [1:0] io_roundingMode,
+ output [32:0] io_out,
+ output [4:0] io_exceptionFlags
+);
+ wire [11:0] T_8;
+ wire [1:0] T_9;
+ wire T_11;
+ wire T_19_sign;
+ wire T_19_isNaN;
+ wire T_19_isInf;
+ wire T_19_isZero;
+ wire [12:0] T_19_sExp;
+ wire [55:0] T_19_sig;
+ wire T_26;
+ wire T_27;
+ wire T_28;
+ wire T_29;
+ wire T_31;
+ wire T_32;
+ wire [2:0] T_33;
+ wire T_35;
+ wire [12:0] T_36;
+ wire [51:0] T_38;
+ wire [53:0] T_40;
+ wire [55:0] T_41;
+ wire [11:0] GEN_0;
+ wire [13:0] T_43;
+ wire [12:0] T_44;
+ wire [12:0] T_45;
+ wire outRawFloat_sign;
+ wire outRawFloat_isNaN;
+ wire outRawFloat_isInf;
+ wire outRawFloat_isZero;
+ wire [9:0] outRawFloat_sExp;
+ wire [26:0] outRawFloat_sig;
+ wire GEN_1;
+ wire T_61;
+ wire [2:0] T_62;
+ wire T_64;
+ wire [1:0] T_66;
+ wire [3:0] T_67;
+ wire [5:0] T_68;
+ wire [6:0] T_69;
+ wire [8:0] T_71;
+ wire [8:0] T_72;
+ wire [8:0] T_73;
+ wire [9:0] T_74;
+ wire [9:0] T_75;
+ wire [25:0] T_76;
+ wire [29:0] T_77;
+ wire T_79;
+ wire [26:0] T_80;
+ wire T_81;
+ wire T_83;
+ wire invalidExc;
+ wire T_85_clk;
+ wire T_85_reset;
+ wire T_85_io_invalidExc;
+ wire T_85_io_infiniteExc;
+ wire T_85_io_in_sign;
+ wire T_85_io_in_isNaN;
+ wire T_85_io_in_isInf;
+ wire T_85_io_in_isZero;
+ wire [9:0] T_85_io_in_sExp;
+ wire [26:0] T_85_io_in_sig;
+ wire [1:0] T_85_io_roundingMode;
+ wire [32:0] T_85_io_out;
+ wire [4:0] T_85_io_exceptionFlags;
+ RoundRawFNToRecFN T_85 (
+ .clk(T_85_clk),
+ .reset(T_85_reset),
+ .io_invalidExc(T_85_io_invalidExc),
+ .io_infiniteExc(T_85_io_infiniteExc),
+ .io_in_sign(T_85_io_in_sign),
+ .io_in_isNaN(T_85_io_in_isNaN),
+ .io_in_isInf(T_85_io_in_isInf),
+ .io_in_isZero(T_85_io_in_isZero),
+ .io_in_sExp(T_85_io_in_sExp),
+ .io_in_sig(T_85_io_in_sig),
+ .io_roundingMode(T_85_io_roundingMode),
+ .io_out(T_85_io_out),
+ .io_exceptionFlags(T_85_io_exceptionFlags)
+ );
+ assign io_out = T_85_io_out;
+ assign io_exceptionFlags = T_85_io_exceptionFlags;
+ assign T_8 = io_in[63:52];
+ assign T_9 = T_8[11:10];
+ assign T_11 = T_9 == 2'h3;
+ assign T_19_sign = T_26;
+ assign T_19_isNaN = T_28;
+ assign T_19_isInf = T_32;
+ assign T_19_isZero = T_35;
+ assign T_19_sExp = T_36;
+ assign T_19_sig = T_41;
+ assign T_26 = io_in[64];
+ assign T_27 = T_8[9];
+ assign T_28 = T_11 & T_27;
+ assign T_29 = T_8[9];
+ assign T_31 = T_29 == 1'h0;
+ assign T_32 = T_11 & T_31;
+ assign T_33 = T_8[11:9];
+ assign T_35 = T_33 == 1'h0;
+ assign T_36 = {1'b0,$signed(T_8)};
+ assign T_38 = io_in[51:0];
+ assign T_40 = {T_38,2'h0};
+ assign T_41 = {2'h1,T_40};
+ assign GEN_0 = $signed(12'h900);
+ assign T_43 = $signed(T_19_sExp) + $signed(GEN_0);
+ assign T_44 = T_43[12:0];
+ assign T_45 = $signed(T_44);
+ assign outRawFloat_sign = T_19_sign;
+ assign outRawFloat_isNaN = T_19_isNaN;
+ assign outRawFloat_isInf = T_19_isInf;
+ assign outRawFloat_isZero = T_19_isZero;
+ assign outRawFloat_sExp = T_75;
+ assign outRawFloat_sig = T_80;
+ assign GEN_1 = $signed(1'h0);
+ assign T_61 = $signed(T_45) < $signed(GEN_1);
+ assign T_62 = T_45[11:9];
+ assign T_64 = T_62 != 1'h0;
+ assign T_66 = {1'h1,1'h1};
+ assign T_67 = {T_66,T_66};
+ assign T_68 = {T_66,T_67};
+ assign T_69 = {1'h1,T_68};
+ assign T_71 = {T_69,2'h0};
+ assign T_72 = T_45[8:0];
+ assign T_73 = T_64 ? T_71 : T_72;
+ assign T_74 = {T_61,T_73};
+ assign T_75 = $signed(T_74);
+ assign T_76 = T_19_sig[55:30];
+ assign T_77 = T_19_sig[29:0];
+ assign T_79 = T_77 != 1'h0;
+ assign T_80 = {T_76,T_79};
+ assign T_81 = outRawFloat_sig[24];
+ assign T_83 = T_81 == 1'h0;
+ assign invalidExc = outRawFloat_isNaN & T_83;
+ assign T_85_clk = clk;
+ assign T_85_reset = reset;
+ assign T_85_io_invalidExc = invalidExc;
+ assign T_85_io_infiniteExc = 1'h0;
+ assign T_85_io_in_sign = outRawFloat_sign;
+ assign T_85_io_in_isNaN = outRawFloat_isNaN;
+ assign T_85_io_in_isInf = outRawFloat_isInf;
+ assign T_85_io_in_isZero = outRawFloat_isZero;
+ assign T_85_io_in_sExp = outRawFloat_sExp;
+ assign T_85_io_in_sig = outRawFloat_sig;
+ assign T_85_io_roundingMode = io_roundingMode;
+endmodule
+module FPToFP(
+ input clk,
+ input reset,
+ input io_in_valid,
+ input [4:0] io_in_bits_cmd,
+ input io_in_bits_ldst,
+ input io_in_bits_wen,
+ input io_in_bits_ren1,
+ input io_in_bits_ren2,
+ input io_in_bits_ren3,
+ input io_in_bits_swap12,
+ input io_in_bits_swap23,
+ input io_in_bits_single,
+ input io_in_bits_fromint,
+ input io_in_bits_toint,
+ input io_in_bits_fastpipe,
+ input io_in_bits_fma,
+ input io_in_bits_div,
+ input io_in_bits_sqrt,
+ input io_in_bits_round,
+ input io_in_bits_wflags,
+ input [2:0] io_in_bits_rm,
+ input [1:0] io_in_bits_typ,
+ input [64:0] io_in_bits_in1,
+ input [64:0] io_in_bits_in2,
+ input [64:0] io_in_bits_in3,
+ output io_out_valid,
+ output [64:0] io_out_bits_data,
+ output [4:0] io_out_bits_exc,
+ input io_lt
+);
+ reg T_137;
+ reg [4:0] T_138_cmd;
+ reg T_138_ldst;
+ reg T_138_wen;
+ reg T_138_ren1;
+ reg T_138_ren2;
+ reg T_138_ren3;
+ reg T_138_swap12;
+ reg T_138_swap23;
+ reg T_138_single;
+ reg T_138_fromint;
+ reg T_138_toint;
+ reg T_138_fastpipe;
+ reg T_138_fma;
+ reg T_138_div;
+ reg T_138_sqrt;
+ reg T_138_round;
+ reg T_138_wflags;
+ reg [2:0] T_138_rm;
+ reg [1:0] T_138_typ;
+ reg [64:0] T_138_in1;
+ reg [64:0] T_138_in2;
+ reg [64:0] T_138_in3;
+ wire in_valid;
+ wire [4:0] in_bits_cmd;
+ wire in_bits_ldst;
+ wire in_bits_wen;
+ wire in_bits_ren1;
+ wire in_bits_ren2;
+ wire in_bits_ren3;
+ wire in_bits_swap12;
+ wire in_bits_swap23;
+ wire in_bits_single;
+ wire in_bits_fromint;
+ wire in_bits_toint;
+ wire in_bits_fastpipe;
+ wire in_bits_fma;
+ wire in_bits_div;
+ wire in_bits_sqrt;
+ wire in_bits_round;
+ wire in_bits_wflags;
+ wire [2:0] in_bits_rm;
+ wire [1:0] in_bits_typ;
+ wire [64:0] in_bits_in1;
+ wire [64:0] in_bits_in2;
+ wire [64:0] in_bits_in3;
+ wire [4:0] T_259;
+ wire isSgnj;
+ wire T_261;
+ wire T_262;
+ wire T_264;
+ wire T_265;
+ wire T_266;
+ wire T_267;
+ wire T_268;
+ wire T_269;
+ wire T_270;
+ wire sign_s;
+ wire T_273;
+ wire T_274;
+ wire T_275;
+ wire T_277;
+ wire T_278;
+ wire T_279;
+ wire T_280;
+ wire T_281;
+ wire T_282;
+ wire T_283;
+ wire sign_d;
+ wire [30:0] T_285;
+ wire [31:0] T_286;
+ wire [31:0] T_287;
+ wire [32:0] T_288;
+ wire [64:0] fsgnj;
+ wire s2d_clk;
+ wire s2d_reset;
+ wire [32:0] s2d_io_in;
+ wire [1:0] s2d_io_roundingMode;
+ wire [64:0] s2d_io_out;
+ wire [4:0] s2d_io_exceptionFlags;
+ wire d2s_clk;
+ wire d2s_reset;
+ wire [64:0] d2s_io_in;
+ wire [1:0] d2s_io_roundingMode;
+ wire [32:0] d2s_io_out;
+ wire [4:0] d2s_io_exceptionFlags;
+ wire [2:0] T_292;
+ wire [2:0] T_293;
+ wire T_295;
+ wire [2:0] T_296;
+ wire [2:0] T_297;
+ wire T_299;
+ wire isnan1;
+ wire [2:0] T_301;
+ wire [2:0] T_302;
+ wire T_304;
+ wire [2:0] T_305;
+ wire [2:0] T_306;
+ wire T_308;
+ wire isnan2;
+ wire T_310;
+ wire T_311;
+ wire T_312;
+ wire T_313;
+ wire issnan1;
+ wire T_315;
+ wire T_316;
+ wire T_317;
+ wire T_318;
+ wire issnan2;
+ wire T_320;
+ wire [4:0] minmax_exc;
+ wire isMax;
+ wire T_324;
+ wire T_326;
+ wire T_327;
+ wire isLHS;
+ wire [64:0] mux_data;
+ wire [4:0] mux_exc;
+ wire T_336;
+ wire [4:0] T_339;
+ wire T_340;
+ wire [31:0] GEN_0;
+ wire [31:0] T_342;
+ wire [64:0] T_343;
+ wire T_345;
+ reg T_348;
+ reg [64:0] T_349_data;
+ reg [4:0] T_349_exc;
+ wire T_360_valid;
+ wire [64:0] T_360_bits_data;
+ wire [4:0] T_360_bits_exc;
+ RecFNToRecFN s2d (
+ .clk(s2d_clk),
+ .reset(s2d_reset),
+ .io_in(s2d_io_in),
+ .io_roundingMode(s2d_io_roundingMode),
+ .io_out(s2d_io_out),
+ .io_exceptionFlags(s2d_io_exceptionFlags)
+ );
+ RecFNToRecFN_121 d2s (
+ .clk(d2s_clk),
+ .reset(d2s_reset),
+ .io_in(d2s_io_in),
+ .io_roundingMode(d2s_io_roundingMode),
+ .io_out(d2s_io_out),
+ .io_exceptionFlags(d2s_io_exceptionFlags)
+ );
+ assign io_out_valid = T_360_valid;
+ assign io_out_bits_data = T_360_bits_data;
+ assign io_out_bits_exc = T_360_bits_exc;
+ assign in_valid = T_137;
+ assign in_bits_cmd = T_138_cmd;
+ assign in_bits_ldst = T_138_ldst;
+ assign in_bits_wen = T_138_wen;
+ assign in_bits_ren1 = T_138_ren1;
+ assign in_bits_ren2 = T_138_ren2;
+ assign in_bits_ren3 = T_138_ren3;
+ assign in_bits_swap12 = T_138_swap12;
+ assign in_bits_swap23 = T_138_swap23;
+ assign in_bits_single = T_138_single;
+ assign in_bits_fromint = T_138_fromint;
+ assign in_bits_toint = T_138_toint;
+ assign in_bits_fastpipe = T_138_fastpipe;
+ assign in_bits_fma = T_138_fma;
+ assign in_bits_div = T_138_div;
+ assign in_bits_sqrt = T_138_sqrt;
+ assign in_bits_round = T_138_round;
+ assign in_bits_wflags = T_138_wflags;
+ assign in_bits_rm = T_138_rm;
+ assign in_bits_typ = T_138_typ;
+ assign in_bits_in1 = T_138_in1;
+ assign in_bits_in2 = T_138_in2;
+ assign in_bits_in3 = T_138_in3;
+ assign T_259 = in_bits_cmd & 3'h5;
+ assign isSgnj = 3'h4 == T_259;
+ assign T_261 = in_bits_single & isSgnj;
+ assign T_262 = in_bits_rm[1];
+ assign T_264 = T_261 == 1'h0;
+ assign T_265 = T_262 | T_264;
+ assign T_266 = in_bits_in1[32];
+ assign T_267 = in_bits_rm[0];
+ assign T_268 = T_265 ? T_266 : T_267;
+ assign T_269 = in_bits_in2[32];
+ assign T_270 = T_261 & T_269;
+ assign sign_s = T_268 ^ T_270;
+ assign T_273 = in_bits_single == 1'h0;
+ assign T_274 = T_273 & isSgnj;
+ assign T_275 = in_bits_rm[1];
+ assign T_277 = T_274 == 1'h0;
+ assign T_278 = T_275 | T_277;
+ assign T_279 = in_bits_in1[64];
+ assign T_280 = in_bits_rm[0];
+ assign T_281 = T_278 ? T_279 : T_280;
+ assign T_282 = in_bits_in2[64];
+ assign T_283 = T_274 & T_282;
+ assign sign_d = T_281 ^ T_283;
+ assign T_285 = in_bits_in1[63:33];
+ assign T_286 = in_bits_in1[31:0];
+ assign T_287 = {sign_d,T_285};
+ assign T_288 = {sign_s,T_286};
+ assign fsgnj = {T_287,T_288};
+ assign s2d_clk = clk;
+ assign s2d_reset = reset;
+ assign s2d_io_in = in_bits_in1;
+ assign s2d_io_roundingMode = in_bits_rm;
+ assign d2s_clk = clk;
+ assign d2s_reset = reset;
+ assign d2s_io_in = in_bits_in1;
+ assign d2s_io_roundingMode = in_bits_rm;
+ assign T_292 = in_bits_in1[31:29];
+ assign T_293 = ~ T_292;
+ assign T_295 = T_293 == 1'h0;
+ assign T_296 = in_bits_in1[63:61];
+ assign T_297 = ~ T_296;
+ assign T_299 = T_297 == 1'h0;
+ assign isnan1 = in_bits_single ? T_295 : T_299;
+ assign T_301 = in_bits_in2[31:29];
+ assign T_302 = ~ T_301;
+ assign T_304 = T_302 == 1'h0;
+ assign T_305 = in_bits_in2[63:61];
+ assign T_306 = ~ T_305;
+ assign T_308 = T_306 == 1'h0;
+ assign isnan2 = in_bits_single ? T_304 : T_308;
+ assign T_310 = in_bits_in1[22];
+ assign T_311 = in_bits_in1[51];
+ assign T_312 = in_bits_single ? T_310 : T_311;
+ assign T_313 = ~ T_312;
+ assign issnan1 = isnan1 & T_313;
+ assign T_315 = in_bits_in2[22];
+ assign T_316 = in_bits_in2[51];
+ assign T_317 = in_bits_single ? T_315 : T_316;
+ assign T_318 = ~ T_317;
+ assign issnan2 = isnan2 & T_318;
+ assign T_320 = issnan1 | issnan2;
+ assign minmax_exc = {T_320,4'h0};
+ assign isMax = in_bits_rm[0];
+ assign T_324 = isMax != io_lt;
+ assign T_326 = isnan1 == 1'h0;
+ assign T_327 = T_324 & T_326;
+ assign isLHS = isnan2 | T_327;
+ assign mux_data = T_340 ? T_345 ? s2d_io_out : in_bits_single ? T_343 : T_336 ? fsgnj : in_bits_in2 : T_336 ? fsgnj : in_bits_in2;
+ assign mux_exc = T_340 ? T_345 ? s2d_io_exceptionFlags : in_bits_single ? d2s_io_exceptionFlags : isSgnj ? 1'h0 : minmax_exc : isSgnj ? 1'h0 : minmax_exc;
+ assign T_336 = isSgnj | isLHS;
+ assign T_339 = in_bits_cmd & 3'h4;
+ assign T_340 = 1'h0 == T_339;
+ assign GEN_0 = $signed(32'hffffffff);
+ assign T_342 = $unsigned(GEN_0);
+ assign T_343 = {T_342,d2s_io_out};
+ assign T_345 = in_bits_single == 1'h0;
+ assign T_360_valid = T_348;
+ assign T_360_bits_data = T_349_data;
+ assign T_360_bits_exc = T_349_exc;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_137 = {1{$random}};
+ T_138_cmd = {1{$random}};
+ T_138_ldst = {1{$random}};
+ T_138_wen = {1{$random}};
+ T_138_ren1 = {1{$random}};
+ T_138_ren2 = {1{$random}};
+ T_138_ren3 = {1{$random}};
+ T_138_swap12 = {1{$random}};
+ T_138_swap23 = {1{$random}};
+ T_138_single = {1{$random}};
+ T_138_fromint = {1{$random}};
+ T_138_toint = {1{$random}};
+ T_138_fastpipe = {1{$random}};
+ T_138_fma = {1{$random}};
+ T_138_div = {1{$random}};
+ T_138_sqrt = {1{$random}};
+ T_138_round = {1{$random}};
+ T_138_wflags = {1{$random}};
+ T_138_rm = {1{$random}};
+ T_138_typ = {1{$random}};
+ T_138_in1 = {3{$random}};
+ T_138_in2 = {3{$random}};
+ T_138_in3 = {3{$random}};
+ T_348 = {1{$random}};
+ T_349_data = {3{$random}};
+ T_349_exc = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ T_137 <= 1'h0;
+ end else begin
+ T_137 <= io_in_valid;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_138_cmd <= io_in_bits_cmd;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_138_ldst <= io_in_bits_ldst;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_138_wen <= io_in_bits_wen;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_138_ren1 <= io_in_bits_ren1;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_138_ren2 <= io_in_bits_ren2;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_138_ren3 <= io_in_bits_ren3;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_138_swap12 <= io_in_bits_swap12;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_138_swap23 <= io_in_bits_swap23;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_138_single <= io_in_bits_single;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_138_fromint <= io_in_bits_fromint;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_138_toint <= io_in_bits_toint;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_138_fastpipe <= io_in_bits_fastpipe;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_138_fma <= io_in_bits_fma;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_138_div <= io_in_bits_div;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_138_sqrt <= io_in_bits_sqrt;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_138_round <= io_in_bits_round;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_138_wflags <= io_in_bits_wflags;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_138_rm <= io_in_bits_rm;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_138_typ <= io_in_bits_typ;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_138_in1 <= io_in_bits_in1;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_138_in2 <= io_in_bits_in2;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_in_valid) begin
+ T_138_in3 <= io_in_bits_in3;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_348 <= 1'h0;
+ end else begin
+ T_348 <= in_valid;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(in_valid) begin
+ T_349_data <= mux_data;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(in_valid) begin
+ T_349_exc <= mux_exc;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module DivSqrtRecF64_mulAddZ31(
+ input clk,
+ input reset,
+ output io_inReady_div,
+ output io_inReady_sqrt,
+ input io_inValid,
+ input io_sqrtOp,
+ input [64:0] io_a,
+ input [64:0] io_b,
+ input [1:0] io_roundingMode,
+ output io_outValid_div,
+ output io_outValid_sqrt,
+ output [64:0] io_out,
+ output [4:0] io_exceptionFlags,
+ output [3:0] io_usingMulAdd,
+ output io_latchMulAddA_0,
+ output [53:0] io_mulAddA_0,
+ output io_latchMulAddB_0,
+ output [53:0] io_mulAddB_0,
+ output [104:0] io_mulAddC_2,
+ input [104:0] io_mulAddResult_3
+);
+ reg valid_PA;
+ reg sqrtOp_PA;
+ reg sign_PA;
+ reg [2:0] specialCodeB_PA;
+ reg fractB_51_PA;
+ reg [1:0] roundingMode_PA;
+ reg [2:0] specialCodeA_PA;
+ reg fractA_51_PA;
+ reg [13:0] exp_PA;
+ reg [50:0] fractB_other_PA;
+ reg [50:0] fractA_other_PA;
+ reg valid_PB;
+ reg sqrtOp_PB;
+ reg sign_PB;
+ reg [2:0] specialCodeA_PB;
+ reg fractA_51_PB;
+ reg [2:0] specialCodeB_PB;
+ reg fractB_51_PB;
+ reg [1:0] roundingMode_PB;
+ reg [13:0] exp_PB;
+ reg fractA_0_PB;
+ reg [50:0] fractB_other_PB;
+ reg valid_PC;
+ reg sqrtOp_PC;
+ reg sign_PC;
+ reg [2:0] specialCodeA_PC;
+ reg fractA_51_PC;
+ reg [2:0] specialCodeB_PC;
+ reg fractB_51_PC;
+ reg [1:0] roundingMode_PC;
+ reg [13:0] exp_PC;
+ reg fractA_0_PC;
+ reg [50:0] fractB_other_PC;
+ reg [2:0] cycleNum_A;
+ reg [3:0] cycleNum_B;
+ reg [2:0] cycleNum_C;
+ reg [2:0] cycleNum_E;
+ reg [8:0] fractR0_A;
+ reg [9:0] hiSqrR0_A_sqrt;
+ reg [20:0] partNegSigma0_A;
+ reg [8:0] nextMulAdd9A_A;
+ reg [8:0] nextMulAdd9B_A;
+ reg [16:0] ER1_B_sqrt;
+ reg [31:0] ESqrR1_B_sqrt;
+ reg [57:0] sigX1_B;
+ reg [32:0] sqrSigma1_C;
+ reg [57:0] sigXN_C;
+ reg [30:0] u_C_sqrt;
+ reg E_E_div;
+ reg [52:0] sigT_E;
+ reg extraT_E;
+ reg isNegRemT_E;
+ reg trueEqX_E1;
+ wire ready_PA;
+ wire ready_PB;
+ wire ready_PC;
+ wire leaving_PA;
+ wire leaving_PB;
+ wire leaving_PC;
+ wire cyc_B10_sqrt;
+ wire cyc_B9_sqrt;
+ wire cyc_B8_sqrt;
+ wire cyc_B7_sqrt;
+ wire cyc_B6;
+ wire cyc_B5;
+ wire cyc_B4;
+ wire cyc_B3;
+ wire cyc_B2;
+ wire cyc_B1;
+ wire cyc_B6_div;
+ wire cyc_B5_div;
+ wire cyc_B4_div;
+ wire cyc_B3_div;
+ wire cyc_B2_div;
+ wire cyc_B1_div;
+ wire cyc_B6_sqrt;
+ wire cyc_B5_sqrt;
+ wire cyc_B4_sqrt;
+ wire cyc_B3_sqrt;
+ wire cyc_B2_sqrt;
+ wire cyc_B1_sqrt;
+ wire cyc_C5;
+ wire cyc_C4;
+ wire valid_normalCase_leaving_PB;
+ wire cyc_C2;
+ wire cyc_C1;
+ wire cyc_E4;
+ wire cyc_E3;
+ wire cyc_E2;
+ wire cyc_E1;
+ wire [45:0] zSigma1_B4;
+ wire [57:0] sigXNU_B3_CX;
+ wire [53:0] zComplSigT_C1_sqrt;
+ wire [53:0] zComplSigT_C1;
+ wire T_210;
+ wire T_211;
+ wire T_212;
+ wire T_213;
+ wire T_214;
+ wire T_215;
+ wire T_216;
+ wire T_217;
+ wire T_218;
+ wire T_219;
+ wire T_220;
+ wire T_221;
+ wire T_222;
+ wire T_223;
+ wire T_224;
+ wire T_225;
+ wire T_226;
+ wire T_227;
+ wire T_228;
+ wire T_229;
+ wire T_230;
+ wire T_231;
+ wire T_232;
+ wire T_233;
+ wire T_234;
+ wire T_235;
+ wire T_236;
+ wire T_237;
+ wire T_238;
+ wire T_239;
+ wire cyc_S_div;
+ wire T_241;
+ wire cyc_S_sqrt;
+ wire cyc_S;
+ wire signA_S;
+ wire [11:0] expA_S;
+ wire [51:0] fractA_S;
+ wire [2:0] specialCodeA_S;
+ wire isZeroA_S;
+ wire [1:0] T_250;
+ wire isSpecialA_S;
+ wire signB_S;
+ wire [11:0] expB_S;
+ wire [51:0] fractB_S;
+ wire [2:0] specialCodeB_S;
+ wire isZeroB_S;
+ wire [1:0] T_259;
+ wire isSpecialB_S;
+ wire T_262;
+ wire sign_S;
+ wire T_264;
+ wire T_265;
+ wire T_266;
+ wire T_267;
+ wire T_268;
+ wire T_269;
+ wire normalCase_S_div;
+ wire T_271;
+ wire T_272;
+ wire T_273;
+ wire T_274;
+ wire normalCase_S_sqrt;
+ wire normalCase_S;
+ wire entering_PA_normalCase_div;
+ wire entering_PA_normalCase_sqrt;
+ wire entering_PA_normalCase;
+ wire T_280;
+ wire T_281;
+ wire T_282;
+ wire entering_PA;
+ wire T_284;
+ wire T_285;
+ wire T_286;
+ wire T_287;
+ wire T_288;
+ wire T_289;
+ wire T_290;
+ wire T_291;
+ wire entering_PB_S;
+ wire T_293;
+ wire T_294;
+ wire T_295;
+ wire T_296;
+ wire T_297;
+ wire T_298;
+ wire entering_PC_S;
+ wire T_300;
+ wire T_301;
+ wire T_302;
+ wire T_303;
+ wire T_304;
+ wire T_305;
+ wire [3:0] T_307;
+ wire [2:0] T_308;
+ wire [10:0] T_309;
+ wire [10:0] T_310;
+ wire [13:0] T_311;
+ wire [14:0] T_312;
+ wire [13:0] T_313;
+ wire [13:0] T_314;
+ wire [50:0] T_315;
+ wire [50:0] T_316;
+ wire isZeroA_PA;
+ wire [1:0] T_319;
+ wire isSpecialA_PA;
+ wire [51:0] T_323;
+ wire [52:0] sigA_PA;
+ wire isZeroB_PA;
+ wire [1:0] T_327;
+ wire isSpecialB_PA;
+ wire [51:0] T_331;
+ wire [52:0] sigB_PA;
+ wire T_333;
+ wire T_334;
+ wire T_335;
+ wire T_336;
+ wire T_337;
+ wire T_338;
+ wire T_339;
+ wire T_340;
+ wire T_341;
+ wire T_342;
+ wire T_343;
+ wire T_344;
+ wire normalCase_PA;
+ wire valid_normalCase_leaving_PA;
+ wire valid_leaving_PA;
+ wire T_348;
+ wire T_349;
+ wire T_350;
+ wire T_351;
+ wire entering_PB_normalCase;
+ wire entering_PB;
+ wire T_354;
+ wire T_355;
+ wire T_356;
+ wire [2:0] T_357;
+ wire T_358;
+ wire T_359;
+ wire [2:0] T_360;
+ wire T_361;
+ wire T_362;
+ wire [1:0] T_363;
+ wire T_364;
+ wire isZeroA_PB;
+ wire [1:0] T_367;
+ wire isSpecialA_PB;
+ wire isZeroB_PB;
+ wire [1:0] T_372;
+ wire isSpecialB_PB;
+ wire T_375;
+ wire T_376;
+ wire T_377;
+ wire T_378;
+ wire T_379;
+ wire T_380;
+ wire T_381;
+ wire T_382;
+ wire T_383;
+ wire T_384;
+ wire T_385;
+ wire T_386;
+ wire normalCase_PB;
+ wire valid_leaving_PB;
+ wire T_389;
+ wire T_390;
+ wire T_391;
+ wire T_392;
+ wire entering_PC_normalCase;
+ wire entering_PC;
+ wire T_395;
+ wire T_396;
+ wire T_397;
+ wire [2:0] T_398;
+ wire T_399;
+ wire T_400;
+ wire [2:0] T_401;
+ wire T_402;
+ wire T_403;
+ wire [1:0] T_404;
+ wire isZeroA_PC;
+ wire [1:0] T_407;
+ wire isSpecialA_PC;
+ wire T_410;
+ wire T_411;
+ wire isInfA_PC;
+ wire T_413;
+ wire isNaNA_PC;
+ wire T_415;
+ wire isSigNaNA_PC;
+ wire isZeroB_PC;
+ wire [1:0] T_419;
+ wire isSpecialB_PC;
+ wire T_422;
+ wire T_423;
+ wire isInfB_PC;
+ wire T_425;
+ wire isNaNB_PC;
+ wire T_427;
+ wire isSigNaNB_PC;
+ wire [51:0] T_430;
+ wire [52:0] sigB_PC;
+ wire T_432;
+ wire T_433;
+ wire T_434;
+ wire T_435;
+ wire T_436;
+ wire T_437;
+ wire T_438;
+ wire T_439;
+ wire T_440;
+ wire T_441;
+ wire T_442;
+ wire T_443;
+ wire normalCase_PC;
+ wire [14:0] T_446;
+ wire [13:0] expP2_PC;
+ wire T_448;
+ wire [12:0] T_449;
+ wire [13:0] T_451;
+ wire [12:0] T_452;
+ wire [13:0] T_454;
+ wire [13:0] expP1_PC;
+ wire roundingMode_near_even_PC;
+ wire roundingMode_minMag_PC;
+ wire roundingMode_min_PC;
+ wire roundingMode_max_PC;
+ wire roundMagUp_PC;
+ wire overflowY_roundMagUp_PC;
+ wire T_462;
+ wire T_463;
+ wire roundMagDown_PC;
+ wire T_465;
+ wire valid_leaving_PC;
+ wire T_467;
+ wire T_468;
+ wire T_469;
+ wire T_470;
+ wire T_471;
+ wire T_472;
+ wire T_474;
+ wire T_475;
+ wire [1:0] T_478;
+ wire [2:0] T_481;
+ wire [2:0] T_482;
+ wire T_483;
+ wire [3:0] T_485;
+ wire [2:0] T_486;
+ wire [2:0] T_488;
+ wire [2:0] T_489;
+ wire cyc_A6_sqrt;
+ wire cyc_A5_sqrt;
+ wire cyc_A4_sqrt;
+ wire cyc_A4;
+ wire cyc_A3;
+ wire cyc_A2;
+ wire cyc_A1;
+ wire T_503;
+ wire cyc_A3_div;
+ wire T_505;
+ wire cyc_A2_div;
+ wire T_507;
+ wire cyc_A1_div;
+ wire cyc_A3_sqrt;
+ wire cyc_A2_sqrt;
+ wire cyc_A1_sqrt;
+ wire T_513;
+ wire T_514;
+ wire [3:0] T_517;
+ wire [4:0] T_519;
+ wire [3:0] T_520;
+ wire [3:0] T_521;
+ wire T_523;
+ wire T_525;
+ wire T_527;
+ wire T_529;
+ wire T_531;
+ wire T_533;
+ wire T_535;
+ wire T_537;
+ wire T_539;
+ wire T_541;
+ wire T_542;
+ wire T_543;
+ wire T_544;
+ wire T_545;
+ wire T_546;
+ wire T_547;
+ wire T_548;
+ wire T_549;
+ wire T_550;
+ wire T_551;
+ wire T_552;
+ wire T_553;
+ wire T_554;
+ wire T_555;
+ wire T_556;
+ wire T_557;
+ wire T_558;
+ wire T_559;
+ wire T_560;
+ wire T_561;
+ wire T_562;
+ wire T_563;
+ wire T_564;
+ wire T_565;
+ wire T_567;
+ wire T_568;
+ wire [2:0] T_571;
+ wire [3:0] T_573;
+ wire [2:0] T_574;
+ wire [2:0] T_575;
+ wire cyc_C6_sqrt;
+ wire T_579;
+ wire T_581;
+ wire T_583;
+ wire T_585;
+ wire T_587;
+ wire T_588;
+ wire cyc_C5_div;
+ wire T_590;
+ wire cyc_C4_div;
+ wire T_592;
+ wire cyc_C3_div;
+ wire T_594;
+ wire cyc_C2_div;
+ wire T_596;
+ wire cyc_C1_div;
+ wire cyc_C5_sqrt;
+ wire cyc_C4_sqrt;
+ wire cyc_C3_sqrt;
+ wire cyc_C2_sqrt;
+ wire cyc_C1_sqrt;
+ wire T_604;
+ wire T_605;
+ wire [3:0] T_608;
+ wire [2:0] T_609;
+ wire [2:0] T_610;
+ wire T_612;
+ wire T_614;
+ wire T_616;
+ wire T_618;
+ wire T_619;
+ wire cyc_E4_div;
+ wire T_621;
+ wire cyc_E3_div;
+ wire T_623;
+ wire cyc_E2_div;
+ wire T_625;
+ wire cyc_E1_div;
+ wire cyc_E4_sqrt;
+ wire cyc_E3_sqrt;
+ wire cyc_E2_sqrt;
+ wire cyc_E1_sqrt;
+ wire [51:0] zFractB_A4_div;
+ wire [2:0] T_633;
+ wire T_635;
+ wire zLinPiece_0_A4_div;
+ wire [2:0] T_637;
+ wire T_639;
+ wire zLinPiece_1_A4_div;
+ wire [2:0] T_641;
+ wire T_643;
+ wire zLinPiece_2_A4_div;
+ wire [2:0] T_645;
+ wire T_647;
+ wire zLinPiece_3_A4_div;
+ wire [2:0] T_649;
+ wire T_651;
+ wire zLinPiece_4_A4_div;
+ wire [2:0] T_653;
+ wire T_655;
+ wire zLinPiece_5_A4_div;
+ wire [2:0] T_657;
+ wire T_659;
+ wire zLinPiece_6_A4_div;
+ wire [2:0] T_661;
+ wire T_663;
+ wire zLinPiece_7_A4_div;
+ wire [8:0] T_667;
+ wire [8:0] T_670;
+ wire [8:0] T_671;
+ wire [8:0] T_674;
+ wire [8:0] T_675;
+ wire [8:0] T_678;
+ wire [8:0] T_679;
+ wire [8:0] T_682;
+ wire [8:0] T_683;
+ wire [8:0] T_686;
+ wire [8:0] T_687;
+ wire [8:0] T_690;
+ wire [8:0] T_691;
+ wire [8:0] T_694;
+ wire [8:0] zK1_A4_div;
+ wire [11:0] T_697;
+ wire [11:0] T_699;
+ wire [11:0] T_701;
+ wire [11:0] T_703;
+ wire [11:0] T_704;
+ wire [11:0] T_706;
+ wire [11:0] T_708;
+ wire [11:0] T_709;
+ wire [11:0] T_711;
+ wire [11:0] T_713;
+ wire [11:0] T_714;
+ wire [11:0] T_716;
+ wire [11:0] T_718;
+ wire [11:0] T_719;
+ wire [11:0] T_721;
+ wire [11:0] T_723;
+ wire [11:0] T_724;
+ wire [11:0] T_726;
+ wire [11:0] T_728;
+ wire [11:0] T_729;
+ wire [11:0] T_731;
+ wire [11:0] T_733;
+ wire [11:0] zComplFractK0_A4_div;
+ wire [51:0] zFractB_A7_sqrt;
+ wire T_737;
+ wire T_738;
+ wire T_739;
+ wire T_740;
+ wire T_741;
+ wire zQuadPiece_0_A7_sqrt;
+ wire T_743;
+ wire T_744;
+ wire T_745;
+ wire T_746;
+ wire zQuadPiece_1_A7_sqrt;
+ wire T_748;
+ wire T_749;
+ wire T_750;
+ wire T_751;
+ wire zQuadPiece_2_A7_sqrt;
+ wire T_753;
+ wire T_754;
+ wire T_755;
+ wire zQuadPiece_3_A7_sqrt;
+ wire [8:0] T_759;
+ wire [8:0] T_762;
+ wire [8:0] T_763;
+ wire [8:0] T_766;
+ wire [8:0] T_767;
+ wire [8:0] T_770;
+ wire [8:0] zK2_A7_sqrt;
+ wire [9:0] T_773;
+ wire [9:0] T_775;
+ wire [9:0] T_777;
+ wire [9:0] T_779;
+ wire [9:0] T_780;
+ wire [9:0] T_782;
+ wire [9:0] T_784;
+ wire [9:0] T_785;
+ wire [9:0] T_787;
+ wire [9:0] T_789;
+ wire [9:0] zComplK1_A7_sqrt;
+ wire T_791;
+ wire T_792;
+ wire T_793;
+ wire T_794;
+ wire T_795;
+ wire zQuadPiece_0_A6_sqrt;
+ wire T_797;
+ wire T_798;
+ wire T_799;
+ wire T_800;
+ wire zQuadPiece_1_A6_sqrt;
+ wire T_802;
+ wire T_803;
+ wire T_804;
+ wire T_805;
+ wire zQuadPiece_2_A6_sqrt;
+ wire T_807;
+ wire T_808;
+ wire T_809;
+ wire zQuadPiece_3_A6_sqrt;
+ wire [12:0] T_812;
+ wire [12:0] T_814;
+ wire [12:0] T_816;
+ wire [12:0] T_818;
+ wire [12:0] T_819;
+ wire [12:0] T_821;
+ wire [12:0] T_823;
+ wire [12:0] T_824;
+ wire [12:0] T_826;
+ wire [12:0] T_828;
+ wire [12:0] zComplFractK0_A6_sqrt;
+ wire [8:0] T_830;
+ wire [8:0] T_831;
+ wire T_832;
+ wire [8:0] T_834;
+ wire [8:0] mulAdd9A_A;
+ wire [8:0] T_836;
+ wire [8:0] T_837;
+ wire T_838;
+ wire [8:0] T_840;
+ wire [8:0] mulAdd9B_A;
+ wire [19:0] T_842;
+ wire [6:0] T_844;
+ wire [5:0] T_845;
+ wire [18:0] T_846;
+ wire [19:0] T_847;
+ wire [19:0] T_848;
+ wire [8:0] T_850;
+ wire [7:0] T_851;
+ wire [19:0] T_852;
+ wire [20:0] T_853;
+ wire [20:0] T_854;
+ wire [18:0] T_856;
+ wire [20:0] T_857;
+ wire [19:0] T_858;
+ wire [19:0] T_860;
+ wire [20:0] T_861;
+ wire T_862;
+ wire T_863;
+ wire T_864;
+ wire [10:0] T_867;
+ wire [20:0] T_868;
+ wire T_869;
+ wire T_870;
+ wire T_871;
+ wire [20:0] T_872;
+ wire [21:0] T_874;
+ wire [20:0] T_875;
+ wire [20:0] T_877;
+ wire [20:0] T_878;
+ wire T_879;
+ wire [20:0] T_881;
+ wire [20:0] T_882;
+ wire [24:0] T_883;
+ wire [24:0] T_885;
+ wire [24:0] T_886;
+ wire [23:0] T_887;
+ wire [23:0] T_889;
+ wire [24:0] mulAdd9C_A;
+ wire [17:0] T_891;
+ wire [17:0] T_893;
+ wire [18:0] T_894;
+ wire [19:0] T_895;
+ wire [18:0] loMulAdd9Out_A;
+ wire T_897;
+ wire [6:0] T_898;
+ wire [7:0] T_900;
+ wire [6:0] T_901;
+ wire [6:0] T_902;
+ wire [6:0] T_903;
+ wire [17:0] T_904;
+ wire [24:0] mulAdd9Out_A;
+ wire T_906;
+ wire T_907;
+ wire [24:0] T_908;
+ wire [14:0] T_909;
+ wire [14:0] T_911;
+ wire [8:0] zFractR0_A6_sqrt;
+ wire T_913;
+ wire [25:0] T_914;
+ wire [25:0] sqrR0_A5_sqrt;
+ wire T_916;
+ wire T_917;
+ wire [24:0] T_918;
+ wire [13:0] T_919;
+ wire [13:0] T_921;
+ wire [8:0] zFractR0_A4_div;
+ wire T_923;
+ wire T_924;
+ wire [24:0] T_925;
+ wire [22:0] T_926;
+ wire [22:0] T_928;
+ wire [8:0] zSigma0_A2;
+ wire [14:0] T_930;
+ wire [15:0] T_931;
+ wire [15:0] T_932;
+ wire [14:0] fractR1_A1;
+ wire [15:0] r1_A1;
+ wire T_936;
+ wire [16:0] T_937;
+ wire [16:0] ER1_A1_sqrt;
+ wire T_939;
+ wire [8:0] T_940;
+ wire [15:0] T_941;
+ wire T_942;
+ wire [15:0] T_943;
+ wire [24:0] T_944;
+ wire [20:0] T_945;
+ wire T_946;
+ wire T_947;
+ wire T_948;
+ wire T_949;
+ wire T_950;
+ wire [24:0] T_951;
+ wire [13:0] T_952;
+ wire [13:0] T_954;
+ wire [13:0] T_955;
+ wire [8:0] T_956;
+ wire [8:0] T_958;
+ wire [13:0] T_959;
+ wire [8:0] T_960;
+ wire [13:0] T_961;
+ wire T_962;
+ wire [8:0] T_963;
+ wire [8:0] T_965;
+ wire [13:0] T_966;
+ wire [13:0] T_967;
+ wire T_968;
+ wire T_969;
+ wire T_970;
+ wire T_971;
+ wire [8:0] T_972;
+ wire [8:0] T_973;
+ wire [8:0] T_974;
+ wire [8:0] T_976;
+ wire [8:0] T_977;
+ wire [8:0] T_978;
+ wire [8:0] T_979;
+ wire [8:0] T_981;
+ wire [8:0] T_982;
+ wire [7:0] T_984;
+ wire [8:0] T_985;
+ wire [8:0] T_987;
+ wire [8:0] T_988;
+ wire T_989;
+ wire T_990;
+ wire T_991;
+ wire T_992;
+ wire T_993;
+ wire T_994;
+ wire T_995;
+ wire [52:0] T_996;
+ wire [52:0] T_998;
+ wire T_999;
+ wire [52:0] T_1001;
+ wire [52:0] T_1002;
+ wire [52:0] T_1004;
+ wire [52:0] T_1005;
+ wire [33:0] T_1006;
+ wire [52:0] T_1007;
+ wire T_1008;
+ wire [45:0] T_1009;
+ wire [45:0] T_1011;
+ wire [52:0] T_1012;
+ wire [32:0] T_1013;
+ wire [45:0] T_1014;
+ wire [45:0] T_1016;
+ wire [52:0] T_1017;
+ wire [45:0] T_1018;
+ wire [45:0] T_1020;
+ wire [52:0] T_1021;
+ wire [52:0] T_1023;
+ wire [52:0] T_1024;
+ wire [53:0] T_1025;
+ wire T_1026;
+ wire T_1027;
+ wire T_1028;
+ wire T_1029;
+ wire T_1030;
+ wire T_1031;
+ wire [51:0] T_1032;
+ wire [51:0] T_1034;
+ wire [50:0] T_1035;
+ wire [50:0] T_1037;
+ wire [51:0] T_1038;
+ wire [52:0] T_1039;
+ wire [52:0] T_1041;
+ wire [52:0] T_1042;
+ wire [52:0] T_1043;
+ wire [29:0] T_1044;
+ wire [29:0] T_1046;
+ wire [52:0] T_1047;
+ wire [32:0] T_1049;
+ wire [52:0] T_1050;
+ wire [53:0] T_1051;
+ wire T_1052;
+ wire T_1053;
+ wire T_1054;
+ wire T_1055;
+ wire T_1056;
+ wire T_1057;
+ wire T_1058;
+ wire T_1059;
+ wire T_1060;
+ wire T_1061;
+ wire T_1062;
+ wire T_1063;
+ wire T_1064;
+ wire T_1065;
+ wire T_1066;
+ wire T_1067;
+ wire T_1068;
+ wire T_1069;
+ wire T_1070;
+ wire T_1071;
+ wire T_1072;
+ wire T_1073;
+ wire T_1074;
+ wire T_1075;
+ wire T_1076;
+ wire T_1077;
+ wire T_1078;
+ wire T_1079;
+ wire T_1080;
+ wire T_1081;
+ wire T_1082;
+ wire T_1083;
+ wire [1:0] T_1084;
+ wire [1:0] T_1085;
+ wire [3:0] T_1086;
+ wire [104:0] T_1087;
+ wire [104:0] T_1089;
+ wire [103:0] T_1090;
+ wire [103:0] T_1092;
+ wire [104:0] T_1093;
+ wire T_1094;
+ wire [104:0] T_1095;
+ wire [104:0] T_1097;
+ wire [104:0] T_1098;
+ wire T_1099;
+ wire T_1100;
+ wire [53:0] T_1101;
+ wire [53:0] T_1103;
+ wire [104:0] T_1104;
+ wire T_1105;
+ wire T_1106;
+ wire [1:0] T_1108;
+ wire T_1109;
+ wire T_1110;
+ wire T_1111;
+ wire T_1112;
+ wire [1:0] T_1113;
+ wire [1:0] T_1114;
+ wire T_1115;
+ wire [1:0] T_1117;
+ wire [1:0] T_1118;
+ wire [55:0] T_1119;
+ wire [55:0] T_1121;
+ wire [104:0] T_1122;
+ wire [31:0] ESqrR1_B8_sqrt;
+ wire [45:0] T_1124;
+ wire [45:0] T_1125;
+ wire [45:0] T_1127;
+ wire [32:0] sqrSigma1_B1;
+ wire [57:0] T_1129;
+ wire T_1130;
+ wire E_C1_div;
+ wire T_1132;
+ wire T_1133;
+ wire T_1134;
+ wire [53:0] T_1135;
+ wire [53:0] T_1136;
+ wire [53:0] T_1138;
+ wire T_1139;
+ wire [52:0] T_1141;
+ wire [52:0] T_1142;
+ wire [53:0] T_1143;
+ wire [53:0] T_1145;
+ wire [53:0] T_1146;
+ wire [53:0] T_1147;
+ wire [53:0] T_1148;
+ wire [53:0] T_1150;
+ wire [53:0] sigT_C1;
+ wire [55:0] remT_E2;
+ wire T_1153;
+ wire T_1154;
+ wire [30:0] T_1155;
+ wire [52:0] T_1156;
+ wire T_1157;
+ wire T_1158;
+ wire T_1159;
+ wire T_1160;
+ wire [53:0] T_1161;
+ wire T_1163;
+ wire T_1164;
+ wire [1:0] T_1165;
+ wire T_1167;
+ wire T_1168;
+ wire T_1169;
+ wire T_1170;
+ wire T_1171;
+ wire [13:0] T_1173;
+ wire T_1174;
+ wire T_1175;
+ wire T_1176;
+ wire [13:0] T_1178;
+ wire [13:0] T_1179;
+ wire [12:0] T_1180;
+ wire [13:0] T_1182;
+ wire [12:0] T_1183;
+ wire [12:0] T_1185;
+ wire [13:0] sExpX_E;
+ wire [12:0] posExpX_E;
+ wire [12:0] T_1188;
+ wire [8192:0] GEN_0;
+ wire [8192:0] T_1190;
+ wire [52:0] T_1191;
+ wire [31:0] T_1192;
+ wire [31:0] T_1195;
+ wire [31:0] T_1196;
+ wire [15:0] T_1197;
+ wire [31:0] T_1198;
+ wire [15:0] T_1199;
+ wire [31:0] T_1200;
+ wire [31:0] T_1201;
+ wire [31:0] T_1202;
+ wire [31:0] T_1203;
+ wire [23:0] T_1204;
+ wire [31:0] T_1205;
+ wire [31:0] T_1206;
+ wire [23:0] T_1207;
+ wire [31:0] T_1208;
+ wire [23:0] T_1209;
+ wire [31:0] T_1210;
+ wire [31:0] T_1211;
+ wire [31:0] T_1212;
+ wire [31:0] T_1213;
+ wire [27:0] T_1214;
+ wire [31:0] T_1215;
+ wire [31:0] T_1216;
+ wire [27:0] T_1217;
+ wire [31:0] T_1218;
+ wire [27:0] T_1219;
+ wire [31:0] T_1220;
+ wire [31:0] T_1221;
+ wire [31:0] T_1222;
+ wire [31:0] T_1223;
+ wire [29:0] T_1224;
+ wire [31:0] T_1225;
+ wire [31:0] T_1226;
+ wire [29:0] T_1227;
+ wire [31:0] T_1228;
+ wire [29:0] T_1229;
+ wire [31:0] T_1230;
+ wire [31:0] T_1231;
+ wire [31:0] T_1232;
+ wire [31:0] T_1233;
+ wire [30:0] T_1234;
+ wire [31:0] T_1235;
+ wire [31:0] T_1236;
+ wire [30:0] T_1237;
+ wire [31:0] T_1238;
+ wire [30:0] T_1239;
+ wire [31:0] T_1240;
+ wire [31:0] T_1241;
+ wire [31:0] T_1242;
+ wire [31:0] T_1243;
+ wire [20:0] T_1244;
+ wire [15:0] T_1245;
+ wire [15:0] T_1248;
+ wire [15:0] T_1249;
+ wire [7:0] T_1250;
+ wire [15:0] T_1251;
+ wire [7:0] T_1252;
+ wire [15:0] T_1253;
+ wire [15:0] T_1254;
+ wire [15:0] T_1255;
+ wire [15:0] T_1256;
+ wire [11:0] T_1257;
+ wire [15:0] T_1258;
+ wire [15:0] T_1259;
+ wire [11:0] T_1260;
+ wire [15:0] T_1261;
+ wire [11:0] T_1262;
+ wire [15:0] T_1263;
+ wire [15:0] T_1264;
+ wire [15:0] T_1265;
+ wire [15:0] T_1266;
+ wire [13:0] T_1267;
+ wire [15:0] T_1268;
+ wire [15:0] T_1269;
+ wire [13:0] T_1270;
+ wire [15:0] T_1271;
+ wire [13:0] T_1272;
+ wire [15:0] T_1273;
+ wire [15:0] T_1274;
+ wire [15:0] T_1275;
+ wire [15:0] T_1276;
+ wire [14:0] T_1277;
+ wire [15:0] T_1278;
+ wire [15:0] T_1279;
+ wire [14:0] T_1280;
+ wire [15:0] T_1281;
+ wire [14:0] T_1282;
+ wire [15:0] T_1283;
+ wire [15:0] T_1284;
+ wire [15:0] T_1285;
+ wire [15:0] T_1286;
+ wire [4:0] T_1287;
+ wire [3:0] T_1288;
+ wire [1:0] T_1289;
+ wire T_1290;
+ wire T_1291;
+ wire [1:0] T_1292;
+ wire [1:0] T_1293;
+ wire T_1294;
+ wire T_1295;
+ wire [1:0] T_1296;
+ wire [3:0] T_1297;
+ wire T_1298;
+ wire [4:0] T_1299;
+ wire [20:0] T_1300;
+ wire [52:0] roundMask_E;
+ wire [53:0] T_1303;
+ wire [53:0] T_1304;
+ wire [53:0] T_1306;
+ wire [53:0] incrPosMask_E;
+ wire [52:0] T_1308;
+ wire [52:0] T_1309;
+ wire hiRoundPosBitT_E;
+ wire [51:0] T_1312;
+ wire [52:0] T_1313;
+ wire all0sHiRoundExtraT_E;
+ wire [52:0] T_1316;
+ wire [51:0] T_1317;
+ wire [52:0] T_1318;
+ wire all1sHiRoundExtraT_E;
+ wire T_1321;
+ wire T_1322;
+ wire T_1323;
+ wire all1sHiRoundT_E;
+ wire [54:0] T_1326;
+ wire [53:0] T_1327;
+ wire [54:0] T_1328;
+ wire [53:0] sigAdjT_E;
+ wire [52:0] T_1331;
+ wire [53:0] T_1332;
+ wire [53:0] sigY0_E;
+ wire [53:0] T_1335;
+ wire [53:0] T_1336;
+ wire [54:0] T_1338;
+ wire [53:0] sigY1_E;
+ wire T_1340;
+ wire T_1341;
+ wire T_1342;
+ wire trueLtX_E1;
+ wire T_1344;
+ wire T_1345;
+ wire T_1346;
+ wire T_1347;
+ wire T_1348;
+ wire hiRoundPosBit_E1;
+ wire T_1350;
+ wire T_1351;
+ wire T_1352;
+ wire T_1353;
+ wire anyRoundExtra_E1;
+ wire T_1355;
+ wire T_1356;
+ wire T_1357;
+ wire [53:0] roundEvenMask_E1;
+ wire T_1360;
+ wire T_1361;
+ wire T_1362;
+ wire T_1363;
+ wire T_1364;
+ wire T_1365;
+ wire T_1366;
+ wire T_1367;
+ wire T_1368;
+ wire T_1369;
+ wire T_1370;
+ wire T_1371;
+ wire T_1372;
+ wire T_1373;
+ wire T_1374;
+ wire T_1375;
+ wire T_1376;
+ wire T_1377;
+ wire T_1378;
+ wire T_1379;
+ wire T_1380;
+ wire T_1381;
+ wire T_1382;
+ wire T_1383;
+ wire [53:0] T_1384;
+ wire [53:0] T_1385;
+ wire [53:0] sigY_E1;
+ wire [51:0] fractY_E1;
+ wire inexactY_E1;
+ wire T_1389;
+ wire T_1390;
+ wire [13:0] T_1392;
+ wire T_1393;
+ wire T_1394;
+ wire T_1395;
+ wire T_1396;
+ wire [13:0] T_1398;
+ wire [13:0] T_1399;
+ wire T_1400;
+ wire T_1401;
+ wire T_1402;
+ wire T_1403;
+ wire T_1404;
+ wire [13:0] T_1406;
+ wire [13:0] T_1407;
+ wire T_1408;
+ wire T_1409;
+ wire [12:0] T_1410;
+ wire [13:0] T_1412;
+ wire [12:0] T_1413;
+ wire [12:0] T_1415;
+ wire [13:0] sExpY_E1;
+ wire [11:0] expY_E1;
+ wire T_1418;
+ wire T_1419;
+ wire [2:0] T_1421;
+ wire T_1422;
+ wire overflowY_E1;
+ wire T_1424;
+ wire [12:0] T_1425;
+ wire T_1427;
+ wire totalUnderflowY_E1;
+ wire T_1430;
+ wire T_1431;
+ wire underflowY_E1;
+ wire T_1433;
+ wire T_1434;
+ wire T_1435;
+ wire T_1436;
+ wire T_1437;
+ wire T_1438;
+ wire T_1439;
+ wire notSigNaN_invalid_PC;
+ wire T_1441;
+ wire T_1442;
+ wire T_1443;
+ wire invalid_PC;
+ wire T_1445;
+ wire T_1446;
+ wire T_1447;
+ wire T_1448;
+ wire T_1449;
+ wire infinity_PC;
+ wire overflow_E1;
+ wire underflow_E1;
+ wire T_1453;
+ wire T_1454;
+ wire inexact_E1;
+ wire T_1456;
+ wire T_1457;
+ wire T_1458;
+ wire T_1459;
+ wire notSpecial_isZeroOut_E1;
+ wire T_1461;
+ wire pegMinFiniteMagOut_E1;
+ wire T_1463;
+ wire pegMaxFiniteMagOut_E1;
+ wire T_1465;
+ wire T_1466;
+ wire T_1467;
+ wire notNaN_isInfOut_E1;
+ wire T_1469;
+ wire T_1470;
+ wire T_1471;
+ wire isNaNOut_PC;
+ wire T_1473;
+ wire T_1474;
+ wire T_1475;
+ wire signOut_PC;
+ wire [11:0] T_1478;
+ wire [11:0] T_1480;
+ wire [11:0] T_1481;
+ wire [11:0] T_1482;
+ wire [11:0] T_1484;
+ wire [11:0] T_1486;
+ wire [11:0] T_1487;
+ wire [11:0] T_1488;
+ wire [11:0] T_1490;
+ wire [11:0] T_1492;
+ wire [11:0] T_1493;
+ wire [11:0] T_1494;
+ wire [11:0] T_1496;
+ wire [11:0] T_1498;
+ wire [11:0] T_1499;
+ wire [11:0] T_1500;
+ wire [11:0] T_1503;
+ wire [11:0] T_1504;
+ wire [11:0] T_1507;
+ wire [11:0] T_1508;
+ wire [11:0] T_1511;
+ wire [11:0] T_1512;
+ wire [11:0] T_1515;
+ wire [11:0] expOut_E1;
+ wire T_1517;
+ wire T_1518;
+ wire [51:0] T_1520;
+ wire [52:0] T_1522;
+ wire [51:0] T_1523;
+ wire [51:0] T_1524;
+ wire [51:0] T_1525;
+ wire [51:0] fractOut_E1;
+ wire [63:0] T_1527;
+ wire [64:0] T_1528;
+ wire [1:0] T_1529;
+ wire [1:0] T_1530;
+ wire [2:0] T_1531;
+ wire [4:0] T_1532;
+ assign io_inReady_div = T_227;
+ assign io_inReady_sqrt = T_237;
+ assign io_outValid_div = T_471;
+ assign io_outValid_sqrt = T_472;
+ assign io_out = T_1528;
+ assign io_exceptionFlags = T_1532;
+ assign io_usingMulAdd = T_1086;
+ assign io_latchMulAddA_0 = T_995;
+ assign io_mulAddA_0 = T_1025;
+ assign io_latchMulAddB_0 = T_1031;
+ assign io_mulAddB_0 = T_1051;
+ assign io_mulAddC_2 = T_1122;
+ assign ready_PA = T_350;
+ assign ready_PB = T_391;
+ assign ready_PC = T_469;
+ assign leaving_PA = T_348;
+ assign leaving_PB = T_389;
+ assign leaving_PC = T_467;
+ assign cyc_B10_sqrt = T_523;
+ assign cyc_B9_sqrt = T_525;
+ assign cyc_B8_sqrt = T_527;
+ assign cyc_B7_sqrt = T_529;
+ assign cyc_B6 = T_531;
+ assign cyc_B5 = T_533;
+ assign cyc_B4 = T_535;
+ assign cyc_B3 = T_537;
+ assign cyc_B2 = T_539;
+ assign cyc_B1 = T_541;
+ assign cyc_B6_div = T_544;
+ assign cyc_B5_div = T_547;
+ assign cyc_B4_div = T_550;
+ assign cyc_B3_div = T_552;
+ assign cyc_B2_div = T_554;
+ assign cyc_B1_div = T_556;
+ assign cyc_B6_sqrt = T_558;
+ assign cyc_B5_sqrt = T_560;
+ assign cyc_B4_sqrt = T_562;
+ assign cyc_B3_sqrt = T_563;
+ assign cyc_B2_sqrt = T_564;
+ assign cyc_B1_sqrt = T_565;
+ assign cyc_C5 = T_579;
+ assign cyc_C4 = T_581;
+ assign valid_normalCase_leaving_PB = T_583;
+ assign cyc_C2 = T_585;
+ assign cyc_C1 = T_587;
+ assign cyc_E4 = T_612;
+ assign cyc_E3 = T_614;
+ assign cyc_E2 = T_616;
+ assign cyc_E1 = T_618;
+ assign zSigma1_B4 = T_1127;
+ assign sigXNU_B3_CX = T_1129;
+ assign zComplSigT_C1_sqrt = T_1150;
+ assign zComplSigT_C1 = T_1146;
+ assign T_210 = ~ cyc_B7_sqrt;
+ assign T_211 = ready_PA & T_210;
+ assign T_212 = ~ cyc_B6_sqrt;
+ assign T_213 = T_211 & T_212;
+ assign T_214 = ~ cyc_B5_sqrt;
+ assign T_215 = T_213 & T_214;
+ assign T_216 = ~ cyc_B4_sqrt;
+ assign T_217 = T_215 & T_216;
+ assign T_218 = ~ cyc_B3;
+ assign T_219 = T_217 & T_218;
+ assign T_220 = ~ cyc_B2;
+ assign T_221 = T_219 & T_220;
+ assign T_222 = ~ cyc_B1_sqrt;
+ assign T_223 = T_221 & T_222;
+ assign T_224 = ~ cyc_C5;
+ assign T_225 = T_223 & T_224;
+ assign T_226 = ~ cyc_C4;
+ assign T_227 = T_225 & T_226;
+ assign T_228 = ~ cyc_B6_sqrt;
+ assign T_229 = ready_PA & T_228;
+ assign T_230 = ~ cyc_B5_sqrt;
+ assign T_231 = T_229 & T_230;
+ assign T_232 = ~ cyc_B4_sqrt;
+ assign T_233 = T_231 & T_232;
+ assign T_234 = ~ cyc_B2_div;
+ assign T_235 = T_233 & T_234;
+ assign T_236 = ~ cyc_B1_sqrt;
+ assign T_237 = T_235 & T_236;
+ assign T_238 = io_inReady_div & io_inValid;
+ assign T_239 = ~ io_sqrtOp;
+ assign cyc_S_div = T_238 & T_239;
+ assign T_241 = io_inReady_sqrt & io_inValid;
+ assign cyc_S_sqrt = T_241 & io_sqrtOp;
+ assign cyc_S = cyc_S_div | cyc_S_sqrt;
+ assign signA_S = io_a[64];
+ assign expA_S = io_a[63:52];
+ assign fractA_S = io_a[51:0];
+ assign specialCodeA_S = expA_S[11:9];
+ assign isZeroA_S = specialCodeA_S == 3'h0;
+ assign T_250 = specialCodeA_S[2:1];
+ assign isSpecialA_S = T_250 == 2'h3;
+ assign signB_S = io_b[64];
+ assign expB_S = io_b[63:52];
+ assign fractB_S = io_b[51:0];
+ assign specialCodeB_S = expB_S[11:9];
+ assign isZeroB_S = specialCodeB_S == 3'h0;
+ assign T_259 = specialCodeB_S[2:1];
+ assign isSpecialB_S = T_259 == 2'h3;
+ assign T_262 = signA_S ^ signB_S;
+ assign sign_S = io_sqrtOp ? signB_S : T_262;
+ assign T_264 = ~ isSpecialA_S;
+ assign T_265 = ~ isSpecialB_S;
+ assign T_266 = T_264 & T_265;
+ assign T_267 = ~ isZeroA_S;
+ assign T_268 = T_266 & T_267;
+ assign T_269 = ~ isZeroB_S;
+ assign normalCase_S_div = T_268 & T_269;
+ assign T_271 = ~ isSpecialB_S;
+ assign T_272 = ~ isZeroB_S;
+ assign T_273 = T_271 & T_272;
+ assign T_274 = ~ signB_S;
+ assign normalCase_S_sqrt = T_273 & T_274;
+ assign normalCase_S = io_sqrtOp ? normalCase_S_sqrt : normalCase_S_div;
+ assign entering_PA_normalCase_div = cyc_S_div & normalCase_S_div;
+ assign entering_PA_normalCase_sqrt = cyc_S_sqrt & normalCase_S_sqrt;
+ assign entering_PA_normalCase = entering_PA_normalCase_div | entering_PA_normalCase_sqrt;
+ assign T_280 = ~ ready_PB;
+ assign T_281 = valid_PA | T_280;
+ assign T_282 = cyc_S & T_281;
+ assign entering_PA = entering_PA_normalCase | T_282;
+ assign T_284 = ~ normalCase_S;
+ assign T_285 = cyc_S & T_284;
+ assign T_286 = ~ valid_PA;
+ assign T_287 = T_285 & T_286;
+ assign T_288 = ~ valid_PB;
+ assign T_289 = ~ ready_PC;
+ assign T_290 = T_288 & T_289;
+ assign T_291 = leaving_PB | T_290;
+ assign entering_PB_S = T_287 & T_291;
+ assign T_293 = ~ normalCase_S;
+ assign T_294 = cyc_S & T_293;
+ assign T_295 = ~ valid_PA;
+ assign T_296 = T_294 & T_295;
+ assign T_297 = ~ valid_PB;
+ assign T_298 = T_296 & T_297;
+ assign entering_PC_S = T_298 & ready_PC;
+ assign T_300 = entering_PA | leaving_PA;
+ assign T_301 = fractB_S[51];
+ assign T_302 = ~ io_sqrtOp;
+ assign T_303 = entering_PA & T_302;
+ assign T_304 = fractA_S[51];
+ assign T_305 = expB_S[11];
+ assign T_307 = 3'h0 - T_305;
+ assign T_308 = T_307[2:0];
+ assign T_309 = expB_S[10:0];
+ assign T_310 = ~ T_309;
+ assign T_311 = {T_308,T_310};
+ assign T_312 = expA_S + T_311;
+ assign T_313 = T_312[13:0];
+ assign T_314 = io_sqrtOp ? expB_S : T_313;
+ assign T_315 = fractB_S[50:0];
+ assign T_316 = fractA_S[50:0];
+ assign isZeroA_PA = specialCodeA_PA == 3'h0;
+ assign T_319 = specialCodeA_PA[2:1];
+ assign isSpecialA_PA = T_319 == 2'h3;
+ assign T_323 = {fractA_51_PA,fractA_other_PA};
+ assign sigA_PA = {1'h1,T_323};
+ assign isZeroB_PA = specialCodeB_PA == 3'h0;
+ assign T_327 = specialCodeB_PA[2:1];
+ assign isSpecialB_PA = T_327 == 2'h3;
+ assign T_331 = {fractB_51_PA,fractB_other_PA};
+ assign sigB_PA = {1'h1,T_331};
+ assign T_333 = ~ isSpecialB_PA;
+ assign T_334 = ~ isZeroB_PA;
+ assign T_335 = T_333 & T_334;
+ assign T_336 = ~ sign_PA;
+ assign T_337 = T_335 & T_336;
+ assign T_338 = ~ isSpecialA_PA;
+ assign T_339 = ~ isSpecialB_PA;
+ assign T_340 = T_338 & T_339;
+ assign T_341 = ~ isZeroA_PA;
+ assign T_342 = T_340 & T_341;
+ assign T_343 = ~ isZeroB_PA;
+ assign T_344 = T_342 & T_343;
+ assign normalCase_PA = sqrtOp_PA ? T_337 : T_344;
+ assign valid_normalCase_leaving_PA = cyc_B4_div | cyc_B7_sqrt;
+ assign valid_leaving_PA = normalCase_PA ? valid_normalCase_leaving_PA : ready_PB;
+ assign T_348 = valid_PA & valid_leaving_PA;
+ assign T_349 = ~ valid_PA;
+ assign T_350 = T_349 | valid_leaving_PA;
+ assign T_351 = valid_PA & normalCase_PA;
+ assign entering_PB_normalCase = T_351 & valid_normalCase_leaving_PA;
+ assign entering_PB = entering_PB_S | leaving_PA;
+ assign T_354 = entering_PB | leaving_PB;
+ assign T_355 = valid_PA ? sqrtOp_PA : io_sqrtOp;
+ assign T_356 = valid_PA ? sign_PA : sign_S;
+ assign T_357 = valid_PA ? specialCodeA_PA : specialCodeA_S;
+ assign T_358 = fractA_S[51];
+ assign T_359 = valid_PA ? fractA_51_PA : T_358;
+ assign T_360 = valid_PA ? specialCodeB_PA : specialCodeB_S;
+ assign T_361 = fractB_S[51];
+ assign T_362 = valid_PA ? fractB_51_PA : T_361;
+ assign T_363 = valid_PA ? roundingMode_PA : io_roundingMode;
+ assign T_364 = fractA_other_PA[0];
+ assign isZeroA_PB = specialCodeA_PB == 3'h0;
+ assign T_367 = specialCodeA_PB[2:1];
+ assign isSpecialA_PB = T_367 == 2'h3;
+ assign isZeroB_PB = specialCodeB_PB == 3'h0;
+ assign T_372 = specialCodeB_PB[2:1];
+ assign isSpecialB_PB = T_372 == 2'h3;
+ assign T_375 = ~ isSpecialB_PB;
+ assign T_376 = ~ isZeroB_PB;
+ assign T_377 = T_375 & T_376;
+ assign T_378 = ~ sign_PB;
+ assign T_379 = T_377 & T_378;
+ assign T_380 = ~ isSpecialA_PB;
+ assign T_381 = ~ isSpecialB_PB;
+ assign T_382 = T_380 & T_381;
+ assign T_383 = ~ isZeroA_PB;
+ assign T_384 = T_382 & T_383;
+ assign T_385 = ~ isZeroB_PB;
+ assign T_386 = T_384 & T_385;
+ assign normalCase_PB = sqrtOp_PB ? T_379 : T_386;
+ assign valid_leaving_PB = normalCase_PB ? valid_normalCase_leaving_PB : ready_PC;
+ assign T_389 = valid_PB & valid_leaving_PB;
+ assign T_390 = ~ valid_PB;
+ assign T_391 = T_390 | valid_leaving_PB;
+ assign T_392 = valid_PB & normalCase_PB;
+ assign entering_PC_normalCase = T_392 & valid_normalCase_leaving_PB;
+ assign entering_PC = entering_PC_S | leaving_PB;
+ assign T_395 = entering_PC | leaving_PC;
+ assign T_396 = valid_PB ? sqrtOp_PB : io_sqrtOp;
+ assign T_397 = valid_PB ? sign_PB : sign_S;
+ assign T_398 = valid_PB ? specialCodeA_PB : specialCodeA_S;
+ assign T_399 = fractA_S[51];
+ assign T_400 = valid_PB ? fractA_51_PB : T_399;
+ assign T_401 = valid_PB ? specialCodeB_PB : specialCodeB_S;
+ assign T_402 = fractB_S[51];
+ assign T_403 = valid_PB ? fractB_51_PB : T_402;
+ assign T_404 = valid_PB ? roundingMode_PB : io_roundingMode;
+ assign isZeroA_PC = specialCodeA_PC == 3'h0;
+ assign T_407 = specialCodeA_PC[2:1];
+ assign isSpecialA_PC = T_407 == 2'h3;
+ assign T_410 = specialCodeA_PC[0];
+ assign T_411 = ~ T_410;
+ assign isInfA_PC = isSpecialA_PC & T_411;
+ assign T_413 = specialCodeA_PC[0];
+ assign isNaNA_PC = isSpecialA_PC & T_413;
+ assign T_415 = ~ fractA_51_PC;
+ assign isSigNaNA_PC = isNaNA_PC & T_415;
+ assign isZeroB_PC = specialCodeB_PC == 3'h0;
+ assign T_419 = specialCodeB_PC[2:1];
+ assign isSpecialB_PC = T_419 == 2'h3;
+ assign T_422 = specialCodeB_PC[0];
+ assign T_423 = ~ T_422;
+ assign isInfB_PC = isSpecialB_PC & T_423;
+ assign T_425 = specialCodeB_PC[0];
+ assign isNaNB_PC = isSpecialB_PC & T_425;
+ assign T_427 = ~ fractB_51_PC;
+ assign isSigNaNB_PC = isNaNB_PC & T_427;
+ assign T_430 = {fractB_51_PC,fractB_other_PC};
+ assign sigB_PC = {1'h1,T_430};
+ assign T_432 = ~ isSpecialB_PC;
+ assign T_433 = ~ isZeroB_PC;
+ assign T_434 = T_432 & T_433;
+ assign T_435 = ~ sign_PC;
+ assign T_436 = T_434 & T_435;
+ assign T_437 = ~ isSpecialA_PC;
+ assign T_438 = ~ isSpecialB_PC;
+ assign T_439 = T_437 & T_438;
+ assign T_440 = ~ isZeroA_PC;
+ assign T_441 = T_439 & T_440;
+ assign T_442 = ~ isZeroB_PC;
+ assign T_443 = T_441 & T_442;
+ assign normalCase_PC = sqrtOp_PC ? T_436 : T_443;
+ assign T_446 = exp_PC + 2'h2;
+ assign expP2_PC = T_446[13:0];
+ assign T_448 = exp_PC[0];
+ assign T_449 = expP2_PC[13:1];
+ assign T_451 = {T_449,1'h0};
+ assign T_452 = exp_PC[13:1];
+ assign T_454 = {T_452,1'h1};
+ assign expP1_PC = T_448 ? T_451 : T_454;
+ assign roundingMode_near_even_PC = roundingMode_PC == 2'h0;
+ assign roundingMode_minMag_PC = roundingMode_PC == 2'h1;
+ assign roundingMode_min_PC = roundingMode_PC == 2'h2;
+ assign roundingMode_max_PC = roundingMode_PC == 2'h3;
+ assign roundMagUp_PC = sign_PC ? roundingMode_min_PC : roundingMode_max_PC;
+ assign overflowY_roundMagUp_PC = roundingMode_near_even_PC | roundMagUp_PC;
+ assign T_462 = ~ roundMagUp_PC;
+ assign T_463 = ~ roundingMode_near_even_PC;
+ assign roundMagDown_PC = T_462 & T_463;
+ assign T_465 = ~ normalCase_PC;
+ assign valid_leaving_PC = T_465 | cyc_E1;
+ assign T_467 = valid_PC & valid_leaving_PC;
+ assign T_468 = ~ valid_PC;
+ assign T_469 = T_468 | valid_leaving_PC;
+ assign T_470 = ~ sqrtOp_PC;
+ assign T_471 = leaving_PC & T_470;
+ assign T_472 = leaving_PC & sqrtOp_PC;
+ assign T_474 = cycleNum_A != 1'h0;
+ assign T_475 = entering_PA_normalCase | T_474;
+ assign T_478 = entering_PA_normalCase_div ? 2'h3 : 1'h0;
+ assign T_481 = entering_PA_normalCase_sqrt ? 3'h6 : 1'h0;
+ assign T_482 = T_478 | T_481;
+ assign T_483 = ~ entering_PA_normalCase;
+ assign T_485 = cycleNum_A - 1'h1;
+ assign T_486 = T_485[2:0];
+ assign T_488 = T_483 ? T_486 : 1'h0;
+ assign T_489 = T_482 | T_488;
+ assign cyc_A6_sqrt = cycleNum_A == 3'h6;
+ assign cyc_A5_sqrt = cycleNum_A == 3'h5;
+ assign cyc_A4_sqrt = cycleNum_A == 3'h4;
+ assign cyc_A4 = cyc_A4_sqrt | entering_PA_normalCase_div;
+ assign cyc_A3 = cycleNum_A == 2'h3;
+ assign cyc_A2 = cycleNum_A == 2'h2;
+ assign cyc_A1 = cycleNum_A == 1'h1;
+ assign T_503 = ~ sqrtOp_PA;
+ assign cyc_A3_div = cyc_A3 & T_503;
+ assign T_505 = ~ sqrtOp_PA;
+ assign cyc_A2_div = cyc_A2 & T_505;
+ assign T_507 = ~ sqrtOp_PA;
+ assign cyc_A1_div = cyc_A1 & T_507;
+ assign cyc_A3_sqrt = cyc_A3 & sqrtOp_PA;
+ assign cyc_A2_sqrt = cyc_A2 & sqrtOp_PA;
+ assign cyc_A1_sqrt = cyc_A1 & sqrtOp_PA;
+ assign T_513 = cycleNum_B != 1'h0;
+ assign T_514 = cyc_A1 | T_513;
+ assign T_517 = sqrtOp_PA ? 4'ha : 3'h6;
+ assign T_519 = cycleNum_B - 1'h1;
+ assign T_520 = T_519[3:0];
+ assign T_521 = cyc_A1 ? T_517 : T_520;
+ assign T_523 = cycleNum_B == 4'ha;
+ assign T_525 = cycleNum_B == 4'h9;
+ assign T_527 = cycleNum_B == 4'h8;
+ assign T_529 = cycleNum_B == 3'h7;
+ assign T_531 = cycleNum_B == 3'h6;
+ assign T_533 = cycleNum_B == 3'h5;
+ assign T_535 = cycleNum_B == 3'h4;
+ assign T_537 = cycleNum_B == 2'h3;
+ assign T_539 = cycleNum_B == 2'h2;
+ assign T_541 = cycleNum_B == 1'h1;
+ assign T_542 = cyc_B6 & valid_PA;
+ assign T_543 = ~ sqrtOp_PA;
+ assign T_544 = T_542 & T_543;
+ assign T_545 = cyc_B5 & valid_PA;
+ assign T_546 = ~ sqrtOp_PA;
+ assign T_547 = T_545 & T_546;
+ assign T_548 = cyc_B4 & valid_PA;
+ assign T_549 = ~ sqrtOp_PA;
+ assign T_550 = T_548 & T_549;
+ assign T_551 = ~ sqrtOp_PB;
+ assign T_552 = cyc_B3 & T_551;
+ assign T_553 = ~ sqrtOp_PB;
+ assign T_554 = cyc_B2 & T_553;
+ assign T_555 = ~ sqrtOp_PB;
+ assign T_556 = cyc_B1 & T_555;
+ assign T_557 = cyc_B6 & valid_PB;
+ assign T_558 = T_557 & sqrtOp_PB;
+ assign T_559 = cyc_B5 & valid_PB;
+ assign T_560 = T_559 & sqrtOp_PB;
+ assign T_561 = cyc_B4 & valid_PB;
+ assign T_562 = T_561 & sqrtOp_PB;
+ assign T_563 = cyc_B3 & sqrtOp_PB;
+ assign T_564 = cyc_B2 & sqrtOp_PB;
+ assign T_565 = cyc_B1 & sqrtOp_PB;
+ assign T_567 = cycleNum_C != 1'h0;
+ assign T_568 = cyc_B1 | T_567;
+ assign T_571 = sqrtOp_PB ? 3'h6 : 3'h5;
+ assign T_573 = cycleNum_C - 1'h1;
+ assign T_574 = T_573[2:0];
+ assign T_575 = cyc_B1 ? T_571 : T_574;
+ assign cyc_C6_sqrt = cycleNum_C == 3'h6;
+ assign T_579 = cycleNum_C == 3'h5;
+ assign T_581 = cycleNum_C == 3'h4;
+ assign T_583 = cycleNum_C == 2'h3;
+ assign T_585 = cycleNum_C == 2'h2;
+ assign T_587 = cycleNum_C == 1'h1;
+ assign T_588 = ~ sqrtOp_PB;
+ assign cyc_C5_div = cyc_C5 & T_588;
+ assign T_590 = ~ sqrtOp_PB;
+ assign cyc_C4_div = cyc_C4 & T_590;
+ assign T_592 = ~ sqrtOp_PB;
+ assign cyc_C3_div = valid_normalCase_leaving_PB & T_592;
+ assign T_594 = ~ sqrtOp_PC;
+ assign cyc_C2_div = cyc_C2 & T_594;
+ assign T_596 = ~ sqrtOp_PC;
+ assign cyc_C1_div = cyc_C1 & T_596;
+ assign cyc_C5_sqrt = cyc_C5 & sqrtOp_PB;
+ assign cyc_C4_sqrt = cyc_C4 & sqrtOp_PB;
+ assign cyc_C3_sqrt = valid_normalCase_leaving_PB & sqrtOp_PB;
+ assign cyc_C2_sqrt = cyc_C2 & sqrtOp_PC;
+ assign cyc_C1_sqrt = cyc_C1 & sqrtOp_PC;
+ assign T_604 = cycleNum_E != 1'h0;
+ assign T_605 = cyc_C1 | T_604;
+ assign T_608 = cycleNum_E - 1'h1;
+ assign T_609 = T_608[2:0];
+ assign T_610 = cyc_C1 ? 3'h4 : T_609;
+ assign T_612 = cycleNum_E == 3'h4;
+ assign T_614 = cycleNum_E == 2'h3;
+ assign T_616 = cycleNum_E == 2'h2;
+ assign T_618 = cycleNum_E == 1'h1;
+ assign T_619 = ~ sqrtOp_PC;
+ assign cyc_E4_div = cyc_E4 & T_619;
+ assign T_621 = ~ sqrtOp_PC;
+ assign cyc_E3_div = cyc_E3 & T_621;
+ assign T_623 = ~ sqrtOp_PC;
+ assign cyc_E2_div = cyc_E2 & T_623;
+ assign T_625 = ~ sqrtOp_PC;
+ assign cyc_E1_div = cyc_E1 & T_625;
+ assign cyc_E4_sqrt = cyc_E4 & sqrtOp_PC;
+ assign cyc_E3_sqrt = cyc_E3 & sqrtOp_PC;
+ assign cyc_E2_sqrt = cyc_E2 & sqrtOp_PC;
+ assign cyc_E1_sqrt = cyc_E1 & sqrtOp_PC;
+ assign zFractB_A4_div = entering_PA_normalCase_div ? fractB_S : 1'h0;
+ assign T_633 = fractB_S[51:49];
+ assign T_635 = T_633 == 1'h0;
+ assign zLinPiece_0_A4_div = entering_PA_normalCase_div & T_635;
+ assign T_637 = fractB_S[51:49];
+ assign T_639 = T_637 == 1'h1;
+ assign zLinPiece_1_A4_div = entering_PA_normalCase_div & T_639;
+ assign T_641 = fractB_S[51:49];
+ assign T_643 = T_641 == 2'h2;
+ assign zLinPiece_2_A4_div = entering_PA_normalCase_div & T_643;
+ assign T_645 = fractB_S[51:49];
+ assign T_647 = T_645 == 2'h3;
+ assign zLinPiece_3_A4_div = entering_PA_normalCase_div & T_647;
+ assign T_649 = fractB_S[51:49];
+ assign T_651 = T_649 == 3'h4;
+ assign zLinPiece_4_A4_div = entering_PA_normalCase_div & T_651;
+ assign T_653 = fractB_S[51:49];
+ assign T_655 = T_653 == 3'h5;
+ assign zLinPiece_5_A4_div = entering_PA_normalCase_div & T_655;
+ assign T_657 = fractB_S[51:49];
+ assign T_659 = T_657 == 3'h6;
+ assign zLinPiece_6_A4_div = entering_PA_normalCase_div & T_659;
+ assign T_661 = fractB_S[51:49];
+ assign T_663 = T_661 == 3'h7;
+ assign zLinPiece_7_A4_div = entering_PA_normalCase_div & T_663;
+ assign T_667 = zLinPiece_0_A4_div ? 9'h1c7 : 1'h0;
+ assign T_670 = zLinPiece_1_A4_div ? 9'h16c : 1'h0;
+ assign T_671 = T_667 | T_670;
+ assign T_674 = zLinPiece_2_A4_div ? 9'h12a : 1'h0;
+ assign T_675 = T_671 | T_674;
+ assign T_678 = zLinPiece_3_A4_div ? 9'hf8 : 1'h0;
+ assign T_679 = T_675 | T_678;
+ assign T_682 = zLinPiece_4_A4_div ? 9'hd2 : 1'h0;
+ assign T_683 = T_679 | T_682;
+ assign T_686 = zLinPiece_5_A4_div ? 9'hb4 : 1'h0;
+ assign T_687 = T_683 | T_686;
+ assign T_690 = zLinPiece_6_A4_div ? 9'h9c : 1'h0;
+ assign T_691 = T_687 | T_690;
+ assign T_694 = zLinPiece_7_A4_div ? 9'h89 : 1'h0;
+ assign zK1_A4_div = T_691 | T_694;
+ assign T_697 = ~ 12'hfe3;
+ assign T_699 = zLinPiece_0_A4_div ? T_697 : 1'h0;
+ assign T_701 = ~ 12'hc5d;
+ assign T_703 = zLinPiece_1_A4_div ? T_701 : 1'h0;
+ assign T_704 = T_699 | T_703;
+ assign T_706 = ~ 12'h98a;
+ assign T_708 = zLinPiece_2_A4_div ? T_706 : 1'h0;
+ assign T_709 = T_704 | T_708;
+ assign T_711 = ~ 12'h739;
+ assign T_713 = zLinPiece_3_A4_div ? T_711 : 1'h0;
+ assign T_714 = T_709 | T_713;
+ assign T_716 = ~ 12'h54b;
+ assign T_718 = zLinPiece_4_A4_div ? T_716 : 1'h0;
+ assign T_719 = T_714 | T_718;
+ assign T_721 = ~ 12'h3a9;
+ assign T_723 = zLinPiece_5_A4_div ? T_721 : 1'h0;
+ assign T_724 = T_719 | T_723;
+ assign T_726 = ~ 12'h242;
+ assign T_728 = zLinPiece_6_A4_div ? T_726 : 1'h0;
+ assign T_729 = T_724 | T_728;
+ assign T_731 = ~ 12'h10b;
+ assign T_733 = zLinPiece_7_A4_div ? T_731 : 1'h0;
+ assign zComplFractK0_A4_div = T_729 | T_733;
+ assign zFractB_A7_sqrt = entering_PA_normalCase_sqrt ? fractB_S : 1'h0;
+ assign T_737 = expB_S[0];
+ assign T_738 = ~ T_737;
+ assign T_739 = entering_PA_normalCase_sqrt & T_738;
+ assign T_740 = fractB_S[51];
+ assign T_741 = ~ T_740;
+ assign zQuadPiece_0_A7_sqrt = T_739 & T_741;
+ assign T_743 = expB_S[0];
+ assign T_744 = ~ T_743;
+ assign T_745 = entering_PA_normalCase_sqrt & T_744;
+ assign T_746 = fractB_S[51];
+ assign zQuadPiece_1_A7_sqrt = T_745 & T_746;
+ assign T_748 = expB_S[0];
+ assign T_749 = entering_PA_normalCase_sqrt & T_748;
+ assign T_750 = fractB_S[51];
+ assign T_751 = ~ T_750;
+ assign zQuadPiece_2_A7_sqrt = T_749 & T_751;
+ assign T_753 = expB_S[0];
+ assign T_754 = entering_PA_normalCase_sqrt & T_753;
+ assign T_755 = fractB_S[51];
+ assign zQuadPiece_3_A7_sqrt = T_754 & T_755;
+ assign T_759 = zQuadPiece_0_A7_sqrt ? 9'h1c8 : 1'h0;
+ assign T_762 = zQuadPiece_1_A7_sqrt ? 9'hc1 : 1'h0;
+ assign T_763 = T_759 | T_762;
+ assign T_766 = zQuadPiece_2_A7_sqrt ? 9'h143 : 1'h0;
+ assign T_767 = T_763 | T_766;
+ assign T_770 = zQuadPiece_3_A7_sqrt ? 9'h89 : 1'h0;
+ assign zK2_A7_sqrt = T_767 | T_770;
+ assign T_773 = ~ 10'h3d0;
+ assign T_775 = zQuadPiece_0_A7_sqrt ? T_773 : 1'h0;
+ assign T_777 = ~ 10'h220;
+ assign T_779 = zQuadPiece_1_A7_sqrt ? T_777 : 1'h0;
+ assign T_780 = T_775 | T_779;
+ assign T_782 = ~ 10'h2b2;
+ assign T_784 = zQuadPiece_2_A7_sqrt ? T_782 : 1'h0;
+ assign T_785 = T_780 | T_784;
+ assign T_787 = ~ 10'h181;
+ assign T_789 = zQuadPiece_3_A7_sqrt ? T_787 : 1'h0;
+ assign zComplK1_A7_sqrt = T_785 | T_789;
+ assign T_791 = exp_PA[0];
+ assign T_792 = ~ T_791;
+ assign T_793 = cyc_A6_sqrt & T_792;
+ assign T_794 = sigB_PA[51];
+ assign T_795 = ~ T_794;
+ assign zQuadPiece_0_A6_sqrt = T_793 & T_795;
+ assign T_797 = exp_PA[0];
+ assign T_798 = ~ T_797;
+ assign T_799 = cyc_A6_sqrt & T_798;
+ assign T_800 = sigB_PA[51];
+ assign zQuadPiece_1_A6_sqrt = T_799 & T_800;
+ assign T_802 = exp_PA[0];
+ assign T_803 = cyc_A6_sqrt & T_802;
+ assign T_804 = sigB_PA[51];
+ assign T_805 = ~ T_804;
+ assign zQuadPiece_2_A6_sqrt = T_803 & T_805;
+ assign T_807 = exp_PA[0];
+ assign T_808 = cyc_A6_sqrt & T_807;
+ assign T_809 = sigB_PA[51];
+ assign zQuadPiece_3_A6_sqrt = T_808 & T_809;
+ assign T_812 = ~ 13'h1fe5;
+ assign T_814 = zQuadPiece_0_A6_sqrt ? T_812 : 1'h0;
+ assign T_816 = ~ 13'h1435;
+ assign T_818 = zQuadPiece_1_A6_sqrt ? T_816 : 1'h0;
+ assign T_819 = T_814 | T_818;
+ assign T_821 = ~ 13'hd2c;
+ assign T_823 = zQuadPiece_2_A6_sqrt ? T_821 : 1'h0;
+ assign T_824 = T_819 | T_823;
+ assign T_826 = ~ 13'h4e8;
+ assign T_828 = zQuadPiece_3_A6_sqrt ? T_826 : 1'h0;
+ assign zComplFractK0_A6_sqrt = T_824 | T_828;
+ assign T_830 = zFractB_A4_div[48:40];
+ assign T_831 = T_830 | zK2_A7_sqrt;
+ assign T_832 = ~ cyc_S;
+ assign T_834 = T_832 ? nextMulAdd9A_A : 1'h0;
+ assign mulAdd9A_A = T_831 | T_834;
+ assign T_836 = zFractB_A7_sqrt[50:42];
+ assign T_837 = zK1_A4_div | T_836;
+ assign T_838 = ~ cyc_S;
+ assign T_840 = T_838 ? nextMulAdd9B_A : 1'h0;
+ assign mulAdd9B_A = T_837 | T_840;
+ assign T_842 = zComplK1_A7_sqrt << 10;
+ assign T_844 = 6'h0 - cyc_A6_sqrt;
+ assign T_845 = T_844[5:0];
+ assign T_846 = {zComplFractK0_A6_sqrt,T_845};
+ assign T_847 = {cyc_A6_sqrt,T_846};
+ assign T_848 = T_842 | T_847;
+ assign T_850 = 8'h0 - entering_PA_normalCase_div;
+ assign T_851 = T_850[7:0];
+ assign T_852 = {zComplFractK0_A4_div,T_851};
+ assign T_853 = {entering_PA_normalCase_div,T_852};
+ assign T_854 = T_848 | T_853;
+ assign T_856 = fractR0_A << 10;
+ assign T_857 = 20'h40000 + T_856;
+ assign T_858 = T_857[19:0];
+ assign T_860 = cyc_A5_sqrt ? T_858 : 1'h0;
+ assign T_861 = T_854 | T_860;
+ assign T_862 = hiSqrR0_A_sqrt[9];
+ assign T_863 = ~ T_862;
+ assign T_864 = cyc_A4_sqrt & T_863;
+ assign T_867 = T_864 ? 11'h400 : 1'h0;
+ assign T_868 = T_861 | T_867;
+ assign T_869 = hiSqrR0_A_sqrt[9];
+ assign T_870 = cyc_A4_sqrt & T_869;
+ assign T_871 = T_870 | cyc_A3_div;
+ assign T_872 = sigB_PA[46:26];
+ assign T_874 = T_872 + 11'h400;
+ assign T_875 = T_874[20:0];
+ assign T_877 = T_871 ? T_875 : 1'h0;
+ assign T_878 = T_868 | T_877;
+ assign T_879 = cyc_A3_sqrt | cyc_A2;
+ assign T_881 = T_879 ? partNegSigma0_A : 1'h0;
+ assign T_882 = T_878 | T_881;
+ assign T_883 = fractR0_A << 16;
+ assign T_885 = cyc_A1_sqrt ? T_883 : 1'h0;
+ assign T_886 = T_882 | T_885;
+ assign T_887 = fractR0_A << 15;
+ assign T_889 = cyc_A1_div ? T_887 : 1'h0;
+ assign mulAdd9C_A = T_886 | T_889;
+ assign T_891 = mulAdd9A_A * mulAdd9B_A;
+ assign T_893 = mulAdd9C_A[17:0];
+ assign T_894 = {1'h0,T_893};
+ assign T_895 = T_891 + T_894;
+ assign loMulAdd9Out_A = T_895[18:0];
+ assign T_897 = loMulAdd9Out_A[18];
+ assign T_898 = mulAdd9C_A[24:18];
+ assign T_900 = T_898 + 1'h1;
+ assign T_901 = T_900[6:0];
+ assign T_902 = mulAdd9C_A[24:18];
+ assign T_903 = T_897 ? T_901 : T_902;
+ assign T_904 = loMulAdd9Out_A[17:0];
+ assign mulAdd9Out_A = {T_903,T_904};
+ assign T_906 = mulAdd9Out_A[19];
+ assign T_907 = cyc_A6_sqrt & T_906;
+ assign T_908 = ~ mulAdd9Out_A;
+ assign T_909 = T_908[24:10];
+ assign T_911 = T_907 ? T_909 : 1'h0;
+ assign zFractR0_A6_sqrt = T_911[8:0];
+ assign T_913 = exp_PA[0];
+ assign T_914 = mulAdd9Out_A << 1;
+ assign sqrR0_A5_sqrt = T_913 ? T_914 : mulAdd9Out_A;
+ assign T_916 = mulAdd9Out_A[20];
+ assign T_917 = entering_PA_normalCase_div & T_916;
+ assign T_918 = ~ mulAdd9Out_A;
+ assign T_919 = T_918[24:11];
+ assign T_921 = T_917 ? T_919 : 1'h0;
+ assign zFractR0_A4_div = T_921[8:0];
+ assign T_923 = mulAdd9Out_A[11];
+ assign T_924 = cyc_A2 & T_923;
+ assign T_925 = ~ mulAdd9Out_A;
+ assign T_926 = T_925[24:2];
+ assign T_928 = T_924 ? T_926 : 1'h0;
+ assign zSigma0_A2 = T_928[8:0];
+ assign T_930 = mulAdd9Out_A[24:10];
+ assign T_931 = mulAdd9Out_A[24:9];
+ assign T_932 = sqrtOp_PA ? T_930 : T_931;
+ assign fractR1_A1 = T_932[14:0];
+ assign r1_A1 = {1'h1,fractR1_A1};
+ assign T_936 = exp_PA[0];
+ assign T_937 = r1_A1 << 1;
+ assign ER1_A1_sqrt = T_936 ? T_937 : r1_A1;
+ assign T_939 = cyc_A6_sqrt | entering_PA_normalCase_div;
+ assign T_940 = zFractR0_A6_sqrt | zFractR0_A4_div;
+ assign T_941 = sqrR0_A5_sqrt[25:10];
+ assign T_942 = cyc_A4_sqrt | cyc_A3;
+ assign T_943 = mulAdd9Out_A[24:9];
+ assign T_944 = cyc_A4_sqrt ? mulAdd9Out_A : T_943;
+ assign T_945 = T_944[20:0];
+ assign T_946 = entering_PA_normalCase_sqrt | cyc_A6_sqrt;
+ assign T_947 = T_946 | cyc_A5_sqrt;
+ assign T_948 = T_947 | cyc_A4;
+ assign T_949 = T_948 | cyc_A3;
+ assign T_950 = T_949 | cyc_A2;
+ assign T_951 = ~ mulAdd9Out_A;
+ assign T_952 = T_951[24:11];
+ assign T_954 = entering_PA_normalCase_sqrt ? T_952 : 1'h0;
+ assign T_955 = T_954 | zFractR0_A6_sqrt;
+ assign T_956 = sigB_PA[43:35];
+ assign T_958 = cyc_A4_sqrt ? T_956 : 1'h0;
+ assign T_959 = T_955 | T_958;
+ assign T_960 = zFractB_A4_div[43:35];
+ assign T_961 = T_959 | T_960;
+ assign T_962 = cyc_A5_sqrt | cyc_A3;
+ assign T_963 = sigB_PA[52:44];
+ assign T_965 = T_962 ? T_963 : 1'h0;
+ assign T_966 = T_961 | T_965;
+ assign T_967 = T_966 | zSigma0_A2;
+ assign T_968 = entering_PA_normalCase_sqrt | cyc_A6_sqrt;
+ assign T_969 = T_968 | cyc_A5_sqrt;
+ assign T_970 = T_969 | cyc_A4;
+ assign T_971 = T_970 | cyc_A2;
+ assign T_972 = zFractB_A7_sqrt[50:42];
+ assign T_973 = T_972 | zFractR0_A6_sqrt;
+ assign T_974 = sqrR0_A5_sqrt[9:1];
+ assign T_976 = cyc_A5_sqrt ? T_974 : 1'h0;
+ assign T_977 = T_973 | T_976;
+ assign T_978 = T_977 | zFractR0_A4_div;
+ assign T_979 = hiSqrR0_A_sqrt[8:0];
+ assign T_981 = cyc_A4_sqrt ? T_979 : 1'h0;
+ assign T_982 = T_978 | T_981;
+ assign T_984 = fractR0_A[8:1];
+ assign T_985 = {1'h1,T_984};
+ assign T_987 = cyc_A2 ? T_985 : 1'h0;
+ assign T_988 = T_982 | T_987;
+ assign T_989 = cyc_A1 | cyc_B7_sqrt;
+ assign T_990 = T_989 | cyc_B6_div;
+ assign T_991 = T_990 | cyc_B4;
+ assign T_992 = T_991 | cyc_B3;
+ assign T_993 = T_992 | cyc_C6_sqrt;
+ assign T_994 = T_993 | cyc_C4;
+ assign T_995 = T_994 | cyc_C1;
+ assign T_996 = ER1_A1_sqrt << 36;
+ assign T_998 = cyc_A1_sqrt ? T_996 : 1'h0;
+ assign T_999 = cyc_B7_sqrt | cyc_A1_div;
+ assign T_1001 = T_999 ? sigB_PA : 1'h0;
+ assign T_1002 = T_998 | T_1001;
+ assign T_1004 = cyc_B6_div ? sigA_PA : 1'h0;
+ assign T_1005 = T_1002 | T_1004;
+ assign T_1006 = zSigma1_B4[45:12];
+ assign T_1007 = T_1005 | T_1006;
+ assign T_1008 = cyc_B3 | cyc_C6_sqrt;
+ assign T_1009 = sigXNU_B3_CX[57:12];
+ assign T_1011 = T_1008 ? T_1009 : 1'h0;
+ assign T_1012 = T_1007 | T_1011;
+ assign T_1013 = sigXN_C[57:25];
+ assign T_1014 = T_1013 << 13;
+ assign T_1016 = cyc_C4_div ? T_1014 : 1'h0;
+ assign T_1017 = T_1012 | T_1016;
+ assign T_1018 = u_C_sqrt << 15;
+ assign T_1020 = cyc_C4_sqrt ? T_1018 : 1'h0;
+ assign T_1021 = T_1017 | T_1020;
+ assign T_1023 = cyc_C1_div ? sigB_PC : 1'h0;
+ assign T_1024 = T_1021 | T_1023;
+ assign T_1025 = T_1024 | zComplSigT_C1_sqrt;
+ assign T_1026 = cyc_A1 | cyc_B7_sqrt;
+ assign T_1027 = T_1026 | cyc_B6_sqrt;
+ assign T_1028 = T_1027 | cyc_B4;
+ assign T_1029 = T_1028 | cyc_C6_sqrt;
+ assign T_1030 = T_1029 | cyc_C4;
+ assign T_1031 = T_1030 | cyc_C1;
+ assign T_1032 = r1_A1 << 36;
+ assign T_1034 = cyc_A1 ? T_1032 : 1'h0;
+ assign T_1035 = ESqrR1_B_sqrt << 19;
+ assign T_1037 = cyc_B7_sqrt ? T_1035 : 1'h0;
+ assign T_1038 = T_1034 | T_1037;
+ assign T_1039 = ER1_B_sqrt << 36;
+ assign T_1041 = cyc_B6_sqrt ? T_1039 : 1'h0;
+ assign T_1042 = T_1038 | T_1041;
+ assign T_1043 = T_1042 | zSigma1_B4;
+ assign T_1044 = sqrSigma1_C[30:1];
+ assign T_1046 = cyc_C6_sqrt ? T_1044 : 1'h0;
+ assign T_1047 = T_1043 | T_1046;
+ assign T_1049 = cyc_C4 ? sqrSigma1_C : 1'h0;
+ assign T_1050 = T_1047 | T_1049;
+ assign T_1051 = T_1050 | zComplSigT_C1;
+ assign T_1052 = cyc_A4 | cyc_A3_div;
+ assign T_1053 = T_1052 | cyc_A1_div;
+ assign T_1054 = T_1053 | cyc_B10_sqrt;
+ assign T_1055 = T_1054 | cyc_B9_sqrt;
+ assign T_1056 = T_1055 | cyc_B7_sqrt;
+ assign T_1057 = T_1056 | cyc_B6;
+ assign T_1058 = T_1057 | cyc_B5_sqrt;
+ assign T_1059 = T_1058 | cyc_B3_sqrt;
+ assign T_1060 = T_1059 | cyc_B2_div;
+ assign T_1061 = T_1060 | cyc_B1_sqrt;
+ assign T_1062 = T_1061 | cyc_C4;
+ assign T_1063 = cyc_A3 | cyc_A2_div;
+ assign T_1064 = T_1063 | cyc_B9_sqrt;
+ assign T_1065 = T_1064 | cyc_B8_sqrt;
+ assign T_1066 = T_1065 | cyc_B6;
+ assign T_1067 = T_1066 | cyc_B5;
+ assign T_1068 = T_1067 | cyc_B4_sqrt;
+ assign T_1069 = T_1068 | cyc_B2_sqrt;
+ assign T_1070 = T_1069 | cyc_B1_div;
+ assign T_1071 = T_1070 | cyc_C6_sqrt;
+ assign T_1072 = T_1071 | valid_normalCase_leaving_PB;
+ assign T_1073 = cyc_A2 | cyc_A1_div;
+ assign T_1074 = T_1073 | cyc_B8_sqrt;
+ assign T_1075 = T_1074 | cyc_B7_sqrt;
+ assign T_1076 = T_1075 | cyc_B5;
+ assign T_1077 = T_1076 | cyc_B4;
+ assign T_1078 = T_1077 | cyc_B3_sqrt;
+ assign T_1079 = T_1078 | cyc_B1_sqrt;
+ assign T_1080 = T_1079 | cyc_C5;
+ assign T_1081 = T_1080 | cyc_C2;
+ assign T_1082 = io_latchMulAddA_0 | cyc_B6;
+ assign T_1083 = T_1082 | cyc_B2_sqrt;
+ assign T_1084 = {T_1062,T_1072};
+ assign T_1085 = {T_1081,T_1083};
+ assign T_1086 = {T_1084,T_1085};
+ assign T_1087 = sigX1_B << 47;
+ assign T_1089 = cyc_B1 ? T_1087 : 1'h0;
+ assign T_1090 = sigX1_B << 46;
+ assign T_1092 = cyc_C6_sqrt ? T_1090 : 1'h0;
+ assign T_1093 = T_1089 | T_1092;
+ assign T_1094 = cyc_C4_sqrt | cyc_C2;
+ assign T_1095 = sigXN_C << 47;
+ assign T_1097 = T_1094 ? T_1095 : 1'h0;
+ assign T_1098 = T_1093 | T_1097;
+ assign T_1099 = ~ E_E_div;
+ assign T_1100 = cyc_E3_div & T_1099;
+ assign T_1101 = fractA_0_PC << 53;
+ assign T_1103 = T_1100 ? T_1101 : 1'h0;
+ assign T_1104 = T_1098 | T_1103;
+ assign T_1105 = exp_PC[0];
+ assign T_1106 = sigB_PC[0];
+ assign T_1108 = {T_1106,1'h0};
+ assign T_1109 = sigB_PC[1];
+ assign T_1110 = sigB_PC[0];
+ assign T_1111 = T_1109 ^ T_1110;
+ assign T_1112 = sigB_PC[0];
+ assign T_1113 = {T_1111,T_1112};
+ assign T_1114 = T_1105 ? T_1108 : T_1113;
+ assign T_1115 = ~ extraT_E;
+ assign T_1117 = {T_1115,1'h0};
+ assign T_1118 = T_1114 ^ T_1117;
+ assign T_1119 = T_1118 << 54;
+ assign T_1121 = cyc_E3_sqrt ? T_1119 : 1'h0;
+ assign T_1122 = T_1104 | T_1121;
+ assign ESqrR1_B8_sqrt = io_mulAddResult_3[103:72];
+ assign T_1124 = io_mulAddResult_3[90:45];
+ assign T_1125 = ~ T_1124;
+ assign T_1127 = cyc_B4 ? T_1125 : 1'h0;
+ assign sqrSigma1_B1 = io_mulAddResult_3[79:47];
+ assign T_1129 = io_mulAddResult_3[104:47];
+ assign T_1130 = io_mulAddResult_3[104];
+ assign E_C1_div = ~ T_1130;
+ assign T_1132 = ~ E_C1_div;
+ assign T_1133 = cyc_C1_div & T_1132;
+ assign T_1134 = T_1133 | cyc_C1_sqrt;
+ assign T_1135 = io_mulAddResult_3[104:51];
+ assign T_1136 = ~ T_1135;
+ assign T_1138 = T_1134 ? T_1136 : 1'h0;
+ assign T_1139 = cyc_C1_div & E_C1_div;
+ assign T_1141 = io_mulAddResult_3[102:50];
+ assign T_1142 = ~ T_1141;
+ assign T_1143 = {1'h0,T_1142};
+ assign T_1145 = T_1139 ? T_1143 : 1'h0;
+ assign T_1146 = T_1138 | T_1145;
+ assign T_1147 = io_mulAddResult_3[104:51];
+ assign T_1148 = ~ T_1147;
+ assign T_1150 = cyc_C1_sqrt ? T_1148 : 1'h0;
+ assign sigT_C1 = ~ zComplSigT_C1;
+ assign remT_E2 = io_mulAddResult_3[55:0];
+ assign T_1153 = cyc_C6_sqrt | cyc_C5_div;
+ assign T_1154 = T_1153 | cyc_C3_sqrt;
+ assign T_1155 = sigXNU_B3_CX[56:26];
+ assign T_1156 = sigT_C1[53:1];
+ assign T_1157 = sigT_C1[0];
+ assign T_1158 = remT_E2[55];
+ assign T_1159 = remT_E2[53];
+ assign T_1160 = sqrtOp_PC ? T_1158 : T_1159;
+ assign T_1161 = remT_E2[53:0];
+ assign T_1163 = T_1161 == 1'h0;
+ assign T_1164 = ~ sqrtOp_PC;
+ assign T_1165 = remT_E2[55:54];
+ assign T_1167 = T_1165 == 1'h0;
+ assign T_1168 = T_1164 | T_1167;
+ assign T_1169 = T_1163 & T_1168;
+ assign T_1170 = ~ sqrtOp_PC;
+ assign T_1171 = T_1170 & E_E_div;
+ assign T_1173 = T_1171 ? exp_PC : 1'h0;
+ assign T_1174 = ~ sqrtOp_PC;
+ assign T_1175 = ~ E_E_div;
+ assign T_1176 = T_1174 & T_1175;
+ assign T_1178 = T_1176 ? expP1_PC : 1'h0;
+ assign T_1179 = T_1173 | T_1178;
+ assign T_1180 = exp_PC[13:1];
+ assign T_1182 = T_1180 + 12'h400;
+ assign T_1183 = T_1182[12:0];
+ assign T_1185 = sqrtOp_PC ? T_1183 : 1'h0;
+ assign sExpX_E = T_1179 | T_1185;
+ assign posExpX_E = sExpX_E[12:0];
+ assign T_1188 = ~ posExpX_E;
+ assign GEN_0 = $signed(8193'h100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000);
+ assign T_1190 = $signed(GEN_0) >>> T_1188;
+ assign T_1191 = T_1190[1026:974];
+ assign T_1192 = T_1191[31:0];
+ assign T_1195 = 16'hffff << 16;
+ assign T_1196 = 32'hffffffff ^ T_1195;
+ assign T_1197 = T_1192[31:16];
+ assign T_1198 = T_1197 & T_1196;
+ assign T_1199 = T_1192[15:0];
+ assign T_1200 = T_1199 << 16;
+ assign T_1201 = ~ T_1196;
+ assign T_1202 = T_1200 & T_1201;
+ assign T_1203 = T_1198 | T_1202;
+ assign T_1204 = T_1196[23:0];
+ assign T_1205 = T_1204 << 8;
+ assign T_1206 = T_1196 ^ T_1205;
+ assign T_1207 = T_1203[31:8];
+ assign T_1208 = T_1207 & T_1206;
+ assign T_1209 = T_1203[23:0];
+ assign T_1210 = T_1209 << 8;
+ assign T_1211 = ~ T_1206;
+ assign T_1212 = T_1210 & T_1211;
+ assign T_1213 = T_1208 | T_1212;
+ assign T_1214 = T_1206[27:0];
+ assign T_1215 = T_1214 << 4;
+ assign T_1216 = T_1206 ^ T_1215;
+ assign T_1217 = T_1213[31:4];
+ assign T_1218 = T_1217 & T_1216;
+ assign T_1219 = T_1213[27:0];
+ assign T_1220 = T_1219 << 4;
+ assign T_1221 = ~ T_1216;
+ assign T_1222 = T_1220 & T_1221;
+ assign T_1223 = T_1218 | T_1222;
+ assign T_1224 = T_1216[29:0];
+ assign T_1225 = T_1224 << 2;
+ assign T_1226 = T_1216 ^ T_1225;
+ assign T_1227 = T_1223[31:2];
+ assign T_1228 = T_1227 & T_1226;
+ assign T_1229 = T_1223[29:0];
+ assign T_1230 = T_1229 << 2;
+ assign T_1231 = ~ T_1226;
+ assign T_1232 = T_1230 & T_1231;
+ assign T_1233 = T_1228 | T_1232;
+ assign T_1234 = T_1226[30:0];
+ assign T_1235 = T_1234 << 1;
+ assign T_1236 = T_1226 ^ T_1235;
+ assign T_1237 = T_1233[31:1];
+ assign T_1238 = T_1237 & T_1236;
+ assign T_1239 = T_1233[30:0];
+ assign T_1240 = T_1239 << 1;
+ assign T_1241 = ~ T_1236;
+ assign T_1242 = T_1240 & T_1241;
+ assign T_1243 = T_1238 | T_1242;
+ assign T_1244 = T_1191[52:32];
+ assign T_1245 = T_1244[15:0];
+ assign T_1248 = 8'hff << 8;
+ assign T_1249 = 16'hffff ^ T_1248;
+ assign T_1250 = T_1245[15:8];
+ assign T_1251 = T_1250 & T_1249;
+ assign T_1252 = T_1245[7:0];
+ assign T_1253 = T_1252 << 8;
+ assign T_1254 = ~ T_1249;
+ assign T_1255 = T_1253 & T_1254;
+ assign T_1256 = T_1251 | T_1255;
+ assign T_1257 = T_1249[11:0];
+ assign T_1258 = T_1257 << 4;
+ assign T_1259 = T_1249 ^ T_1258;
+ assign T_1260 = T_1256[15:4];
+ assign T_1261 = T_1260 & T_1259;
+ assign T_1262 = T_1256[11:0];
+ assign T_1263 = T_1262 << 4;
+ assign T_1264 = ~ T_1259;
+ assign T_1265 = T_1263 & T_1264;
+ assign T_1266 = T_1261 | T_1265;
+ assign T_1267 = T_1259[13:0];
+ assign T_1268 = T_1267 << 2;
+ assign T_1269 = T_1259 ^ T_1268;
+ assign T_1270 = T_1266[15:2];
+ assign T_1271 = T_1270 & T_1269;
+ assign T_1272 = T_1266[13:0];
+ assign T_1273 = T_1272 << 2;
+ assign T_1274 = ~ T_1269;
+ assign T_1275 = T_1273 & T_1274;
+ assign T_1276 = T_1271 | T_1275;
+ assign T_1277 = T_1269[14:0];
+ assign T_1278 = T_1277 << 1;
+ assign T_1279 = T_1269 ^ T_1278;
+ assign T_1280 = T_1276[15:1];
+ assign T_1281 = T_1280 & T_1279;
+ assign T_1282 = T_1276[14:0];
+ assign T_1283 = T_1282 << 1;
+ assign T_1284 = ~ T_1279;
+ assign T_1285 = T_1283 & T_1284;
+ assign T_1286 = T_1281 | T_1285;
+ assign T_1287 = T_1244[20:16];
+ assign T_1288 = T_1287[3:0];
+ assign T_1289 = T_1288[1:0];
+ assign T_1290 = T_1289[0];
+ assign T_1291 = T_1289[1];
+ assign T_1292 = {T_1290,T_1291};
+ assign T_1293 = T_1288[3:2];
+ assign T_1294 = T_1293[0];
+ assign T_1295 = T_1293[1];
+ assign T_1296 = {T_1294,T_1295};
+ assign T_1297 = {T_1292,T_1296};
+ assign T_1298 = T_1287[4];
+ assign T_1299 = {T_1297,T_1298};
+ assign T_1300 = {T_1286,T_1299};
+ assign roundMask_E = {T_1243,T_1300};
+ assign T_1303 = {1'h0,roundMask_E};
+ assign T_1304 = ~ T_1303;
+ assign T_1306 = {roundMask_E,1'h1};
+ assign incrPosMask_E = T_1304 & T_1306;
+ assign T_1308 = incrPosMask_E[53:1];
+ assign T_1309 = sigT_E & T_1308;
+ assign hiRoundPosBitT_E = T_1309 != 1'h0;
+ assign T_1312 = roundMask_E[52:1];
+ assign T_1313 = sigT_E & T_1312;
+ assign all0sHiRoundExtraT_E = T_1313 == 1'h0;
+ assign T_1316 = ~ sigT_E;
+ assign T_1317 = roundMask_E[52:1];
+ assign T_1318 = T_1316 & T_1317;
+ assign all1sHiRoundExtraT_E = T_1318 == 1'h0;
+ assign T_1321 = roundMask_E[0];
+ assign T_1322 = ~ T_1321;
+ assign T_1323 = T_1322 | hiRoundPosBitT_E;
+ assign all1sHiRoundT_E = T_1323 & all1sHiRoundExtraT_E;
+ assign T_1326 = 54'h0 + sigT_E;
+ assign T_1327 = T_1326[53:0];
+ assign T_1328 = T_1327 + roundMagUp_PC;
+ assign sigAdjT_E = T_1328[53:0];
+ assign T_1331 = ~ roundMask_E;
+ assign T_1332 = {1'h1,T_1331};
+ assign sigY0_E = sigAdjT_E & T_1332;
+ assign T_1335 = {1'h0,roundMask_E};
+ assign T_1336 = sigAdjT_E | T_1335;
+ assign T_1338 = T_1336 + 1'h1;
+ assign sigY1_E = T_1338[53:0];
+ assign T_1340 = ~ isNegRemT_E;
+ assign T_1341 = ~ trueEqX_E1;
+ assign T_1342 = T_1340 & T_1341;
+ assign trueLtX_E1 = sqrtOp_PC ? T_1342 : isNegRemT_E;
+ assign T_1344 = roundMask_E[0];
+ assign T_1345 = ~ trueLtX_E1;
+ assign T_1346 = T_1344 & T_1345;
+ assign T_1347 = T_1346 & all1sHiRoundExtraT_E;
+ assign T_1348 = T_1347 & extraT_E;
+ assign hiRoundPosBit_E1 = hiRoundPosBitT_E ^ T_1348;
+ assign T_1350 = ~ trueEqX_E1;
+ assign T_1351 = ~ extraT_E;
+ assign T_1352 = T_1350 | T_1351;
+ assign T_1353 = ~ all1sHiRoundExtraT_E;
+ assign anyRoundExtra_E1 = T_1352 | T_1353;
+ assign T_1355 = roundingMode_near_even_PC & hiRoundPosBit_E1;
+ assign T_1356 = ~ anyRoundExtra_E1;
+ assign T_1357 = T_1355 & T_1356;
+ assign roundEvenMask_E1 = T_1357 ? incrPosMask_E : 1'h0;
+ assign T_1360 = roundMagDown_PC & extraT_E;
+ assign T_1361 = ~ trueLtX_E1;
+ assign T_1362 = T_1360 & T_1361;
+ assign T_1363 = T_1362 & all1sHiRoundT_E;
+ assign T_1364 = ~ trueLtX_E1;
+ assign T_1365 = extraT_E & T_1364;
+ assign T_1366 = ~ trueEqX_E1;
+ assign T_1367 = T_1365 & T_1366;
+ assign T_1368 = ~ all1sHiRoundT_E;
+ assign T_1369 = T_1367 | T_1368;
+ assign T_1370 = roundMagUp_PC & T_1369;
+ assign T_1371 = T_1363 | T_1370;
+ assign T_1372 = ~ trueLtX_E1;
+ assign T_1373 = extraT_E | T_1372;
+ assign T_1374 = roundMask_E[0];
+ assign T_1375 = ~ T_1374;
+ assign T_1376 = T_1373 & T_1375;
+ assign T_1377 = hiRoundPosBitT_E | T_1376;
+ assign T_1378 = ~ trueLtX_E1;
+ assign T_1379 = extraT_E & T_1378;
+ assign T_1380 = T_1379 & all1sHiRoundExtraT_E;
+ assign T_1381 = T_1377 | T_1380;
+ assign T_1382 = roundingMode_near_even_PC & T_1381;
+ assign T_1383 = T_1371 | T_1382;
+ assign T_1384 = T_1383 ? sigY1_E : sigY0_E;
+ assign T_1385 = ~ roundEvenMask_E1;
+ assign sigY_E1 = T_1384 & T_1385;
+ assign fractY_E1 = sigY_E1[51:0];
+ assign inexactY_E1 = hiRoundPosBit_E1 | anyRoundExtra_E1;
+ assign T_1389 = sigY_E1[53];
+ assign T_1390 = ~ T_1389;
+ assign T_1392 = T_1390 ? sExpX_E : 1'h0;
+ assign T_1393 = sigY_E1[53];
+ assign T_1394 = ~ sqrtOp_PC;
+ assign T_1395 = T_1393 & T_1394;
+ assign T_1396 = T_1395 & E_E_div;
+ assign T_1398 = T_1396 ? expP1_PC : 1'h0;
+ assign T_1399 = T_1392 | T_1398;
+ assign T_1400 = sigY_E1[53];
+ assign T_1401 = ~ sqrtOp_PC;
+ assign T_1402 = T_1400 & T_1401;
+ assign T_1403 = ~ E_E_div;
+ assign T_1404 = T_1402 & T_1403;
+ assign T_1406 = T_1404 ? expP2_PC : 1'h0;
+ assign T_1407 = T_1399 | T_1406;
+ assign T_1408 = sigY_E1[53];
+ assign T_1409 = T_1408 & sqrtOp_PC;
+ assign T_1410 = expP2_PC[13:1];
+ assign T_1412 = T_1410 + 12'h400;
+ assign T_1413 = T_1412[12:0];
+ assign T_1415 = T_1409 ? T_1413 : 1'h0;
+ assign sExpY_E1 = T_1407 | T_1415;
+ assign expY_E1 = sExpY_E1[11:0];
+ assign T_1418 = sExpY_E1[13];
+ assign T_1419 = ~ T_1418;
+ assign T_1421 = sExpY_E1[12:10];
+ assign T_1422 = 3'h3 <= T_1421;
+ assign overflowY_E1 = T_1419 & T_1422;
+ assign T_1424 = sExpY_E1[13];
+ assign T_1425 = sExpY_E1[12:0];
+ assign T_1427 = T_1425 < 13'h3ce;
+ assign totalUnderflowY_E1 = T_1424 | T_1427;
+ assign T_1430 = posExpX_E <= 13'h401;
+ assign T_1431 = T_1430 & inexactY_E1;
+ assign underflowY_E1 = totalUnderflowY_E1 | T_1431;
+ assign T_1433 = ~ isNaNB_PC;
+ assign T_1434 = ~ isZeroB_PC;
+ assign T_1435 = T_1433 & T_1434;
+ assign T_1436 = T_1435 & sign_PC;
+ assign T_1437 = isZeroA_PC & isZeroB_PC;
+ assign T_1438 = isInfA_PC & isInfB_PC;
+ assign T_1439 = T_1437 | T_1438;
+ assign notSigNaN_invalid_PC = sqrtOp_PC ? T_1436 : T_1439;
+ assign T_1441 = ~ sqrtOp_PC;
+ assign T_1442 = T_1441 & isSigNaNA_PC;
+ assign T_1443 = T_1442 | isSigNaNB_PC;
+ assign invalid_PC = T_1443 | notSigNaN_invalid_PC;
+ assign T_1445 = ~ sqrtOp_PC;
+ assign T_1446 = ~ isSpecialA_PC;
+ assign T_1447 = T_1445 & T_1446;
+ assign T_1448 = ~ isZeroA_PC;
+ assign T_1449 = T_1447 & T_1448;
+ assign infinity_PC = T_1449 & isZeroB_PC;
+ assign overflow_E1 = normalCase_PC & overflowY_E1;
+ assign underflow_E1 = normalCase_PC & underflowY_E1;
+ assign T_1453 = overflow_E1 | underflow_E1;
+ assign T_1454 = normalCase_PC & inexactY_E1;
+ assign inexact_E1 = T_1453 | T_1454;
+ assign T_1456 = isZeroA_PC | isInfB_PC;
+ assign T_1457 = ~ roundMagUp_PC;
+ assign T_1458 = totalUnderflowY_E1 & T_1457;
+ assign T_1459 = T_1456 | T_1458;
+ assign notSpecial_isZeroOut_E1 = sqrtOp_PC ? isZeroB_PC : T_1459;
+ assign T_1461 = normalCase_PC & totalUnderflowY_E1;
+ assign pegMinFiniteMagOut_E1 = T_1461 & roundMagUp_PC;
+ assign T_1463 = ~ overflowY_roundMagUp_PC;
+ assign pegMaxFiniteMagOut_E1 = overflow_E1 & T_1463;
+ assign T_1465 = isInfA_PC | isZeroB_PC;
+ assign T_1466 = overflow_E1 & overflowY_roundMagUp_PC;
+ assign T_1467 = T_1465 | T_1466;
+ assign notNaN_isInfOut_E1 = sqrtOp_PC ? isInfB_PC : T_1467;
+ assign T_1469 = ~ sqrtOp_PC;
+ assign T_1470 = T_1469 & isNaNA_PC;
+ assign T_1471 = T_1470 | isNaNB_PC;
+ assign isNaNOut_PC = T_1471 | notSigNaN_invalid_PC;
+ assign T_1473 = ~ isNaNOut_PC;
+ assign T_1474 = isZeroB_PC & sign_PC;
+ assign T_1475 = sqrtOp_PC ? T_1474 : sign_PC;
+ assign signOut_PC = T_1473 & T_1475;
+ assign T_1478 = ~ 12'h1ff;
+ assign T_1480 = notSpecial_isZeroOut_E1 ? T_1478 : 1'h0;
+ assign T_1481 = ~ T_1480;
+ assign T_1482 = expY_E1 & T_1481;
+ assign T_1484 = ~ 12'h3ce;
+ assign T_1486 = pegMinFiniteMagOut_E1 ? T_1484 : 1'h0;
+ assign T_1487 = ~ T_1486;
+ assign T_1488 = T_1482 & T_1487;
+ assign T_1490 = ~ 12'hbff;
+ assign T_1492 = pegMaxFiniteMagOut_E1 ? T_1490 : 1'h0;
+ assign T_1493 = ~ T_1492;
+ assign T_1494 = T_1488 & T_1493;
+ assign T_1496 = ~ 12'hdff;
+ assign T_1498 = notNaN_isInfOut_E1 ? T_1496 : 1'h0;
+ assign T_1499 = ~ T_1498;
+ assign T_1500 = T_1494 & T_1499;
+ assign T_1503 = pegMinFiniteMagOut_E1 ? 12'h3ce : 1'h0;
+ assign T_1504 = T_1500 | T_1503;
+ assign T_1507 = pegMaxFiniteMagOut_E1 ? 12'hbff : 1'h0;
+ assign T_1508 = T_1504 | T_1507;
+ assign T_1511 = notNaN_isInfOut_E1 ? 12'hc00 : 1'h0;
+ assign T_1512 = T_1508 | T_1511;
+ assign T_1515 = isNaNOut_PC ? 12'he00 : 1'h0;
+ assign expOut_E1 = T_1512 | T_1515;
+ assign T_1517 = notSpecial_isZeroOut_E1 | totalUnderflowY_E1;
+ assign T_1518 = T_1517 | isNaNOut_PC;
+ assign T_1520 = T_1518 ? 1'h0 : fractY_E1;
+ assign T_1522 = 52'h0 - pegMaxFiniteMagOut_E1;
+ assign T_1523 = T_1522[51:0];
+ assign T_1524 = T_1520 | T_1523;
+ assign T_1525 = isNaNOut_PC << 51;
+ assign fractOut_E1 = T_1524 | T_1525;
+ assign T_1527 = {expOut_E1,fractOut_E1};
+ assign T_1528 = {signOut_PC,T_1527};
+ assign T_1529 = {invalid_PC,infinity_PC};
+ assign T_1530 = {underflow_E1,inexact_E1};
+ assign T_1531 = {overflow_E1,T_1530};
+ assign T_1532 = {T_1529,T_1531};
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ valid_PA = {1{$random}};
+ sqrtOp_PA = {1{$random}};
+ sign_PA = {1{$random}};
+ specialCodeB_PA = {1{$random}};
+ fractB_51_PA = {1{$random}};
+ roundingMode_PA = {1{$random}};
+ specialCodeA_PA = {1{$random}};
+ fractA_51_PA = {1{$random}};
+ exp_PA = {1{$random}};
+ fractB_other_PA = {2{$random}};
+ fractA_other_PA = {2{$random}};
+ valid_PB = {1{$random}};
+ sqrtOp_PB = {1{$random}};
+ sign_PB = {1{$random}};
+ specialCodeA_PB = {1{$random}};
+ fractA_51_PB = {1{$random}};
+ specialCodeB_PB = {1{$random}};
+ fractB_51_PB = {1{$random}};
+ roundingMode_PB = {1{$random}};
+ exp_PB = {1{$random}};
+ fractA_0_PB = {1{$random}};
+ fractB_other_PB = {2{$random}};
+ valid_PC = {1{$random}};
+ sqrtOp_PC = {1{$random}};
+ sign_PC = {1{$random}};
+ specialCodeA_PC = {1{$random}};
+ fractA_51_PC = {1{$random}};
+ specialCodeB_PC = {1{$random}};
+ fractB_51_PC = {1{$random}};
+ roundingMode_PC = {1{$random}};
+ exp_PC = {1{$random}};
+ fractA_0_PC = {1{$random}};
+ fractB_other_PC = {2{$random}};
+ cycleNum_A = {1{$random}};
+ cycleNum_B = {1{$random}};
+ cycleNum_C = {1{$random}};
+ cycleNum_E = {1{$random}};
+ fractR0_A = {1{$random}};
+ hiSqrR0_A_sqrt = {1{$random}};
+ partNegSigma0_A = {1{$random}};
+ nextMulAdd9A_A = {1{$random}};
+ nextMulAdd9B_A = {1{$random}};
+ ER1_B_sqrt = {1{$random}};
+ ESqrR1_B_sqrt = {1{$random}};
+ sigX1_B = {2{$random}};
+ sqrSigma1_C = {2{$random}};
+ sigXN_C = {2{$random}};
+ u_C_sqrt = {1{$random}};
+ E_E_div = {1{$random}};
+ sigT_E = {2{$random}};
+ extraT_E = {1{$random}};
+ isNegRemT_E = {1{$random}};
+ trueEqX_E1 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ valid_PA <= 1'h0;
+ end else begin
+ if(T_300) begin
+ valid_PA <= entering_PA;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PA) begin
+ sqrtOp_PA <= io_sqrtOp;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PA) begin
+ sign_PA <= sign_S;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PA) begin
+ specialCodeB_PA <= specialCodeB_S;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PA) begin
+ fractB_51_PA <= T_301;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PA) begin
+ roundingMode_PA <= io_roundingMode;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_303) begin
+ specialCodeA_PA <= specialCodeA_S;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_303) begin
+ fractA_51_PA <= T_304;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PA_normalCase) begin
+ exp_PA <= T_314;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PA_normalCase) begin
+ fractB_other_PA <= T_315;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PA_normalCase_div) begin
+ fractA_other_PA <= T_316;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ valid_PB <= 1'h0;
+ end else begin
+ if(T_354) begin
+ valid_PB <= entering_PB;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PB) begin
+ sqrtOp_PB <= T_355;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PB) begin
+ sign_PB <= T_356;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PB) begin
+ specialCodeA_PB <= T_357;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PB) begin
+ fractA_51_PB <= T_359;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PB) begin
+ specialCodeB_PB <= T_360;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PB) begin
+ fractB_51_PB <= T_362;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PB) begin
+ roundingMode_PB <= T_363;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PB_normalCase) begin
+ exp_PB <= exp_PA;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PB_normalCase) begin
+ fractA_0_PB <= T_364;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PB_normalCase) begin
+ fractB_other_PB <= fractB_other_PA;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ valid_PC <= 1'h0;
+ end else begin
+ if(T_395) begin
+ valid_PC <= entering_PC;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PC) begin
+ sqrtOp_PC <= T_396;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PC) begin
+ sign_PC <= T_397;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PC) begin
+ specialCodeA_PC <= T_398;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PC) begin
+ fractA_51_PC <= T_400;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PC) begin
+ specialCodeB_PC <= T_401;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PC) begin
+ fractB_51_PC <= T_403;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PC) begin
+ roundingMode_PC <= T_404;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PC_normalCase) begin
+ exp_PC <= exp_PB;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PC_normalCase) begin
+ fractA_0_PC <= fractA_0_PB;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(entering_PC_normalCase) begin
+ fractB_other_PC <= fractB_other_PB;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ cycleNum_A <= 3'h0;
+ end else begin
+ if(T_475) begin
+ cycleNum_A <= T_489;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ cycleNum_B <= 4'h0;
+ end else begin
+ if(T_514) begin
+ cycleNum_B <= T_521;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ cycleNum_C <= 3'h0;
+ end else begin
+ if(T_568) begin
+ cycleNum_C <= T_575;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ cycleNum_E <= 3'h0;
+ end else begin
+ if(T_605) begin
+ cycleNum_E <= T_610;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_939) begin
+ fractR0_A <= T_940;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(cyc_A5_sqrt) begin
+ hiSqrR0_A_sqrt <= T_941;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_942) begin
+ partNegSigma0_A <= T_945;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_950) begin
+ nextMulAdd9A_A <= T_967;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_971) begin
+ nextMulAdd9B_A <= T_988;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(cyc_A1_sqrt) begin
+ ER1_B_sqrt <= ER1_A1_sqrt;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(cyc_B8_sqrt) begin
+ ESqrR1_B_sqrt <= ESqrR1_B8_sqrt;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(cyc_B3) begin
+ sigX1_B <= sigXNU_B3_CX;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(cyc_B1) begin
+ sqrSigma1_C <= sqrSigma1_B1;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1154) begin
+ sigXN_C <= sigXNU_B3_CX;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(cyc_C5_sqrt) begin
+ u_C_sqrt <= T_1155;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(cyc_C1) begin
+ E_E_div <= E_C1_div;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(cyc_C1) begin
+ sigT_E <= T_1156;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(cyc_C1) begin
+ extraT_E <= T_1157;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(cyc_E2) begin
+ isNegRemT_E <= T_1160;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(cyc_E2) begin
+ trueEqX_E1 <= T_1169;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module Mul54(
+ input clk,
+ input reset,
+ input io_val_s0,
+ input io_latch_a_s0,
+ input [53:0] io_a_s0,
+ input io_latch_b_s0,
+ input [53:0] io_b_s0,
+ input [104:0] io_c_s2,
+ output [104:0] io_result_s3
+);
+ reg val_s1;
+ reg val_s2;
+ reg [53:0] reg_a_s1;
+ reg [53:0] reg_b_s1;
+ reg [53:0] reg_a_s2;
+ reg [53:0] reg_b_s2;
+ reg [104:0] reg_result_s3;
+ wire [107:0] T_25;
+ wire [104:0] T_26;
+ wire [105:0] T_27;
+ wire [104:0] T_28;
+ assign io_result_s3 = reg_result_s3;
+ assign T_25 = reg_a_s2 * reg_b_s2;
+ assign T_26 = T_25[104:0];
+ assign T_27 = T_26 + io_c_s2;
+ assign T_28 = T_27[104:0];
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ val_s1 = {1{$random}};
+ val_s2 = {1{$random}};
+ reg_a_s1 = {2{$random}};
+ reg_b_s1 = {2{$random}};
+ reg_a_s2 = {2{$random}};
+ reg_b_s2 = {2{$random}};
+ reg_result_s3 = {4{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(1'h0) begin
+ ;
+ end else begin
+ val_s1 <= io_val_s0;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ val_s2 <= val_s1;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_val_s0) begin
+ if(io_latch_a_s0) begin
+ reg_a_s1 <= io_a_s0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_val_s0) begin
+ if(io_latch_b_s0) begin
+ reg_b_s1 <= io_b_s0;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(val_s1) begin
+ reg_a_s2 <= reg_a_s1;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(val_s1) begin
+ reg_b_s2 <= reg_b_s1;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(val_s2) begin
+ reg_result_s3 <= T_28;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module DivSqrtRecF64(
+ input clk,
+ input reset,
+ output io_inReady_div,
+ output io_inReady_sqrt,
+ input io_inValid,
+ input io_sqrtOp,
+ input [64:0] io_a,
+ input [64:0] io_b,
+ input [1:0] io_roundingMode,
+ output io_outValid_div,
+ output io_outValid_sqrt,
+ output [64:0] io_out,
+ output [4:0] io_exceptionFlags
+);
+ wire ds_clk;
+ wire ds_reset;
+ wire ds_io_inReady_div;
+ wire ds_io_inReady_sqrt;
+ wire ds_io_inValid;
+ wire ds_io_sqrtOp;
+ wire [64:0] ds_io_a;
+ wire [64:0] ds_io_b;
+ wire [1:0] ds_io_roundingMode;
+ wire ds_io_outValid_div;
+ wire ds_io_outValid_sqrt;
+ wire [64:0] ds_io_out;
+ wire [4:0] ds_io_exceptionFlags;
+ wire [3:0] ds_io_usingMulAdd;
+ wire ds_io_latchMulAddA_0;
+ wire [53:0] ds_io_mulAddA_0;
+ wire ds_io_latchMulAddB_0;
+ wire [53:0] ds_io_mulAddB_0;
+ wire [104:0] ds_io_mulAddC_2;
+ wire [104:0] ds_io_mulAddResult_3;
+ wire mul_clk;
+ wire mul_reset;
+ wire mul_io_val_s0;
+ wire mul_io_latch_a_s0;
+ wire [53:0] mul_io_a_s0;
+ wire mul_io_latch_b_s0;
+ wire [53:0] mul_io_b_s0;
+ wire [104:0] mul_io_c_s2;
+ wire [104:0] mul_io_result_s3;
+ wire T_17;
+ DivSqrtRecF64_mulAddZ31 ds (
+ .clk(ds_clk),
+ .reset(ds_reset),
+ .io_inReady_div(ds_io_inReady_div),
+ .io_inReady_sqrt(ds_io_inReady_sqrt),
+ .io_inValid(ds_io_inValid),
+ .io_sqrtOp(ds_io_sqrtOp),
+ .io_a(ds_io_a),
+ .io_b(ds_io_b),
+ .io_roundingMode(ds_io_roundingMode),
+ .io_outValid_div(ds_io_outValid_div),
+ .io_outValid_sqrt(ds_io_outValid_sqrt),
+ .io_out(ds_io_out),
+ .io_exceptionFlags(ds_io_exceptionFlags),
+ .io_usingMulAdd(ds_io_usingMulAdd),
+ .io_latchMulAddA_0(ds_io_latchMulAddA_0),
+ .io_mulAddA_0(ds_io_mulAddA_0),
+ .io_latchMulAddB_0(ds_io_latchMulAddB_0),
+ .io_mulAddB_0(ds_io_mulAddB_0),
+ .io_mulAddC_2(ds_io_mulAddC_2),
+ .io_mulAddResult_3(ds_io_mulAddResult_3)
+ );
+ Mul54 mul (
+ .clk(mul_clk),
+ .reset(mul_reset),
+ .io_val_s0(mul_io_val_s0),
+ .io_latch_a_s0(mul_io_latch_a_s0),
+ .io_a_s0(mul_io_a_s0),
+ .io_latch_b_s0(mul_io_latch_b_s0),
+ .io_b_s0(mul_io_b_s0),
+ .io_c_s2(mul_io_c_s2),
+ .io_result_s3(mul_io_result_s3)
+ );
+ assign io_inReady_div = ds_io_inReady_div;
+ assign io_inReady_sqrt = ds_io_inReady_sqrt;
+ assign io_outValid_div = ds_io_outValid_div;
+ assign io_outValid_sqrt = ds_io_outValid_sqrt;
+ assign io_out = ds_io_out;
+ assign io_exceptionFlags = ds_io_exceptionFlags;
+ assign ds_clk = clk;
+ assign ds_reset = reset;
+ assign ds_io_inValid = io_inValid;
+ assign ds_io_sqrtOp = io_sqrtOp;
+ assign ds_io_a = io_a;
+ assign ds_io_b = io_b;
+ assign ds_io_roundingMode = io_roundingMode;
+ assign ds_io_mulAddResult_3 = mul_io_result_s3;
+ assign mul_clk = clk;
+ assign mul_reset = reset;
+ assign mul_io_val_s0 = T_17;
+ assign mul_io_latch_a_s0 = ds_io_latchMulAddA_0;
+ assign mul_io_a_s0 = ds_io_mulAddA_0;
+ assign mul_io_latch_b_s0 = ds_io_latchMulAddB_0;
+ assign mul_io_b_s0 = ds_io_mulAddB_0;
+ assign mul_io_c_s2 = ds_io_mulAddC_2;
+ assign T_17 = ds_io_usingMulAdd[0];
+endmodule
+module FPU(
+ input clk,
+ input reset,
+ input [31:0] io_inst,
+ input [63:0] io_fromint_data,
+ input [2:0] io_fcsr_rm,
+ output io_fcsr_flags_valid,
+ output [4:0] io_fcsr_flags_bits,
+ output [63:0] io_store_data,
+ output [63:0] io_toint_data,
+ input io_dmem_resp_val,
+ input [2:0] io_dmem_resp_type,
+ input [4:0] io_dmem_resp_tag,
+ input [63:0] io_dmem_resp_data,
+ input io_valid,
+ output io_fcsr_rdy,
+ output io_nack_mem,
+ output io_illegal_rm,
+ input io_killx,
+ input io_killm,
+ output [4:0] io_dec_cmd,
+ output io_dec_ldst,
+ output io_dec_wen,
+ output io_dec_ren1,
+ output io_dec_ren2,
+ output io_dec_ren3,
+ output io_dec_swap12,
+ output io_dec_swap23,
+ output io_dec_single,
+ output io_dec_fromint,
+ output io_dec_toint,
+ output io_dec_fastpipe,
+ output io_dec_fma,
+ output io_dec_div,
+ output io_dec_sqrt,
+ output io_dec_round,
+ output io_dec_wflags,
+ output io_sboard_set,
+ output io_sboard_clr,
+ output [4:0] io_sboard_clra,
+ output io_cp_req_ready,
+ input io_cp_req_valid,
+ input [4:0] io_cp_req_bits_cmd,
+ input io_cp_req_bits_ldst,
+ input io_cp_req_bits_wen,
+ input io_cp_req_bits_ren1,
+ input io_cp_req_bits_ren2,
+ input io_cp_req_bits_ren3,
+ input io_cp_req_bits_swap12,
+ input io_cp_req_bits_swap23,
+ input io_cp_req_bits_single,
+ input io_cp_req_bits_fromint,
+ input io_cp_req_bits_toint,
+ input io_cp_req_bits_fastpipe,
+ input io_cp_req_bits_fma,
+ input io_cp_req_bits_div,
+ input io_cp_req_bits_sqrt,
+ input io_cp_req_bits_round,
+ input io_cp_req_bits_wflags,
+ input [2:0] io_cp_req_bits_rm,
+ input [1:0] io_cp_req_bits_typ,
+ input [64:0] io_cp_req_bits_in1,
+ input [64:0] io_cp_req_bits_in2,
+ input [64:0] io_cp_req_bits_in3,
+ input io_cp_resp_ready,
+ output io_cp_resp_valid,
+ output [64:0] io_cp_resp_bits_data,
+ output [4:0] io_cp_resp_bits_exc
+);
+ reg ex_reg_valid;
+ wire req_valid;
+ reg [31:0] ex_reg_inst;
+ wire T_202;
+ wire ex_cp_valid;
+ wire T_205;
+ wire T_206;
+ wire T_207;
+ reg mem_reg_valid;
+ reg [31:0] mem_reg_inst;
+ reg mem_cp_valid;
+ wire T_213;
+ wire T_215;
+ wire killm;
+ wire T_218;
+ wire T_219;
+ wire T_220;
+ reg wb_reg_valid;
+ reg wb_cp_valid;
+ wire fp_decoder_clk;
+ wire fp_decoder_reset;
+ wire [31:0] fp_decoder_io_inst;
+ wire [4:0] fp_decoder_io_sigs_cmd;
+ wire fp_decoder_io_sigs_ldst;
+ wire fp_decoder_io_sigs_wen;
+ wire fp_decoder_io_sigs_ren1;
+ wire fp_decoder_io_sigs_ren2;
+ wire fp_decoder_io_sigs_ren3;
+ wire fp_decoder_io_sigs_swap12;
+ wire fp_decoder_io_sigs_swap23;
+ wire fp_decoder_io_sigs_single;
+ wire fp_decoder_io_sigs_fromint;
+ wire fp_decoder_io_sigs_toint;
+ wire fp_decoder_io_sigs_fastpipe;
+ wire fp_decoder_io_sigs_fma;
+ wire fp_decoder_io_sigs_div;
+ wire fp_decoder_io_sigs_sqrt;
+ wire fp_decoder_io_sigs_round;
+ wire fp_decoder_io_sigs_wflags;
+ wire [4:0] cp_ctrl_cmd;
+ wire cp_ctrl_ldst;
+ wire cp_ctrl_wen;
+ wire cp_ctrl_ren1;
+ wire cp_ctrl_ren2;
+ wire cp_ctrl_ren3;
+ wire cp_ctrl_swap12;
+ wire cp_ctrl_swap23;
+ wire cp_ctrl_single;
+ wire cp_ctrl_fromint;
+ wire cp_ctrl_toint;
+ wire cp_ctrl_fastpipe;
+ wire cp_ctrl_fma;
+ wire cp_ctrl_div;
+ wire cp_ctrl_sqrt;
+ wire cp_ctrl_round;
+ wire cp_ctrl_wflags;
+ reg [4:0] T_264_cmd;
+ reg T_264_ldst;
+ reg T_264_wen;
+ reg T_264_ren1;
+ reg T_264_ren2;
+ reg T_264_ren3;
+ reg T_264_swap12;
+ reg T_264_swap23;
+ reg T_264_single;
+ reg T_264_fromint;
+ reg T_264_toint;
+ reg T_264_fastpipe;
+ reg T_264_fma;
+ reg T_264_div;
+ reg T_264_sqrt;
+ reg T_264_round;
+ reg T_264_wflags;
+ wire [4:0] ex_ctrl_cmd;
+ wire ex_ctrl_ldst;
+ wire ex_ctrl_wen;
+ wire ex_ctrl_ren1;
+ wire ex_ctrl_ren2;
+ wire ex_ctrl_ren3;
+ wire ex_ctrl_swap12;
+ wire ex_ctrl_swap23;
+ wire ex_ctrl_single;
+ wire ex_ctrl_fromint;
+ wire ex_ctrl_toint;
+ wire ex_ctrl_fastpipe;
+ wire ex_ctrl_fma;
+ wire ex_ctrl_div;
+ wire ex_ctrl_sqrt;
+ wire ex_ctrl_round;
+ wire ex_ctrl_wflags;
+ reg [4:0] mem_ctrl_cmd;
+ reg mem_ctrl_ldst;
+ reg mem_ctrl_wen;
+ reg mem_ctrl_ren1;
+ reg mem_ctrl_ren2;
+ reg mem_ctrl_ren3;
+ reg mem_ctrl_swap12;
+ reg mem_ctrl_swap23;
+ reg mem_ctrl_single;
+ reg mem_ctrl_fromint;
+ reg mem_ctrl_toint;
+ reg mem_ctrl_fastpipe;
+ reg mem_ctrl_fma;
+ reg mem_ctrl_div;
+ reg mem_ctrl_sqrt;
+ reg mem_ctrl_round;
+ reg mem_ctrl_wflags;
+ reg [4:0] wb_ctrl_cmd;
+ reg wb_ctrl_ldst;
+ reg wb_ctrl_wen;
+ reg wb_ctrl_ren1;
+ reg wb_ctrl_ren2;
+ reg wb_ctrl_ren3;
+ reg wb_ctrl_swap12;
+ reg wb_ctrl_swap23;
+ reg wb_ctrl_single;
+ reg wb_ctrl_fromint;
+ reg wb_ctrl_toint;
+ reg wb_ctrl_fastpipe;
+ reg wb_ctrl_fma;
+ reg wb_ctrl_div;
+ reg wb_ctrl_sqrt;
+ reg wb_ctrl_round;
+ reg wb_ctrl_wflags;
+ reg load_wb;
+ wire T_337;
+ wire T_338;
+ wire T_339;
+ reg load_wb_single;
+ reg [63:0] load_wb_data;
+ reg [4:0] load_wb_tag;
+ wire T_343;
+ wire [7:0] T_344;
+ wire [22:0] T_345;
+ wire T_347;
+ wire T_349;
+ wire T_350;
+ wire [31:0] T_351;
+ wire T_352;
+ wire T_354;
+ wire T_356;
+ wire T_358;
+ wire T_360;
+ wire T_362;
+ wire T_364;
+ wire T_366;
+ wire T_368;
+ wire T_370;
+ wire T_372;
+ wire T_374;
+ wire T_376;
+ wire T_378;
+ wire T_380;
+ wire T_382;
+ wire T_384;
+ wire T_386;
+ wire T_388;
+ wire T_390;
+ wire T_392;
+ wire T_394;
+ wire T_396;
+ wire T_398;
+ wire T_400;
+ wire T_402;
+ wire T_404;
+ wire T_406;
+ wire T_408;
+ wire T_410;
+ wire T_412;
+ wire T_413;
+ wire [1:0] T_414;
+ wire [1:0] T_415;
+ wire [2:0] T_416;
+ wire [2:0] T_417;
+ wire [2:0] T_418;
+ wire [2:0] T_419;
+ wire [3:0] T_420;
+ wire [3:0] T_421;
+ wire [3:0] T_422;
+ wire [3:0] T_423;
+ wire [3:0] T_424;
+ wire [3:0] T_425;
+ wire [3:0] T_426;
+ wire [3:0] T_427;
+ wire [4:0] T_428;
+ wire [4:0] T_429;
+ wire [4:0] T_430;
+ wire [4:0] T_431;
+ wire [4:0] T_432;
+ wire [4:0] T_433;
+ wire [4:0] T_434;
+ wire [4:0] T_435;
+ wire [4:0] T_436;
+ wire [4:0] T_437;
+ wire [4:0] T_438;
+ wire [4:0] T_439;
+ wire [4:0] T_440;
+ wire [4:0] T_441;
+ wire [4:0] T_442;
+ wire [4:0] T_443;
+ wire [4:0] T_444;
+ wire [53:0] T_445;
+ wire [21:0] T_446;
+ wire [22:0] T_448;
+ wire [9:0] T_451;
+ wire [8:0] T_452;
+ wire [8:0] T_453;
+ wire [8:0] T_454;
+ wire [1:0] T_458;
+ wire [7:0] T_459;
+ wire [9:0] T_460;
+ wire [8:0] T_461;
+ wire [1:0] T_462;
+ wire T_464;
+ wire T_466;
+ wire T_467;
+ wire [3:0] T_469;
+ wire [2:0] T_470;
+ wire [8:0] T_471;
+ wire [8:0] T_472;
+ wire [8:0] T_473;
+ wire [6:0] T_474;
+ wire [8:0] T_475;
+ wire [22:0] T_476;
+ wire [31:0] T_477;
+ wire [32:0] rec_s;
+ wire T_479;
+ wire [10:0] T_480;
+ wire [51:0] T_481;
+ wire T_483;
+ wire T_485;
+ wire T_486;
+ wire [63:0] T_487;
+ wire T_488;
+ wire T_490;
+ wire T_492;
+ wire T_494;
+ wire T_496;
+ wire T_498;
+ wire T_500;
+ wire T_502;
+ wire T_504;
+ wire T_506;
+ wire T_508;
+ wire T_510;
+ wire T_512;
+ wire T_514;
+ wire T_516;
+ wire T_518;
+ wire T_520;
+ wire T_522;
+ wire T_524;
+ wire T_526;
+ wire T_528;
+ wire T_530;
+ wire T_532;
+ wire T_534;
+ wire T_536;
+ wire T_538;
+ wire T_540;
+ wire T_542;
+ wire T_544;
+ wire T_546;
+ wire T_548;
+ wire T_550;
+ wire T_552;
+ wire T_554;
+ wire T_556;
+ wire T_558;
+ wire T_560;
+ wire T_562;
+ wire T_564;
+ wire T_566;
+ wire T_568;
+ wire T_570;
+ wire T_572;
+ wire T_574;
+ wire T_576;
+ wire T_578;
+ wire T_580;
+ wire T_582;
+ wire T_584;
+ wire T_586;
+ wire T_588;
+ wire T_590;
+ wire T_592;
+ wire T_594;
+ wire T_596;
+ wire T_598;
+ wire T_600;
+ wire T_602;
+ wire T_604;
+ wire T_606;
+ wire T_608;
+ wire T_610;
+ wire T_612;
+ wire T_613;
+ wire [1:0] T_614;
+ wire [1:0] T_615;
+ wire [2:0] T_616;
+ wire [2:0] T_617;
+ wire [2:0] T_618;
+ wire [2:0] T_619;
+ wire [3:0] T_620;
+ wire [3:0] T_621;
+ wire [3:0] T_622;
+ wire [3:0] T_623;
+ wire [3:0] T_624;
+ wire [3:0] T_625;
+ wire [3:0] T_626;
+ wire [3:0] T_627;
+ wire [4:0] T_628;
+ wire [4:0] T_629;
+ wire [4:0] T_630;
+ wire [4:0] T_631;
+ wire [4:0] T_632;
+ wire [4:0] T_633;
+ wire [4:0] T_634;
+ wire [4:0] T_635;
+ wire [4:0] T_636;
+ wire [4:0] T_637;
+ wire [4:0] T_638;
+ wire [4:0] T_639;
+ wire [4:0] T_640;
+ wire [4:0] T_641;
+ wire [4:0] T_642;
+ wire [4:0] T_643;
+ wire [5:0] T_644;
+ wire [5:0] T_645;
+ wire [5:0] T_646;
+ wire [5:0] T_647;
+ wire [5:0] T_648;
+ wire [5:0] T_649;
+ wire [5:0] T_650;
+ wire [5:0] T_651;
+ wire [5:0] T_652;
+ wire [5:0] T_653;
+ wire [5:0] T_654;
+ wire [5:0] T_655;
+ wire [5:0] T_656;
+ wire [5:0] T_657;
+ wire [5:0] T_658;
+ wire [5:0] T_659;
+ wire [5:0] T_660;
+ wire [5:0] T_661;
+ wire [5:0] T_662;
+ wire [5:0] T_663;
+ wire [5:0] T_664;
+ wire [5:0] T_665;
+ wire [5:0] T_666;
+ wire [5:0] T_667;
+ wire [5:0] T_668;
+ wire [5:0] T_669;
+ wire [5:0] T_670;
+ wire [5:0] T_671;
+ wire [5:0] T_672;
+ wire [5:0] T_673;
+ wire [5:0] T_674;
+ wire [5:0] T_675;
+ wire [5:0] T_676;
+ wire [114:0] T_677;
+ wire [50:0] T_678;
+ wire [51:0] T_680;
+ wire [12:0] T_683;
+ wire [11:0] T_684;
+ wire [11:0] T_685;
+ wire [11:0] T_686;
+ wire [1:0] T_690;
+ wire [10:0] T_691;
+ wire [12:0] T_692;
+ wire [11:0] T_693;
+ wire [1:0] T_694;
+ wire T_696;
+ wire T_698;
+ wire T_699;
+ wire [3:0] T_701;
+ wire [2:0] T_702;
+ wire [11:0] T_703;
+ wire [11:0] T_704;
+ wire [11:0] T_705;
+ wire [9:0] T_706;
+ wire [11:0] T_707;
+ wire [51:0] T_708;
+ wire [63:0] T_709;
+ wire [64:0] rec_d;
+ wire [31:0] GEN_2;
+ wire [31:0] T_712;
+ wire [64:0] T_713;
+ wire [64:0] load_wb_data_recoded;
+ reg [64:0] regfile [0:31];
+ wire [64:0] regfile_ex_rs1_data;
+ wire [4:0] regfile_ex_rs1_addr;
+ wire regfile_ex_rs1_en;
+ wire regfile_ex_rs1_clk;
+ wire [64:0] regfile_ex_rs2_data;
+ wire [4:0] regfile_ex_rs2_addr;
+ wire regfile_ex_rs2_en;
+ wire regfile_ex_rs2_clk;
+ wire [64:0] regfile_ex_rs3_data;
+ wire [4:0] regfile_ex_rs3_addr;
+ wire regfile_ex_rs3_en;
+ wire regfile_ex_rs3_clk;
+ wire [64:0] regfile_T_718_data;
+ wire [4:0] regfile_T_718_addr;
+ wire regfile_T_718_mask;
+ wire regfile_T_718_en;
+ wire regfile_T_718_clk;
+ wire [64:0] regfile_T_985_data;
+ wire [4:0] regfile_T_985_addr;
+ wire regfile_T_985_mask;
+ wire regfile_T_985_en;
+ wire regfile_T_985_clk;
+ reg [4:0] ex_ra1;
+ reg [4:0] ex_ra2;
+ reg [4:0] ex_ra3;
+ wire T_726;
+ wire [4:0] T_727;
+ wire [4:0] T_728;
+ wire [4:0] T_729;
+ wire [4:0] T_730;
+ wire T_732;
+ wire T_734;
+ wire T_735;
+ wire [4:0] T_736;
+ wire [4:0] T_737;
+ wire [2:0] T_741;
+ wire T_743;
+ wire [2:0] T_744;
+ wire [2:0] ex_rm;
+ wire [64:0] cp_rs2;
+ wire [64:0] cp_rs3;
+ wire [4:0] req_cmd;
+ wire req_ldst;
+ wire req_wen;
+ wire req_ren1;
+ wire req_ren2;
+ wire req_ren3;
+ wire req_swap12;
+ wire req_swap23;
+ wire req_single;
+ wire req_fromint;
+ wire req_toint;
+ wire req_fastpipe;
+ wire req_fma;
+ wire req_div;
+ wire req_sqrt;
+ wire req_round;
+ wire req_wflags;
+ wire [2:0] req_rm;
+ wire [1:0] req_typ;
+ wire [64:0] req_in1;
+ wire [64:0] req_in2;
+ wire [64:0] req_in3;
+ wire [2:0] T_794;
+ wire [64:0] T_795;
+ wire [64:0] T_796;
+ wire [64:0] T_797;
+ wire [1:0] T_798;
+ wire [1:0] T_799;
+ wire sfma_clk;
+ wire sfma_reset;
+ wire sfma_io_in_valid;
+ wire [4:0] sfma_io_in_bits_cmd;
+ wire sfma_io_in_bits_ldst;
+ wire sfma_io_in_bits_wen;
+ wire sfma_io_in_bits_ren1;
+ wire sfma_io_in_bits_ren2;
+ wire sfma_io_in_bits_ren3;
+ wire sfma_io_in_bits_swap12;
+ wire sfma_io_in_bits_swap23;
+ wire sfma_io_in_bits_single;
+ wire sfma_io_in_bits_fromint;
+ wire sfma_io_in_bits_toint;
+ wire sfma_io_in_bits_fastpipe;
+ wire sfma_io_in_bits_fma;
+ wire sfma_io_in_bits_div;
+ wire sfma_io_in_bits_sqrt;
+ wire sfma_io_in_bits_round;
+ wire sfma_io_in_bits_wflags;
+ wire [2:0] sfma_io_in_bits_rm;
+ wire [1:0] sfma_io_in_bits_typ;
+ wire [64:0] sfma_io_in_bits_in1;
+ wire [64:0] sfma_io_in_bits_in2;
+ wire [64:0] sfma_io_in_bits_in3;
+ wire sfma_io_out_valid;
+ wire [64:0] sfma_io_out_bits_data;
+ wire [4:0] sfma_io_out_bits_exc;
+ wire T_801;
+ wire T_802;
+ wire dfma_clk;
+ wire dfma_reset;
+ wire dfma_io_in_valid;
+ wire [4:0] dfma_io_in_bits_cmd;
+ wire dfma_io_in_bits_ldst;
+ wire dfma_io_in_bits_wen;
+ wire dfma_io_in_bits_ren1;
+ wire dfma_io_in_bits_ren2;
+ wire dfma_io_in_bits_ren3;
+ wire dfma_io_in_bits_swap12;
+ wire dfma_io_in_bits_swap23;
+ wire dfma_io_in_bits_single;
+ wire dfma_io_in_bits_fromint;
+ wire dfma_io_in_bits_toint;
+ wire dfma_io_in_bits_fastpipe;
+ wire dfma_io_in_bits_fma;
+ wire dfma_io_in_bits_div;
+ wire dfma_io_in_bits_sqrt;
+ wire dfma_io_in_bits_round;
+ wire dfma_io_in_bits_wflags;
+ wire [2:0] dfma_io_in_bits_rm;
+ wire [1:0] dfma_io_in_bits_typ;
+ wire [64:0] dfma_io_in_bits_in1;
+ wire [64:0] dfma_io_in_bits_in2;
+ wire [64:0] dfma_io_in_bits_in3;
+ wire dfma_io_out_valid;
+ wire [64:0] dfma_io_out_bits_data;
+ wire [4:0] dfma_io_out_bits_exc;
+ wire T_804;
+ wire T_806;
+ wire T_807;
+ wire fpiu_clk;
+ wire fpiu_reset;
+ wire fpiu_io_in_valid;
+ wire [4:0] fpiu_io_in_bits_cmd;
+ wire fpiu_io_in_bits_ldst;
+ wire fpiu_io_in_bits_wen;
+ wire fpiu_io_in_bits_ren1;
+ wire fpiu_io_in_bits_ren2;
+ wire fpiu_io_in_bits_ren3;
+ wire fpiu_io_in_bits_swap12;
+ wire fpiu_io_in_bits_swap23;
+ wire fpiu_io_in_bits_single;
+ wire fpiu_io_in_bits_fromint;
+ wire fpiu_io_in_bits_toint;
+ wire fpiu_io_in_bits_fastpipe;
+ wire fpiu_io_in_bits_fma;
+ wire fpiu_io_in_bits_div;
+ wire fpiu_io_in_bits_sqrt;
+ wire fpiu_io_in_bits_round;
+ wire fpiu_io_in_bits_wflags;
+ wire [2:0] fpiu_io_in_bits_rm;
+ wire [1:0] fpiu_io_in_bits_typ;
+ wire [64:0] fpiu_io_in_bits_in1;
+ wire [64:0] fpiu_io_in_bits_in2;
+ wire [64:0] fpiu_io_in_bits_in3;
+ wire [4:0] fpiu_io_as_double_cmd;
+ wire fpiu_io_as_double_ldst;
+ wire fpiu_io_as_double_wen;
+ wire fpiu_io_as_double_ren1;
+ wire fpiu_io_as_double_ren2;
+ wire fpiu_io_as_double_ren3;
+ wire fpiu_io_as_double_swap12;
+ wire fpiu_io_as_double_swap23;
+ wire fpiu_io_as_double_single;
+ wire fpiu_io_as_double_fromint;
+ wire fpiu_io_as_double_toint;
+ wire fpiu_io_as_double_fastpipe;
+ wire fpiu_io_as_double_fma;
+ wire fpiu_io_as_double_div;
+ wire fpiu_io_as_double_sqrt;
+ wire fpiu_io_as_double_round;
+ wire fpiu_io_as_double_wflags;
+ wire [2:0] fpiu_io_as_double_rm;
+ wire [1:0] fpiu_io_as_double_typ;
+ wire [64:0] fpiu_io_as_double_in1;
+ wire [64:0] fpiu_io_as_double_in2;
+ wire [64:0] fpiu_io_as_double_in3;
+ wire fpiu_io_out_valid;
+ wire fpiu_io_out_bits_lt;
+ wire [63:0] fpiu_io_out_bits_store;
+ wire [63:0] fpiu_io_out_bits_toint;
+ wire [4:0] fpiu_io_out_bits_exc;
+ wire T_809;
+ wire T_810;
+ wire [4:0] T_813;
+ wire T_814;
+ wire T_815;
+ wire T_816;
+ wire T_817;
+ wire T_818;
+ wire ifpu_clk;
+ wire ifpu_reset;
+ wire ifpu_io_in_valid;
+ wire [4:0] ifpu_io_in_bits_cmd;
+ wire ifpu_io_in_bits_ldst;
+ wire ifpu_io_in_bits_wen;
+ wire ifpu_io_in_bits_ren1;
+ wire ifpu_io_in_bits_ren2;
+ wire ifpu_io_in_bits_ren3;
+ wire ifpu_io_in_bits_swap12;
+ wire ifpu_io_in_bits_swap23;
+ wire ifpu_io_in_bits_single;
+ wire ifpu_io_in_bits_fromint;
+ wire ifpu_io_in_bits_toint;
+ wire ifpu_io_in_bits_fastpipe;
+ wire ifpu_io_in_bits_fma;
+ wire ifpu_io_in_bits_div;
+ wire ifpu_io_in_bits_sqrt;
+ wire ifpu_io_in_bits_round;
+ wire ifpu_io_in_bits_wflags;
+ wire [2:0] ifpu_io_in_bits_rm;
+ wire [1:0] ifpu_io_in_bits_typ;
+ wire [64:0] ifpu_io_in_bits_in1;
+ wire [64:0] ifpu_io_in_bits_in2;
+ wire [64:0] ifpu_io_in_bits_in3;
+ wire ifpu_io_out_valid;
+ wire [64:0] ifpu_io_out_bits_data;
+ wire [4:0] ifpu_io_out_bits_exc;
+ wire T_821;
+ wire [64:0] T_822;
+ wire fpmu_clk;
+ wire fpmu_reset;
+ wire fpmu_io_in_valid;
+ wire [4:0] fpmu_io_in_bits_cmd;
+ wire fpmu_io_in_bits_ldst;
+ wire fpmu_io_in_bits_wen;
+ wire fpmu_io_in_bits_ren1;
+ wire fpmu_io_in_bits_ren2;
+ wire fpmu_io_in_bits_ren3;
+ wire fpmu_io_in_bits_swap12;
+ wire fpmu_io_in_bits_swap23;
+ wire fpmu_io_in_bits_single;
+ wire fpmu_io_in_bits_fromint;
+ wire fpmu_io_in_bits_toint;
+ wire fpmu_io_in_bits_fastpipe;
+ wire fpmu_io_in_bits_fma;
+ wire fpmu_io_in_bits_div;
+ wire fpmu_io_in_bits_sqrt;
+ wire fpmu_io_in_bits_round;
+ wire fpmu_io_in_bits_wflags;
+ wire [2:0] fpmu_io_in_bits_rm;
+ wire [1:0] fpmu_io_in_bits_typ;
+ wire [64:0] fpmu_io_in_bits_in1;
+ wire [64:0] fpmu_io_in_bits_in2;
+ wire [64:0] fpmu_io_in_bits_in3;
+ wire fpmu_io_out_valid;
+ wire [64:0] fpmu_io_out_bits_data;
+ wire [4:0] fpmu_io_out_bits_exc;
+ wire fpmu_io_lt;
+ wire T_824;
+ reg divSqrt_wen;
+ wire divSqrt_inReady;
+ reg [4:0] divSqrt_waddr;
+ wire [64:0] divSqrt_wdata;
+ wire [4:0] divSqrt_flags;
+ reg divSqrt_in_flight;
+ reg divSqrt_killed;
+ wire T_841;
+ wire [1:0] T_844;
+ wire T_845;
+ wire T_848;
+ wire T_850;
+ wire T_851;
+ wire [1:0] T_854;
+ wire [1:0] T_855;
+ wire [1:0] T_856;
+ wire [1:0] memLatencyMask;
+ reg [1:0] wen;
+ reg [8:0] winfo_0;
+ reg [8:0] winfo_1;
+ wire T_872;
+ wire T_873;
+ wire mem_wen;
+ wire [1:0] T_877;
+ wire [2:0] T_880;
+ wire T_881;
+ wire [1:0] T_884;
+ wire T_886;
+ wire T_887;
+ wire [2:0] T_890;
+ wire [2:0] T_891;
+ wire [2:0] T_892;
+ wire [2:0] T_893;
+ wire [2:0] T_894;
+ wire T_896;
+ wire T_897;
+ wire [2:0] T_900;
+ wire [3:0] T_903;
+ wire T_904;
+ wire [2:0] T_907;
+ wire T_909;
+ wire T_910;
+ wire [3:0] T_913;
+ wire [3:0] T_914;
+ wire [3:0] T_915;
+ wire [3:0] T_916;
+ wire [3:0] T_917;
+ wire T_919;
+ wire T_920;
+ reg write_port_busy;
+ wire T_924;
+ wire T_927;
+ wire T_928;
+ wire [1:0] T_931;
+ wire T_933;
+ wire T_934;
+ wire [1:0] T_937;
+ wire T_938;
+ wire [1:0] T_939;
+ wire [1:0] T_940;
+ wire [4:0] T_941;
+ wire [2:0] T_942;
+ wire [5:0] T_943;
+ wire [8:0] mem_winfo;
+ wire T_945;
+ wire T_946;
+ wire T_948;
+ wire T_949;
+ wire [1:0] T_950;
+ wire T_952;
+ wire T_953;
+ wire T_954;
+ wire T_956;
+ wire T_957;
+ wire T_958;
+ wire [4:0] T_959;
+ wire [4:0] waddr;
+ wire [2:0] wsrc;
+ wire wcp;
+ wire [64:0] T_964_0;
+ wire [64:0] T_964_1;
+ wire [64:0] T_964_2;
+ wire [64:0] T_964_3;
+ wire [64:0] GEN_0;
+ wire [64:0] wdata;
+ wire [4:0] T_973_0;
+ wire [4:0] T_973_1;
+ wire [4:0] T_973_2;
+ wire [4:0] T_973_3;
+ wire T_981;
+ wire T_982;
+ wire T_983;
+ wire T_984;
+ wire T_986;
+ wire T_987;
+ wire T_990;
+ wire wb_toint_valid;
+ reg [4:0] wb_toint_exc;
+ wire T_993;
+ wire T_994;
+ wire T_995;
+ wire [4:0] T_997;
+ wire [4:0] T_999;
+ wire [4:0] T_1000;
+ wire T_1001;
+ wire [4:0] GEN_1;
+ wire [4:0] T_1003;
+ wire [4:0] T_1004;
+ wire T_1005;
+ wire T_1006;
+ wire T_1008;
+ wire T_1010;
+ wire T_1011;
+ wire units_busy;
+ wire T_1013;
+ wire T_1014;
+ wire T_1015;
+ wire T_1016;
+ wire T_1017;
+ wire T_1019;
+ wire T_1020;
+ wire T_1021;
+ wire T_1023;
+ wire T_1024;
+ wire T_1025;
+ wire T_1027;
+ wire T_1028;
+ wire T_1030;
+ wire T_1031;
+ reg T_1032;
+ wire T_1033;
+ wire T_1035;
+ wire T_1036;
+ wire T_1038;
+ wire T_1039;
+ wire T_1040;
+ wire T_1041;
+ wire T_1042;
+ reg T_1046;
+ reg [1:0] T_1048;
+ reg [4:0] T_1050;
+ reg [64:0] T_1052;
+ wire T_1053_clk;
+ wire T_1053_reset;
+ wire T_1053_io_inReady_div;
+ wire T_1053_io_inReady_sqrt;
+ wire T_1053_io_inValid;
+ wire T_1053_io_sqrtOp;
+ wire [64:0] T_1053_io_a;
+ wire [64:0] T_1053_io_b;
+ wire [1:0] T_1053_io_roundingMode;
+ wire T_1053_io_outValid_div;
+ wire T_1053_io_outValid_sqrt;
+ wire [64:0] T_1053_io_out;
+ wire [4:0] T_1053_io_exceptionFlags;
+ wire T_1054;
+ wire T_1055;
+ wire T_1056;
+ wire T_1057;
+ wire T_1059;
+ wire T_1060;
+ wire T_1061;
+ wire [4:0] T_1063;
+ wire T_1065;
+ wire T_1067_clk;
+ wire T_1067_reset;
+ wire [64:0] T_1067_io_in;
+ wire [1:0] T_1067_io_roundingMode;
+ wire [32:0] T_1067_io_out;
+ wire [4:0] T_1067_io_exceptionFlags;
+ wire [64:0] T_1068;
+ wire [4:0] T_1070;
+ wire [4:0] T_1071;
+ wire GEN_3;
+ wire GEN_4;
+ wire GEN_5;
+ wire GEN_6;
+ wire GEN_7;
+ wire GEN_8;
+ reg [4:0] GEN_9;
+ FPUDecoder fp_decoder (
+ .clk(fp_decoder_clk),
+ .reset(fp_decoder_reset),
+ .io_inst(fp_decoder_io_inst),
+ .io_sigs_cmd(fp_decoder_io_sigs_cmd),
+ .io_sigs_ldst(fp_decoder_io_sigs_ldst),
+ .io_sigs_wen(fp_decoder_io_sigs_wen),
+ .io_sigs_ren1(fp_decoder_io_sigs_ren1),
+ .io_sigs_ren2(fp_decoder_io_sigs_ren2),
+ .io_sigs_ren3(fp_decoder_io_sigs_ren3),
+ .io_sigs_swap12(fp_decoder_io_sigs_swap12),
+ .io_sigs_swap23(fp_decoder_io_sigs_swap23),
+ .io_sigs_single(fp_decoder_io_sigs_single),
+ .io_sigs_fromint(fp_decoder_io_sigs_fromint),
+ .io_sigs_toint(fp_decoder_io_sigs_toint),
+ .io_sigs_fastpipe(fp_decoder_io_sigs_fastpipe),
+ .io_sigs_fma(fp_decoder_io_sigs_fma),
+ .io_sigs_div(fp_decoder_io_sigs_div),
+ .io_sigs_sqrt(fp_decoder_io_sigs_sqrt),
+ .io_sigs_round(fp_decoder_io_sigs_round),
+ .io_sigs_wflags(fp_decoder_io_sigs_wflags)
+ );
+ FPUFMAPipe sfma (
+ .clk(sfma_clk),
+ .reset(sfma_reset),
+ .io_in_valid(sfma_io_in_valid),
+ .io_in_bits_cmd(sfma_io_in_bits_cmd),
+ .io_in_bits_ldst(sfma_io_in_bits_ldst),
+ .io_in_bits_wen(sfma_io_in_bits_wen),
+ .io_in_bits_ren1(sfma_io_in_bits_ren1),
+ .io_in_bits_ren2(sfma_io_in_bits_ren2),
+ .io_in_bits_ren3(sfma_io_in_bits_ren3),
+ .io_in_bits_swap12(sfma_io_in_bits_swap12),
+ .io_in_bits_swap23(sfma_io_in_bits_swap23),
+ .io_in_bits_single(sfma_io_in_bits_single),
+ .io_in_bits_fromint(sfma_io_in_bits_fromint),
+ .io_in_bits_toint(sfma_io_in_bits_toint),
+ .io_in_bits_fastpipe(sfma_io_in_bits_fastpipe),
+ .io_in_bits_fma(sfma_io_in_bits_fma),
+ .io_in_bits_div(sfma_io_in_bits_div),
+ .io_in_bits_sqrt(sfma_io_in_bits_sqrt),
+ .io_in_bits_round(sfma_io_in_bits_round),
+ .io_in_bits_wflags(sfma_io_in_bits_wflags),
+ .io_in_bits_rm(sfma_io_in_bits_rm),
+ .io_in_bits_typ(sfma_io_in_bits_typ),
+ .io_in_bits_in1(sfma_io_in_bits_in1),
+ .io_in_bits_in2(sfma_io_in_bits_in2),
+ .io_in_bits_in3(sfma_io_in_bits_in3),
+ .io_out_valid(sfma_io_out_valid),
+ .io_out_bits_data(sfma_io_out_bits_data),
+ .io_out_bits_exc(sfma_io_out_bits_exc)
+ );
+ FPUFMAPipe_113 dfma (
+ .clk(dfma_clk),
+ .reset(dfma_reset),
+ .io_in_valid(dfma_io_in_valid),
+ .io_in_bits_cmd(dfma_io_in_bits_cmd),
+ .io_in_bits_ldst(dfma_io_in_bits_ldst),
+ .io_in_bits_wen(dfma_io_in_bits_wen),
+ .io_in_bits_ren1(dfma_io_in_bits_ren1),
+ .io_in_bits_ren2(dfma_io_in_bits_ren2),
+ .io_in_bits_ren3(dfma_io_in_bits_ren3),
+ .io_in_bits_swap12(dfma_io_in_bits_swap12),
+ .io_in_bits_swap23(dfma_io_in_bits_swap23),
+ .io_in_bits_single(dfma_io_in_bits_single),
+ .io_in_bits_fromint(dfma_io_in_bits_fromint),
+ .io_in_bits_toint(dfma_io_in_bits_toint),
+ .io_in_bits_fastpipe(dfma_io_in_bits_fastpipe),
+ .io_in_bits_fma(dfma_io_in_bits_fma),
+ .io_in_bits_div(dfma_io_in_bits_div),
+ .io_in_bits_sqrt(dfma_io_in_bits_sqrt),
+ .io_in_bits_round(dfma_io_in_bits_round),
+ .io_in_bits_wflags(dfma_io_in_bits_wflags),
+ .io_in_bits_rm(dfma_io_in_bits_rm),
+ .io_in_bits_typ(dfma_io_in_bits_typ),
+ .io_in_bits_in1(dfma_io_in_bits_in1),
+ .io_in_bits_in2(dfma_io_in_bits_in2),
+ .io_in_bits_in3(dfma_io_in_bits_in3),
+ .io_out_valid(dfma_io_out_valid),
+ .io_out_bits_data(dfma_io_out_bits_data),
+ .io_out_bits_exc(dfma_io_out_bits_exc)
+ );
+ FPToInt fpiu (
+ .clk(fpiu_clk),
+ .reset(fpiu_reset),
+ .io_in_valid(fpiu_io_in_valid),
+ .io_in_bits_cmd(fpiu_io_in_bits_cmd),
+ .io_in_bits_ldst(fpiu_io_in_bits_ldst),
+ .io_in_bits_wen(fpiu_io_in_bits_wen),
+ .io_in_bits_ren1(fpiu_io_in_bits_ren1),
+ .io_in_bits_ren2(fpiu_io_in_bits_ren2),
+ .io_in_bits_ren3(fpiu_io_in_bits_ren3),
+ .io_in_bits_swap12(fpiu_io_in_bits_swap12),
+ .io_in_bits_swap23(fpiu_io_in_bits_swap23),
+ .io_in_bits_single(fpiu_io_in_bits_single),
+ .io_in_bits_fromint(fpiu_io_in_bits_fromint),
+ .io_in_bits_toint(fpiu_io_in_bits_toint),
+ .io_in_bits_fastpipe(fpiu_io_in_bits_fastpipe),
+ .io_in_bits_fma(fpiu_io_in_bits_fma),
+ .io_in_bits_div(fpiu_io_in_bits_div),
+ .io_in_bits_sqrt(fpiu_io_in_bits_sqrt),
+ .io_in_bits_round(fpiu_io_in_bits_round),
+ .io_in_bits_wflags(fpiu_io_in_bits_wflags),
+ .io_in_bits_rm(fpiu_io_in_bits_rm),
+ .io_in_bits_typ(fpiu_io_in_bits_typ),
+ .io_in_bits_in1(fpiu_io_in_bits_in1),
+ .io_in_bits_in2(fpiu_io_in_bits_in2),
+ .io_in_bits_in3(fpiu_io_in_bits_in3),
+ .io_as_double_cmd(fpiu_io_as_double_cmd),
+ .io_as_double_ldst(fpiu_io_as_double_ldst),
+ .io_as_double_wen(fpiu_io_as_double_wen),
+ .io_as_double_ren1(fpiu_io_as_double_ren1),
+ .io_as_double_ren2(fpiu_io_as_double_ren2),
+ .io_as_double_ren3(fpiu_io_as_double_ren3),
+ .io_as_double_swap12(fpiu_io_as_double_swap12),
+ .io_as_double_swap23(fpiu_io_as_double_swap23),
+ .io_as_double_single(fpiu_io_as_double_single),
+ .io_as_double_fromint(fpiu_io_as_double_fromint),
+ .io_as_double_toint(fpiu_io_as_double_toint),
+ .io_as_double_fastpipe(fpiu_io_as_double_fastpipe),
+ .io_as_double_fma(fpiu_io_as_double_fma),
+ .io_as_double_div(fpiu_io_as_double_div),
+ .io_as_double_sqrt(fpiu_io_as_double_sqrt),
+ .io_as_double_round(fpiu_io_as_double_round),
+ .io_as_double_wflags(fpiu_io_as_double_wflags),
+ .io_as_double_rm(fpiu_io_as_double_rm),
+ .io_as_double_typ(fpiu_io_as_double_typ),
+ .io_as_double_in1(fpiu_io_as_double_in1),
+ .io_as_double_in2(fpiu_io_as_double_in2),
+ .io_as_double_in3(fpiu_io_as_double_in3),
+ .io_out_valid(fpiu_io_out_valid),
+ .io_out_bits_lt(fpiu_io_out_bits_lt),
+ .io_out_bits_store(fpiu_io_out_bits_store),
+ .io_out_bits_toint(fpiu_io_out_bits_toint),
+ .io_out_bits_exc(fpiu_io_out_bits_exc)
+ );
+ IntToFP ifpu (
+ .clk(ifpu_clk),
+ .reset(ifpu_reset),
+ .io_in_valid(ifpu_io_in_valid),
+ .io_in_bits_cmd(ifpu_io_in_bits_cmd),
+ .io_in_bits_ldst(ifpu_io_in_bits_ldst),
+ .io_in_bits_wen(ifpu_io_in_bits_wen),
+ .io_in_bits_ren1(ifpu_io_in_bits_ren1),
+ .io_in_bits_ren2(ifpu_io_in_bits_ren2),
+ .io_in_bits_ren3(ifpu_io_in_bits_ren3),
+ .io_in_bits_swap12(ifpu_io_in_bits_swap12),
+ .io_in_bits_swap23(ifpu_io_in_bits_swap23),
+ .io_in_bits_single(ifpu_io_in_bits_single),
+ .io_in_bits_fromint(ifpu_io_in_bits_fromint),
+ .io_in_bits_toint(ifpu_io_in_bits_toint),
+ .io_in_bits_fastpipe(ifpu_io_in_bits_fastpipe),
+ .io_in_bits_fma(ifpu_io_in_bits_fma),
+ .io_in_bits_div(ifpu_io_in_bits_div),
+ .io_in_bits_sqrt(ifpu_io_in_bits_sqrt),
+ .io_in_bits_round(ifpu_io_in_bits_round),
+ .io_in_bits_wflags(ifpu_io_in_bits_wflags),
+ .io_in_bits_rm(ifpu_io_in_bits_rm),
+ .io_in_bits_typ(ifpu_io_in_bits_typ),
+ .io_in_bits_in1(ifpu_io_in_bits_in1),
+ .io_in_bits_in2(ifpu_io_in_bits_in2),
+ .io_in_bits_in3(ifpu_io_in_bits_in3),
+ .io_out_valid(ifpu_io_out_valid),
+ .io_out_bits_data(ifpu_io_out_bits_data),
+ .io_out_bits_exc(ifpu_io_out_bits_exc)
+ );
+ FPToFP fpmu (
+ .clk(fpmu_clk),
+ .reset(fpmu_reset),
+ .io_in_valid(fpmu_io_in_valid),
+ .io_in_bits_cmd(fpmu_io_in_bits_cmd),
+ .io_in_bits_ldst(fpmu_io_in_bits_ldst),
+ .io_in_bits_wen(fpmu_io_in_bits_wen),
+ .io_in_bits_ren1(fpmu_io_in_bits_ren1),
+ .io_in_bits_ren2(fpmu_io_in_bits_ren2),
+ .io_in_bits_ren3(fpmu_io_in_bits_ren3),
+ .io_in_bits_swap12(fpmu_io_in_bits_swap12),
+ .io_in_bits_swap23(fpmu_io_in_bits_swap23),
+ .io_in_bits_single(fpmu_io_in_bits_single),
+ .io_in_bits_fromint(fpmu_io_in_bits_fromint),
+ .io_in_bits_toint(fpmu_io_in_bits_toint),
+ .io_in_bits_fastpipe(fpmu_io_in_bits_fastpipe),
+ .io_in_bits_fma(fpmu_io_in_bits_fma),
+ .io_in_bits_div(fpmu_io_in_bits_div),
+ .io_in_bits_sqrt(fpmu_io_in_bits_sqrt),
+ .io_in_bits_round(fpmu_io_in_bits_round),
+ .io_in_bits_wflags(fpmu_io_in_bits_wflags),
+ .io_in_bits_rm(fpmu_io_in_bits_rm),
+ .io_in_bits_typ(fpmu_io_in_bits_typ),
+ .io_in_bits_in1(fpmu_io_in_bits_in1),
+ .io_in_bits_in2(fpmu_io_in_bits_in2),
+ .io_in_bits_in3(fpmu_io_in_bits_in3),
+ .io_out_valid(fpmu_io_out_valid),
+ .io_out_bits_data(fpmu_io_out_bits_data),
+ .io_out_bits_exc(fpmu_io_out_bits_exc),
+ .io_lt(fpmu_io_lt)
+ );
+ DivSqrtRecF64 T_1053 (
+ .clk(T_1053_clk),
+ .reset(T_1053_reset),
+ .io_inReady_div(T_1053_io_inReady_div),
+ .io_inReady_sqrt(T_1053_io_inReady_sqrt),
+ .io_inValid(T_1053_io_inValid),
+ .io_sqrtOp(T_1053_io_sqrtOp),
+ .io_a(T_1053_io_a),
+ .io_b(T_1053_io_b),
+ .io_roundingMode(T_1053_io_roundingMode),
+ .io_outValid_div(T_1053_io_outValid_div),
+ .io_outValid_sqrt(T_1053_io_outValid_sqrt),
+ .io_out(T_1053_io_out),
+ .io_exceptionFlags(T_1053_io_exceptionFlags)
+ );
+ RecFNToRecFN_121 T_1067 (
+ .clk(T_1067_clk),
+ .reset(T_1067_reset),
+ .io_in(T_1067_io_in),
+ .io_roundingMode(T_1067_io_roundingMode),
+ .io_out(T_1067_io_out),
+ .io_exceptionFlags(T_1067_io_exceptionFlags)
+ );
+ assign io_fcsr_flags_valid = T_995;
+ assign io_fcsr_flags_bits = T_1004;
+ assign io_store_data = fpiu_io_out_bits_store;
+ assign io_toint_data = fpiu_io_out_bits_toint;
+ assign io_fcsr_rdy = T_1023;
+ assign io_nack_mem = T_1025;
+ assign io_illegal_rm = T_1042;
+ assign io_dec_cmd = fp_decoder_io_sigs_cmd;
+ assign io_dec_ldst = fp_decoder_io_sigs_ldst;
+ assign io_dec_wen = fp_decoder_io_sigs_wen;
+ assign io_dec_ren1 = fp_decoder_io_sigs_ren1;
+ assign io_dec_ren2 = fp_decoder_io_sigs_ren2;
+ assign io_dec_ren3 = fp_decoder_io_sigs_ren3;
+ assign io_dec_swap12 = fp_decoder_io_sigs_swap12;
+ assign io_dec_swap23 = fp_decoder_io_sigs_swap23;
+ assign io_dec_single = fp_decoder_io_sigs_single;
+ assign io_dec_fromint = fp_decoder_io_sigs_fromint;
+ assign io_dec_toint = fp_decoder_io_sigs_toint;
+ assign io_dec_fastpipe = fp_decoder_io_sigs_fastpipe;
+ assign io_dec_fma = fp_decoder_io_sigs_fma;
+ assign io_dec_div = fp_decoder_io_sigs_div;
+ assign io_dec_sqrt = fp_decoder_io_sigs_sqrt;
+ assign io_dec_round = fp_decoder_io_sigs_round;
+ assign io_dec_wflags = fp_decoder_io_sigs_wflags;
+ assign io_sboard_set = T_1033;
+ assign io_sboard_clr = T_1040;
+ assign io_sboard_clra = waddr;
+ assign io_cp_req_ready = T_990;
+ assign io_cp_resp_valid = T_987 ? 1'h1 : T_818 ? 1'h1 : 1'h0;
+ assign io_cp_resp_bits_data = T_987 ? wdata : T_818 ? fpiu_io_out_bits_toint : 1'h0;
+ assign io_cp_resp_bits_exc = GEN_9;
+ assign req_valid = ex_reg_valid | io_cp_req_valid;
+ assign T_202 = ex_reg_valid == 1'h0;
+ assign ex_cp_valid = io_cp_req_valid & T_202;
+ assign T_205 = io_killx == 1'h0;
+ assign T_206 = ex_reg_valid & T_205;
+ assign T_207 = T_206 | ex_cp_valid;
+ assign T_213 = io_killm | io_nack_mem;
+ assign T_215 = mem_cp_valid == 1'h0;
+ assign killm = T_213 & T_215;
+ assign T_218 = killm == 1'h0;
+ assign T_219 = T_218 | mem_cp_valid;
+ assign T_220 = mem_reg_valid & T_219;
+ assign fp_decoder_clk = clk;
+ assign fp_decoder_reset = reset;
+ assign fp_decoder_io_inst = io_inst;
+ assign cp_ctrl_cmd = io_cp_req_bits_cmd;
+ assign cp_ctrl_ldst = io_cp_req_bits_ldst;
+ assign cp_ctrl_wen = io_cp_req_bits_wen;
+ assign cp_ctrl_ren1 = io_cp_req_bits_ren1;
+ assign cp_ctrl_ren2 = io_cp_req_bits_ren2;
+ assign cp_ctrl_ren3 = io_cp_req_bits_ren3;
+ assign cp_ctrl_swap12 = io_cp_req_bits_swap12;
+ assign cp_ctrl_swap23 = io_cp_req_bits_swap23;
+ assign cp_ctrl_single = io_cp_req_bits_single;
+ assign cp_ctrl_fromint = io_cp_req_bits_fromint;
+ assign cp_ctrl_toint = io_cp_req_bits_toint;
+ assign cp_ctrl_fastpipe = io_cp_req_bits_fastpipe;
+ assign cp_ctrl_fma = io_cp_req_bits_fma;
+ assign cp_ctrl_div = io_cp_req_bits_div;
+ assign cp_ctrl_sqrt = io_cp_req_bits_sqrt;
+ assign cp_ctrl_round = io_cp_req_bits_round;
+ assign cp_ctrl_wflags = io_cp_req_bits_wflags;
+ assign ex_ctrl_cmd = ex_reg_valid ? T_264_cmd : cp_ctrl_cmd;
+ assign ex_ctrl_ldst = ex_reg_valid ? T_264_ldst : cp_ctrl_ldst;
+ assign ex_ctrl_wen = ex_reg_valid ? T_264_wen : cp_ctrl_wen;
+ assign ex_ctrl_ren1 = ex_reg_valid ? T_264_ren1 : cp_ctrl_ren1;
+ assign ex_ctrl_ren2 = ex_reg_valid ? T_264_ren2 : cp_ctrl_ren2;
+ assign ex_ctrl_ren3 = ex_reg_valid ? T_264_ren3 : cp_ctrl_ren3;
+ assign ex_ctrl_swap12 = ex_reg_valid ? T_264_swap12 : cp_ctrl_swap12;
+ assign ex_ctrl_swap23 = ex_reg_valid ? T_264_swap23 : cp_ctrl_swap23;
+ assign ex_ctrl_single = ex_reg_valid ? T_264_single : cp_ctrl_single;
+ assign ex_ctrl_fromint = ex_reg_valid ? T_264_fromint : cp_ctrl_fromint;
+ assign ex_ctrl_toint = ex_reg_valid ? T_264_toint : cp_ctrl_toint;
+ assign ex_ctrl_fastpipe = ex_reg_valid ? T_264_fastpipe : cp_ctrl_fastpipe;
+ assign ex_ctrl_fma = ex_reg_valid ? T_264_fma : cp_ctrl_fma;
+ assign ex_ctrl_div = ex_reg_valid ? T_264_div : cp_ctrl_div;
+ assign ex_ctrl_sqrt = ex_reg_valid ? T_264_sqrt : cp_ctrl_sqrt;
+ assign ex_ctrl_round = ex_reg_valid ? T_264_round : cp_ctrl_round;
+ assign ex_ctrl_wflags = ex_reg_valid ? T_264_wflags : cp_ctrl_wflags;
+ assign T_337 = io_dmem_resp_type == 3'h2;
+ assign T_338 = io_dmem_resp_type == 3'h6;
+ assign T_339 = T_337 | T_338;
+ assign T_343 = load_wb_data[31];
+ assign T_344 = load_wb_data[30:23];
+ assign T_345 = load_wb_data[22:0];
+ assign T_347 = T_344 == 1'h0;
+ assign T_349 = T_345 == 1'h0;
+ assign T_350 = T_347 & T_349;
+ assign T_351 = T_345 << 9;
+ assign T_352 = T_351[31];
+ assign T_354 = T_351[30];
+ assign T_356 = T_351[29];
+ assign T_358 = T_351[28];
+ assign T_360 = T_351[27];
+ assign T_362 = T_351[26];
+ assign T_364 = T_351[25];
+ assign T_366 = T_351[24];
+ assign T_368 = T_351[23];
+ assign T_370 = T_351[22];
+ assign T_372 = T_351[21];
+ assign T_374 = T_351[20];
+ assign T_376 = T_351[19];
+ assign T_378 = T_351[18];
+ assign T_380 = T_351[17];
+ assign T_382 = T_351[16];
+ assign T_384 = T_351[15];
+ assign T_386 = T_351[14];
+ assign T_388 = T_351[13];
+ assign T_390 = T_351[12];
+ assign T_392 = T_351[11];
+ assign T_394 = T_351[10];
+ assign T_396 = T_351[9];
+ assign T_398 = T_351[8];
+ assign T_400 = T_351[7];
+ assign T_402 = T_351[6];
+ assign T_404 = T_351[5];
+ assign T_406 = T_351[4];
+ assign T_408 = T_351[3];
+ assign T_410 = T_351[2];
+ assign T_412 = T_351[1];
+ assign T_413 = T_412 << 0;
+ assign T_414 = T_410 ? 2'h2 : T_413;
+ assign T_415 = T_408 ? 2'h3 : T_414;
+ assign T_416 = T_406 ? 3'h4 : T_415;
+ assign T_417 = T_404 ? 3'h5 : T_416;
+ assign T_418 = T_402 ? 3'h6 : T_417;
+ assign T_419 = T_400 ? 3'h7 : T_418;
+ assign T_420 = T_398 ? 4'h8 : T_419;
+ assign T_421 = T_396 ? 4'h9 : T_420;
+ assign T_422 = T_394 ? 4'ha : T_421;
+ assign T_423 = T_392 ? 4'hb : T_422;
+ assign T_424 = T_390 ? 4'hc : T_423;
+ assign T_425 = T_388 ? 4'hd : T_424;
+ assign T_426 = T_386 ? 4'he : T_425;
+ assign T_427 = T_384 ? 4'hf : T_426;
+ assign T_428 = T_382 ? 5'h10 : T_427;
+ assign T_429 = T_380 ? 5'h11 : T_428;
+ assign T_430 = T_378 ? 5'h12 : T_429;
+ assign T_431 = T_376 ? 5'h13 : T_430;
+ assign T_432 = T_374 ? 5'h14 : T_431;
+ assign T_433 = T_372 ? 5'h15 : T_432;
+ assign T_434 = T_370 ? 5'h16 : T_433;
+ assign T_435 = T_368 ? 5'h17 : T_434;
+ assign T_436 = T_366 ? 5'h18 : T_435;
+ assign T_437 = T_364 ? 5'h19 : T_436;
+ assign T_438 = T_362 ? 5'h1a : T_437;
+ assign T_439 = T_360 ? 5'h1b : T_438;
+ assign T_440 = T_358 ? 5'h1c : T_439;
+ assign T_441 = T_356 ? 5'h1d : T_440;
+ assign T_442 = T_354 ? 5'h1e : T_441;
+ assign T_443 = T_352 ? 5'h1f : T_442;
+ assign T_444 = ~ T_443;
+ assign T_445 = T_345 << T_444;
+ assign T_446 = T_445[21:0];
+ assign T_448 = {T_446,1'h0};
+ assign T_451 = 9'h0 - 1'h1;
+ assign T_452 = T_451[8:0];
+ assign T_453 = T_444 ^ T_452;
+ assign T_454 = T_347 ? T_453 : T_344;
+ assign T_458 = T_347 ? 2'h2 : 1'h1;
+ assign T_459 = 8'h80 | T_458;
+ assign T_460 = T_454 + T_459;
+ assign T_461 = T_460[8:0];
+ assign T_462 = T_461[8:7];
+ assign T_464 = T_462 == 2'h3;
+ assign T_466 = T_349 == 1'h0;
+ assign T_467 = T_464 & T_466;
+ assign T_469 = 3'h0 - T_350;
+ assign T_470 = T_469[2:0];
+ assign T_471 = T_470 << 6;
+ assign T_472 = ~ T_471;
+ assign T_473 = T_461 & T_472;
+ assign T_474 = T_467 << 6;
+ assign T_475 = T_473 | T_474;
+ assign T_476 = T_347 ? T_448 : T_345;
+ assign T_477 = {T_475,T_476};
+ assign rec_s = {T_343,T_477};
+ assign T_479 = load_wb_data[63];
+ assign T_480 = load_wb_data[62:52];
+ assign T_481 = load_wb_data[51:0];
+ assign T_483 = T_480 == 1'h0;
+ assign T_485 = T_481 == 1'h0;
+ assign T_486 = T_483 & T_485;
+ assign T_487 = T_481 << 12;
+ assign T_488 = T_487[63];
+ assign T_490 = T_487[62];
+ assign T_492 = T_487[61];
+ assign T_494 = T_487[60];
+ assign T_496 = T_487[59];
+ assign T_498 = T_487[58];
+ assign T_500 = T_487[57];
+ assign T_502 = T_487[56];
+ assign T_504 = T_487[55];
+ assign T_506 = T_487[54];
+ assign T_508 = T_487[53];
+ assign T_510 = T_487[52];
+ assign T_512 = T_487[51];
+ assign T_514 = T_487[50];
+ assign T_516 = T_487[49];
+ assign T_518 = T_487[48];
+ assign T_520 = T_487[47];
+ assign T_522 = T_487[46];
+ assign T_524 = T_487[45];
+ assign T_526 = T_487[44];
+ assign T_528 = T_487[43];
+ assign T_530 = T_487[42];
+ assign T_532 = T_487[41];
+ assign T_534 = T_487[40];
+ assign T_536 = T_487[39];
+ assign T_538 = T_487[38];
+ assign T_540 = T_487[37];
+ assign T_542 = T_487[36];
+ assign T_544 = T_487[35];
+ assign T_546 = T_487[34];
+ assign T_548 = T_487[33];
+ assign T_550 = T_487[32];
+ assign T_552 = T_487[31];
+ assign T_554 = T_487[30];
+ assign T_556 = T_487[29];
+ assign T_558 = T_487[28];
+ assign T_560 = T_487[27];
+ assign T_562 = T_487[26];
+ assign T_564 = T_487[25];
+ assign T_566 = T_487[24];
+ assign T_568 = T_487[23];
+ assign T_570 = T_487[22];
+ assign T_572 = T_487[21];
+ assign T_574 = T_487[20];
+ assign T_576 = T_487[19];
+ assign T_578 = T_487[18];
+ assign T_580 = T_487[17];
+ assign T_582 = T_487[16];
+ assign T_584 = T_487[15];
+ assign T_586 = T_487[14];
+ assign T_588 = T_487[13];
+ assign T_590 = T_487[12];
+ assign T_592 = T_487[11];
+ assign T_594 = T_487[10];
+ assign T_596 = T_487[9];
+ assign T_598 = T_487[8];
+ assign T_600 = T_487[7];
+ assign T_602 = T_487[6];
+ assign T_604 = T_487[5];
+ assign T_606 = T_487[4];
+ assign T_608 = T_487[3];
+ assign T_610 = T_487[2];
+ assign T_612 = T_487[1];
+ assign T_613 = T_612 << 0;
+ assign T_614 = T_610 ? 2'h2 : T_613;
+ assign T_615 = T_608 ? 2'h3 : T_614;
+ assign T_616 = T_606 ? 3'h4 : T_615;
+ assign T_617 = T_604 ? 3'h5 : T_616;
+ assign T_618 = T_602 ? 3'h6 : T_617;
+ assign T_619 = T_600 ? 3'h7 : T_618;
+ assign T_620 = T_598 ? 4'h8 : T_619;
+ assign T_621 = T_596 ? 4'h9 : T_620;
+ assign T_622 = T_594 ? 4'ha : T_621;
+ assign T_623 = T_592 ? 4'hb : T_622;
+ assign T_624 = T_590 ? 4'hc : T_623;
+ assign T_625 = T_588 ? 4'hd : T_624;
+ assign T_626 = T_586 ? 4'he : T_625;
+ assign T_627 = T_584 ? 4'hf : T_626;
+ assign T_628 = T_582 ? 5'h10 : T_627;
+ assign T_629 = T_580 ? 5'h11 : T_628;
+ assign T_630 = T_578 ? 5'h12 : T_629;
+ assign T_631 = T_576 ? 5'h13 : T_630;
+ assign T_632 = T_574 ? 5'h14 : T_631;
+ assign T_633 = T_572 ? 5'h15 : T_632;
+ assign T_634 = T_570 ? 5'h16 : T_633;
+ assign T_635 = T_568 ? 5'h17 : T_634;
+ assign T_636 = T_566 ? 5'h18 : T_635;
+ assign T_637 = T_564 ? 5'h19 : T_636;
+ assign T_638 = T_562 ? 5'h1a : T_637;
+ assign T_639 = T_560 ? 5'h1b : T_638;
+ assign T_640 = T_558 ? 5'h1c : T_639;
+ assign T_641 = T_556 ? 5'h1d : T_640;
+ assign T_642 = T_554 ? 5'h1e : T_641;
+ assign T_643 = T_552 ? 5'h1f : T_642;
+ assign T_644 = T_550 ? 6'h20 : T_643;
+ assign T_645 = T_548 ? 6'h21 : T_644;
+ assign T_646 = T_546 ? 6'h22 : T_645;
+ assign T_647 = T_544 ? 6'h23 : T_646;
+ assign T_648 = T_542 ? 6'h24 : T_647;
+ assign T_649 = T_540 ? 6'h25 : T_648;
+ assign T_650 = T_538 ? 6'h26 : T_649;
+ assign T_651 = T_536 ? 6'h27 : T_650;
+ assign T_652 = T_534 ? 6'h28 : T_651;
+ assign T_653 = T_532 ? 6'h29 : T_652;
+ assign T_654 = T_530 ? 6'h2a : T_653;
+ assign T_655 = T_528 ? 6'h2b : T_654;
+ assign T_656 = T_526 ? 6'h2c : T_655;
+ assign T_657 = T_524 ? 6'h2d : T_656;
+ assign T_658 = T_522 ? 6'h2e : T_657;
+ assign T_659 = T_520 ? 6'h2f : T_658;
+ assign T_660 = T_518 ? 6'h30 : T_659;
+ assign T_661 = T_516 ? 6'h31 : T_660;
+ assign T_662 = T_514 ? 6'h32 : T_661;
+ assign T_663 = T_512 ? 6'h33 : T_662;
+ assign T_664 = T_510 ? 6'h34 : T_663;
+ assign T_665 = T_508 ? 6'h35 : T_664;
+ assign T_666 = T_506 ? 6'h36 : T_665;
+ assign T_667 = T_504 ? 6'h37 : T_666;
+ assign T_668 = T_502 ? 6'h38 : T_667;
+ assign T_669 = T_500 ? 6'h39 : T_668;
+ assign T_670 = T_498 ? 6'h3a : T_669;
+ assign T_671 = T_496 ? 6'h3b : T_670;
+ assign T_672 = T_494 ? 6'h3c : T_671;
+ assign T_673 = T_492 ? 6'h3d : T_672;
+ assign T_674 = T_490 ? 6'h3e : T_673;
+ assign T_675 = T_488 ? 6'h3f : T_674;
+ assign T_676 = ~ T_675;
+ assign T_677 = T_481 << T_676;
+ assign T_678 = T_677[50:0];
+ assign T_680 = {T_678,1'h0};
+ assign T_683 = 12'h0 - 1'h1;
+ assign T_684 = T_683[11:0];
+ assign T_685 = T_676 ^ T_684;
+ assign T_686 = T_483 ? T_685 : T_480;
+ assign T_690 = T_483 ? 2'h2 : 1'h1;
+ assign T_691 = 11'h400 | T_690;
+ assign T_692 = T_686 + T_691;
+ assign T_693 = T_692[11:0];
+ assign T_694 = T_693[11:10];
+ assign T_696 = T_694 == 2'h3;
+ assign T_698 = T_485 == 1'h0;
+ assign T_699 = T_696 & T_698;
+ assign T_701 = 3'h0 - T_486;
+ assign T_702 = T_701[2:0];
+ assign T_703 = T_702 << 9;
+ assign T_704 = ~ T_703;
+ assign T_705 = T_693 & T_704;
+ assign T_706 = T_699 << 9;
+ assign T_707 = T_705 | T_706;
+ assign T_708 = T_483 ? T_680 : T_481;
+ assign T_709 = {T_707,T_708};
+ assign rec_d = {T_479,T_709};
+ assign GEN_2 = $signed(32'hffffffff);
+ assign T_712 = $unsigned(GEN_2);
+ assign T_713 = {T_712,rec_s};
+ assign load_wb_data_recoded = load_wb_single ? T_713 : rec_d;
+ assign regfile_ex_rs1_addr = ex_ra1;
+ assign regfile_ex_rs1_en = 1'h1;
+ assign regfile_ex_rs1_clk = clk;
+ assign regfile_ex_rs1_data = regfile[regfile_ex_rs1_addr];
+ assign regfile_ex_rs2_addr = ex_ra2;
+ assign regfile_ex_rs2_en = 1'h1;
+ assign regfile_ex_rs2_clk = clk;
+ assign regfile_ex_rs2_data = regfile[regfile_ex_rs2_addr];
+ assign regfile_ex_rs3_addr = ex_ra3;
+ assign regfile_ex_rs3_en = 1'h1;
+ assign regfile_ex_rs3_clk = clk;
+ assign regfile_ex_rs3_data = regfile[regfile_ex_rs3_addr];
+ assign regfile_T_718_data = load_wb_data_recoded;
+ assign regfile_T_718_addr = load_wb_tag;
+ assign regfile_T_718_mask = load_wb ? 1'h1 : 1'h0;
+ assign regfile_T_718_en = load_wb ? 1'h1 : 1'h0;
+ assign regfile_T_718_clk = clk;
+ assign regfile_T_985_data = wdata;
+ assign regfile_T_985_addr = waddr;
+ assign regfile_T_985_mask = T_984 ? 1'h1 : 1'h0;
+ assign regfile_T_985_en = T_984 ? 1'h1 : 1'h0;
+ assign regfile_T_985_clk = clk;
+ assign T_726 = fp_decoder_io_sigs_swap12 == 1'h0;
+ assign T_727 = io_inst[19:15];
+ assign T_728 = io_inst[19:15];
+ assign T_729 = io_inst[24:20];
+ assign T_730 = io_inst[24:20];
+ assign T_732 = fp_decoder_io_sigs_swap12 == 1'h0;
+ assign T_734 = fp_decoder_io_sigs_swap23 == 1'h0;
+ assign T_735 = T_732 & T_734;
+ assign T_736 = io_inst[24:20];
+ assign T_737 = io_inst[31:27];
+ assign T_741 = ex_reg_inst[14:12];
+ assign T_743 = T_741 == 3'h7;
+ assign T_744 = ex_reg_inst[14:12];
+ assign ex_rm = T_743 ? io_fcsr_rm : T_744;
+ assign cp_rs2 = io_cp_req_bits_swap23 ? io_cp_req_bits_in3 : io_cp_req_bits_in2;
+ assign cp_rs3 = io_cp_req_bits_swap23 ? io_cp_req_bits_in2 : io_cp_req_bits_in3;
+ assign req_cmd = ex_ctrl_cmd;
+ assign req_ldst = ex_ctrl_ldst;
+ assign req_wen = ex_ctrl_wen;
+ assign req_ren1 = ex_ctrl_ren1;
+ assign req_ren2 = ex_ctrl_ren2;
+ assign req_ren3 = ex_ctrl_ren3;
+ assign req_swap12 = ex_ctrl_swap12;
+ assign req_swap23 = ex_ctrl_swap23;
+ assign req_single = ex_ctrl_single;
+ assign req_fromint = ex_ctrl_fromint;
+ assign req_toint = ex_ctrl_toint;
+ assign req_fastpipe = ex_ctrl_fastpipe;
+ assign req_fma = ex_ctrl_fma;
+ assign req_div = ex_ctrl_div;
+ assign req_sqrt = ex_ctrl_sqrt;
+ assign req_round = ex_ctrl_round;
+ assign req_wflags = ex_ctrl_wflags;
+ assign req_rm = T_794;
+ assign req_typ = T_799;
+ assign req_in1 = T_795;
+ assign req_in2 = T_796;
+ assign req_in3 = T_797;
+ assign T_794 = ex_reg_valid ? ex_rm : io_cp_req_bits_rm;
+ assign T_795 = ex_reg_valid ? regfile_ex_rs1_data : io_cp_req_bits_in1;
+ assign T_796 = ex_reg_valid ? regfile_ex_rs2_data : cp_rs2;
+ assign T_797 = ex_reg_valid ? regfile_ex_rs3_data : cp_rs3;
+ assign T_798 = ex_reg_inst[21:20];
+ assign T_799 = ex_reg_valid ? T_798 : io_cp_req_bits_typ;
+ assign sfma_clk = clk;
+ assign sfma_reset = reset;
+ assign sfma_io_in_valid = T_802;
+ assign sfma_io_in_bits_cmd = req_cmd;
+ assign sfma_io_in_bits_ldst = req_ldst;
+ assign sfma_io_in_bits_wen = req_wen;
+ assign sfma_io_in_bits_ren1 = req_ren1;
+ assign sfma_io_in_bits_ren2 = req_ren2;
+ assign sfma_io_in_bits_ren3 = req_ren3;
+ assign sfma_io_in_bits_swap12 = req_swap12;
+ assign sfma_io_in_bits_swap23 = req_swap23;
+ assign sfma_io_in_bits_single = req_single;
+ assign sfma_io_in_bits_fromint = req_fromint;
+ assign sfma_io_in_bits_toint = req_toint;
+ assign sfma_io_in_bits_fastpipe = req_fastpipe;
+ assign sfma_io_in_bits_fma = req_fma;
+ assign sfma_io_in_bits_div = req_div;
+ assign sfma_io_in_bits_sqrt = req_sqrt;
+ assign sfma_io_in_bits_round = req_round;
+ assign sfma_io_in_bits_wflags = req_wflags;
+ assign sfma_io_in_bits_rm = req_rm;
+ assign sfma_io_in_bits_typ = req_typ;
+ assign sfma_io_in_bits_in1 = req_in1;
+ assign sfma_io_in_bits_in2 = req_in2;
+ assign sfma_io_in_bits_in3 = req_in3;
+ assign T_801 = req_valid & ex_ctrl_fma;
+ assign T_802 = T_801 & ex_ctrl_single;
+ assign dfma_clk = clk;
+ assign dfma_reset = reset;
+ assign dfma_io_in_valid = T_807;
+ assign dfma_io_in_bits_cmd = req_cmd;
+ assign dfma_io_in_bits_ldst = req_ldst;
+ assign dfma_io_in_bits_wen = req_wen;
+ assign dfma_io_in_bits_ren1 = req_ren1;
+ assign dfma_io_in_bits_ren2 = req_ren2;
+ assign dfma_io_in_bits_ren3 = req_ren3;
+ assign dfma_io_in_bits_swap12 = req_swap12;
+ assign dfma_io_in_bits_swap23 = req_swap23;
+ assign dfma_io_in_bits_single = req_single;
+ assign dfma_io_in_bits_fromint = req_fromint;
+ assign dfma_io_in_bits_toint = req_toint;
+ assign dfma_io_in_bits_fastpipe = req_fastpipe;
+ assign dfma_io_in_bits_fma = req_fma;
+ assign dfma_io_in_bits_div = req_div;
+ assign dfma_io_in_bits_sqrt = req_sqrt;
+ assign dfma_io_in_bits_round = req_round;
+ assign dfma_io_in_bits_wflags = req_wflags;
+ assign dfma_io_in_bits_rm = req_rm;
+ assign dfma_io_in_bits_typ = req_typ;
+ assign dfma_io_in_bits_in1 = req_in1;
+ assign dfma_io_in_bits_in2 = req_in2;
+ assign dfma_io_in_bits_in3 = req_in3;
+ assign T_804 = req_valid & ex_ctrl_fma;
+ assign T_806 = ex_ctrl_single == 1'h0;
+ assign T_807 = T_804 & T_806;
+ assign fpiu_clk = clk;
+ assign fpiu_reset = reset;
+ assign fpiu_io_in_valid = T_816;
+ assign fpiu_io_in_bits_cmd = req_cmd;
+ assign fpiu_io_in_bits_ldst = req_ldst;
+ assign fpiu_io_in_bits_wen = req_wen;
+ assign fpiu_io_in_bits_ren1 = req_ren1;
+ assign fpiu_io_in_bits_ren2 = req_ren2;
+ assign fpiu_io_in_bits_ren3 = req_ren3;
+ assign fpiu_io_in_bits_swap12 = req_swap12;
+ assign fpiu_io_in_bits_swap23 = req_swap23;
+ assign fpiu_io_in_bits_single = req_single;
+ assign fpiu_io_in_bits_fromint = req_fromint;
+ assign fpiu_io_in_bits_toint = req_toint;
+ assign fpiu_io_in_bits_fastpipe = req_fastpipe;
+ assign fpiu_io_in_bits_fma = req_fma;
+ assign fpiu_io_in_bits_div = req_div;
+ assign fpiu_io_in_bits_sqrt = req_sqrt;
+ assign fpiu_io_in_bits_round = req_round;
+ assign fpiu_io_in_bits_wflags = req_wflags;
+ assign fpiu_io_in_bits_rm = req_rm;
+ assign fpiu_io_in_bits_typ = req_typ;
+ assign fpiu_io_in_bits_in1 = req_in1;
+ assign fpiu_io_in_bits_in2 = req_in2;
+ assign fpiu_io_in_bits_in3 = req_in3;
+ assign T_809 = ex_ctrl_toint | ex_ctrl_div;
+ assign T_810 = T_809 | ex_ctrl_sqrt;
+ assign T_813 = ex_ctrl_cmd & 4'hd;
+ assign T_814 = 3'h5 == T_813;
+ assign T_815 = T_810 | T_814;
+ assign T_816 = req_valid & T_815;
+ assign T_817 = fpiu_io_out_valid & mem_cp_valid;
+ assign T_818 = T_817 & mem_ctrl_toint;
+ assign ifpu_clk = clk;
+ assign ifpu_reset = reset;
+ assign ifpu_io_in_valid = T_821;
+ assign ifpu_io_in_bits_cmd = req_cmd;
+ assign ifpu_io_in_bits_ldst = req_ldst;
+ assign ifpu_io_in_bits_wen = req_wen;
+ assign ifpu_io_in_bits_ren1 = req_ren1;
+ assign ifpu_io_in_bits_ren2 = req_ren2;
+ assign ifpu_io_in_bits_ren3 = req_ren3;
+ assign ifpu_io_in_bits_swap12 = req_swap12;
+ assign ifpu_io_in_bits_swap23 = req_swap23;
+ assign ifpu_io_in_bits_single = req_single;
+ assign ifpu_io_in_bits_fromint = req_fromint;
+ assign ifpu_io_in_bits_toint = req_toint;
+ assign ifpu_io_in_bits_fastpipe = req_fastpipe;
+ assign ifpu_io_in_bits_fma = req_fma;
+ assign ifpu_io_in_bits_div = req_div;
+ assign ifpu_io_in_bits_sqrt = req_sqrt;
+ assign ifpu_io_in_bits_round = req_round;
+ assign ifpu_io_in_bits_wflags = req_wflags;
+ assign ifpu_io_in_bits_rm = req_rm;
+ assign ifpu_io_in_bits_typ = req_typ;
+ assign ifpu_io_in_bits_in1 = T_822;
+ assign ifpu_io_in_bits_in2 = req_in2;
+ assign ifpu_io_in_bits_in3 = req_in3;
+ assign T_821 = req_valid & ex_ctrl_fromint;
+ assign T_822 = ex_reg_valid ? io_fromint_data : io_cp_req_bits_in1;
+ assign fpmu_clk = clk;
+ assign fpmu_reset = reset;
+ assign fpmu_io_in_valid = T_824;
+ assign fpmu_io_in_bits_cmd = req_cmd;
+ assign fpmu_io_in_bits_ldst = req_ldst;
+ assign fpmu_io_in_bits_wen = req_wen;
+ assign fpmu_io_in_bits_ren1 = req_ren1;
+ assign fpmu_io_in_bits_ren2 = req_ren2;
+ assign fpmu_io_in_bits_ren3 = req_ren3;
+ assign fpmu_io_in_bits_swap12 = req_swap12;
+ assign fpmu_io_in_bits_swap23 = req_swap23;
+ assign fpmu_io_in_bits_single = req_single;
+ assign fpmu_io_in_bits_fromint = req_fromint;
+ assign fpmu_io_in_bits_toint = req_toint;
+ assign fpmu_io_in_bits_fastpipe = req_fastpipe;
+ assign fpmu_io_in_bits_fma = req_fma;
+ assign fpmu_io_in_bits_div = req_div;
+ assign fpmu_io_in_bits_sqrt = req_sqrt;
+ assign fpmu_io_in_bits_round = req_round;
+ assign fpmu_io_in_bits_wflags = req_wflags;
+ assign fpmu_io_in_bits_rm = req_rm;
+ assign fpmu_io_in_bits_typ = req_typ;
+ assign fpmu_io_in_bits_in1 = req_in1;
+ assign fpmu_io_in_bits_in2 = req_in2;
+ assign fpmu_io_in_bits_in3 = req_in3;
+ assign fpmu_io_lt = fpiu_io_out_bits_lt;
+ assign T_824 = req_valid & ex_ctrl_fastpipe;
+ assign divSqrt_inReady = T_1054;
+ assign divSqrt_wdata = T_1068;
+ assign divSqrt_flags = T_1071;
+ assign T_841 = mem_ctrl_fastpipe ? 1'h1 : 1'h0;
+ assign T_844 = mem_ctrl_fromint ? 2'h2 : 1'h0;
+ assign T_845 = mem_ctrl_fma & mem_ctrl_single;
+ assign T_848 = T_845 ? 1'h1 : 1'h0;
+ assign T_850 = mem_ctrl_single == 1'h0;
+ assign T_851 = mem_ctrl_fma & T_850;
+ assign T_854 = T_851 ? 2'h2 : 1'h0;
+ assign T_855 = T_841 | T_844;
+ assign T_856 = T_855 | T_848;
+ assign memLatencyMask = T_856 | T_854;
+ assign T_872 = mem_ctrl_fma | mem_ctrl_fastpipe;
+ assign T_873 = T_872 | mem_ctrl_fromint;
+ assign mem_wen = mem_reg_valid & T_873;
+ assign T_877 = ex_ctrl_fastpipe ? 2'h2 : 1'h0;
+ assign T_880 = ex_ctrl_fromint ? 3'h4 : 1'h0;
+ assign T_881 = ex_ctrl_fma & ex_ctrl_single;
+ assign T_884 = T_881 ? 2'h2 : 1'h0;
+ assign T_886 = ex_ctrl_single == 1'h0;
+ assign T_887 = ex_ctrl_fma & T_886;
+ assign T_890 = T_887 ? 3'h4 : 1'h0;
+ assign T_891 = T_877 | T_880;
+ assign T_892 = T_891 | T_884;
+ assign T_893 = T_892 | T_890;
+ assign T_894 = memLatencyMask & T_893;
+ assign T_896 = T_894 != 1'h0;
+ assign T_897 = mem_wen & T_896;
+ assign T_900 = ex_ctrl_fastpipe ? 3'h4 : 1'h0;
+ assign T_903 = ex_ctrl_fromint ? 4'h8 : 1'h0;
+ assign T_904 = ex_ctrl_fma & ex_ctrl_single;
+ assign T_907 = T_904 ? 3'h4 : 1'h0;
+ assign T_909 = ex_ctrl_single == 1'h0;
+ assign T_910 = ex_ctrl_fma & T_909;
+ assign T_913 = T_910 ? 4'h8 : 1'h0;
+ assign T_914 = T_900 | T_903;
+ assign T_915 = T_914 | T_907;
+ assign T_916 = T_915 | T_913;
+ assign T_917 = wen & T_916;
+ assign T_919 = T_917 != 1'h0;
+ assign T_920 = T_897 | T_919;
+ assign T_924 = mem_ctrl_fastpipe ? 1'h0 : 1'h0;
+ assign T_927 = mem_ctrl_fromint ? 1'h1 : 1'h0;
+ assign T_928 = mem_ctrl_fma & mem_ctrl_single;
+ assign T_931 = T_928 ? 2'h2 : 1'h0;
+ assign T_933 = mem_ctrl_single == 1'h0;
+ assign T_934 = mem_ctrl_fma & T_933;
+ assign T_937 = T_934 ? 2'h3 : 1'h0;
+ assign T_938 = T_924 | T_927;
+ assign T_939 = T_938 | T_931;
+ assign T_940 = T_939 | T_937;
+ assign T_941 = mem_reg_inst[11:7];
+ assign T_942 = {mem_cp_valid,T_940};
+ assign T_943 = {mem_ctrl_single,T_941};
+ assign mem_winfo = {T_942,T_943};
+ assign T_945 = wen[1];
+ assign T_946 = wen[1:1];
+ assign T_948 = killm == 1'h0;
+ assign T_949 = wen[1:1];
+ assign T_950 = T_949 | memLatencyMask;
+ assign T_952 = write_port_busy == 1'h0;
+ assign T_953 = memLatencyMask[0];
+ assign T_954 = T_952 & T_953;
+ assign T_956 = write_port_busy == 1'h0;
+ assign T_957 = memLatencyMask[1];
+ assign T_958 = T_956 & T_957;
+ assign T_959 = winfo_0[4:0];
+ assign waddr = divSqrt_wen ? divSqrt_waddr : T_959;
+ assign wsrc = winfo_0[8:6];
+ assign wcp = winfo_0[8];
+ assign T_964_0 = fpmu_io_out_bits_data;
+ assign T_964_1 = ifpu_io_out_bits_data;
+ assign T_964_2 = sfma_io_out_bits_data;
+ assign T_964_3 = dfma_io_out_bits_data;
+ assign GEN_0 = GEN_3 ? T_964_3 : GEN_4 ? T_964_2 : GEN_5 ? T_964_1 : T_964_0;
+ assign wdata = divSqrt_wen ? divSqrt_wdata : GEN_0;
+ assign T_973_0 = fpmu_io_out_bits_exc;
+ assign T_973_1 = ifpu_io_out_bits_exc;
+ assign T_973_2 = sfma_io_out_bits_exc;
+ assign T_973_3 = dfma_io_out_bits_exc;
+ assign T_981 = wcp == 1'h0;
+ assign T_982 = wen[0];
+ assign T_983 = T_981 & T_982;
+ assign T_984 = T_983 | divSqrt_wen;
+ assign T_986 = wen[0];
+ assign T_987 = wcp & T_986;
+ assign T_990 = ex_reg_valid == 1'h0;
+ assign wb_toint_valid = wb_reg_valid & wb_ctrl_toint;
+ assign T_993 = wb_toint_valid | divSqrt_wen;
+ assign T_994 = wen[0];
+ assign T_995 = T_993 | T_994;
+ assign T_997 = wb_toint_valid ? wb_toint_exc : 1'h0;
+ assign T_999 = divSqrt_wen ? divSqrt_flags : 1'h0;
+ assign T_1000 = T_997 | T_999;
+ assign T_1001 = wen[0];
+ assign GEN_1 = GEN_6 ? T_973_3 : GEN_7 ? T_973_2 : GEN_8 ? T_973_1 : T_973_0;
+ assign T_1003 = T_1001 ? GEN_1 : 1'h0;
+ assign T_1004 = T_1000 | T_1003;
+ assign T_1005 = mem_ctrl_div | mem_ctrl_sqrt;
+ assign T_1006 = mem_reg_valid & T_1005;
+ assign T_1008 = divSqrt_inReady == 1'h0;
+ assign T_1010 = wen != 1'h0;
+ assign T_1011 = T_1008 | T_1010;
+ assign units_busy = T_1006 & T_1011;
+ assign T_1013 = ex_reg_valid & ex_ctrl_wflags;
+ assign T_1014 = mem_reg_valid & mem_ctrl_wflags;
+ assign T_1015 = T_1013 | T_1014;
+ assign T_1016 = wb_reg_valid & wb_ctrl_toint;
+ assign T_1017 = T_1015 | T_1016;
+ assign T_1019 = wen != 1'h0;
+ assign T_1020 = T_1017 | T_1019;
+ assign T_1021 = T_1020 | divSqrt_in_flight;
+ assign T_1023 = T_1021 == 1'h0;
+ assign T_1024 = units_busy | write_port_busy;
+ assign T_1025 = T_1024 | divSqrt_in_flight;
+ assign T_1027 = wb_cp_valid == 1'h0;
+ assign T_1028 = wb_reg_valid & T_1027;
+ assign T_1030 = 1'h0 | mem_ctrl_div;
+ assign T_1031 = T_1030 | mem_ctrl_sqrt;
+ assign T_1033 = T_1028 & T_1032;
+ assign T_1035 = wb_cp_valid == 1'h0;
+ assign T_1036 = wen[0];
+ assign T_1038 = T_1036 & 1'h0;
+ assign T_1039 = divSqrt_wen | T_1038;
+ assign T_1040 = T_1035 & T_1039;
+ assign T_1041 = ex_rm[2];
+ assign T_1042 = T_1041 & ex_ctrl_round;
+ assign T_1053_clk = clk;
+ assign T_1053_reset = reset;
+ assign T_1053_io_inValid = T_1060;
+ assign T_1053_io_sqrtOp = mem_ctrl_sqrt;
+ assign T_1053_io_a = fpiu_io_as_double_in1;
+ assign T_1053_io_b = fpiu_io_as_double_in2;
+ assign T_1053_io_roundingMode = fpiu_io_as_double_rm;
+ assign T_1054 = T_1053_io_sqrtOp ? T_1053_io_inReady_sqrt : T_1053_io_inReady_div;
+ assign T_1055 = T_1053_io_outValid_div | T_1053_io_outValid_sqrt;
+ assign T_1056 = mem_ctrl_div | mem_ctrl_sqrt;
+ assign T_1057 = mem_reg_valid & T_1056;
+ assign T_1059 = divSqrt_in_flight == 1'h0;
+ assign T_1060 = T_1057 & T_1059;
+ assign T_1061 = T_1053_io_inValid & divSqrt_inReady;
+ assign T_1063 = mem_reg_inst[11:7];
+ assign T_1065 = divSqrt_killed == 1'h0;
+ assign T_1067_clk = clk;
+ assign T_1067_reset = reset;
+ assign T_1067_io_in = T_1052;
+ assign T_1067_io_roundingMode = ex_rm;
+ assign T_1068 = T_1046 ? T_1067_io_out : T_1052;
+ assign T_1070 = T_1046 ? T_1067_io_exceptionFlags : 1'h0;
+ assign T_1071 = T_1050 | T_1070;
+ assign GEN_3 = 2'h3 == wsrc;
+ assign GEN_4 = 2'h2 == wsrc;
+ assign GEN_5 = 1'h1 == wsrc;
+ assign GEN_6 = 2'h3 == wsrc;
+ assign GEN_7 = 2'h2 == wsrc;
+ assign GEN_8 = 1'h1 == wsrc;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ ex_reg_valid = {1{$random}};
+ ex_reg_inst = {1{$random}};
+ mem_reg_valid = {1{$random}};
+ mem_reg_inst = {1{$random}};
+ mem_cp_valid = {1{$random}};
+ wb_reg_valid = {1{$random}};
+ wb_cp_valid = {1{$random}};
+ T_264_cmd = {1{$random}};
+ T_264_ldst = {1{$random}};
+ T_264_wen = {1{$random}};
+ T_264_ren1 = {1{$random}};
+ T_264_ren2 = {1{$random}};
+ T_264_ren3 = {1{$random}};
+ T_264_swap12 = {1{$random}};
+ T_264_swap23 = {1{$random}};
+ T_264_single = {1{$random}};
+ T_264_fromint = {1{$random}};
+ T_264_toint = {1{$random}};
+ T_264_fastpipe = {1{$random}};
+ T_264_fma = {1{$random}};
+ T_264_div = {1{$random}};
+ T_264_sqrt = {1{$random}};
+ T_264_round = {1{$random}};
+ T_264_wflags = {1{$random}};
+ mem_ctrl_cmd = {1{$random}};
+ mem_ctrl_ldst = {1{$random}};
+ mem_ctrl_wen = {1{$random}};
+ mem_ctrl_ren1 = {1{$random}};
+ mem_ctrl_ren2 = {1{$random}};
+ mem_ctrl_ren3 = {1{$random}};
+ mem_ctrl_swap12 = {1{$random}};
+ mem_ctrl_swap23 = {1{$random}};
+ mem_ctrl_single = {1{$random}};
+ mem_ctrl_fromint = {1{$random}};
+ mem_ctrl_toint = {1{$random}};
+ mem_ctrl_fastpipe = {1{$random}};
+ mem_ctrl_fma = {1{$random}};
+ mem_ctrl_div = {1{$random}};
+ mem_ctrl_sqrt = {1{$random}};
+ mem_ctrl_round = {1{$random}};
+ mem_ctrl_wflags = {1{$random}};
+ wb_ctrl_cmd = {1{$random}};
+ wb_ctrl_ldst = {1{$random}};
+ wb_ctrl_wen = {1{$random}};
+ wb_ctrl_ren1 = {1{$random}};
+ wb_ctrl_ren2 = {1{$random}};
+ wb_ctrl_ren3 = {1{$random}};
+ wb_ctrl_swap12 = {1{$random}};
+ wb_ctrl_swap23 = {1{$random}};
+ wb_ctrl_single = {1{$random}};
+ wb_ctrl_fromint = {1{$random}};
+ wb_ctrl_toint = {1{$random}};
+ wb_ctrl_fastpipe = {1{$random}};
+ wb_ctrl_fma = {1{$random}};
+ wb_ctrl_div = {1{$random}};
+ wb_ctrl_sqrt = {1{$random}};
+ wb_ctrl_round = {1{$random}};
+ wb_ctrl_wflags = {1{$random}};
+ load_wb = {1{$random}};
+ load_wb_single = {1{$random}};
+ load_wb_data = {2{$random}};
+ load_wb_tag = {1{$random}};
+ for (initvar = 0; initvar < 32; initvar = initvar+1)
+ regfile[initvar] = {3{$random}};
+ ex_ra1 = {1{$random}};
+ ex_ra2 = {1{$random}};
+ ex_ra3 = {1{$random}};
+ divSqrt_wen = {1{$random}};
+ divSqrt_waddr = {1{$random}};
+ divSqrt_in_flight = {1{$random}};
+ divSqrt_killed = {1{$random}};
+ wen = {1{$random}};
+ winfo_0 = {1{$random}};
+ winfo_1 = {1{$random}};
+ write_port_busy = {1{$random}};
+ wb_toint_exc = {1{$random}};
+ T_1032 = {1{$random}};
+ T_1046 = {1{$random}};
+ T_1048 = {1{$random}};
+ T_1050 = {1{$random}};
+ T_1052 = {3{$random}};
+ GEN_9 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(reset) begin
+ ex_reg_valid <= 1'h0;
+ end else begin
+ ex_reg_valid <= io_valid;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_valid) begin
+ ex_reg_inst <= io_inst;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ mem_reg_valid <= 1'h0;
+ end else begin
+ mem_reg_valid <= T_207;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(ex_reg_valid) begin
+ mem_reg_inst <= ex_reg_inst;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ mem_cp_valid <= 1'h0;
+ end else begin
+ mem_cp_valid <= ex_cp_valid;
+ end
+ if(reset) begin
+ wb_reg_valid <= 1'h0;
+ end else begin
+ wb_reg_valid <= T_220;
+ end
+ if(reset) begin
+ wb_cp_valid <= 1'h0;
+ end else begin
+ wb_cp_valid <= mem_cp_valid;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_valid) begin
+ T_264_cmd <= fp_decoder_io_sigs_cmd;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_valid) begin
+ T_264_ldst <= fp_decoder_io_sigs_ldst;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_valid) begin
+ T_264_wen <= fp_decoder_io_sigs_wen;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_valid) begin
+ T_264_ren1 <= fp_decoder_io_sigs_ren1;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_valid) begin
+ T_264_ren2 <= fp_decoder_io_sigs_ren2;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_valid) begin
+ T_264_ren3 <= fp_decoder_io_sigs_ren3;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_valid) begin
+ T_264_swap12 <= fp_decoder_io_sigs_swap12;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_valid) begin
+ T_264_swap23 <= fp_decoder_io_sigs_swap23;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_valid) begin
+ T_264_single <= fp_decoder_io_sigs_single;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_valid) begin
+ T_264_fromint <= fp_decoder_io_sigs_fromint;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_valid) begin
+ T_264_toint <= fp_decoder_io_sigs_toint;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_valid) begin
+ T_264_fastpipe <= fp_decoder_io_sigs_fastpipe;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_valid) begin
+ T_264_fma <= fp_decoder_io_sigs_fma;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_valid) begin
+ T_264_div <= fp_decoder_io_sigs_div;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_valid) begin
+ T_264_sqrt <= fp_decoder_io_sigs_sqrt;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_valid) begin
+ T_264_round <= fp_decoder_io_sigs_round;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_valid) begin
+ T_264_wflags <= fp_decoder_io_sigs_wflags;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(req_valid) begin
+ mem_ctrl_cmd <= ex_ctrl_cmd;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(req_valid) begin
+ mem_ctrl_ldst <= ex_ctrl_ldst;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(req_valid) begin
+ mem_ctrl_wen <= ex_ctrl_wen;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(req_valid) begin
+ mem_ctrl_ren1 <= ex_ctrl_ren1;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(req_valid) begin
+ mem_ctrl_ren2 <= ex_ctrl_ren2;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(req_valid) begin
+ mem_ctrl_ren3 <= ex_ctrl_ren3;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(req_valid) begin
+ mem_ctrl_swap12 <= ex_ctrl_swap12;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(req_valid) begin
+ mem_ctrl_swap23 <= ex_ctrl_swap23;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(req_valid) begin
+ mem_ctrl_single <= ex_ctrl_single;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(req_valid) begin
+ mem_ctrl_fromint <= ex_ctrl_fromint;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(req_valid) begin
+ mem_ctrl_toint <= ex_ctrl_toint;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(req_valid) begin
+ mem_ctrl_fastpipe <= ex_ctrl_fastpipe;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(req_valid) begin
+ mem_ctrl_fma <= ex_ctrl_fma;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(req_valid) begin
+ mem_ctrl_div <= ex_ctrl_div;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(req_valid) begin
+ mem_ctrl_sqrt <= ex_ctrl_sqrt;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(req_valid) begin
+ mem_ctrl_round <= ex_ctrl_round;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(req_valid) begin
+ mem_ctrl_wflags <= ex_ctrl_wflags;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(mem_reg_valid) begin
+ wb_ctrl_cmd <= mem_ctrl_cmd;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(mem_reg_valid) begin
+ wb_ctrl_ldst <= mem_ctrl_ldst;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(mem_reg_valid) begin
+ wb_ctrl_wen <= mem_ctrl_wen;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(mem_reg_valid) begin
+ wb_ctrl_ren1 <= mem_ctrl_ren1;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(mem_reg_valid) begin
+ wb_ctrl_ren2 <= mem_ctrl_ren2;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(mem_reg_valid) begin
+ wb_ctrl_ren3 <= mem_ctrl_ren3;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(mem_reg_valid) begin
+ wb_ctrl_swap12 <= mem_ctrl_swap12;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(mem_reg_valid) begin
+ wb_ctrl_swap23 <= mem_ctrl_swap23;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(mem_reg_valid) begin
+ wb_ctrl_single <= mem_ctrl_single;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(mem_reg_valid) begin
+ wb_ctrl_fromint <= mem_ctrl_fromint;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(mem_reg_valid) begin
+ wb_ctrl_toint <= mem_ctrl_toint;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(mem_reg_valid) begin
+ wb_ctrl_fastpipe <= mem_ctrl_fastpipe;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(mem_reg_valid) begin
+ wb_ctrl_fma <= mem_ctrl_fma;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(mem_reg_valid) begin
+ wb_ctrl_div <= mem_ctrl_div;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(mem_reg_valid) begin
+ wb_ctrl_sqrt <= mem_ctrl_sqrt;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(mem_reg_valid) begin
+ wb_ctrl_round <= mem_ctrl_round;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(mem_reg_valid) begin
+ wb_ctrl_wflags <= mem_ctrl_wflags;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ load_wb <= io_dmem_resp_val;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_dmem_resp_val) begin
+ load_wb_single <= T_339;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_dmem_resp_val) begin
+ load_wb_data <= io_dmem_resp_data;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_dmem_resp_val) begin
+ load_wb_tag <= io_dmem_resp_tag;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_valid) begin
+ if(fp_decoder_io_sigs_ren2) begin
+ if(fp_decoder_io_sigs_swap12) begin
+ ex_ra1 <= T_729;
+ end else begin
+ if(fp_decoder_io_sigs_ren1) begin
+ if(T_726) begin
+ ex_ra1 <= T_727;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(fp_decoder_io_sigs_ren1) begin
+ if(T_726) begin
+ ex_ra1 <= T_727;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_valid) begin
+ if(fp_decoder_io_sigs_ren2) begin
+ if(T_735) begin
+ ex_ra2 <= T_736;
+ end else begin
+ if(fp_decoder_io_sigs_ren1) begin
+ if(fp_decoder_io_sigs_swap12) begin
+ ex_ra2 <= T_728;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(fp_decoder_io_sigs_ren1) begin
+ if(fp_decoder_io_sigs_swap12) begin
+ ex_ra2 <= T_728;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(io_valid) begin
+ if(fp_decoder_io_sigs_ren3) begin
+ ex_ra3 <= T_737;
+ end else begin
+ if(fp_decoder_io_sigs_ren2) begin
+ if(fp_decoder_io_sigs_swap23) begin
+ ex_ra3 <= T_730;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1055) begin
+ divSqrt_wen <= T_1065;
+ end else begin
+ divSqrt_wen <= 1'h0;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1061) begin
+ divSqrt_waddr <= T_1063;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ divSqrt_in_flight <= 1'h0;
+ end else begin
+ if(T_1055) begin
+ divSqrt_in_flight <= 1'h0;
+ end else begin
+ if(T_1061) begin
+ divSqrt_in_flight <= 1'h1;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1061) begin
+ divSqrt_killed <= killm;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ wen <= 2'h0;
+ end else begin
+ if(mem_wen) begin
+ if(T_948) begin
+ wen <= T_950;
+ end else begin
+ wen <= T_946;
+ end
+ end else begin
+ wen <= T_946;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(mem_wen) begin
+ if(T_954) begin
+ winfo_0 <= mem_winfo;
+ end else begin
+ if(T_945) begin
+ winfo_0 <= winfo_1;
+ end else begin
+ ;
+ end
+ end
+ end else begin
+ if(T_945) begin
+ winfo_0 <= winfo_1;
+ end else begin
+ ;
+ end
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(mem_wen) begin
+ if(T_958) begin
+ winfo_1 <= mem_winfo;
+ end else begin
+ ;
+ end
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(req_valid) begin
+ write_port_busy <= T_920;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(mem_ctrl_toint) begin
+ wb_toint_exc <= fpiu_io_out_bits_exc;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ T_1032 <= T_1031;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1061) begin
+ T_1046 <= mem_ctrl_single;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1061) begin
+ T_1048 <= T_1053_io_roundingMode;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1055) begin
+ T_1050 <= T_1053_io_exceptionFlags;
+ end else begin
+ ;
+ end
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ if(T_1055) begin
+ T_1052 <= T_1053_io_out;
+ end else begin
+ ;
+ end
+ end
+ end
+ always @(posedge regfile_T_718_clk) begin
+ if(regfile_T_718_en & regfile_T_718_mask) begin
+ regfile[regfile_T_718_addr] <= regfile_T_718_data;
+ end
+ end
+ always @(posedge regfile_T_985_clk) begin
+ if(regfile_T_985_en & regfile_T_985_mask) begin
+ regfile[regfile_T_985_addr] <= regfile_T_985_data;
+ end
+ end
+endmodule
+module RocketTile(
+ input clk,
+ input reset,
+ input io_cached_0_acquire_ready,
+ output io_cached_0_acquire_valid,
+ output [25:0] io_cached_0_acquire_bits_addr_block,
+ output [1:0] io_cached_0_acquire_bits_client_xact_id,
+ output [1:0] io_cached_0_acquire_bits_addr_beat,
+ output io_cached_0_acquire_bits_is_builtin_type,
+ output [2:0] io_cached_0_acquire_bits_a_type,
+ output [16:0] io_cached_0_acquire_bits_union,
+ output [127:0] io_cached_0_acquire_bits_data,
+ output io_cached_0_grant_ready,
+ input io_cached_0_grant_valid,
+ input [1:0] io_cached_0_grant_bits_addr_beat,
+ input [1:0] io_cached_0_grant_bits_client_xact_id,
+ input [3:0] io_cached_0_grant_bits_manager_xact_id,
+ input io_cached_0_grant_bits_is_builtin_type,
+ input [3:0] io_cached_0_grant_bits_g_type,
+ input [127:0] io_cached_0_grant_bits_data,
+ output io_cached_0_probe_ready,
+ input io_cached_0_probe_valid,
+ input [25:0] io_cached_0_probe_bits_addr_block,
+ input [1:0] io_cached_0_probe_bits_p_type,
+ input io_cached_0_release_ready,
+ output io_cached_0_release_valid,
+ output [1:0] io_cached_0_release_bits_addr_beat,
+ output [25:0] io_cached_0_release_bits_addr_block,
+ output [1:0] io_cached_0_release_bits_client_xact_id,
+ output io_cached_0_release_bits_voluntary,
+ output [2:0] io_cached_0_release_bits_r_type,
+ output [127:0] io_cached_0_release_bits_data,
+ input io_uncached_0_acquire_ready,
+ output io_uncached_0_acquire_valid,
+ output [25:0] io_uncached_0_acquire_bits_addr_block,
+ output [1:0] io_uncached_0_acquire_bits_client_xact_id,
+ output [1:0] io_uncached_0_acquire_bits_addr_beat,
+ output io_uncached_0_acquire_bits_is_builtin_type,
+ output [2:0] io_uncached_0_acquire_bits_a_type,
+ output [16:0] io_uncached_0_acquire_bits_union,
+ output [127:0] io_uncached_0_acquire_bits_data,
+ output io_uncached_0_grant_ready,
+ input io_uncached_0_grant_valid,
+ input [1:0] io_uncached_0_grant_bits_addr_beat,
+ input [1:0] io_uncached_0_grant_bits_client_xact_id,
+ input [3:0] io_uncached_0_grant_bits_manager_xact_id,
+ input io_uncached_0_grant_bits_is_builtin_type,
+ input [3:0] io_uncached_0_grant_bits_g_type,
+ input [127:0] io_uncached_0_grant_bits_data,
+ input io_host_reset,
+ input io_host_id,
+ output io_host_csr_req_ready,
+ input io_host_csr_req_valid,
+ input io_host_csr_req_bits_rw,
+ input [11:0] io_host_csr_req_bits_addr,
+ input [63:0] io_host_csr_req_bits_data,
+ input io_host_csr_resp_ready,
+ output io_host_csr_resp_valid,
+ output [63:0] io_host_csr_resp_bits,
+ output io_host_debug_stats_csr,
+ input io_dma_req_ready,
+ output io_dma_req_valid,
+ output [1:0] io_dma_req_bits_client_xact_id,
+ output [2:0] io_dma_req_bits_cmd,
+ output [31:0] io_dma_req_bits_source,
+ output [31:0] io_dma_req_bits_dest,
+ output [31:0] io_dma_req_bits_length,
+ output [1:0] io_dma_req_bits_size,
+ output io_dma_resp_ready,
+ input io_dma_resp_valid,
+ input [1:0] io_dma_resp_bits_client_xact_id,
+ input [1:0] io_dma_resp_bits_status
+);
+ wire core_clk;
+ wire core_reset;
+ wire core_io_host_reset;
+ wire core_io_host_id;
+ wire core_io_host_csr_req_ready;
+ wire core_io_host_csr_req_valid;
+ wire core_io_host_csr_req_bits_rw;
+ wire [11:0] core_io_host_csr_req_bits_addr;
+ wire [63:0] core_io_host_csr_req_bits_data;
+ wire core_io_host_csr_resp_ready;
+ wire core_io_host_csr_resp_valid;
+ wire [63:0] core_io_host_csr_resp_bits;
+ wire core_io_host_debug_stats_csr;
+ wire core_io_imem_req_valid;
+ wire [39:0] core_io_imem_req_bits_pc;
+ wire core_io_imem_resp_ready;
+ wire core_io_imem_resp_valid;
+ wire [39:0] core_io_imem_resp_bits_pc;
+ wire [31:0] core_io_imem_resp_bits_data_0;
+ wire core_io_imem_resp_bits_mask;
+ wire core_io_imem_resp_bits_xcpt_if;
+ wire core_io_imem_btb_resp_valid;
+ wire core_io_imem_btb_resp_bits_taken;
+ wire core_io_imem_btb_resp_bits_mask;
+ wire core_io_imem_btb_resp_bits_bridx;
+ wire [38:0] core_io_imem_btb_resp_bits_target;
+ wire [5:0] core_io_imem_btb_resp_bits_entry;
+ wire [6:0] core_io_imem_btb_resp_bits_bht_history;
+ wire [1:0] core_io_imem_btb_resp_bits_bht_value;
+ wire core_io_imem_btb_update_valid;
+ wire core_io_imem_btb_update_bits_prediction_valid;
+ wire core_io_imem_btb_update_bits_prediction_bits_taken;
+ wire core_io_imem_btb_update_bits_prediction_bits_mask;
+ wire core_io_imem_btb_update_bits_prediction_bits_bridx;
+ wire [38:0] core_io_imem_btb_update_bits_prediction_bits_target;
+ wire [5:0] core_io_imem_btb_update_bits_prediction_bits_entry;
+ wire [6:0] core_io_imem_btb_update_bits_prediction_bits_bht_history;
+ wire [1:0] core_io_imem_btb_update_bits_prediction_bits_bht_value;
+ wire [38:0] core_io_imem_btb_update_bits_pc;
+ wire [38:0] core_io_imem_btb_update_bits_target;
+ wire core_io_imem_btb_update_bits_taken;
+ wire core_io_imem_btb_update_bits_isJump;
+ wire core_io_imem_btb_update_bits_isReturn;
+ wire [38:0] core_io_imem_btb_update_bits_br_pc;
+ wire core_io_imem_bht_update_valid;
+ wire core_io_imem_bht_update_bits_prediction_valid;
+ wire core_io_imem_bht_update_bits_prediction_bits_taken;
+ wire core_io_imem_bht_update_bits_prediction_bits_mask;
+ wire core_io_imem_bht_update_bits_prediction_bits_bridx;
+ wire [38:0] core_io_imem_bht_update_bits_prediction_bits_target;
+ wire [5:0] core_io_imem_bht_update_bits_prediction_bits_entry;
+ wire [6:0] core_io_imem_bht_update_bits_prediction_bits_bht_history;
+ wire [1:0] core_io_imem_bht_update_bits_prediction_bits_bht_value;
+ wire [38:0] core_io_imem_bht_update_bits_pc;
+ wire core_io_imem_bht_update_bits_taken;
+ wire core_io_imem_bht_update_bits_mispredict;
+ wire core_io_imem_ras_update_valid;
+ wire core_io_imem_ras_update_bits_isCall;
+ wire core_io_imem_ras_update_bits_isReturn;
+ wire [38:0] core_io_imem_ras_update_bits_returnAddr;
+ wire core_io_imem_ras_update_bits_prediction_valid;
+ wire core_io_imem_ras_update_bits_prediction_bits_taken;
+ wire core_io_imem_ras_update_bits_prediction_bits_mask;
+ wire core_io_imem_ras_update_bits_prediction_bits_bridx;
+ wire [38:0] core_io_imem_ras_update_bits_prediction_bits_target;
+ wire [5:0] core_io_imem_ras_update_bits_prediction_bits_entry;
+ wire [6:0] core_io_imem_ras_update_bits_prediction_bits_bht_history;
+ wire [1:0] core_io_imem_ras_update_bits_prediction_bits_bht_value;
+ wire core_io_imem_invalidate;
+ wire [39:0] core_io_imem_npc;
+ wire core_io_dmem_req_ready;
+ wire core_io_dmem_req_valid;
+ wire [39:0] core_io_dmem_req_bits_addr;
+ wire [8:0] core_io_dmem_req_bits_tag;
+ wire [4:0] core_io_dmem_req_bits_cmd;
+ wire [2:0] core_io_dmem_req_bits_typ;
+ wire core_io_dmem_req_bits_kill;
+ wire core_io_dmem_req_bits_phys;
+ wire [63:0] core_io_dmem_req_bits_data;
+ wire core_io_dmem_resp_valid;
+ wire [39:0] core_io_dmem_resp_bits_addr;
+ wire [8:0] core_io_dmem_resp_bits_tag;
+ wire [4:0] core_io_dmem_resp_bits_cmd;
+ wire [2:0] core_io_dmem_resp_bits_typ;
+ wire [63:0] core_io_dmem_resp_bits_data;
+ wire core_io_dmem_resp_bits_nack;
+ wire core_io_dmem_resp_bits_replay;
+ wire core_io_dmem_resp_bits_has_data;
+ wire [63:0] core_io_dmem_resp_bits_data_word_bypass;
+ wire [63:0] core_io_dmem_resp_bits_store_data;
+ wire core_io_dmem_replay_next_valid;
+ wire [8:0] core_io_dmem_replay_next_bits;
+ wire core_io_dmem_xcpt_ma_ld;
+ wire core_io_dmem_xcpt_ma_st;
+ wire core_io_dmem_xcpt_pf_ld;
+ wire core_io_dmem_xcpt_pf_st;
+ wire core_io_dmem_invalidate_lr;
+ wire core_io_dmem_ordered;
+ wire [31:0] core_io_ptw_ptbr;
+ wire core_io_ptw_invalidate;
+ wire core_io_ptw_status_sd;
+ wire [30:0] core_io_ptw_status_zero2;
+ wire core_io_ptw_status_sd_rv32;
+ wire [8:0] core_io_ptw_status_zero1;
+ wire [4:0] core_io_ptw_status_vm;
+ wire core_io_ptw_status_mprv;
+ wire [1:0] core_io_ptw_status_xs;
+ wire [1:0] core_io_ptw_status_fs;
+ wire [1:0] core_io_ptw_status_prv3;
+ wire core_io_ptw_status_ie3;
+ wire [1:0] core_io_ptw_status_prv2;
+ wire core_io_ptw_status_ie2;
+ wire [1:0] core_io_ptw_status_prv1;
+ wire core_io_ptw_status_ie1;
+ wire [1:0] core_io_ptw_status_prv;
+ wire core_io_ptw_status_ie;
+ wire [31:0] core_io_fpu_inst;
+ wire [63:0] core_io_fpu_fromint_data;
+ wire [2:0] core_io_fpu_fcsr_rm;
+ wire core_io_fpu_fcsr_flags_valid;
+ wire [4:0] core_io_fpu_fcsr_flags_bits;
+ wire [63:0] core_io_fpu_store_data;
+ wire [63:0] core_io_fpu_toint_data;
+ wire core_io_fpu_dmem_resp_val;
+ wire [2:0] core_io_fpu_dmem_resp_type;
+ wire [4:0] core_io_fpu_dmem_resp_tag;
+ wire [63:0] core_io_fpu_dmem_resp_data;
+ wire core_io_fpu_valid;
+ wire core_io_fpu_fcsr_rdy;
+ wire core_io_fpu_nack_mem;
+ wire core_io_fpu_illegal_rm;
+ wire core_io_fpu_killx;
+ wire core_io_fpu_killm;
+ wire [4:0] core_io_fpu_dec_cmd;
+ wire core_io_fpu_dec_ldst;
+ wire core_io_fpu_dec_wen;
+ wire core_io_fpu_dec_ren1;
+ wire core_io_fpu_dec_ren2;
+ wire core_io_fpu_dec_ren3;
+ wire core_io_fpu_dec_swap12;
+ wire core_io_fpu_dec_swap23;
+ wire core_io_fpu_dec_single;
+ wire core_io_fpu_dec_fromint;
+ wire core_io_fpu_dec_toint;
+ wire core_io_fpu_dec_fastpipe;
+ wire core_io_fpu_dec_fma;
+ wire core_io_fpu_dec_div;
+ wire core_io_fpu_dec_sqrt;
+ wire core_io_fpu_dec_round;
+ wire core_io_fpu_dec_wflags;
+ wire core_io_fpu_sboard_set;
+ wire core_io_fpu_sboard_clr;
+ wire [4:0] core_io_fpu_sboard_clra;
+ wire core_io_fpu_cp_req_ready;
+ wire core_io_fpu_cp_req_valid;
+ wire [4:0] core_io_fpu_cp_req_bits_cmd;
+ wire core_io_fpu_cp_req_bits_ldst;
+ wire core_io_fpu_cp_req_bits_wen;
+ wire core_io_fpu_cp_req_bits_ren1;
+ wire core_io_fpu_cp_req_bits_ren2;
+ wire core_io_fpu_cp_req_bits_ren3;
+ wire core_io_fpu_cp_req_bits_swap12;
+ wire core_io_fpu_cp_req_bits_swap23;
+ wire core_io_fpu_cp_req_bits_single;
+ wire core_io_fpu_cp_req_bits_fromint;
+ wire core_io_fpu_cp_req_bits_toint;
+ wire core_io_fpu_cp_req_bits_fastpipe;
+ wire core_io_fpu_cp_req_bits_fma;
+ wire core_io_fpu_cp_req_bits_div;
+ wire core_io_fpu_cp_req_bits_sqrt;
+ wire core_io_fpu_cp_req_bits_round;
+ wire core_io_fpu_cp_req_bits_wflags;
+ wire [2:0] core_io_fpu_cp_req_bits_rm;
+ wire [1:0] core_io_fpu_cp_req_bits_typ;
+ wire [64:0] core_io_fpu_cp_req_bits_in1;
+ wire [64:0] core_io_fpu_cp_req_bits_in2;
+ wire [64:0] core_io_fpu_cp_req_bits_in3;
+ wire core_io_fpu_cp_resp_ready;
+ wire core_io_fpu_cp_resp_valid;
+ wire [64:0] core_io_fpu_cp_resp_bits_data;
+ wire [4:0] core_io_fpu_cp_resp_bits_exc;
+ wire core_io_rocc_cmd_ready;
+ wire core_io_rocc_cmd_valid;
+ wire [6:0] core_io_rocc_cmd_bits_inst_funct;
+ wire [4:0] core_io_rocc_cmd_bits_inst_rs2;
+ wire [4:0] core_io_rocc_cmd_bits_inst_rs1;
+ wire core_io_rocc_cmd_bits_inst_xd;
+ wire core_io_rocc_cmd_bits_inst_xs1;
+ wire core_io_rocc_cmd_bits_inst_xs2;
+ wire [4:0] core_io_rocc_cmd_bits_inst_rd;
+ wire [6:0] core_io_rocc_cmd_bits_inst_opcode;
+ wire [63:0] core_io_rocc_cmd_bits_rs1;
+ wire [63:0] core_io_rocc_cmd_bits_rs2;
+ wire core_io_rocc_resp_ready;
+ wire core_io_rocc_resp_valid;
+ wire [4:0] core_io_rocc_resp_bits_rd;
+ wire [63:0] core_io_rocc_resp_bits_data;
+ wire core_io_rocc_mem_req_ready;
+ wire core_io_rocc_mem_req_valid;
+ wire [39:0] core_io_rocc_mem_req_bits_addr;
+ wire [8:0] core_io_rocc_mem_req_bits_tag;
+ wire [4:0] core_io_rocc_mem_req_bits_cmd;
+ wire [2:0] core_io_rocc_mem_req_bits_typ;
+ wire core_io_rocc_mem_req_bits_kill;
+ wire core_io_rocc_mem_req_bits_phys;
+ wire [63:0] core_io_rocc_mem_req_bits_data;
+ wire core_io_rocc_mem_resp_valid;
+ wire [39:0] core_io_rocc_mem_resp_bits_addr;
+ wire [8:0] core_io_rocc_mem_resp_bits_tag;
+ wire [4:0] core_io_rocc_mem_resp_bits_cmd;
+ wire [2:0] core_io_rocc_mem_resp_bits_typ;
+ wire [63:0] core_io_rocc_mem_resp_bits_data;
+ wire core_io_rocc_mem_resp_bits_nack;
+ wire core_io_rocc_mem_resp_bits_replay;
+ wire core_io_rocc_mem_resp_bits_has_data;
+ wire [63:0] core_io_rocc_mem_resp_bits_data_word_bypass;
+ wire [63:0] core_io_rocc_mem_resp_bits_store_data;
+ wire core_io_rocc_mem_replay_next_valid;
+ wire [8:0] core_io_rocc_mem_replay_next_bits;
+ wire core_io_rocc_mem_xcpt_ma_ld;
+ wire core_io_rocc_mem_xcpt_ma_st;
+ wire core_io_rocc_mem_xcpt_pf_ld;
+ wire core_io_rocc_mem_xcpt_pf_st;
+ wire core_io_rocc_mem_invalidate_lr;
+ wire core_io_rocc_mem_ordered;
+ wire core_io_rocc_busy;
+ wire core_io_rocc_s;
+ wire core_io_rocc_interrupt;
+ wire core_io_rocc_autl_acquire_ready;
+ wire core_io_rocc_autl_acquire_valid;
+ wire [25:0] core_io_rocc_autl_acquire_bits_addr_block;
+ wire [1:0] core_io_rocc_autl_acquire_bits_client_xact_id;
+ wire [1:0] core_io_rocc_autl_acquire_bits_addr_beat;
+ wire core_io_rocc_autl_acquire_bits_is_builtin_type;
+ wire [2:0] core_io_rocc_autl_acquire_bits_a_type;
+ wire [16:0] core_io_rocc_autl_acquire_bits_union;
+ wire [127:0] core_io_rocc_autl_acquire_bits_data;
+ wire core_io_rocc_autl_grant_ready;
+ wire core_io_rocc_autl_grant_valid;
+ wire [1:0] core_io_rocc_autl_grant_bits_addr_beat;
+ wire [1:0] core_io_rocc_autl_grant_bits_client_xact_id;
+ wire [3:0] core_io_rocc_autl_grant_bits_manager_xact_id;
+ wire core_io_rocc_autl_grant_bits_is_builtin_type;
+ wire [3:0] core_io_rocc_autl_grant_bits_g_type;
+ wire [127:0] core_io_rocc_autl_grant_bits_data;
+ wire core_io_rocc_iptw_req_ready;
+ wire core_io_rocc_iptw_req_valid;
+ wire [26:0] core_io_rocc_iptw_req_bits_addr;
+ wire [1:0] core_io_rocc_iptw_req_bits_prv;
+ wire core_io_rocc_iptw_req_bits_store;
+ wire core_io_rocc_iptw_req_bits_fetch;
+ wire core_io_rocc_iptw_resp_valid;
+ wire core_io_rocc_iptw_resp_bits_error;
+ wire [19:0] core_io_rocc_iptw_resp_bits_pte_ppn;
+ wire [2:0] core_io_rocc_iptw_resp_bits_pte_reserved_for_software;
+ wire core_io_rocc_iptw_resp_bits_pte_d;
+ wire core_io_rocc_iptw_resp_bits_pte_r;
+ wire [3:0] core_io_rocc_iptw_resp_bits_pte_typ;
+ wire core_io_rocc_iptw_resp_bits_pte_v;
+ wire core_io_rocc_iptw_status_sd;
+ wire [30:0] core_io_rocc_iptw_status_zero2;
+ wire core_io_rocc_iptw_status_sd_rv32;
+ wire [8:0] core_io_rocc_iptw_status_zero1;
+ wire [4:0] core_io_rocc_iptw_status_vm;
+ wire core_io_rocc_iptw_status_mprv;
+ wire [1:0] core_io_rocc_iptw_status_xs;
+ wire [1:0] core_io_rocc_iptw_status_fs;
+ wire [1:0] core_io_rocc_iptw_status_prv3;
+ wire core_io_rocc_iptw_status_ie3;
+ wire [1:0] core_io_rocc_iptw_status_prv2;
+ wire core_io_rocc_iptw_status_ie2;
+ wire [1:0] core_io_rocc_iptw_status_prv1;
+ wire core_io_rocc_iptw_status_ie1;
+ wire [1:0] core_io_rocc_iptw_status_prv;
+ wire core_io_rocc_iptw_status_ie;
+ wire core_io_rocc_iptw_invalidate;
+ wire core_io_rocc_dptw_req_ready;
+ wire core_io_rocc_dptw_req_valid;
+ wire [26:0] core_io_rocc_dptw_req_bits_addr;
+ wire [1:0] core_io_rocc_dptw_req_bits_prv;
+ wire core_io_rocc_dptw_req_bits_store;
+ wire core_io_rocc_dptw_req_bits_fetch;
+ wire core_io_rocc_dptw_resp_valid;
+ wire core_io_rocc_dptw_resp_bits_error;
+ wire [19:0] core_io_rocc_dptw_resp_bits_pte_ppn;
+ wire [2:0] core_io_rocc_dptw_resp_bits_pte_reserved_for_software;
+ wire core_io_rocc_dptw_resp_bits_pte_d;
+ wire core_io_rocc_dptw_resp_bits_pte_r;
+ wire [3:0] core_io_rocc_dptw_resp_bits_pte_typ;
+ wire core_io_rocc_dptw_resp_bits_pte_v;
+ wire core_io_rocc_dptw_status_sd;
+ wire [30:0] core_io_rocc_dptw_status_zero2;
+ wire core_io_rocc_dptw_status_sd_rv32;
+ wire [8:0] core_io_rocc_dptw_status_zero1;
+ wire [4:0] core_io_rocc_dptw_status_vm;
+ wire core_io_rocc_dptw_status_mprv;
+ wire [1:0] core_io_rocc_dptw_status_xs;
+ wire [1:0] core_io_rocc_dptw_status_fs;
+ wire [1:0] core_io_rocc_dptw_status_prv3;
+ wire core_io_rocc_dptw_status_ie3;
+ wire [1:0] core_io_rocc_dptw_status_prv2;
+ wire core_io_rocc_dptw_status_ie2;
+ wire [1:0] core_io_rocc_dptw_status_prv1;
+ wire core_io_rocc_dptw_status_ie1;
+ wire [1:0] core_io_rocc_dptw_status_prv;
+ wire core_io_rocc_dptw_status_ie;
+ wire core_io_rocc_dptw_invalidate;
+ wire core_io_rocc_pptw_req_ready;
+ wire core_io_rocc_pptw_req_valid;
+ wire [26:0] core_io_rocc_pptw_req_bits_addr;
+ wire [1:0] core_io_rocc_pptw_req_bits_prv;
+ wire core_io_rocc_pptw_req_bits_store;
+ wire core_io_rocc_pptw_req_bits_fetch;
+ wire core_io_rocc_pptw_resp_valid;
+ wire core_io_rocc_pptw_resp_bits_error;
+ wire [19:0] core_io_rocc_pptw_resp_bits_pte_ppn;
+ wire [2:0] core_io_rocc_pptw_resp_bits_pte_reserved_for_software;
+ wire core_io_rocc_pptw_resp_bits_pte_d;
+ wire core_io_rocc_pptw_resp_bits_pte_r;
+ wire [3:0] core_io_rocc_pptw_resp_bits_pte_typ;
+ wire core_io_rocc_pptw_resp_bits_pte_v;
+ wire core_io_rocc_pptw_status_sd;
+ wire [30:0] core_io_rocc_pptw_status_zero2;
+ wire core_io_rocc_pptw_status_sd_rv32;
+ wire [8:0] core_io_rocc_pptw_status_zero1;
+ wire [4:0] core_io_rocc_pptw_status_vm;
+ wire core_io_rocc_pptw_status_mprv;
+ wire [1:0] core_io_rocc_pptw_status_xs;
+ wire [1:0] core_io_rocc_pptw_status_fs;
+ wire [1:0] core_io_rocc_pptw_status_prv3;
+ wire core_io_rocc_pptw_status_ie3;
+ wire [1:0] core_io_rocc_pptw_status_prv2;
+ wire core_io_rocc_pptw_status_ie2;
+ wire [1:0] core_io_rocc_pptw_status_prv1;
+ wire core_io_rocc_pptw_status_ie1;
+ wire [1:0] core_io_rocc_pptw_status_prv;
+ wire core_io_rocc_pptw_status_ie;
+ wire core_io_rocc_pptw_invalidate;
+ wire core_io_rocc_fpu_req_ready;
+ wire core_io_rocc_fpu_req_valid;
+ wire [4:0] core_io_rocc_fpu_req_bits_cmd;
+ wire core_io_rocc_fpu_req_bits_ldst;
+ wire core_io_rocc_fpu_req_bits_wen;
+ wire core_io_rocc_fpu_req_bits_ren1;
+ wire core_io_rocc_fpu_req_bits_ren2;
+ wire core_io_rocc_fpu_req_bits_ren3;
+ wire core_io_rocc_fpu_req_bits_swap12;
+ wire core_io_rocc_fpu_req_bits_swap23;
+ wire core_io_rocc_fpu_req_bits_single;
+ wire core_io_rocc_fpu_req_bits_fromint;
+ wire core_io_rocc_fpu_req_bits_toint;
+ wire core_io_rocc_fpu_req_bits_fastpipe;
+ wire core_io_rocc_fpu_req_bits_fma;
+ wire core_io_rocc_fpu_req_bits_div;
+ wire core_io_rocc_fpu_req_bits_sqrt;
+ wire core_io_rocc_fpu_req_bits_round;
+ wire core_io_rocc_fpu_req_bits_wflags;
+ wire [2:0] core_io_rocc_fpu_req_bits_rm;
+ wire [1:0] core_io_rocc_fpu_req_bits_typ;
+ wire [64:0] core_io_rocc_fpu_req_bits_in1;
+ wire [64:0] core_io_rocc_fpu_req_bits_in2;
+ wire [64:0] core_io_rocc_fpu_req_bits_in3;
+ wire core_io_rocc_fpu_resp_ready;
+ wire core_io_rocc_fpu_resp_valid;
+ wire [64:0] core_io_rocc_fpu_resp_bits_data;
+ wire [4:0] core_io_rocc_fpu_resp_bits_exc;
+ wire core_io_rocc_exception;
+ wire core_io_rocc_dma_req_ready;
+ wire core_io_rocc_dma_req_valid;
+ wire [1:0] core_io_rocc_dma_req_bits_client_xact_id;
+ wire [2:0] core_io_rocc_dma_req_bits_cmd;
+ wire [31:0] core_io_rocc_dma_req_bits_source;
+ wire [31:0] core_io_rocc_dma_req_bits_dest;
+ wire [31:0] core_io_rocc_dma_req_bits_length;
+ wire [1:0] core_io_rocc_dma_req_bits_size;
+ wire core_io_rocc_dma_resp_ready;
+ wire core_io_rocc_dma_resp_valid;
+ wire [1:0] core_io_rocc_dma_resp_bits_client_xact_id;
+ wire [1:0] core_io_rocc_dma_resp_bits_status;
+ wire icache_clk;
+ wire icache_reset;
+ wire icache_io_cpu_req_valid;
+ wire [39:0] icache_io_cpu_req_bits_pc;
+ wire icache_io_cpu_resp_ready;
+ wire icache_io_cpu_resp_valid;
+ wire [39:0] icache_io_cpu_resp_bits_pc;
+ wire [31:0] icache_io_cpu_resp_bits_data_0;
+ wire icache_io_cpu_resp_bits_mask;
+ wire icache_io_cpu_resp_bits_xcpt_if;
+ wire icache_io_cpu_btb_resp_valid;
+ wire icache_io_cpu_btb_resp_bits_taken;
+ wire icache_io_cpu_btb_resp_bits_mask;
+ wire icache_io_cpu_btb_resp_bits_bridx;
+ wire [38:0] icache_io_cpu_btb_resp_bits_target;
+ wire [5:0] icache_io_cpu_btb_resp_bits_entry;
+ wire [6:0] icache_io_cpu_btb_resp_bits_bht_history;
+ wire [1:0] icache_io_cpu_btb_resp_bits_bht_value;
+ wire icache_io_cpu_btb_update_valid;
+ wire icache_io_cpu_btb_update_bits_prediction_valid;
+ wire icache_io_cpu_btb_update_bits_prediction_bits_taken;
+ wire icache_io_cpu_btb_update_bits_prediction_bits_mask;
+ wire icache_io_cpu_btb_update_bits_prediction_bits_bridx;
+ wire [38:0] icache_io_cpu_btb_update_bits_prediction_bits_target;
+ wire [5:0] icache_io_cpu_btb_update_bits_prediction_bits_entry;
+ wire [6:0] icache_io_cpu_btb_update_bits_prediction_bits_bht_history;
+ wire [1:0] icache_io_cpu_btb_update_bits_prediction_bits_bht_value;
+ wire [38:0] icache_io_cpu_btb_update_bits_pc;
+ wire [38:0] icache_io_cpu_btb_update_bits_target;
+ wire icache_io_cpu_btb_update_bits_taken;
+ wire icache_io_cpu_btb_update_bits_isJump;
+ wire icache_io_cpu_btb_update_bits_isReturn;
+ wire [38:0] icache_io_cpu_btb_update_bits_br_pc;
+ wire icache_io_cpu_bht_update_valid;
+ wire icache_io_cpu_bht_update_bits_prediction_valid;
+ wire icache_io_cpu_bht_update_bits_prediction_bits_taken;
+ wire icache_io_cpu_bht_update_bits_prediction_bits_mask;
+ wire icache_io_cpu_bht_update_bits_prediction_bits_bridx;
+ wire [38:0] icache_io_cpu_bht_update_bits_prediction_bits_target;
+ wire [5:0] icache_io_cpu_bht_update_bits_prediction_bits_entry;
+ wire [6:0] icache_io_cpu_bht_update_bits_prediction_bits_bht_history;
+ wire [1:0] icache_io_cpu_bht_update_bits_prediction_bits_bht_value;
+ wire [38:0] icache_io_cpu_bht_update_bits_pc;
+ wire icache_io_cpu_bht_update_bits_taken;
+ wire icache_io_cpu_bht_update_bits_mispredict;
+ wire icache_io_cpu_ras_update_valid;
+ wire icache_io_cpu_ras_update_bits_isCall;
+ wire icache_io_cpu_ras_update_bits_isReturn;
+ wire [38:0] icache_io_cpu_ras_update_bits_returnAddr;
+ wire icache_io_cpu_ras_update_bits_prediction_valid;
+ wire icache_io_cpu_ras_update_bits_prediction_bits_taken;
+ wire icache_io_cpu_ras_update_bits_prediction_bits_mask;
+ wire icache_io_cpu_ras_update_bits_prediction_bits_bridx;
+ wire [38:0] icache_io_cpu_ras_update_bits_prediction_bits_target;
+ wire [5:0] icache_io_cpu_ras_update_bits_prediction_bits_entry;
+ wire [6:0] icache_io_cpu_ras_update_bits_prediction_bits_bht_history;
+ wire [1:0] icache_io_cpu_ras_update_bits_prediction_bits_bht_value;
+ wire icache_io_cpu_invalidate;
+ wire [39:0] icache_io_cpu_npc;
+ wire icache_io_ptw_req_ready;
+ wire icache_io_ptw_req_valid;
+ wire [26:0] icache_io_ptw_req_bits_addr;
+ wire [1:0] icache_io_ptw_req_bits_prv;
+ wire icache_io_ptw_req_bits_store;
+ wire icache_io_ptw_req_bits_fetch;
+ wire icache_io_ptw_resp_valid;
+ wire icache_io_ptw_resp_bits_error;
+ wire [19:0] icache_io_ptw_resp_bits_pte_ppn;
+ wire [2:0] icache_io_ptw_resp_bits_pte_reserved_for_software;
+ wire icache_io_ptw_resp_bits_pte_d;
+ wire icache_io_ptw_resp_bits_pte_r;
+ wire [3:0] icache_io_ptw_resp_bits_pte_typ;
+ wire icache_io_ptw_resp_bits_pte_v;
+ wire icache_io_ptw_status_sd;
+ wire [30:0] icache_io_ptw_status_zero2;
+ wire icache_io_ptw_status_sd_rv32;
+ wire [8:0] icache_io_ptw_status_zero1;
+ wire [4:0] icache_io_ptw_status_vm;
+ wire icache_io_ptw_status_mprv;
+ wire [1:0] icache_io_ptw_status_xs;
+ wire [1:0] icache_io_ptw_status_fs;
+ wire [1:0] icache_io_ptw_status_prv3;
+ wire icache_io_ptw_status_ie3;
+ wire [1:0] icache_io_ptw_status_prv2;
+ wire icache_io_ptw_status_ie2;
+ wire [1:0] icache_io_ptw_status_prv1;
+ wire icache_io_ptw_status_ie1;
+ wire [1:0] icache_io_ptw_status_prv;
+ wire icache_io_ptw_status_ie;
+ wire icache_io_ptw_invalidate;
+ wire icache_io_mem_acquire_ready;
+ wire icache_io_mem_acquire_valid;
+ wire [25:0] icache_io_mem_acquire_bits_addr_block;
+ wire [1:0] icache_io_mem_acquire_bits_client_xact_id;
+ wire [1:0] icache_io_mem_acquire_bits_addr_beat;
+ wire icache_io_mem_acquire_bits_is_builtin_type;
+ wire [2:0] icache_io_mem_acquire_bits_a_type;
+ wire [16:0] icache_io_mem_acquire_bits_union;
+ wire [127:0] icache_io_mem_acquire_bits_data;
+ wire icache_io_mem_grant_ready;
+ wire icache_io_mem_grant_valid;
+ wire [1:0] icache_io_mem_grant_bits_addr_beat;
+ wire [1:0] icache_io_mem_grant_bits_client_xact_id;
+ wire [3:0] icache_io_mem_grant_bits_manager_xact_id;
+ wire icache_io_mem_grant_bits_is_builtin_type;
+ wire [3:0] icache_io_mem_grant_bits_g_type;
+ wire [127:0] icache_io_mem_grant_bits_data;
+ wire dcache_clk;
+ wire dcache_reset;
+ wire dcache_io_cpu_req_ready;
+ wire dcache_io_cpu_req_valid;
+ wire [39:0] dcache_io_cpu_req_bits_addr;
+ wire [8:0] dcache_io_cpu_req_bits_tag;
+ wire [4:0] dcache_io_cpu_req_bits_cmd;
+ wire [2:0] dcache_io_cpu_req_bits_typ;
+ wire dcache_io_cpu_req_bits_kill;
+ wire dcache_io_cpu_req_bits_phys;
+ wire [63:0] dcache_io_cpu_req_bits_data;
+ wire dcache_io_cpu_resp_valid;
+ wire [39:0] dcache_io_cpu_resp_bits_addr;
+ wire [8:0] dcache_io_cpu_resp_bits_tag;
+ wire [4:0] dcache_io_cpu_resp_bits_cmd;
+ wire [2:0] dcache_io_cpu_resp_bits_typ;
+ wire [63:0] dcache_io_cpu_resp_bits_data;
+ wire dcache_io_cpu_resp_bits_nack;
+ wire dcache_io_cpu_resp_bits_replay;
+ wire dcache_io_cpu_resp_bits_has_data;
+ wire [63:0] dcache_io_cpu_resp_bits_data_word_bypass;
+ wire [63:0] dcache_io_cpu_resp_bits_store_data;
+ wire dcache_io_cpu_replay_next_valid;
+ wire [8:0] dcache_io_cpu_replay_next_bits;
+ wire dcache_io_cpu_xcpt_ma_ld;
+ wire dcache_io_cpu_xcpt_ma_st;
+ wire dcache_io_cpu_xcpt_pf_ld;
+ wire dcache_io_cpu_xcpt_pf_st;
+ wire dcache_io_cpu_invalidate_lr;
+ wire dcache_io_cpu_ordered;
+ wire dcache_io_ptw_req_ready;
+ wire dcache_io_ptw_req_valid;
+ wire [26:0] dcache_io_ptw_req_bits_addr;
+ wire [1:0] dcache_io_ptw_req_bits_prv;
+ wire dcache_io_ptw_req_bits_store;
+ wire dcache_io_ptw_req_bits_fetch;
+ wire dcache_io_ptw_resp_valid;
+ wire dcache_io_ptw_resp_bits_error;
+ wire [19:0] dcache_io_ptw_resp_bits_pte_ppn;
+ wire [2:0] dcache_io_ptw_resp_bits_pte_reserved_for_software;
+ wire dcache_io_ptw_resp_bits_pte_d;
+ wire dcache_io_ptw_resp_bits_pte_r;
+ wire [3:0] dcache_io_ptw_resp_bits_pte_typ;
+ wire dcache_io_ptw_resp_bits_pte_v;
+ wire dcache_io_ptw_status_sd;
+ wire [30:0] dcache_io_ptw_status_zero2;
+ wire dcache_io_ptw_status_sd_rv32;
+ wire [8:0] dcache_io_ptw_status_zero1;
+ wire [4:0] dcache_io_ptw_status_vm;
+ wire dcache_io_ptw_status_mprv;
+ wire [1:0] dcache_io_ptw_status_xs;
+ wire [1:0] dcache_io_ptw_status_fs;
+ wire [1:0] dcache_io_ptw_status_prv3;
+ wire dcache_io_ptw_status_ie3;
+ wire [1:0] dcache_io_ptw_status_prv2;
+ wire dcache_io_ptw_status_ie2;
+ wire [1:0] dcache_io_ptw_status_prv1;
+ wire dcache_io_ptw_status_ie1;
+ wire [1:0] dcache_io_ptw_status_prv;
+ wire dcache_io_ptw_status_ie;
+ wire dcache_io_ptw_invalidate;
+ wire dcache_io_mem_acquire_ready;
+ wire dcache_io_mem_acquire_valid;
+ wire [25:0] dcache_io_mem_acquire_bits_addr_block;
+ wire [1:0] dcache_io_mem_acquire_bits_client_xact_id;
+ wire [1:0] dcache_io_mem_acquire_bits_addr_beat;
+ wire dcache_io_mem_acquire_bits_is_builtin_type;
+ wire [2:0] dcache_io_mem_acquire_bits_a_type;
+ wire [16:0] dcache_io_mem_acquire_bits_union;
+ wire [127:0] dcache_io_mem_acquire_bits_data;
+ wire dcache_io_mem_grant_ready;
+ wire dcache_io_mem_grant_valid;
+ wire [1:0] dcache_io_mem_grant_bits_addr_beat;
+ wire [1:0] dcache_io_mem_grant_bits_client_xact_id;
+ wire [3:0] dcache_io_mem_grant_bits_manager_xact_id;
+ wire dcache_io_mem_grant_bits_is_builtin_type;
+ wire [3:0] dcache_io_mem_grant_bits_g_type;
+ wire [127:0] dcache_io_mem_grant_bits_data;
+ wire dcache_io_mem_probe_ready;
+ wire dcache_io_mem_probe_valid;
+ wire [25:0] dcache_io_mem_probe_bits_addr_block;
+ wire [1:0] dcache_io_mem_probe_bits_p_type;
+ wire dcache_io_mem_release_ready;
+ wire dcache_io_mem_release_valid;
+ wire [1:0] dcache_io_mem_release_bits_addr_beat;
+ wire [25:0] dcache_io_mem_release_bits_addr_block;
+ wire [1:0] dcache_io_mem_release_bits_client_xact_id;
+ wire dcache_io_mem_release_bits_voluntary;
+ wire [2:0] dcache_io_mem_release_bits_r_type;
+ wire [127:0] dcache_io_mem_release_bits_data;
+ wire ptw_clk;
+ wire ptw_reset;
+ wire ptw_io_requestor_0_req_ready;
+ wire ptw_io_requestor_0_req_valid;
+ wire [26:0] ptw_io_requestor_0_req_bits_addr;
+ wire [1:0] ptw_io_requestor_0_req_bits_prv;
+ wire ptw_io_requestor_0_req_bits_store;
+ wire ptw_io_requestor_0_req_bits_fetch;
+ wire ptw_io_requestor_0_resp_valid;
+ wire ptw_io_requestor_0_resp_bits_error;
+ wire [19:0] ptw_io_requestor_0_resp_bits_pte_ppn;
+ wire [2:0] ptw_io_requestor_0_resp_bits_pte_reserved_for_software;
+ wire ptw_io_requestor_0_resp_bits_pte_d;
+ wire ptw_io_requestor_0_resp_bits_pte_r;
+ wire [3:0] ptw_io_requestor_0_resp_bits_pte_typ;
+ wire ptw_io_requestor_0_resp_bits_pte_v;
+ wire ptw_io_requestor_0_status_sd;
+ wire [30:0] ptw_io_requestor_0_status_zero2;
+ wire ptw_io_requestor_0_status_sd_rv32;
+ wire [8:0] ptw_io_requestor_0_status_zero1;
+ wire [4:0] ptw_io_requestor_0_status_vm;
+ wire ptw_io_requestor_0_status_mprv;
+ wire [1:0] ptw_io_requestor_0_status_xs;
+ wire [1:0] ptw_io_requestor_0_status_fs;
+ wire [1:0] ptw_io_requestor_0_status_prv3;
+ wire ptw_io_requestor_0_status_ie3;
+ wire [1:0] ptw_io_requestor_0_status_prv2;
+ wire ptw_io_requestor_0_status_ie2;
+ wire [1:0] ptw_io_requestor_0_status_prv1;
+ wire ptw_io_requestor_0_status_ie1;
+ wire [1:0] ptw_io_requestor_0_status_prv;
+ wire ptw_io_requestor_0_status_ie;
+ wire ptw_io_requestor_0_invalidate;
+ wire ptw_io_requestor_1_req_ready;
+ wire ptw_io_requestor_1_req_valid;
+ wire [26:0] ptw_io_requestor_1_req_bits_addr;
+ wire [1:0] ptw_io_requestor_1_req_bits_prv;
+ wire ptw_io_requestor_1_req_bits_store;
+ wire ptw_io_requestor_1_req_bits_fetch;
+ wire ptw_io_requestor_1_resp_valid;
+ wire ptw_io_requestor_1_resp_bits_error;
+ wire [19:0] ptw_io_requestor_1_resp_bits_pte_ppn;
+ wire [2:0] ptw_io_requestor_1_resp_bits_pte_reserved_for_software;
+ wire ptw_io_requestor_1_resp_bits_pte_d;
+ wire ptw_io_requestor_1_resp_bits_pte_r;
+ wire [3:0] ptw_io_requestor_1_resp_bits_pte_typ;
+ wire ptw_io_requestor_1_resp_bits_pte_v;
+ wire ptw_io_requestor_1_status_sd;
+ wire [30:0] ptw_io_requestor_1_status_zero2;
+ wire ptw_io_requestor_1_status_sd_rv32;
+ wire [8:0] ptw_io_requestor_1_status_zero1;
+ wire [4:0] ptw_io_requestor_1_status_vm;
+ wire ptw_io_requestor_1_status_mprv;
+ wire [1:0] ptw_io_requestor_1_status_xs;
+ wire [1:0] ptw_io_requestor_1_status_fs;
+ wire [1:0] ptw_io_requestor_1_status_prv3;
+ wire ptw_io_requestor_1_status_ie3;
+ wire [1:0] ptw_io_requestor_1_status_prv2;
+ wire ptw_io_requestor_1_status_ie2;
+ wire [1:0] ptw_io_requestor_1_status_prv1;
+ wire ptw_io_requestor_1_status_ie1;
+ wire [1:0] ptw_io_requestor_1_status_prv;
+ wire ptw_io_requestor_1_status_ie;
+ wire ptw_io_requestor_1_invalidate;
+ wire ptw_io_mem_req_ready;
+ wire ptw_io_mem_req_valid;
+ wire [39:0] ptw_io_mem_req_bits_addr;
+ wire [8:0] ptw_io_mem_req_bits_tag;
+ wire [4:0] ptw_io_mem_req_bits_cmd;
+ wire [2:0] ptw_io_mem_req_bits_typ;
+ wire ptw_io_mem_req_bits_kill;
+ wire ptw_io_mem_req_bits_phys;
+ wire [63:0] ptw_io_mem_req_bits_data;
+ wire ptw_io_mem_resp_valid;
+ wire [39:0] ptw_io_mem_resp_bits_addr;
+ wire [8:0] ptw_io_mem_resp_bits_tag;
+ wire [4:0] ptw_io_mem_resp_bits_cmd;
+ wire [2:0] ptw_io_mem_resp_bits_typ;
+ wire [63:0] ptw_io_mem_resp_bits_data;
+ wire ptw_io_mem_resp_bits_nack;
+ wire ptw_io_mem_resp_bits_replay;
+ wire ptw_io_mem_resp_bits_has_data;
+ wire [63:0] ptw_io_mem_resp_bits_data_word_bypass;
+ wire [63:0] ptw_io_mem_resp_bits_store_data;
+ wire ptw_io_mem_replay_next_valid;
+ wire [8:0] ptw_io_mem_replay_next_bits;
+ wire ptw_io_mem_xcpt_ma_ld;
+ wire ptw_io_mem_xcpt_ma_st;
+ wire ptw_io_mem_xcpt_pf_ld;
+ wire ptw_io_mem_xcpt_pf_st;
+ wire ptw_io_mem_invalidate_lr;
+ wire ptw_io_mem_ordered;
+ wire [31:0] ptw_io_dpath_ptbr;
+ wire ptw_io_dpath_invalidate;
+ wire ptw_io_dpath_status_sd;
+ wire [30:0] ptw_io_dpath_status_zero2;
+ wire ptw_io_dpath_status_sd_rv32;
+ wire [8:0] ptw_io_dpath_status_zero1;
+ wire [4:0] ptw_io_dpath_status_vm;
+ wire ptw_io_dpath_status_mprv;
+ wire [1:0] ptw_io_dpath_status_xs;
+ wire [1:0] ptw_io_dpath_status_fs;
+ wire [1:0] ptw_io_dpath_status_prv3;
+ wire ptw_io_dpath_status_ie3;
+ wire [1:0] ptw_io_dpath_status_prv2;
+ wire ptw_io_dpath_status_ie2;
+ wire [1:0] ptw_io_dpath_status_prv1;
+ wire ptw_io_dpath_status_ie1;
+ wire [1:0] ptw_io_dpath_status_prv;
+ wire ptw_io_dpath_status_ie;
+ wire dcArb_clk;
+ wire dcArb_reset;
+ wire dcArb_io_requestor_0_req_ready;
+ wire dcArb_io_requestor_0_req_valid;
+ wire [39:0] dcArb_io_requestor_0_req_bits_addr;
+ wire [8:0] dcArb_io_requestor_0_req_bits_tag;
+ wire [4:0] dcArb_io_requestor_0_req_bits_cmd;
+ wire [2:0] dcArb_io_requestor_0_req_bits_typ;
+ wire dcArb_io_requestor_0_req_bits_kill;
+ wire dcArb_io_requestor_0_req_bits_phys;
+ wire [63:0] dcArb_io_requestor_0_req_bits_data;
+ wire dcArb_io_requestor_0_resp_valid;
+ wire [39:0] dcArb_io_requestor_0_resp_bits_addr;
+ wire [8:0] dcArb_io_requestor_0_resp_bits_tag;
+ wire [4:0] dcArb_io_requestor_0_resp_bits_cmd;
+ wire [2:0] dcArb_io_requestor_0_resp_bits_typ;
+ wire [63:0] dcArb_io_requestor_0_resp_bits_data;
+ wire dcArb_io_requestor_0_resp_bits_nack;
+ wire dcArb_io_requestor_0_resp_bits_replay;
+ wire dcArb_io_requestor_0_resp_bits_has_data;
+ wire [63:0] dcArb_io_requestor_0_resp_bits_data_word_bypass;
+ wire [63:0] dcArb_io_requestor_0_resp_bits_store_data;
+ wire dcArb_io_requestor_0_replay_next_valid;
+ wire [8:0] dcArb_io_requestor_0_replay_next_bits;
+ wire dcArb_io_requestor_0_xcpt_ma_ld;
+ wire dcArb_io_requestor_0_xcpt_ma_st;
+ wire dcArb_io_requestor_0_xcpt_pf_ld;
+ wire dcArb_io_requestor_0_xcpt_pf_st;
+ wire dcArb_io_requestor_0_invalidate_lr;
+ wire dcArb_io_requestor_0_ordered;
+ wire dcArb_io_requestor_1_req_ready;
+ wire dcArb_io_requestor_1_req_valid;
+ wire [39:0] dcArb_io_requestor_1_req_bits_addr;
+ wire [8:0] dcArb_io_requestor_1_req_bits_tag;
+ wire [4:0] dcArb_io_requestor_1_req_bits_cmd;
+ wire [2:0] dcArb_io_requestor_1_req_bits_typ;
+ wire dcArb_io_requestor_1_req_bits_kill;
+ wire dcArb_io_requestor_1_req_bits_phys;
+ wire [63:0] dcArb_io_requestor_1_req_bits_data;
+ wire dcArb_io_requestor_1_resp_valid;
+ wire [39:0] dcArb_io_requestor_1_resp_bits_addr;
+ wire [8:0] dcArb_io_requestor_1_resp_bits_tag;
+ wire [4:0] dcArb_io_requestor_1_resp_bits_cmd;
+ wire [2:0] dcArb_io_requestor_1_resp_bits_typ;
+ wire [63:0] dcArb_io_requestor_1_resp_bits_data;
+ wire dcArb_io_requestor_1_resp_bits_nack;
+ wire dcArb_io_requestor_1_resp_bits_replay;
+ wire dcArb_io_requestor_1_resp_bits_has_data;
+ wire [63:0] dcArb_io_requestor_1_resp_bits_data_word_bypass;
+ wire [63:0] dcArb_io_requestor_1_resp_bits_store_data;
+ wire dcArb_io_requestor_1_replay_next_valid;
+ wire [8:0] dcArb_io_requestor_1_replay_next_bits;
+ wire dcArb_io_requestor_1_xcpt_ma_ld;
+ wire dcArb_io_requestor_1_xcpt_ma_st;
+ wire dcArb_io_requestor_1_xcpt_pf_ld;
+ wire dcArb_io_requestor_1_xcpt_pf_st;
+ wire dcArb_io_requestor_1_invalidate_lr;
+ wire dcArb_io_requestor_1_ordered;
+ wire dcArb_io_mem_req_ready;
+ wire dcArb_io_mem_req_valid;
+ wire [39:0] dcArb_io_mem_req_bits_addr;
+ wire [8:0] dcArb_io_mem_req_bits_tag;
+ wire [4:0] dcArb_io_mem_req_bits_cmd;
+ wire [2:0] dcArb_io_mem_req_bits_typ;
+ wire dcArb_io_mem_req_bits_kill;
+ wire dcArb_io_mem_req_bits_phys;
+ wire [63:0] dcArb_io_mem_req_bits_data;
+ wire dcArb_io_mem_resp_valid;
+ wire [39:0] dcArb_io_mem_resp_bits_addr;
+ wire [8:0] dcArb_io_mem_resp_bits_tag;
+ wire [4:0] dcArb_io_mem_resp_bits_cmd;
+ wire [2:0] dcArb_io_mem_resp_bits_typ;
+ wire [63:0] dcArb_io_mem_resp_bits_data;
+ wire dcArb_io_mem_resp_bits_nack;
+ wire dcArb_io_mem_resp_bits_replay;
+ wire dcArb_io_mem_resp_bits_has_data;
+ wire [63:0] dcArb_io_mem_resp_bits_data_word_bypass;
+ wire [63:0] dcArb_io_mem_resp_bits_store_data;
+ wire dcArb_io_mem_replay_next_valid;
+ wire [8:0] dcArb_io_mem_replay_next_bits;
+ wire dcArb_io_mem_xcpt_ma_ld;
+ wire dcArb_io_mem_xcpt_ma_st;
+ wire dcArb_io_mem_xcpt_pf_ld;
+ wire dcArb_io_mem_xcpt_pf_st;
+ wire dcArb_io_mem_invalidate_lr;
+ wire dcArb_io_mem_ordered;
+ wire T_3284_clk;
+ wire T_3284_reset;
+ wire [31:0] T_3284_io_inst;
+ wire [63:0] T_3284_io_fromint_data;
+ wire [2:0] T_3284_io_fcsr_rm;
+ wire T_3284_io_fcsr_flags_valid;
+ wire [4:0] T_3284_io_fcsr_flags_bits;
+ wire [63:0] T_3284_io_store_data;
+ wire [63:0] T_3284_io_toint_data;
+ wire T_3284_io_dmem_resp_val;
+ wire [2:0] T_3284_io_dmem_resp_type;
+ wire [4:0] T_3284_io_dmem_resp_tag;
+ wire [63:0] T_3284_io_dmem_resp_data;
+ wire T_3284_io_valid;
+ wire T_3284_io_fcsr_rdy;
+ wire T_3284_io_nack_mem;
+ wire T_3284_io_illegal_rm;
+ wire T_3284_io_killx;
+ wire T_3284_io_killm;
+ wire [4:0] T_3284_io_dec_cmd;
+ wire T_3284_io_dec_ldst;
+ wire T_3284_io_dec_wen;
+ wire T_3284_io_dec_ren1;
+ wire T_3284_io_dec_ren2;
+ wire T_3284_io_dec_ren3;
+ wire T_3284_io_dec_swap12;
+ wire T_3284_io_dec_swap23;
+ wire T_3284_io_dec_single;
+ wire T_3284_io_dec_fromint;
+ wire T_3284_io_dec_toint;
+ wire T_3284_io_dec_fastpipe;
+ wire T_3284_io_dec_fma;
+ wire T_3284_io_dec_div;
+ wire T_3284_io_dec_sqrt;
+ wire T_3284_io_dec_round;
+ wire T_3284_io_dec_wflags;
+ wire T_3284_io_sboard_set;
+ wire T_3284_io_sboard_clr;
+ wire [4:0] T_3284_io_sboard_clra;
+ wire T_3284_io_cp_req_ready;
+ wire T_3284_io_cp_req_valid;
+ wire [4:0] T_3284_io_cp_req_bits_cmd;
+ wire T_3284_io_cp_req_bits_ldst;
+ wire T_3284_io_cp_req_bits_wen;
+ wire T_3284_io_cp_req_bits_ren1;
+ wire T_3284_io_cp_req_bits_ren2;
+ wire T_3284_io_cp_req_bits_ren3;
+ wire T_3284_io_cp_req_bits_swap12;
+ wire T_3284_io_cp_req_bits_swap23;
+ wire T_3284_io_cp_req_bits_single;
+ wire T_3284_io_cp_req_bits_fromint;
+ wire T_3284_io_cp_req_bits_toint;
+ wire T_3284_io_cp_req_bits_fastpipe;
+ wire T_3284_io_cp_req_bits_fma;
+ wire T_3284_io_cp_req_bits_div;
+ wire T_3284_io_cp_req_bits_sqrt;
+ wire T_3284_io_cp_req_bits_round;
+ wire T_3284_io_cp_req_bits_wflags;
+ wire [2:0] T_3284_io_cp_req_bits_rm;
+ wire [1:0] T_3284_io_cp_req_bits_typ;
+ wire [64:0] T_3284_io_cp_req_bits_in1;
+ wire [64:0] T_3284_io_cp_req_bits_in2;
+ wire [64:0] T_3284_io_cp_req_bits_in3;
+ wire T_3284_io_cp_resp_ready;
+ wire T_3284_io_cp_resp_valid;
+ wire [64:0] T_3284_io_cp_resp_bits_data;
+ wire [4:0] T_3284_io_cp_resp_bits_exc;
+ reg GEN_0;
+ reg GEN_1;
+ reg [4:0] GEN_2;
+ reg [63:0] GEN_3;
+ reg GEN_4;
+ reg [39:0] GEN_5;
+ reg [8:0] GEN_6;
+ reg [4:0] GEN_7;
+ reg [2:0] GEN_8;
+ reg GEN_9;
+ reg GEN_10;
+ reg [63:0] GEN_11;
+ reg GEN_12;
+ reg GEN_13;
+ reg GEN_14;
+ reg GEN_15;
+ reg [25:0] GEN_16;
+ reg [1:0] GEN_17;
+ reg [1:0] GEN_18;
+ reg GEN_19;
+ reg [2:0] GEN_20;
+ reg [16:0] GEN_21;
+ reg [127:0] GEN_22;
+ reg GEN_23;
+ reg GEN_24;
+ reg [26:0] GEN_25;
+ reg [1:0] GEN_26;
+ reg GEN_27;
+ reg GEN_28;
+ reg GEN_29;
+ reg [26:0] GEN_30;
+ reg [1:0] GEN_31;
+ reg GEN_32;
+ reg GEN_33;
+ reg GEN_34;
+ reg [26:0] GEN_35;
+ reg [1:0] GEN_36;
+ reg GEN_37;
+ reg GEN_38;
+ reg GEN_39;
+ reg [4:0] GEN_40;
+ reg GEN_41;
+ reg GEN_42;
+ reg GEN_43;
+ reg GEN_44;
+ reg GEN_45;
+ reg GEN_46;
+ reg GEN_47;
+ reg GEN_48;
+ reg GEN_49;
+ reg GEN_50;
+ reg GEN_51;
+ reg GEN_52;
+ reg GEN_53;
+ reg GEN_54;
+ reg GEN_55;
+ reg GEN_56;
+ reg [2:0] GEN_57;
+ reg [1:0] GEN_58;
+ reg [64:0] GEN_59;
+ reg [64:0] GEN_60;
+ reg [64:0] GEN_61;
+ reg GEN_62;
+ reg GEN_63;
+ reg [1:0] GEN_64;
+ reg [2:0] GEN_65;
+ reg [31:0] GEN_66;
+ reg [31:0] GEN_67;
+ reg [31:0] GEN_68;
+ reg [1:0] GEN_69;
+ reg GEN_70;
+ reg [1:0] GEN_71;
+ reg [2:0] GEN_72;
+ reg [31:0] GEN_73;
+ reg [31:0] GEN_74;
+ reg [31:0] GEN_75;
+ reg [1:0] GEN_76;
+ Rocket core (
+ .clk(core_clk),
+ .reset(core_reset),
+ .io_host_reset(core_io_host_reset),
+ .io_host_id(core_io_host_id),
+ .io_host_csr_req_ready(core_io_host_csr_req_ready),
+ .io_host_csr_req_valid(core_io_host_csr_req_valid),
+ .io_host_csr_req_bits_rw(core_io_host_csr_req_bits_rw),
+ .io_host_csr_req_bits_addr(core_io_host_csr_req_bits_addr),
+ .io_host_csr_req_bits_data(core_io_host_csr_req_bits_data),
+ .io_host_csr_resp_ready(core_io_host_csr_resp_ready),
+ .io_host_csr_resp_valid(core_io_host_csr_resp_valid),
+ .io_host_csr_resp_bits(core_io_host_csr_resp_bits),
+ .io_host_debug_stats_csr(core_io_host_debug_stats_csr),
+ .io_imem_req_valid(core_io_imem_req_valid),
+ .io_imem_req_bits_pc(core_io_imem_req_bits_pc),
+ .io_imem_resp_ready(core_io_imem_resp_ready),
+ .io_imem_resp_valid(core_io_imem_resp_valid),
+ .io_imem_resp_bits_pc(core_io_imem_resp_bits_pc),
+ .io_imem_resp_bits_data_0(core_io_imem_resp_bits_data_0),
+ .io_imem_resp_bits_mask(core_io_imem_resp_bits_mask),
+ .io_imem_resp_bits_xcpt_if(core_io_imem_resp_bits_xcpt_if),
+ .io_imem_btb_resp_valid(core_io_imem_btb_resp_valid),
+ .io_imem_btb_resp_bits_taken(core_io_imem_btb_resp_bits_taken),
+ .io_imem_btb_resp_bits_mask(core_io_imem_btb_resp_bits_mask),
+ .io_imem_btb_resp_bits_bridx(core_io_imem_btb_resp_bits_bridx),
+ .io_imem_btb_resp_bits_target(core_io_imem_btb_resp_bits_target),
+ .io_imem_btb_resp_bits_entry(core_io_imem_btb_resp_bits_entry),
+ .io_imem_btb_resp_bits_bht_history(core_io_imem_btb_resp_bits_bht_history),
+ .io_imem_btb_resp_bits_bht_value(core_io_imem_btb_resp_bits_bht_value),
+ .io_imem_btb_update_valid(core_io_imem_btb_update_valid),
+ .io_imem_btb_update_bits_prediction_valid(core_io_imem_btb_update_bits_prediction_valid),
+ .io_imem_btb_update_bits_prediction_bits_taken(core_io_imem_btb_update_bits_prediction_bits_taken),
+ .io_imem_btb_update_bits_prediction_bits_mask(core_io_imem_btb_update_bits_prediction_bits_mask),
+ .io_imem_btb_update_bits_prediction_bits_bridx(core_io_imem_btb_update_bits_prediction_bits_bridx),
+ .io_imem_btb_update_bits_prediction_bits_target(core_io_imem_btb_update_bits_prediction_bits_target),
+ .io_imem_btb_update_bits_prediction_bits_entry(core_io_imem_btb_update_bits_prediction_bits_entry),
+ .io_imem_btb_update_bits_prediction_bits_bht_history(core_io_imem_btb_update_bits_prediction_bits_bht_history),
+ .io_imem_btb_update_bits_prediction_bits_bht_value(core_io_imem_btb_update_bits_prediction_bits_bht_value),
+ .io_imem_btb_update_bits_pc(core_io_imem_btb_update_bits_pc),
+ .io_imem_btb_update_bits_target(core_io_imem_btb_update_bits_target),
+ .io_imem_btb_update_bits_taken(core_io_imem_btb_update_bits_taken),
+ .io_imem_btb_update_bits_isJump(core_io_imem_btb_update_bits_isJump),
+ .io_imem_btb_update_bits_isReturn(core_io_imem_btb_update_bits_isReturn),
+ .io_imem_btb_update_bits_br_pc(core_io_imem_btb_update_bits_br_pc),
+ .io_imem_bht_update_valid(core_io_imem_bht_update_valid),
+ .io_imem_bht_update_bits_prediction_valid(core_io_imem_bht_update_bits_prediction_valid),
+ .io_imem_bht_update_bits_prediction_bits_taken(core_io_imem_bht_update_bits_prediction_bits_taken),
+ .io_imem_bht_update_bits_prediction_bits_mask(core_io_imem_bht_update_bits_prediction_bits_mask),
+ .io_imem_bht_update_bits_prediction_bits_bridx(core_io_imem_bht_update_bits_prediction_bits_bridx),
+ .io_imem_bht_update_bits_prediction_bits_target(core_io_imem_bht_update_bits_prediction_bits_target),
+ .io_imem_bht_update_bits_prediction_bits_entry(core_io_imem_bht_update_bits_prediction_bits_entry),
+ .io_imem_bht_update_bits_prediction_bits_bht_history(core_io_imem_bht_update_bits_prediction_bits_bht_history),
+ .io_imem_bht_update_bits_prediction_bits_bht_value(core_io_imem_bht_update_bits_prediction_bits_bht_value),
+ .io_imem_bht_update_bits_pc(core_io_imem_bht_update_bits_pc),
+ .io_imem_bht_update_bits_taken(core_io_imem_bht_update_bits_taken),
+ .io_imem_bht_update_bits_mispredict(core_io_imem_bht_update_bits_mispredict),
+ .io_imem_ras_update_valid(core_io_imem_ras_update_valid),
+ .io_imem_ras_update_bits_isCall(core_io_imem_ras_update_bits_isCall),
+ .io_imem_ras_update_bits_isReturn(core_io_imem_ras_update_bits_isReturn),
+ .io_imem_ras_update_bits_returnAddr(core_io_imem_ras_update_bits_returnAddr),
+ .io_imem_ras_update_bits_prediction_valid(core_io_imem_ras_update_bits_prediction_valid),
+ .io_imem_ras_update_bits_prediction_bits_taken(core_io_imem_ras_update_bits_prediction_bits_taken),
+ .io_imem_ras_update_bits_prediction_bits_mask(core_io_imem_ras_update_bits_prediction_bits_mask),
+ .io_imem_ras_update_bits_prediction_bits_bridx(core_io_imem_ras_update_bits_prediction_bits_bridx),
+ .io_imem_ras_update_bits_prediction_bits_target(core_io_imem_ras_update_bits_prediction_bits_target),
+ .io_imem_ras_update_bits_prediction_bits_entry(core_io_imem_ras_update_bits_prediction_bits_entry),
+ .io_imem_ras_update_bits_prediction_bits_bht_history(core_io_imem_ras_update_bits_prediction_bits_bht_history),
+ .io_imem_ras_update_bits_prediction_bits_bht_value(core_io_imem_ras_update_bits_prediction_bits_bht_value),
+ .io_imem_invalidate(core_io_imem_invalidate),
+ .io_imem_npc(core_io_imem_npc),
+ .io_dmem_req_ready(core_io_dmem_req_ready),
+ .io_dmem_req_valid(core_io_dmem_req_valid),
+ .io_dmem_req_bits_addr(core_io_dmem_req_bits_addr),
+ .io_dmem_req_bits_tag(core_io_dmem_req_bits_tag),
+ .io_dmem_req_bits_cmd(core_io_dmem_req_bits_cmd),
+ .io_dmem_req_bits_typ(core_io_dmem_req_bits_typ),
+ .io_dmem_req_bits_kill(core_io_dmem_req_bits_kill),
+ .io_dmem_req_bits_phys(core_io_dmem_req_bits_phys),
+ .io_dmem_req_bits_data(core_io_dmem_req_bits_data),
+ .io_dmem_resp_valid(core_io_dmem_resp_valid),
+ .io_dmem_resp_bits_addr(core_io_dmem_resp_bits_addr),
+ .io_dmem_resp_bits_tag(core_io_dmem_resp_bits_tag),
+ .io_dmem_resp_bits_cmd(core_io_dmem_resp_bits_cmd),
+ .io_dmem_resp_bits_typ(core_io_dmem_resp_bits_typ),
+ .io_dmem_resp_bits_data(core_io_dmem_resp_bits_data),
+ .io_dmem_resp_bits_nack(core_io_dmem_resp_bits_nack),
+ .io_dmem_resp_bits_replay(core_io_dmem_resp_bits_replay),
+ .io_dmem_resp_bits_has_data(core_io_dmem_resp_bits_has_data),
+ .io_dmem_resp_bits_data_word_bypass(core_io_dmem_resp_bits_data_word_bypass),
+ .io_dmem_resp_bits_store_data(core_io_dmem_resp_bits_store_data),
+ .io_dmem_replay_next_valid(core_io_dmem_replay_next_valid),
+ .io_dmem_replay_next_bits(core_io_dmem_replay_next_bits),
+ .io_dmem_xcpt_ma_ld(core_io_dmem_xcpt_ma_ld),
+ .io_dmem_xcpt_ma_st(core_io_dmem_xcpt_ma_st),
+ .io_dmem_xcpt_pf_ld(core_io_dmem_xcpt_pf_ld),
+ .io_dmem_xcpt_pf_st(core_io_dmem_xcpt_pf_st),
+ .io_dmem_invalidate_lr(core_io_dmem_invalidate_lr),
+ .io_dmem_ordered(core_io_dmem_ordered),
+ .io_ptw_ptbr(core_io_ptw_ptbr),
+ .io_ptw_invalidate(core_io_ptw_invalidate),
+ .io_ptw_status_sd(core_io_ptw_status_sd),
+ .io_ptw_status_zero2(core_io_ptw_status_zero2),
+ .io_ptw_status_sd_rv32(core_io_ptw_status_sd_rv32),
+ .io_ptw_status_zero1(core_io_ptw_status_zero1),
+ .io_ptw_status_vm(core_io_ptw_status_vm),
+ .io_ptw_status_mprv(core_io_ptw_status_mprv),
+ .io_ptw_status_xs(core_io_ptw_status_xs),
+ .io_ptw_status_fs(core_io_ptw_status_fs),
+ .io_ptw_status_prv3(core_io_ptw_status_prv3),
+ .io_ptw_status_ie3(core_io_ptw_status_ie3),
+ .io_ptw_status_prv2(core_io_ptw_status_prv2),
+ .io_ptw_status_ie2(core_io_ptw_status_ie2),
+ .io_ptw_status_prv1(core_io_ptw_status_prv1),
+ .io_ptw_status_ie1(core_io_ptw_status_ie1),
+ .io_ptw_status_prv(core_io_ptw_status_prv),
+ .io_ptw_status_ie(core_io_ptw_status_ie),
+ .io_fpu_inst(core_io_fpu_inst),
+ .io_fpu_fromint_data(core_io_fpu_fromint_data),
+ .io_fpu_fcsr_rm(core_io_fpu_fcsr_rm),
+ .io_fpu_fcsr_flags_valid(core_io_fpu_fcsr_flags_valid),
+ .io_fpu_fcsr_flags_bits(core_io_fpu_fcsr_flags_bits),
+ .io_fpu_store_data(core_io_fpu_store_data),
+ .io_fpu_toint_data(core_io_fpu_toint_data),
+ .io_fpu_dmem_resp_val(core_io_fpu_dmem_resp_val),
+ .io_fpu_dmem_resp_type(core_io_fpu_dmem_resp_type),
+ .io_fpu_dmem_resp_tag(core_io_fpu_dmem_resp_tag),
+ .io_fpu_dmem_resp_data(core_io_fpu_dmem_resp_data),
+ .io_fpu_valid(core_io_fpu_valid),
+ .io_fpu_fcsr_rdy(core_io_fpu_fcsr_rdy),
+ .io_fpu_nack_mem(core_io_fpu_nack_mem),
+ .io_fpu_illegal_rm(core_io_fpu_illegal_rm),
+ .io_fpu_killx(core_io_fpu_killx),
+ .io_fpu_killm(core_io_fpu_killm),
+ .io_fpu_dec_cmd(core_io_fpu_dec_cmd),
+ .io_fpu_dec_ldst(core_io_fpu_dec_ldst),
+ .io_fpu_dec_wen(core_io_fpu_dec_wen),
+ .io_fpu_dec_ren1(core_io_fpu_dec_ren1),
+ .io_fpu_dec_ren2(core_io_fpu_dec_ren2),
+ .io_fpu_dec_ren3(core_io_fpu_dec_ren3),
+ .io_fpu_dec_swap12(core_io_fpu_dec_swap12),
+ .io_fpu_dec_swap23(core_io_fpu_dec_swap23),
+ .io_fpu_dec_single(core_io_fpu_dec_single),
+ .io_fpu_dec_fromint(core_io_fpu_dec_fromint),
+ .io_fpu_dec_toint(core_io_fpu_dec_toint),
+ .io_fpu_dec_fastpipe(core_io_fpu_dec_fastpipe),
+ .io_fpu_dec_fma(core_io_fpu_dec_fma),
+ .io_fpu_dec_div(core_io_fpu_dec_div),
+ .io_fpu_dec_sqrt(core_io_fpu_dec_sqrt),
+ .io_fpu_dec_round(core_io_fpu_dec_round),
+ .io_fpu_dec_wflags(core_io_fpu_dec_wflags),
+ .io_fpu_sboard_set(core_io_fpu_sboard_set),
+ .io_fpu_sboard_clr(core_io_fpu_sboard_clr),
+ .io_fpu_sboard_clra(core_io_fpu_sboard_clra),
+ .io_fpu_cp_req_ready(core_io_fpu_cp_req_ready),
+ .io_fpu_cp_req_valid(core_io_fpu_cp_req_valid),
+ .io_fpu_cp_req_bits_cmd(core_io_fpu_cp_req_bits_cmd),
+ .io_fpu_cp_req_bits_ldst(core_io_fpu_cp_req_bits_ldst),
+ .io_fpu_cp_req_bits_wen(core_io_fpu_cp_req_bits_wen),
+ .io_fpu_cp_req_bits_ren1(core_io_fpu_cp_req_bits_ren1),
+ .io_fpu_cp_req_bits_ren2(core_io_fpu_cp_req_bits_ren2),
+ .io_fpu_cp_req_bits_ren3(core_io_fpu_cp_req_bits_ren3),
+ .io_fpu_cp_req_bits_swap12(core_io_fpu_cp_req_bits_swap12),
+ .io_fpu_cp_req_bits_swap23(core_io_fpu_cp_req_bits_swap23),
+ .io_fpu_cp_req_bits_single(core_io_fpu_cp_req_bits_single),
+ .io_fpu_cp_req_bits_fromint(core_io_fpu_cp_req_bits_fromint),
+ .io_fpu_cp_req_bits_toint(core_io_fpu_cp_req_bits_toint),
+ .io_fpu_cp_req_bits_fastpipe(core_io_fpu_cp_req_bits_fastpipe),
+ .io_fpu_cp_req_bits_fma(core_io_fpu_cp_req_bits_fma),
+ .io_fpu_cp_req_bits_div(core_io_fpu_cp_req_bits_div),
+ .io_fpu_cp_req_bits_sqrt(core_io_fpu_cp_req_bits_sqrt),
+ .io_fpu_cp_req_bits_round(core_io_fpu_cp_req_bits_round),
+ .io_fpu_cp_req_bits_wflags(core_io_fpu_cp_req_bits_wflags),
+ .io_fpu_cp_req_bits_rm(core_io_fpu_cp_req_bits_rm),
+ .io_fpu_cp_req_bits_typ(core_io_fpu_cp_req_bits_typ),
+ .io_fpu_cp_req_bits_in1(core_io_fpu_cp_req_bits_in1),
+ .io_fpu_cp_req_bits_in2(core_io_fpu_cp_req_bits_in2),
+ .io_fpu_cp_req_bits_in3(core_io_fpu_cp_req_bits_in3),
+ .io_fpu_cp_resp_ready(core_io_fpu_cp_resp_ready),
+ .io_fpu_cp_resp_valid(core_io_fpu_cp_resp_valid),
+ .io_fpu_cp_resp_bits_data(core_io_fpu_cp_resp_bits_data),
+ .io_fpu_cp_resp_bits_exc(core_io_fpu_cp_resp_bits_exc),
+ .io_rocc_cmd_ready(core_io_rocc_cmd_ready),
+ .io_rocc_cmd_valid(core_io_rocc_cmd_valid),
+ .io_rocc_cmd_bits_inst_funct(core_io_rocc_cmd_bits_inst_funct),
+ .io_rocc_cmd_bits_inst_rs2(core_io_rocc_cmd_bits_inst_rs2),
+ .io_rocc_cmd_bits_inst_rs1(core_io_rocc_cmd_bits_inst_rs1),
+ .io_rocc_cmd_bits_inst_xd(core_io_rocc_cmd_bits_inst_xd),
+ .io_rocc_cmd_bits_inst_xs1(core_io_rocc_cmd_bits_inst_xs1),
+ .io_rocc_cmd_bits_inst_xs2(core_io_rocc_cmd_bits_inst_xs2),
+ .io_rocc_cmd_bits_inst_rd(core_io_rocc_cmd_bits_inst_rd),
+ .io_rocc_cmd_bits_inst_opcode(core_io_rocc_cmd_bits_inst_opcode),
+ .io_rocc_cmd_bits_rs1(core_io_rocc_cmd_bits_rs1),
+ .io_rocc_cmd_bits_rs2(core_io_rocc_cmd_bits_rs2),
+ .io_rocc_resp_ready(core_io_rocc_resp_ready),
+ .io_rocc_resp_valid(core_io_rocc_resp_valid),
+ .io_rocc_resp_bits_rd(core_io_rocc_resp_bits_rd),
+ .io_rocc_resp_bits_data(core_io_rocc_resp_bits_data),
+ .io_rocc_mem_req_ready(core_io_rocc_mem_req_ready),
+ .io_rocc_mem_req_valid(core_io_rocc_mem_req_valid),
+ .io_rocc_mem_req_bits_addr(core_io_rocc_mem_req_bits_addr),
+ .io_rocc_mem_req_bits_tag(core_io_rocc_mem_req_bits_tag),
+ .io_rocc_mem_req_bits_cmd(core_io_rocc_mem_req_bits_cmd),
+ .io_rocc_mem_req_bits_typ(core_io_rocc_mem_req_bits_typ),
+ .io_rocc_mem_req_bits_kill(core_io_rocc_mem_req_bits_kill),
+ .io_rocc_mem_req_bits_phys(core_io_rocc_mem_req_bits_phys),
+ .io_rocc_mem_req_bits_data(core_io_rocc_mem_req_bits_data),
+ .io_rocc_mem_resp_valid(core_io_rocc_mem_resp_valid),
+ .io_rocc_mem_resp_bits_addr(core_io_rocc_mem_resp_bits_addr),
+ .io_rocc_mem_resp_bits_tag(core_io_rocc_mem_resp_bits_tag),
+ .io_rocc_mem_resp_bits_cmd(core_io_rocc_mem_resp_bits_cmd),
+ .io_rocc_mem_resp_bits_typ(core_io_rocc_mem_resp_bits_typ),
+ .io_rocc_mem_resp_bits_data(core_io_rocc_mem_resp_bits_data),
+ .io_rocc_mem_resp_bits_nack(core_io_rocc_mem_resp_bits_nack),
+ .io_rocc_mem_resp_bits_replay(core_io_rocc_mem_resp_bits_replay),
+ .io_rocc_mem_resp_bits_has_data(core_io_rocc_mem_resp_bits_has_data),
+ .io_rocc_mem_resp_bits_data_word_bypass(core_io_rocc_mem_resp_bits_data_word_bypass),
+ .io_rocc_mem_resp_bits_store_data(core_io_rocc_mem_resp_bits_store_data),
+ .io_rocc_mem_replay_next_valid(core_io_rocc_mem_replay_next_valid),
+ .io_rocc_mem_replay_next_bits(core_io_rocc_mem_replay_next_bits),
+ .io_rocc_mem_xcpt_ma_ld(core_io_rocc_mem_xcpt_ma_ld),
+ .io_rocc_mem_xcpt_ma_st(core_io_rocc_mem_xcpt_ma_st),
+ .io_rocc_mem_xcpt_pf_ld(core_io_rocc_mem_xcpt_pf_ld),
+ .io_rocc_mem_xcpt_pf_st(core_io_rocc_mem_xcpt_pf_st),
+ .io_rocc_mem_invalidate_lr(core_io_rocc_mem_invalidate_lr),
+ .io_rocc_mem_ordered(core_io_rocc_mem_ordered),
+ .io_rocc_busy(core_io_rocc_busy),
+ .io_rocc_s(core_io_rocc_s),
+ .io_rocc_interrupt(core_io_rocc_interrupt),
+ .io_rocc_autl_acquire_ready(core_io_rocc_autl_acquire_ready),
+ .io_rocc_autl_acquire_valid(core_io_rocc_autl_acquire_valid),
+ .io_rocc_autl_acquire_bits_addr_block(core_io_rocc_autl_acquire_bits_addr_block),
+ .io_rocc_autl_acquire_bits_client_xact_id(core_io_rocc_autl_acquire_bits_client_xact_id),
+ .io_rocc_autl_acquire_bits_addr_beat(core_io_rocc_autl_acquire_bits_addr_beat),
+ .io_rocc_autl_acquire_bits_is_builtin_type(core_io_rocc_autl_acquire_bits_is_builtin_type),
+ .io_rocc_autl_acquire_bits_a_type(core_io_rocc_autl_acquire_bits_a_type),
+ .io_rocc_autl_acquire_bits_union(core_io_rocc_autl_acquire_bits_union),
+ .io_rocc_autl_acquire_bits_data(core_io_rocc_autl_acquire_bits_data),
+ .io_rocc_autl_grant_ready(core_io_rocc_autl_grant_ready),
+ .io_rocc_autl_grant_valid(core_io_rocc_autl_grant_valid),
+ .io_rocc_autl_grant_bits_addr_beat(core_io_rocc_autl_grant_bits_addr_beat),
+ .io_rocc_autl_grant_bits_client_xact_id(core_io_rocc_autl_grant_bits_client_xact_id),
+ .io_rocc_autl_grant_bits_manager_xact_id(core_io_rocc_autl_grant_bits_manager_xact_id),
+ .io_rocc_autl_grant_bits_is_builtin_type(core_io_rocc_autl_grant_bits_is_builtin_type),
+ .io_rocc_autl_grant_bits_g_type(core_io_rocc_autl_grant_bits_g_type),
+ .io_rocc_autl_grant_bits_data(core_io_rocc_autl_grant_bits_data),
+ .io_rocc_iptw_req_ready(core_io_rocc_iptw_req_ready),
+ .io_rocc_iptw_req_valid(core_io_rocc_iptw_req_valid),
+ .io_rocc_iptw_req_bits_addr(core_io_rocc_iptw_req_bits_addr),
+ .io_rocc_iptw_req_bits_prv(core_io_rocc_iptw_req_bits_prv),
+ .io_rocc_iptw_req_bits_store(core_io_rocc_iptw_req_bits_store),
+ .io_rocc_iptw_req_bits_fetch(core_io_rocc_iptw_req_bits_fetch),
+ .io_rocc_iptw_resp_valid(core_io_rocc_iptw_resp_valid),
+ .io_rocc_iptw_resp_bits_error(core_io_rocc_iptw_resp_bits_error),
+ .io_rocc_iptw_resp_bits_pte_ppn(core_io_rocc_iptw_resp_bits_pte_ppn),
+ .io_rocc_iptw_resp_bits_pte_reserved_for_software(core_io_rocc_iptw_resp_bits_pte_reserved_for_software),
+ .io_rocc_iptw_resp_bits_pte_d(core_io_rocc_iptw_resp_bits_pte_d),
+ .io_rocc_iptw_resp_bits_pte_r(core_io_rocc_iptw_resp_bits_pte_r),
+ .io_rocc_iptw_resp_bits_pte_typ(core_io_rocc_iptw_resp_bits_pte_typ),
+ .io_rocc_iptw_resp_bits_pte_v(core_io_rocc_iptw_resp_bits_pte_v),
+ .io_rocc_iptw_status_sd(core_io_rocc_iptw_status_sd),
+ .io_rocc_iptw_status_zero2(core_io_rocc_iptw_status_zero2),
+ .io_rocc_iptw_status_sd_rv32(core_io_rocc_iptw_status_sd_rv32),
+ .io_rocc_iptw_status_zero1(core_io_rocc_iptw_status_zero1),
+ .io_rocc_iptw_status_vm(core_io_rocc_iptw_status_vm),
+ .io_rocc_iptw_status_mprv(core_io_rocc_iptw_status_mprv),
+ .io_rocc_iptw_status_xs(core_io_rocc_iptw_status_xs),
+ .io_rocc_iptw_status_fs(core_io_rocc_iptw_status_fs),
+ .io_rocc_iptw_status_prv3(core_io_rocc_iptw_status_prv3),
+ .io_rocc_iptw_status_ie3(core_io_rocc_iptw_status_ie3),
+ .io_rocc_iptw_status_prv2(core_io_rocc_iptw_status_prv2),
+ .io_rocc_iptw_status_ie2(core_io_rocc_iptw_status_ie2),
+ .io_rocc_iptw_status_prv1(core_io_rocc_iptw_status_prv1),
+ .io_rocc_iptw_status_ie1(core_io_rocc_iptw_status_ie1),
+ .io_rocc_iptw_status_prv(core_io_rocc_iptw_status_prv),
+ .io_rocc_iptw_status_ie(core_io_rocc_iptw_status_ie),
+ .io_rocc_iptw_invalidate(core_io_rocc_iptw_invalidate),
+ .io_rocc_dptw_req_ready(core_io_rocc_dptw_req_ready),
+ .io_rocc_dptw_req_valid(core_io_rocc_dptw_req_valid),
+ .io_rocc_dptw_req_bits_addr(core_io_rocc_dptw_req_bits_addr),
+ .io_rocc_dptw_req_bits_prv(core_io_rocc_dptw_req_bits_prv),
+ .io_rocc_dptw_req_bits_store(core_io_rocc_dptw_req_bits_store),
+ .io_rocc_dptw_req_bits_fetch(core_io_rocc_dptw_req_bits_fetch),
+ .io_rocc_dptw_resp_valid(core_io_rocc_dptw_resp_valid),
+ .io_rocc_dptw_resp_bits_error(core_io_rocc_dptw_resp_bits_error),
+ .io_rocc_dptw_resp_bits_pte_ppn(core_io_rocc_dptw_resp_bits_pte_ppn),
+ .io_rocc_dptw_resp_bits_pte_reserved_for_software(core_io_rocc_dptw_resp_bits_pte_reserved_for_software),
+ .io_rocc_dptw_resp_bits_pte_d(core_io_rocc_dptw_resp_bits_pte_d),
+ .io_rocc_dptw_resp_bits_pte_r(core_io_rocc_dptw_resp_bits_pte_r),
+ .io_rocc_dptw_resp_bits_pte_typ(core_io_rocc_dptw_resp_bits_pte_typ),
+ .io_rocc_dptw_resp_bits_pte_v(core_io_rocc_dptw_resp_bits_pte_v),
+ .io_rocc_dptw_status_sd(core_io_rocc_dptw_status_sd),
+ .io_rocc_dptw_status_zero2(core_io_rocc_dptw_status_zero2),
+ .io_rocc_dptw_status_sd_rv32(core_io_rocc_dptw_status_sd_rv32),
+ .io_rocc_dptw_status_zero1(core_io_rocc_dptw_status_zero1),
+ .io_rocc_dptw_status_vm(core_io_rocc_dptw_status_vm),
+ .io_rocc_dptw_status_mprv(core_io_rocc_dptw_status_mprv),
+ .io_rocc_dptw_status_xs(core_io_rocc_dptw_status_xs),
+ .io_rocc_dptw_status_fs(core_io_rocc_dptw_status_fs),
+ .io_rocc_dptw_status_prv3(core_io_rocc_dptw_status_prv3),
+ .io_rocc_dptw_status_ie3(core_io_rocc_dptw_status_ie3),
+ .io_rocc_dptw_status_prv2(core_io_rocc_dptw_status_prv2),
+ .io_rocc_dptw_status_ie2(core_io_rocc_dptw_status_ie2),
+ .io_rocc_dptw_status_prv1(core_io_rocc_dptw_status_prv1),
+ .io_rocc_dptw_status_ie1(core_io_rocc_dptw_status_ie1),
+ .io_rocc_dptw_status_prv(core_io_rocc_dptw_status_prv),
+ .io_rocc_dptw_status_ie(core_io_rocc_dptw_status_ie),
+ .io_rocc_dptw_invalidate(core_io_rocc_dptw_invalidate),
+ .io_rocc_pptw_req_ready(core_io_rocc_pptw_req_ready),
+ .io_rocc_pptw_req_valid(core_io_rocc_pptw_req_valid),
+ .io_rocc_pptw_req_bits_addr(core_io_rocc_pptw_req_bits_addr),
+ .io_rocc_pptw_req_bits_prv(core_io_rocc_pptw_req_bits_prv),
+ .io_rocc_pptw_req_bits_store(core_io_rocc_pptw_req_bits_store),
+ .io_rocc_pptw_req_bits_fetch(core_io_rocc_pptw_req_bits_fetch),
+ .io_rocc_pptw_resp_valid(core_io_rocc_pptw_resp_valid),
+ .io_rocc_pptw_resp_bits_error(core_io_rocc_pptw_resp_bits_error),
+ .io_rocc_pptw_resp_bits_pte_ppn(core_io_rocc_pptw_resp_bits_pte_ppn),
+ .io_rocc_pptw_resp_bits_pte_reserved_for_software(core_io_rocc_pptw_resp_bits_pte_reserved_for_software),
+ .io_rocc_pptw_resp_bits_pte_d(core_io_rocc_pptw_resp_bits_pte_d),
+ .io_rocc_pptw_resp_bits_pte_r(core_io_rocc_pptw_resp_bits_pte_r),
+ .io_rocc_pptw_resp_bits_pte_typ(core_io_rocc_pptw_resp_bits_pte_typ),
+ .io_rocc_pptw_resp_bits_pte_v(core_io_rocc_pptw_resp_bits_pte_v),
+ .io_rocc_pptw_status_sd(core_io_rocc_pptw_status_sd),
+ .io_rocc_pptw_status_zero2(core_io_rocc_pptw_status_zero2),
+ .io_rocc_pptw_status_sd_rv32(core_io_rocc_pptw_status_sd_rv32),
+ .io_rocc_pptw_status_zero1(core_io_rocc_pptw_status_zero1),
+ .io_rocc_pptw_status_vm(core_io_rocc_pptw_status_vm),
+ .io_rocc_pptw_status_mprv(core_io_rocc_pptw_status_mprv),
+ .io_rocc_pptw_status_xs(core_io_rocc_pptw_status_xs),
+ .io_rocc_pptw_status_fs(core_io_rocc_pptw_status_fs),
+ .io_rocc_pptw_status_prv3(core_io_rocc_pptw_status_prv3),
+ .io_rocc_pptw_status_ie3(core_io_rocc_pptw_status_ie3),
+ .io_rocc_pptw_status_prv2(core_io_rocc_pptw_status_prv2),
+ .io_rocc_pptw_status_ie2(core_io_rocc_pptw_status_ie2),
+ .io_rocc_pptw_status_prv1(core_io_rocc_pptw_status_prv1),
+ .io_rocc_pptw_status_ie1(core_io_rocc_pptw_status_ie1),
+ .io_rocc_pptw_status_prv(core_io_rocc_pptw_status_prv),
+ .io_rocc_pptw_status_ie(core_io_rocc_pptw_status_ie),
+ .io_rocc_pptw_invalidate(core_io_rocc_pptw_invalidate),
+ .io_rocc_fpu_req_ready(core_io_rocc_fpu_req_ready),
+ .io_rocc_fpu_req_valid(core_io_rocc_fpu_req_valid),
+ .io_rocc_fpu_req_bits_cmd(core_io_rocc_fpu_req_bits_cmd),
+ .io_rocc_fpu_req_bits_ldst(core_io_rocc_fpu_req_bits_ldst),
+ .io_rocc_fpu_req_bits_wen(core_io_rocc_fpu_req_bits_wen),
+ .io_rocc_fpu_req_bits_ren1(core_io_rocc_fpu_req_bits_ren1),
+ .io_rocc_fpu_req_bits_ren2(core_io_rocc_fpu_req_bits_ren2),
+ .io_rocc_fpu_req_bits_ren3(core_io_rocc_fpu_req_bits_ren3),
+ .io_rocc_fpu_req_bits_swap12(core_io_rocc_fpu_req_bits_swap12),
+ .io_rocc_fpu_req_bits_swap23(core_io_rocc_fpu_req_bits_swap23),
+ .io_rocc_fpu_req_bits_single(core_io_rocc_fpu_req_bits_single),
+ .io_rocc_fpu_req_bits_fromint(core_io_rocc_fpu_req_bits_fromint),
+ .io_rocc_fpu_req_bits_toint(core_io_rocc_fpu_req_bits_toint),
+ .io_rocc_fpu_req_bits_fastpipe(core_io_rocc_fpu_req_bits_fastpipe),
+ .io_rocc_fpu_req_bits_fma(core_io_rocc_fpu_req_bits_fma),
+ .io_rocc_fpu_req_bits_div(core_io_rocc_fpu_req_bits_div),
+ .io_rocc_fpu_req_bits_sqrt(core_io_rocc_fpu_req_bits_sqrt),
+ .io_rocc_fpu_req_bits_round(core_io_rocc_fpu_req_bits_round),
+ .io_rocc_fpu_req_bits_wflags(core_io_rocc_fpu_req_bits_wflags),
+ .io_rocc_fpu_req_bits_rm(core_io_rocc_fpu_req_bits_rm),
+ .io_rocc_fpu_req_bits_typ(core_io_rocc_fpu_req_bits_typ),
+ .io_rocc_fpu_req_bits_in1(core_io_rocc_fpu_req_bits_in1),
+ .io_rocc_fpu_req_bits_in2(core_io_rocc_fpu_req_bits_in2),
+ .io_rocc_fpu_req_bits_in3(core_io_rocc_fpu_req_bits_in3),
+ .io_rocc_fpu_resp_ready(core_io_rocc_fpu_resp_ready),
+ .io_rocc_fpu_resp_valid(core_io_rocc_fpu_resp_valid),
+ .io_rocc_fpu_resp_bits_data(core_io_rocc_fpu_resp_bits_data),
+ .io_rocc_fpu_resp_bits_exc(core_io_rocc_fpu_resp_bits_exc),
+ .io_rocc_exception(core_io_rocc_exception),
+ .io_rocc_dma_req_ready(core_io_rocc_dma_req_ready),
+ .io_rocc_dma_req_valid(core_io_rocc_dma_req_valid),
+ .io_rocc_dma_req_bits_client_xact_id(core_io_rocc_dma_req_bits_client_xact_id),
+ .io_rocc_dma_req_bits_cmd(core_io_rocc_dma_req_bits_cmd),
+ .io_rocc_dma_req_bits_source(core_io_rocc_dma_req_bits_source),
+ .io_rocc_dma_req_bits_dest(core_io_rocc_dma_req_bits_dest),
+ .io_rocc_dma_req_bits_length(core_io_rocc_dma_req_bits_length),
+ .io_rocc_dma_req_bits_size(core_io_rocc_dma_req_bits_size),
+ .io_rocc_dma_resp_ready(core_io_rocc_dma_resp_ready),
+ .io_rocc_dma_resp_valid(core_io_rocc_dma_resp_valid),
+ .io_rocc_dma_resp_bits_client_xact_id(core_io_rocc_dma_resp_bits_client_xact_id),
+ .io_rocc_dma_resp_bits_status(core_io_rocc_dma_resp_bits_status)
+ );
+ Frontend icache (
+ .clk(icache_clk),
+ .reset(icache_reset),
+ .io_cpu_req_valid(icache_io_cpu_req_valid),
+ .io_cpu_req_bits_pc(icache_io_cpu_req_bits_pc),
+ .io_cpu_resp_ready(icache_io_cpu_resp_ready),
+ .io_cpu_resp_valid(icache_io_cpu_resp_valid),
+ .io_cpu_resp_bits_pc(icache_io_cpu_resp_bits_pc),
+ .io_cpu_resp_bits_data_0(icache_io_cpu_resp_bits_data_0),
+ .io_cpu_resp_bits_mask(icache_io_cpu_resp_bits_mask),
+ .io_cpu_resp_bits_xcpt_if(icache_io_cpu_resp_bits_xcpt_if),
+ .io_cpu_btb_resp_valid(icache_io_cpu_btb_resp_valid),
+ .io_cpu_btb_resp_bits_taken(icache_io_cpu_btb_resp_bits_taken),
+ .io_cpu_btb_resp_bits_mask(icache_io_cpu_btb_resp_bits_mask),
+ .io_cpu_btb_resp_bits_bridx(icache_io_cpu_btb_resp_bits_bridx),
+ .io_cpu_btb_resp_bits_target(icache_io_cpu_btb_resp_bits_target),
+ .io_cpu_btb_resp_bits_entry(icache_io_cpu_btb_resp_bits_entry),
+ .io_cpu_btb_resp_bits_bht_history(icache_io_cpu_btb_resp_bits_bht_history),
+ .io_cpu_btb_resp_bits_bht_value(icache_io_cpu_btb_resp_bits_bht_value),
+ .io_cpu_btb_update_valid(icache_io_cpu_btb_update_valid),
+ .io_cpu_btb_update_bits_prediction_valid(icache_io_cpu_btb_update_bits_prediction_valid),
+ .io_cpu_btb_update_bits_prediction_bits_taken(icache_io_cpu_btb_update_bits_prediction_bits_taken),
+ .io_cpu_btb_update_bits_prediction_bits_mask(icache_io_cpu_btb_update_bits_prediction_bits_mask),
+ .io_cpu_btb_update_bits_prediction_bits_bridx(icache_io_cpu_btb_update_bits_prediction_bits_bridx),
+ .io_cpu_btb_update_bits_prediction_bits_target(icache_io_cpu_btb_update_bits_prediction_bits_target),
+ .io_cpu_btb_update_bits_prediction_bits_entry(icache_io_cpu_btb_update_bits_prediction_bits_entry),
+ .io_cpu_btb_update_bits_prediction_bits_bht_history(icache_io_cpu_btb_update_bits_prediction_bits_bht_history),
+ .io_cpu_btb_update_bits_prediction_bits_bht_value(icache_io_cpu_btb_update_bits_prediction_bits_bht_value),
+ .io_cpu_btb_update_bits_pc(icache_io_cpu_btb_update_bits_pc),
+ .io_cpu_btb_update_bits_target(icache_io_cpu_btb_update_bits_target),
+ .io_cpu_btb_update_bits_taken(icache_io_cpu_btb_update_bits_taken),
+ .io_cpu_btb_update_bits_isJump(icache_io_cpu_btb_update_bits_isJump),
+ .io_cpu_btb_update_bits_isReturn(icache_io_cpu_btb_update_bits_isReturn),
+ .io_cpu_btb_update_bits_br_pc(icache_io_cpu_btb_update_bits_br_pc),
+ .io_cpu_bht_update_valid(icache_io_cpu_bht_update_valid),
+ .io_cpu_bht_update_bits_prediction_valid(icache_io_cpu_bht_update_bits_prediction_valid),
+ .io_cpu_bht_update_bits_prediction_bits_taken(icache_io_cpu_bht_update_bits_prediction_bits_taken),
+ .io_cpu_bht_update_bits_prediction_bits_mask(icache_io_cpu_bht_update_bits_prediction_bits_mask),
+ .io_cpu_bht_update_bits_prediction_bits_bridx(icache_io_cpu_bht_update_bits_prediction_bits_bridx),
+ .io_cpu_bht_update_bits_prediction_bits_target(icache_io_cpu_bht_update_bits_prediction_bits_target),
+ .io_cpu_bht_update_bits_prediction_bits_entry(icache_io_cpu_bht_update_bits_prediction_bits_entry),
+ .io_cpu_bht_update_bits_prediction_bits_bht_history(icache_io_cpu_bht_update_bits_prediction_bits_bht_history),
+ .io_cpu_bht_update_bits_prediction_bits_bht_value(icache_io_cpu_bht_update_bits_prediction_bits_bht_value),
+ .io_cpu_bht_update_bits_pc(icache_io_cpu_bht_update_bits_pc),
+ .io_cpu_bht_update_bits_taken(icache_io_cpu_bht_update_bits_taken),
+ .io_cpu_bht_update_bits_mispredict(icache_io_cpu_bht_update_bits_mispredict),
+ .io_cpu_ras_update_valid(icache_io_cpu_ras_update_valid),
+ .io_cpu_ras_update_bits_isCall(icache_io_cpu_ras_update_bits_isCall),
+ .io_cpu_ras_update_bits_isReturn(icache_io_cpu_ras_update_bits_isReturn),
+ .io_cpu_ras_update_bits_returnAddr(icache_io_cpu_ras_update_bits_returnAddr),
+ .io_cpu_ras_update_bits_prediction_valid(icache_io_cpu_ras_update_bits_prediction_valid),
+ .io_cpu_ras_update_bits_prediction_bits_taken(icache_io_cpu_ras_update_bits_prediction_bits_taken),
+ .io_cpu_ras_update_bits_prediction_bits_mask(icache_io_cpu_ras_update_bits_prediction_bits_mask),
+ .io_cpu_ras_update_bits_prediction_bits_bridx(icache_io_cpu_ras_update_bits_prediction_bits_bridx),
+ .io_cpu_ras_update_bits_prediction_bits_target(icache_io_cpu_ras_update_bits_prediction_bits_target),
+ .io_cpu_ras_update_bits_prediction_bits_entry(icache_io_cpu_ras_update_bits_prediction_bits_entry),
+ .io_cpu_ras_update_bits_prediction_bits_bht_history(icache_io_cpu_ras_update_bits_prediction_bits_bht_history),
+ .io_cpu_ras_update_bits_prediction_bits_bht_value(icache_io_cpu_ras_update_bits_prediction_bits_bht_value),
+ .io_cpu_invalidate(icache_io_cpu_invalidate),
+ .io_cpu_npc(icache_io_cpu_npc),
+ .io_ptw_req_ready(icache_io_ptw_req_ready),
+ .io_ptw_req_valid(icache_io_ptw_req_valid),
+ .io_ptw_req_bits_addr(icache_io_ptw_req_bits_addr),
+ .io_ptw_req_bits_prv(icache_io_ptw_req_bits_prv),
+ .io_ptw_req_bits_store(icache_io_ptw_req_bits_store),
+ .io_ptw_req_bits_fetch(icache_io_ptw_req_bits_fetch),
+ .io_ptw_resp_valid(icache_io_ptw_resp_valid),
+ .io_ptw_resp_bits_error(icache_io_ptw_resp_bits_error),
+ .io_ptw_resp_bits_pte_ppn(icache_io_ptw_resp_bits_pte_ppn),
+ .io_ptw_resp_bits_pte_reserved_for_software(icache_io_ptw_resp_bits_pte_reserved_for_software),
+ .io_ptw_resp_bits_pte_d(icache_io_ptw_resp_bits_pte_d),
+ .io_ptw_resp_bits_pte_r(icache_io_ptw_resp_bits_pte_r),
+ .io_ptw_resp_bits_pte_typ(icache_io_ptw_resp_bits_pte_typ),
+ .io_ptw_resp_bits_pte_v(icache_io_ptw_resp_bits_pte_v),
+ .io_ptw_status_sd(icache_io_ptw_status_sd),
+ .io_ptw_status_zero2(icache_io_ptw_status_zero2),
+ .io_ptw_status_sd_rv32(icache_io_ptw_status_sd_rv32),
+ .io_ptw_status_zero1(icache_io_ptw_status_zero1),
+ .io_ptw_status_vm(icache_io_ptw_status_vm),
+ .io_ptw_status_mprv(icache_io_ptw_status_mprv),
+ .io_ptw_status_xs(icache_io_ptw_status_xs),
+ .io_ptw_status_fs(icache_io_ptw_status_fs),
+ .io_ptw_status_prv3(icache_io_ptw_status_prv3),
+ .io_ptw_status_ie3(icache_io_ptw_status_ie3),
+ .io_ptw_status_prv2(icache_io_ptw_status_prv2),
+ .io_ptw_status_ie2(icache_io_ptw_status_ie2),
+ .io_ptw_status_prv1(icache_io_ptw_status_prv1),
+ .io_ptw_status_ie1(icache_io_ptw_status_ie1),
+ .io_ptw_status_prv(icache_io_ptw_status_prv),
+ .io_ptw_status_ie(icache_io_ptw_status_ie),
+ .io_ptw_invalidate(icache_io_ptw_invalidate),
+ .io_mem_acquire_ready(icache_io_mem_acquire_ready),
+ .io_mem_acquire_valid(icache_io_mem_acquire_valid),
+ .io_mem_acquire_bits_addr_block(icache_io_mem_acquire_bits_addr_block),
+ .io_mem_acquire_bits_client_xact_id(icache_io_mem_acquire_bits_client_xact_id),
+ .io_mem_acquire_bits_addr_beat(icache_io_mem_acquire_bits_addr_beat),
+ .io_mem_acquire_bits_is_builtin_type(icache_io_mem_acquire_bits_is_builtin_type),
+ .io_mem_acquire_bits_a_type(icache_io_mem_acquire_bits_a_type),
+ .io_mem_acquire_bits_union(icache_io_mem_acquire_bits_union),
+ .io_mem_acquire_bits_data(icache_io_mem_acquire_bits_data),
+ .io_mem_grant_ready(icache_io_mem_grant_ready),
+ .io_mem_grant_valid(icache_io_mem_grant_valid),
+ .io_mem_grant_bits_addr_beat(icache_io_mem_grant_bits_addr_beat),
+ .io_mem_grant_bits_client_xact_id(icache_io_mem_grant_bits_client_xact_id),
+ .io_mem_grant_bits_manager_xact_id(icache_io_mem_grant_bits_manager_xact_id),
+ .io_mem_grant_bits_is_builtin_type(icache_io_mem_grant_bits_is_builtin_type),
+ .io_mem_grant_bits_g_type(icache_io_mem_grant_bits_g_type),
+ .io_mem_grant_bits_data(icache_io_mem_grant_bits_data)
+ );
+ HellaCache dcache (
+ .clk(dcache_clk),
+ .reset(dcache_reset),
+ .io_cpu_req_ready(dcache_io_cpu_req_ready),
+ .io_cpu_req_valid(dcache_io_cpu_req_valid),
+ .io_cpu_req_bits_addr(dcache_io_cpu_req_bits_addr),
+ .io_cpu_req_bits_tag(dcache_io_cpu_req_bits_tag),
+ .io_cpu_req_bits_cmd(dcache_io_cpu_req_bits_cmd),
+ .io_cpu_req_bits_typ(dcache_io_cpu_req_bits_typ),
+ .io_cpu_req_bits_kill(dcache_io_cpu_req_bits_kill),
+ .io_cpu_req_bits_phys(dcache_io_cpu_req_bits_phys),
+ .io_cpu_req_bits_data(dcache_io_cpu_req_bits_data),
+ .io_cpu_resp_valid(dcache_io_cpu_resp_valid),
+ .io_cpu_resp_bits_addr(dcache_io_cpu_resp_bits_addr),
+ .io_cpu_resp_bits_tag(dcache_io_cpu_resp_bits_tag),
+ .io_cpu_resp_bits_cmd(dcache_io_cpu_resp_bits_cmd),
+ .io_cpu_resp_bits_typ(dcache_io_cpu_resp_bits_typ),
+ .io_cpu_resp_bits_data(dcache_io_cpu_resp_bits_data),
+ .io_cpu_resp_bits_nack(dcache_io_cpu_resp_bits_nack),
+ .io_cpu_resp_bits_replay(dcache_io_cpu_resp_bits_replay),
+ .io_cpu_resp_bits_has_data(dcache_io_cpu_resp_bits_has_data),
+ .io_cpu_resp_bits_data_word_bypass(dcache_io_cpu_resp_bits_data_word_bypass),
+ .io_cpu_resp_bits_store_data(dcache_io_cpu_resp_bits_store_data),
+ .io_cpu_replay_next_valid(dcache_io_cpu_replay_next_valid),
+ .io_cpu_replay_next_bits(dcache_io_cpu_replay_next_bits),
+ .io_cpu_xcpt_ma_ld(dcache_io_cpu_xcpt_ma_ld),
+ .io_cpu_xcpt_ma_st(dcache_io_cpu_xcpt_ma_st),
+ .io_cpu_xcpt_pf_ld(dcache_io_cpu_xcpt_pf_ld),
+ .io_cpu_xcpt_pf_st(dcache_io_cpu_xcpt_pf_st),
+ .io_cpu_invalidate_lr(dcache_io_cpu_invalidate_lr),
+ .io_cpu_ordered(dcache_io_cpu_ordered),
+ .io_ptw_req_ready(dcache_io_ptw_req_ready),
+ .io_ptw_req_valid(dcache_io_ptw_req_valid),
+ .io_ptw_req_bits_addr(dcache_io_ptw_req_bits_addr),
+ .io_ptw_req_bits_prv(dcache_io_ptw_req_bits_prv),
+ .io_ptw_req_bits_store(dcache_io_ptw_req_bits_store),
+ .io_ptw_req_bits_fetch(dcache_io_ptw_req_bits_fetch),
+ .io_ptw_resp_valid(dcache_io_ptw_resp_valid),
+ .io_ptw_resp_bits_error(dcache_io_ptw_resp_bits_error),
+ .io_ptw_resp_bits_pte_ppn(dcache_io_ptw_resp_bits_pte_ppn),
+ .io_ptw_resp_bits_pte_reserved_for_software(dcache_io_ptw_resp_bits_pte_reserved_for_software),
+ .io_ptw_resp_bits_pte_d(dcache_io_ptw_resp_bits_pte_d),
+ .io_ptw_resp_bits_pte_r(dcache_io_ptw_resp_bits_pte_r),
+ .io_ptw_resp_bits_pte_typ(dcache_io_ptw_resp_bits_pte_typ),
+ .io_ptw_resp_bits_pte_v(dcache_io_ptw_resp_bits_pte_v),
+ .io_ptw_status_sd(dcache_io_ptw_status_sd),
+ .io_ptw_status_zero2(dcache_io_ptw_status_zero2),
+ .io_ptw_status_sd_rv32(dcache_io_ptw_status_sd_rv32),
+ .io_ptw_status_zero1(dcache_io_ptw_status_zero1),
+ .io_ptw_status_vm(dcache_io_ptw_status_vm),
+ .io_ptw_status_mprv(dcache_io_ptw_status_mprv),
+ .io_ptw_status_xs(dcache_io_ptw_status_xs),
+ .io_ptw_status_fs(dcache_io_ptw_status_fs),
+ .io_ptw_status_prv3(dcache_io_ptw_status_prv3),
+ .io_ptw_status_ie3(dcache_io_ptw_status_ie3),
+ .io_ptw_status_prv2(dcache_io_ptw_status_prv2),
+ .io_ptw_status_ie2(dcache_io_ptw_status_ie2),
+ .io_ptw_status_prv1(dcache_io_ptw_status_prv1),
+ .io_ptw_status_ie1(dcache_io_ptw_status_ie1),
+ .io_ptw_status_prv(dcache_io_ptw_status_prv),
+ .io_ptw_status_ie(dcache_io_ptw_status_ie),
+ .io_ptw_invalidate(dcache_io_ptw_invalidate),
+ .io_mem_acquire_ready(dcache_io_mem_acquire_ready),
+ .io_mem_acquire_valid(dcache_io_mem_acquire_valid),
+ .io_mem_acquire_bits_addr_block(dcache_io_mem_acquire_bits_addr_block),
+ .io_mem_acquire_bits_client_xact_id(dcache_io_mem_acquire_bits_client_xact_id),
+ .io_mem_acquire_bits_addr_beat(dcache_io_mem_acquire_bits_addr_beat),
+ .io_mem_acquire_bits_is_builtin_type(dcache_io_mem_acquire_bits_is_builtin_type),
+ .io_mem_acquire_bits_a_type(dcache_io_mem_acquire_bits_a_type),
+ .io_mem_acquire_bits_union(dcache_io_mem_acquire_bits_union),
+ .io_mem_acquire_bits_data(dcache_io_mem_acquire_bits_data),
+ .io_mem_grant_ready(dcache_io_mem_grant_ready),
+ .io_mem_grant_valid(dcache_io_mem_grant_valid),
+ .io_mem_grant_bits_addr_beat(dcache_io_mem_grant_bits_addr_beat),
+ .io_mem_grant_bits_client_xact_id(dcache_io_mem_grant_bits_client_xact_id),
+ .io_mem_grant_bits_manager_xact_id(dcache_io_mem_grant_bits_manager_xact_id),
+ .io_mem_grant_bits_is_builtin_type(dcache_io_mem_grant_bits_is_builtin_type),
+ .io_mem_grant_bits_g_type(dcache_io_mem_grant_bits_g_type),
+ .io_mem_grant_bits_data(dcache_io_mem_grant_bits_data),
+ .io_mem_probe_ready(dcache_io_mem_probe_ready),
+ .io_mem_probe_valid(dcache_io_mem_probe_valid),
+ .io_mem_probe_bits_addr_block(dcache_io_mem_probe_bits_addr_block),
+ .io_mem_probe_bits_p_type(dcache_io_mem_probe_bits_p_type),
+ .io_mem_release_ready(dcache_io_mem_release_ready),
+ .io_mem_release_valid(dcache_io_mem_release_valid),
+ .io_mem_release_bits_addr_beat(dcache_io_mem_release_bits_addr_beat),
+ .io_mem_release_bits_addr_block(dcache_io_mem_release_bits_addr_block),
+ .io_mem_release_bits_client_xact_id(dcache_io_mem_release_bits_client_xact_id),
+ .io_mem_release_bits_voluntary(dcache_io_mem_release_bits_voluntary),
+ .io_mem_release_bits_r_type(dcache_io_mem_release_bits_r_type),
+ .io_mem_release_bits_data(dcache_io_mem_release_bits_data)
+ );
+ PTW ptw (
+ .clk(ptw_clk),
+ .reset(ptw_reset),
+ .io_requestor_0_req_ready(ptw_io_requestor_0_req_ready),
+ .io_requestor_0_req_valid(ptw_io_requestor_0_req_valid),
+ .io_requestor_0_req_bits_addr(ptw_io_requestor_0_req_bits_addr),
+ .io_requestor_0_req_bits_prv(ptw_io_requestor_0_req_bits_prv),
+ .io_requestor_0_req_bits_store(ptw_io_requestor_0_req_bits_store),
+ .io_requestor_0_req_bits_fetch(ptw_io_requestor_0_req_bits_fetch),
+ .io_requestor_0_resp_valid(ptw_io_requestor_0_resp_valid),
+ .io_requestor_0_resp_bits_error(ptw_io_requestor_0_resp_bits_error),
+ .io_requestor_0_resp_bits_pte_ppn(ptw_io_requestor_0_resp_bits_pte_ppn),
+ .io_requestor_0_resp_bits_pte_reserved_for_software(ptw_io_requestor_0_resp_bits_pte_reserved_for_software),
+ .io_requestor_0_resp_bits_pte_d(ptw_io_requestor_0_resp_bits_pte_d),
+ .io_requestor_0_resp_bits_pte_r(ptw_io_requestor_0_resp_bits_pte_r),
+ .io_requestor_0_resp_bits_pte_typ(ptw_io_requestor_0_resp_bits_pte_typ),
+ .io_requestor_0_resp_bits_pte_v(ptw_io_requestor_0_resp_bits_pte_v),
+ .io_requestor_0_status_sd(ptw_io_requestor_0_status_sd),
+ .io_requestor_0_status_zero2(ptw_io_requestor_0_status_zero2),
+ .io_requestor_0_status_sd_rv32(ptw_io_requestor_0_status_sd_rv32),
+ .io_requestor_0_status_zero1(ptw_io_requestor_0_status_zero1),
+ .io_requestor_0_status_vm(ptw_io_requestor_0_status_vm),
+ .io_requestor_0_status_mprv(ptw_io_requestor_0_status_mprv),
+ .io_requestor_0_status_xs(ptw_io_requestor_0_status_xs),
+ .io_requestor_0_status_fs(ptw_io_requestor_0_status_fs),
+ .io_requestor_0_status_prv3(ptw_io_requestor_0_status_prv3),
+ .io_requestor_0_status_ie3(ptw_io_requestor_0_status_ie3),
+ .io_requestor_0_status_prv2(ptw_io_requestor_0_status_prv2),
+ .io_requestor_0_status_ie2(ptw_io_requestor_0_status_ie2),
+ .io_requestor_0_status_prv1(ptw_io_requestor_0_status_prv1),
+ .io_requestor_0_status_ie1(ptw_io_requestor_0_status_ie1),
+ .io_requestor_0_status_prv(ptw_io_requestor_0_status_prv),
+ .io_requestor_0_status_ie(ptw_io_requestor_0_status_ie),
+ .io_requestor_0_invalidate(ptw_io_requestor_0_invalidate),
+ .io_requestor_1_req_ready(ptw_io_requestor_1_req_ready),
+ .io_requestor_1_req_valid(ptw_io_requestor_1_req_valid),
+ .io_requestor_1_req_bits_addr(ptw_io_requestor_1_req_bits_addr),
+ .io_requestor_1_req_bits_prv(ptw_io_requestor_1_req_bits_prv),
+ .io_requestor_1_req_bits_store(ptw_io_requestor_1_req_bits_store),
+ .io_requestor_1_req_bits_fetch(ptw_io_requestor_1_req_bits_fetch),
+ .io_requestor_1_resp_valid(ptw_io_requestor_1_resp_valid),
+ .io_requestor_1_resp_bits_error(ptw_io_requestor_1_resp_bits_error),
+ .io_requestor_1_resp_bits_pte_ppn(ptw_io_requestor_1_resp_bits_pte_ppn),
+ .io_requestor_1_resp_bits_pte_reserved_for_software(ptw_io_requestor_1_resp_bits_pte_reserved_for_software),
+ .io_requestor_1_resp_bits_pte_d(ptw_io_requestor_1_resp_bits_pte_d),
+ .io_requestor_1_resp_bits_pte_r(ptw_io_requestor_1_resp_bits_pte_r),
+ .io_requestor_1_resp_bits_pte_typ(ptw_io_requestor_1_resp_bits_pte_typ),
+ .io_requestor_1_resp_bits_pte_v(ptw_io_requestor_1_resp_bits_pte_v),
+ .io_requestor_1_status_sd(ptw_io_requestor_1_status_sd),
+ .io_requestor_1_status_zero2(ptw_io_requestor_1_status_zero2),
+ .io_requestor_1_status_sd_rv32(ptw_io_requestor_1_status_sd_rv32),
+ .io_requestor_1_status_zero1(ptw_io_requestor_1_status_zero1),
+ .io_requestor_1_status_vm(ptw_io_requestor_1_status_vm),
+ .io_requestor_1_status_mprv(ptw_io_requestor_1_status_mprv),
+ .io_requestor_1_status_xs(ptw_io_requestor_1_status_xs),
+ .io_requestor_1_status_fs(ptw_io_requestor_1_status_fs),
+ .io_requestor_1_status_prv3(ptw_io_requestor_1_status_prv3),
+ .io_requestor_1_status_ie3(ptw_io_requestor_1_status_ie3),
+ .io_requestor_1_status_prv2(ptw_io_requestor_1_status_prv2),
+ .io_requestor_1_status_ie2(ptw_io_requestor_1_status_ie2),
+ .io_requestor_1_status_prv1(ptw_io_requestor_1_status_prv1),
+ .io_requestor_1_status_ie1(ptw_io_requestor_1_status_ie1),
+ .io_requestor_1_status_prv(ptw_io_requestor_1_status_prv),
+ .io_requestor_1_status_ie(ptw_io_requestor_1_status_ie),
+ .io_requestor_1_invalidate(ptw_io_requestor_1_invalidate),
+ .io_mem_req_ready(ptw_io_mem_req_ready),
+ .io_mem_req_valid(ptw_io_mem_req_valid),
+ .io_mem_req_bits_addr(ptw_io_mem_req_bits_addr),
+ .io_mem_req_bits_tag(ptw_io_mem_req_bits_tag),
+ .io_mem_req_bits_cmd(ptw_io_mem_req_bits_cmd),
+ .io_mem_req_bits_typ(ptw_io_mem_req_bits_typ),
+ .io_mem_req_bits_kill(ptw_io_mem_req_bits_kill),
+ .io_mem_req_bits_phys(ptw_io_mem_req_bits_phys),
+ .io_mem_req_bits_data(ptw_io_mem_req_bits_data),
+ .io_mem_resp_valid(ptw_io_mem_resp_valid),
+ .io_mem_resp_bits_addr(ptw_io_mem_resp_bits_addr),
+ .io_mem_resp_bits_tag(ptw_io_mem_resp_bits_tag),
+ .io_mem_resp_bits_cmd(ptw_io_mem_resp_bits_cmd),
+ .io_mem_resp_bits_typ(ptw_io_mem_resp_bits_typ),
+ .io_mem_resp_bits_data(ptw_io_mem_resp_bits_data),
+ .io_mem_resp_bits_nack(ptw_io_mem_resp_bits_nack),
+ .io_mem_resp_bits_replay(ptw_io_mem_resp_bits_replay),
+ .io_mem_resp_bits_has_data(ptw_io_mem_resp_bits_has_data),
+ .io_mem_resp_bits_data_word_bypass(ptw_io_mem_resp_bits_data_word_bypass),
+ .io_mem_resp_bits_store_data(ptw_io_mem_resp_bits_store_data),
+ .io_mem_replay_next_valid(ptw_io_mem_replay_next_valid),
+ .io_mem_replay_next_bits(ptw_io_mem_replay_next_bits),
+ .io_mem_xcpt_ma_ld(ptw_io_mem_xcpt_ma_ld),
+ .io_mem_xcpt_ma_st(ptw_io_mem_xcpt_ma_st),
+ .io_mem_xcpt_pf_ld(ptw_io_mem_xcpt_pf_ld),
+ .io_mem_xcpt_pf_st(ptw_io_mem_xcpt_pf_st),
+ .io_mem_invalidate_lr(ptw_io_mem_invalidate_lr),
+ .io_mem_ordered(ptw_io_mem_ordered),
+ .io_dpath_ptbr(ptw_io_dpath_ptbr),
+ .io_dpath_invalidate(ptw_io_dpath_invalidate),
+ .io_dpath_status_sd(ptw_io_dpath_status_sd),
+ .io_dpath_status_zero2(ptw_io_dpath_status_zero2),
+ .io_dpath_status_sd_rv32(ptw_io_dpath_status_sd_rv32),
+ .io_dpath_status_zero1(ptw_io_dpath_status_zero1),
+ .io_dpath_status_vm(ptw_io_dpath_status_vm),
+ .io_dpath_status_mprv(ptw_io_dpath_status_mprv),
+ .io_dpath_status_xs(ptw_io_dpath_status_xs),
+ .io_dpath_status_fs(ptw_io_dpath_status_fs),
+ .io_dpath_status_prv3(ptw_io_dpath_status_prv3),
+ .io_dpath_status_ie3(ptw_io_dpath_status_ie3),
+ .io_dpath_status_prv2(ptw_io_dpath_status_prv2),
+ .io_dpath_status_ie2(ptw_io_dpath_status_ie2),
+ .io_dpath_status_prv1(ptw_io_dpath_status_prv1),
+ .io_dpath_status_ie1(ptw_io_dpath_status_ie1),
+ .io_dpath_status_prv(ptw_io_dpath_status_prv),
+ .io_dpath_status_ie(ptw_io_dpath_status_ie)
+ );
+ HellaCacheArbiter dcArb (
+ .clk(dcArb_clk),
+ .reset(dcArb_reset),
+ .io_requestor_0_req_ready(dcArb_io_requestor_0_req_ready),
+ .io_requestor_0_req_valid(dcArb_io_requestor_0_req_valid),
+ .io_requestor_0_req_bits_addr(dcArb_io_requestor_0_req_bits_addr),
+ .io_requestor_0_req_bits_tag(dcArb_io_requestor_0_req_bits_tag),
+ .io_requestor_0_req_bits_cmd(dcArb_io_requestor_0_req_bits_cmd),
+ .io_requestor_0_req_bits_typ(dcArb_io_requestor_0_req_bits_typ),
+ .io_requestor_0_req_bits_kill(dcArb_io_requestor_0_req_bits_kill),
+ .io_requestor_0_req_bits_phys(dcArb_io_requestor_0_req_bits_phys),
+ .io_requestor_0_req_bits_data(dcArb_io_requestor_0_req_bits_data),
+ .io_requestor_0_resp_valid(dcArb_io_requestor_0_resp_valid),
+ .io_requestor_0_resp_bits_addr(dcArb_io_requestor_0_resp_bits_addr),
+ .io_requestor_0_resp_bits_tag(dcArb_io_requestor_0_resp_bits_tag),
+ .io_requestor_0_resp_bits_cmd(dcArb_io_requestor_0_resp_bits_cmd),
+ .io_requestor_0_resp_bits_typ(dcArb_io_requestor_0_resp_bits_typ),
+ .io_requestor_0_resp_bits_data(dcArb_io_requestor_0_resp_bits_data),
+ .io_requestor_0_resp_bits_nack(dcArb_io_requestor_0_resp_bits_nack),
+ .io_requestor_0_resp_bits_replay(dcArb_io_requestor_0_resp_bits_replay),
+ .io_requestor_0_resp_bits_has_data(dcArb_io_requestor_0_resp_bits_has_data),
+ .io_requestor_0_resp_bits_data_word_bypass(dcArb_io_requestor_0_resp_bits_data_word_bypass),
+ .io_requestor_0_resp_bits_store_data(dcArb_io_requestor_0_resp_bits_store_data),
+ .io_requestor_0_replay_next_valid(dcArb_io_requestor_0_replay_next_valid),
+ .io_requestor_0_replay_next_bits(dcArb_io_requestor_0_replay_next_bits),
+ .io_requestor_0_xcpt_ma_ld(dcArb_io_requestor_0_xcpt_ma_ld),
+ .io_requestor_0_xcpt_ma_st(dcArb_io_requestor_0_xcpt_ma_st),
+ .io_requestor_0_xcpt_pf_ld(dcArb_io_requestor_0_xcpt_pf_ld),
+ .io_requestor_0_xcpt_pf_st(dcArb_io_requestor_0_xcpt_pf_st),
+ .io_requestor_0_invalidate_lr(dcArb_io_requestor_0_invalidate_lr),
+ .io_requestor_0_ordered(dcArb_io_requestor_0_ordered),
+ .io_requestor_1_req_ready(dcArb_io_requestor_1_req_ready),
+ .io_requestor_1_req_valid(dcArb_io_requestor_1_req_valid),
+ .io_requestor_1_req_bits_addr(dcArb_io_requestor_1_req_bits_addr),
+ .io_requestor_1_req_bits_tag(dcArb_io_requestor_1_req_bits_tag),
+ .io_requestor_1_req_bits_cmd(dcArb_io_requestor_1_req_bits_cmd),
+ .io_requestor_1_req_bits_typ(dcArb_io_requestor_1_req_bits_typ),
+ .io_requestor_1_req_bits_kill(dcArb_io_requestor_1_req_bits_kill),
+ .io_requestor_1_req_bits_phys(dcArb_io_requestor_1_req_bits_phys),
+ .io_requestor_1_req_bits_data(dcArb_io_requestor_1_req_bits_data),
+ .io_requestor_1_resp_valid(dcArb_io_requestor_1_resp_valid),
+ .io_requestor_1_resp_bits_addr(dcArb_io_requestor_1_resp_bits_addr),
+ .io_requestor_1_resp_bits_tag(dcArb_io_requestor_1_resp_bits_tag),
+ .io_requestor_1_resp_bits_cmd(dcArb_io_requestor_1_resp_bits_cmd),
+ .io_requestor_1_resp_bits_typ(dcArb_io_requestor_1_resp_bits_typ),
+ .io_requestor_1_resp_bits_data(dcArb_io_requestor_1_resp_bits_data),
+ .io_requestor_1_resp_bits_nack(dcArb_io_requestor_1_resp_bits_nack),
+ .io_requestor_1_resp_bits_replay(dcArb_io_requestor_1_resp_bits_replay),
+ .io_requestor_1_resp_bits_has_data(dcArb_io_requestor_1_resp_bits_has_data),
+ .io_requestor_1_resp_bits_data_word_bypass(dcArb_io_requestor_1_resp_bits_data_word_bypass),
+ .io_requestor_1_resp_bits_store_data(dcArb_io_requestor_1_resp_bits_store_data),
+ .io_requestor_1_replay_next_valid(dcArb_io_requestor_1_replay_next_valid),
+ .io_requestor_1_replay_next_bits(dcArb_io_requestor_1_replay_next_bits),
+ .io_requestor_1_xcpt_ma_ld(dcArb_io_requestor_1_xcpt_ma_ld),
+ .io_requestor_1_xcpt_ma_st(dcArb_io_requestor_1_xcpt_ma_st),
+ .io_requestor_1_xcpt_pf_ld(dcArb_io_requestor_1_xcpt_pf_ld),
+ .io_requestor_1_xcpt_pf_st(dcArb_io_requestor_1_xcpt_pf_st),
+ .io_requestor_1_invalidate_lr(dcArb_io_requestor_1_invalidate_lr),
+ .io_requestor_1_ordered(dcArb_io_requestor_1_ordered),
+ .io_mem_req_ready(dcArb_io_mem_req_ready),
+ .io_mem_req_valid(dcArb_io_mem_req_valid),
+ .io_mem_req_bits_addr(dcArb_io_mem_req_bits_addr),
+ .io_mem_req_bits_tag(dcArb_io_mem_req_bits_tag),
+ .io_mem_req_bits_cmd(dcArb_io_mem_req_bits_cmd),
+ .io_mem_req_bits_typ(dcArb_io_mem_req_bits_typ),
+ .io_mem_req_bits_kill(dcArb_io_mem_req_bits_kill),
+ .io_mem_req_bits_phys(dcArb_io_mem_req_bits_phys),
+ .io_mem_req_bits_data(dcArb_io_mem_req_bits_data),
+ .io_mem_resp_valid(dcArb_io_mem_resp_valid),
+ .io_mem_resp_bits_addr(dcArb_io_mem_resp_bits_addr),
+ .io_mem_resp_bits_tag(dcArb_io_mem_resp_bits_tag),
+ .io_mem_resp_bits_cmd(dcArb_io_mem_resp_bits_cmd),
+ .io_mem_resp_bits_typ(dcArb_io_mem_resp_bits_typ),
+ .io_mem_resp_bits_data(dcArb_io_mem_resp_bits_data),
+ .io_mem_resp_bits_nack(dcArb_io_mem_resp_bits_nack),
+ .io_mem_resp_bits_replay(dcArb_io_mem_resp_bits_replay),
+ .io_mem_resp_bits_has_data(dcArb_io_mem_resp_bits_has_data),
+ .io_mem_resp_bits_data_word_bypass(dcArb_io_mem_resp_bits_data_word_bypass),
+ .io_mem_resp_bits_store_data(dcArb_io_mem_resp_bits_store_data),
+ .io_mem_replay_next_valid(dcArb_io_mem_replay_next_valid),
+ .io_mem_replay_next_bits(dcArb_io_mem_replay_next_bits),
+ .io_mem_xcpt_ma_ld(dcArb_io_mem_xcpt_ma_ld),
+ .io_mem_xcpt_ma_st(dcArb_io_mem_xcpt_ma_st),
+ .io_mem_xcpt_pf_ld(dcArb_io_mem_xcpt_pf_ld),
+ .io_mem_xcpt_pf_st(dcArb_io_mem_xcpt_pf_st),
+ .io_mem_invalidate_lr(dcArb_io_mem_invalidate_lr),
+ .io_mem_ordered(dcArb_io_mem_ordered)
+ );
+ FPU T_3284 (
+ .clk(T_3284_clk),
+ .reset(T_3284_reset),
+ .io_inst(T_3284_io_inst),
+ .io_fromint_data(T_3284_io_fromint_data),
+ .io_fcsr_rm(T_3284_io_fcsr_rm),
+ .io_fcsr_flags_valid(T_3284_io_fcsr_flags_valid),
+ .io_fcsr_flags_bits(T_3284_io_fcsr_flags_bits),
+ .io_store_data(T_3284_io_store_data),
+ .io_toint_data(T_3284_io_toint_data),
+ .io_dmem_resp_val(T_3284_io_dmem_resp_val),
+ .io_dmem_resp_type(T_3284_io_dmem_resp_type),
+ .io_dmem_resp_tag(T_3284_io_dmem_resp_tag),
+ .io_dmem_resp_data(T_3284_io_dmem_resp_data),
+ .io_valid(T_3284_io_valid),
+ .io_fcsr_rdy(T_3284_io_fcsr_rdy),
+ .io_nack_mem(T_3284_io_nack_mem),
+ .io_illegal_rm(T_3284_io_illegal_rm),
+ .io_killx(T_3284_io_killx),
+ .io_killm(T_3284_io_killm),
+ .io_dec_cmd(T_3284_io_dec_cmd),
+ .io_dec_ldst(T_3284_io_dec_ldst),
+ .io_dec_wen(T_3284_io_dec_wen),
+ .io_dec_ren1(T_3284_io_dec_ren1),
+ .io_dec_ren2(T_3284_io_dec_ren2),
+ .io_dec_ren3(T_3284_io_dec_ren3),
+ .io_dec_swap12(T_3284_io_dec_swap12),
+ .io_dec_swap23(T_3284_io_dec_swap23),
+ .io_dec_single(T_3284_io_dec_single),
+ .io_dec_fromint(T_3284_io_dec_fromint),
+ .io_dec_toint(T_3284_io_dec_toint),
+ .io_dec_fastpipe(T_3284_io_dec_fastpipe),
+ .io_dec_fma(T_3284_io_dec_fma),
+ .io_dec_div(T_3284_io_dec_div),
+ .io_dec_sqrt(T_3284_io_dec_sqrt),
+ .io_dec_round(T_3284_io_dec_round),
+ .io_dec_wflags(T_3284_io_dec_wflags),
+ .io_sboard_set(T_3284_io_sboard_set),
+ .io_sboard_clr(T_3284_io_sboard_clr),
+ .io_sboard_clra(T_3284_io_sboard_clra),
+ .io_cp_req_ready(T_3284_io_cp_req_ready),
+ .io_cp_req_valid(T_3284_io_cp_req_valid),
+ .io_cp_req_bits_cmd(T_3284_io_cp_req_bits_cmd),
+ .io_cp_req_bits_ldst(T_3284_io_cp_req_bits_ldst),
+ .io_cp_req_bits_wen(T_3284_io_cp_req_bits_wen),
+ .io_cp_req_bits_ren1(T_3284_io_cp_req_bits_ren1),
+ .io_cp_req_bits_ren2(T_3284_io_cp_req_bits_ren2),
+ .io_cp_req_bits_ren3(T_3284_io_cp_req_bits_ren3),
+ .io_cp_req_bits_swap12(T_3284_io_cp_req_bits_swap12),
+ .io_cp_req_bits_swap23(T_3284_io_cp_req_bits_swap23),
+ .io_cp_req_bits_single(T_3284_io_cp_req_bits_single),
+ .io_cp_req_bits_fromint(T_3284_io_cp_req_bits_fromint),
+ .io_cp_req_bits_toint(T_3284_io_cp_req_bits_toint),
+ .io_cp_req_bits_fastpipe(T_3284_io_cp_req_bits_fastpipe),
+ .io_cp_req_bits_fma(T_3284_io_cp_req_bits_fma),
+ .io_cp_req_bits_div(T_3284_io_cp_req_bits_div),
+ .io_cp_req_bits_sqrt(T_3284_io_cp_req_bits_sqrt),
+ .io_cp_req_bits_round(T_3284_io_cp_req_bits_round),
+ .io_cp_req_bits_wflags(T_3284_io_cp_req_bits_wflags),
+ .io_cp_req_bits_rm(T_3284_io_cp_req_bits_rm),
+ .io_cp_req_bits_typ(T_3284_io_cp_req_bits_typ),
+ .io_cp_req_bits_in1(T_3284_io_cp_req_bits_in1),
+ .io_cp_req_bits_in2(T_3284_io_cp_req_bits_in2),
+ .io_cp_req_bits_in3(T_3284_io_cp_req_bits_in3),
+ .io_cp_resp_ready(T_3284_io_cp_resp_ready),
+ .io_cp_resp_valid(T_3284_io_cp_resp_valid),
+ .io_cp_resp_bits_data(T_3284_io_cp_resp_bits_data),
+ .io_cp_resp_bits_exc(T_3284_io_cp_resp_bits_exc)
+ );
+ assign io_cached_0_acquire_valid = dcache_io_mem_acquire_valid;
+ assign io_cached_0_acquire_bits_addr_block = dcache_io_mem_acquire_bits_addr_block;
+ assign io_cached_0_acquire_bits_client_xact_id = dcache_io_mem_acquire_bits_client_xact_id;
+ assign io_cached_0_acquire_bits_addr_beat = dcache_io_mem_acquire_bits_addr_beat;
+ assign io_cached_0_acquire_bits_is_builtin_type = dcache_io_mem_acquire_bits_is_builtin_type;
+ assign io_cached_0_acquire_bits_a_type = dcache_io_mem_acquire_bits_a_type;
+ assign io_cached_0_acquire_bits_union = dcache_io_mem_acquire_bits_union;
+ assign io_cached_0_acquire_bits_data = dcache_io_mem_acquire_bits_data;
+ assign io_cached_0_grant_ready = dcache_io_mem_grant_ready;
+ assign io_cached_0_probe_ready = dcache_io_mem_probe_ready;
+ assign io_cached_0_release_valid = dcache_io_mem_release_valid;
+ assign io_cached_0_release_bits_addr_beat = dcache_io_mem_release_bits_addr_beat;
+ assign io_cached_0_release_bits_addr_block = dcache_io_mem_release_bits_addr_block;
+ assign io_cached_0_release_bits_client_xact_id = dcache_io_mem_release_bits_client_xact_id;
+ assign io_cached_0_release_bits_voluntary = dcache_io_mem_release_bits_voluntary;
+ assign io_cached_0_release_bits_r_type = dcache_io_mem_release_bits_r_type;
+ assign io_cached_0_release_bits_data = dcache_io_mem_release_bits_data;
+ assign io_uncached_0_acquire_valid = icache_io_mem_acquire_valid;
+ assign io_uncached_0_acquire_bits_addr_block = icache_io_mem_acquire_bits_addr_block;
+ assign io_uncached_0_acquire_bits_client_xact_id = icache_io_mem_acquire_bits_client_xact_id;
+ assign io_uncached_0_acquire_bits_addr_beat = icache_io_mem_acquire_bits_addr_beat;
+ assign io_uncached_0_acquire_bits_is_builtin_type = icache_io_mem_acquire_bits_is_builtin_type;
+ assign io_uncached_0_acquire_bits_a_type = icache_io_mem_acquire_bits_a_type;
+ assign io_uncached_0_acquire_bits_union = icache_io_mem_acquire_bits_union;
+ assign io_uncached_0_acquire_bits_data = icache_io_mem_acquire_bits_data;
+ assign io_uncached_0_grant_ready = icache_io_mem_grant_ready;
+ assign io_host_csr_req_ready = core_io_host_csr_req_ready;
+ assign io_host_csr_resp_valid = core_io_host_csr_resp_valid;
+ assign io_host_csr_resp_bits = core_io_host_csr_resp_bits;
+ assign io_host_debug_stats_csr = core_io_host_debug_stats_csr;
+ assign io_dma_req_valid = 1'h0;
+ assign io_dma_req_bits_client_xact_id = GEN_71;
+ assign io_dma_req_bits_cmd = GEN_72;
+ assign io_dma_req_bits_source = GEN_73;
+ assign io_dma_req_bits_dest = GEN_74;
+ assign io_dma_req_bits_length = GEN_75;
+ assign io_dma_req_bits_size = GEN_76;
+ assign io_dma_resp_ready = 1'h0;
+ assign core_clk = clk;
+ assign core_reset = reset;
+ assign core_io_host_reset = io_host_reset;
+ assign core_io_host_id = io_host_id;
+ assign core_io_host_csr_req_valid = io_host_csr_req_valid;
+ assign core_io_host_csr_req_bits_rw = io_host_csr_req_bits_rw;
+ assign core_io_host_csr_req_bits_addr = io_host_csr_req_bits_addr;
+ assign core_io_host_csr_req_bits_data = io_host_csr_req_bits_data;
+ assign core_io_host_csr_resp_ready = io_host_csr_resp_ready;
+ assign core_io_imem_resp_valid = icache_io_cpu_resp_valid;
+ assign core_io_imem_resp_bits_pc = icache_io_cpu_resp_bits_pc;
+ assign core_io_imem_resp_bits_data_0 = icache_io_cpu_resp_bits_data_0;
+ assign core_io_imem_resp_bits_mask = icache_io_cpu_resp_bits_mask;
+ assign core_io_imem_resp_bits_xcpt_if = icache_io_cpu_resp_bits_xcpt_if;
+ assign core_io_imem_btb_resp_valid = icache_io_cpu_btb_resp_valid;
+ assign core_io_imem_btb_resp_bits_taken = icache_io_cpu_btb_resp_bits_taken;
+ assign core_io_imem_btb_resp_bits_mask = icache_io_cpu_btb_resp_bits_mask;
+ assign core_io_imem_btb_resp_bits_bridx = icache_io_cpu_btb_resp_bits_bridx;
+ assign core_io_imem_btb_resp_bits_target = icache_io_cpu_btb_resp_bits_target;
+ assign core_io_imem_btb_resp_bits_entry = icache_io_cpu_btb_resp_bits_entry;
+ assign core_io_imem_btb_resp_bits_bht_history = icache_io_cpu_btb_resp_bits_bht_history;
+ assign core_io_imem_btb_resp_bits_bht_value = icache_io_cpu_btb_resp_bits_bht_value;
+ assign core_io_imem_npc = icache_io_cpu_npc;
+ assign core_io_dmem_req_ready = dcArb_io_requestor_1_req_ready;
+ assign core_io_dmem_resp_valid = dcArb_io_requestor_1_resp_valid;
+ assign core_io_dmem_resp_bits_addr = dcArb_io_requestor_1_resp_bits_addr;
+ assign core_io_dmem_resp_bits_tag = dcArb_io_requestor_1_resp_bits_tag;
+ assign core_io_dmem_resp_bits_cmd = dcArb_io_requestor_1_resp_bits_cmd;
+ assign core_io_dmem_resp_bits_typ = dcArb_io_requestor_1_resp_bits_typ;
+ assign core_io_dmem_resp_bits_data = dcArb_io_requestor_1_resp_bits_data;
+ assign core_io_dmem_resp_bits_nack = dcArb_io_requestor_1_resp_bits_nack;
+ assign core_io_dmem_resp_bits_replay = dcArb_io_requestor_1_resp_bits_replay;
+ assign core_io_dmem_resp_bits_has_data = dcArb_io_requestor_1_resp_bits_has_data;
+ assign core_io_dmem_resp_bits_data_word_bypass = dcArb_io_requestor_1_resp_bits_data_word_bypass;
+ assign core_io_dmem_resp_bits_store_data = dcArb_io_requestor_1_resp_bits_store_data;
+ assign core_io_dmem_replay_next_valid = dcArb_io_requestor_1_replay_next_valid;
+ assign core_io_dmem_replay_next_bits = dcArb_io_requestor_1_replay_next_bits;
+ assign core_io_dmem_xcpt_ma_ld = dcArb_io_requestor_1_xcpt_ma_ld;
+ assign core_io_dmem_xcpt_ma_st = dcArb_io_requestor_1_xcpt_ma_st;
+ assign core_io_dmem_xcpt_pf_ld = dcArb_io_requestor_1_xcpt_pf_ld;
+ assign core_io_dmem_xcpt_pf_st = dcArb_io_requestor_1_xcpt_pf_st;
+ assign core_io_dmem_ordered = dcArb_io_requestor_1_ordered;
+ assign core_io_fpu_fcsr_flags_valid = T_3284_io_fcsr_flags_valid;
+ assign core_io_fpu_fcsr_flags_bits = T_3284_io_fcsr_flags_bits;
+ assign core_io_fpu_store_data = T_3284_io_store_data;
+ assign core_io_fpu_toint_data = T_3284_io_toint_data;
+ assign core_io_fpu_fcsr_rdy = T_3284_io_fcsr_rdy;
+ assign core_io_fpu_nack_mem = T_3284_io_nack_mem;
+ assign core_io_fpu_illegal_rm = T_3284_io_illegal_rm;
+ assign core_io_fpu_dec_cmd = T_3284_io_dec_cmd;
+ assign core_io_fpu_dec_ldst = T_3284_io_dec_ldst;
+ assign core_io_fpu_dec_wen = T_3284_io_dec_wen;
+ assign core_io_fpu_dec_ren1 = T_3284_io_dec_ren1;
+ assign core_io_fpu_dec_ren2 = T_3284_io_dec_ren2;
+ assign core_io_fpu_dec_ren3 = T_3284_io_dec_ren3;
+ assign core_io_fpu_dec_swap12 = T_3284_io_dec_swap12;
+ assign core_io_fpu_dec_swap23 = T_3284_io_dec_swap23;
+ assign core_io_fpu_dec_single = T_3284_io_dec_single;
+ assign core_io_fpu_dec_fromint = T_3284_io_dec_fromint;
+ assign core_io_fpu_dec_toint = T_3284_io_dec_toint;
+ assign core_io_fpu_dec_fastpipe = T_3284_io_dec_fastpipe;
+ assign core_io_fpu_dec_fma = T_3284_io_dec_fma;
+ assign core_io_fpu_dec_div = T_3284_io_dec_div;
+ assign core_io_fpu_dec_sqrt = T_3284_io_dec_sqrt;
+ assign core_io_fpu_dec_round = T_3284_io_dec_round;
+ assign core_io_fpu_dec_wflags = T_3284_io_dec_wflags;
+ assign core_io_fpu_sboard_set = T_3284_io_sboard_set;
+ assign core_io_fpu_sboard_clr = T_3284_io_sboard_clr;
+ assign core_io_fpu_sboard_clra = T_3284_io_sboard_clra;
+ assign core_io_fpu_cp_req_ready = T_3284_io_cp_req_ready;
+ assign core_io_fpu_cp_resp_valid = T_3284_io_cp_resp_valid;
+ assign core_io_fpu_cp_resp_bits_data = T_3284_io_cp_resp_bits_data;
+ assign core_io_fpu_cp_resp_bits_exc = T_3284_io_cp_resp_bits_exc;
+ assign core_io_rocc_cmd_ready = GEN_0;
+ assign core_io_rocc_resp_valid = GEN_1;
+ assign core_io_rocc_resp_bits_rd = GEN_2;
+ assign core_io_rocc_resp_bits_data = GEN_3;
+ assign core_io_rocc_mem_req_valid = GEN_4;
+ assign core_io_rocc_mem_req_bits_addr = GEN_5;
+ assign core_io_rocc_mem_req_bits_tag = GEN_6;
+ assign core_io_rocc_mem_req_bits_cmd = GEN_7;
+ assign core_io_rocc_mem_req_bits_typ = GEN_8;
+ assign core_io_rocc_mem_req_bits_kill = GEN_9;
+ assign core_io_rocc_mem_req_bits_phys = GEN_10;
+ assign core_io_rocc_mem_req_bits_data = GEN_11;
+ assign core_io_rocc_mem_invalidate_lr = GEN_12;
+ assign core_io_rocc_busy = GEN_13;
+ assign core_io_rocc_interrupt = GEN_14;
+ assign core_io_rocc_autl_acquire_valid = GEN_15;
+ assign core_io_rocc_autl_acquire_bits_addr_block = GEN_16;
+ assign core_io_rocc_autl_acquire_bits_client_xact_id = GEN_17;
+ assign core_io_rocc_autl_acquire_bits_addr_beat = GEN_18;
+ assign core_io_rocc_autl_acquire_bits_is_builtin_type = GEN_19;
+ assign core_io_rocc_autl_acquire_bits_a_type = GEN_20;
+ assign core_io_rocc_autl_acquire_bits_union = GEN_21;
+ assign core_io_rocc_autl_acquire_bits_data = GEN_22;
+ assign core_io_rocc_autl_grant_ready = GEN_23;
+ assign core_io_rocc_iptw_req_valid = GEN_24;
+ assign core_io_rocc_iptw_req_bits_addr = GEN_25;
+ assign core_io_rocc_iptw_req_bits_prv = GEN_26;
+ assign core_io_rocc_iptw_req_bits_store = GEN_27;
+ assign core_io_rocc_iptw_req_bits_fetch = GEN_28;
+ assign core_io_rocc_dptw_req_valid = GEN_29;
+ assign core_io_rocc_dptw_req_bits_addr = GEN_30;
+ assign core_io_rocc_dptw_req_bits_prv = GEN_31;
+ assign core_io_rocc_dptw_req_bits_store = GEN_32;
+ assign core_io_rocc_dptw_req_bits_fetch = GEN_33;
+ assign core_io_rocc_pptw_req_valid = GEN_34;
+ assign core_io_rocc_pptw_req_bits_addr = GEN_35;
+ assign core_io_rocc_pptw_req_bits_prv = GEN_36;
+ assign core_io_rocc_pptw_req_bits_store = GEN_37;
+ assign core_io_rocc_pptw_req_bits_fetch = GEN_38;
+ assign core_io_rocc_fpu_req_valid = GEN_39;
+ assign core_io_rocc_fpu_req_bits_cmd = GEN_40;
+ assign core_io_rocc_fpu_req_bits_ldst = GEN_41;
+ assign core_io_rocc_fpu_req_bits_wen = GEN_42;
+ assign core_io_rocc_fpu_req_bits_ren1 = GEN_43;
+ assign core_io_rocc_fpu_req_bits_ren2 = GEN_44;
+ assign core_io_rocc_fpu_req_bits_ren3 = GEN_45;
+ assign core_io_rocc_fpu_req_bits_swap12 = GEN_46;
+ assign core_io_rocc_fpu_req_bits_swap23 = GEN_47;
+ assign core_io_rocc_fpu_req_bits_single = GEN_48;
+ assign core_io_rocc_fpu_req_bits_fromint = GEN_49;
+ assign core_io_rocc_fpu_req_bits_toint = GEN_50;
+ assign core_io_rocc_fpu_req_bits_fastpipe = GEN_51;
+ assign core_io_rocc_fpu_req_bits_fma = GEN_52;
+ assign core_io_rocc_fpu_req_bits_div = GEN_53;
+ assign core_io_rocc_fpu_req_bits_sqrt = GEN_54;
+ assign core_io_rocc_fpu_req_bits_round = GEN_55;
+ assign core_io_rocc_fpu_req_bits_wflags = GEN_56;
+ assign core_io_rocc_fpu_req_bits_rm = GEN_57;
+ assign core_io_rocc_fpu_req_bits_typ = GEN_58;
+ assign core_io_rocc_fpu_req_bits_in1 = GEN_59;
+ assign core_io_rocc_fpu_req_bits_in2 = GEN_60;
+ assign core_io_rocc_fpu_req_bits_in3 = GEN_61;
+ assign core_io_rocc_fpu_resp_ready = GEN_62;
+ assign core_io_rocc_dma_req_valid = GEN_63;
+ assign core_io_rocc_dma_req_bits_client_xact_id = GEN_64;
+ assign core_io_rocc_dma_req_bits_cmd = GEN_65;
+ assign core_io_rocc_dma_req_bits_source = GEN_66;
+ assign core_io_rocc_dma_req_bits_dest = GEN_67;
+ assign core_io_rocc_dma_req_bits_length = GEN_68;
+ assign core_io_rocc_dma_req_bits_size = GEN_69;
+ assign core_io_rocc_dma_resp_ready = GEN_70;
+ assign icache_clk = clk;
+ assign icache_reset = reset;
+ assign icache_io_cpu_req_valid = core_io_imem_req_valid;
+ assign icache_io_cpu_req_bits_pc = core_io_imem_req_bits_pc;
+ assign icache_io_cpu_resp_ready = core_io_imem_resp_ready;
+ assign icache_io_cpu_btb_update_valid = core_io_imem_btb_update_valid;
+ assign icache_io_cpu_btb_update_bits_prediction_valid = core_io_imem_btb_update_bits_prediction_valid;
+ assign icache_io_cpu_btb_update_bits_prediction_bits_taken = core_io_imem_btb_update_bits_prediction_bits_taken;
+ assign icache_io_cpu_btb_update_bits_prediction_bits_mask = core_io_imem_btb_update_bits_prediction_bits_mask;
+ assign icache_io_cpu_btb_update_bits_prediction_bits_bridx = core_io_imem_btb_update_bits_prediction_bits_bridx;
+ assign icache_io_cpu_btb_update_bits_prediction_bits_target = core_io_imem_btb_update_bits_prediction_bits_target;
+ assign icache_io_cpu_btb_update_bits_prediction_bits_entry = core_io_imem_btb_update_bits_prediction_bits_entry;
+ assign icache_io_cpu_btb_update_bits_prediction_bits_bht_history = core_io_imem_btb_update_bits_prediction_bits_bht_history;
+ assign icache_io_cpu_btb_update_bits_prediction_bits_bht_value = core_io_imem_btb_update_bits_prediction_bits_bht_value;
+ assign icache_io_cpu_btb_update_bits_pc = core_io_imem_btb_update_bits_pc;
+ assign icache_io_cpu_btb_update_bits_target = core_io_imem_btb_update_bits_target;
+ assign icache_io_cpu_btb_update_bits_taken = core_io_imem_btb_update_bits_taken;
+ assign icache_io_cpu_btb_update_bits_isJump = core_io_imem_btb_update_bits_isJump;
+ assign icache_io_cpu_btb_update_bits_isReturn = core_io_imem_btb_update_bits_isReturn;
+ assign icache_io_cpu_btb_update_bits_br_pc = core_io_imem_btb_update_bits_br_pc;
+ assign icache_io_cpu_bht_update_valid = core_io_imem_bht_update_valid;
+ assign icache_io_cpu_bht_update_bits_prediction_valid = core_io_imem_bht_update_bits_prediction_valid;
+ assign icache_io_cpu_bht_update_bits_prediction_bits_taken = core_io_imem_bht_update_bits_prediction_bits_taken;
+ assign icache_io_cpu_bht_update_bits_prediction_bits_mask = core_io_imem_bht_update_bits_prediction_bits_mask;
+ assign icache_io_cpu_bht_update_bits_prediction_bits_bridx = core_io_imem_bht_update_bits_prediction_bits_bridx;
+ assign icache_io_cpu_bht_update_bits_prediction_bits_target = core_io_imem_bht_update_bits_prediction_bits_target;
+ assign icache_io_cpu_bht_update_bits_prediction_bits_entry = core_io_imem_bht_update_bits_prediction_bits_entry;
+ assign icache_io_cpu_bht_update_bits_prediction_bits_bht_history = core_io_imem_bht_update_bits_prediction_bits_bht_history;
+ assign icache_io_cpu_bht_update_bits_prediction_bits_bht_value = core_io_imem_bht_update_bits_prediction_bits_bht_value;
+ assign icache_io_cpu_bht_update_bits_pc = core_io_imem_bht_update_bits_pc;
+ assign icache_io_cpu_bht_update_bits_taken = core_io_imem_bht_update_bits_taken;
+ assign icache_io_cpu_bht_update_bits_mispredict = core_io_imem_bht_update_bits_mispredict;
+ assign icache_io_cpu_ras_update_valid = core_io_imem_ras_update_valid;
+ assign icache_io_cpu_ras_update_bits_isCall = core_io_imem_ras_update_bits_isCall;
+ assign icache_io_cpu_ras_update_bits_isReturn = core_io_imem_ras_update_bits_isReturn;
+ assign icache_io_cpu_ras_update_bits_returnAddr = core_io_imem_ras_update_bits_returnAddr;
+ assign icache_io_cpu_ras_update_bits_prediction_valid = core_io_imem_ras_update_bits_prediction_valid;
+ assign icache_io_cpu_ras_update_bits_prediction_bits_taken = core_io_imem_ras_update_bits_prediction_bits_taken;
+ assign icache_io_cpu_ras_update_bits_prediction_bits_mask = core_io_imem_ras_update_bits_prediction_bits_mask;
+ assign icache_io_cpu_ras_update_bits_prediction_bits_bridx = core_io_imem_ras_update_bits_prediction_bits_bridx;
+ assign icache_io_cpu_ras_update_bits_prediction_bits_target = core_io_imem_ras_update_bits_prediction_bits_target;
+ assign icache_io_cpu_ras_update_bits_prediction_bits_entry = core_io_imem_ras_update_bits_prediction_bits_entry;
+ assign icache_io_cpu_ras_update_bits_prediction_bits_bht_history = core_io_imem_ras_update_bits_prediction_bits_bht_history;
+ assign icache_io_cpu_ras_update_bits_prediction_bits_bht_value = core_io_imem_ras_update_bits_prediction_bits_bht_value;
+ assign icache_io_cpu_invalidate = core_io_imem_invalidate;
+ assign icache_io_ptw_req_ready = ptw_io_requestor_0_req_ready;
+ assign icache_io_ptw_resp_valid = ptw_io_requestor_0_resp_valid;
+ assign icache_io_ptw_resp_bits_error = ptw_io_requestor_0_resp_bits_error;
+ assign icache_io_ptw_resp_bits_pte_ppn = ptw_io_requestor_0_resp_bits_pte_ppn;
+ assign icache_io_ptw_resp_bits_pte_reserved_for_software = ptw_io_requestor_0_resp_bits_pte_reserved_for_software;
+ assign icache_io_ptw_resp_bits_pte_d = ptw_io_requestor_0_resp_bits_pte_d;
+ assign icache_io_ptw_resp_bits_pte_r = ptw_io_requestor_0_resp_bits_pte_r;
+ assign icache_io_ptw_resp_bits_pte_typ = ptw_io_requestor_0_resp_bits_pte_typ;
+ assign icache_io_ptw_resp_bits_pte_v = ptw_io_requestor_0_resp_bits_pte_v;
+ assign icache_io_ptw_status_sd = ptw_io_requestor_0_status_sd;
+ assign icache_io_ptw_status_zero2 = ptw_io_requestor_0_status_zero2;
+ assign icache_io_ptw_status_sd_rv32 = ptw_io_requestor_0_status_sd_rv32;
+ assign icache_io_ptw_status_zero1 = ptw_io_requestor_0_status_zero1;
+ assign icache_io_ptw_status_vm = ptw_io_requestor_0_status_vm;
+ assign icache_io_ptw_status_mprv = ptw_io_requestor_0_status_mprv;
+ assign icache_io_ptw_status_xs = ptw_io_requestor_0_status_xs;
+ assign icache_io_ptw_status_fs = ptw_io_requestor_0_status_fs;
+ assign icache_io_ptw_status_prv3 = ptw_io_requestor_0_status_prv3;
+ assign icache_io_ptw_status_ie3 = ptw_io_requestor_0_status_ie3;
+ assign icache_io_ptw_status_prv2 = ptw_io_requestor_0_status_prv2;
+ assign icache_io_ptw_status_ie2 = ptw_io_requestor_0_status_ie2;
+ assign icache_io_ptw_status_prv1 = ptw_io_requestor_0_status_prv1;
+ assign icache_io_ptw_status_ie1 = ptw_io_requestor_0_status_ie1;
+ assign icache_io_ptw_status_prv = ptw_io_requestor_0_status_prv;
+ assign icache_io_ptw_status_ie = ptw_io_requestor_0_status_ie;
+ assign icache_io_ptw_invalidate = ptw_io_requestor_0_invalidate;
+ assign icache_io_mem_acquire_ready = io_uncached_0_acquire_ready;
+ assign icache_io_mem_grant_valid = io_uncached_0_grant_valid;
+ assign icache_io_mem_grant_bits_addr_beat = io_uncached_0_grant_bits_addr_beat;
+ assign icache_io_mem_grant_bits_client_xact_id = io_uncached_0_grant_bits_client_xact_id;
+ assign icache_io_mem_grant_bits_manager_xact_id = io_uncached_0_grant_bits_manager_xact_id;
+ assign icache_io_mem_grant_bits_is_builtin_type = io_uncached_0_grant_bits_is_builtin_type;
+ assign icache_io_mem_grant_bits_g_type = io_uncached_0_grant_bits_g_type;
+ assign icache_io_mem_grant_bits_data = io_uncached_0_grant_bits_data;
+ assign dcache_clk = clk;
+ assign dcache_reset = reset;
+ assign dcache_io_cpu_req_valid = dcArb_io_mem_req_valid;
+ assign dcache_io_cpu_req_bits_addr = dcArb_io_mem_req_bits_addr;
+ assign dcache_io_cpu_req_bits_tag = dcArb_io_mem_req_bits_tag;
+ assign dcache_io_cpu_req_bits_cmd = dcArb_io_mem_req_bits_cmd;
+ assign dcache_io_cpu_req_bits_typ = dcArb_io_mem_req_bits_typ;
+ assign dcache_io_cpu_req_bits_kill = dcArb_io_mem_req_bits_kill;
+ assign dcache_io_cpu_req_bits_phys = dcArb_io_mem_req_bits_phys;
+ assign dcache_io_cpu_req_bits_data = dcArb_io_mem_req_bits_data;
+ assign dcache_io_cpu_invalidate_lr = dcArb_io_mem_invalidate_lr;
+ assign dcache_io_ptw_req_ready = ptw_io_requestor_1_req_ready;
+ assign dcache_io_ptw_resp_valid = ptw_io_requestor_1_resp_valid;
+ assign dcache_io_ptw_resp_bits_error = ptw_io_requestor_1_resp_bits_error;
+ assign dcache_io_ptw_resp_bits_pte_ppn = ptw_io_requestor_1_resp_bits_pte_ppn;
+ assign dcache_io_ptw_resp_bits_pte_reserved_for_software = ptw_io_requestor_1_resp_bits_pte_reserved_for_software;
+ assign dcache_io_ptw_resp_bits_pte_d = ptw_io_requestor_1_resp_bits_pte_d;
+ assign dcache_io_ptw_resp_bits_pte_r = ptw_io_requestor_1_resp_bits_pte_r;
+ assign dcache_io_ptw_resp_bits_pte_typ = ptw_io_requestor_1_resp_bits_pte_typ;
+ assign dcache_io_ptw_resp_bits_pte_v = ptw_io_requestor_1_resp_bits_pte_v;
+ assign dcache_io_ptw_status_sd = ptw_io_requestor_1_status_sd;
+ assign dcache_io_ptw_status_zero2 = ptw_io_requestor_1_status_zero2;
+ assign dcache_io_ptw_status_sd_rv32 = ptw_io_requestor_1_status_sd_rv32;
+ assign dcache_io_ptw_status_zero1 = ptw_io_requestor_1_status_zero1;
+ assign dcache_io_ptw_status_vm = ptw_io_requestor_1_status_vm;
+ assign dcache_io_ptw_status_mprv = ptw_io_requestor_1_status_mprv;
+ assign dcache_io_ptw_status_xs = ptw_io_requestor_1_status_xs;
+ assign dcache_io_ptw_status_fs = ptw_io_requestor_1_status_fs;
+ assign dcache_io_ptw_status_prv3 = ptw_io_requestor_1_status_prv3;
+ assign dcache_io_ptw_status_ie3 = ptw_io_requestor_1_status_ie3;
+ assign dcache_io_ptw_status_prv2 = ptw_io_requestor_1_status_prv2;
+ assign dcache_io_ptw_status_ie2 = ptw_io_requestor_1_status_ie2;
+ assign dcache_io_ptw_status_prv1 = ptw_io_requestor_1_status_prv1;
+ assign dcache_io_ptw_status_ie1 = ptw_io_requestor_1_status_ie1;
+ assign dcache_io_ptw_status_prv = ptw_io_requestor_1_status_prv;
+ assign dcache_io_ptw_status_ie = ptw_io_requestor_1_status_ie;
+ assign dcache_io_ptw_invalidate = ptw_io_requestor_1_invalidate;
+ assign dcache_io_mem_acquire_ready = io_cached_0_acquire_ready;
+ assign dcache_io_mem_grant_valid = io_cached_0_grant_valid;
+ assign dcache_io_mem_grant_bits_addr_beat = io_cached_0_grant_bits_addr_beat;
+ assign dcache_io_mem_grant_bits_client_xact_id = io_cached_0_grant_bits_client_xact_id;
+ assign dcache_io_mem_grant_bits_manager_xact_id = io_cached_0_grant_bits_manager_xact_id;
+ assign dcache_io_mem_grant_bits_is_builtin_type = io_cached_0_grant_bits_is_builtin_type;
+ assign dcache_io_mem_grant_bits_g_type = io_cached_0_grant_bits_g_type;
+ assign dcache_io_mem_grant_bits_data = io_cached_0_grant_bits_data;
+ assign dcache_io_mem_probe_valid = io_cached_0_probe_valid;
+ assign dcache_io_mem_probe_bits_addr_block = io_cached_0_probe_bits_addr_block;
+ assign dcache_io_mem_probe_bits_p_type = io_cached_0_probe_bits_p_type;
+ assign dcache_io_mem_release_ready = io_cached_0_release_ready;
+ assign ptw_clk = clk;
+ assign ptw_reset = reset;
+ assign ptw_io_requestor_0_req_valid = icache_io_ptw_req_valid;
+ assign ptw_io_requestor_0_req_bits_addr = icache_io_ptw_req_bits_addr;
+ assign ptw_io_requestor_0_req_bits_prv = icache_io_ptw_req_bits_prv;
+ assign ptw_io_requestor_0_req_bits_store = icache_io_ptw_req_bits_store;
+ assign ptw_io_requestor_0_req_bits_fetch = icache_io_ptw_req_bits_fetch;
+ assign ptw_io_requestor_1_req_valid = dcache_io_ptw_req_valid;
+ assign ptw_io_requestor_1_req_bits_addr = dcache_io_ptw_req_bits_addr;
+ assign ptw_io_requestor_1_req_bits_prv = dcache_io_ptw_req_bits_prv;
+ assign ptw_io_requestor_1_req_bits_store = dcache_io_ptw_req_bits_store;
+ assign ptw_io_requestor_1_req_bits_fetch = dcache_io_ptw_req_bits_fetch;
+ assign ptw_io_mem_req_ready = dcArb_io_requestor_0_req_ready;
+ assign ptw_io_mem_resp_valid = dcArb_io_requestor_0_resp_valid;
+ assign ptw_io_mem_resp_bits_addr = dcArb_io_requestor_0_resp_bits_addr;
+ assign ptw_io_mem_resp_bits_tag = dcArb_io_requestor_0_resp_bits_tag;
+ assign ptw_io_mem_resp_bits_cmd = dcArb_io_requestor_0_resp_bits_cmd;
+ assign ptw_io_mem_resp_bits_typ = dcArb_io_requestor_0_resp_bits_typ;
+ assign ptw_io_mem_resp_bits_data = dcArb_io_requestor_0_resp_bits_data;
+ assign ptw_io_mem_resp_bits_nack = dcArb_io_requestor_0_resp_bits_nack;
+ assign ptw_io_mem_resp_bits_replay = dcArb_io_requestor_0_resp_bits_replay;
+ assign ptw_io_mem_resp_bits_has_data = dcArb_io_requestor_0_resp_bits_has_data;
+ assign ptw_io_mem_resp_bits_data_word_bypass = dcArb_io_requestor_0_resp_bits_data_word_bypass;
+ assign ptw_io_mem_resp_bits_store_data = dcArb_io_requestor_0_resp_bits_store_data;
+ assign ptw_io_mem_replay_next_valid = dcArb_io_requestor_0_replay_next_valid;
+ assign ptw_io_mem_replay_next_bits = dcArb_io_requestor_0_replay_next_bits;
+ assign ptw_io_mem_xcpt_ma_ld = dcArb_io_requestor_0_xcpt_ma_ld;
+ assign ptw_io_mem_xcpt_ma_st = dcArb_io_requestor_0_xcpt_ma_st;
+ assign ptw_io_mem_xcpt_pf_ld = dcArb_io_requestor_0_xcpt_pf_ld;
+ assign ptw_io_mem_xcpt_pf_st = dcArb_io_requestor_0_xcpt_pf_st;
+ assign ptw_io_mem_ordered = dcArb_io_requestor_0_ordered;
+ assign ptw_io_dpath_ptbr = core_io_ptw_ptbr;
+ assign ptw_io_dpath_invalidate = core_io_ptw_invalidate;
+ assign ptw_io_dpath_status_sd = core_io_ptw_status_sd;
+ assign ptw_io_dpath_status_zero2 = core_io_ptw_status_zero2;
+ assign ptw_io_dpath_status_sd_rv32 = core_io_ptw_status_sd_rv32;
+ assign ptw_io_dpath_status_zero1 = core_io_ptw_status_zero1;
+ assign ptw_io_dpath_status_vm = core_io_ptw_status_vm;
+ assign ptw_io_dpath_status_mprv = core_io_ptw_status_mprv;
+ assign ptw_io_dpath_status_xs = core_io_ptw_status_xs;
+ assign ptw_io_dpath_status_fs = core_io_ptw_status_fs;
+ assign ptw_io_dpath_status_prv3 = core_io_ptw_status_prv3;
+ assign ptw_io_dpath_status_ie3 = core_io_ptw_status_ie3;
+ assign ptw_io_dpath_status_prv2 = core_io_ptw_status_prv2;
+ assign ptw_io_dpath_status_ie2 = core_io_ptw_status_ie2;
+ assign ptw_io_dpath_status_prv1 = core_io_ptw_status_prv1;
+ assign ptw_io_dpath_status_ie1 = core_io_ptw_status_ie1;
+ assign ptw_io_dpath_status_prv = core_io_ptw_status_prv;
+ assign ptw_io_dpath_status_ie = core_io_ptw_status_ie;
+ assign dcArb_clk = clk;
+ assign dcArb_reset = reset;
+ assign dcArb_io_requestor_0_req_valid = ptw_io_mem_req_valid;
+ assign dcArb_io_requestor_0_req_bits_addr = ptw_io_mem_req_bits_addr;
+ assign dcArb_io_requestor_0_req_bits_tag = ptw_io_mem_req_bits_tag;
+ assign dcArb_io_requestor_0_req_bits_cmd = ptw_io_mem_req_bits_cmd;
+ assign dcArb_io_requestor_0_req_bits_typ = ptw_io_mem_req_bits_typ;
+ assign dcArb_io_requestor_0_req_bits_kill = ptw_io_mem_req_bits_kill;
+ assign dcArb_io_requestor_0_req_bits_phys = ptw_io_mem_req_bits_phys;
+ assign dcArb_io_requestor_0_req_bits_data = ptw_io_mem_req_bits_data;
+ assign dcArb_io_requestor_0_invalidate_lr = ptw_io_mem_invalidate_lr;
+ assign dcArb_io_requestor_1_req_valid = core_io_dmem_req_valid;
+ assign dcArb_io_requestor_1_req_bits_addr = core_io_dmem_req_bits_addr;
+ assign dcArb_io_requestor_1_req_bits_tag = core_io_dmem_req_bits_tag;
+ assign dcArb_io_requestor_1_req_bits_cmd = core_io_dmem_req_bits_cmd;
+ assign dcArb_io_requestor_1_req_bits_typ = core_io_dmem_req_bits_typ;
+ assign dcArb_io_requestor_1_req_bits_kill = core_io_dmem_req_bits_kill;
+ assign dcArb_io_requestor_1_req_bits_phys = core_io_dmem_req_bits_phys;
+ assign dcArb_io_requestor_1_req_bits_data = core_io_dmem_req_bits_data;
+ assign dcArb_io_requestor_1_invalidate_lr = core_io_dmem_invalidate_lr;
+ assign dcArb_io_mem_req_ready = dcache_io_cpu_req_ready;
+ assign dcArb_io_mem_resp_valid = dcache_io_cpu_resp_valid;
+ assign dcArb_io_mem_resp_bits_addr = dcache_io_cpu_resp_bits_addr;
+ assign dcArb_io_mem_resp_bits_tag = dcache_io_cpu_resp_bits_tag;
+ assign dcArb_io_mem_resp_bits_cmd = dcache_io_cpu_resp_bits_cmd;
+ assign dcArb_io_mem_resp_bits_typ = dcache_io_cpu_resp_bits_typ;
+ assign dcArb_io_mem_resp_bits_data = dcache_io_cpu_resp_bits_data;
+ assign dcArb_io_mem_resp_bits_nack = dcache_io_cpu_resp_bits_nack;
+ assign dcArb_io_mem_resp_bits_replay = dcache_io_cpu_resp_bits_replay;
+ assign dcArb_io_mem_resp_bits_has_data = dcache_io_cpu_resp_bits_has_data;
+ assign dcArb_io_mem_resp_bits_data_word_bypass = dcache_io_cpu_resp_bits_data_word_bypass;
+ assign dcArb_io_mem_resp_bits_store_data = dcache_io_cpu_resp_bits_store_data;
+ assign dcArb_io_mem_replay_next_valid = dcache_io_cpu_replay_next_valid;
+ assign dcArb_io_mem_replay_next_bits = dcache_io_cpu_replay_next_bits;
+ assign dcArb_io_mem_xcpt_ma_ld = dcache_io_cpu_xcpt_ma_ld;
+ assign dcArb_io_mem_xcpt_ma_st = dcache_io_cpu_xcpt_ma_st;
+ assign dcArb_io_mem_xcpt_pf_ld = dcache_io_cpu_xcpt_pf_ld;
+ assign dcArb_io_mem_xcpt_pf_st = dcache_io_cpu_xcpt_pf_st;
+ assign dcArb_io_mem_ordered = dcache_io_cpu_ordered;
+ assign T_3284_clk = clk;
+ assign T_3284_reset = reset;
+ assign T_3284_io_inst = core_io_fpu_inst;
+ assign T_3284_io_fromint_data = core_io_fpu_fromint_data;
+ assign T_3284_io_fcsr_rm = core_io_fpu_fcsr_rm;
+ assign T_3284_io_dmem_resp_val = core_io_fpu_dmem_resp_val;
+ assign T_3284_io_dmem_resp_type = core_io_fpu_dmem_resp_type;
+ assign T_3284_io_dmem_resp_tag = core_io_fpu_dmem_resp_tag;
+ assign T_3284_io_dmem_resp_data = core_io_fpu_dmem_resp_data;
+ assign T_3284_io_valid = core_io_fpu_valid;
+ assign T_3284_io_killx = core_io_fpu_killx;
+ assign T_3284_io_killm = core_io_fpu_killm;
+ assign T_3284_io_cp_req_valid = 1'h0;
+ assign T_3284_io_cp_req_bits_cmd = core_io_fpu_cp_req_bits_cmd;
+ assign T_3284_io_cp_req_bits_ldst = core_io_fpu_cp_req_bits_ldst;
+ assign T_3284_io_cp_req_bits_wen = core_io_fpu_cp_req_bits_wen;
+ assign T_3284_io_cp_req_bits_ren1 = core_io_fpu_cp_req_bits_ren1;
+ assign T_3284_io_cp_req_bits_ren2 = core_io_fpu_cp_req_bits_ren2;
+ assign T_3284_io_cp_req_bits_ren3 = core_io_fpu_cp_req_bits_ren3;
+ assign T_3284_io_cp_req_bits_swap12 = core_io_fpu_cp_req_bits_swap12;
+ assign T_3284_io_cp_req_bits_swap23 = core_io_fpu_cp_req_bits_swap23;
+ assign T_3284_io_cp_req_bits_single = core_io_fpu_cp_req_bits_single;
+ assign T_3284_io_cp_req_bits_fromint = core_io_fpu_cp_req_bits_fromint;
+ assign T_3284_io_cp_req_bits_toint = core_io_fpu_cp_req_bits_toint;
+ assign T_3284_io_cp_req_bits_fastpipe = core_io_fpu_cp_req_bits_fastpipe;
+ assign T_3284_io_cp_req_bits_fma = core_io_fpu_cp_req_bits_fma;
+ assign T_3284_io_cp_req_bits_div = core_io_fpu_cp_req_bits_div;
+ assign T_3284_io_cp_req_bits_sqrt = core_io_fpu_cp_req_bits_sqrt;
+ assign T_3284_io_cp_req_bits_round = core_io_fpu_cp_req_bits_round;
+ assign T_3284_io_cp_req_bits_wflags = core_io_fpu_cp_req_bits_wflags;
+ assign T_3284_io_cp_req_bits_rm = core_io_fpu_cp_req_bits_rm;
+ assign T_3284_io_cp_req_bits_typ = core_io_fpu_cp_req_bits_typ;
+ assign T_3284_io_cp_req_bits_in1 = core_io_fpu_cp_req_bits_in1;
+ assign T_3284_io_cp_req_bits_in2 = core_io_fpu_cp_req_bits_in2;
+ assign T_3284_io_cp_req_bits_in3 = core_io_fpu_cp_req_bits_in3;
+ assign T_3284_io_cp_resp_ready = 1'h0;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ GEN_0 = {1{$random}};
+ GEN_1 = {1{$random}};
+ GEN_2 = {1{$random}};
+ GEN_3 = {2{$random}};
+ GEN_4 = {1{$random}};
+ GEN_5 = {2{$random}};
+ GEN_6 = {1{$random}};
+ GEN_7 = {1{$random}};
+ GEN_8 = {1{$random}};
+ GEN_9 = {1{$random}};
+ GEN_10 = {1{$random}};
+ GEN_11 = {2{$random}};
+ GEN_12 = {1{$random}};
+ GEN_13 = {1{$random}};
+ GEN_14 = {1{$random}};
+ GEN_15 = {1{$random}};
+ GEN_16 = {1{$random}};
+ GEN_17 = {1{$random}};
+ GEN_18 = {1{$random}};
+ GEN_19 = {1{$random}};
+ GEN_20 = {1{$random}};
+ GEN_21 = {1{$random}};
+ GEN_22 = {4{$random}};
+ GEN_23 = {1{$random}};
+ GEN_24 = {1{$random}};
+ GEN_25 = {1{$random}};
+ GEN_26 = {1{$random}};
+ GEN_27 = {1{$random}};
+ GEN_28 = {1{$random}};
+ GEN_29 = {1{$random}};
+ GEN_30 = {1{$random}};
+ GEN_31 = {1{$random}};
+ GEN_32 = {1{$random}};
+ GEN_33 = {1{$random}};
+ GEN_34 = {1{$random}};
+ GEN_35 = {1{$random}};
+ GEN_36 = {1{$random}};
+ GEN_37 = {1{$random}};
+ GEN_38 = {1{$random}};
+ GEN_39 = {1{$random}};
+ GEN_40 = {1{$random}};
+ GEN_41 = {1{$random}};
+ GEN_42 = {1{$random}};
+ GEN_43 = {1{$random}};
+ GEN_44 = {1{$random}};
+ GEN_45 = {1{$random}};
+ GEN_46 = {1{$random}};
+ GEN_47 = {1{$random}};
+ GEN_48 = {1{$random}};
+ GEN_49 = {1{$random}};
+ GEN_50 = {1{$random}};
+ GEN_51 = {1{$random}};
+ GEN_52 = {1{$random}};
+ GEN_53 = {1{$random}};
+ GEN_54 = {1{$random}};
+ GEN_55 = {1{$random}};
+ GEN_56 = {1{$random}};
+ GEN_57 = {1{$random}};
+ GEN_58 = {1{$random}};
+ GEN_59 = {3{$random}};
+ GEN_60 = {3{$random}};
+ GEN_61 = {3{$random}};
+ GEN_62 = {1{$random}};
+ GEN_63 = {1{$random}};
+ GEN_64 = {1{$random}};
+ GEN_65 = {1{$random}};
+ GEN_66 = {1{$random}};
+ GEN_67 = {1{$random}};
+ GEN_68 = {1{$random}};
+ GEN_69 = {1{$random}};
+ GEN_70 = {1{$random}};
+ GEN_71 = {1{$random}};
+ GEN_72 = {1{$random}};
+ GEN_73 = {1{$random}};
+ GEN_74 = {1{$random}};
+ GEN_75 = {1{$random}};
+ GEN_76 = {1{$random}};
+ end
+`endif
+endmodule
+module Queue_124(
+ input clk,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input io_enq_bits_rw,
+ input [11:0] io_enq_bits_addr,
+ input [63:0] io_enq_bits_data,
+ input io_deq_ready,
+ output io_deq_valid,
+ output io_deq_bits_rw,
+ output [11:0] io_deq_bits_addr,
+ output [63:0] io_deq_bits_data,
+ output [1:0] io_count
+);
+ reg ram_rw [0:1];
+ wire ram_rw_T_107_data;
+ wire ram_rw_T_107_addr;
+ wire ram_rw_T_107_en;
+ wire ram_rw_T_107_clk;
+ wire ram_rw_T_74_data;
+ wire ram_rw_T_74_addr;
+ wire ram_rw_T_74_mask;
+ wire ram_rw_T_74_en;
+ wire ram_rw_T_74_clk;
+ reg [11:0] ram_addr [0:1];
+ wire [11:0] ram_addr_T_107_data;
+ wire ram_addr_T_107_addr;
+ wire ram_addr_T_107_en;
+ wire ram_addr_T_107_clk;
+ wire [11:0] ram_addr_T_74_data;
+ wire ram_addr_T_74_addr;
+ wire ram_addr_T_74_mask;
+ wire ram_addr_T_74_en;
+ wire ram_addr_T_74_clk;
+ reg [63:0] ram_data [0:1];
+ wire [63:0] ram_data_T_107_data;
+ wire ram_data_T_107_addr;
+ wire ram_data_T_107_en;
+ wire ram_data_T_107_clk;
+ wire [63:0] ram_data_T_74_data;
+ wire ram_data_T_74_addr;
+ wire ram_data_T_74_mask;
+ wire ram_data_T_74_en;
+ wire ram_data_T_74_clk;
+ reg T_53;
+ reg T_55;
+ reg maybe_full;
+ wire ptr_match;
+ wire T_60;
+ wire empty;
+ wire full;
+ wire maybe_flow;
+ wire do_flow;
+ wire T_66;
+ wire T_68;
+ wire do_enq;
+ wire T_70;
+ wire T_72;
+ wire do_deq;
+ wire T_79;
+ wire T_81;
+ wire [1:0] T_84;
+ wire T_85;
+ wire T_86;
+ wire T_88;
+ wire T_90;
+ wire [1:0] T_93;
+ wire T_94;
+ wire T_95;
+ wire T_96;
+ wire T_98;
+ wire T_100;
+ wire T_101;
+ wire T_103;
+ wire T_105;
+ wire T_106;
+ wire T_111_rw;
+ wire [11:0] T_111_addr;
+ wire [63:0] T_111_data;
+ wire [1:0] T_115;
+ wire ptr_diff;
+ wire T_117;
+ wire [1:0] T_118;
+ assign io_enq_ready = T_106;
+ assign io_deq_valid = T_101;
+ assign io_deq_bits_rw = T_111_rw;
+ assign io_deq_bits_addr = T_111_addr;
+ assign io_deq_bits_data = T_111_data;
+ assign io_count = T_118;
+ assign ram_rw_T_107_addr = T_55;
+ assign ram_rw_T_107_en = 1'h1;
+ assign ram_rw_T_107_clk = clk;
+ assign ram_rw_T_107_data = ram_rw[ram_rw_T_107_addr];
+ assign ram_rw_T_74_data = io_enq_bits_rw;
+ assign ram_rw_T_74_addr = T_53;
+ assign ram_rw_T_74_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_rw_T_74_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_rw_T_74_clk = clk;
+ assign ram_addr_T_107_addr = T_55;
+ assign ram_addr_T_107_en = 1'h1;
+ assign ram_addr_T_107_clk = clk;
+ assign ram_addr_T_107_data = ram_addr[ram_addr_T_107_addr];
+ assign ram_addr_T_74_data = io_enq_bits_addr;
+ assign ram_addr_T_74_addr = T_53;
+ assign ram_addr_T_74_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_addr_T_74_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_addr_T_74_clk = clk;
+ assign ram_data_T_107_addr = T_55;
+ assign ram_data_T_107_en = 1'h1;
+ assign ram_data_T_107_clk = clk;
+ assign ram_data_T_107_data = ram_data[ram_data_T_107_addr];
+ assign ram_data_T_74_data = io_enq_bits_data;
+ assign ram_data_T_74_addr = T_53;
+ assign ram_data_T_74_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_data_T_74_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_data_T_74_clk = clk;
+ assign ptr_match = T_53 == T_55;
+ assign T_60 = maybe_full == 1'h0;
+ assign empty = ptr_match & T_60;
+ assign full = ptr_match & maybe_full;
+ assign maybe_flow = 1'h0 & empty;
+ assign do_flow = maybe_flow & io_deq_ready;
+ assign T_66 = io_enq_ready & io_enq_valid;
+ assign T_68 = do_flow == 1'h0;
+ assign do_enq = T_66 & T_68;
+ assign T_70 = io_deq_ready & io_deq_valid;
+ assign T_72 = do_flow == 1'h0;
+ assign do_deq = T_70 & T_72;
+ assign T_79 = T_53 == 1'h1;
+ assign T_81 = 1'h0 & T_79;
+ assign T_84 = T_53 + 1'h1;
+ assign T_85 = T_84[0:0];
+ assign T_86 = T_81 ? 1'h0 : T_85;
+ assign T_88 = T_55 == 1'h1;
+ assign T_90 = 1'h0 & T_88;
+ assign T_93 = T_55 + 1'h1;
+ assign T_94 = T_93[0:0];
+ assign T_95 = T_90 ? 1'h0 : T_94;
+ assign T_96 = do_enq != do_deq;
+ assign T_98 = empty == 1'h0;
+ assign T_100 = 1'h0 & io_enq_valid;
+ assign T_101 = T_98 | T_100;
+ assign T_103 = full == 1'h0;
+ assign T_105 = 1'h0 & io_deq_ready;
+ assign T_106 = T_103 | T_105;
+ assign T_111_rw = maybe_flow ? io_enq_bits_rw : ram_rw_T_107_data;
+ assign T_111_addr = maybe_flow ? io_enq_bits_addr : ram_addr_T_107_data;
+ assign T_111_data = maybe_flow ? io_enq_bits_data : ram_data_T_107_data;
+ assign T_115 = T_53 - T_55;
+ assign ptr_diff = T_115[0:0];
+ assign T_117 = maybe_full & ptr_match;
+ assign T_118 = {T_117,ptr_diff};
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_rw[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_addr[initvar] = {1{$random}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_data[initvar] = {2{$random}};
+ T_53 = {1{$random}};
+ T_55 = {1{$random}};
+ maybe_full = {1{$random}};
+ end
+`endif
+ always @(posedge ram_rw_T_74_clk) begin
+ if(ram_rw_T_74_en & ram_rw_T_74_mask) begin
+ ram_rw[ram_rw_T_74_addr] <= ram_rw_T_74_data;
+ end
+ end
+ always @(posedge ram_addr_T_74_clk) begin
+ if(ram_addr_T_74_en & ram_addr_T_74_mask) begin
+ ram_addr[ram_addr_T_74_addr] <= ram_addr_T_74_data;
+ end
+ end
+ always @(posedge ram_data_T_74_clk) begin
+ if(ram_data_T_74_en & ram_data_T_74_mask) begin
+ ram_data[ram_data_T_74_addr] <= ram_data_T_74_data;
+ end
+ end
+ always @(posedge clk) begin
+ if(reset) begin
+ T_53 <= 1'h0;
+ end else begin
+ if(do_enq) begin
+ T_53 <= T_86;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_55 <= 1'h0;
+ end else begin
+ if(do_deq) begin
+ T_55 <= T_95;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ maybe_full <= 1'h0;
+ end else begin
+ if(T_96) begin
+ maybe_full <= do_enq;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module Queue_125(
+ input clk,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [63:0] io_enq_bits,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [63:0] io_deq_bits,
+ output [1:0] io_count
+);
+ reg [63:0] ram [0:1];
+ wire [63:0] ram_T_77_data;
+ wire ram_T_77_addr;
+ wire ram_T_77_en;
+ wire ram_T_77_clk;
+ wire [63:0] ram_T_47_data;
+ wire ram_T_47_addr;
+ wire ram_T_47_mask;
+ wire ram_T_47_en;
+ wire ram_T_47_clk;
+ reg T_26;
+ reg T_28;
+ reg maybe_full;
+ wire ptr_match;
+ wire T_33;
+ wire empty;
+ wire full;
+ wire maybe_flow;
+ wire do_flow;
+ wire T_39;
+ wire T_41;
+ wire do_enq;
+ wire T_43;
+ wire T_45;
+ wire do_deq;
+ wire T_49;
+ wire T_51;
+ wire [1:0] T_54;
+ wire T_55;
+ wire T_56;
+ wire T_58;
+ wire T_60;
+ wire [1:0] T_63;
+ wire T_64;
+ wire T_65;
+ wire T_66;
+ wire T_68;
+ wire T_70;
+ wire T_71;
+ wire T_73;
+ wire T_75;
+ wire T_76;
+ wire [63:0] T_78;
+ wire [1:0] T_79;
+ wire ptr_diff;
+ wire T_81;
+ wire [1:0] T_82;
+ assign io_enq_ready = T_76;
+ assign io_deq_valid = T_71;
+ assign io_deq_bits = T_78;
+ assign io_count = T_82;
+ assign ram_T_77_addr = T_28;
+ assign ram_T_77_en = 1'h1;
+ assign ram_T_77_clk = clk;
+ assign ram_T_77_data = ram[ram_T_77_addr];
+ assign ram_T_47_data = io_enq_bits;
+ assign ram_T_47_addr = T_26;
+ assign ram_T_47_mask = do_enq ? 1'h1 : 1'h0;
+ assign ram_T_47_en = do_enq ? 1'h1 : 1'h0;
+ assign ram_T_47_clk = clk;
+ assign ptr_match = T_26 == T_28;
+ assign T_33 = maybe_full == 1'h0;
+ assign empty = ptr_match & T_33;
+ assign full = ptr_match & maybe_full;
+ assign maybe_flow = 1'h0 & empty;
+ assign do_flow = maybe_flow & io_deq_ready;
+ assign T_39 = io_enq_ready & io_enq_valid;
+ assign T_41 = do_flow == 1'h0;
+ assign do_enq = T_39 & T_41;
+ assign T_43 = io_deq_ready & io_deq_valid;
+ assign T_45 = do_flow == 1'h0;
+ assign do_deq = T_43 & T_45;
+ assign T_49 = T_26 == 1'h1;
+ assign T_51 = 1'h0 & T_49;
+ assign T_54 = T_26 + 1'h1;
+ assign T_55 = T_54[0:0];
+ assign T_56 = T_51 ? 1'h0 : T_55;
+ assign T_58 = T_28 == 1'h1;
+ assign T_60 = 1'h0 & T_58;
+ assign T_63 = T_28 + 1'h1;
+ assign T_64 = T_63[0:0];
+ assign T_65 = T_60 ? 1'h0 : T_64;
+ assign T_66 = do_enq != do_deq;
+ assign T_68 = empty == 1'h0;
+ assign T_70 = 1'h0 & io_enq_valid;
+ assign T_71 = T_68 | T_70;
+ assign T_73 = full == 1'h0;
+ assign T_75 = 1'h0 & io_deq_ready;
+ assign T_76 = T_73 | T_75;
+ assign T_78 = maybe_flow ? io_enq_bits : ram_T_77_data;
+ assign T_79 = T_26 - T_28;
+ assign ptr_diff = T_79[0:0];
+ assign T_81 = maybe_full & ptr_match;
+ assign T_82 = {T_81,ptr_diff};
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram[initvar] = {2{$random}};
+ T_26 = {1{$random}};
+ T_28 = {1{$random}};
+ maybe_full = {1{$random}};
+ end
+`endif
+ always @(posedge ram_T_47_clk) begin
+ if(ram_T_47_en & ram_T_47_mask) begin
+ ram[ram_T_47_addr] <= ram_T_47_data;
+ end
+ end
+ always @(posedge clk) begin
+ if(reset) begin
+ T_26 <= 1'h0;
+ end else begin
+ if(do_enq) begin
+ T_26 <= T_56;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ T_28 <= 1'h0;
+ end else begin
+ if(do_deq) begin
+ T_28 <= T_65;
+ end else begin
+ ;
+ end
+ end
+ if(reset) begin
+ maybe_full <= 1'h0;
+ end else begin
+ if(T_66) begin
+ maybe_full <= do_enq;
+ end else begin
+ ;
+ end
+ end
+ end
+endmodule
+module Top(
+ input clk,
+ input reset,
+ output io_host_clk,
+ output io_host_clk_edge,
+ output io_host_in_ready,
+ input io_host_in_valid,
+ input [15:0] io_host_in_bits,
+ input io_host_out_ready,
+ output io_host_out_valid,
+ output [15:0] io_host_out_bits,
+ output io_host_debug_stats_csr,
+ input io_mem_backup_ctrl_en,
+ input io_mem_backup_ctrl_in_valid,
+ input io_mem_backup_ctrl_out_ready,
+ output io_mem_backup_ctrl_out_valid,
+ input io_mem_0_aw_ready,
+ output io_mem_0_aw_valid,
+ output [31:0] io_mem_0_aw_bits_addr,
+ output [7:0] io_mem_0_aw_bits_len,
+ output [2:0] io_mem_0_aw_bits_size,
+ output [1:0] io_mem_0_aw_bits_burst,
+ output io_mem_0_aw_bits_lock,
+ output [3:0] io_mem_0_aw_bits_cache,
+ output [2:0] io_mem_0_aw_bits_prot,
+ output [3:0] io_mem_0_aw_bits_qos,
+ output [3:0] io_mem_0_aw_bits_region,
+ output [4:0] io_mem_0_aw_bits_id,
+ output io_mem_0_aw_bits_user,
+ input io_mem_0_w_ready,
+ output io_mem_0_w_valid,
+ output [63:0] io_mem_0_w_bits_data,
+ output io_mem_0_w_bits_last,
+ output [7:0] io_mem_0_w_bits_strb,
+ output io_mem_0_w_bits_user,
+ output io_mem_0_b_ready,
+ input io_mem_0_b_valid,
+ input [1:0] io_mem_0_b_bits_resp,
+ input [4:0] io_mem_0_b_bits_id,
+ input io_mem_0_b_bits_user,
+ input io_mem_0_ar_ready,
+ output io_mem_0_ar_valid,
+ output [31:0] io_mem_0_ar_bits_addr,
+ output [7:0] io_mem_0_ar_bits_len,
+ output [2:0] io_mem_0_ar_bits_size,
+ output [1:0] io_mem_0_ar_bits_burst,
+ output io_mem_0_ar_bits_lock,
+ output [3:0] io_mem_0_ar_bits_cache,
+ output [2:0] io_mem_0_ar_bits_prot,
+ output [3:0] io_mem_0_ar_bits_qos,
+ output [3:0] io_mem_0_ar_bits_region,
+ output [4:0] io_mem_0_ar_bits_id,
+ output io_mem_0_ar_bits_user,
+ output io_mem_0_r_ready,
+ input io_mem_0_r_valid,
+ input [1:0] io_mem_0_r_bits_resp,
+ input [63:0] io_mem_0_r_bits_data,
+ input io_mem_0_r_bits_last,
+ input [4:0] io_mem_0_r_bits_id,
+ input io_mem_0_r_bits_user
+);
+ wire uncore_clk;
+ wire uncore_reset;
+ wire uncore_io_host_clk;
+ wire uncore_io_host_clk_edge;
+ wire uncore_io_host_in_ready;
+ wire uncore_io_host_in_valid;
+ wire [15:0] uncore_io_host_in_bits;
+ wire uncore_io_host_out_ready;
+ wire uncore_io_host_out_valid;
+ wire [15:0] uncore_io_host_out_bits;
+ wire uncore_io_host_debug_stats_csr;
+ wire uncore_io_mem_0_aw_ready;
+ wire uncore_io_mem_0_aw_valid;
+ wire [31:0] uncore_io_mem_0_aw_bits_addr;
+ wire [7:0] uncore_io_mem_0_aw_bits_len;
+ wire [2:0] uncore_io_mem_0_aw_bits_size;
+ wire [1:0] uncore_io_mem_0_aw_bits_burst;
+ wire uncore_io_mem_0_aw_bits_lock;
+ wire [3:0] uncore_io_mem_0_aw_bits_cache;
+ wire [2:0] uncore_io_mem_0_aw_bits_prot;
+ wire [3:0] uncore_io_mem_0_aw_bits_qos;
+ wire [3:0] uncore_io_mem_0_aw_bits_region;
+ wire [4:0] uncore_io_mem_0_aw_bits_id;
+ wire uncore_io_mem_0_aw_bits_user;
+ wire uncore_io_mem_0_w_ready;
+ wire uncore_io_mem_0_w_valid;
+ wire [63:0] uncore_io_mem_0_w_bits_data;
+ wire uncore_io_mem_0_w_bits_last;
+ wire [7:0] uncore_io_mem_0_w_bits_strb;
+ wire uncore_io_mem_0_w_bits_user;
+ wire uncore_io_mem_0_b_ready;
+ wire uncore_io_mem_0_b_valid;
+ wire [1:0] uncore_io_mem_0_b_bits_resp;
+ wire [4:0] uncore_io_mem_0_b_bits_id;
+ wire uncore_io_mem_0_b_bits_user;
+ wire uncore_io_mem_0_ar_ready;
+ wire uncore_io_mem_0_ar_valid;
+ wire [31:0] uncore_io_mem_0_ar_bits_addr;
+ wire [7:0] uncore_io_mem_0_ar_bits_len;
+ wire [2:0] uncore_io_mem_0_ar_bits_size;
+ wire [1:0] uncore_io_mem_0_ar_bits_burst;
+ wire uncore_io_mem_0_ar_bits_lock;
+ wire [3:0] uncore_io_mem_0_ar_bits_cache;
+ wire [2:0] uncore_io_mem_0_ar_bits_prot;
+ wire [3:0] uncore_io_mem_0_ar_bits_qos;
+ wire [3:0] uncore_io_mem_0_ar_bits_region;
+ wire [4:0] uncore_io_mem_0_ar_bits_id;
+ wire uncore_io_mem_0_ar_bits_user;
+ wire uncore_io_mem_0_r_ready;
+ wire uncore_io_mem_0_r_valid;
+ wire [1:0] uncore_io_mem_0_r_bits_resp;
+ wire [63:0] uncore_io_mem_0_r_bits_data;
+ wire uncore_io_mem_0_r_bits_last;
+ wire [4:0] uncore_io_mem_0_r_bits_id;
+ wire uncore_io_mem_0_r_bits_user;
+ wire uncore_io_tiles_cached_0_acquire_ready;
+ wire uncore_io_tiles_cached_0_acquire_valid;
+ wire [25:0] uncore_io_tiles_cached_0_acquire_bits_addr_block;
+ wire [1:0] uncore_io_tiles_cached_0_acquire_bits_client_xact_id;
+ wire [1:0] uncore_io_tiles_cached_0_acquire_bits_addr_beat;
+ wire uncore_io_tiles_cached_0_acquire_bits_is_builtin_type;
+ wire [2:0] uncore_io_tiles_cached_0_acquire_bits_a_type;
+ wire [16:0] uncore_io_tiles_cached_0_acquire_bits_union;
+ wire [127:0] uncore_io_tiles_cached_0_acquire_bits_data;
+ wire uncore_io_tiles_cached_0_grant_ready;
+ wire uncore_io_tiles_cached_0_grant_valid;
+ wire [1:0] uncore_io_tiles_cached_0_grant_bits_addr_beat;
+ wire [1:0] uncore_io_tiles_cached_0_grant_bits_client_xact_id;
+ wire [3:0] uncore_io_tiles_cached_0_grant_bits_manager_xact_id;
+ wire uncore_io_tiles_cached_0_grant_bits_is_builtin_type;
+ wire [3:0] uncore_io_tiles_cached_0_grant_bits_g_type;
+ wire [127:0] uncore_io_tiles_cached_0_grant_bits_data;
+ wire uncore_io_tiles_cached_0_probe_ready;
+ wire uncore_io_tiles_cached_0_probe_valid;
+ wire [25:0] uncore_io_tiles_cached_0_probe_bits_addr_block;
+ wire [1:0] uncore_io_tiles_cached_0_probe_bits_p_type;
+ wire uncore_io_tiles_cached_0_release_ready;
+ wire uncore_io_tiles_cached_0_release_valid;
+ wire [1:0] uncore_io_tiles_cached_0_release_bits_addr_beat;
+ wire [25:0] uncore_io_tiles_cached_0_release_bits_addr_block;
+ wire [1:0] uncore_io_tiles_cached_0_release_bits_client_xact_id;
+ wire uncore_io_tiles_cached_0_release_bits_voluntary;
+ wire [2:0] uncore_io_tiles_cached_0_release_bits_r_type;
+ wire [127:0] uncore_io_tiles_cached_0_release_bits_data;
+ wire uncore_io_tiles_uncached_0_acquire_ready;
+ wire uncore_io_tiles_uncached_0_acquire_valid;
+ wire [25:0] uncore_io_tiles_uncached_0_acquire_bits_addr_block;
+ wire [1:0] uncore_io_tiles_uncached_0_acquire_bits_client_xact_id;
+ wire [1:0] uncore_io_tiles_uncached_0_acquire_bits_addr_beat;
+ wire uncore_io_tiles_uncached_0_acquire_bits_is_builtin_type;
+ wire [2:0] uncore_io_tiles_uncached_0_acquire_bits_a_type;
+ wire [16:0] uncore_io_tiles_uncached_0_acquire_bits_union;
+ wire [127:0] uncore_io_tiles_uncached_0_acquire_bits_data;
+ wire uncore_io_tiles_uncached_0_grant_ready;
+ wire uncore_io_tiles_uncached_0_grant_valid;
+ wire [1:0] uncore_io_tiles_uncached_0_grant_bits_addr_beat;
+ wire [1:0] uncore_io_tiles_uncached_0_grant_bits_client_xact_id;
+ wire [3:0] uncore_io_tiles_uncached_0_grant_bits_manager_xact_id;
+ wire uncore_io_tiles_uncached_0_grant_bits_is_builtin_type;
+ wire [3:0] uncore_io_tiles_uncached_0_grant_bits_g_type;
+ wire [127:0] uncore_io_tiles_uncached_0_grant_bits_data;
+ wire uncore_io_htif_0_reset;
+ wire uncore_io_htif_0_id;
+ wire uncore_io_htif_0_csr_req_ready;
+ wire uncore_io_htif_0_csr_req_valid;
+ wire uncore_io_htif_0_csr_req_bits_rw;
+ wire [11:0] uncore_io_htif_0_csr_req_bits_addr;
+ wire [63:0] uncore_io_htif_0_csr_req_bits_data;
+ wire uncore_io_htif_0_csr_resp_ready;
+ wire uncore_io_htif_0_csr_resp_valid;
+ wire [63:0] uncore_io_htif_0_csr_resp_bits;
+ wire uncore_io_htif_0_debug_stats_csr;
+ wire uncore_io_mem_backup_ctrl_en;
+ wire uncore_io_mem_backup_ctrl_in_valid;
+ wire uncore_io_mem_backup_ctrl_out_ready;
+ wire uncore_io_mem_backup_ctrl_out_valid;
+ wire uncore_io_mmio_aw_ready;
+ wire uncore_io_mmio_aw_valid;
+ wire [31:0] uncore_io_mmio_aw_bits_addr;
+ wire [7:0] uncore_io_mmio_aw_bits_len;
+ wire [2:0] uncore_io_mmio_aw_bits_size;
+ wire [1:0] uncore_io_mmio_aw_bits_burst;
+ wire uncore_io_mmio_aw_bits_lock;
+ wire [3:0] uncore_io_mmio_aw_bits_cache;
+ wire [2:0] uncore_io_mmio_aw_bits_prot;
+ wire [3:0] uncore_io_mmio_aw_bits_qos;
+ wire [3:0] uncore_io_mmio_aw_bits_region;
+ wire [4:0] uncore_io_mmio_aw_bits_id;
+ wire uncore_io_mmio_aw_bits_user;
+ wire uncore_io_mmio_w_ready;
+ wire uncore_io_mmio_w_valid;
+ wire [63:0] uncore_io_mmio_w_bits_data;
+ wire uncore_io_mmio_w_bits_last;
+ wire [7:0] uncore_io_mmio_w_bits_strb;
+ wire uncore_io_mmio_w_bits_user;
+ wire uncore_io_mmio_b_ready;
+ wire uncore_io_mmio_b_valid;
+ wire [1:0] uncore_io_mmio_b_bits_resp;
+ wire [4:0] uncore_io_mmio_b_bits_id;
+ wire uncore_io_mmio_b_bits_user;
+ wire uncore_io_mmio_ar_ready;
+ wire uncore_io_mmio_ar_valid;
+ wire [31:0] uncore_io_mmio_ar_bits_addr;
+ wire [7:0] uncore_io_mmio_ar_bits_len;
+ wire [2:0] uncore_io_mmio_ar_bits_size;
+ wire [1:0] uncore_io_mmio_ar_bits_burst;
+ wire uncore_io_mmio_ar_bits_lock;
+ wire [3:0] uncore_io_mmio_ar_bits_cache;
+ wire [2:0] uncore_io_mmio_ar_bits_prot;
+ wire [3:0] uncore_io_mmio_ar_bits_qos;
+ wire [3:0] uncore_io_mmio_ar_bits_region;
+ wire [4:0] uncore_io_mmio_ar_bits_id;
+ wire uncore_io_mmio_ar_bits_user;
+ wire uncore_io_mmio_r_ready;
+ wire uncore_io_mmio_r_valid;
+ wire [1:0] uncore_io_mmio_r_bits_resp;
+ wire [63:0] uncore_io_mmio_r_bits_data;
+ wire uncore_io_mmio_r_bits_last;
+ wire [4:0] uncore_io_mmio_r_bits_id;
+ wire uncore_io_mmio_r_bits_user;
+ wire uncore_io_dma_0_req_ready;
+ wire uncore_io_dma_0_req_valid;
+ wire [1:0] uncore_io_dma_0_req_bits_client_xact_id;
+ wire [2:0] uncore_io_dma_0_req_bits_cmd;
+ wire [31:0] uncore_io_dma_0_req_bits_source;
+ wire [31:0] uncore_io_dma_0_req_bits_dest;
+ wire [31:0] uncore_io_dma_0_req_bits_length;
+ wire [1:0] uncore_io_dma_0_req_bits_size;
+ wire uncore_io_dma_0_resp_ready;
+ wire uncore_io_dma_0_resp_valid;
+ wire [1:0] uncore_io_dma_0_resp_bits_client_xact_id;
+ wire [1:0] uncore_io_dma_0_resp_bits_status;
+ wire T_669_clk;
+ wire T_669_reset;
+ wire T_669_io_cached_0_acquire_ready;
+ wire T_669_io_cached_0_acquire_valid;
+ wire [25:0] T_669_io_cached_0_acquire_bits_addr_block;
+ wire [1:0] T_669_io_cached_0_acquire_bits_client_xact_id;
+ wire [1:0] T_669_io_cached_0_acquire_bits_addr_beat;
+ wire T_669_io_cached_0_acquire_bits_is_builtin_type;
+ wire [2:0] T_669_io_cached_0_acquire_bits_a_type;
+ wire [16:0] T_669_io_cached_0_acquire_bits_union;
+ wire [127:0] T_669_io_cached_0_acquire_bits_data;
+ wire T_669_io_cached_0_grant_ready;
+ wire T_669_io_cached_0_grant_valid;
+ wire [1:0] T_669_io_cached_0_grant_bits_addr_beat;
+ wire [1:0] T_669_io_cached_0_grant_bits_client_xact_id;
+ wire [3:0] T_669_io_cached_0_grant_bits_manager_xact_id;
+ wire T_669_io_cached_0_grant_bits_is_builtin_type;
+ wire [3:0] T_669_io_cached_0_grant_bits_g_type;
+ wire [127:0] T_669_io_cached_0_grant_bits_data;
+ wire T_669_io_cached_0_probe_ready;
+ wire T_669_io_cached_0_probe_valid;
+ wire [25:0] T_669_io_cached_0_probe_bits_addr_block;
+ wire [1:0] T_669_io_cached_0_probe_bits_p_type;
+ wire T_669_io_cached_0_release_ready;
+ wire T_669_io_cached_0_release_valid;
+ wire [1:0] T_669_io_cached_0_release_bits_addr_beat;
+ wire [25:0] T_669_io_cached_0_release_bits_addr_block;
+ wire [1:0] T_669_io_cached_0_release_bits_client_xact_id;
+ wire T_669_io_cached_0_release_bits_voluntary;
+ wire [2:0] T_669_io_cached_0_release_bits_r_type;
+ wire [127:0] T_669_io_cached_0_release_bits_data;
+ wire T_669_io_uncached_0_acquire_ready;
+ wire T_669_io_uncached_0_acquire_valid;
+ wire [25:0] T_669_io_uncached_0_acquire_bits_addr_block;
+ wire [1:0] T_669_io_uncached_0_acquire_bits_client_xact_id;
+ wire [1:0] T_669_io_uncached_0_acquire_bits_addr_beat;
+ wire T_669_io_uncached_0_acquire_bits_is_builtin_type;
+ wire [2:0] T_669_io_uncached_0_acquire_bits_a_type;
+ wire [16:0] T_669_io_uncached_0_acquire_bits_union;
+ wire [127:0] T_669_io_uncached_0_acquire_bits_data;
+ wire T_669_io_uncached_0_grant_ready;
+ wire T_669_io_uncached_0_grant_valid;
+ wire [1:0] T_669_io_uncached_0_grant_bits_addr_beat;
+ wire [1:0] T_669_io_uncached_0_grant_bits_client_xact_id;
+ wire [3:0] T_669_io_uncached_0_grant_bits_manager_xact_id;
+ wire T_669_io_uncached_0_grant_bits_is_builtin_type;
+ wire [3:0] T_669_io_uncached_0_grant_bits_g_type;
+ wire [127:0] T_669_io_uncached_0_grant_bits_data;
+ wire T_669_io_host_reset;
+ wire T_669_io_host_id;
+ wire T_669_io_host_csr_req_ready;
+ wire T_669_io_host_csr_req_valid;
+ wire T_669_io_host_csr_req_bits_rw;
+ wire [11:0] T_669_io_host_csr_req_bits_addr;
+ wire [63:0] T_669_io_host_csr_req_bits_data;
+ wire T_669_io_host_csr_resp_ready;
+ wire T_669_io_host_csr_resp_valid;
+ wire [63:0] T_669_io_host_csr_resp_bits;
+ wire T_669_io_host_debug_stats_csr;
+ wire T_669_io_dma_req_ready;
+ wire T_669_io_dma_req_valid;
+ wire [1:0] T_669_io_dma_req_bits_client_xact_id;
+ wire [2:0] T_669_io_dma_req_bits_cmd;
+ wire [31:0] T_669_io_dma_req_bits_source;
+ wire [31:0] T_669_io_dma_req_bits_dest;
+ wire [31:0] T_669_io_dma_req_bits_length;
+ wire [1:0] T_669_io_dma_req_bits_size;
+ wire T_669_io_dma_resp_ready;
+ wire T_669_io_dma_resp_valid;
+ wire [1:0] T_669_io_dma_resp_bits_client_xact_id;
+ wire [1:0] T_669_io_dma_resp_bits_status;
+ reg T_671;
+ reg T_672;
+ wire T_677_clk;
+ wire T_677_reset;
+ wire T_677_io_enq_ready;
+ wire T_677_io_enq_valid;
+ wire T_677_io_enq_bits_rw;
+ wire [11:0] T_677_io_enq_bits_addr;
+ wire [63:0] T_677_io_enq_bits_data;
+ wire T_677_io_deq_ready;
+ wire T_677_io_deq_valid;
+ wire T_677_io_deq_bits_rw;
+ wire [11:0] T_677_io_deq_bits_addr;
+ wire [63:0] T_677_io_deq_bits_data;
+ wire [1:0] T_677_io_count;
+ wire T_679_clk;
+ wire T_679_reset;
+ wire T_679_io_enq_ready;
+ wire T_679_io_enq_valid;
+ wire [63:0] T_679_io_enq_bits;
+ wire T_679_io_deq_ready;
+ wire T_679_io_deq_valid;
+ wire [63:0] T_679_io_deq_bits;
+ wire [1:0] T_679_io_count;
+ wire T_692_clk;
+ wire T_692_reset;
+ wire T_692_io_enq_ready;
+ wire T_692_io_enq_valid;
+ wire [31:0] T_692_io_enq_bits_addr;
+ wire [7:0] T_692_io_enq_bits_len;
+ wire [2:0] T_692_io_enq_bits_size;
+ wire [1:0] T_692_io_enq_bits_burst;
+ wire T_692_io_enq_bits_lock;
+ wire [3:0] T_692_io_enq_bits_cache;
+ wire [2:0] T_692_io_enq_bits_prot;
+ wire [3:0] T_692_io_enq_bits_qos;
+ wire [3:0] T_692_io_enq_bits_region;
+ wire [4:0] T_692_io_enq_bits_id;
+ wire T_692_io_enq_bits_user;
+ wire T_692_io_deq_ready;
+ wire T_692_io_deq_valid;
+ wire [31:0] T_692_io_deq_bits_addr;
+ wire [7:0] T_692_io_deq_bits_len;
+ wire [2:0] T_692_io_deq_bits_size;
+ wire [1:0] T_692_io_deq_bits_burst;
+ wire T_692_io_deq_bits_lock;
+ wire [3:0] T_692_io_deq_bits_cache;
+ wire [2:0] T_692_io_deq_bits_prot;
+ wire [3:0] T_692_io_deq_bits_qos;
+ wire [3:0] T_692_io_deq_bits_region;
+ wire [4:0] T_692_io_deq_bits_id;
+ wire T_692_io_deq_bits_user;
+ wire [1:0] T_692_io_count;
+ wire T_705_clk;
+ wire T_705_reset;
+ wire T_705_io_enq_ready;
+ wire T_705_io_enq_valid;
+ wire [31:0] T_705_io_enq_bits_addr;
+ wire [7:0] T_705_io_enq_bits_len;
+ wire [2:0] T_705_io_enq_bits_size;
+ wire [1:0] T_705_io_enq_bits_burst;
+ wire T_705_io_enq_bits_lock;
+ wire [3:0] T_705_io_enq_bits_cache;
+ wire [2:0] T_705_io_enq_bits_prot;
+ wire [3:0] T_705_io_enq_bits_qos;
+ wire [3:0] T_705_io_enq_bits_region;
+ wire [4:0] T_705_io_enq_bits_id;
+ wire T_705_io_enq_bits_user;
+ wire T_705_io_deq_ready;
+ wire T_705_io_deq_valid;
+ wire [31:0] T_705_io_deq_bits_addr;
+ wire [7:0] T_705_io_deq_bits_len;
+ wire [2:0] T_705_io_deq_bits_size;
+ wire [1:0] T_705_io_deq_bits_burst;
+ wire T_705_io_deq_bits_lock;
+ wire [3:0] T_705_io_deq_bits_cache;
+ wire [2:0] T_705_io_deq_bits_prot;
+ wire [3:0] T_705_io_deq_bits_qos;
+ wire [3:0] T_705_io_deq_bits_region;
+ wire [4:0] T_705_io_deq_bits_id;
+ wire T_705_io_deq_bits_user;
+ wire [1:0] T_705_io_count;
+ wire T_711_clk;
+ wire T_711_reset;
+ wire T_711_io_enq_ready;
+ wire T_711_io_enq_valid;
+ wire [63:0] T_711_io_enq_bits_data;
+ wire T_711_io_enq_bits_last;
+ wire [7:0] T_711_io_enq_bits_strb;
+ wire T_711_io_enq_bits_user;
+ wire T_711_io_deq_ready;
+ wire T_711_io_deq_valid;
+ wire [63:0] T_711_io_deq_bits_data;
+ wire T_711_io_deq_bits_last;
+ wire [7:0] T_711_io_deq_bits_strb;
+ wire T_711_io_deq_bits_user;
+ wire [3:0] T_711_io_count;
+ wire T_718_clk;
+ wire T_718_reset;
+ wire T_718_io_enq_ready;
+ wire T_718_io_enq_valid;
+ wire [1:0] T_718_io_enq_bits_resp;
+ wire [63:0] T_718_io_enq_bits_data;
+ wire T_718_io_enq_bits_last;
+ wire [4:0] T_718_io_enq_bits_id;
+ wire T_718_io_enq_bits_user;
+ wire T_718_io_deq_ready;
+ wire T_718_io_deq_valid;
+ wire [1:0] T_718_io_deq_bits_resp;
+ wire [63:0] T_718_io_deq_bits_data;
+ wire T_718_io_deq_bits_last;
+ wire [4:0] T_718_io_deq_bits_id;
+ wire T_718_io_deq_bits_user;
+ wire [3:0] T_718_io_count;
+ wire T_723_clk;
+ wire T_723_reset;
+ wire T_723_io_enq_ready;
+ wire T_723_io_enq_valid;
+ wire [1:0] T_723_io_enq_bits_resp;
+ wire [4:0] T_723_io_enq_bits_id;
+ wire T_723_io_enq_bits_user;
+ wire T_723_io_deq_ready;
+ wire T_723_io_deq_valid;
+ wire [1:0] T_723_io_deq_bits_resp;
+ wire [4:0] T_723_io_deq_bits_id;
+ wire T_723_io_deq_bits_user;
+ wire [1:0] T_723_io_count;
+ wire errslave_clk;
+ wire errslave_reset;
+ wire errslave_io_aw_ready;
+ wire errslave_io_aw_valid;
+ wire [31:0] errslave_io_aw_bits_addr;
+ wire [7:0] errslave_io_aw_bits_len;
+ wire [2:0] errslave_io_aw_bits_size;
+ wire [1:0] errslave_io_aw_bits_burst;
+ wire errslave_io_aw_bits_lock;
+ wire [3:0] errslave_io_aw_bits_cache;
+ wire [2:0] errslave_io_aw_bits_prot;
+ wire [3:0] errslave_io_aw_bits_qos;
+ wire [3:0] errslave_io_aw_bits_region;
+ wire [4:0] errslave_io_aw_bits_id;
+ wire errslave_io_aw_bits_user;
+ wire errslave_io_w_ready;
+ wire errslave_io_w_valid;
+ wire [63:0] errslave_io_w_bits_data;
+ wire errslave_io_w_bits_last;
+ wire [7:0] errslave_io_w_bits_strb;
+ wire errslave_io_w_bits_user;
+ wire errslave_io_b_ready;
+ wire errslave_io_b_valid;
+ wire [1:0] errslave_io_b_bits_resp;
+ wire [4:0] errslave_io_b_bits_id;
+ wire errslave_io_b_bits_user;
+ wire errslave_io_ar_ready;
+ wire errslave_io_ar_valid;
+ wire [31:0] errslave_io_ar_bits_addr;
+ wire [7:0] errslave_io_ar_bits_len;
+ wire [2:0] errslave_io_ar_bits_size;
+ wire [1:0] errslave_io_ar_bits_burst;
+ wire errslave_io_ar_bits_lock;
+ wire [3:0] errslave_io_ar_bits_cache;
+ wire [2:0] errslave_io_ar_bits_prot;
+ wire [3:0] errslave_io_ar_bits_qos;
+ wire [3:0] errslave_io_ar_bits_region;
+ wire [4:0] errslave_io_ar_bits_id;
+ wire errslave_io_ar_bits_user;
+ wire errslave_io_r_ready;
+ wire errslave_io_r_valid;
+ wire [1:0] errslave_io_r_bits_resp;
+ wire [63:0] errslave_io_r_bits_data;
+ wire errslave_io_r_bits_last;
+ wire [4:0] errslave_io_r_bits_id;
+ wire errslave_io_r_bits_user;
+ reg GEN_0;
+ reg [1:0] GEN_1;
+ reg [2:0] GEN_2;
+ reg [31:0] GEN_3;
+ reg [31:0] GEN_4;
+ reg [31:0] GEN_5;
+ reg [1:0] GEN_6;
+ reg GEN_7;
+ reg GEN_8;
+ reg GEN_9;
+ reg [1:0] GEN_10;
+ reg [1:0] GEN_11;
+ Uncore uncore (
+ .clk(uncore_clk),
+ .reset(uncore_reset),
+ .io_host_clk(uncore_io_host_clk),
+ .io_host_clk_edge(uncore_io_host_clk_edge),
+ .io_host_in_ready(uncore_io_host_in_ready),
+ .io_host_in_valid(uncore_io_host_in_valid),
+ .io_host_in_bits(uncore_io_host_in_bits),
+ .io_host_out_ready(uncore_io_host_out_ready),
+ .io_host_out_valid(uncore_io_host_out_valid),
+ .io_host_out_bits(uncore_io_host_out_bits),
+ .io_host_debug_stats_csr(uncore_io_host_debug_stats_csr),
+ .io_mem_0_aw_ready(uncore_io_mem_0_aw_ready),
+ .io_mem_0_aw_valid(uncore_io_mem_0_aw_valid),
+ .io_mem_0_aw_bits_addr(uncore_io_mem_0_aw_bits_addr),
+ .io_mem_0_aw_bits_len(uncore_io_mem_0_aw_bits_len),
+ .io_mem_0_aw_bits_size(uncore_io_mem_0_aw_bits_size),
+ .io_mem_0_aw_bits_burst(uncore_io_mem_0_aw_bits_burst),
+ .io_mem_0_aw_bits_lock(uncore_io_mem_0_aw_bits_lock),
+ .io_mem_0_aw_bits_cache(uncore_io_mem_0_aw_bits_cache),
+ .io_mem_0_aw_bits_prot(uncore_io_mem_0_aw_bits_prot),
+ .io_mem_0_aw_bits_qos(uncore_io_mem_0_aw_bits_qos),
+ .io_mem_0_aw_bits_region(uncore_io_mem_0_aw_bits_region),
+ .io_mem_0_aw_bits_id(uncore_io_mem_0_aw_bits_id),
+ .io_mem_0_aw_bits_user(uncore_io_mem_0_aw_bits_user),
+ .io_mem_0_w_ready(uncore_io_mem_0_w_ready),
+ .io_mem_0_w_valid(uncore_io_mem_0_w_valid),
+ .io_mem_0_w_bits_data(uncore_io_mem_0_w_bits_data),
+ .io_mem_0_w_bits_last(uncore_io_mem_0_w_bits_last),
+ .io_mem_0_w_bits_strb(uncore_io_mem_0_w_bits_strb),
+ .io_mem_0_w_bits_user(uncore_io_mem_0_w_bits_user),
+ .io_mem_0_b_ready(uncore_io_mem_0_b_ready),
+ .io_mem_0_b_valid(uncore_io_mem_0_b_valid),
+ .io_mem_0_b_bits_resp(uncore_io_mem_0_b_bits_resp),
+ .io_mem_0_b_bits_id(uncore_io_mem_0_b_bits_id),
+ .io_mem_0_b_bits_user(uncore_io_mem_0_b_bits_user),
+ .io_mem_0_ar_ready(uncore_io_mem_0_ar_ready),
+ .io_mem_0_ar_valid(uncore_io_mem_0_ar_valid),
+ .io_mem_0_ar_bits_addr(uncore_io_mem_0_ar_bits_addr),
+ .io_mem_0_ar_bits_len(uncore_io_mem_0_ar_bits_len),
+ .io_mem_0_ar_bits_size(uncore_io_mem_0_ar_bits_size),
+ .io_mem_0_ar_bits_burst(uncore_io_mem_0_ar_bits_burst),
+ .io_mem_0_ar_bits_lock(uncore_io_mem_0_ar_bits_lock),
+ .io_mem_0_ar_bits_cache(uncore_io_mem_0_ar_bits_cache),
+ .io_mem_0_ar_bits_prot(uncore_io_mem_0_ar_bits_prot),
+ .io_mem_0_ar_bits_qos(uncore_io_mem_0_ar_bits_qos),
+ .io_mem_0_ar_bits_region(uncore_io_mem_0_ar_bits_region),
+ .io_mem_0_ar_bits_id(uncore_io_mem_0_ar_bits_id),
+ .io_mem_0_ar_bits_user(uncore_io_mem_0_ar_bits_user),
+ .io_mem_0_r_ready(uncore_io_mem_0_r_ready),
+ .io_mem_0_r_valid(uncore_io_mem_0_r_valid),
+ .io_mem_0_r_bits_resp(uncore_io_mem_0_r_bits_resp),
+ .io_mem_0_r_bits_data(uncore_io_mem_0_r_bits_data),
+ .io_mem_0_r_bits_last(uncore_io_mem_0_r_bits_last),
+ .io_mem_0_r_bits_id(uncore_io_mem_0_r_bits_id),
+ .io_mem_0_r_bits_user(uncore_io_mem_0_r_bits_user),
+ .io_tiles_cached_0_acquire_ready(uncore_io_tiles_cached_0_acquire_ready),
+ .io_tiles_cached_0_acquire_valid(uncore_io_tiles_cached_0_acquire_valid),
+ .io_tiles_cached_0_acquire_bits_addr_block(uncore_io_tiles_cached_0_acquire_bits_addr_block),
+ .io_tiles_cached_0_acquire_bits_client_xact_id(uncore_io_tiles_cached_0_acquire_bits_client_xact_id),
+ .io_tiles_cached_0_acquire_bits_addr_beat(uncore_io_tiles_cached_0_acquire_bits_addr_beat),
+ .io_tiles_cached_0_acquire_bits_is_builtin_type(uncore_io_tiles_cached_0_acquire_bits_is_builtin_type),
+ .io_tiles_cached_0_acquire_bits_a_type(uncore_io_tiles_cached_0_acquire_bits_a_type),
+ .io_tiles_cached_0_acquire_bits_union(uncore_io_tiles_cached_0_acquire_bits_union),
+ .io_tiles_cached_0_acquire_bits_data(uncore_io_tiles_cached_0_acquire_bits_data),
+ .io_tiles_cached_0_grant_ready(uncore_io_tiles_cached_0_grant_ready),
+ .io_tiles_cached_0_grant_valid(uncore_io_tiles_cached_0_grant_valid),
+ .io_tiles_cached_0_grant_bits_addr_beat(uncore_io_tiles_cached_0_grant_bits_addr_beat),
+ .io_tiles_cached_0_grant_bits_client_xact_id(uncore_io_tiles_cached_0_grant_bits_client_xact_id),
+ .io_tiles_cached_0_grant_bits_manager_xact_id(uncore_io_tiles_cached_0_grant_bits_manager_xact_id),
+ .io_tiles_cached_0_grant_bits_is_builtin_type(uncore_io_tiles_cached_0_grant_bits_is_builtin_type),
+ .io_tiles_cached_0_grant_bits_g_type(uncore_io_tiles_cached_0_grant_bits_g_type),
+ .io_tiles_cached_0_grant_bits_data(uncore_io_tiles_cached_0_grant_bits_data),
+ .io_tiles_cached_0_probe_ready(uncore_io_tiles_cached_0_probe_ready),
+ .io_tiles_cached_0_probe_valid(uncore_io_tiles_cached_0_probe_valid),
+ .io_tiles_cached_0_probe_bits_addr_block(uncore_io_tiles_cached_0_probe_bits_addr_block),
+ .io_tiles_cached_0_probe_bits_p_type(uncore_io_tiles_cached_0_probe_bits_p_type),
+ .io_tiles_cached_0_release_ready(uncore_io_tiles_cached_0_release_ready),
+ .io_tiles_cached_0_release_valid(uncore_io_tiles_cached_0_release_valid),
+ .io_tiles_cached_0_release_bits_addr_beat(uncore_io_tiles_cached_0_release_bits_addr_beat),
+ .io_tiles_cached_0_release_bits_addr_block(uncore_io_tiles_cached_0_release_bits_addr_block),
+ .io_tiles_cached_0_release_bits_client_xact_id(uncore_io_tiles_cached_0_release_bits_client_xact_id),
+ .io_tiles_cached_0_release_bits_voluntary(uncore_io_tiles_cached_0_release_bits_voluntary),
+ .io_tiles_cached_0_release_bits_r_type(uncore_io_tiles_cached_0_release_bits_r_type),
+ .io_tiles_cached_0_release_bits_data(uncore_io_tiles_cached_0_release_bits_data),
+ .io_tiles_uncached_0_acquire_ready(uncore_io_tiles_uncached_0_acquire_ready),
+ .io_tiles_uncached_0_acquire_valid(uncore_io_tiles_uncached_0_acquire_valid),
+ .io_tiles_uncached_0_acquire_bits_addr_block(uncore_io_tiles_uncached_0_acquire_bits_addr_block),
+ .io_tiles_uncached_0_acquire_bits_client_xact_id(uncore_io_tiles_uncached_0_acquire_bits_client_xact_id),
+ .io_tiles_uncached_0_acquire_bits_addr_beat(uncore_io_tiles_uncached_0_acquire_bits_addr_beat),
+ .io_tiles_uncached_0_acquire_bits_is_builtin_type(uncore_io_tiles_uncached_0_acquire_bits_is_builtin_type),
+ .io_tiles_uncached_0_acquire_bits_a_type(uncore_io_tiles_uncached_0_acquire_bits_a_type),
+ .io_tiles_uncached_0_acquire_bits_union(uncore_io_tiles_uncached_0_acquire_bits_union),
+ .io_tiles_uncached_0_acquire_bits_data(uncore_io_tiles_uncached_0_acquire_bits_data),
+ .io_tiles_uncached_0_grant_ready(uncore_io_tiles_uncached_0_grant_ready),
+ .io_tiles_uncached_0_grant_valid(uncore_io_tiles_uncached_0_grant_valid),
+ .io_tiles_uncached_0_grant_bits_addr_beat(uncore_io_tiles_uncached_0_grant_bits_addr_beat),
+ .io_tiles_uncached_0_grant_bits_client_xact_id(uncore_io_tiles_uncached_0_grant_bits_client_xact_id),
+ .io_tiles_uncached_0_grant_bits_manager_xact_id(uncore_io_tiles_uncached_0_grant_bits_manager_xact_id),
+ .io_tiles_uncached_0_grant_bits_is_builtin_type(uncore_io_tiles_uncached_0_grant_bits_is_builtin_type),
+ .io_tiles_uncached_0_grant_bits_g_type(uncore_io_tiles_uncached_0_grant_bits_g_type),
+ .io_tiles_uncached_0_grant_bits_data(uncore_io_tiles_uncached_0_grant_bits_data),
+ .io_htif_0_reset(uncore_io_htif_0_reset),
+ .io_htif_0_id(uncore_io_htif_0_id),
+ .io_htif_0_csr_req_ready(uncore_io_htif_0_csr_req_ready),
+ .io_htif_0_csr_req_valid(uncore_io_htif_0_csr_req_valid),
+ .io_htif_0_csr_req_bits_rw(uncore_io_htif_0_csr_req_bits_rw),
+ .io_htif_0_csr_req_bits_addr(uncore_io_htif_0_csr_req_bits_addr),
+ .io_htif_0_csr_req_bits_data(uncore_io_htif_0_csr_req_bits_data),
+ .io_htif_0_csr_resp_ready(uncore_io_htif_0_csr_resp_ready),
+ .io_htif_0_csr_resp_valid(uncore_io_htif_0_csr_resp_valid),
+ .io_htif_0_csr_resp_bits(uncore_io_htif_0_csr_resp_bits),
+ .io_htif_0_debug_stats_csr(uncore_io_htif_0_debug_stats_csr),
+ .io_mem_backup_ctrl_en(uncore_io_mem_backup_ctrl_en),
+ .io_mem_backup_ctrl_in_valid(uncore_io_mem_backup_ctrl_in_valid),
+ .io_mem_backup_ctrl_out_ready(uncore_io_mem_backup_ctrl_out_ready),
+ .io_mem_backup_ctrl_out_valid(uncore_io_mem_backup_ctrl_out_valid),
+ .io_mmio_aw_ready(uncore_io_mmio_aw_ready),
+ .io_mmio_aw_valid(uncore_io_mmio_aw_valid),
+ .io_mmio_aw_bits_addr(uncore_io_mmio_aw_bits_addr),
+ .io_mmio_aw_bits_len(uncore_io_mmio_aw_bits_len),
+ .io_mmio_aw_bits_size(uncore_io_mmio_aw_bits_size),
+ .io_mmio_aw_bits_burst(uncore_io_mmio_aw_bits_burst),
+ .io_mmio_aw_bits_lock(uncore_io_mmio_aw_bits_lock),
+ .io_mmio_aw_bits_cache(uncore_io_mmio_aw_bits_cache),
+ .io_mmio_aw_bits_prot(uncore_io_mmio_aw_bits_prot),
+ .io_mmio_aw_bits_qos(uncore_io_mmio_aw_bits_qos),
+ .io_mmio_aw_bits_region(uncore_io_mmio_aw_bits_region),
+ .io_mmio_aw_bits_id(uncore_io_mmio_aw_bits_id),
+ .io_mmio_aw_bits_user(uncore_io_mmio_aw_bits_user),
+ .io_mmio_w_ready(uncore_io_mmio_w_ready),
+ .io_mmio_w_valid(uncore_io_mmio_w_valid),
+ .io_mmio_w_bits_data(uncore_io_mmio_w_bits_data),
+ .io_mmio_w_bits_last(uncore_io_mmio_w_bits_last),
+ .io_mmio_w_bits_strb(uncore_io_mmio_w_bits_strb),
+ .io_mmio_w_bits_user(uncore_io_mmio_w_bits_user),
+ .io_mmio_b_ready(uncore_io_mmio_b_ready),
+ .io_mmio_b_valid(uncore_io_mmio_b_valid),
+ .io_mmio_b_bits_resp(uncore_io_mmio_b_bits_resp),
+ .io_mmio_b_bits_id(uncore_io_mmio_b_bits_id),
+ .io_mmio_b_bits_user(uncore_io_mmio_b_bits_user),
+ .io_mmio_ar_ready(uncore_io_mmio_ar_ready),
+ .io_mmio_ar_valid(uncore_io_mmio_ar_valid),
+ .io_mmio_ar_bits_addr(uncore_io_mmio_ar_bits_addr),
+ .io_mmio_ar_bits_len(uncore_io_mmio_ar_bits_len),
+ .io_mmio_ar_bits_size(uncore_io_mmio_ar_bits_size),
+ .io_mmio_ar_bits_burst(uncore_io_mmio_ar_bits_burst),
+ .io_mmio_ar_bits_lock(uncore_io_mmio_ar_bits_lock),
+ .io_mmio_ar_bits_cache(uncore_io_mmio_ar_bits_cache),
+ .io_mmio_ar_bits_prot(uncore_io_mmio_ar_bits_prot),
+ .io_mmio_ar_bits_qos(uncore_io_mmio_ar_bits_qos),
+ .io_mmio_ar_bits_region(uncore_io_mmio_ar_bits_region),
+ .io_mmio_ar_bits_id(uncore_io_mmio_ar_bits_id),
+ .io_mmio_ar_bits_user(uncore_io_mmio_ar_bits_user),
+ .io_mmio_r_ready(uncore_io_mmio_r_ready),
+ .io_mmio_r_valid(uncore_io_mmio_r_valid),
+ .io_mmio_r_bits_resp(uncore_io_mmio_r_bits_resp),
+ .io_mmio_r_bits_data(uncore_io_mmio_r_bits_data),
+ .io_mmio_r_bits_last(uncore_io_mmio_r_bits_last),
+ .io_mmio_r_bits_id(uncore_io_mmio_r_bits_id),
+ .io_mmio_r_bits_user(uncore_io_mmio_r_bits_user),
+ .io_dma_0_req_ready(uncore_io_dma_0_req_ready),
+ .io_dma_0_req_valid(uncore_io_dma_0_req_valid),
+ .io_dma_0_req_bits_client_xact_id(uncore_io_dma_0_req_bits_client_xact_id),
+ .io_dma_0_req_bits_cmd(uncore_io_dma_0_req_bits_cmd),
+ .io_dma_0_req_bits_source(uncore_io_dma_0_req_bits_source),
+ .io_dma_0_req_bits_dest(uncore_io_dma_0_req_bits_dest),
+ .io_dma_0_req_bits_length(uncore_io_dma_0_req_bits_length),
+ .io_dma_0_req_bits_size(uncore_io_dma_0_req_bits_size),
+ .io_dma_0_resp_ready(uncore_io_dma_0_resp_ready),
+ .io_dma_0_resp_valid(uncore_io_dma_0_resp_valid),
+ .io_dma_0_resp_bits_client_xact_id(uncore_io_dma_0_resp_bits_client_xact_id),
+ .io_dma_0_resp_bits_status(uncore_io_dma_0_resp_bits_status)
+ );
+ RocketTile T_669 (
+ .clk(T_669_clk),
+ .reset(T_669_reset),
+ .io_cached_0_acquire_ready(T_669_io_cached_0_acquire_ready),
+ .io_cached_0_acquire_valid(T_669_io_cached_0_acquire_valid),
+ .io_cached_0_acquire_bits_addr_block(T_669_io_cached_0_acquire_bits_addr_block),
+ .io_cached_0_acquire_bits_client_xact_id(T_669_io_cached_0_acquire_bits_client_xact_id),
+ .io_cached_0_acquire_bits_addr_beat(T_669_io_cached_0_acquire_bits_addr_beat),
+ .io_cached_0_acquire_bits_is_builtin_type(T_669_io_cached_0_acquire_bits_is_builtin_type),
+ .io_cached_0_acquire_bits_a_type(T_669_io_cached_0_acquire_bits_a_type),
+ .io_cached_0_acquire_bits_union(T_669_io_cached_0_acquire_bits_union),
+ .io_cached_0_acquire_bits_data(T_669_io_cached_0_acquire_bits_data),
+ .io_cached_0_grant_ready(T_669_io_cached_0_grant_ready),
+ .io_cached_0_grant_valid(T_669_io_cached_0_grant_valid),
+ .io_cached_0_grant_bits_addr_beat(T_669_io_cached_0_grant_bits_addr_beat),
+ .io_cached_0_grant_bits_client_xact_id(T_669_io_cached_0_grant_bits_client_xact_id),
+ .io_cached_0_grant_bits_manager_xact_id(T_669_io_cached_0_grant_bits_manager_xact_id),
+ .io_cached_0_grant_bits_is_builtin_type(T_669_io_cached_0_grant_bits_is_builtin_type),
+ .io_cached_0_grant_bits_g_type(T_669_io_cached_0_grant_bits_g_type),
+ .io_cached_0_grant_bits_data(T_669_io_cached_0_grant_bits_data),
+ .io_cached_0_probe_ready(T_669_io_cached_0_probe_ready),
+ .io_cached_0_probe_valid(T_669_io_cached_0_probe_valid),
+ .io_cached_0_probe_bits_addr_block(T_669_io_cached_0_probe_bits_addr_block),
+ .io_cached_0_probe_bits_p_type(T_669_io_cached_0_probe_bits_p_type),
+ .io_cached_0_release_ready(T_669_io_cached_0_release_ready),
+ .io_cached_0_release_valid(T_669_io_cached_0_release_valid),
+ .io_cached_0_release_bits_addr_beat(T_669_io_cached_0_release_bits_addr_beat),
+ .io_cached_0_release_bits_addr_block(T_669_io_cached_0_release_bits_addr_block),
+ .io_cached_0_release_bits_client_xact_id(T_669_io_cached_0_release_bits_client_xact_id),
+ .io_cached_0_release_bits_voluntary(T_669_io_cached_0_release_bits_voluntary),
+ .io_cached_0_release_bits_r_type(T_669_io_cached_0_release_bits_r_type),
+ .io_cached_0_release_bits_data(T_669_io_cached_0_release_bits_data),
+ .io_uncached_0_acquire_ready(T_669_io_uncached_0_acquire_ready),
+ .io_uncached_0_acquire_valid(T_669_io_uncached_0_acquire_valid),
+ .io_uncached_0_acquire_bits_addr_block(T_669_io_uncached_0_acquire_bits_addr_block),
+ .io_uncached_0_acquire_bits_client_xact_id(T_669_io_uncached_0_acquire_bits_client_xact_id),
+ .io_uncached_0_acquire_bits_addr_beat(T_669_io_uncached_0_acquire_bits_addr_beat),
+ .io_uncached_0_acquire_bits_is_builtin_type(T_669_io_uncached_0_acquire_bits_is_builtin_type),
+ .io_uncached_0_acquire_bits_a_type(T_669_io_uncached_0_acquire_bits_a_type),
+ .io_uncached_0_acquire_bits_union(T_669_io_uncached_0_acquire_bits_union),
+ .io_uncached_0_acquire_bits_data(T_669_io_uncached_0_acquire_bits_data),
+ .io_uncached_0_grant_ready(T_669_io_uncached_0_grant_ready),
+ .io_uncached_0_grant_valid(T_669_io_uncached_0_grant_valid),
+ .io_uncached_0_grant_bits_addr_beat(T_669_io_uncached_0_grant_bits_addr_beat),
+ .io_uncached_0_grant_bits_client_xact_id(T_669_io_uncached_0_grant_bits_client_xact_id),
+ .io_uncached_0_grant_bits_manager_xact_id(T_669_io_uncached_0_grant_bits_manager_xact_id),
+ .io_uncached_0_grant_bits_is_builtin_type(T_669_io_uncached_0_grant_bits_is_builtin_type),
+ .io_uncached_0_grant_bits_g_type(T_669_io_uncached_0_grant_bits_g_type),
+ .io_uncached_0_grant_bits_data(T_669_io_uncached_0_grant_bits_data),
+ .io_host_reset(T_669_io_host_reset),
+ .io_host_id(T_669_io_host_id),
+ .io_host_csr_req_ready(T_669_io_host_csr_req_ready),
+ .io_host_csr_req_valid(T_669_io_host_csr_req_valid),
+ .io_host_csr_req_bits_rw(T_669_io_host_csr_req_bits_rw),
+ .io_host_csr_req_bits_addr(T_669_io_host_csr_req_bits_addr),
+ .io_host_csr_req_bits_data(T_669_io_host_csr_req_bits_data),
+ .io_host_csr_resp_ready(T_669_io_host_csr_resp_ready),
+ .io_host_csr_resp_valid(T_669_io_host_csr_resp_valid),
+ .io_host_csr_resp_bits(T_669_io_host_csr_resp_bits),
+ .io_host_debug_stats_csr(T_669_io_host_debug_stats_csr),
+ .io_dma_req_ready(T_669_io_dma_req_ready),
+ .io_dma_req_valid(T_669_io_dma_req_valid),
+ .io_dma_req_bits_client_xact_id(T_669_io_dma_req_bits_client_xact_id),
+ .io_dma_req_bits_cmd(T_669_io_dma_req_bits_cmd),
+ .io_dma_req_bits_source(T_669_io_dma_req_bits_source),
+ .io_dma_req_bits_dest(T_669_io_dma_req_bits_dest),
+ .io_dma_req_bits_length(T_669_io_dma_req_bits_length),
+ .io_dma_req_bits_size(T_669_io_dma_req_bits_size),
+ .io_dma_resp_ready(T_669_io_dma_resp_ready),
+ .io_dma_resp_valid(T_669_io_dma_resp_valid),
+ .io_dma_resp_bits_client_xact_id(T_669_io_dma_resp_bits_client_xact_id),
+ .io_dma_resp_bits_status(T_669_io_dma_resp_bits_status)
+ );
+ Queue_124 T_677 (
+ .clk(T_677_clk),
+ .reset(T_677_reset),
+ .io_enq_ready(T_677_io_enq_ready),
+ .io_enq_valid(T_677_io_enq_valid),
+ .io_enq_bits_rw(T_677_io_enq_bits_rw),
+ .io_enq_bits_addr(T_677_io_enq_bits_addr),
+ .io_enq_bits_data(T_677_io_enq_bits_data),
+ .io_deq_ready(T_677_io_deq_ready),
+ .io_deq_valid(T_677_io_deq_valid),
+ .io_deq_bits_rw(T_677_io_deq_bits_rw),
+ .io_deq_bits_addr(T_677_io_deq_bits_addr),
+ .io_deq_bits_data(T_677_io_deq_bits_data),
+ .io_count(T_677_io_count)
+ );
+ Queue_125 T_679 (
+ .clk(T_679_clk),
+ .reset(T_679_reset),
+ .io_enq_ready(T_679_io_enq_ready),
+ .io_enq_valid(T_679_io_enq_valid),
+ .io_enq_bits(T_679_io_enq_bits),
+ .io_deq_ready(T_679_io_deq_ready),
+ .io_deq_valid(T_679_io_deq_valid),
+ .io_deq_bits(T_679_io_deq_bits),
+ .io_count(T_679_io_count)
+ );
+ Queue_36 T_692 (
+ .clk(T_692_clk),
+ .reset(T_692_reset),
+ .io_enq_ready(T_692_io_enq_ready),
+ .io_enq_valid(T_692_io_enq_valid),
+ .io_enq_bits_addr(T_692_io_enq_bits_addr),
+ .io_enq_bits_len(T_692_io_enq_bits_len),
+ .io_enq_bits_size(T_692_io_enq_bits_size),
+ .io_enq_bits_burst(T_692_io_enq_bits_burst),
+ .io_enq_bits_lock(T_692_io_enq_bits_lock),
+ .io_enq_bits_cache(T_692_io_enq_bits_cache),
+ .io_enq_bits_prot(T_692_io_enq_bits_prot),
+ .io_enq_bits_qos(T_692_io_enq_bits_qos),
+ .io_enq_bits_region(T_692_io_enq_bits_region),
+ .io_enq_bits_id(T_692_io_enq_bits_id),
+ .io_enq_bits_user(T_692_io_enq_bits_user),
+ .io_deq_ready(T_692_io_deq_ready),
+ .io_deq_valid(T_692_io_deq_valid),
+ .io_deq_bits_addr(T_692_io_deq_bits_addr),
+ .io_deq_bits_len(T_692_io_deq_bits_len),
+ .io_deq_bits_size(T_692_io_deq_bits_size),
+ .io_deq_bits_burst(T_692_io_deq_bits_burst),
+ .io_deq_bits_lock(T_692_io_deq_bits_lock),
+ .io_deq_bits_cache(T_692_io_deq_bits_cache),
+ .io_deq_bits_prot(T_692_io_deq_bits_prot),
+ .io_deq_bits_qos(T_692_io_deq_bits_qos),
+ .io_deq_bits_region(T_692_io_deq_bits_region),
+ .io_deq_bits_id(T_692_io_deq_bits_id),
+ .io_deq_bits_user(T_692_io_deq_bits_user),
+ .io_count(T_692_io_count)
+ );
+ Queue_36 T_705 (
+ .clk(T_705_clk),
+ .reset(T_705_reset),
+ .io_enq_ready(T_705_io_enq_ready),
+ .io_enq_valid(T_705_io_enq_valid),
+ .io_enq_bits_addr(T_705_io_enq_bits_addr),
+ .io_enq_bits_len(T_705_io_enq_bits_len),
+ .io_enq_bits_size(T_705_io_enq_bits_size),
+ .io_enq_bits_burst(T_705_io_enq_bits_burst),
+ .io_enq_bits_lock(T_705_io_enq_bits_lock),
+ .io_enq_bits_cache(T_705_io_enq_bits_cache),
+ .io_enq_bits_prot(T_705_io_enq_bits_prot),
+ .io_enq_bits_qos(T_705_io_enq_bits_qos),
+ .io_enq_bits_region(T_705_io_enq_bits_region),
+ .io_enq_bits_id(T_705_io_enq_bits_id),
+ .io_enq_bits_user(T_705_io_enq_bits_user),
+ .io_deq_ready(T_705_io_deq_ready),
+ .io_deq_valid(T_705_io_deq_valid),
+ .io_deq_bits_addr(T_705_io_deq_bits_addr),
+ .io_deq_bits_len(T_705_io_deq_bits_len),
+ .io_deq_bits_size(T_705_io_deq_bits_size),
+ .io_deq_bits_burst(T_705_io_deq_bits_burst),
+ .io_deq_bits_lock(T_705_io_deq_bits_lock),
+ .io_deq_bits_cache(T_705_io_deq_bits_cache),
+ .io_deq_bits_prot(T_705_io_deq_bits_prot),
+ .io_deq_bits_qos(T_705_io_deq_bits_qos),
+ .io_deq_bits_region(T_705_io_deq_bits_region),
+ .io_deq_bits_id(T_705_io_deq_bits_id),
+ .io_deq_bits_user(T_705_io_deq_bits_user),
+ .io_count(T_705_io_count)
+ );
+ Queue_74 T_711 (
+ .clk(T_711_clk),
+ .reset(T_711_reset),
+ .io_enq_ready(T_711_io_enq_ready),
+ .io_enq_valid(T_711_io_enq_valid),
+ .io_enq_bits_data(T_711_io_enq_bits_data),
+ .io_enq_bits_last(T_711_io_enq_bits_last),
+ .io_enq_bits_strb(T_711_io_enq_bits_strb),
+ .io_enq_bits_user(T_711_io_enq_bits_user),
+ .io_deq_ready(T_711_io_deq_ready),
+ .io_deq_valid(T_711_io_deq_valid),
+ .io_deq_bits_data(T_711_io_deq_bits_data),
+ .io_deq_bits_last(T_711_io_deq_bits_last),
+ .io_deq_bits_strb(T_711_io_deq_bits_strb),
+ .io_deq_bits_user(T_711_io_deq_bits_user),
+ .io_count(T_711_io_count)
+ );
+ Queue_75 T_718 (
+ .clk(T_718_clk),
+ .reset(T_718_reset),
+ .io_enq_ready(T_718_io_enq_ready),
+ .io_enq_valid(T_718_io_enq_valid),
+ .io_enq_bits_resp(T_718_io_enq_bits_resp),
+ .io_enq_bits_data(T_718_io_enq_bits_data),
+ .io_enq_bits_last(T_718_io_enq_bits_last),
+ .io_enq_bits_id(T_718_io_enq_bits_id),
+ .io_enq_bits_user(T_718_io_enq_bits_user),
+ .io_deq_ready(T_718_io_deq_ready),
+ .io_deq_valid(T_718_io_deq_valid),
+ .io_deq_bits_resp(T_718_io_deq_bits_resp),
+ .io_deq_bits_data(T_718_io_deq_bits_data),
+ .io_deq_bits_last(T_718_io_deq_bits_last),
+ .io_deq_bits_id(T_718_io_deq_bits_id),
+ .io_deq_bits_user(T_718_io_deq_bits_user),
+ .io_count(T_718_io_count)
+ );
+ Queue_76 T_723 (
+ .clk(T_723_clk),
+ .reset(T_723_reset),
+ .io_enq_ready(T_723_io_enq_ready),
+ .io_enq_valid(T_723_io_enq_valid),
+ .io_enq_bits_resp(T_723_io_enq_bits_resp),
+ .io_enq_bits_id(T_723_io_enq_bits_id),
+ .io_enq_bits_user(T_723_io_enq_bits_user),
+ .io_deq_ready(T_723_io_deq_ready),
+ .io_deq_valid(T_723_io_deq_valid),
+ .io_deq_bits_resp(T_723_io_deq_bits_resp),
+ .io_deq_bits_id(T_723_io_deq_bits_id),
+ .io_deq_bits_user(T_723_io_deq_bits_user),
+ .io_count(T_723_io_count)
+ );
+ NastiErrorSlave_40 errslave (
+ .clk(errslave_clk),
+ .reset(errslave_reset),
+ .io_aw_ready(errslave_io_aw_ready),
+ .io_aw_valid(errslave_io_aw_valid),
+ .io_aw_bits_addr(errslave_io_aw_bits_addr),
+ .io_aw_bits_len(errslave_io_aw_bits_len),
+ .io_aw_bits_size(errslave_io_aw_bits_size),
+ .io_aw_bits_burst(errslave_io_aw_bits_burst),
+ .io_aw_bits_lock(errslave_io_aw_bits_lock),
+ .io_aw_bits_cache(errslave_io_aw_bits_cache),
+ .io_aw_bits_prot(errslave_io_aw_bits_prot),
+ .io_aw_bits_qos(errslave_io_aw_bits_qos),
+ .io_aw_bits_region(errslave_io_aw_bits_region),
+ .io_aw_bits_id(errslave_io_aw_bits_id),
+ .io_aw_bits_user(errslave_io_aw_bits_user),
+ .io_w_ready(errslave_io_w_ready),
+ .io_w_valid(errslave_io_w_valid),
+ .io_w_bits_data(errslave_io_w_bits_data),
+ .io_w_bits_last(errslave_io_w_bits_last),
+ .io_w_bits_strb(errslave_io_w_bits_strb),
+ .io_w_bits_user(errslave_io_w_bits_user),
+ .io_b_ready(errslave_io_b_ready),
+ .io_b_valid(errslave_io_b_valid),
+ .io_b_bits_resp(errslave_io_b_bits_resp),
+ .io_b_bits_id(errslave_io_b_bits_id),
+ .io_b_bits_user(errslave_io_b_bits_user),
+ .io_ar_ready(errslave_io_ar_ready),
+ .io_ar_valid(errslave_io_ar_valid),
+ .io_ar_bits_addr(errslave_io_ar_bits_addr),
+ .io_ar_bits_len(errslave_io_ar_bits_len),
+ .io_ar_bits_size(errslave_io_ar_bits_size),
+ .io_ar_bits_burst(errslave_io_ar_bits_burst),
+ .io_ar_bits_lock(errslave_io_ar_bits_lock),
+ .io_ar_bits_cache(errslave_io_ar_bits_cache),
+ .io_ar_bits_prot(errslave_io_ar_bits_prot),
+ .io_ar_bits_qos(errslave_io_ar_bits_qos),
+ .io_ar_bits_region(errslave_io_ar_bits_region),
+ .io_ar_bits_id(errslave_io_ar_bits_id),
+ .io_ar_bits_user(errslave_io_ar_bits_user),
+ .io_r_ready(errslave_io_r_ready),
+ .io_r_valid(errslave_io_r_valid),
+ .io_r_bits_resp(errslave_io_r_bits_resp),
+ .io_r_bits_data(errslave_io_r_bits_data),
+ .io_r_bits_last(errslave_io_r_bits_last),
+ .io_r_bits_id(errslave_io_r_bits_id),
+ .io_r_bits_user(errslave_io_r_bits_user)
+ );
+ assign io_host_clk = uncore_io_host_clk;
+ assign io_host_clk_edge = uncore_io_host_clk_edge;
+ assign io_host_in_ready = uncore_io_host_in_ready;
+ assign io_host_out_valid = uncore_io_host_out_valid;
+ assign io_host_out_bits = uncore_io_host_out_bits;
+ assign io_host_debug_stats_csr = uncore_io_host_debug_stats_csr;
+ assign io_mem_backup_ctrl_out_valid = uncore_io_mem_backup_ctrl_out_valid;
+ assign io_mem_0_aw_valid = T_705_io_deq_valid;
+ assign io_mem_0_aw_bits_addr = T_705_io_deq_bits_addr;
+ assign io_mem_0_aw_bits_len = T_705_io_deq_bits_len;
+ assign io_mem_0_aw_bits_size = T_705_io_deq_bits_size;
+ assign io_mem_0_aw_bits_burst = T_705_io_deq_bits_burst;
+ assign io_mem_0_aw_bits_lock = T_705_io_deq_bits_lock;
+ assign io_mem_0_aw_bits_cache = 4'h3;
+ assign io_mem_0_aw_bits_prot = T_705_io_deq_bits_prot;
+ assign io_mem_0_aw_bits_qos = T_705_io_deq_bits_qos;
+ assign io_mem_0_aw_bits_region = T_705_io_deq_bits_region;
+ assign io_mem_0_aw_bits_id = T_705_io_deq_bits_id;
+ assign io_mem_0_aw_bits_user = T_705_io_deq_bits_user;
+ assign io_mem_0_w_valid = T_711_io_deq_valid;
+ assign io_mem_0_w_bits_data = T_711_io_deq_bits_data;
+ assign io_mem_0_w_bits_last = T_711_io_deq_bits_last;
+ assign io_mem_0_w_bits_strb = T_711_io_deq_bits_strb;
+ assign io_mem_0_w_bits_user = T_711_io_deq_bits_user;
+ assign io_mem_0_b_ready = T_723_io_enq_ready;
+ assign io_mem_0_ar_valid = T_692_io_deq_valid;
+ assign io_mem_0_ar_bits_addr = T_692_io_deq_bits_addr;
+ assign io_mem_0_ar_bits_len = T_692_io_deq_bits_len;
+ assign io_mem_0_ar_bits_size = T_692_io_deq_bits_size;
+ assign io_mem_0_ar_bits_burst = T_692_io_deq_bits_burst;
+ assign io_mem_0_ar_bits_lock = T_692_io_deq_bits_lock;
+ assign io_mem_0_ar_bits_cache = 4'h3;
+ assign io_mem_0_ar_bits_prot = T_692_io_deq_bits_prot;
+ assign io_mem_0_ar_bits_qos = T_692_io_deq_bits_qos;
+ assign io_mem_0_ar_bits_region = T_692_io_deq_bits_region;
+ assign io_mem_0_ar_bits_id = T_692_io_deq_bits_id;
+ assign io_mem_0_ar_bits_user = T_692_io_deq_bits_user;
+ assign io_mem_0_r_ready = T_718_io_enq_ready;
+ assign uncore_clk = clk;
+ assign uncore_reset = reset;
+ assign uncore_io_host_in_valid = io_host_in_valid;
+ assign uncore_io_host_in_bits = io_host_in_bits;
+ assign uncore_io_host_out_ready = io_host_out_ready;
+ assign uncore_io_mem_0_aw_ready = T_705_io_enq_ready;
+ assign uncore_io_mem_0_w_ready = T_711_io_enq_ready;
+ assign uncore_io_mem_0_b_valid = T_723_io_deq_valid;
+ assign uncore_io_mem_0_b_bits_resp = T_723_io_deq_bits_resp;
+ assign uncore_io_mem_0_b_bits_id = T_723_io_deq_bits_id;
+ assign uncore_io_mem_0_b_bits_user = T_723_io_deq_bits_user;
+ assign uncore_io_mem_0_ar_ready = T_692_io_enq_ready;
+ assign uncore_io_mem_0_r_valid = T_718_io_deq_valid;
+ assign uncore_io_mem_0_r_bits_resp = T_718_io_deq_bits_resp;
+ assign uncore_io_mem_0_r_bits_data = T_718_io_deq_bits_data;
+ assign uncore_io_mem_0_r_bits_last = T_718_io_deq_bits_last;
+ assign uncore_io_mem_0_r_bits_id = T_718_io_deq_bits_id;
+ assign uncore_io_mem_0_r_bits_user = T_718_io_deq_bits_user;
+ assign uncore_io_tiles_cached_0_acquire_valid = T_669_io_cached_0_acquire_valid;
+ assign uncore_io_tiles_cached_0_acquire_bits_addr_block = T_669_io_cached_0_acquire_bits_addr_block;
+ assign uncore_io_tiles_cached_0_acquire_bits_client_xact_id = T_669_io_cached_0_acquire_bits_client_xact_id;
+ assign uncore_io_tiles_cached_0_acquire_bits_addr_beat = T_669_io_cached_0_acquire_bits_addr_beat;
+ assign uncore_io_tiles_cached_0_acquire_bits_is_builtin_type = T_669_io_cached_0_acquire_bits_is_builtin_type;
+ assign uncore_io_tiles_cached_0_acquire_bits_a_type = T_669_io_cached_0_acquire_bits_a_type;
+ assign uncore_io_tiles_cached_0_acquire_bits_union = T_669_io_cached_0_acquire_bits_union;
+ assign uncore_io_tiles_cached_0_acquire_bits_data = T_669_io_cached_0_acquire_bits_data;
+ assign uncore_io_tiles_cached_0_grant_ready = T_669_io_cached_0_grant_ready;
+ assign uncore_io_tiles_cached_0_probe_ready = T_669_io_cached_0_probe_ready;
+ assign uncore_io_tiles_cached_0_release_valid = T_669_io_cached_0_release_valid;
+ assign uncore_io_tiles_cached_0_release_bits_addr_beat = T_669_io_cached_0_release_bits_addr_beat;
+ assign uncore_io_tiles_cached_0_release_bits_addr_block = T_669_io_cached_0_release_bits_addr_block;
+ assign uncore_io_tiles_cached_0_release_bits_client_xact_id = T_669_io_cached_0_release_bits_client_xact_id;
+ assign uncore_io_tiles_cached_0_release_bits_voluntary = T_669_io_cached_0_release_bits_voluntary;
+ assign uncore_io_tiles_cached_0_release_bits_r_type = T_669_io_cached_0_release_bits_r_type;
+ assign uncore_io_tiles_cached_0_release_bits_data = T_669_io_cached_0_release_bits_data;
+ assign uncore_io_tiles_uncached_0_acquire_valid = T_669_io_uncached_0_acquire_valid;
+ assign uncore_io_tiles_uncached_0_acquire_bits_addr_block = T_669_io_uncached_0_acquire_bits_addr_block;
+ assign uncore_io_tiles_uncached_0_acquire_bits_client_xact_id = T_669_io_uncached_0_acquire_bits_client_xact_id;
+ assign uncore_io_tiles_uncached_0_acquire_bits_addr_beat = T_669_io_uncached_0_acquire_bits_addr_beat;
+ assign uncore_io_tiles_uncached_0_acquire_bits_is_builtin_type = T_669_io_uncached_0_acquire_bits_is_builtin_type;
+ assign uncore_io_tiles_uncached_0_acquire_bits_a_type = T_669_io_uncached_0_acquire_bits_a_type;
+ assign uncore_io_tiles_uncached_0_acquire_bits_union = T_669_io_uncached_0_acquire_bits_union;
+ assign uncore_io_tiles_uncached_0_acquire_bits_data = T_669_io_uncached_0_acquire_bits_data;
+ assign uncore_io_tiles_uncached_0_grant_ready = T_669_io_uncached_0_grant_ready;
+ assign uncore_io_htif_0_csr_req_ready = T_677_io_enq_ready;
+ assign uncore_io_htif_0_csr_resp_valid = T_679_io_deq_valid;
+ assign uncore_io_htif_0_csr_resp_bits = T_679_io_deq_bits;
+ assign uncore_io_htif_0_debug_stats_csr = T_669_io_host_debug_stats_csr;
+ assign uncore_io_mem_backup_ctrl_en = io_mem_backup_ctrl_en;
+ assign uncore_io_mem_backup_ctrl_in_valid = io_mem_backup_ctrl_in_valid;
+ assign uncore_io_mem_backup_ctrl_out_ready = io_mem_backup_ctrl_out_ready;
+ assign uncore_io_mmio_aw_ready = errslave_io_aw_ready;
+ assign uncore_io_mmio_w_ready = errslave_io_w_ready;
+ assign uncore_io_mmio_b_valid = errslave_io_b_valid;
+ assign uncore_io_mmio_b_bits_resp = errslave_io_b_bits_resp;
+ assign uncore_io_mmio_b_bits_id = errslave_io_b_bits_id;
+ assign uncore_io_mmio_b_bits_user = errslave_io_b_bits_user;
+ assign uncore_io_mmio_ar_ready = errslave_io_ar_ready;
+ assign uncore_io_mmio_r_valid = errslave_io_r_valid;
+ assign uncore_io_mmio_r_bits_resp = errslave_io_r_bits_resp;
+ assign uncore_io_mmio_r_bits_data = errslave_io_r_bits_data;
+ assign uncore_io_mmio_r_bits_last = errslave_io_r_bits_last;
+ assign uncore_io_mmio_r_bits_id = errslave_io_r_bits_id;
+ assign uncore_io_mmio_r_bits_user = errslave_io_r_bits_user;
+ assign uncore_io_dma_0_req_valid = GEN_0;
+ assign uncore_io_dma_0_req_bits_client_xact_id = GEN_1;
+ assign uncore_io_dma_0_req_bits_cmd = GEN_2;
+ assign uncore_io_dma_0_req_bits_source = GEN_3;
+ assign uncore_io_dma_0_req_bits_dest = GEN_4;
+ assign uncore_io_dma_0_req_bits_length = GEN_5;
+ assign uncore_io_dma_0_req_bits_size = GEN_6;
+ assign uncore_io_dma_0_resp_ready = GEN_7;
+ assign T_669_clk = clk;
+ assign T_669_reset = uncore_io_htif_0_reset;
+ assign T_669_io_cached_0_acquire_ready = uncore_io_tiles_cached_0_acquire_ready;
+ assign T_669_io_cached_0_grant_valid = uncore_io_tiles_cached_0_grant_valid;
+ assign T_669_io_cached_0_grant_bits_addr_beat = uncore_io_tiles_cached_0_grant_bits_addr_beat;
+ assign T_669_io_cached_0_grant_bits_client_xact_id = uncore_io_tiles_cached_0_grant_bits_client_xact_id;
+ assign T_669_io_cached_0_grant_bits_manager_xact_id = uncore_io_tiles_cached_0_grant_bits_manager_xact_id;
+ assign T_669_io_cached_0_grant_bits_is_builtin_type = uncore_io_tiles_cached_0_grant_bits_is_builtin_type;
+ assign T_669_io_cached_0_grant_bits_g_type = uncore_io_tiles_cached_0_grant_bits_g_type;
+ assign T_669_io_cached_0_grant_bits_data = uncore_io_tiles_cached_0_grant_bits_data;
+ assign T_669_io_cached_0_probe_valid = uncore_io_tiles_cached_0_probe_valid;
+ assign T_669_io_cached_0_probe_bits_addr_block = uncore_io_tiles_cached_0_probe_bits_addr_block;
+ assign T_669_io_cached_0_probe_bits_p_type = uncore_io_tiles_cached_0_probe_bits_p_type;
+ assign T_669_io_cached_0_release_ready = uncore_io_tiles_cached_0_release_ready;
+ assign T_669_io_uncached_0_acquire_ready = uncore_io_tiles_uncached_0_acquire_ready;
+ assign T_669_io_uncached_0_grant_valid = uncore_io_tiles_uncached_0_grant_valid;
+ assign T_669_io_uncached_0_grant_bits_addr_beat = uncore_io_tiles_uncached_0_grant_bits_addr_beat;
+ assign T_669_io_uncached_0_grant_bits_client_xact_id = uncore_io_tiles_uncached_0_grant_bits_client_xact_id;
+ assign T_669_io_uncached_0_grant_bits_manager_xact_id = uncore_io_tiles_uncached_0_grant_bits_manager_xact_id;
+ assign T_669_io_uncached_0_grant_bits_is_builtin_type = uncore_io_tiles_uncached_0_grant_bits_is_builtin_type;
+ assign T_669_io_uncached_0_grant_bits_g_type = uncore_io_tiles_uncached_0_grant_bits_g_type;
+ assign T_669_io_uncached_0_grant_bits_data = uncore_io_tiles_uncached_0_grant_bits_data;
+ assign T_669_io_host_reset = T_672;
+ assign T_669_io_host_id = 1'h0;
+ assign T_669_io_host_csr_req_valid = T_677_io_deq_valid;
+ assign T_669_io_host_csr_req_bits_rw = T_677_io_deq_bits_rw;
+ assign T_669_io_host_csr_req_bits_addr = T_677_io_deq_bits_addr;
+ assign T_669_io_host_csr_req_bits_data = T_677_io_deq_bits_data;
+ assign T_669_io_host_csr_resp_ready = T_679_io_enq_ready;
+ assign T_669_io_dma_req_ready = GEN_8;
+ assign T_669_io_dma_resp_valid = GEN_9;
+ assign T_669_io_dma_resp_bits_client_xact_id = GEN_10;
+ assign T_669_io_dma_resp_bits_status = GEN_11;
+ assign T_677_clk = clk;
+ assign T_677_reset = reset;
+ assign T_677_io_enq_valid = uncore_io_htif_0_csr_req_valid;
+ assign T_677_io_enq_bits_rw = uncore_io_htif_0_csr_req_bits_rw;
+ assign T_677_io_enq_bits_addr = uncore_io_htif_0_csr_req_bits_addr;
+ assign T_677_io_enq_bits_data = uncore_io_htif_0_csr_req_bits_data;
+ assign T_677_io_deq_ready = T_669_io_host_csr_req_ready;
+ assign T_679_clk = clk;
+ assign T_679_reset = reset;
+ assign T_679_io_enq_valid = T_669_io_host_csr_resp_valid;
+ assign T_679_io_enq_bits = T_669_io_host_csr_resp_bits;
+ assign T_679_io_deq_ready = uncore_io_htif_0_csr_resp_ready;
+ assign T_692_clk = clk;
+ assign T_692_reset = reset;
+ assign T_692_io_enq_valid = uncore_io_mem_0_ar_valid;
+ assign T_692_io_enq_bits_addr = uncore_io_mem_0_ar_bits_addr;
+ assign T_692_io_enq_bits_len = uncore_io_mem_0_ar_bits_len;
+ assign T_692_io_enq_bits_size = uncore_io_mem_0_ar_bits_size;
+ assign T_692_io_enq_bits_burst = uncore_io_mem_0_ar_bits_burst;
+ assign T_692_io_enq_bits_lock = uncore_io_mem_0_ar_bits_lock;
+ assign T_692_io_enq_bits_cache = uncore_io_mem_0_ar_bits_cache;
+ assign T_692_io_enq_bits_prot = uncore_io_mem_0_ar_bits_prot;
+ assign T_692_io_enq_bits_qos = uncore_io_mem_0_ar_bits_qos;
+ assign T_692_io_enq_bits_region = uncore_io_mem_0_ar_bits_region;
+ assign T_692_io_enq_bits_id = uncore_io_mem_0_ar_bits_id;
+ assign T_692_io_enq_bits_user = uncore_io_mem_0_ar_bits_user;
+ assign T_692_io_deq_ready = io_mem_0_ar_ready;
+ assign T_705_clk = clk;
+ assign T_705_reset = reset;
+ assign T_705_io_enq_valid = uncore_io_mem_0_aw_valid;
+ assign T_705_io_enq_bits_addr = uncore_io_mem_0_aw_bits_addr;
+ assign T_705_io_enq_bits_len = uncore_io_mem_0_aw_bits_len;
+ assign T_705_io_enq_bits_size = uncore_io_mem_0_aw_bits_size;
+ assign T_705_io_enq_bits_burst = uncore_io_mem_0_aw_bits_burst;
+ assign T_705_io_enq_bits_lock = uncore_io_mem_0_aw_bits_lock;
+ assign T_705_io_enq_bits_cache = uncore_io_mem_0_aw_bits_cache;
+ assign T_705_io_enq_bits_prot = uncore_io_mem_0_aw_bits_prot;
+ assign T_705_io_enq_bits_qos = uncore_io_mem_0_aw_bits_qos;
+ assign T_705_io_enq_bits_region = uncore_io_mem_0_aw_bits_region;
+ assign T_705_io_enq_bits_id = uncore_io_mem_0_aw_bits_id;
+ assign T_705_io_enq_bits_user = uncore_io_mem_0_aw_bits_user;
+ assign T_705_io_deq_ready = io_mem_0_aw_ready;
+ assign T_711_clk = clk;
+ assign T_711_reset = reset;
+ assign T_711_io_enq_valid = uncore_io_mem_0_w_valid;
+ assign T_711_io_enq_bits_data = uncore_io_mem_0_w_bits_data;
+ assign T_711_io_enq_bits_last = uncore_io_mem_0_w_bits_last;
+ assign T_711_io_enq_bits_strb = uncore_io_mem_0_w_bits_strb;
+ assign T_711_io_enq_bits_user = uncore_io_mem_0_w_bits_user;
+ assign T_711_io_deq_ready = io_mem_0_w_ready;
+ assign T_718_clk = clk;
+ assign T_718_reset = reset;
+ assign T_718_io_enq_valid = io_mem_0_r_valid;
+ assign T_718_io_enq_bits_resp = io_mem_0_r_bits_resp;
+ assign T_718_io_enq_bits_data = io_mem_0_r_bits_data;
+ assign T_718_io_enq_bits_last = io_mem_0_r_bits_last;
+ assign T_718_io_enq_bits_id = io_mem_0_r_bits_id;
+ assign T_718_io_enq_bits_user = io_mem_0_r_bits_user;
+ assign T_718_io_deq_ready = uncore_io_mem_0_r_ready;
+ assign T_723_clk = clk;
+ assign T_723_reset = reset;
+ assign T_723_io_enq_valid = io_mem_0_b_valid;
+ assign T_723_io_enq_bits_resp = io_mem_0_b_bits_resp;
+ assign T_723_io_enq_bits_id = io_mem_0_b_bits_id;
+ assign T_723_io_enq_bits_user = io_mem_0_b_bits_user;
+ assign T_723_io_deq_ready = uncore_io_mem_0_b_ready;
+ assign errslave_clk = clk;
+ assign errslave_reset = reset;
+ assign errslave_io_aw_valid = uncore_io_mmio_aw_valid;
+ assign errslave_io_aw_bits_addr = uncore_io_mmio_aw_bits_addr;
+ assign errslave_io_aw_bits_len = uncore_io_mmio_aw_bits_len;
+ assign errslave_io_aw_bits_size = uncore_io_mmio_aw_bits_size;
+ assign errslave_io_aw_bits_burst = uncore_io_mmio_aw_bits_burst;
+ assign errslave_io_aw_bits_lock = uncore_io_mmio_aw_bits_lock;
+ assign errslave_io_aw_bits_cache = uncore_io_mmio_aw_bits_cache;
+ assign errslave_io_aw_bits_prot = uncore_io_mmio_aw_bits_prot;
+ assign errslave_io_aw_bits_qos = uncore_io_mmio_aw_bits_qos;
+ assign errslave_io_aw_bits_region = uncore_io_mmio_aw_bits_region;
+ assign errslave_io_aw_bits_id = uncore_io_mmio_aw_bits_id;
+ assign errslave_io_aw_bits_user = uncore_io_mmio_aw_bits_user;
+ assign errslave_io_w_valid = uncore_io_mmio_w_valid;
+ assign errslave_io_w_bits_data = uncore_io_mmio_w_bits_data;
+ assign errslave_io_w_bits_last = uncore_io_mmio_w_bits_last;
+ assign errslave_io_w_bits_strb = uncore_io_mmio_w_bits_strb;
+ assign errslave_io_w_bits_user = uncore_io_mmio_w_bits_user;
+ assign errslave_io_b_ready = uncore_io_mmio_b_ready;
+ assign errslave_io_ar_valid = uncore_io_mmio_ar_valid;
+ assign errslave_io_ar_bits_addr = uncore_io_mmio_ar_bits_addr;
+ assign errslave_io_ar_bits_len = uncore_io_mmio_ar_bits_len;
+ assign errslave_io_ar_bits_size = uncore_io_mmio_ar_bits_size;
+ assign errslave_io_ar_bits_burst = uncore_io_mmio_ar_bits_burst;
+ assign errslave_io_ar_bits_lock = uncore_io_mmio_ar_bits_lock;
+ assign errslave_io_ar_bits_cache = uncore_io_mmio_ar_bits_cache;
+ assign errslave_io_ar_bits_prot = uncore_io_mmio_ar_bits_prot;
+ assign errslave_io_ar_bits_qos = uncore_io_mmio_ar_bits_qos;
+ assign errslave_io_ar_bits_region = uncore_io_mmio_ar_bits_region;
+ assign errslave_io_ar_bits_id = uncore_io_mmio_ar_bits_id;
+ assign errslave_io_ar_bits_user = uncore_io_mmio_ar_bits_user;
+ assign errslave_io_r_ready = uncore_io_mmio_r_ready;
+`ifndef SYNTHESIS
+ integer initvar;
+ initial begin
+ #0.002;
+ T_671 = {1{$random}};
+ T_672 = {1{$random}};
+ GEN_0 = {1{$random}};
+ GEN_1 = {1{$random}};
+ GEN_2 = {1{$random}};
+ GEN_3 = {1{$random}};
+ GEN_4 = {1{$random}};
+ GEN_5 = {1{$random}};
+ GEN_6 = {1{$random}};
+ GEN_7 = {1{$random}};
+ GEN_8 = {1{$random}};
+ GEN_9 = {1{$random}};
+ GEN_10 = {1{$random}};
+ GEN_11 = {1{$random}};
+ end
+`endif
+ always @(posedge clk) begin
+ if(1'h0) begin
+ ;
+ end else begin
+ T_671 <= uncore_io_htif_0_reset;
+ end
+ if(1'h0) begin
+ ;
+ end else begin
+ T_672 <= T_671;
+ end
+ end
+endmodule
diff --git a/regress/rocket.fir b/regress/rocket.fir
index debd6af4..adc4bb4d 100644
--- a/regress/rocket.fir
+++ b/regress/rocket.fir
@@ -17900,7 +17900,7 @@ circuit Top :
T_7824 <= T_7823
node T_7826 = eq(reset, UInt<1>("h00"))
when T_7826 :
- printf(clk, UInt<1>(1), "C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n ", io.host.id, T_7816, wb_valid, wb_reg_pc, T_7818, rf_wdata, rf_wen, T_7819, T_7821, T_7822, T_7824, wb_reg_inst, wb_reg_inst)
+ printf(clk, UInt<1>(1), "C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", io.host.id, T_7816, wb_valid, wb_reg_pc, T_7818, rf_wdata, rf_wen, T_7819, T_7821, T_7822, T_7824, wb_reg_inst, wb_reg_inst)
skip
module BTB :
diff --git a/src/test/resources/regress b/src/test/resources/regress
new file mode 120000
index 00000000..3691434b
--- /dev/null
+++ b/src/test/resources/regress
@@ -0,0 +1 @@
+../../../regress \ No newline at end of file
diff --git a/src/test/scala/firrtlTests/Regress.scala b/src/test/scala/firrtlTests/Regress.scala
new file mode 100644
index 00000000..49c95590
--- /dev/null
+++ b/src/test/scala/firrtlTests/Regress.scala
@@ -0,0 +1,23 @@
+
+package firrtlTests
+
+import org.scalatest._
+
+import firrtl._
+import java.io._
+import scala.io.Source
+
+class RocketRegressionSpec extends FlatSpec with Matchers {
+
+ // This test is temporary until we move to simulation-based testing
+ "CHIRRTL Rocket" should "match expected Verilog" in {
+ val firrtlSource = Source.fromURL(getClass.getResource("/regress/rocket.fir"))
+ val highCircuit = firrtl.Parser.parse("rocket.fir", firrtlSource.getLines)
+ val verilogSW = new StringWriter()
+ VerilogCompiler.run(highCircuit, verilogSW)
+
+ val goldenVerilog = Source.fromURL(getClass.getResource("/regress/rocket-golden.v"))
+
+ verilogSW.toString shouldEqual goldenVerilog.mkString
+ }
+}
generated by cgit v1.2.3 (git 2.25.1) at 2026-03-09 11:11:09 +0000