Finished Split Expressions

3 files changed, 74 insertions, 3 deletions

diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 18f75b2c..1dd3a57b 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -1906,6 +1906,31 @@ defn inline-instances (c:Circuit) :
    Circuit(list(Module(name(top),ports(top),inline-inst(body(top)))),main(c))
 
 
+;================= Split Expressions ========================
+; Inteded to only work on low firrtl
+
+defn split-exp (c:Circuit) :
+   defn split-exp-s (s:Stmt,v:Vector<Stmt>) -> False :
+      match(s) :
+         (s:Begin) : 
+            defn f (s:Stmt) -> False: split-exp-s(s,v)
+            do(f,s)
+         (s:Conditionally) : error("Shouldn't be here")
+         (s) : add(v,map(split-exp-e{_,v},s))
+      false
+   defn split-exp-e (e:Expression,v:Vector<Stmt>) -> Expression :
+      match(map(split-exp-e{_,v},e)):
+         (e:Subfield|DoPrim|ReadPort|Register) : 
+            val n = gensym(`T)
+            add(v,DefNode(n,e))
+            WRef(n,type(e),NodeKind(),UNKNOWN-GENDER)
+         (e) : e
+
+   Circuit{_,main(c)} $
+      for m in modules(c) map :
+         val v = Vector<Stmt>()
+         split-exp-s(body(m),v)
+         Module(name(m),ports(m),Begin(to-list(v)))
 
 ;================= Bring to Real IR ========================
 ; Returns a new Circuit with only real IR nodes.
@@ -1956,8 +1981,9 @@ public defn run-passes (c: Circuit, p: List<Char>) :
    if contains(p,'p') : do-stage("Initialize Registers", initialize-registers)
    if contains(p,'j') : do-stage("Expand Whens", expand-whens)
    if contains(p,'k') : do-stage("Infer Widths", infer-widths)
-   if contains(p,'n') : do-stage("Inline Instances", inline-instances)
-   ;if contains(p,'n') : do-stage("Pad Widths", pad-widths)
+   if contains(p,'l') : do-stage("Inline Instances", inline-instances)
+   if contains(p,'m') : do-stage("Split Expressions", split-exp)
+   if contains(p,'n') : do-stage("Real IR", to-real-ir)
 
    println("Done!")
 
diff --git a/test/passes/inline/gcd.fir b/test/passes/inline/gcd.fir
index d2e843e6..bf6f87ab 100644
--- a/test/passes/inline/gcd.fir
+++ b/test/passes/inline/gcd.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl %s abcefghipjkn c | tee %s.out | FileCheck %s
+; RUN: firrtl %s abcefghipjkl c | tee %s.out | FileCheck %s
 
 ;CHECK: Inline Instances
 circuit top :
diff --git a/test/passes/split-exp/gcd.fir b/test/passes/split-exp/gcd.fir
new file mode 100644
index 00000000..a659aa07
--- /dev/null
+++ b/test/passes/split-exp/gcd.fir
@@ -0,0 +1,45 @@
+; RUN: firrtl %s abcefghipjklm c | tee %s.out | FileCheck %s
+
+;CHECK: Split Expressions
+circuit top :
+   module subtracter :
+      input x : UInt
+      input y : UInt
+      output q : UInt
+      q := sub-wrap-uu(x, y)
+   module gcd :
+      input a : UInt(16)
+      input b : UInt(16)
+      input e : UInt(1)
+      output z : UInt(16)
+      output v : UInt(1)
+      reg x : UInt
+      reg y : UInt
+      x.init := UInt(0)
+      y.init := UInt(42)
+      when gt-uu(x, y) :
+         inst s of subtracter
+         s.x := x
+         s.y := y
+         x := s.q
+      else :
+         inst s2 of subtracter
+         s2.x := x
+         s2.y := y
+         y := s2.q
+      when e :
+         x := a
+         y := b
+      v := equal-uu(v, UInt(0))
+      z := x
+   module top :
+      input a : UInt(16)
+      input b : UInt(16)
+      output z : UInt
+      inst i of gcd
+      i.a := a
+      i.b := b
+      i.e := UInt(1)
+      z := i.z
+
+; CHECK: Finished Split Expressions