sfcX/test/riscv-mini, branch master Scala FIRRTL Compiler for chiselX Changed all tests to use verilog backend. 2015-08-24T18:45:37+00:00 azidar 2015-08-24T18:45:37+00:00 5d3061bfed8445370e6fa97ec9238ba49e8fafbc 






Pass most tests. The ones that do not pass are not expected to, yet
2015-07-14T18:29:55+00:00

azidar

2015-07-07T17:13:29+00:00

d696dd01de8a1a83a376c719490f475be991f387












Fixed verilog backend bugs. Passes ALU. Fails Datapath
2015-06-04T03:39:41+00:00

azidar

2015-06-04T03:39:41+00:00

887d785ecc2ba7c363194cef89b72bc026c81cf9












Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve correct low-firrtl syntax. Generates verilog that compiles, but is not correct
2015-06-02T22:35:02+00:00

azidar

2015-06-02T22:35:02+00:00

eb5ca3c967c929c8331fd17e04dbd9402e41e986












Added sequential/combinational memories. Started debugging verilog backend. Added Long support so UInt(LARGENUMBER) works
2015-06-02T17:41:27+00:00

azidar

2015-06-02T17:41:27+00:00

f8f9de58dbba5e53193246a5fd2145dfe6537e10