sfcX/test/passes/to-verilog, branch master

Remove stanza (#231)

2016-08-15T17:32:41+00:00

* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)

Fixed printf bugs in scala and stanza versions. Required special casing prints in SplitExp, and emitting expressions instead of their toString counterparts

2016-02-25T06:40:28+00:00

Escape quotes in strings before emitting as Verilog

2016-02-09T01:28:09+00:00

Without this we get failures with the current rocket-chip, when there are
assertions with escaped strings in them.

Fixed rdwr and wr to verilog tests

2016-01-28T17:38:07+00:00

Added tests for previous commit

2016-01-28T17:25:04+00:00

Updated all tests to pass

2016-01-28T17:25:04+00:00

Fixed additional tests and inferring rdwr ports in chirrtl

2016-01-27T19:28:37+00:00

Changed tests to pass with change to postfix of generated name

2016-01-25T19:29:45+00:00

Fixed tests that broke from changing verilog backend and removing mask from write mport declaration

2016-01-25T00:36:13+00:00

WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadblock in assigning clocked ports

2016-01-16T22:28:17+00:00