sfcX/test/passes/resolve-genders, branch master Scala FIRRTL Compiler for chiselX Remove stanza (#231) 2016-08-15T17:32:41+00:00 Adam Izraelevitz 2016-08-15T17:32:41+00:00 bebd04c4c68c320b2b72325e348c726dc33beae6 * Removed stanza implementation/tests. In the future we can move the stanza tests over, but for now they should be deleted. * Added back integration .fir files * Added Makefile to give Travis hooks * Added firrtl script (was ignored before) 
* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)
Updated all tests to pass 2016-01-28T17:25:04+00:00 azidar 2016-01-26T22:18:34+00:00 5ab30c681558d2a26000696e518ee5b28deb1303 






WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadblock in assigning clocked ports
2016-01-16T22:28:17+00:00

azidar

2015-12-12T22:37:41+00:00

28e4c6a09011cafdd1e3533118f7c3499e0d3dc6












New memory works with verilog. Slowly changing tests and fixing bugs.
2016-01-16T22:28:17+00:00

azidar

2015-12-10T02:31:45+00:00

be78d49aa01c097978f69a3b022acb2047fdf438

Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables





Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables







WIP need to correctly output readwrite ports
2016-01-16T22:28:16+00:00

azidar

2015-10-26T22:12:42+00:00

50ef3c4aa6c0ce8edb3f9d3fa7ac6bb5d081de7f












Changed all tests to use verilog backend.
2015-08-24T18:45:37+00:00

azidar

2015-08-24T18:45:37+00:00

5d3061bfed8445370e6fa97ec9238ba49e8fafbc












Updated tests to pipe from stderr to stdout
2015-07-31T23:05:53+00:00

azidar

2015-07-31T23:05:53+00:00

d5cc3210aabf7b4d69e2f3c5ed45c9c097c3ebdf












Added tests for clocks. Added remove scope and special chars passes. Added tests. Made more tests pass
2015-07-14T18:29:55+00:00

azidar

2015-07-13T23:22:43+00:00

271e1bf5ed56847c1ce7d50bdb7f1db9ccc5ea55












Pass most tests. The ones that do not pass are not expected to, yet
2015-07-14T18:29:55+00:00

azidar

2015-07-07T17:13:29+00:00

d696dd01de8a1a83a376c719490f475be991f387












First pass at a Verilog Backend. Not tested, but compiles and generates reasonable verilog. Requires inlining, future versions will instantiate modules
2015-05-19T03:33:23+00:00

azidar

2015-05-19T03:33:23+00:00

14bb9cda8352388bcd33ba9ca2700805dc51639f