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<title>sfcX/test/passes/lower-to-ground, branch master</title>
<subtitle>Scala FIRRTL Compiler for chiselX</subtitle>
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<entry>
<title>Remove stanza (#231)</title>
<updated>2016-08-15T17:32:41+00:00</updated>
<author>
<name>Adam Izraelevitz</name>
</author>
<published>2016-08-15T17:32:41+00:00</published>
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* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)
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* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)
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<entry>
<title>Changed stanza output of UInt/SInt to include widths. Made tests match accordingly</title>
<updated>2016-02-10T02:57:06+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2016-01-31T20:59:31+00:00</published>
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<entry>
<title>Added addw to working ir as an optimized verilog emission</title>
<updated>2016-01-28T17:25:04+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2016-01-27T22:18:09+00:00</published>
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<entry>
<title>Updated all tests to pass</title>
<updated>2016-01-28T17:25:04+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2016-01-26T22:18:34+00:00</published>
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<entry>
<title>Changed tests to pass with change to postfix of generated name</title>
<updated>2016-01-25T19:29:45+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2016-01-25T19:29:45+00:00</published>
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<entry>
<title>Added DefMemory to CInfer Types</title>
<updated>2016-01-24T22:13:52+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2016-01-24T22:13:52+00:00</published>
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<entry>
<title>Fixed a bunch of tests, and minor bugs</title>
<updated>2016-01-16T22:28:18+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2016-01-08T01:15:31+00:00</published>
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<entry>
<title>WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadblock in assigning clocked ports</title>
<updated>2016-01-16T22:28:17+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2015-12-12T22:37:41+00:00</published>
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<entry>
<title>New memory works with verilog. Slowly changing tests and fixing bugs.</title>
<updated>2016-01-16T22:28:17+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2015-12-10T02:31:45+00:00</published>
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Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
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Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
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</entry>
<entry>
<title>Fixed final bug. All tests pass. Accessors are a go.</title>
<updated>2015-09-30T03:38:47+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2015-09-30T03:38:47+00:00</published>
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