sfcX/test/passes/jacktest, branch 1.6.x Scala FIRRTL Compiler for chiselX Remove stanza (#231) 2016-08-15T17:32:41+00:00 Adam Izraelevitz 2016-08-15T17:32:41+00:00 bebd04c4c68c320b2b72325e348c726dc33beae6 * Removed stanza implementation/tests. In the future we can move the stanza tests over, but for now they should be deleted. * Added back integration .fir files * Added Makefile to give Travis hooks * Added firrtl script (was ignored before) 
* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)
Fixed bug where subaccess indexes were being classified as female, 2016-01-28T17:25:05+00:00 azidar 2016-01-28T00:28:53+00:00 b37f91017c9a8ad2800b97a9f27cbc94de0c82f5 mucking up the chirrtl->firrtl transform. #56. 
mucking up the chirrtl->firrtl transform. #56.
Changed rmode to wmode 2016-01-28T17:25:05+00:00 azidar 2016-01-27T23:59:48+00:00 cfedffd1fc7d5846e9f633bf13ea194b8ab2293d 






Updated all tests to pass
2016-01-28T17:25:04+00:00

azidar

2016-01-26T22:18:34+00:00

5ab30c681558d2a26000696e518ee5b28deb1303












Fixed bug where poisons were not being declared
2016-01-26T00:20:12+00:00

azidar

2016-01-26T00:20:12+00:00

84d9509cb943c859a2d469c56d8973a5efded071












Fixed support for muxes and nodes with passive aggregate types
2016-01-25T19:35:28+00:00

azidar

2016-01-25T19:35:28+00:00

7eba69618f681ec9ce817ef53d8cad226094ab9c












Fixed tests that broke from changing verilog backend and removing mask from write mport declaration
2016-01-25T00:36:13+00:00

azidar

2016-01-25T00:36:13+00:00

5cb43f0cb9ff16a448f8f7b76698b569d2d63125












Finished first cut at new firrtl - time for testing! Chirrtl requires masks to be specified with write and rdwr mports
2016-01-16T22:28:18+00:00

azidar

2016-01-08T23:51:41+00:00

168843e45656b3569461f496b85def20b70779d2












Fixed a bunch of tests, and minor bugs
2016-01-16T22:28:18+00:00

azidar

2016-01-08T01:15:31+00:00

4569194392122ae4715549b2f0b9fffff051b278












New memory works with verilog. Slowly changing tests and fixing bugs.
2016-01-16T22:28:17+00:00

azidar

2015-12-10T02:31:45+00:00

be78d49aa01c097978f69a3b022acb2047fdf438

Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables





Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables