sfcX/test/passes/expand-whens, branch master Scala FIRRTL Compiler for chiselX Remove stanza (#231) 2016-08-15T17:32:41+00:00 Adam Izraelevitz 2016-08-15T17:32:41+00:00 bebd04c4c68c320b2b72325e348c726dc33beae6 * Removed stanza implementation/tests. In the future we can move the stanza tests over, but for now they should be deleted. * Added back integration .fir files * Added Makefile to give Travis hooks * Added firrtl script (was ignored before) 
* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)
Changed stanza output of UInt/SInt to include widths. Made tests match accordingly 2016-02-10T02:57:06+00:00 azidar 2016-01-31T20:59:31+00:00 e985d47312458459e9ebe42fe99b5a063c08e637 






Updated all tests to pass
2016-01-28T17:25:04+00:00

azidar

2016-01-26T22:18:34+00:00

5ab30c681558d2a26000696e518ee5b28deb1303












BIT-AND, BIT-OR, and BIT-XOR now can accept SInts. Fixed tests
2016-01-17T22:42:04+00:00

azidar

2016-01-17T22:42:04+00:00

427898760862bc4c0910f8194fed2260a29315cc












Fixed all tests so they either pass are marked as expected failures
2016-01-16T23:24:04+00:00

azidar

2016-01-16T23:24:04+00:00

c4271d9e428bba7b447ed6d18fb11729d2b61b22












WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadblock in assigning clocked ports
2016-01-16T22:28:17+00:00

azidar

2015-12-12T22:37:41+00:00

28e4c6a09011cafdd1e3533118f7c3499e0d3dc6












New memory works with verilog. Slowly changing tests and fixing bugs.
2016-01-16T22:28:17+00:00

azidar

2015-12-10T02:31:45+00:00

be78d49aa01c097978f69a3b022acb2047fdf438

Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables





Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables







Merge pull request #43 from ucb-bar/new-semantics
2015-10-01T22:24:06+00:00

Andrew Waterman

2015-10-01T22:24:06+00:00

0a9cc3d72fa2c6f19385efa8350f232e2e9faf10

Change of FIRRTL semantics!




Change of FIRRTL semantics!






Change of FIRRTL semantics!
2015-10-01T17:12:38+00:00

azidar

2015-10-01T16:56:11+00:00

ded5cd987b8d275bbff3904903a37837a504098b

Assignments to a register are no longer affected by enclosing when
statements:

when p :
  reg r : UInt,clk,reset
  r := a

will lower to:

reg r : UInt,clk,reset
r := a

instead of:

reg r : UInt,clk,reset
when p : r := a





Assignments to a register are no longer affected by enclosing when
statements:

when p :
  reg r : UInt,clk,reset
  r := a

will lower to:

reg r : UInt,clk,reset
r := a

instead of:

reg r : UInt,clk,reset
when p : r := a







Fixed naming bug where __1 was matching. Caused lots o issues.
2015-09-30T16:28:08+00:00

azidar

2015-09-30T16:28:08+00:00

4fefd791eed5ede508a7d47a3f21bf7790d05514