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<title>sfcX/test/passes/expand-accessors, branch master</title>
<subtitle>Scala FIRRTL Compiler for chiselX</subtitle>
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<entry>
<title>Remove stanza (#231)</title>
<updated>2016-08-15T17:32:41+00:00</updated>
<author>
<name>Adam Izraelevitz</name>
</author>
<published>2016-08-15T17:32:41+00:00</published>
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* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)
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* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)
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</entry>
<entry>
<title>Updated passes so they test new-mem</title>
<updated>2016-01-16T22:28:19+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2016-01-16T22:26:12+00:00</published>
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<entry>
<title>Fixed a test</title>
<updated>2016-01-16T22:28:19+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2016-01-16T22:13:28+00:00</published>
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<entry>
<title>New memory works with verilog. Slowly changing tests and fixing bugs.</title>
<updated>2016-01-16T22:28:17+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2015-12-10T02:31:45+00:00</published>
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Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
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Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
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</entry>
<entry>
<title>Fixed final bug. All tests pass. Accessors are a go.</title>
<updated>2015-09-30T03:38:47+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2015-09-30T03:38:47+00:00</published>
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<entry>
<title>Added DecToIndexer/DecFromIndexer. Fixed most use cases of incorrect catching of initialization of accessors. Missing use case of accessing an accessor. Still need to update tests to pass</title>
<updated>2015-09-29T22:49:52+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2015-09-29T22:49:52+00:00</published>
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<entry>
<title>Changed all tests to use verilog backend.</title>
<updated>2015-08-24T18:45:37+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2015-08-24T18:45:37+00:00</published>
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<entry>
<title>Updated tests to pipe from stderr to stdout</title>
<updated>2015-07-31T23:05:53+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2015-07-31T23:05:53+00:00</published>
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<entry>
<title>Updated lots of tests so they pass. Found one bug in expand whens</title>
<updated>2015-07-30T18:50:54+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2015-07-30T18:50:54+00:00</published>
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<entry>
<title>Added clock support</title>
<updated>2015-07-14T18:29:55+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2015-07-10T20:25:21+00:00</published>
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