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<title>sfcX/test/passes/const-prop, branch master</title>
<subtitle>Scala FIRRTL Compiler for chiselX</subtitle>
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<entry>
<title>Remove stanza (#231)</title>
<updated>2016-08-15T17:32:41+00:00</updated>
<author>
<name>Adam Izraelevitz</name>
</author>
<published>2016-08-15T17:32:41+00:00</published>
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<id>bebd04c4c68c320b2b72325e348c726dc33beae6</id>
<content type='text'>
* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)
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<pre>
* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)
</pre>
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</entry>
<entry>
<title>Changed stanza output of UInt/SInt to include widths. Made tests match accordingly</title>
<updated>2016-02-10T02:57:06+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2016-01-31T20:59:31+00:00</published>
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</entry>
<entry>
<title>New memory works with verilog. Slowly changing tests and fixing bugs.</title>
<updated>2016-01-16T22:28:17+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2015-12-10T02:31:45+00:00</published>
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Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
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<pre>
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
</pre>
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</content>
</entry>
<entry>
<title>Added rsh test for const-prop</title>
<updated>2015-08-20T21:21:51+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2015-08-20T21:21:51+00:00</published>
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<entry>
<title>Added new const propagation test</title>
<updated>2015-08-20T00:15:57+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2015-08-20T00:15:57+00:00</published>
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