sfcX/test/integration, branch 1.6.x Scala FIRRTL Compiler for chiselX Change to Apache 2.0 License (#1901) 2020-09-17T01:52:16+00:00 Chick Markley 2020-09-17T01:52:16+00:00 ecb96e83324ea17cf38b7b90753d745d3c7f51bd 






Update RightShiftTests.fir to avoid buggy Counter pattern
2020-07-27T15:50:09+00:00

Albert Magyar

2020-04-14T21:27:07+00:00

9ab58c1efb503aec00c22dbd70434038ec87dcab

* See freechipsproject/chisel3#1408





* See freechipsproject/chisel3#1408







Protobuf (#832)
2018-06-28T23:57:03+00:00

Jack Koenig

2018-06-28T23:57:03+00:00

3243f05a69b4b77761699be412f349a9b8b9193f

Add support for ProtoBuf serialization and deserialization

* Add support for additional features in .proto description

Features added: Info, Fixed[Type|Literal], AnalogType, Attach, Params

* Add support for .pb input files

This involves an API change where FIRRTL no longer implicitly adds .fir
to input file names




Add support for ProtoBuf serialization and deserialization

* Add support for additional features in .proto description

Features added: Info, Fixed[Type|Literal], AnalogType, Attach, Params

* Add support for .pb input files

This involves an API change where FIRRTL no longer implicitly adds .fir
to input file names






Emitting reg update mux tree, only walk netlist for wires and nodes
2017-06-28T01:50:15+00:00

Jack Koenig

2017-06-28T00:25:57+00:00

6f55a30b201716b6a0e72b65f6e5777b6b5d4b81

Fixes bug where the Verilog emitter could pull the next value for a
register that feeds a second register, removing the first register from
the second register's update.





Fixes bug where the Verilog emitter could pull the next value for a
register that feeds a second register, removing the first register from
the second register's update.







Clk2clock - rename the implicit "clk" module input "clock" (#387)
2016-12-08T17:25:42+00:00

Jim Lawson

2016-12-08T17:25:42+00:00

cfb3a48986500422cbf6ba8887030dee3a973933

* Rename implict module "clk" input to "clock".
This doesn't rename all the "self-contained" test instances.
nor the memory "clk" enables,
nor the implict module "clk"s in the regress .fir files.

* Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances.
This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.





* Rename implict module "clk" input to "clock".
This doesn't rename all the "self-contained" test instances.
nor the memory "clk" enables,
nor the implict module "clk"s in the regress .fir files.

* Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances.
This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.







Change RW port names (#236)
2016-08-17T20:34:14+00:00

Angie Wang

2016-08-17T20:34:14+00:00

5db4abebb7ceb5939a9efca158d78e3dc0e32c44

* Updated FIRRTL spec + related code for readwrite ports.
    (write) data -> wdata & mask -> wmask for clarity

* Also removed simple.fir that snuck into master branch.




* Updated FIRRTL spec + related code for readwrite ports.
    (write) data -> wdata & mask -> wmask for clarity

* Also removed simple.fir that snuck into master branch.






Add integration test for single-ported memory
2016-05-24T16:46:40+00:00

jackkoenig

2016-04-27T07:32:38+00:00

89cbd83265c5bfb3968865ebaddf79efb4f47050












Revamp string literal handling
2016-03-15T20:43:57+00:00

jackkoenig

2016-03-15T05:35:06+00:00

373d3cfcb5566c448dcad6b679dee43bf66f878a












Add support for right shift by amount larger than argument width
2016-03-10T21:37:53+00:00

jackkoenig

2016-03-10T09:23:14+00:00

5737a8ccbf54a6d22095023205867e851e204c3f












Add some integration tests: successful compilation and execution
2016-03-03T20:23:57+00:00

jackkoenig

2016-03-03T20:23:57+00:00

4d77e3ac1020b404e5a0f5d68cd36fb3a07ef333