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<title>sfcX/test/features, branch 1.6.x</title>
<subtitle>Scala FIRRTL Compiler for chiselX</subtitle>
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<entry>
<title>Remove stanza (#231)</title>
<updated>2016-08-15T17:32:41+00:00</updated>
<author>
<name>Adam Izraelevitz</name>
</author>
<published>2016-08-15T17:32:41+00:00</published>
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* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)
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* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)
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</entry>
<entry>
<title>Fixed bug in Remove Accesses where a WSubAccess's index was not checked for accesses.</title>
<updated>2016-04-09T00:46:07+00:00</updated>
<author>
<name>Adam Izraelevitz</name>
</author>
<published>2016-04-08T22:14:57+00:00</published>
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Fixes #105
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Fixes #105
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</entry>
<entry>
<title>Added remaining check passes. Ready for open sourcing</title>
<updated>2016-02-10T02:57:08+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2016-02-09T22:48:12+00:00</published>
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<entry>
<title>Changed stanza output of UInt/SInt to include widths. Made tests match accordingly</title>
<updated>2016-02-10T02:57:06+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2016-01-31T20:59:31+00:00</published>
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<entry>
<title>Changed rmode to wmode</title>
<updated>2016-01-28T17:25:05+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2016-01-27T23:59:48+00:00</published>
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<entry>
<title>Updated all tests to pass</title>
<updated>2016-01-28T17:25:04+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2016-01-26T22:18:34+00:00</published>
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<entry>
<title>Changed register syntax for optional reset and init values</title>
<updated>2016-01-28T17:25:03+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2016-01-26T22:16:09+00:00</published>
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<entry>
<title>Reworked readwriter types</title>
<updated>2016-01-27T19:30:57+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2016-01-26T18:52:17+00:00</published>
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<entry>
<title>Added verilog rename pass</title>
<updated>2016-01-25T23:59:59+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2016-01-25T23:59:59+00:00</published>
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<entry>
<title>Added isinvalid and validif</title>
<updated>2016-01-25T23:34:32+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2016-01-25T23:34:32+00:00</published>
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