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<title>sfcX/test/errors, branch master</title>
<subtitle>Scala FIRRTL Compiler for chiselX</subtitle>
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<entry>
<title>Remove stanza (#231)</title>
<updated>2016-08-15T17:32:41+00:00</updated>
<author>
<name>Adam Izraelevitz</name>
</author>
<published>2016-08-15T17:32:41+00:00</published>
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* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)
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* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)
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</entry>
<entry>
<title>Updated all tests to pass</title>
<updated>2016-01-28T17:25:04+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2016-01-26T22:18:34+00:00</published>
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<entry>
<title>Added muxing on passive aggregate types</title>
<updated>2016-01-25T00:30:50+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2016-01-25T00:30:50+00:00</published>
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<entry>
<title>Added prefix checker, now compliant with firrtl spec</title>
<updated>2016-01-23T15:00:39+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2016-01-23T15:00:39+00:00</published>
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<entry>
<title>Added check for uint on access index type</title>
<updated>2016-01-17T23:05:07+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2016-01-17T23:05:07+00:00</published>
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<entry>
<title>Fixed all tests so they either pass are marked as expected failures</title>
<updated>2016-01-16T23:24:04+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2016-01-16T23:24:04+00:00</published>
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<entry>
<title>Fixed a bunch of tests, and minor bugs</title>
<updated>2016-01-16T22:28:18+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2016-01-08T01:15:31+00:00</published>
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<entry>
<title>New memory works with verilog. Slowly changing tests and fixing bugs.</title>
<updated>2016-01-16T22:28:17+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2015-12-10T02:31:45+00:00</published>
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Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
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Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
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<entry>
<title>WIP. Compiles and almost done with verilog backend. Need to think about emitting ports (and the assignments to them)</title>
<updated>2016-01-16T22:28:17+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2015-12-03T23:12:02+00:00</published>
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<entry>
<title>Added Printf and Stop to firrtl. #23 #24.</title>
<updated>2015-10-07T21:49:54+00:00</updated>
<author>
<name>azidar</name>
</author>
<published>2015-10-07T21:48:04+00:00</published>
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