Directly subclassing Iterable is lazy-ish, but if you call any operation
on the resulting value (eg. map or ++) it will evaluate the Iterable and
return a List.

Transformation of mem readwriters whose address contain references to
readwriters of mems declared before it would contain invalid references
to untransformed memory readwriter, as the connection is not transformed.
This commit fixes this issue.

* [smem] fix read-under-write serialization

Also adds some tests for the parser and
the serializer.

* Serializer: always serialize smem ruw behavior

* test: simplify smem test circuit

* allow for zero-width integer literals
* CheckWidths: ensure that width is non-negative

Also get rid of whitespace-only lines that were emitted after every when
block.

Ever since introducing the Listener, the firrtl Parser now can hit
errors in the code converting from concrete syntax to abstract syntax
that may be due to syntax errors. These errors are essentially broken
assumptions about the structure of the parsed code because there is an
error. These errors are reported before the standard ANTLR syntax errors
are aggregated and reported, and thus could result in less than elegant
error messages (eg. NullPointerException). Now, the Parser will mask off
such errors in the event of standard syntax errors caught by the
ANTLR-generated parser.

This commit also cleans up some ParserSpec tests slightly to make the
ScalaTest style more canonical.

* Parse version and hardcode emitted version

* Throw error if version is too high

* Parse version even if rest is invalid

* Change pattern match to if statement

* Improve version grammar

* Update tests

* Remove outdated comment

* Simplify grammar and use version class

* Simplify and add no version test

* Fix for conflicting lexer rule

Fixes #2516

Previously,

reg r : UInt<8>, clock with :
  reset => (p, UInt<8>(3))
r is invalid

would compile to:

reg r : UInt<8>, clock
r <= UInt<8>(0)

now it compiles to:

reg r : UInt<8>, clock
wire r_1 : UInt<8>
r_1 is invalid
r <= mux(reset, UInt<8>(3), r_1)

This is consistent with the behavior for a reset with an asynchronous
reset.