We never tested the case where the width of the
numerator was less than the denominator.
This should fix any issue with this combination.

* rearrange passes to enable optimized firrtl emission

* Support ConstProp on padded arguments to comparisons with literals

* Move shr legalization logic into ConstProp

Continue calling ConstProp of shr in Legalize.

Co-authored-by: Jack Koenig <koenig@sifive.com>

Co-authored-by: Jack Koenig <koenig@sifive.com>

* smt: include firrtl statement names in SMT and btor2 output

* smt: remove println

* smt: make tests run again and fix stale ones

Apparently `private` classes aren't found by th sbt test runner.

This adds an experimental new SMTLib and Btor2 emitter
that converts a firrtl module into a format
suitable for open source model checkers.
The format generally follows the behavior of yosys'
write_smt2 and write_btor commands.

To generate btor2 for the module in m.fir run
> ./utils/bin/firrtl -i m.fir -E experimental-btor2
for SMT:
> ./utils/bin/firrtl -i m.fir -E experimental-smt2

If you have a design with multiple clocks
or an asynchronous reset, try out the new StutteringClockTransform.
You can designate any input of type Clock to be your
global simulation clock using the new GlobalClockAnnotation.

If your toplevel module instantiates submodules,
you need to inline them if you want the submodule
logic to be included in the formal model.