sfcX/src/test/scala/firrtl/backends/experimental/rtlil, branch master Scala FIRRTL Compiler for chiselX Remove some printlns in tests (#2445) 2021-12-17T17:39:34+00:00 Jack Koenig 2021-12-17T17:39:34+00:00 6b82bcf6690e38ff472a39eaae7e6375ff7085e4 Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> 
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
 Add RTLIL Backend. (#2331) 2021-09-29T03:18:48+00:00 Nicolas Machado 2021-09-29T03:18:48+00:00 e70ee5367c864e55ff16637430b712666b7dbd2b * Added RTLIL Backend. * Add test for Rtlil Backend, fix per-module file emission, scalafmt, and apply bugfixes for inconsistencies found during testing. * Fix build on scala 2.13 * Add additional equivalence test, make some bugfixes and perf opts to the emitter. * Final changes as requested by Kevin, code cleanup, add support for formal cells. 
* Added RTLIL Backend.

* Add test for Rtlil Backend, fix per-module file emission, scalafmt, and apply bugfixes for inconsistencies found during testing.

* Fix build on scala 2.13

* Add additional equivalence test, make some bugfixes and perf opts to the emitter.

* Final changes as requested by Kevin, code cleanup, add support for formal cells.