sfcX/src/test/resources, branch sfc-scala3 Scala FIRRTL Compiler for chiselX Add RTLIL Backend. (#2331) 2021-09-29T03:18:48+00:00 Nicolas Machado 2021-09-29T03:18:48+00:00 e70ee5367c864e55ff16637430b712666b7dbd2b * Added RTLIL Backend. * Add test for Rtlil Backend, fix per-module file emission, scalafmt, and apply bugfixes for inconsistencies found during testing. * Fix build on scala 2.13 * Add additional equivalence test, make some bugfixes and perf opts to the emitter. * Final changes as requested by Kevin, code cleanup, add support for formal cells. 
* Added RTLIL Backend.

* Add test for Rtlil Backend, fix per-module file emission, scalafmt, and apply bugfixes for inconsistencies found during testing.

* Fix build on scala 2.13

* Add additional equivalence test, make some bugfixes and perf opts to the emitter.

* Final changes as requested by Kevin, code cleanup, add support for formal cells.
 Legalize neg: -x becomes 0 - x (#2128) 2021-03-19T20:59:52+00:00 Jack Koenig 2021-03-19T20:59:52+00:00 49b823244732e8d3a4b0fe91d0f10625fea34eec This fixes an error with negating a negative SInt literal and a [debatable] lint warning in Verilator when negating any value. This behavior matches that of Chisel (which directly emits the 0 - x already). 
This fixes an error with negating a negative SInt literal and a
[debatable] lint warning in Verilator when negating any value.

This behavior matches that of Chisel (which directly emits the 0 - x
already).
 Change to Apache 2.0 License (#1901) 2020-09-17T01:52:16+00:00 Chick Markley 2020-09-17T01:52:16+00:00 ecb96e83324ea17cf38b7b90753d745d3c7f51bd 






Remove LegacyAnnotation and [most] MoultingYaml (#1833)
2020-08-13T04:17:14+00:00

Jack Koenig

2020-08-13T04:17:14+00:00

39f510a9081d09d94d56eb89ceb97a678993fda1

* Remove LegacyAnnotation and MoultingYaml

It has been deprecated since 1.1

* Remove all uses of ConvertLegacyAnnotations

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>




* Remove LegacyAnnotation and MoultingYaml

It has been deprecated since 1.1

* Remove all uses of ConvertLegacyAnnotations

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>






Error on ExtModules w/ same defname, diff. ports (#1734)
2020-08-01T17:01:44+00:00

Schuyler Eldridge

2020-08-01T17:01:44+00:00

687f3ddbbcd9217542a4bc0e2c256559d2c67a5b

* Use signed output in LargeParamExecutionTest

Change the Verilog used in LargeParamExecutionTest to match its
ExtModule specification. An ExtModule with an SInt port should map to
a separate Verilog module with a signed port and this is disjoint from
an ExtModule with a UInt port.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Error on ExtModules w/ same defname, diff. ports

Adds a high form check to ensure that external modules that have the
same defname also have exactly the same ports.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>




* Use signed output in LargeParamExecutionTest

Change the Verilog used in LargeParamExecutionTest to match its
ExtModule specification. An ExtModule with an SInt port should map to
a separate Verilog module with a signed port and this is disjoint from
an ExtModule with a UInt port.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Error on ExtModules w/ same defname, diff. ports

Adds a high form check to ensure that external modules that have the
same defname also have exactly the same ports.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>






Fix out-of-scope reference in handwritten CHIRRTL mem test
2020-07-27T15:50:09+00:00

Albert Magyar

2020-04-14T22:29:43+00:00

1220a23ac9dfc26dbf5475ef064b644cdd1d7983












Add Support for FPGA Bitstream Preset-registers (#1050)
2020-03-13T01:35:10+00:00

John's Brew

2020-03-13T01:35:10+00:00

5c0c0018d812d57270035a9d3bd82e2289acf4ec

Introduce Preset Register Specialized Emission
- Introduce EmissionOption trait
- Introduce PresetAnnotation & PresetRegAnnotation
- Enable the collection of Annotations in the Emitter
- Introduce collection mechanism for EmissionOptions in the Emitter
- Add PropagatePresetAnnotation transform to annotate register for emission and clean-up the useless reset tree (no DCE involved)
- Add corresponding tests spec and tester

Co-authored-by: Jack Koenig <koenig@sifive.com>




Introduce Preset Register Specialized Emission
- Introduce EmissionOption trait
- Introduce PresetAnnotation & PresetRegAnnotation
- Enable the collection of Annotations in the Emitter
- Introduce collection mechanism for EmissionOptions in the Emitter
- Add PropagatePresetAnnotation transform to annotate register for emission and clean-up the useless reset tree (no DCE involved)
- Add corresponding tests spec and tester

Co-authored-by: Jack Koenig <koenig@sifive.com>






Emit legal Verilog literals for ExtModule IntParams > 32-bit (#1087)
2019-05-24T21:37:52+00:00

Jack Koenig

2019-05-24T21:37:52+00:00

228c9a4b7432ac52178d63b8f27fe064aec71e9c

Emit Verilog IntParams that fit in 32-bits as Integer literals





Emit Verilog IntParams that fit in 32-bits as Integer literals







Asynchronous Reset (#1011)
2019-02-14T23:08:35+00:00

Jack Koenig

2019-02-14T23:08:35+00:00

2272044c6ab46b5148c39c124e66e1a8e9073a24

Fixes #219

* Adds AsyncResetType (similar to ClockType)
* Registers with reset signal of type AsyncResetType are async reset
  registers
* Registers with async reset can only be reset to literal values
* Add initialization logic for async reset registers




Fixes #219

* Adds AsyncResetType (similar to ClockType)
* Registers with reset signal of type AsyncResetType are async reset
  registers
* Registers with async reset can only be reset to literal values
* Add initialization logic for async reset registers






Add firrtl.options tests
2018-11-07T18:26:09+00:00

Schuyler Eldridge

2018-09-28T16:39:01+00:00

27c1b366ce58e93434e77e964365474f5e7aa8d7

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>





Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>