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<title>sfcX/src/test/resources/regress, branch 1.6.x</title>
<subtitle>Scala FIRRTL Compiler for chiselX</subtitle>
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<entry>
<title>Add rocket regression, just runs rocket.fir through Verilog compiler and compares to expected Verilog. Uses ScalaTest. Should be eventually replaced with actual simulation of rocket-chip</title>
<updated>2016-02-23T08:57:09+00:00</updated>
<author>
<name>Jack</name>
</author>
<published>2016-02-23T08:57:09+00:00</published>
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