sfcX/src/test/resources/passes, branch sfc-scala3 Scala FIRRTL Compiler for chiselX Legalize neg: -x becomes 0 - x (#2128) 2021-03-19T20:59:52+00:00 Jack Koenig 2021-03-19T20:59:52+00:00 49b823244732e8d3a4b0fe91d0f10625fea34eec This fixes an error with negating a negative SInt literal and a [debatable] lint warning in Verilator when negating any value. This behavior matches that of Chisel (which directly emits the 0 - x already). 
This fixes an error with negating a negative SInt literal and a
[debatable] lint warning in Verilator when negating any value.

This behavior matches that of Chisel (which directly emits the 0 - x
already).
 Change to Apache 2.0 License (#1901) 2020-09-17T01:52:16+00:00 Chick Markley 2020-09-17T01:52:16+00:00 ecb96e83324ea17cf38b7b90753d745d3c7f51bd 






Clk2clock - rename the implicit "clk" module input "clock" (#387)
2016-12-08T17:25:42+00:00

Jim Lawson

2016-12-08T17:25:42+00:00

cfb3a48986500422cbf6ba8887030dee3a973933

* Rename implict module "clk" input to "clock".
This doesn't rename all the "self-contained" test instances.
nor the memory "clk" enables,
nor the implict module "clk"s in the regress .fir files.

* Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances.
This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.





* Rename implict module "clk" input to "clock".
This doesn't rename all the "self-contained" test instances.
nor the memory "clk" enables,
nor the implict module "clk"s in the regress .fir files.

* Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances.
This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.







Cleanup license at top of every file (#364)
2016-11-04T22:47:10+00:00

Jack Koenig

2016-11-04T22:47:10+00:00

82da5e7903817b877bff3c07e09b0b7e9d009351

Replace with more sensible comment to see LICENSE rather than including the
whole license in every file




Replace with more sensible comment to see LICENSE rather than including the
whole license in every file






Add LegalizeSpec for testing Verilog Legalization pass
2016-09-13T04:30:40+00:00

Jack

2016-05-18T18:59:11+00:00

9a68008856f390bdc3be858f9cce5ed484cdb68f












Add Expand Whens test
2016-05-03T23:56:52+00:00

jackkoenig

2016-04-28T23:43:25+00:00

72763a13141345aca79554d743cf3951e726d95f