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<title>sfcX/src/test/resources/features, branch master</title>
<subtitle>Scala FIRRTL Compiler for chiselX</subtitle>
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<entry>
<title>Change to Apache 2.0 License (#1901)</title>
<updated>2020-09-17T01:52:16+00:00</updated>
<author>
<name>Chick Markley</name>
</author>
<published>2020-09-17T01:52:16+00:00</published>
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<pre>
</pre>
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<entry>
<title>Fix out-of-scope reference in handwritten CHIRRTL mem test</title>
<updated>2020-07-27T15:50:09+00:00</updated>
<author>
<name>Albert Magyar</name>
</author>
<published>2020-04-14T22:29:43+00:00</published>
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<pre>
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<entry>
<title>Add Support for FPGA Bitstream Preset-registers (#1050)</title>
<updated>2020-03-13T01:35:10+00:00</updated>
<author>
<name>John's Brew</name>
</author>
<published>2020-03-13T01:35:10+00:00</published>
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Introduce Preset Register Specialized Emission
- Introduce EmissionOption trait
- Introduce PresetAnnotation &amp; PresetRegAnnotation
- Enable the collection of Annotations in the Emitter
- Introduce collection mechanism for EmissionOptions in the Emitter
- Add PropagatePresetAnnotation transform to annotate register for emission and clean-up the useless reset tree (no DCE involved)
- Add corresponding tests spec and tester

Co-authored-by: Jack Koenig &lt;koenig@sifive.com&gt;</content>
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Introduce Preset Register Specialized Emission
- Introduce EmissionOption trait
- Introduce PresetAnnotation &amp; PresetRegAnnotation
- Enable the collection of Annotations in the Emitter
- Introduce collection mechanism for EmissionOptions in the Emitter
- Add PropagatePresetAnnotation transform to annotate register for emission and clean-up the useless reset tree (no DCE involved)
- Add corresponding tests spec and tester

Co-authored-by: Jack Koenig &lt;koenig@sifive.com&gt;</pre>
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</content>
</entry>
<entry>
<title>Asynchronous Reset (#1011)</title>
<updated>2019-02-14T23:08:35+00:00</updated>
<author>
<name>Jack Koenig</name>
</author>
<published>2019-02-14T23:08:35+00:00</published>
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<content type='text'>
Fixes #219

* Adds AsyncResetType (similar to ClockType)
* Registers with reset signal of type AsyncResetType are async reset
  registers
* Registers with async reset can only be reset to literal values
* Add initialization logic for async reset registers</content>
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<pre>
Fixes #219

* Adds AsyncResetType (similar to ClockType)
* Registers with reset signal of type AsyncResetType are async reset
  registers
* Registers with async reset can only be reset to literal values
* Add initialization logic for async reset registers</pre>
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</entry>
<entry>
<title>Fix more problems with zero width things. (#779)</title>
<updated>2018-05-21T20:09:00+00:00</updated>
<author>
<name>grebe</name>
</author>
<published>2018-05-21T20:09:00+00:00</published>
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This should close #757. It should also allow for stop() and printf()
to be used with zero-width fields.
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This should close #757. It should also allow for stop() and printf()
to be used with zero-width fields.
</pre>
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</entry>
<entry>
<title>Masks for zero-width fields of mems should be width zero. (#763)</title>
<updated>2018-03-19T22:37:25+00:00</updated>
<author>
<name>grebe</name>
</author>
<published>2018-03-19T22:37:25+00:00</published>
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Closes #666.</content>
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<pre>
Closes #666.</pre>
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</entry>
<entry>
<title>Add --no-dce command-line option to skip DCE</title>
<updated>2017-06-21T17:18:20+00:00</updated>
<author>
<name>Jack Koenig</name>
</author>
<published>2017-06-21T16:35:15+00:00</published>
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<pre>
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<entry>
<title>Add option to disable combinational loop detection</title>
<updated>2017-06-13T01:52:46+00:00</updated>
<author>
<name>Jack Koenig</name>
</author>
<published>2017-06-12T20:58:26+00:00</published>
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<content type='text'>
Resolves #600
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<pre>
Resolves #600
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</entry>
<entry>
<title>Clk2clock - rename the implicit "clk" module input "clock" (#387)</title>
<updated>2016-12-08T17:25:42+00:00</updated>
<author>
<name>Jim Lawson</name>
</author>
<published>2016-12-08T17:25:42+00:00</published>
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<content type='text'>
* Rename implict module "clk" input to "clock".
This doesn't rename all the "self-contained" test instances.
nor the memory "clk" enables,
nor the implict module "clk"s in the regress .fir files.

* Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances.
This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.
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* Rename implict module "clk" input to "clock".
This doesn't rename all the "self-contained" test instances.
nor the memory "clk" enables,
nor the implict module "clk"s in the regress .fir files.

* Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances.
This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.
</pre>
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</entry>
<entry>
<title>Fix CHIRRTL bugs (#355)</title>
<updated>2016-11-06T04:23:14+00:00</updated>
<author>
<name>Donggyu</name>
</author>
<published>2016-11-06T04:23:14+00:00</published>
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<content type='text'>
* handle uninferred ports gracefully in RemoveCHIRRTL

memory port directions are not inferred during CInferMDir if not being used, so handle them properly in RemoveCHIRRTL

* fix CInferTypes
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* handle uninferred ports gracefully in RemoveCHIRRTL

memory port directions are not inferred during CInferMDir if not being used, so handle them properly in RemoveCHIRRTL

* fix CInferTypes
</pre>
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