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<title>sfcX/src/main/scala/midas, branch master</title>
<subtitle>Scala FIRRTL Compiler for chiselX</subtitle>
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<title>Refactored MIDAS code into its own repo</title>
<updated>2015-12-08T20:39:49+00:00</updated>
<author>
<name>jackkoenig</name>
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<published>2015-12-08T20:39:49+00:00</published>
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<entry>
<title>Fixed bug, I think transformation works now for the most part</title>
<updated>2015-12-08T04:02:05+00:00</updated>
<author>
<name>jackkoenig</name>
</author>
<published>2015-12-08T04:02:05+00:00</published>
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<title>The transformation works! Kind of, it works fine when everything is alwasy ready, has some weird issues when they're not, but also kind of works in that the hardware verifier still reports the right answer, it seems to go to half duty cycle and then do every token twice</title>
<updated>2015-12-07T09:11:10+00:00</updated>
<author>
<name>jackkoenig</name>
</author>
<published>2015-12-07T09:11:10+00:00</published>
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<entry>
<title>Working on generating SimTop, need to figure out how to split the top-level IO between the sim modules.</title>
<updated>2015-12-06T08:36:12+00:00</updated>
<author>
<name>jackkoenig</name>
</author>
<published>2015-12-06T08:36:12+00:00</published>
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<entry>
<title>Everything is broken, need Translator to work on files without a circuit, need to parse queue module text in midas/Utils.scala, need to create (src, dst) -&gt; Module mapping in midas/Fame.scala</title>
<updated>2015-12-05T02:15:03+00:00</updated>
<author>
<name>jackkoenig</name>
</author>
<published>2015-12-05T02:15:03+00:00</published>
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<entry>
<title>Some stylistic changes and a couple bugfixes to simulation wrapper generation</title>
<updated>2015-12-04T07:32:36+00:00</updated>
<author>
<name>jackkoenig</name>
</author>
<published>2015-12-04T07:32:36+00:00</published>
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<entry>
<title>New wrapper generator complete</title>
<updated>2015-12-04T05:14:34+00:00</updated>
<author>
<name>jackkoenig</name>
</author>
<published>2015-12-04T05:14:34+00:00</published>
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<entry>
<title>Changing simwrapper to group ports that go to different places, not quite there yet. Will allow simple bulk connecting at top-level</title>
<updated>2015-12-04T02:03:31+00:00</updated>
<author>
<name>jackkoenig</name>
</author>
<published>2015-12-04T02:03:31+00:00</published>
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<entry>
<title>Seem to be able to generate simulation wrapper module from DefInst</title>
<updated>2015-12-03T09:27:42+00:00</updated>
<author>
<name>jackkoenig</name>
</author>
<published>2015-12-03T09:27:42+00:00</published>
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<entry>
<title>Added fame transformation and new package, making progress</title>
<updated>2015-12-03T02:03:35+00:00</updated>
<author>
<name>jackkoenig</name>
</author>
<published>2015-12-03T02:03:35+00:00</published>
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