sfcX/src/main/scala/firrtl/transforms/formal/ConvertAsserts.scala, branch 1.6.x Scala FIRRTL Compiler for chiselX transforms.formal: ensure named statements as output (#2367) 2021-09-23T23:34:28+00:00 Kevin Laeufer 2021-09-23T23:34:28+00:00 034445e31ec53100abe259d407e62e278fdb50fa 






Change to Apache 2.0 License (#1901)
2020-09-17T01:52:16+00:00

Chick Markley

2020-09-17T01:52:16+00:00

ecb96e83324ea17cf38b7b90753d745d3c7f51bd












All of src/ formatted with scalafmt
2020-08-15T02:47:53+00:00

chick

2020-08-15T02:47:53+00:00

6fc742bfaf5ee508a34189400a1a7dbffe3f1cac












Add ConvertAsserts transform to map asserts to Verilog-friendly nodes
2020-06-26T18:08:42+00:00

Albert Magyar

2020-06-25T20:05:52+00:00

fe7754a4ef92b2333f43458e53478e29cedad1c7

* ConvertAsserts maps each assert into a gated print-and-stop
* ConvertAsserts is an optional prereq of RemoveVerificationStatements
* ConvertAsserts generates Low FIRRTL
* Drop print for asserts that have an empty message
* Fix scaladoc formatting from review

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>





* ConvertAsserts maps each assert into a gated print-and-stop
* ConvertAsserts is an optional prereq of RemoveVerificationStatements
* ConvertAsserts generates Low FIRRTL
* Drop print for asserts that have an empty message
* Fix scaladoc formatting from review

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>