sfcX/src/main/scala/firrtl/passes, branch master Scala FIRRTL Compiler for chiselX Fix invalid references generated by VerilogMemDelays (#2588) 2023-02-03T07:38:07+00:00 Alan L 2023-02-03T07:38:07+00:00 94d425f0f48e84bbae1be9d44d64615a37d960d8 Transformation of mem readwriters whose address contain references to readwriters of mems declared before it would contain invalid references to untransformed memory readwriter, as the connection is not transformed. This commit fixes this issue. 
Transformation of mem readwriters whose address contain references to
readwriters of mems declared before it would contain invalid references
to untransformed memory readwriter, as the connection is not transformed.
This commit fixes this issue.
 0-bit literals (#2544) 2022-12-15T22:09:14+00:00 Kevin Laeufer 2022-12-15T22:09:14+00:00 135739f0c7ef3f6404ba7115f77c7d7b913f6748 * allow for zero-width integer literals * CheckWidths: ensure that width is non-negative 
* allow for zero-width integer literals
* CheckWidths: ensure that width is non-negative
 Make MemConf's MemPort serialization deterministic (#2508) 2022-04-08T00:07:48+00:00 Chick Markley 2022-04-08T00:07:48+00:00 f7b4aa8a3a759c94e0de8e1aeeacc69d3d702945 Problem: MemConf serialization of MemPorts was not deterministic and the ordering seems to have changed as we move projects to 2.13 Downstream project can be adversely affected by changes in ordering This changes specifies as specific ordering that should be compatible with the historical one. 
Problem: MemConf serialization of MemPorts was not deterministic
and the ordering seems to have changed as we move projects to 2.13
Downstream project can be adversely affected by changes in ordering
This changes specifies as specific ordering that should be compatible with
the historical one.
 Fold VerilogModulusCleanup into LegalizeVerilog (#2485) 2022-03-02T17:31:57+00:00 Jack Koenig 2022-03-02T17:31:57+00:00 95cae3cd0eb9ac72eb6373207dbf9f09fb1c7086 This fixes handling of signed modulus and removes some redundant work. 
This fixes handling of signed modulus and removes some redundant work.
 Remove some warnings (#2448) 2021-12-22T02:47:18+00:00 Jack Koenig 2021-12-22T02:47:18+00:00 4f3d1003811aa38d10e32b347c8607414d9be034 * Fix unreachable code warning by changing match order Simulation Statements did not previously extend IsDeclaration, but now they do so their match blocks need to be above IsDeclaration. * Handle MemoryNoInit case in RtlilEmitter * Remove use of deprecated logToFile * Fix uses of LegalizeClocksTransform Replaced all uses of LegalizeClocksTransform with LegalizeClocksAndAsyncResetsTransform. * Remove use of CircuitForm in ZeroWidth 
* Fix unreachable code warning by changing match order

Simulation Statements did not previously extend IsDeclaration, but now
they do so their match blocks need to be above IsDeclaration.

* Handle MemoryNoInit case in RtlilEmitter

* Remove use of deprecated logToFile

* Fix uses of LegalizeClocksTransform

Replaced all uses of LegalizeClocksTransform with
LegalizeClocksAndAsyncResetsTransform.

* Remove use of CircuitForm in ZeroWidth
 Fix width of signed addition when input to mux (#2440) 2021-12-18T06:40:46+00:00 Jack Koenig 2021-12-18T06:40:46+00:00 c00a4ebb0608f9ef98729e9b610a2678be2bc4fd Fix bugs related to arithmetic ops inlined into a mux leg. Add formal equivalence checks to lock in this behavior. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> 
Fix bugs related to arithmetic ops inlined into a mux leg.  Add formal
equivalence checks to lock in this behavior.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
 Deprecate all mutable methods on RenameMap (#2444) 2021-12-17T18:07:25+00:00 Jack Koenig 2021-12-17T18:07:25+00:00 37c8528cfed4395924820b54498ef761ded17393 * Add renamemap.MutableRenameMap which includes these methods without deprecation * Deprecate Stringly typed RenameMap APIs which were accidentally undeprecated a while ago Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> 
* Add renamemap.MutableRenameMap which includes these methods without
  deprecation
* Deprecate Stringly typed RenameMap APIs which were accidentally
  undeprecated a while ago

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
 Hotfix for Vector Reg Init LegalizeConnects Bug 2021-10-05T02:24:51+00:00 Schuyler Eldridge 2021-10-05T02:24:51+00:00 527eba4966513bcfd1453fd76cfb241272fe602c Add a private pass, LegalizeConnectsOnly, that behaves like LegalizeConnects, but only pads connects instead of connects and register inits. Padding is necessary for ReplSeqMem, but ReplSeqMem runs before LowerTypes and vector registers can still exist at this point. Connects, conversely, are all blown out by ExpandConnects and can be safely, blindly treated as ground type. Fixes #2379. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> 
Add a private pass, LegalizeConnectsOnly, that behaves like
LegalizeConnects, but only pads connects instead of connects and
register inits.  Padding is necessary for ReplSeqMem, but ReplSeqMem
runs before LowerTypes and vector registers can still exist at this
point.  Connects, conversely, are all blown out by ExpandConnects and
can be safely, blindly treated as ground type.

Fixes #2379.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Have Flatten & InlineInstances remove their annotations (#2374) 2021-09-29T20:55:32+00:00 David Biancolin 2021-09-29T20:55:32+00:00 b81de69928b765949be0c79dea1d0cc714a31aa1 * Have Flatten & InlineInstances remove their annotations * Format 
* Have Flatten & InlineInstances remove their annotations

* Format
 Remove BlackBoxSourceHelper from ReplaceMemTransform (#2355) 2021-09-11T07:29:10+00:00 Jack Koenig 2021-09-11T07:29:10+00:00 beb5bc9850fd69adff36f38fb00a1f68bb1918fe BlackBoxSourceHelper should only run late in compilation to allow transforms to tweak its behavior (eg. changing BlackBoxTargetDirAnno). 
BlackBoxSourceHelper should only run late in compilation to allow
transforms to tweak its behavior (eg. changing BlackBoxTargetDirAnno).