Transformation of mem readwriters whose address contain references to readwriters of mems declared before it would contain invalid references to untransformed memory readwriter, as the connection is not transformed. This commit fixes this issue.
Problem: MemConf serialization of MemPorts was not deterministic and the ordering seems to have changed as we move projects to 2.13 Downstream project can be adversely affected by changes in ordering This changes specifies as specific ordering that should be compatible with the historical one.
* Add renamemap.MutableRenameMap which includes these methods without deprecation * Deprecate Stringly typed RenameMap APIs which were accidentally undeprecated a while ago Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Add a private pass, LegalizeConnectsOnly, that behaves like LegalizeConnects, but only pads connects instead of connects and register inits. Padding is necessary for ReplSeqMem, but ReplSeqMem runs before LowerTypes and vector registers can still exist at this point. Connects, conversely, are all blown out by ExpandConnects and can be safely, blindly treated as ground type. Fixes #2379. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
BlackBoxSourceHelper should only run late in compilation to allow transforms to tweak its behavior (eg. changing BlackBoxTargetDirAnno).
* rearrange passes to enable optimized firrtl emission * Support ConstProp on padded arguments to comparisons with literals * Move shr legalization logic into ConstProp Continue calling ConstProp of shr in Legalize. Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
The pass injects pipe registers immediately after the declaration of the memory. This can be problematic if the clock for the associated memory port is defined after the declaration of the memory. For any memory port clocks that are driven by non-ports, we now inject a wire before the pipe register declarations to be sure there are no use-before-declaration issues.
* ReplaceMemMacros: add target rename test case * ReplaceMemMacros: rename references to instances * fix renaming for deduped mems * use grouped DummyAnnos to preserve order * Apply suggestions from code review Co-authored-by: Jack Koenig <koenig@sifive.com> * run scalafmt * flatten targets Co-authored-by: Jack Koenig <koenig@sifive.com>
* Add GenVerilogMemBehaviorModelAnno & vlsiMemGen * Add CLI support for GenVerilogMemBehaviorModelAnno * Add simple test for GenVerilogMemBehaviorModelAnno * Fix for review 1. rename case class Port(prefix, `type`) to Port(prefix, portType) 2. fix AnnotatedMemoriesAnnotation collect function. 3. fix bug that ModuleName is not correct. * Format DumpMemoryAnnotations & ReplSeqMemTests * Fix for review 1. Inline genDecl, genPortSpec, genSequential, genCombinational 2. Add DefAnnotatedMemory informations in header 3. Change helpText 4. Check output Verilog by Verilator, the code is from FirrtlRunners#lintVerilog * Fix ReadWritePort mask name Co-authored-by: Jiuyang Liu <liu@jiuyang.me> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>