This fixes handling of signed modulus and removes some redundant work.
- Fix & test MemorySynthInit behavior with MemoryArrayInitAnnotation and MemoryScalarInitAnnotation. Add test case for MemoryRandomInitAnnotation which is, on the contrary, expected not to leak any randomization statement in synthesis context. - Refactor MemoryInitSpec for improved results readability Context: PR #2166 (commit: 4530152) introduced MemorySynthInit annotation to control whether statement generated with Memory*InitAnnotation (emitted within initial begin block in verilog) should be guarded with ifndef SYNTHESIS or not. Unfortunately only one configuration (MemoryFileInlineAnnotation) has been tested while the others have been generating incorrect verilog statements (MemoryArrayInitAnnotation and MemoryScalarInitAnnotation). Signed-off-by: Jean Bruant <jean.bruant@ovhcloud.com>
* Add FileInfo to asyncResetAlwaysBlocks
Always blocks need three FileInfo (if, true, false) to show line numbers,
but initially, every always blocks only have one FileInfo (false).
RemoveReset adds the extra two FileInfo to sync always blocks,
so sync always blocks can have line numbers.
Async always blocks don't provide their only FileInfo, so there are no line numbers.
This commit gives async always block the extra FileInfo to show line numbers for them.
This code:
```scala
import chisel3._
import chisel3.stage._
import firrtl.CustomDefaultRegisterEmission
class Test extends Module with RequireAsyncReset {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val valid = RegInit(false.B)
valid := io.in
io.out := valid
}
object Test extends App {
new ChiselStage().execute(Array(), Seq(
ChiselGeneratorAnnotation(() => new Test()),
CustomDefaultRegisterEmission(useInitAsPreset = false, disableRandomization = true)
))
}
```
will generate this Verilog:
```verilog
module Test(
input clock,
input reset,
input io_in,
output io_out
);
reg valid; // @[Playground.scala 10:22]
assign io_out = valid; // @[Playground.scala 12:10]
always @(posedge clock or posedge reset) begin
if (reset) begin // @[Playground.scala 10:22]
valid <= 1'h0; // @[Playground.scala 10:22]
end else begin
valid <= io_in; // @[Playground.scala 11:9]
end
end
endmodule
```
they have correct line numbers (10, 10, 11).
* Add test for async always block line numbers
* Add comment for review
* Add option to disable random mem/reg init Co-authored-by: Jiuyang Liu <liu@jiuyang.me> * fix for code review. Co-authored-by: SharzyL <me@sharzy.in>
+ correct the Error Info of "At least one dedupable annotation..."
* rearrange passes to enable optimized firrtl emission * Support ConstProp on padded arguments to comparisons with literals * Move shr legalization logic into ConstProp Continue calling ConstProp of shr in Legalize. Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
* Add new util "groupByIntoSeq" * Restore annotation order when dedupping annotations * Attribute annotations now deduplicate * Implement doc string anno dedup Co-authored-by: Jack Koenig <koenig@sifive.com>
* Add transform to deduplicate memory annotations * Add annotation deduplication to Dedup stage * ResolveAnnotationPaths and EliminateTargetPaths now invalidate the dedup annotations transform * Verilog emitter now throws exception when memory annotations fail to dedup Co-authored-by: Jack Koenig <koenig@sifive.com>
* Fixes #2173
* Emit readwrite ports, if applicable * Does not change VerilogMemDelays -> no effect on default flow * Use more single-line declare-and-assign statements for mem wires * Update error messages for too-complex memories in VerilogEmitter * Run scalafmt on VerilogEmitter