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<title>sfcX/src/main/scala/firrtl/backends/experimental, branch master</title>
<subtitle>Scala FIRRTL Compiler for chiselX</subtitle>
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<entry>
<title>smt: make SMTExprMap object public (#2534)</title>
<updated>2022-08-03T16:05:36+00:00</updated>
<author>
<name>Kevin Laeufer</name>
</author>
<published>2022-08-03T16:05:36+00:00</published>
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<id>ad0dd6a2808789d0eda3665d5f565f0988db2c77</id>
<content type='text'>
The simple functionality is needed in chiseltest.</content>
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<pre>
The simple functionality is needed in chiseltest.</pre>
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</content>
</entry>
<entry>
<title>[smt] correct comparison for out-of-bounds memory access check (#2463)</title>
<updated>2022-01-17T23:29:14+00:00</updated>
<author>
<name>Kevin Laeufer</name>
</author>
<published>2022-01-17T23:29:14+00:00</published>
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<id>5569c72c1b6246efd203e00f7af6041567575eec</id>
<content type='text'>
This fixes an off by one error, where 3 was erroneously
accepted as in-bounds for a memory of depth=3</content>
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<pre>
This fixes an off by one error, where 3 was erroneously
accepted as in-bounds for a memory of depth=3</pre>
</div>
</content>
</entry>
<entry>
<title>Remove some warnings (#2448)</title>
<updated>2021-12-22T02:47:18+00:00</updated>
<author>
<name>Jack Koenig</name>
</author>
<published>2021-12-22T02:47:18+00:00</published>
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<id>4f3d1003811aa38d10e32b347c8607414d9be034</id>
<content type='text'>
* Fix unreachable code warning by changing match order

Simulation Statements did not previously extend IsDeclaration, but now
they do so their match blocks need to be above IsDeclaration.

* Handle MemoryNoInit case in RtlilEmitter

* Remove use of deprecated logToFile

* Fix uses of LegalizeClocksTransform

Replaced all uses of LegalizeClocksTransform with
LegalizeClocksAndAsyncResetsTransform.

* Remove use of CircuitForm in ZeroWidth</content>
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<pre>
* Fix unreachable code warning by changing match order

Simulation Statements did not previously extend IsDeclaration, but now
they do so their match blocks need to be above IsDeclaration.

* Handle MemoryNoInit case in RtlilEmitter

* Remove use of deprecated logToFile

* Fix uses of LegalizeClocksTransform

Replaced all uses of LegalizeClocksTransform with
LegalizeClocksAndAsyncResetsTransform.

* Remove use of CircuitForm in ZeroWidth</pre>
</div>
</content>
</entry>
<entry>
<title>smt: deal correctly with negative SInt literals (#2447)</title>
<updated>2021-12-21T17:07:30+00:00</updated>
<author>
<name>Kevin Laeufer</name>
</author>
<published>2021-12-21T17:07:30+00:00</published>
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<id>2d197c841c5400c6deaa1592525be6a1d81dc1e2</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>smt: correctly serialize array index on read (#2446)</title>
<updated>2021-12-17T20:04:52+00:00</updated>
<author>
<name>Kevin Laeufer</name>
</author>
<published>2021-12-17T20:04:52+00:00</published>
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<id>57ce615d73995a29f89c2f9b11482fe80442439b</id>
<content type='text'>
This should fix issue #2436</content>
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<pre>
This should fix issue #2436</pre>
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</content>
</entry>
<entry>
<title>Deprecate all mutable methods on RenameMap (#2444)</title>
<updated>2021-12-17T18:07:25+00:00</updated>
<author>
<name>Jack Koenig</name>
</author>
<published>2021-12-17T18:07:25+00:00</published>
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<id>37c8528cfed4395924820b54498ef761ded17393</id>
<content type='text'>
* Add renamemap.MutableRenameMap which includes these methods without
  deprecation
* Deprecate Stringly typed RenameMap APIs which were accidentally
  undeprecated a while ago

Co-authored-by: mergify[bot] &lt;37929162+mergify[bot]@users.noreply.github.com&gt;</content>
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<pre>
* Add renamemap.MutableRenameMap which includes these methods without
  deprecation
* Deprecate Stringly typed RenameMap APIs which were accidentally
  undeprecated a while ago

Co-authored-by: mergify[bot] &lt;37929162+mergify[bot]@users.noreply.github.com&gt;</pre>
</div>
</content>
</entry>
<entry>
<title>Disable random init (#2396)</title>
<updated>2021-11-19T19:17:37+00:00</updated>
<author>
<name>Jiuyang Liu</name>
</author>
<published>2021-11-19T19:17:37+00:00</published>
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<id>b027eb466b033a0a9d229f19feb931ddb292a9fa</id>
<content type='text'>
* Add option to disable random mem/reg init

Co-authored-by: Jiuyang Liu &lt;liu@jiuyang.me&gt;

* fix for code review.

Co-authored-by: SharzyL &lt;me@sharzy.in&gt;</content>
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<pre>
* Add option to disable random mem/reg init

Co-authored-by: Jiuyang Liu &lt;liu@jiuyang.me&gt;

* fix for code review.

Co-authored-by: SharzyL &lt;me@sharzy.in&gt;</pre>
</div>
</content>
</entry>
<entry>
<title>smt: fix handling of div primitive in formal backend (#2409)</title>
<updated>2021-11-10T14:33:39+00:00</updated>
<author>
<name>Kevin Laeufer</name>
</author>
<published>2021-11-10T14:33:39+00:00</published>
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<id>18b9a987552492928aa1199d8cf498fe561c2f03</id>
<content type='text'>
We never tested the case where the width of the
numerator was less than the denominator.
This should fix any issue with this combination.</content>
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<pre>
We never tested the case where the width of the
numerator was less than the denominator.
This should fix any issue with this combination.</pre>
</div>
</content>
</entry>
<entry>
<title>typo: correct Error Info (#2398)</title>
<updated>2021-10-28T13:33:16+00:00</updated>
<author>
<name>SingularityKChen</name>
</author>
<published>2021-10-28T13:33:16+00:00</published>
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<id>e298b01d3086e78c187cb1c3611a206216499031</id>
<content type='text'>
+ correct the Error Info of "At least one dedupable annotation..."</content>
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<pre>
+ correct the Error Info of "At least one dedupable annotation..."</pre>
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</content>
</entry>
<entry>
<title>Add RTLIL Backend. (#2331)</title>
<updated>2021-09-29T03:18:48+00:00</updated>
<author>
<name>Nicolas Machado</name>
</author>
<published>2021-09-29T03:18:48+00:00</published>
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<id>e70ee5367c864e55ff16637430b712666b7dbd2b</id>
<content type='text'>
* Added RTLIL Backend.

* Add test for Rtlil Backend, fix per-module file emission, scalafmt, and apply bugfixes for inconsistencies found during testing.

* Fix build on scala 2.13

* Add additional equivalence test, make some bugfixes and perf opts to the emitter.

* Final changes as requested by Kevin, code cleanup, add support for formal cells.</content>
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<pre>
* Added RTLIL Backend.

* Add test for Rtlil Backend, fix per-module file emission, scalafmt, and apply bugfixes for inconsistencies found during testing.

* Fix build on scala 2.13

* Add additional equivalence test, make some bugfixes and perf opts to the emitter.

* Final changes as requested by Kevin, code cleanup, add support for formal cells.</pre>
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</content>
</entry>
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