sfcX/src/main/scala/firrtl/backends/experimental/rtlil, branch master Scala FIRRTL Compiler for chiselX Remove some warnings (#2448) 2021-12-22T02:47:18+00:00 Jack Koenig 2021-12-22T02:47:18+00:00 4f3d1003811aa38d10e32b347c8607414d9be034 * Fix unreachable code warning by changing match order Simulation Statements did not previously extend IsDeclaration, but now they do so their match blocks need to be above IsDeclaration. * Handle MemoryNoInit case in RtlilEmitter * Remove use of deprecated logToFile * Fix uses of LegalizeClocksTransform Replaced all uses of LegalizeClocksTransform with LegalizeClocksAndAsyncResetsTransform. * Remove use of CircuitForm in ZeroWidth 
* Fix unreachable code warning by changing match order

Simulation Statements did not previously extend IsDeclaration, but now
they do so their match blocks need to be above IsDeclaration.

* Handle MemoryNoInit case in RtlilEmitter

* Remove use of deprecated logToFile

* Fix uses of LegalizeClocksTransform

Replaced all uses of LegalizeClocksTransform with
LegalizeClocksAndAsyncResetsTransform.

* Remove use of CircuitForm in ZeroWidth
 Disable random init (#2396) 2021-11-19T19:17:37+00:00 Jiuyang Liu 2021-11-19T19:17:37+00:00 b027eb466b033a0a9d229f19feb931ddb292a9fa * Add option to disable random mem/reg init Co-authored-by: Jiuyang Liu <liu@jiuyang.me> * fix for code review. Co-authored-by: SharzyL <me@sharzy.in> 
* Add option to disable random mem/reg init

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

* fix for code review.

Co-authored-by: SharzyL <me@sharzy.in>
 typo: correct Error Info (#2398) 2021-10-28T13:33:16+00:00 SingularityKChen 2021-10-28T13:33:16+00:00 e298b01d3086e78c187cb1c3611a206216499031 + correct the Error Info of "At least one dedupable annotation..." 
+ correct the Error Info of "At least one dedupable annotation..."
 Add RTLIL Backend. (#2331) 2021-09-29T03:18:48+00:00 Nicolas Machado 2021-09-29T03:18:48+00:00 e70ee5367c864e55ff16637430b712666b7dbd2b * Added RTLIL Backend. * Add test for Rtlil Backend, fix per-module file emission, scalafmt, and apply bugfixes for inconsistencies found during testing. * Fix build on scala 2.13 * Add additional equivalence test, make some bugfixes and perf opts to the emitter. * Final changes as requested by Kevin, code cleanup, add support for formal cells. 
* Added RTLIL Backend.

* Add test for Rtlil Backend, fix per-module file emission, scalafmt, and apply bugfixes for inconsistencies found during testing.

* Fix build on scala 2.13

* Add additional equivalence test, make some bugfixes and perf opts to the emitter.

* Final changes as requested by Kevin, code cleanup, add support for formal cells.