This removes the FIRRTL specification as this now lives in its own
repository:

    https://github.com/chipsalliance/firrtl-spec

All git history (excluding binary updates to spec.pdf) have been
migrated to the new repository.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

- Convert FIRRTL spec to Markdown file.
- Add PDF generation via pandoc.
- Remove old LaTeX specification.

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Add defname, parameter to extmodule spec, NFC

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

8abf3085e3efb2b6dd3e123f13577b367d3f2695 reordered the fields, but it
unintentionally placed a closing brace before the actual end of the
write port type. This moves the brace to the end of the port.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Correct incorrect type specified for memories in the FIRRTL
specification.  This is important because the memory type determines
what is a legal bundle to try to connect to a memory port.

I based this off of FIRRTL accepting the following circuit:

    circuit MemOrder:
      module MemOrder:
        input r: {addr : UInt<3>, en : UInt<1>, clk : Clock, flip data : UInt<1>}
        input w: {addr : UInt<3>, en : UInt<1>, clk : Clock, data : UInt<1>, mask : UInt<1>}
        input rw: {addr : UInt<3>, en : UInt<1>, clk : Clock, flip rdata : UInt<1>, wmode : UInt<1>, wdata : UInt<1>, wmask : UInt<1>}

        mem memory:
          data-type => UInt<1>
          depth => 8
          reader => r
          writer => w
          readwriter => rw
          read-latency => 1
          write-latency => 1
          read-under-write => undefined

        memory.r <= r
        memory.w <= w
        memory.rw <= rw

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Change the FIRRTL spec to disallow a zero-width multiplexer select.
Clarify that the select line can be either one-bit or zero-bit, but will
infer to one-bit.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Change the FIRRTL specification document to allow for 0-bit mux selects.
The existing ZeroWidths pass will promote these to a 1-bit, 0-valued
select signal (which effectively means that the mux can be optimized
away to just the false path).

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Fixes #2206

* firrtl: add optional statement labels for stop, printf, assert, assume and cover

* test: parsing of statement labels

* ir: ensure that name is properly retained

* SymbolTable: add support for labled statements

* test: parsing statement labels

* test: lower types name collisions with named statements

* ignore empty names

* Inline: deal with named and unnamed statements

* RemoveWires: treat stop, printf and verification statements as "others"

* test: fix InlineInstance tests

* DeadCodeEliminations: statements are now als declarations

* CheckHighForm: ensure that statement names are not used as references

* CheckSpec: throw error if statement name collides

* add pass to automatically add missing statement names

* check: make sure that two statements cannot have the same name

* stmtLabel -> stmtName

* scalafmt

* add statement names to spec

* spec: meta data -> metadata

* EnsureStatementNames: explain naming algorithm

* remove returns

* better namespace use

* ir: add CanBeReferenced trait

* ir: add newline as jack requested