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<title>sfcX/regress, branch master</title>
<subtitle>Scala FIRRTL Compiler for chiselX</subtitle>
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<title>Change to Apache 2.0 License (#1901)</title>
<updated>2020-09-17T01:52:16+00:00</updated>
<author>
<name>Chick Markley</name>
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<published>2020-09-17T01:52:16+00:00</published>
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<entry>
<title>Incorporate new AddNot formal regression test</title>
<updated>2020-03-04T20:00:19+00:00</updated>
<author>
<name>Albert Magyar</name>
</author>
<published>2020-03-04T07:28:12+00:00</published>
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* Feedback from @jackkoening
* Merge into same stage as Ops to avoid Travis delays
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* Feedback from @jackkoening
* Merge into same stage as Ops to avoid Travis delays
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</entry>
<entry>
<title>Add Ops equiv check to stress degenerate binary op ConstProp</title>
<updated>2020-02-13T17:25:53+00:00</updated>
<author>
<name>Albert Magyar</name>
</author>
<published>2020-02-13T06:21:44+00:00</published>
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* Send in the Yosys
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* Send in the Yosys
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<entry>
<title>Faster reg constprop (#1067)</title>
<updated>2019-03-30T00:09:57+00:00</updated>
<author>
<name>Albert Magyar</name>
</author>
<published>2019-03-30T00:09:57+00:00</published>
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* Improve memoization for register const prop

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* Improve memoization for register const prop

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<entry>
<title>Change primop arg type (#587)</title>
<updated>2018-02-21T22:30:00+00:00</updated>
<author>
<name>Adam Izraelevitz</name>
</author>
<published>2018-02-21T22:30:00+00:00</published>
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* Changed primops to not accept mixed-type args

* Changed return type of sub of two uints to uint

* Added negative tests

* Removed rocket.fir. Manually changed RocketCore to not mix mul arg types. Added integration tests

* Clarified test description and remove println

* Fixed use of throwInternalError
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* Changed primops to not accept mixed-type args

* Changed return type of sub of two uints to uint

* Added negative tests

* Removed rocket.fir. Manually changed RocketCore to not mix mul arg types. Added integration tests

* Clarified test description and remove println

* Fixed use of throwInternalError
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</entry>
<entry>
<title>Refactor formal equivalence CI test</title>
<updated>2017-12-12T23:34:43+00:00</updated>
<author>
<name>Jack Koenig</name>
</author>
<published>2017-12-12T23:33:00+00:00</published>
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Make the check script allow different designs
Add FPU, ICache, and RocketCore to regress and use instead of Rob for CI
equivalence check
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Make the check script allow different designs
Add FPU, ICache, and RocketCore to regress and use instead of Rob for CI
equivalence check
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</entry>
<entry>
<title>Use newer rocket regression spec without comb loop</title>
<updated>2017-03-15T23:14:39+00:00</updated>
<author>
<name>Albert Magyar</name>
</author>
<published>2017-03-15T23:10:06+00:00</published>
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<entry>
<title>Added Rob.fir for regression testing (#258)</title>
<updated>2016-09-14T22:02:21+00:00</updated>
<author>
<name>Donggyu</name>
</author>
<published>2016-09-14T22:02:21+00:00</published>
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<entry>
<title>Remove brittle rocket comparison to expected verilog test.</title>
<updated>2016-02-26T00:09:12+00:00</updated>
<author>
<name>jackkoenig</name>
</author>
<published>2016-02-26T00:09:12+00:00</published>
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<entry>
<title>Make rocket-golden.v match output of #75</title>
<updated>2016-02-25T06:40:28+00:00</updated>
<author>
<name>jackkoenig</name>
</author>
<published>2016-02-25T06:37:20+00:00</published>
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