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open import Pervasives
open import Pervasives_extra
open import Sail_impl_base
open import Sail_values
open import Prompt
val MEMr : (vector bitU * integer) -> M (vector bitU)
val MEMr_reserve : (vector bitU * integer) -> M (vector bitU)
val MEMr_tag : (vector bitU * integer) -> M (vector bitU)
val MEMr_tag_reserve : (vector bitU * integer) -> M (vector bitU)
let MEMr (addr,size) = read_mem false Read_plain addr size
let MEMr_reserve (addr,size) = read_mem false Read_reserve addr size
let MEMr_tag (addr,size) = read_mem false Read_plain addr size
let MEMr_tag_reserve (addr,size) = read_mem false Read_reserve addr size
val MEMea : (vector bitU * integer) -> M unit
val MEMea_conditional : (vector bitU * integer) -> M unit
val MEMea_tag : (vector bitU * integer) -> M unit
val MEMea_tag_conditional : (vector bitU * integer) -> M unit
let MEMea (addr,size) = write_mem_ea Write_plain addr size
let MEMea_conditional (addr,size) = write_mem_ea Write_conditional addr size
let MEMea_tag (addr,size) = write_mem_ea Write_plain addr size
let MEMea_tag_conditional (addr,size) = write_mem_ea Write_conditional addr size
val MEMval : (vector bitU * integer * vector bitU) -> M unit
val MEMval_conditional : (vector bitU * integer * vector bitU) -> M bool
val MEMval_tag : (vector bitU * integer * vector bitU) -> M unit
val MEMval_tag_conditional : (vector bitU * integer * vector bitU) -> M bool
let MEMval (_,_,v) = write_mem_val v >>= fun _ -> return ()
let MEMval_conditional (_,_,v) = write_mem_val v >>= fun b -> return (if b then true else false)
let MEMval_tag (_,_,v) = write_mem_val v >>= fun _ -> return ()
let MEMval_tag_conditional (_,_,v) = write_mem_val v >>= fun b -> return (if b then true else false)
(* TODO *)
val TAGw : (vector bitU * vector bitU) -> M unit
let TAGw (addr, tag) = failwith "TAGw not implemented"
val MEM_sync : unit -> M unit
let MEM_sync () = barrier Barrier_Isync
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