1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
|
open import Pervasives
open import Pervasives_extra
open import Sail_impl_base
open import Sail_values
open import Prompt
val MEMr : forall 'a 'b. Bitvector 'a, Bitvector 'b => ('a * integer) -> M 'b
val MEMr_reserve : forall 'a 'b. Bitvector 'a, Bitvector 'b => ('a * integer) -> M 'b
val MEMr_tag : forall 'a 'b. Bitvector 'a, Bitvector 'b => ('a * integer) -> M 'b
val MEMr_tag_reserve : forall 'a 'b. Bitvector 'a, Bitvector 'b => ('a * integer) -> M 'b
let MEMr (addr,size) = read_mem false Read_plain addr size
let MEMr_reserve (addr,size) = read_mem false Read_reserve addr size
let MEMr_tag (addr,size) = read_mem false Read_plain addr size
let MEMr_tag_reserve (addr,size) = read_mem false Read_reserve addr size
val MEMea : forall 'a. Bitvector 'a => ('a * integer) -> M unit
val MEMea_conditional : forall 'a. Bitvector 'a => ('a * integer) -> M unit
val MEMea_tag : forall 'a. Bitvector 'a => ('a * integer) -> M unit
val MEMea_tag_conditional : forall 'a. Bitvector 'a => ('a * integer) -> M unit
let MEMea (addr,size) = write_mem_ea Write_plain addr size
let MEMea_conditional (addr,size) = write_mem_ea Write_conditional addr size
let MEMea_tag (addr,size) = write_mem_ea Write_plain addr size
let MEMea_tag_conditional (addr,size) = write_mem_ea Write_conditional addr size
val MEMval : forall 'a 'b. Bitvector 'a, Bitvector 'b => ('a * integer * 'b) -> M unit
val MEMval_conditional : forall 'a 'b. Bitvector 'a, Bitvector 'b => ('a * integer * 'b) -> M bool
val MEMval_tag : forall 'a 'b. Bitvector 'a, Bitvector 'b => ('a * integer * 'b) -> M unit
val MEMval_tag_conditional : forall 'a 'b. Bitvector 'a, Bitvector 'b => ('a * integer * 'b) -> M bool
let MEMval (_,_,v) = write_mem_val v >>= fun _ -> return ()
let MEMval_conditional (_,_,v) = write_mem_val v >>= fun b -> return (if b then true else false)
let MEMval_tag (_,_,v) = write_mem_val v >>= fun _ -> return ()
let MEMval_tag_conditional (_,_,v) = write_mem_val v >>= fun b -> return (if b then true else false)
(* TODO *)
val TAGw : (vector bitU * vector bitU) -> M unit
let TAGw (addr, tag) = failwith "TAGw not implemented"
val MEM_sync : unit -> M unit
let MEM_sync () = barrier Barrier_Isync
|
