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open import Pervasives
open import Pervasives_extra
open import Sail_instr_kinds
open import Sail_values
open import Sail_operators
open import Prompt_monad
open import Prompt
val MEMr : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e
val MEMr_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e
val MEMr_tag : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e
val MEMr_tag_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e
let MEMr addr size = read_mem Read_plain addr size
let MEMr_reserve addr size = read_mem Read_reserve addr size
let MEMr_tag addr size =
read_mem Read_plain addr size >>= fun v ->
read_tag addr >>= fun t ->
return (bool_of_bitU t, v)
let MEMr_tag_reserve addr size =
read_mem Read_plain addr size >>= fun v ->
read_tag addr >>= fun t ->
return (bool_of_bitU t, v)
val MEMea : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e
val MEMea_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e
val MEMea_tag : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e
val MEMea_tag_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e
let MEMea addr size = write_mem_ea Write_plain addr size
let MEMea_conditional addr size = write_mem_ea Write_conditional addr size
let MEMea_tag addr size = write_mem_ea Write_plain addr size
let MEMea_tag_conditional addr size = write_mem_ea Write_conditional addr size
val MEMval : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> 'b -> monad 'regval unit 'e
val MEMval_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> 'b -> monad 'regval bool 'e
val MEMval_tag : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval unit 'e
val MEMval_tag_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval bool 'e
let MEMval _ size v = write_mem_val v >>= fun _ -> return ()
let MEMval_conditional _ size v = write_mem_val v >>= fun b -> return (if b then true else false)
let MEMval_tag _ size t v = write_mem_val v >>= fun _ -> write_tag_val (bitU_of_bool t) >>= fun _ -> return ()
let MEMval_tag_conditional _ size t v = write_mem_val v >>= fun b -> write_tag_val (bitU_of_bool t) >>= fun _ -> return (if b then true else false)
val MEM_sync : forall 'regval 'e. unit -> monad 'regval unit 'e
let MEM_sync () = barrier Barrier_MIPS_SYNC
(* Some wrappers copied from aarch64_extras *)
(* TODO: Harmonise into a common library *)
let get_slice_int_bl len n lo =
(* TODO: Is this the intended behaviour? *)
let hi = lo + len - 1 in
let bits = bits_of_int (hi + 1) n in
get_bits false bits hi lo
val get_slice_int : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a
let get_slice_int len n lo = of_bits (get_slice_int_bl len n lo)
let write_ram _ size _ addr data =
MEMea addr size >>
MEMval addr size data
let read_ram _ size _ addr = MEMr addr size
let sign_extend bits len = exts_bv len bits
let zero_extend bits len = extz_bv len bits
let shift_bits_left v n = shiftl_bv v (unsigned n)
let shift_bits_right v n = shiftr_bv v (unsigned n)
let shift_bits_right_arith v n = arith_shiftr_bv v (unsigned n)
(* TODO: These could be monadic instead of hardcoded *)
let internal_pick vs = head vs
let undefined_string () = ""
let undefined_unit () = ()
let undefined_int () = (0:ii)
let undefined_bool () = false
val undefined_vector : forall 'a. integer -> 'a -> list 'a
let undefined_vector len u = repeat [u] len
val undefined_bitvector : forall 'a. Bitvector 'a => integer -> 'a
let undefined_bitvector len = of_bits (repeat [B0] len)
let undefined_bits len = undefined_bitvector len
let undefined_bit () = B0
let undefined_real () = realFromFrac 0 1
let undefined_range i j = i
let undefined_atom i = i
let undefined_nat () = (0:ii)
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