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| `MIPSThreadStart -> "syscall 0xfffff" (* thread start *)
| `MIPSStopFetching -> "STOP" (* TODO *)
| `MIPSRType (op, rd,rs,rt) ->
sprintf "%s %s,%s,%s" (pp_rtype_op op) (pp_reg rd) (pp_reg rs) (pp_reg rt)
| `MIPSIType (op,rd,rs,imm) ->
sprintf "%s %s,%s,%d" (pp_itype_op op) (pp_reg rd) (pp_reg rs) imm
| `MIPSShiftI (op, rs, rt, imm) ->
sprintf "%s %s,%s,%d" (pp_shifti_op op) (pp_reg rs) (pp_reg rt) imm
| `MIPSShiftV (op, rd,rs,rt) ->
sprintf "%s %s,%s,%s" (pp_shiftv_op op) (pp_reg rd) (pp_reg rs) (pp_reg rt)
| `MIPSMulDiv (op, rs, rt) ->
sprintf "%s %s,%s" (pp_muldiv_op op) (pp_reg rs) (pp_reg rt)
| `MIPSMFHiLo (op, rs) ->
sprintf "%s %s" (pp_mfhilo_op op) (pp_reg rs)
| `MIPSLUI (rt, imm) ->
sprintf "lui %s,%d" (pp_reg rt) imm
| `MIPSLoad (width, signed, linked, base, rt, offset) ->
sprintf "%s %s,%d(%s)" (pp_load_op width signed linked) (pp_reg rt) offset (pp_reg base)
| `MIPSStore (width, conditional, base, rt, offset) ->
sprintf "%s %s,%d(%s)" (pp_store_op width conditional) (pp_reg rt) offset (pp_reg base)
| `MIPSLSLR (store, double, left, base, rt, offset) ->
sprintf "%s %s,%d(%s)" (pp_lslr_op store double left) (pp_reg rt) offset (pp_reg base)
| `MIPSSYNC -> "sync"
| `MIPSBEQ (rs, rt, offset, ne, likely) ->
sprintf "%s %s,%s,.%+d" (pp_beq_op ne likely) (pp_reg rs) (pp_reg rt) offset
| `MIPSBCMPZ (rs, offset, cmp, link, likely) ->
sprintf "%s,%s,.%+d" (pp_bcmpz_op cmp link likely) (pp_reg rs) offset
| `MIPSJ (offset) ->
sprintf "j %d" offset
| `MIPSJAL (offset) ->
sprintf "jal %d" offset
| `MIPSJR(rd) ->
sprintf "jr %s" (pp_reg rd)
| `MIPSJALR(rd, rs) ->
sprintf "jalr %s,%s" (pp_reg rd) (pp_reg rs)
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