open import Pervasives
open import Pervasives_extra
open import Sail_impl_base
open import Sail_values
open import State

val MEMr             : (vector bitU * integer) -> M (vector bitU)
val MEMr_reserve     : (vector bitU * integer) -> M (vector bitU)

let MEMr (addr,size)             = read_mem false Read_plain addr size
let MEMr_reserve (addr,size)     = read_mem false Read_reserve addr size

val MEMea                 : (vector bitU * integer) -> M unit
val MEMea_conditional     : (vector bitU * integer) -> M unit

let MEMea (addr,size)                 = write_mem_ea Write_plain addr size
let MEMea_conditional (addr,size)     = write_mem_ea Write_conditional addr size


val MEMval                 : (vector bitU * integer * vector bitU) -> M unit
val MEMval_conditional     : (vector bitU * integer * vector bitU) -> M bitU

let MEMval (_,_,v)                   = write_mem_val v >>= fun _ -> return ()
let MEMval_conditional (_,_,v)       = write_mem_val v >>= fun b -> return (if b then B1 else B0)

val MEM_fence_rw_rw : unit -> M unit
val MEM_fence_r_rw  : unit -> M unit
val MEM_fence_rw_w  : unit -> M unit

let MEM_fence_rw_rw () = barrier Barrier_RISCV_rw_rw
let MEM_fence_r_rw  () = barrier Barrier_RISCV_r_rw
let MEM_fence_rw_w  () = barrier Barrier_RISCV_rw_w

let duplicate (bit,len) =
  let bits = repeat [bit] len in
  let start = len - 1 in
  Vector bits start false