From 4b6732fdddebc07f072e012a52f7d9541e4d657c Mon Sep 17 00:00:00 2001
From: Alasdair Armstrong
Date: Wed, 13 Jun 2018 21:26:35 +0100
Subject: Tracing instrumentation for C backend

---
 test/c/read_write_ram.expect |  1 +
 test/c/read_write_ram.sail   | 29 +++++++++++++++++++++++++++++
 2 files changed, 30 insertions(+)
 create mode 100644 test/c/read_write_ram.expect
 create mode 100644 test/c/read_write_ram.sail

(limited to 'test')

diff --git a/test/c/read_write_ram.expect b/test/c/read_write_ram.expect
new file mode 100644
index 00000000..9766475a
--- /dev/null
+++ b/test/c/read_write_ram.expect
@@ -0,0 +1 @@
+ok
diff --git a/test/c/read_write_ram.sail b/test/c/read_write_ram.sail
new file mode 100644
index 00000000..751d15b5
--- /dev/null
+++ b/test/c/read_write_ram.sail
@@ -0,0 +1,29 @@
+default Order dec
+
+$include <flow.sail>
+$include <arith.sail>
+$include <vector_dec.sail>
+$include <string.sail>
+$include <exception_basic.sail>
+
+val write_ram = "write_ram" : forall 'n 'm.
+  (atom('m), atom('n), bits('m), bits('m), bits(8 * 'n)) -> unit effect {wmem}
+
+val read_ram = "read_ram" : forall 'n 'm.
+  (atom('m), atom('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem}
+
+val main : unit -> unit effect {escape, wmem, rmem}
+
+function main() = {
+  write_ram(64, 4, 64^0x0, 64^0x8000_0000, 0x01020304);
+  let data = read_ram(64, 4, 64^0x0, 64^0x8000_0000);
+  assert(data == 0x01020304);
+  let data = read_ram(64, 3, 64^0x0, 64^0x8000_0001);
+  assert(data == 0x010203);
+  let data = read_ram(64, 3, 64^0x0, 64^0x8000_0000);
+  assert(data == 0x020304);
+  write_ram(64, 4, 64^0x0, 64^0x7fff_ffff, 0xA1B2C3D4);
+  let data = read_ram(64, 3, 64^0x0, 64^0x8000_0000);
+  assert(data == 0xA1B2C3);
+  print_endline("ok");
+}
\ No newline at end of file
-- 
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