From 65228f7ea61535fa8961dcb8ce8f030e7359c479 Mon Sep 17 00:00:00 2001
From: Thomas Bauereiss
Date: Mon, 24 Feb 2020 19:34:02 +0000
Subject: Allow overloading of subrange builtins for non-bitvectors

---
 test/typecheck/pass/reg_32_64/v3.expect | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

(limited to 'test/typecheck')

diff --git a/test/typecheck/pass/reg_32_64/v3.expect b/test/typecheck/pass/reg_32_64/v3.expect
index cea45127..6de59040 100644
--- a/test/typecheck/pass/reg_32_64/v3.expect
+++ b/test/typecheck/pass/reg_32_64/v3.expect
@@ -1,10 +1,12 @@
 Type error:
-[reg_32_64/v3.sail]:29:15-21
+[reg_32_64/v3.sail]:29:2-27
 29 |  reg_deref(R)['d - 1 .. 0]
-   |               ^----^
-   | No overloading for (operator -), tried:
-   | * sub_atom
-   |    Cannot re-write sizeof('d)
-   | * sub_int
-   |    Cannot re-write sizeof('d)
+   |  ^-----------------------^
+   | No overloading for vector_subrange, tried:
+   | * subrange_bits
+   |    No overloading for (operator -), tried:
+   |    * sub_atom
+   |       Cannot re-write sizeof('d)
+   |    * sub_int
+   |       Cannot re-write sizeof('d)
    | 
-- 
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