From 868ba4b5cc41ee902032154864df560edc22e0d0 Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Thu, 1 Mar 2018 16:33:14 +0000
Subject: Add support for read_tag and write_tag in sail_lib.ml. and support
 for intialising and dumping CHERI state. Somewhat working cheri sail2 model.

---
 src/sail_lib.ml | 10 ++++++++++
 1 file changed, 10 insertions(+)

(limited to 'src')

diff --git a/src/sail_lib.ml b/src/sail_lib.ml
index 44dd4ac5..4e78507f 100644
--- a/src/sail_lib.ml
+++ b/src/sail_lib.ml
@@ -433,6 +433,16 @@ let read_ram (addr_size, data_size, hex_ram, addr) =
   in
   read_byte data_size
 
+let tag_ram : bool RAM.t = RAM.create 256
+
+let write_tag (addr, tag) =
+  let addri = uint addr in
+  RAM.add tag_ram addri tag
+
+let read_tag addr =
+  let addri = uint addr in
+  try RAM.find tag_ram addri with Not_found -> false
+
 let rec reverse_endianness bits =
   if List.length bits <= 8 then bits else
   reverse_endianness (drop 8 bits) @ (take 8 bits)
-- 
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