From 8007d3f8c0ffe2b4d98db63ba390630acbc5e717 Mon Sep 17 00:00:00 2001 From: Robert Norton Date: Wed, 18 May 2016 16:00:33 +0100 Subject: Implement 8-entry software-managed TLB. --- src/lem_interp/run_with_elf.ml | 29 +++++++++++++++++++++++++++++ src/lem_interp/run_with_elf_cheri.ml | 29 +++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+) (limited to 'src') diff --git a/src/lem_interp/run_with_elf.ml b/src/lem_interp/run_with_elf.ml index 7872a5b5..313babe4 100644 --- a/src/lem_interp/run_with_elf.ml +++ b/src/lem_interp/run_with_elf.ml @@ -500,6 +500,24 @@ let mips_register_data_all = [ ("CP0Compare", (D_decreasing, 32, 31)); ("CP0HWREna", (D_decreasing, 32, 31)); ("CP0UserLocal", (D_decreasing, 64, 63)); + ("TLBProbe" ,(D_decreasing, 1, 0)); + ("TLBIndex" ,(D_decreasing, 3, 2)); + ("TLBRandom" ,(D_decreasing, 3, 2)); + ("TLBEntryLo0",(D_decreasing, 30, 29)); + ("TLBEntryLo1",(D_decreasing, 30, 29)); + ("TLBContext" ,(D_decreasing, 64, 63)); + ("TLBPageMask",(D_decreasing, 16, 15)); + ("TLBWired" ,(D_decreasing, 3, 2)); + ("TLBEntryHi" ,(D_decreasing, 64, 63)); + ("TLBXContext",(D_decreasing, 64, 63)); + ("TLBEntry00" ,(D_decreasing, 113, 112)); + ("TLBEntry01" ,(D_decreasing, 113, 112)); + ("TLBEntry02" ,(D_decreasing, 113, 112)); + ("TLBEntry03" ,(D_decreasing, 113, 112)); + ("TLBEntry04" ,(D_decreasing, 113, 112)); + ("TLBEntry05" ,(D_decreasing, 113, 112)); + ("TLBEntry06" ,(D_decreasing, 113, 112)); + ("TLBEntry07" ,(D_decreasing, 113, 112)); ] let initial_stack_and_reg_data_of_MIPS_elf_file e_entry all_data_memory = @@ -880,6 +898,17 @@ let get_addr_trans_regs _ = (Interp_interface.Reg0("CP0Count", 31, 32, Interp_interface.D_decreasing), Reg.find "CP0Count" !reg); (Interp_interface.Reg0("CP0Compare", 31, 32, Interp_interface.D_decreasing), Reg.find "CP0Compare" !reg); (Interp_interface.Reg0("inBranchDelay", 0, 1, Interp_interface.D_decreasing), Reg.find "inBranchDelay" !reg); + (Interp_interface.Reg0("TLBRandom", 2, 3, Interp_interface.D_decreasing), Reg.find "TLBRandom" !reg); + (Interp_interface.Reg0("TLBWired", 2, 3, Interp_interface.D_decreasing), Reg.find "TLBWired" !reg); + (Interp_interface.Reg0("TLBEntryHi", 63, 64, Interp_interface.D_decreasing), Reg.find "TLBEntryHi" !reg); + (Interp_interface.Reg0("TLBEntry00", 112, 113, Interp_interface.D_decreasing), Reg.find "TLBEntry00" !reg); + (Interp_interface.Reg0("TLBEntry01", 112, 113, Interp_interface.D_decreasing), Reg.find "TLBEntry01" !reg); + (Interp_interface.Reg0("TLBEntry02", 112, 113, Interp_interface.D_decreasing), Reg.find "TLBEntry02" !reg); + (Interp_interface.Reg0("TLBEntry03", 112, 113, Interp_interface.D_decreasing), Reg.find "TLBEntry03" !reg); + (Interp_interface.Reg0("TLBEntry04", 112, 113, Interp_interface.D_decreasing), Reg.find "TLBEntry04" !reg); + (Interp_interface.Reg0("TLBEntry05", 112, 113, Interp_interface.D_decreasing), Reg.find "TLBEntry05" !reg); + (Interp_interface.Reg0("TLBEntry06", 112, 113, Interp_interface.D_decreasing), Reg.find "TLBEntry06" !reg); + (Interp_interface.Reg0("TLBEntry07", 112, 113, Interp_interface.D_decreasing), Reg.find "TLBEntry07" !reg); ]) let get_opcode pc_a = diff --git a/src/lem_interp/run_with_elf_cheri.ml b/src/lem_interp/run_with_elf_cheri.ml index 633dda72..dd7a5093 100644 --- a/src/lem_interp/run_with_elf_cheri.ml +++ b/src/lem_interp/run_with_elf_cheri.ml @@ -500,6 +500,24 @@ let mips_register_data_all = [ ("CP0Compare", (D_decreasing, 32, 31)); ("CP0HWREna", (D_decreasing, 32, 31)); ("CP0UserLocal", (D_decreasing, 64, 63)); + ("TLBProbe" ,(D_decreasing, 1, 0)); + ("TLBIndex" ,(D_decreasing, 3, 2)); + ("TLBRandom" ,(D_decreasing, 3, 2)); + ("TLBEntryLo0",(D_decreasing, 30, 29)); + ("TLBEntryLo1",(D_decreasing, 30, 29)); + ("TLBContext" ,(D_decreasing, 64, 63)); + ("TLBPageMask",(D_decreasing, 16, 15)); + ("TLBWired" ,(D_decreasing, 3, 2)); + ("TLBEntryHi" ,(D_decreasing, 64, 63)); + ("TLBXContext",(D_decreasing, 64, 63)); + ("TLBEntry00" ,(D_decreasing, 113, 112)); + ("TLBEntry01" ,(D_decreasing, 113, 112)); + ("TLBEntry02" ,(D_decreasing, 113, 112)); + ("TLBEntry03" ,(D_decreasing, 113, 112)); + ("TLBEntry04" ,(D_decreasing, 113, 112)); + ("TLBEntry05" ,(D_decreasing, 113, 112)); + ("TLBEntry06" ,(D_decreasing, 113, 112)); + ("TLBEntry07" ,(D_decreasing, 113, 112)); ] let cheri_register_data_all = mips_register_data_all @ [ @@ -968,6 +986,17 @@ let get_addr_trans_regs _ = (Interp_interface.Reg0("CP0Count", 31, 32, Interp_interface.D_decreasing), Reg.find "CP0Count" !reg); (Interp_interface.Reg0("CP0Compare", 31, 32, Interp_interface.D_decreasing), Reg.find "CP0Compare" !reg); (Interp_interface.Reg0("inBranchDelay", 0, 1, Interp_interface.D_decreasing), Reg.find "inBranchDelay" !reg); + (Interp_interface.Reg0("TLBRandom", 2, 3, Interp_interface.D_decreasing), Reg.find "TLBRandom" !reg); + (Interp_interface.Reg0("TLBWired", 2, 3, Interp_interface.D_decreasing), Reg.find "TLBWired" !reg); + (Interp_interface.Reg0("TLBEntryHi", 63, 64, Interp_interface.D_decreasing), Reg.find "TLBEntryHi" !reg); + (Interp_interface.Reg0("TLBEntry00", 112, 113, Interp_interface.D_decreasing), Reg.find "TLBEntry00" !reg); + (Interp_interface.Reg0("TLBEntry01", 112, 113, Interp_interface.D_decreasing), Reg.find "TLBEntry01" !reg); + (Interp_interface.Reg0("TLBEntry02", 112, 113, Interp_interface.D_decreasing), Reg.find "TLBEntry02" !reg); + (Interp_interface.Reg0("TLBEntry03", 112, 113, Interp_interface.D_decreasing), Reg.find "TLBEntry03" !reg); + (Interp_interface.Reg0("TLBEntry04", 112, 113, Interp_interface.D_decreasing), Reg.find "TLBEntry04" !reg); + (Interp_interface.Reg0("TLBEntry05", 112, 113, Interp_interface.D_decreasing), Reg.find "TLBEntry05" !reg); + (Interp_interface.Reg0("TLBEntry06", 112, 113, Interp_interface.D_decreasing), Reg.find "TLBEntry06" !reg); + (Interp_interface.Reg0("TLBEntry07", 112, 113, Interp_interface.D_decreasing), Reg.find "TLBEntry07" !reg); ]) let get_opcode pc_a = -- cgit v1.2.3