From 2a89faec667fdf24b93360d3da5f14eab161983b Mon Sep 17 00:00:00 2001
From: Jon French
Date: Wed, 11 Jul 2018 18:13:15 +0100
Subject: RISC-V model fixes for RMEM

---
 src/sail_lib.ml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/sail_lib.ml b/src/sail_lib.ml
index 63260c17..16b1d3cc 100644
--- a/src/sail_lib.ml
+++ b/src/sail_lib.ml
@@ -457,7 +457,7 @@ let write_ram' (data_size, addr, data) =
   end
 
 let write_ram (addr_size, data_size, hex_ram, addr, data) =
-  write_ram' (data_size, uint addr, data)
+  write_ram' (data_size, uint addr, data); true
 
 let wram addr byte =
   let bytes = Bytes.make 1 (char_of_int byte) in
-- 
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