From 79ecf8b83b06a6bd1330e1f243826cbe951a9e7d Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Thu, 12 Jul 2018 15:54:11 +0100
Subject: update arm and mips models for new type of write_ram builtin. Also
 fix c and interpreter implementations of same.

---
 src/value.ml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/value.ml')

diff --git a/src/value.ml b/src/value.ml
index 1d2346af..dccb216e 100644
--- a/src/value.ml
+++ b/src/value.ml
@@ -406,8 +406,8 @@ let value_read_ram = function
 
 let value_write_ram = function
   | [v1; v2; v3; v4; v5] ->
-     Sail_lib.write_ram (coerce_int v1, coerce_int v2, coerce_bv v3, coerce_bv v4, coerce_bv v5);
-     V_unit
+     let b = Sail_lib.write_ram (coerce_int v1, coerce_int v2, coerce_bv v3, coerce_bv v4, coerce_bv v5) in
+     V_bool(b)
   | _ -> failwith "value write_ram"
 
 let value_load_raw = function
-- 
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